Dell 1440 Schematics REV SB 23MAR2009Sec

5

D D

4

3

2

1

Alba Discrete ATI M92-LP gDDR2 Schematics

uFCPGA Mobile Penryn

Intel Cantiga-PM + ICH9M

C C

2009-03-23

REV : SA

B B

DY : Nopop Component

GM : Pop when Cantiga is GM

PM : Pop when Cantiga is PM

G/P : BOM control if Cantiga is PM

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page

Cover Page

Cover Page

Alba Discrete

Alba Discrete

Alba Discrete

1

1 60Monday, March 23, 2009

1 60Monday, March 23, 2009

1 60Monday, March 23, 2009

SB

SB

SB

5

4

3

2

1

ALBA Discrete Block Diagram

CPU DC/DC

ISL6266A

INPUTS

Clock Generator

D D

PCB LAYER

L1: Top
L2: GND

SLG8SP513VTR

7

Intel Mobile CPU

Penryn

Socket P

8,9

L3: Signal
L4: Signal
L5: VCC
L6: Signal

VRAM(gDDR2)

32Mbx16x4 (512MB)

4

57,58

FSB
800/1066MHz

Project code : 91.4BK01.001
Part Number : 48.4BK13.0SA
PCB P/N : 09207
Revision : SA

L7: GND
L8: Bottom

CRT

C C

LCD

RGB CRT

42

LVDS(Dual Channel)

41

ATI M92-LP

53,54,55,56

PCIe x 16

DMIx4

CardReader

(7 in 1)SD/MMC
MS/MS Pro/xD

B B

(On Express Card board)

Digital Mic Array
(Option)

Internal Mic

47

44

MIC IN

Realtek
RTS5159

50

Azalia
CODEC

OP AMP

USB2.0

AZALIA

Intel

Cantiga-GM

AGTL+ CPU I/F

DDR Memory I/F

External Graphics

10,11,12,13,14,15

Intel

ICH9-M

USB 2.0/1.1 ports (12)

PCI Express ports (6)

High Definition Audio

SATA ports (4)

LPC I/F

ACPI 1.1

PCI/PCI BRIDGE

18,19,20,21

CONTROL-LINK

USB 2.0

DDRII 800 Channel A

DDR II 800 Channel B

PCIE

LPC Bus

PCIE x 1

DDRII
800

DDRII
800

PCIE x 1 & USB 2.0 x 1

10/100 LOM

RTL8103EL

USB 2.0 x 2

PCIE x 1

Slot 0

16

Slot 1

17

25

USB 2.0 x 1

USB 2.0 x 1

USB 2.0 x 1

Power SW

TPS2231RGP

New Card

(On Express Card board)

RJ45
CONN

Left Side:
USB x 2

Mini-Card

802.11a/b/g/n

CAMERA
(Option)

Bluetooth

Right Side:
USB x 1

43

47

45

51

50

42

46

+PWR_SRC

SYSTEM DC/DC

INPUTS

+PWR_SRC

SYSTEM DC/DC

INPUTS

+PWR_SRC

INPUTS

+1.8V_SUS

SYSTEM DC/DC

50

INPUTS

+PWR_SRC

SYSTEM DC/DC

INPUTS

+PWR_SRC

INPUTS

+DC_IN
+PBATT

INPUTS

+1.8V_SUS

TPS51117

TPS51125

LDO

L6935TR

TPS51117

TPS51117

CHARGER

MAX8731A

LDO

TPS51100

KBC

(On Express Card board)

HP OUT

IDT
92HD81

22

SATA

SATA

SPI

WINBOND

WPCE773L

26

LDO

L6935TR

INPUTS

A A

2CH SPEAKER

44

5

4

HDD

ODD

44 44

Flash ROM

2MB

3

Touch
PAD

47

Int.
KB

45

Thermal
& Fan

45 28,44

EMC2102

2

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

+1.8V_SUS

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

Block Diagram

Block Diagram

Alba Discrete

Alba Discrete

Alba Discrete

1

2 60Monday, March 23, 2009

2 60Monday, March 23, 2009

2 60Monday, March 23, 2009

34,35

OUTPUTS

+VCC_CORE

OUTPUTS

+1.05V_VCCP

OUTPUTS

+15V_ALW
+3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW

OUTPUTS

+1.5V_RUN

OUTPUTS

+1.8V_SUS

OUTPUTS

+VCC_GFX_CORE

OUTPUTS

+PWR_SRC

OUTPUTS

+V_DDR_MCH_REF
+0.9V_DDR_VTT

OUTPUTS

+1.1V_RUN

36

33

37

38

39

32

38

37

SB

SB

SB

5

D D

4

3

2

1

Adapter

SI4835BDY

Battery

32

+PWR_SRC TPS51117

ISL6266A

34,35 36 39

TPS51117

TPS51117

Charger

MAX8731A

+PBATT

32

+VCC_CORE

+1.05V_VCCP

+VCC_GFX_CORE

TPS51100

TPS51125

C C

+5V_ALW2

+15V_ALW

3D3V_AUX_S5

+3.3V_RTC_LDO

TPS2062AD

+5V_USB1

B B

+5V_ALW

AO4468

46 5130 30

+5V_RUN

33

TPS2062AD

+5V_USB2

AO3403

+3.3V_LAN

RTL8103EL

+DVDD12

25

+3.3V_ALW

TPS2231RGP

TPS2034DR

50

+LCDVDD

AO4468

+3.3V_RUN+3.3V_CARDAUX

41

TPS2231RGP

+3.3V_CARD

5025

38

38

+0.9V_DDR_VTT+V_DDR_MCH_REF

SI2301

+3.3V_DELAY

+1.8V_SUS

L6935TR

+1.1V_RUN

37

L6935TR

+1.5V_RUN

TPS2231RGP

37

50

+1.5V_CARD

30

Power Shape

Regulator LDO Switch

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Power Block Diagram

Power Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Power Block Diagram

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

1

3 59Monday, March 23, 2009

3 59Monday, March 23, 2009

3 59Monday, March 23, 2009

SB

SB

SB

A

ICH9M SMBus Block Diagram

B

C

D

E

KBC SMBus Block Diagram

+5V_RUN

‧

‧

‧

PBAT_SMBCLK1

PBAT_SMBDAT1

2N7002DW-1-GP

SRN10KJ-5-GP

+3.3V_RUN

‧

TouchPad Conn.

TPDATA

TPDATA

TPCLK

TPCLK

Battery Conn.

CLK_SMB

DAT_SMB

MAX8731

SCL

SDA

+3.3V_RUN

SMBus address:12

32

‧

SRN4K7J-8-GP

Thermal

THERM_SCL

‧

THERM_SDA

‧

SCL

SDA

45

SMBus address:16

31

SMBus address:7A

28

1 1

TPDATA

PSDAT1

PSCLK1

SCL1

SDA1

TPCLK

BAT_SCL

BAT_SDA

+3.3V_RTC_LDO

‧

SRN4K7J-8-GP

‧

‧

+3.3V_RTC_LDO

‧

‧

SRN100J-3-GP

+3.3V_RUN

‧

50

+3.3V_RUN

‧

‧

‧

‧

‧

‧

‧

SRN2K2J-1-GP

DIMM 1

ICH_SMBCLK

ICH_SMBDATA

SCL

SDA

SMBus Address:A0

DIMM 2

ICH_SMBCLK

ICH_SMBDATA

SCL

SDA

SMBus Address:A4

Clock
Generator

ICH_SMBCLK

ICH_SMBDATA

SCLK

SDATA

16

17

09

KBC

WPC773L

+3.3V_ALW

‧

SRN2K2J-1-GP

ICH9M

2 2

SMBCLK

SMBDATA

20

SMB_CLK

SMB_DATA

‧

‧

2N7002SPT

Express
Card

SMB_CLK

SMB_CLK

SMB_DATA

SMB_DATA

SMBus address:D2

‧

SMB_CLK

SMB_DATA

Minicard
WLAN

SMB_CLK

SMB_DATA

43

GPIO73/SCL2

GPIO74/SDA2

KBC_SCL1

KBC_SDA1

SRN4K7J-8-GP

‧

‧

3 3

26

+3.3V_RUN

‧

SRN2K2J-1-GP

M92CRT_DDCCLK

M92CRT_DDCDATA

54

LDDC_CLK

LDDC_DATA

+3.3V_DELAY

‧

C

‧

SRN2K2J-1-GP

‧

‧

‧

2N7002DW-1-GP

LCD Conn.

+3.3V_DELAY

‧

41

+5V_CRT_RUN

‧

D

‧

SRN2K2J-1-GP

‧

DDC_CLK_CON

DDC_DATA_CON

CRT CONN

42

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

SMBUS Block Diagram

SMBUS Block Diagram

SMBUS Block Diagram

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

E

SB

SB

4 59Monday, March 23, 2009

4 59Monday, March 23, 2009

4 59Monday, March 23, 2009

SB

DDC1CLK

DDC1DATA

VGA

DDC2CLK

4 4

A

B

DDC2DATA

A

B

C

D

E

Thermal Block Diagram

1 1

DP1

H_THERMDA

2 2

DN1

H_THERMDC

SC470P50V3JN-2GP

Thermal
EMC2102

DP2

VGA_THERMDA

SC470P50V3JN-2GP

DN2

VGA_THERMDC

THRMDA

THRMDC

DPLUS

DMINUS

CPU

8

GPU

54

Audio Block Diagram

SPKR_PORT_D_L+

SPKR_PORT_D_L-

SPKR_PORT_D_R-

SPKR_PORT_D_R+

HP1_PORT_B_L

HP1_PORT_B_R

Codec
92HD81

HP0_PORT_A_L

HP0_PORT_A_R

VREFOUT_A_OR_F

AUD_SPK_L1

AUD_SPK_L2

AUD_SPK_R2

AUD_SPK_R1

AUD_HP1_JACK_L

AUD_HP1_JACK_R

AUD_EXT_MIC_L

AUD_EXT_MIC_R

AUD_VREFOUT_B

0R3-0-U-GP

AUD_SPK_L1_R

AUD_SPK_L2_R

AUD_SPK_R2_R

AUD_SPK_R1_R

0R3-0-U-V-GP

SPEAKER

44

HP

OUT

50

MIC

IN

50

3 3

DP3

DN3

CPU_THERMDA

SC470P50V3JN-2GP

CPU_THERMDC

MMBT3904-3-GP

DMIC_CLK/GPIO1

DMIC0/GPIO2

HW T8 sensor

28

VREFOUT_C

4 4

A

B

C

PORT_C_L

PORT_C_R

22

AUD_DMIC_CLK

AUD_INT_MIC_L

AUD_INT_MIC_R

AUD_VREFOUT_C

33R2J-2-GP

AUD_DMIC_IN0

4K7R2J-2-GP

D

SC1U10V3KX-3GP

AUD_DMIC_CLK_G_R

33R2J-2-GP

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

AUD_DMIC_IN0_R

INT_MIC_L_R

Thermal/Audio Block Diagram

Thermal/Audio Block Diagram

Thermal/Audio Block Diagram

Digital
MIC
Array

Internal
MIC

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

5 59Monday, March 23, 2009

5 59Monday, March 23, 2009

5 59Monday, March 23, 2009

E

47

44

SB

SB

SB

A

ICH9M Functional Strap Definitions

Signal

HDA_SDOUT

4 4

HDA_SYNC PCIE config1 bit0 ,

GNT2#/
GPIO53

GPIO20 Reserved.

GNT1#/
GPIO51

GNT3#/
GPIO55

GNT0#:
SPI_CS1#/

3 3

GPIO58

SPI_MOSI Integrated TPM En able,

GPIO49 DMI Termination

SATALED# PCI Express Lane

SPKR

TP3

GPIO33/
HDA_DOCK

2 2

_EN#

Usage/When Sampled

XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK.

Rising Edge of PWROK.

PCIE config2 bit2,
Rising Edge of PWROK.

ESI Strap (Server Only)
Rising Edge of PWROK.

Top-Block Swap
override. Rising Edge
of PWROK.

Boot BIOS Destination
Selection 0:1.
Rising Edge of PWROK.

Rising Edge of CLPWROK.

Voltage. Rising Edge
of CLPWROK.

Reversal. Rising Edge
of PWROK.

No Reboot.
Rising Edge of PWROK.

XOR Chain Entrance.
Rising Edge of PWROK.

Flash Descriptor
Security Override
Strap. Rising Edge of
PWROK.

Allows entrance to XOR Chain t esting when TP3
pulled low. When TP3 not pulle d low at rising edge
of PWROK, sets bit1 of RPC.PC (Cofig Registers:
offset 224h). This signal has weak internal
pull-down.

This signal has a weak interna l pull-down.
Sets bit0 of PRC.PC (Config Re gisters: Offset
224h).

This signal has a weak interna l pull-up.
Sets bit2 of PRC.PC2 (Config R egisters: Offset
224h).

This signal should not be pull ed high.

ESI compatible mode is for ser ver platforms only.
This signal should not be pull ed low for desktop
and mobile.

Sampled low: Top-Block Swap mo de (inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be abl e to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled dow n.

Controllable via Boot BIOS Des tination bit
(Config Registers: Offset 3410 h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC

Sample low: the Integrated TPM will be disable.
Sample high: the MCH TPM enabl e strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.

The signal is required to be l ow for desktop
applications and required to b e high for mobile
applications.

Signal has weak internal pull- up. Sets bit 27
of MPC.LR (Device 28: Function 0:Offset D8).

If sampled high, the system is strapped to the
"No Reboot" mode (ICH9 will di sable the TCO Timer
system reboot feature). The st atus is readable
via the NO REBOOT bit.

This signal should not be pull low unless using
XOR Chain testing.

Sampled low: the Flash Descrip tor Security will be
overridden. If high, the secur ity measures will be
in effect. This should only be enabled in
manufacturing environments usi ng an external
pull-up resister.

ICH9 EDS 642879 Rev.1.5

Comment

B

ICH9 Integrated pull-up
and pull-down Resistors

C

Cantiga chipset and ICH9M I/O controller

D

E

Hub strapping configuration

ICH9 EDS 642879 Rev.1.5 Montevina Platform Design guide 22339 Rev.0.5

SIGNAL Resistor Type/Value

CL_CLK[1:0]

CL_DATA[1:0]

CL_RST0#

DPRSLPVR/GPIO16

ENERGY_DETECT

HDA_BIT_CLK

HDA_DOCK_EN#/GPIO33

HDA_RST#

HDA_SDIN[3:0]

HDA_SDOUT

HDA_SYNC

GLAN_DOCK#

GNT[3:0]#/GPIO[55,53,51]

GPIO20

GPIO49

LDA[3:0]#/FHW[3:0]#

LAN_RXD[2:0]

LDRQ[0]

LDRQ[1]/GPIO23

PME#

PWRBTN#

SATALED#

SPI_CS1#/GPIO58/CLGPIO6

SPI_MOSI

SPI_MISO

SPKR

TACH_[3:0]

TP[3]

USB[11:0][P,N]

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K

PULL-DOWN 20K

The pull-up or pull-down
active when configured
for native GLAN_DOCK#
functionality and determined
by LAN controller.

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 20K

PULL-UP 15K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-DOWN 20K

PULL-UP 20K

PULL-UP 20K

PULL-DOWN 15K

Pin Name

CFG[2:0] FSB Frequen cy Select 000 = FSB1067

CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]

CFG5 DMI x2 Select 0 = DMI x2

CFG6 iTPM Host Interface

CFG7 Intel Management

CFG9

CFG10 PCIE Loopback enable 0 = Enable (Note 3)

CFG[13:12] XOR/ALL

CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled

CFG19 DMI Lane Reversal

CFG20 Digital Display Port

SDVO
_CTRLDATA

L_DDC_DATA Local Flat Panel

NOTE:

1. All strap signals are sampl ed with respect to the leading edge of the (G)MCH
Power OK (PWROK) signal.

2. iTPM can be disabled by a ' Soft-Strap' option in the Flas h-decriptor section of
the Firmware. This 'Soft-St rap' is activated only after e nabling iTPM via CFG6.
Only one of the CFG10/CFG12 /CFG13 straps can be enabled a t any time.

Strap Description Configuration

011 = FSB667
010 = FSB800

Reserved

engine crypto strap

PCIE Graphics Lane 0 = Reserved Lanes, 15->0, 1 4->1 ect..

(SDVO/DP/iHDMI)
Concurrent with PCIe

SDVO Present

(LFP) Present

others = Reserved

1 = DMI x4 (Default)

0 = The iTPM Host Interface is enabled (Note 2)

1 = The iTPM Host Interface is disabled (default)

0 = Transport Layer Security ( TLS) cipher

suite with no confidentiality

1 = TLS cipher suite with conf identiality(Default)

1 = Normal operation (Default) : Lane Numbered in

Order

1 = Disable (Default)

00 = Reserve
10 = XOR mode Enabled
01 = ALLZ mode Enable (Note 3)

11 = Disabled (Default)

1 = Dynamic ODT Enabled (Defau lt)

0 = Normal operation (Default) : Lane Numbered in

Order

1 = Reverse Lanes
DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)
DMI x2 mode [MCH->ICH]: (3->0, 2->1)

0 = Only Digital Display Port or PCIE is

operational (Default)

1 = Digital display Port and P CIe are operating

simulataneously via the PEG po rt

0 = No SDVO Card Present (Defa ult)

1 = SDVO Card Present

0 = LFP Disabled (Default)

1 = LFP Card Present; PCIE dis abled

USB TablePCIE Routing

0
1
2
3
4
5
6
7
8
9
10
11

USB

USB1
USB2
USB3
RESERVED
MINI CARD
RESERVED
BLUETOOTH
NEW CARD
RESERVED
RESERVED
Card Reader
CAMERA

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

Table of Content

Table of Content

Alba Discrete

Alba Discrete

Alba Discrete

6 59Monday, March 23, 2009

6 59Monday, March 23, 2009

6 59Monday, March 23, 2009

SB

SB

SB

LANE2

MiniCard WLAN

Pair Device

LANE3 LAN

LANE5 New Card

1 1

5

SSID = CLOCK

+3.3V_RUN

R703

R703

D D

12

C701

C701

+3.3V_RUN 3D3V_S0_CK505

12

C715

C715

C C

B B

3D3V_S0_CK505

0R3-0-U-GP

0R3-0-U-GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP

R704

R704

1 2

0R3-0-U-GP

0R3-0-U-GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

12

DY

DY

12

R713

R713
10KR2J-3-GP

10KR2J-3-GP

ITP_EN

R716

R716
10KR2J-3-GP

10KR2J-3-GP

12

12

C702

C702

DY

DY

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

12

12

C716

C716

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

ITP_EN Output

0 SRC8
1 CPU_ITP

12

C703

C703

C704

C704

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

C717

C717

C718

C718

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

CLKSATAREQ#20

CLKREQ#_B11

PCLK_FWH43

PCLK_KBC26
CLK_PCI_ICH19

CLK_14M_ICH20

12

12

C705

C705

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C719

C719

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

3D3V_S0_CK505_IO

12

12

C706

C706

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

12

C712

C712

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C707

C707

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C720

C720

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

ALBA X00

12

C724

C724

DY

DY

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

C713

C713

DY

DY

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

ALBA X00

12

C721

C721

DY

DY

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

3D3V_S0_CK505

12

R714

R714
10KR2J-3-GP

10KR2J-3-GP

12

R717

R717
10KR2J-3-GP

10KR2J-3-GP

DY

DY

4

SC12P50V2JN-3GP

SC12P50V2JN-3GP

CLK_48M_CARD50

CLK_48M_ICH20

H_STP_PCI#20
H_STP_CPU#20

ICH_SMBCLK16,17,20,43

ICH_SMBDATA16,17,20,43

CK_PWRGD20

12

C722

C722

DY

DY

DY

DY

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

PCI2_TME

3

CLK_XTAL_IN

X701

X701

C711

C711

1 2

CLK_XTAL_OUT

12

R706

R706

1 2

22R2J-2-GP

22R2J-2-GP

CLKSATAREQ#

FSA

CLKREQ#_1
PCI2_TME

27_SEL
ITP_EN

FSB
FSC

ICS9LPRS355BKLFT-GP-U

ICS9LPRS355BKLFT-GP-U

17

45
44

63

10
11
12
13
14

64

55

1 2

X-14D31818M-50GP

X-14D31818M-50GP

12

C708

C708

12

SC12P50V2JN-3GP

SC12P50V2JN-3GP

R705 22R2J-2-GPR705 22R2J-2-GP

1 2

DY

DY

C714 SC4D7P50V2CN-1GP

C714 SC4D7P50V2CN-1GP

R708 475R2F-L1-GPR708 475R2F-L1-GP

1 2

R707 33R2J-2-GP

R707 33R2J-2-GP

1 2

DY

DY

R709 33R2J-2-GPR709 33R2J-2-GP

1 2

R710 33R2J-2-GPR710 33R2J-2-GP

1 2

R711 33R2J-2-GPR711 33R2J-2-GP

1 2

C723

C723

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

Main source: 71.08513.003 (SLG8SP513VTR)
Second source: 71.00875.C03 (RTM875N-606-VD-GRT)

PCI2_TME Output

0

Overclocking of CPU and SRC all owed

1

Overclocking of CPU and SRC not allowed

U701

U701

3

X1

2

X2

USB_48M HZ/FSLA

PCI_STOP#
CPU_STO P#

7

SCLK

6

SDATA

CK_PW RGD/PD#

8

PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SE LECT
PCI_F5/ITP_EN

FSLB/TES T_MODE

5

REF0/FSL C/TEST_SEL

NC#55

2

NEWCARD_CLKREQ#
MINI1_CLKREQ#

NEWCARD_CLKREQ#

CLK_CPU_BCLK1

61

CLK_CPU_BCLK1#

60

CLK_MCH_BCLK1

58

CLK_MCH_BCLK1#

57

CLK_CPU_ITP1

54

CLK_CPU_ITP1#

53

CLK_PCIE_LAN1

51

CLK_PCIE_LAN1#

50

CLK_PCIE_VGA1

48

CLK_PCIE_VGA1#

47

CLK_PCIE_NEW1

41

CLK_PCIE_NEW1#

42

40
39

CLK_PCIE_MINI1_1

37

CLK_PCIE_MINI1_1#

38

CLK_MCH_3GPLL1

34

CLK_MCH_3GPLL1#

35

CLK_PCIE_ICH1

31

CLK_PCIE_ICH1#

32

CLK_PCIE_SATA1

28

CLK_PCIE_SATA1#

29

MCH_SSCDREFCLK1

24

MCH_SSCDREFCLK1#

25

CLK_MCH_DREFCLK1

20

CLK_MCH_DREFCLK1#

21

MCH_SSCDREFCLK1

DY

DY

CLK_PCIE_NEW
CLK_PCIE_NEW#

MCH_SSCDREFCLK1

12

EC702

EC702
SC47P50V2JN-3GP

SC47P50V2JN-3GP

3D3V_S0_CK505_IO3D3V_S0_CK505

4

9

16

VDD48

VDDPCI

VDDREF

GNDREF

GNDPCI

GND48

1

15

18

19

23

27

33

46

62

VDDSRC

VDDCPU

43

52

56

VDDPLL3

VDD96_IO

VDDSRC_IO

VDDSRC_IO

VDDSRC_IO

VDDCPU_IO

VDDPLL3_IO

SRCT11
SRCC11

27MHZ_N ONSS/SRCT1/SE1

27MHZ_S S/SRCC1/SE2

GND

GND

GNDSRC

GNDSRC

GNDSRC

GNDCPU

GND

22

26

30

36

49

59

65

CPUT0
CPUC0

CPUT1_F
CPUC1_F

CPUT2_ITP /SRCT8

CPUC2_ITP /SRCC8

SRCT7/CR #_F

SRCC7/CR #_E

GM 20090310

SRCT6
SRCC6

SRCT10
SRCC10

SRCT11/C R#_H

SRCC11/C R#_G

SRCT9
SRCC9

SRCT4
SRCC4

SRCT3/CR #_C

SRCC3/CR #_D

SRCT2/SA TAT

SRCC2/SA TAC

SRCT0/DO TT_96

SRCC0/DO TC_96

GM 20090311

3D3V_S0_CK505

R724

R724
10KR2J-3-GP

10KR2J-3-GP

PM

PM

1 2

27_SEL

R715

R715
10KR2J-3-GP

10KR2J-3-GP

GM

GM

1 2

R702 10KR2J-3-GPR702 10KR2J-3-GP

1 2

R701 10KR2J-3-GPR701 10KR2J-3-GP

1 2

12

C709

C709

DY

DY

DY

DY

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

RN701 SRN0J-6-GPRN701 SRN0J-6-GP

1

4

2 3

RN702 SRN0J-6-GPRN702 SRN0J-6-GP

1

4

2 3

RN703 SRN0J-6-GPRN703 SRN0J-6-GP

1

4

2 3

RN704 SRN0J-6-GPRN704 SRN0J-6-GP

1

4

2 3

RN712 SRN0J-6-GPRN712 SRN0J-6-GP

1

4

2 3

RN705 SRN0J-6-GPRN705 SRN0J-6-GP

2 3
1

4

RN706 SRN0J-6-GPRN706 SRN0J-6-GP

2 3
1

2 3
1

2 3
1

2 3
1

2 3

GM

GM

1

2 3

GM

GM

1

1 2

PM

PM

MCH_SSCDREFCLK1#

12

DY

DY

4

4

4

4

4

4

EC703

EC703
SC47P50V2JN-3GP

SC47P50V2JN-3GP

RN707 SRN0J-6-GPRN707 SRN0J-6-GP

RN708 SRN0J-6-GPRN708 SRN0J-6-GP

RN709 SRN0J-6-GPRN709 SRN0J-6-GP

RN711 SRN0J-6-GP

RN711 SRN0J-6-GP

RN710 SRN0J-6-GP

RN710 SRN0J-6-GP

R712 0R2J-2-GP

R712 0R2J-2-GP

1

+3.3V_RUN

12

12

C710

C710

EC701

EC701

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

SC22P50V2JN-4GP

SC22P50V2JN-4GP

CLK_CPU_BCLK 8
CLK_CPU_BCLK# 8

CLK_MCH_BCLK 10
CLK_MCH_BCLK# 10

CLK_CPU_ITP 43
CLK_CPU_ITP# 43

CLK_PCIE_LAN 25
CLK_PCIE_LAN# 25

CLK_PCIE_VGA 53
CLK_PCIE_VGA# 53

CLK_PCIE_NEW 50
CLK_PCIE_NEW# 50

NEWCARD_CLKREQ# 50
MINI1_CLKREQ# 43

CLK_PCIE_MINI1 43
CLK_PCIE_MINI1# 43

CLK_MCH_3GPLL 11
CLK_MCH_3GPLL# 11

CLK_PCIE_ICH 19
CLK_PCIE_ICH# 19

CLK_PCIE_SATA 18
CLK_PCIE_SATA# 18

MCH_SSCDREFCLK 11
MCH_SSCDREFCLK# 11

CLK_MCH_DREFCLK 11
CLK_MCH_DREFCLK# 11

GM 20090310

CLK_VGA_27M_NSS 54

27_SEL PIN 20 PIN 21

0 DOT96T DOT96C

1 SRCT0 SRCC0

UMA

Discrete

SEL1
FSB

0 1
0 1

SEL0
FSA

1
01

CPU

100M
133M
166M
200M

4

FSB

533M
667M
800M

1067M266M

R718 10KR2J-3-GPR718 10KR2J-3-GP

CPU_BSEL28

X

CPU_BSEL18

CPU_BSEL08

1 2

R719 0R2J-2-GPR719 0R2J-2-GP

1 2

R720 2K2R2J-2-GPR720 2K2R2J-2-GP

1 2

R721 1KR2J-1-GPR721 1KR2J-1-GP

1 2

R722 1KR2J-1-GPR722 1KR2J-1-GP

1 2

R723 1KR2J-1-GPR723 1KR2J-1-GP

1 2

3

FSC

FSB

FSA

MCH_CLKSEL0 11

MCH_CLKSEL1 11

MCH_CLKSEL2 11

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Clock Generator SLG8SP513VTR

Clock Generator SLG8SP513VTR

Clock Generator SLG8SP513VTR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

1

SB

SB

7 59Monday, March 23, 2009

7 59Monday, March 23, 2009

7 59Monday, March 23, 2009

SB

A A

FSC

1
0
0 1
0
0 0 0

5

SEL2

D

C

B

A

SSID = CPU

D

H_A#[35..3]10

H_REQ#[4..0]10

C

B

5

1 OF 4

1 OF 4

CPU1A

H_A#3
H_A#4
H_A#5

H_A#[35..3]

H_ADSTB#010

H_ADSTB#110

H_A20M#18

H_FERR#18

H_IGNNE#18

H_STPCLK#18

H_INTR18
H_NMI18
H_SMI#18

TP807TP807
TP808TP808
TP802TP802
TP804TP804
TP803TP803
TP805TP805
TP813TP813
TP810TP810
TP806TP806
TP809TP809

TP801TP801

H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

RSVD_CPU_1
RSVD_CPU_2
RSVD_CPU_3
RSVD_CPU_4
RSVD_CPU_5
RSVD_CPU_6
RSVD_CPU_7
RSVD_CPU_8
RSVD_CPU_9
RSVD_CPU_10

RSVD_CPU_11

CPU1A

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD#M4

N5

RSVD#N5

T2

RSVD#T2

V3

RSVD#V3

B2

RSVD#B2

C3

RSVD#C3

D2

RSVD#D2

D22

RSVD#D2 2

D3

RSVD#D3

F6

RSVD#F6

B1

KEY_NC

BGA479-SKT6-GPU7

BGA479-SKT6-GPU7

62.10040.221

TEST7

ADDR GROUP 0

ADDR GROUP 0

ADDR GROUP 1

ADDR GROUP 1

XDP/ITP SIGNALS CONTROL

XDP/ITP SIGNALS CONTROL

THERMAL

THERMAL

PROCHOT #

ICH

ICH

THERMTR IP#

HCLK

HCLK

RESERVED

RESERVED

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS0#
RS1#
RS2#

TRDY#

HIT#

HITM#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#

PREQ#

TCK

TDO
TMS

TRST#

DBR#

THRMDA
THRMDC

BCLK0
BCLK1

4

H1
E2
G5

H5
F21
E1

F1

CPU_IERR#

D20
B3

H4

H_CPURST#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3
G2

G6
E4

ITP_BPM#0

AD4

ITP_BPM#1

AD3

ITP_BPM#2

AD1

ITP_BPM#3

AC4

ITP_BPM#4

AC2

ITP_BPM#5

AC1

ITP_TCK

AC5

ITP_TDI

AA6

TDI

ITP_TDO

AB3

ITP_TMS

AB5

ITP_TRST#

AB6

ITP_DBRESET#

C20

R805 0R2J-2-GP

R805 0R2J-2-GP

R806 56R2J-4-GPR806 56R2J-4-GP

D21
A24
B25

C7

R810 56R2J-4-GP

R810 56R2J-4-GP

A22
A21

TP814TP814

1

R804 56R2J-4-GPR804 56R2J-4-GP

1 2

1 2

DY

DY

1 2

H_THERMDA
H_THERMDC

1 2

DY

DY

H_ADS# 10
H_BNR# 10
H_BPRI# 10

H_DEFER# 10
H_DRDY# 10
H_DBSY# 10

H_BREQ#0 10

H_INIT# 18

H_LOCK# 10
H_CPURST# 10,43
H_RS#[2..0] 10

H_TRDY# 10

H_HIT# 10
H_HITM# 10

ITP_BPM#0 43
ITP_BPM#1 43
ITP_BPM#2 43
ITP_BPM#3 43
ITP_BPM#4 43
ITP_BPM#5 43
ITP_TCK 43

ITP_TDI 43
ITP_TDO 43
ITP_TMS 43
ITP_TRST# 43
ITP_DBRESET# 20,43

CPU_PROCHOT# 34

+1.05V_VCCP

H_THERMDA 28
H_THERMDC 28

H_THRMTRIP# 11,18,26,30,54

+1.05V_VCCP

CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7

2KR2F-3-GP

2KR2F-3-GP

3

+1.05V_VCCP

H_THRMTRIP# should connect to
ICH9 and MCH without T-ing.

+1.05V_VCCP

R814

R814
1KR2F-3-GP

1KR2F-3-GP

1 2

12

R813

R813

Layout notes
Z= 55 Ohm 0.5" MAX for CPU_GTLREF0

CPU_GTLREF0

12

C802

C802

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

X01 20090112

H_DSTBN#010
H_DSTBP#010
H_DINV#010

H_DSTBN#110
H_DSTBP#110
H_DINV#110

R807 1KR2J-1-GP

R807 1KR2J-1-GP

1 2

DY

DY

R809 1KR2J-1-GP

R809 1KR2J-1-GP

1 2

DY

DY

R808 1KR2J-1-GP

R808 1KR2J-1-GP

1 2

DY

DY

R801 1KR2J-1-GP

R801 1KR2J-1-GP

1 2

DY

DY

CPU_BSEL07
CPU_BSEL17
CPU_BSEL27

2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

TEST1
TEST2
CPU_TEST3

CPU_TEST5

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_D#[63..0]

CPU1B

CPU1B

E22

D0#

F24

D1#

E26

D2#

G22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

D9#

J24

D10#

J23

D11#

H22

D12#

F26

D13#

K22

D14#

H23

D15#

J26

DSTBN0#

H26

DSTBP0#

H25

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L23

D20#

M24

D21#

L22

D22#

M23

D23#

P25

D24#

P23

D25#

P22

D26#

T24

D27#

R24

D28#

L25

D29#

T25

D30#

N25

D31#

L26

DSTBN1#

M26

DSTBP1#

N24

DINV1#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL0

B23

BSEL1

C21

BSEL2

BGA479-SKT6-GPU7

BGA479-SKT6-GPU7

62.10040.221

2 OF 4

2 OF 4

DATA GRP0 DATA GRP1

DATA GRP0 DATA GRP1

MISC

MISC

1

H_DINV#[3..0] 10

H_DSTBN#[3..0] 10

H_DSTBP#[3..0] 10

H_D#[63..0] 10

H_D#32

Y22

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#

DATA GRP2DATA GRP3

DATA GRP2DATA GRP3

D43#
D44#
D45#
D46#

D47#
DSTBN2#
DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#
DSTBN3#
DSTBP3#

DINV3#

COMP0
COMP1
COMP2
COMP3

DPRSTP#

DPSLP#
DPWR #

PWRG OOD

SLP#

PSI#

Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 oh m, make
trace length shorter than 0.5" .

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

H_DSTBN#2 10
H_DSTBP#2 10
H_DINV#2 10

H_DSTBN#3 10
H_DSTBP#3 10
H_DINV#3 10

R812 27D4R2F-L1-GPR812 27D4R2F-L1-GP

1 2

R811 54D9R2F-L1-GPR811 54D9R2F-L1-GP

1 2

R803 27D4R2F-L1-GPR803 27D4R2F-L1-GP

1 2

R802 54D9R2F-L1-GPR802 54D9R2F-L1-GP

1 2

H_DPRSTP# 11,18,34
H_DPSLP# 18
H_DPWR# 10
H_PWRGOOD 18,30
H_CPUSLP# 10

PSI# 34

<Core Design>

<Core Design>

A

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

CPU-FSB(1/2)

CPU-FSB(1/2)

CPU-FSB(1/2)

Alba Discrete

Alba Discrete

Alba Discrete

8 59Monday, March 23, 2009

8 59Monday, March 23, 2009

8 59Monday, March 23, 2009

SB

SB

SB

5

4

3

2

1

SSID = CPU

D D

+VCC_CORE

3 OF 4

3 OF 4

CPU1C

CPU1C

A7

VCC

A9

VCC

A10

VCC

A12

VCC

A13

VCC

A15

VCC

A17

VCC

A18

VCC

A20

VCC

B7

VCC

B9

VCC

B10

VCC

B12

VCC

B14

VCC

B15

VCC

B17

VCC

B18

VCC

B20

VCC

C9

VCC

C10

VCC

C12

VCC

C13

VCC

C15

VCC

C C

B B

C17

VCC

C18

VCC

D9

VCC

D10

VCC

D12

VCC

D14

VCC

D15

VCC

D17

VCC

D18

VCC

E7

VCC

E9

VCC

E10

VCC

E12

VCC

E13

VCC

E15

VCC

E17

VCC

E18

VCC

E20

VCC

F7

VCC

F9

VCC

F10

VCC

F12

VCC

F14

VCC

F15

VCC

F17

VCC

F18

VCC

F20

VCC

AA7

VCC

AA9

VCC

AA10

VCC

AA12

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA18

VCC

AA20

VCC

AB9

VCC

AC10

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB15

VCC

AB17

VCC

AB18

VCC

BGA479-SKT6-GPU7

BGA479-SKT6-GPU7

62.10040.221

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCCA
VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENS E

VSSSENS E

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

+VCC_CORE

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

layout note: "+1.5V_VCCA"
as short as possible

CPU_VID[6..0] 34

R902

R902

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U

R901

R901

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U

+VCC_CORE

12

DY

DY

+VCC_CORE

12

+VCC_CORE

12

+1.05V_VCCP

12

DY

DY

PG901

PG901

1 2

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

PG902

PG902

1 2

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

C915

C915

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C911

C911

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C909

C909

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

TC901

TC901

ST220U2D5VBM-LGP

ST220U2D5VBM-LGP

12

12

C922

C922

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

C912

C912

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

C913

C913

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

C923

C923

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

+VCC_CORE

VCC_SENSE 34

VSS_SENSE 34

4 OF 4

4 OF 4

CPU1D

CPU1D

12

12

C919

C919

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C938

C938

C908

C908

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

DY

DY

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C903

C903

C902

C902

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

12

12

C934

C934

C901

C901

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

C935

C935

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C907

C907
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

X01 20090106

DY

DY

12

12

12

C932

C932

C910

C910

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

C937

C937

C930

C930

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

C931

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

C920

C920

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C921

C921

C916

C916

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

C917

C917

C918

C918

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

C931

12

C927

C927

C936

C936

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

C929

C929

C928

C928

DY

DY

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

C933

C933

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

C926

C926
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C914

C914
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

X01 20090106

R903

R903

12

12

C905

C905

C904

C904

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+1.5V_RUN+1.5V_VCCA

Layout Note:
Place as close as possible
to the CPU VCCA pin.

C924

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C939

C939

C906

C906

C925

C925

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1 2

0R3-0-U-GP

0R3-0-U-GP

12

12

C940

C940
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

VCC_SENSE and VSS_SENSE lines
should be of equal length.

12

12

C924

A4

VSS

A8

VSS

A11

VSS

A14

VSS

A16

VSS

A19

VSS

A23

VSS

AF2

VSS

B6

VSS

B8

VSS

B11

VSS

B13

VSS

B16

VSS

B19

VSS

B21

VSS

B24

VSS

C5

VSS

C8

VSS

C11

VSS

C14

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C25

VSS

D1

VSS

D4

VSS

D8

VSS

D11

VSS

D13

VSS

D16

VSS

D19

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E11

VSS

E14

VSS

E16

VSS

E19

VSS

E21

VSS

E24

VSS

F5

VSS

F8

VSS

F11

VSS

F13

VSS

F16

VSS

F19

VSS

F2

VSS

F22

VSS

F25

VSS

G4

VSS

G1

VSS

G23

VSS

G26

VSS

H3

VSS

H6

VSS

H21

VSS

H24

VSS

J2

VSS

J5

VSS

J22

VSS

J25

VSS

K1

VSS

K4

VSS

K23

VSS

K26

VSS

L3

VSS

L6

VSS

L21

VSS

L24

VSS

M2

VSS

M5

VSS

M22

VSS

M25

VSS

N1

VSS

N4

VSS

N23

VSS

N26

VSS

P3

VSS

BGA479-SKT6-GPU7

BGA479-SKT6-GPU7

62.10040.221

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

CPU_GND1

CPU_GND2
CPU_GND3

CPU_GND4

NCTF
PIN

TP902TP902

TP901TP901
TP903TP903

TP904TP904

X01 20090106

A A

5

4

3

2

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

CPU-Power(2/2)

CPU-Power(2/2)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU-Power(2/2)

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

1

9 59Monday, March 23, 2009

9 59Monday, March 23, 2009

9 59Monday, March 23, 2009

SB

SB

SB

5

D

C

B

A

SSID = MCH

4

3

2

1

1 OF 10

U1001A

U1001A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SW ING

E3

H_RCOMP

C12

H_CPURS T#

E11

H_CPUSL P#

A11

H_AVREF

B11

H_DVREF

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

HOST

HOST

H_AVREF

H_D#[63..0]

H_CPURST#8,43
H_CPUSLP#8

12

C1002

C1002

DY

DY

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

D

H_SWING

H_RCOMP

+1.05V_VCCP

12

R1003

R1003
221R2F-2-GP

221R2F-2-GP

12

R1002

R1002
100R2F-L1-GP-U

100R2F-L1-GP-U

C

B

H_SWING routing Trace width and
Spacing use 10 / 20 mil

H_SWING Resistors and
Capacitors close MCH
500 mil ( MAX )

12

C1001

C1001
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

H_RCOMP routing Trace width and
Spacing use 10 / 20 mil

1 2

24D9R2F-L-GP

24D9R2F-L-GP

R1001

R1001

H_D#[63..0]8

Place R1001 near to the chip ( < 0.5")

+1.05V_VCCP

R1004

R1004
1KR2F-3-GP

1KR2F-3-GP

1 2

12

R1005

R1005
2KR2F-3-GP

2KR2F-3-GP

1 OF 10

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB #_0
H_ADSTB #_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER #

H_DBSY#

HPLL_CL K

HPLL_CL K#

H_DPW R#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#

H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN #_0
H_DSTBN #_1
H_DSTBN #_2
H_DSTBN #_3

H_DSTBP #_0
H_DSTBP #_1
H_DSTBP #_2
H_DSTBP #_3

H_REQ#_ 0
H_REQ#_ 1
H_REQ#_ 2
H_REQ#_ 3
H_REQ#_ 4

H_RS#_0
H_RS#_1
H_RS#_2

A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20

H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9

J8
L3
Y13
Y1

L10
M7
AA5
AE6

L9
M8
AA6
AE5

B15
K13
F13
B13
B14

B6
F12
C8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_A#[35..3]

H_ADS# 8
H_ADSTB#0 8
H_ADSTB#1 8
H_BNR# 8

H_BPRI# 8

H_BREQ#0 8

H_DEFER# 8

H_DBSY# 8

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

H_DPWR# 8
H_DRDY# 8
H_HIT# 8
H_HITM# 8

H_LOCK# 8

H_TRDY# 8

H_DINV#[3..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

H_REQ#[4..0]

H_RS#[2..0]

H_A#[35..3] 8

H_DINV#[3..0] 8

H_DSTBN#[3..0] 8

H_DSTBP#[3..0] 8

H_REQ#[4..0] 8

H_RS#[2..0] 8

<Core Design>

<Core Design>

A

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Cantiga-HOST(1/6)

Cantiga-HOST(1/6)

Cantiga-HOST(1/6)

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

10 59Monday, March 23, 2009

10 59Monday, March 23, 2009

10 59Monday, March 23, 2009

SB

SB

SB

D

C

B

A

SSID = MCH

is current setting

*

CFG Strap HighLow

CFG 5

D

C

B

A

CFG 6

CFG 7

CFG 9 PCIE GFX lane reversed

CFG 10 PCIE loopback enable PCIE loopback disable

CFG 12 ALLZ mode enable ALLZ mode disable

CFG 13 XOR mode enable XOR mode disable

CFG 16

CFG 19
DMI Lane Reserved

CFG 20
SDVO concurrent
with PCIE

SDVO_CTRLDATA

L_DDC_DATA LFP disable LFP card present

DDPC_CTRLDATA

+3.3V_RUN

R1105 2K21R2F-GP

R1105 2K21R2F-GP

1 2

DY

DY

R1115 2K21R2F-GP

R1115 2K21R2F-GP

1 2

DY

DY

R1110 4K02R2F-GP

R1110 4K02R2F-GP

1 2

DY

DY

R1112 4K02R2F-GP

R1112 4K02R2F-GP

1 2

DY

DY

RN1101

RN1101

4

SRN10KJ-5-GP

SRN10KJ-5-GP

R1128 2K21R2F-GP

R1128 2K21R2F-GP

1 2

DY

DY

R1108 2K21R2F-GP

R1108 2K21R2F-GP

1 2

DY

DY

R1107 2K21R2F-GP

R1107 2K21R2F-GP

1 2

DY

DY

R1103 2K21R2F-GP

R1103 2K21R2F-GP

1 2

DY

DY

R1127 4K02R2F-GP

R1127 4K02R2F-GP

1 2

DY

DY

R1124 2K21R2F-GP

R1124 2K21R2F-GP

1 2

DY

DY

R1102 2K21R2F-GP

R1102 2K21R2F-GP

1 2

DY

DY

R1106 2K21R2F-GP

R1106 2K21R2F-GP

1 2

DY

DY

R1104 2K21R2F-GP

R1104 2K21R2F-GP

1 2

DY

DY

5

DMI X 2

ITPM enable

TLS cipher suite with
no confidentiality

FSB dynamic ODT disable

Normal operation Reverse DMI lanes

Only PCIE or SDVO
is operational

SDVO interface disable

SDVO/iHDMI/DP
interface disabled

CFG11

CFG18

CFG19

CFG20

PM_EXTTS#0

1

PM_EXTTS#1

23

CFG5

CFG6

CFG7

CFG8

CFG9

CFG10

CFG12

CFG13

CFG16

H_THRMTRIP#8,18,26,30,54

DMI X 4

ITPM disable

TLS cipher suite with
confidentiality

PCIE GFX lane
numbered in oder

FSB Dynamic ODT enable

*

PCIE and SDVO are
operatiing simultaneously

*

via the PEG port

SDVO interface enable

*
*

SDVO/iHDMI/DP

*

interface enabled

4

*
*
*

*

*
*
*
*

M36
N36
R33

AH9
AH10
AH12
AH13

AL34
AK34
AN35

AM35

AY21

BG23

BF23
BH18
BF18

T33

K12

T24

B31

B2

M1

U1001B

U1001B

RESERVE D#M36
RESERVE D#N36
RESERVE D#R33
RESERVE D#T33
RESERVE D#AH9
RESERVE D#AH10
RESERVE D#AH12
RESERVE D#AH13
RESERVE D#K12
RESERVE D#AL34
RESERVE D#AK34
RESERVE D#AN35
RESERVE D#AM35
RESERVE D#T24

RESERVE D#B31
RESERVE D#B2
RESERVE D#M1

RESERVE D#AY21

RESERVE D#BG23
RESERVE D#BF23
RESERVE D#BH18
RESERVE D#BF18

RSVD

RSVD

DDR CLK/ CONTROL/COMPENSATION

DDR CLK/ CONTROL/COMPENSATION

DPLL_RE F_SSCLK

DPLL_RE F_SSCLK#

CLK

CLK

FSB setting

MCH_CLKSEL07
MCH_CLKSEL17
MCH_CLKSEL27

TP1103TP1103
TP1105TP1105

TP1101TP1101
TP1102TP1102

TP1104TP1104

PM_SYNC#20

H_DPRSTP#8,18,34
PM_EXTTS#016
PM_EXTTS#117

R1118

R1118

PM_PWROK20,26,28

PLT_RST#19,25,26,43,50

DPRSLPVR20,34

1 2

0R2J-2-GP

0R2J-2-GP

1 2

R1101

R1101
100R2J-2-GP

100R2J-2-GP

SC100P50V2JN-3GP

SC100P50V2JN-3GP

C1101

C1101

DY

DY

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

PWROK_R
RSTIN#

12

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRS TP#

N33

PM_EXT_ TS#_0

P32

PM_EXT_ TS#_1

AT40

PWRO K

AT11

RSTIN#

T20

THERMTR IP#

R32

DPRSLPV R

BG48

NC#BG48

BF48

NC#BF48

BD48

NC#BD48

BC48

NC#BC48

BH47

NC#BH47

BG47

NC#BG47

BE47

NC#BE47

BH46

NC#BH46

BF46

NC#BF46

BG45

NC#BG45

BH44

NC#BH44

BH43

NC#BH43

BH6

NC#BH6

BH5

NC#BH5

BG4

NC#BG4

BH3

NC#BH3

BF3

NC#BF3

BH2

NC#BH2

BG2

NC#BG2

BE2

NC#BE2

BG1

NC#BG1

BF1

NC#BF1

BD1

NC#BD1

BC1

NC#BC1

F1

NC#F1

A47

NC#A47

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

DMI

DMI

CFG

CFG

PM

PM

GRAPHICS VID

GRAPHICS VID

MEHDA

MEHDA

NC

NC

MISC

MISC

3

2 OF 10

2 OF 10

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_ 0
SA_CK#_ 1
SB_CK#_ 0
SB_CK#_ 1

SA_CKE_ 0
SA_CKE_ 1
SB_CKE_ 0
SB_CKE_ 1

SA_CS#_ 0
SA_CS#_ 1
SB_CS#_ 0
SB_CS#_ 1

SA_ODT_ 0
SA_ODT_ 1
SB_ODT_ 0
SB_ODT_ 1

SM_RCOM P

SM_RCOM P#

SM_RCOM P_VOH

SM_RCOM P_VOL

SM_VREF

SM_PW ROK

SM_REXT

SM_DRAM RST#

DPLL_RE F_CLK

DPLL_RE F_CLK#

PEG_CLK

PEG_CLK #

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_ EN

CL_CLK

CL_DATA

CL_PW ROK

CL_RST#
CL_VREF

DDPC_CT RLCLK

DDPC_CT RLDATA

SDVO_CT RLCLK

SDVO_CT RLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCL K
HDA_RST #

HDA_SDI

HDA_SDO

HDA_SYNC

AP24
AT21
AV24
AU20

AR24
AR21
AU24
AV20

BC28
AY28
AY36
BB36

BA17
AY16
AV16
AR13

BD17
AY17
BF15
AY13

M_RCOMPP

BG22

M_RCOMPN

BH21

SM_RCOMP_VOH

BF28

SM_RCOMP_VOL

BH28

CANTIGA_SM_VREF

AV42
AR36

SM_REXT

BF17
BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_ITXN0_MRXN0

AE41

DMI_ITXN1_MRXN1

AE37

DMI_ITXN2_MRXN2

AE47

DMI_ITXN3_MRXN3

AH39

DMI_ITXP0_MRXP0

AE40

DMI_ITXP1_MRXP1

AE38

DMI_ITXP2_MRXP2

AE48

DMI_ITXP3_MRXP3

AH40

DMI_IRXN0_MTXN0

AE35

DMI_IRXN1_MTXN1

AE43

DMI_IRXN2_MTXN2

AE46

DMI_IRXN3_MTXN3

AH42

DMI_IRXP0_MTXP0

AD35

DMI_IRXP1_MTXP1

AE44

DMI_IRXP2_MTXP2

AF46

DMI_IRXP3_MTXP3

AH43

B33
B32
G33
F33
E33

C34

AH37
AH36
AN36
AJ35

MCH_CLVREF

AH34

N28
M28
G36
E36
K36
H36

TSATN#

B12

B28
B30
B29
C29
A28

MCH_CLVREF ~= 0.35V

1

TP1106TP1106

M_CLK_DDR0 16
M_CLK_DDR1 16
M_CLK_DDR2 17
M_CLK_DDR3 17

M_CLK_DDR#0 16
M_CLK_DDR#1 16
M_CLK_DDR#2 17
M_CLK_DDR#3 17

M_CKE0 16
M_CKE1 16
M_CKE2 17
M_CKE3 17

M_CS0# 16
M_CS1# 16
M_CS2# 17
M_CS3# 17

M_ODT0 16
M_ODT1 16
M_ODT2 17
M_ODT3 17

1 2

R1123

R1123
499R2F-2-GP

499R2F-2-GP

CLK_MCH_DREFCLK 7
CLK_MCH_DREFCLK# 7
MCH_SSCDREFCLK 7
MCH_SSCDREFCLK# 7

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

DMI_ITXN0_MRXN0 19
DMI_ITXN1_MRXN1 19
DMI_ITXN2_MRXN2 19
DMI_ITXN3_MRXN3 19

DMI_ITXP0_MRXP0 19
DMI_ITXP1_MRXP1 19
DMI_ITXP2_MRXP2 19
DMI_ITXP3_MRXP3 19

DMI_IRXN0_MTXN0 19
DMI_IRXN1_MTXN1 19
DMI_IRXN2_MTXN2 19
DMI_IRXN3_MTXN3 19

DMI_IRXP0_MTXP0 19
DMI_IRXP1_MTXP1 19
DMI_IRXP2_MTXP2 19
DMI_IRXP3_MTXP3 19

CL_CLK0 20
CL_DATA0 20

M_PWROK 20

CL_RST#0 20

CLKREQ#_B 7
MCH_ICH_SYNC# 20

2

80D6R2F-L-GP

80D6R2F-L-GP

80D6R2F-L-GP

80D6R2F-L-GP

GM 20090310

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#

MCH_SSCDREFCLK
MCH_SSCDREFCLK#

+1.05V_VCCP

R1114

R1114
1KR2F-3-GP

1KR2F-3-GP

1 2

12

12

R1116

R1116
499R2F-2-GP

499R2F-2-GP

C1106

C1106

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

DY

DY

1

+1.8V_SUS

R1113

+1.8V_SUS

12

R1126

R1126

12

R1125

R1125

12

DY

DY

C1144

C1144

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C1143

C1143

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

RN1102

RN1102

2 3

PM

PM

1

SRN0J-6-GP

SRN0J-6-GP

RN1103

RN1103

2 3

PM

PM

1

SRN0J-6-GP

SRN0J-6-GP

SM_RCOMP_VOH

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

SM_RCOMP_VOL

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

+1.8V_SUS

12

R1119

R1119

DY

DY

10KR2F-2-GP

10KR2F-2-GP

12

R1129

R1129

DY

DY

10KR2F-2-GP

10KR2F-2-GP

4

4

C1104

C1104

C1102

C1102

1 2

R1139

R1139
0R3-0-U-GP

0R3-0-U-GP

12

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

12

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

+V_DDR_MCH_REF

C1105

C1105

C1103

C1103

R1113
1KR2F-3-GP

1KR2F-3-GP

1 2

12

12

R1109

R1109
3K01R2F-3-GP

3K01R2F-3-GP

12

R1111

R1111
1KR2F-3-GP

1KR2F-3-GP

1 2

GM 20090310

+3.3V_RUN+1.05V_VCCP

12

R1121

R1121
56R2J-4-GP

56R2J-4-GP

TSATN#

CLKREQ#_B

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

R1122

R1122

DY

DY

10KR2J-3-GP

10KR2J-3-GP

TSATN#_KBC

C

Q1101

Q1101

B

DY

DY

MMBT3904WT1G-GP

MMBT3904WT1G-GP

E

+3.3V_RUN

R1117

R1117

1 2

10KR2J-3-GP

10KR2J-3-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga-DMI/CFG(2/6)

Cantiga-DMI/CFG(2/6)

Cantiga-DMI/CFG(2/6)

Alba Discrete

Alba Discrete

Alba Discrete

TSATN#_KBC 26

11 59Monday, March 23, 2009

11 59Monday, March 23, 2009

11 59Monday, March 23, 2009

SB

SB

SB

5

D

C

B

A

SSID = MCH

4

3

2

1

M_A_DQ[63..0]16

D

C

B

M_A_DQ[63..0]

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

U1001D

U1001D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_1 0

AT38

SA_DQ_1 1

AN41

SA_DQ_1 2

AN39

SA_DQ_1 3

AU44

SA_DQ_1 4

AU42

SA_DQ_1 5

AV39

SA_DQ_1 6

AY44

SA_DQ_1 7

BA40

SA_DQ_1 8

BD43

SA_DQ_1 9

AV41

SA_DQ_2 0

AY43

SA_DQ_2 1

BB41

SA_DQ_2 2

BC40

SA_DQ_2 3

AY37

SA_DQ_2 4

BD38

SA_DQ_2 5

AV37

SA_DQ_2 6

AT36

SA_DQ_2 7

AY38

SA_DQ_2 8

BB38

SA_DQ_2 9

AV36

SA_DQ_3 0

AW3 6

SA_DQ_3 1

BD13

SA_DQ_3 2

AU11

SA_DQ_3 3

BC11

SA_DQ_3 4

BA12

SA_DQ_3 5

AU13

SA_DQ_3 6

AV13

SA_DQ_3 7

BD12

SA_DQ_3 8

BC12

SA_DQ_3 9

BB9

SA_DQ_4 0

BA9

SA_DQ_4 1

AU10

SA_DQ_4 2

AV9

SA_DQ_4 3

BA11

SA_DQ_4 4

BD9

SA_DQ_4 5

AY8

SA_DQ_4 6

BA6

SA_DQ_4 7

AV5

SA_DQ_4 8

AV7

SA_DQ_4 9

AT9

SA_DQ_5 0

AN8

SA_DQ_5 1

AU5

SA_DQ_5 2

AU6

SA_DQ_5 3

AT5

SA_DQ_5 4

AN10

SA_DQ_5 5

AM11

SA_DQ_5 6

AM5

SA_DQ_5 7

AJ9

SA_DQ_5 8

AJ8

SA_DQ_5 9

AN12

SA_DQ_6 0

AM13

SA_DQ_6 1

AJ11

SA_DQ_6 2

AJ12

SA_DQ_6 3

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

4 OF 10

4 OF 10

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_W E#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_ 0
SA_DQS_ 1
SA_DQS_ 2
SA_DQS_ 3
SA_DQS_ 4
SA_DQS_ 5
SA_DQS_ 6

SA_DQS_ 7
SA_DQS# _0
SA_DQS# _1
SA_DQS# _2
SA_DQS# _3
SA_DQS# _4
SA_DQS# _5
SA_DQS# _6
SA_DQS# _7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_1 0
SA_MA_1 1
SA_MA_1 2
SA_MA_1 3
SA_MA_1 4

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW1 2
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW2 4
BC21
BG26
BH26
BH17
AY25

M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6

M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9

M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_A14

M_A_DM0

AM37

M_A_DM[7..0]

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[14..0]

M_A_BS#0 16
M_A_BS#1 16
M_A_BS#2 16

M_A_RAS# 16
M_A_CAS# 16
M_A_WE# 16

M_A_DM[7..0] 16

M_A_DQS[7..0] 16

M_A_DQS#[7..0] 16

M_A_A[14..0] 16

M_B_DQ[63..0]17

M_B_DQ[63..0]

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

U1001E

U1001E

AK47

SB_DQ_0

AH46

SB_DQ_1

AP47

SB_DQ_2

AP46

SB_DQ_3

AJ46

SB_DQ_4

AJ48

SB_DQ_5

AM48

SB_DQ_6

AP48

SB_DQ_7

AU47

SB_DQ_8

AU46

SB_DQ_9

BA48

SB_DQ_1 0

AY48

SB_DQ_1 1

AT47

SB_DQ_1 2

AR47

SB_DQ_1 3

BA47

SB_DQ_1 4

BC47

SB_DQ_1 5

BC46

SB_DQ_1 6

BC44

SB_DQ_1 7

BG43

SB_DQ_1 8

BF43

SB_DQ_1 9

BE45

SB_DQ_2 0

BC41

SB_DQ_2 1

BF40

SB_DQ_2 2

BF41

SB_DQ_2 3

BG38

SB_DQ_2 4

BF38

SB_DQ_2 5

BH35

SB_DQ_2 6

BG35

SB_DQ_2 7

BH40

SB_DQ_2 8

BG39

SB_DQ_2 9

BG34

SB_DQ_3 0

BH34

SB_DQ_3 1

BH14

SB_DQ_3 2

BG12

SB_DQ_3 3

BH11

SB_DQ_3 4

BG8

SB_DQ_3 5

BH12

SB_DQ_3 6

BF11

SB_DQ_3 7

BF8

SB_DQ_3 8

BG7

SB_DQ_3 9

BC5

SB_DQ_4 0

BC6

SB_DQ_4 1

AY3

SB_DQ_4 2

AY1

SB_DQ_4 3

BF6

SB_DQ_4 4

BF5

SB_DQ_4 5

BA1

SB_DQ_4 6

BD3

SB_DQ_4 7

AV2

SB_DQ_4 8

AU3

SB_DQ_4 9

AR3

SB_DQ_5 0

AN2

SB_DQ_5 1

AY2

SB_DQ_5 2

AV1

SB_DQ_5 3

AP3

SB_DQ_5 4

AR1

SB_DQ_5 5

AL1

SB_DQ_5 6

AL2

SB_DQ_5 7

AJ1

SB_DQ_5 8

AH1

SB_DQ_5 9

AM2

SB_DQ_6 0

AM3

SB_DQ_6 1

AH3

SB_DQ_6 2

AJ3

SB_DQ_6 3

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

5 OF 10

5 OF 10

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_W E#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_ 0
SB_DQS_ 1
SB_DQS_ 2
SB_DQS_ 3
SB_DQS_ 4
SB_DQS_ 5
SB_DQS_ 6

SB_DQS_ 7
SB_DQS# _0
SB_DQS# _1
SB_DQS# _2
SB_DQS# _3
SB_DQS# _4
SB_DQS# _5
SB_DQS# _6
SB_DQS# _7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_1 0
SB_MA_1 1
SB_MA_1 2
SB_MA_1 3
SB_MA_1 4

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW2 5
BB28
AU28
AW2 8
AT33
BD33
BB16
AW3 3
AY33
BH15
AU33

M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14

M_B_DM0

AM47

M_B_DM[7..0]

M_B_DQS[7..0]

M_B_DQS#[7..0]

M_B_A[14..0]

M_B_BS#0 17
M_B_BS#1 17
M_B_BS#2 17

M_B_RAS# 17
M_B_CAS# 17
M_B_WE# 17

M_B_DM[7..0] 17

M_B_DQS[7..0] 17

M_B_DQS#[7..0] 17

M_B_A[14..0] 17

<Core Design>

<Core Design>

A

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Cantiga-DDR(3/6)

Cantiga-DDR(3/6)

Cantiga-DDR(3/6)

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

12 59Monday, March 23, 2009

12 59Monday, March 23, 2009

12 59Monday, March 23, 2009

SB

SB

SB

5

4

3

2

1

SSID = MCH

9 OF 10

U1001I

U1001I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

VSS

AD47

VSS

AB47

VSS

Y47

VSS

T47

VSS

N47

D D

C C

B B

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

VSS

VSS

9 OF 10

U1001J

U1001J

BG21

AM36

VSS

AE36

VSS

P36

VSS

L36

VSS

J36

VSS

F36

VSS

B36

VSS

AH35

VSS

AA35

VSS

Y35

VSS

U35

VSS

T35

VSS

BF34

VSS

AM34

VSS

AJ34

VSS

AF34

VSS

AE34

VSS

W34

VSS

B34

VSS

A34

VSS

BG33

VSS

BC33

VSS

BA33

VSS

AV33

VSS

AR33

VSS

AL33

VSS

AH33

VSS

AB33

VSS

P33

VSS

L33

VSS

H33

VSS

N32

VSS

K32

VSS

F32

VSS

C32

VSS

A31

VSS

AN29

VSS

T29

VSS

N29

VSS

K29

VSS

H29

VSS

F29

VSS

A29

VSS

BG28

VSS

BD28

VSS

BA28

VSS

AV28

VSS

AT28

VSS

AR28

VSS

AJ28

VSS

AG28

VSS

AE28

VSS

AB28

VSS

Y28

VSS

P28

VSS

K28

VSS

H28

VSS

F28

VSS

C28

VSS

BF26

VSS

AH26

VSS

AF26

VSS

AB26

VSS

AA26

VSS

C26

VSS

B26

VSS

BH25

VSS

BD25

VSS

BB25

VSS

AV25

VSS

AR25

VSS

AJ25

VSS

AC25

VSS

Y25

VSS

N25

VSS

L25

VSS

J25

VSS

G25

VSS

E25

VSS

BF24

VSS

AD12

VSS

AY24

VSS

AT24

VSS

AJ24

VSS

AH24

VSS

AF24

VSS

AB24

VSS

R24

VSS

L24

VSS

K24

VSS

J24

VSS

G24

VSS

F24

VSS

E24

VSS

BH23

VSS

AG23

VSS

Y23

VSS

B23

VSS

A23

VSS

AJ6

VSS

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

R17

VSS

M17

VSS

H17

VSS

C17

VSS

BA16

VSS

AU16

VSS

AN16

VSS

N16

VSS

K16

VSS

G16

VSS

E16

VSS

BG15

VSS

AC15

VSS

W15

VSS

A15

VSS

BG14

VSS

AA14

VSS

C14

VSS

BG13

VSS

BC13

VSS

BA13

VSS

AN13

VSS

AJ13

VSS

AE13

VSS

N13

VSS

L13

VSS

G13

VSS

E13

VSS

BF12

VSS

AV12

VSS

AT12

VSS

AM12

VSS

AA12

VSS

J12

VSS

A12

VSS

BD11

VSS

BB11

VSS

AY11

VSS

AN11

VSS

AH11

VSS

Y11

VSS

N11

VSS

G11

VSS

C11

VSS

BG10

VSS

AV10

VSS

AT10

VSS

AJ10

VSS

AE10

VSS

AA10

VSS

M10

VSS

BF9

VSS

BC9

VSS

AN9

VSS

AM9

VSS

AD9

VSS

G9

VSS

B9

VSS

BH8

VSS

BB8

VSS

AV8

VSS

AT8

VSS

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

VSS

VSS

10 OF 10

10 OF 10

AH8

VSS

Y8

VSS

L8

VSS

E8

VSS

B8

VSS

AY7

VSS

AU7

VSS

AN7

VSS

AJ7

VSS

AE7

VSS

AA7

VSS

N7

VSS

J7

VSS

BG6

VSS

BD6

VSS

AV6

VSS

AT6

VSS

AM6

VSS

M6

VSS

C6

VSS

BA5

VSS

AH5

VSS

AD5

VSS

Y5

VSS

L5

VSS

J5

VSS

H5

VSS

F5

VSS

BE4

VSS

BC3

VSS

AV3

VSS

AL3

VSS

R3

VSS

P3

VSS

F3

VSS

BA2

VSS

AW2

VSS

AU2

VSS

AR2

VSS

AP2

VSS

AJ2

VSS

AH2

VSS

AF2

VSS

AE2

VSS

AD2

VSS

AC2

VSS

Y2

VSS

M2

VSS

K2

VSS

AM1

VSS

AA1

VSS

P1

VSS

H1

VSS

U24

VSS

U28

VSS

U25

VSS

U29

VSS

AF32

VSS_NCTF

AB32

VSS_NCTF

V32

VSS_NCTF

AJ30

VSS_NCTF

AM29

VSS_NCTF

AF29

VSS_NCTF

AB29

VSS_NCTF

U26

VSS_NCTF

U23

VSS_NCTF

AL20

VSS_NCTF

V20

VSS_NCTF

AC19

VSS_NCTF

AL17

VSS_NCTF

AJ17

VSS_NCTF

VSS NCTF

VSS NCTF

VSS SCB

VSS SCB

NC

NC

VSS_NCTF
VSS_NCTF

VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB

NC#E1
NC#D2
NC#C3

NC#B4

NC#A5

NC#A6

NC#A43
NC#A44
NC#B45
NC#C46
NC#D47
NC#B47
NC#A46

NC#F48
NC#E48
NC#C48
NC#B48

AA17
U17

BH48
BH1
A48
C1
A3

E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48

GMCH_GND1
GMCH_GND2
GMCH_GND3
GMCH_GND4

GM 20090316

RN1301

RN1301

1
2

PM

PM

3
4 5

SRN0J-7-GP

SRN0J-7-GP

12

TP1303TP1303

NCTF

TP1302TP1302
TP1304TP1304

PIN

TP1301TP1301

GM 20090316

8
7
6

R1302

R1302

0R2J-2-GP

0R2J-2-GP

CRT_DDC_CLK
CRT_DDC_DATA

12

R1303

R1303

0R2J-2-GP

0R2J-2-GP

L_CTRL_CLK

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

CRT_TVO_IREF

12

R1304

R1304

0R2J-2-GP

0R2J-2-GP

U1001C

U1001C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

LVDS

LVDS

TV VGA

TV VGA

3 OF 10

3 OF 10

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

PEG_CMP

T37
T36

PCIE_MRX_GTX_N0

H44

PCIE_MRX_GTX_N1

J46

PCIE_MRX_GTX_N2

L44

PCIE_MRX_GTX_N3

L40

PCIE_MRX_GTX_N4

N41

PCIE_MRX_GTX_N5

P48

PCIE_MRX_GTX_N6

N44

PCIE_MRX_GTX_N7

T43

PCIE_MRX_GTX_N8

U43

PCIE_MRX_GTX_N9

Y43

PCIE_MRX_GTX_N10

Y48

PCIE_MRX_GTX_N11

Y36

PCIE_MRX_GTX_N12

AA43

PCIE_MRX_GTX_N13

AD37

PCIE_MRX_GTX_N14

AC47

PCIE_MRX_GTX_N15

AD39

PCIE_MRX_GTX_P0

H43

PCIE_MRX_GTX_P1

J44

PCIE_MRX_GTX_P2

L43

PCIE_MRX_GTX_P3

L41

PCIE_MRX_GTX_P4

N40

PCIE_MRX_GTX_P5

P47

PCIE_MRX_GTX_P6

N43

PCIE_MRX_GTX_P7

T42

PCIE_MRX_GTX_P8

U42

PCIE_MRX_GTX_P9

Y42

PCIE_MRX_GTX_P10

W47

PCIE_MRX_GTX_P11

Y37

PCIE_MRX_GTX_P12

AA42

PCIE_MRX_GTX_P13

AD36

PCIE_MRX_GTX_P14

AC48

PCIE_MRX_GTX_P15

AD40

PCIE_MTX_GRX_C_N0

J41

PCIE_MTX_GRX_C_N1

M46

PCIE_MTX_GRX_C_N2

M47

PCIE_MTX_GRX_C_N3

M40

PCIE_MTX_GRX_C_N4

M42

PCIE_MTX_GRX_C_N5

R48

PCIE_MTX_GRX_C_N6

N38

PCIE_MTX_GRX_C_N7

T40

PCIE_MTX_GRX_C_N8

U37

PCIE_MTX_GRX_C_N9

U40

PCIE_MTX_GRX_C_N10

Y40

PCIE_MTX_GRX_C_N11

AA46

PCIE_MTX_GRX_C_N12

AA37

PCIE_MTX_GRX_C_N13

AA40

PCIE_MTX_GRX_C_N14

AD43

PCIE_MTX_GRX_C_N15

AC46

PCIE_MTX_GRX_C_P0

J42

PCIE_MTX_GRX_C_P1

L46

PCIE_MTX_GRX_C_P2

M48

PCIE_MTX_GRX_C_P3

M39

PCIE_MTX_GRX_C_P4

M43

PCIE_MTX_GRX_C_P5

R47

PCIE_MTX_GRX_C_P6

N37

PCIE_MTX_GRX_C_P7

T39

PCIE_MTX_GRX_C_P8

U36

PCIE_MTX_GRX_C_P9

U39

PCIE_MTX_GRX_C_P10

Y39

PCIE_MTX_GRX_C_P11

Y46

PCIE_MTX_GRX_C_P12

AA36

PCIE_MTX_GRX_C_P13

AA39

PCIE_MTX_GRX_C_P14

AD42

PCIE_MTX_GRX_C_P15

AD46

+VCC_PEG

1 2

for Discrete

Place R1301
close to
MCH within
500 mils.

R1301

R1301
49D9R2F-GP

49D9R2F-GP

PCIE_MRX_GTX_N[0..15]

PCIE_MRX_GTX_P[0..15]

C1302 SCD1U10V2KX-5GPC1302 SCD1U10V2KX-5GP

1 2

C1305 SCD1U10V2KX-5GPC1305 SCD1U10V2KX-5GP

1 2

C1307 SCD1U10V2KX-5GPC1307 SCD1U10V2KX-5GP

1 2

C1301 SCD1U10V2KX-5GPC1301 SCD1U10V2KX-5GP

1 2

C1310 SCD1U10V2KX-5GPC1310 SCD1U10V2KX-5GP

1 2

C1313 SCD1U10V2KX-5GPC1313 SCD1U10V2KX-5GP

1 2

C1314 SCD1U10V2KX-5GPC1314 SCD1U10V2KX-5GP

1 2

C1315 SCD1U10V2KX-5GPC1315 SCD1U10V2KX-5GP

1 2

C1317 SCD1U10V2KX-5GPC1317 SCD1U10V2KX-5GP

1 2

C1330 SCD1U10V2KX-5GPC1330 SCD1U10V2KX-5GP

1 2

C1311 SCD1U10V2KX-5GPC1311 SCD1U10V2KX-5GP

1 2

C1312 SCD1U10V2KX-5GPC1312 SCD1U10V2KX-5GP

1 2

C1316 SCD1U10V2KX-5GPC1316 SCD1U10V2KX-5GP

1 2

C1327 SCD1U10V2KX-5GPC1327 SCD1U10V2KX-5GP

1 2

C1329 SCD1U10V2KX-5GPC1329 SCD1U10V2KX-5GP

1 2

C1332 SCD1U10V2KX-5GPC1332 SCD1U10V2KX-5GP

1 2

C1303 SCD1U10V2KX-5GPC1303 SCD1U10V2KX-5GP

1 2

C1306 SCD1U10V2KX-5GPC1306 SCD1U10V2KX-5GP

1 2

C1309 SCD1U10V2KX-5GPC1309 SCD1U10V2KX-5GP

1 2

C1304 SCD1U10V2KX-5GPC1304 SCD1U10V2KX-5GP

1 2

C1308 SCD1U10V2KX-5GPC1308 SCD1U10V2KX-5GP

1 2

C1328 SCD1U10V2KX-5GPC1328 SCD1U10V2KX-5GP

1 2

C1324 SCD1U10V2KX-5GPC1324 SCD1U10V2KX-5GP

1 2

C1323 SCD1U10V2KX-5GPC1323 SCD1U10V2KX-5GP

1 2

C1325 SCD1U10V2KX-5GPC1325 SCD1U10V2KX-5GP

1 2

C1326 SCD1U10V2KX-5GPC1326 SCD1U10V2KX-5GP

1 2

C1331 SCD1U10V2KX-5GPC1331 SCD1U10V2KX-5GP

1 2

C1318 SCD1U10V2KX-5GPC1318 SCD1U10V2KX-5GP

1 2

C1319 SCD1U10V2KX-5GPC1319 SCD1U10V2KX-5GP

1 2

C1320 SCD1U10V2KX-5GPC1320 SCD1U10V2KX-5GP

1 2

C1321 SCD1U10V2KX-5GPC1321 SCD1U10V2KX-5GP

1 2

C1322 SCD1U10V2KX-5GPC1322 SCD1U10V2KX-5GP

1 2

PCIE_MRX_GTX_N[0..15] 53

PCIE_MRX_GTX_P[0..15] 53

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

PCIE_MTX_GRX_N[0..15]

PCIE_MTX_GRX_P[0..15]

PCIE_MTX_GRX_N[0..15] 53

PCIE_MTX_GRX_P[0..15] 53

A A

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

Cantiga-GND/LVDS/VGA(4/6)

Cantiga-GND/LVDS/VGA(4/6)

Cantiga-GND/LVDS/VGA(4/6)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

SB

SB

13 59Monday, March 23, 2009

13 59Monday, March 23, 2009

13 59Monday, March 23, 2009

SB

D

C

B

A

SSID = MCH

D

Close to (G)MCH

C

+1.05V_VCCP

R1401

R1401
0R3-0-U-GP

0R3-0-U-GP

1 2

GM

GM

B

R1402

R1402
0R3-0-U-GP

0R3-0-U-GP

1 2

GM

GM

G/P

G/P

A

5

12

C1412

C1412

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C1411

C1411

C1414

C1414

12

12

On the edge

12

12

C1421

C1421

C1420

C1420

G/P

G/P

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

GM 20090311

12

G/P

G/P

TP1402TP1402
TP1401TP1401

+1.8V_SUS

+1.05V_VCCP_AXG

C1416

C1416

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

VCC_AXG_SENSE
VSS_AXG_SENSE

U1001G

U1001G

AP33

VCC_SM

AN33

VCC_SM

BH32

VCC_SM

BG32

VCC_SM

BF32

VCC_SM

BD32

VCC_SM

BC32

VCC_SM

BB32

VCC_SM

BA32

VCC_SM

AY32

VCC_SM

AW3 2

VCC_SM

AV32

VCC_SM

AU32

VCC_SM

AT32

VCC_SM

AR32

VCC_SM

AP32

VCC_SM

AN32

VCC_SM

BH31

VCC_SM

BG31

VCC_SM

BF31

VCC_SM

BG30

VCC_SM

BH29

VCC_SM

BG29

VCC_SM

BF29

VCC_SM

BD29

VCC_SM

BC29

VCC_SM

BB29

VCC_SM

BA29

VCC_SM

AY29

VCC_SM

AW2 9

VCC_SM

AV29

VCC_SM

AU29

VCC_SM

AT29

VCC_SM

AR29

VCC_SM

AP29

VCC_SM

BA36

VCC_SM/N C

BB24

VCC_SM/N C

BD16

VCC_SM/N C

BB21

VCC_SM/N C

AW1 6

VCC_SM/N C

AW1 3

VCC_SM/N C

AT13

VCC_SM/N C

Y26

VCC_AXG

AE25

VCC_AXG

AB25

VCC_AXG

AA25

VCC_AXG

AE24

VCC_AXG

AC24

VCC_AXG

AA24

VCC_AXG

Y24

VCC_AXG

AE23

VCC_AXG

AC23

VCC_AXG

AB23

VCC_AXG

AA23

VCC_AXG

AJ21

VCC_AXG

AG21

VCC_AXG

AE21

VCC_AXG

AC21

VCC_AXG

AA21

VCC_AXG

Y21

VCC_AXG

AH20

VCC_AXG

AF20

VCC_AXG

AE20

VCC_AXG

AC20

VCC_AXG

AB20

VCC_AXG

AA20

VCC_AXG

T17

VCC_AXG

T16

VCC_AXG

AM15

VCC_AXG

AL15

VCC_AXG

AE15

VCC_AXG

AJ15

VCC_AXG

AH15

VCC_AXG

AG15

VCC_AXG

AF15

VCC_AXG

AB15

VCC_AXG

AA15

VCC_AXG

Y15

VCC_AXG

V15

VCC_AXG

U15

VCC_AXG

AN14

VCC_AXG

AM14

VCC_AXG

U14

VCC_AXG

T14

VCC_AXG

AJ14

VCC_AXG _SENSE

AH14

VSS_AXG _SENSE

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

4

7 OF 10

7 OF 10

VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF

POWER

POWER

VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF
VCC_AXG _NCTF

3000mA

VCC SMVCC GFX

VCC SMVCC GFX

8700mA

VCC_SM_ LF
VCC_SM_ LF
VCC_SM_ LF
VCC_SM_ LF
VCC_SM_ LF
VCC_SM_ LF
VCC_SM_ LF

VCC SM LF

VCC SM LF

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

+1.05V_VCCP_AXG

GM 20090311

SM_LF1_GMCH
SM_LF2_GMCH
SM_LF3_GMCH
SM_LF4_GMCH
SM_LF5_GMCH
SM_LF6_GMCH
SM_LF7_GMCH

G/P

G/P

12

12

C1406

C1406

C1404

C1404

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

3

+1.05V_VCCP

12

12

C1413

C1413

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

R1408

R1408
0R3-0-U-GP

0R3-0-U-GP

1 2

12

12

C1415

C1415

C1417

C1417

G/P

G/P

G/P

G/P

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

12

C1418

C1418

C1419

C1419

G/P

G/P

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

Supply Signal Group

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP 50mA

+1.5V_RUN VCCD_TVDAC 35mA

+1.8V_SUS

+1.8V_SUS 124mA

+1.5V_RUN VCCA_PEG_BG 414uA

+3.3V_RUN VCC_HV 105.3mA

12

12

C1401

C1401

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

1

1

C1409

C1409

C1407

C1407

2

2

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

12

12

C1408

C1408

SC1U10V3KX-3GP

SC1U10V3KX-3GP

+1.05V_VCCP

GM

GM

VCCA_SM

VCCA_SM_CK 26mA

VCCA_HPLL 24mA

VCCD_PEG_PLL

VCC_AXF+1.05V_VCCP

VCC_SM_CK

C1410

C1410

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C1402

C1402

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

Imax

3060mAVCC+1.05V_VCCP

852mAVTT

1782mAVCC_PEG

456mAVCC_DMI

720mA+1.05V_VCCP

139.2mAVCCA_MPLL

157.2mAVCCD_HPLL

50mAVCCA_PEG_PLL

321.35mA

3000mAVCC_SM

2

U1001F

U1001F

AG34

VCC

AC34

VCC

AB34

VCC

12

C1405

C1405

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

AA34

VCC

Y34

C1403

C1403

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33
AC33
AA33

W33

AH28
AF28
AC28
AA28

AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24

AJ23
AH23
AF23

3060mA

VCC
VCC
VCC

Y33

VCC
VCC

V33

VCC

U33

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

T32

VCC

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

VCC CORE

VCC CORE

POWER

POWER

VCC NCTF

VCC NCTF

Cantiga-Power(5/6)

Cantiga-Power(5/6)

Cantiga-Power(5/6)

Alba Discrete

Alba Discrete

Alba Discrete

1

6 OF 10

6 OF 10

+1.05V_VCCP

AM32

VCC_NCT F

AL32

VCC_NCT F

AK32

VCC_NCT F

AJ32

VCC_NCT F

AH32

VCC_NCT F

AG32

VCC_NCT F

AE32

VCC_NCT F

AC32

VCC_NCT F

AA32

VCC_NCT F

Y32

VCC_NCT F

W32

VCC_NCT F

U32

VCC_NCT F

AM30

VCC_NCT F

AL30

VCC_NCT F

AK30

VCC_NCT F

AH30

VCC_NCT F

AG30

VCC_NCT F

AF30

VCC_NCT F

AE30

VCC_NCT F

AC30

VCC_NCT F

AB30

VCC_NCT F

AA30

VCC_NCT F

Y30

VCC_NCT F

W30

VCC_NCT F

V30

VCC_NCT F

U30

VCC_NCT F

AL29

VCC_NCT F

AK29

VCC_NCT F

AJ29

VCC_NCT F

AH29

VCC_NCT F

AG29

VCC_NCT F

AE29

VCC_NCT F

AC29

VCC_NCT F

AA29

VCC_NCT F

Y29

VCC_NCT F

W29

VCC_NCT F

V29

VCC_NCT F

AL28

VCC_NCT F

AK28

VCC_NCT F

AL26

VCC_NCT F

AK26

VCC_NCT F

AK25

VCC_NCT F

AK24

VCC_NCT F

AK23

VCC_NCT F

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

14 59Monday, March 23, 2009

14 59Monday, March 23, 2009

14 59Monday, March 23, 2009

SB

SB

SB

D

D

C

B

A

C

B

A

+1.05V_VCCP

+1.05V_VCCP

+1.5V_RUN

5

L1503

L1503

1 2

BLM18PG121SN1D-GP

BLM18PG121SN1D-GP

120ohm 100MHz

L1502

L1502

1 2

BLM18PG121SN1D-GP

BLM18PG121SN1D-GP

120ohm 100MHz

L1504

L1504

1 2

BLM18BB221SN1D-GP

BLM18BB221SN1D-GP

220ohm 100MHz

L1501

L1501

1 2

BLM18PG181SN1D-GP

BLM18PG181SN1D-GP

GM 20090311

M_VCCA_HPLL

12

12

C1523

C1523

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

M_VCCA_MPLL

12

12

DY

DY

C1522

C1522

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1D05V_RUN_PEGPLL

12

12

C1535

C1535

C1531

C1531

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1D5VRUN_QDAC

12

12

C1514

C1514

C1516

C1516

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

+1.05V_VCCP

0R3-0-U-GP

0R3-0-U-GP

1 2

GM

GM

C1521

C1521

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+1.05V_VCCP

C1519

C1519

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

GM 20090316

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

R1515

R1515

+1.5V_RUN

R1501

R1501

1 2

0R3-0-U-GP

0R3-0-U-GP

+1.05V_VCCP

+1.5V_RUN

+1.05V_VCCP

12

G/P

G/P

R1512

R1512

1 2

0R2J-2-GP

0R2J-2-GP

X00 ALBA

12

DY

DY

R1504

R1504

1 2

0R3-0-U-GP

0R3-0-U-GP

R1513

R1513

1 2

DY

DY

0R2J-2-GP

0R2J-2-GP

R1508

R1508

1 2

0R3-0-U-GP

0R3-0-U-GP

4

3

2

1

SSID = MCH

+1.05V_VCCP

8 OF 10

AXF

AXF

VCC_SM_ CK
VCC_SM_ CK
VCC_SM_ CK
VCC_SM_ CK

124mA

SM CK

SM CK

VCC_TX_ LVDS

HV

HV

PEG

PEG

DMI

DMI

456mA

VTTLF

VTTLF

8 OF 10

852mA

VTT

VTT

VCC_AXF
VCC_AXF
VCC_AXF

321.35mA

VCC_HV
VCC_HV
VCC_HV

105.3mA

VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG

1782mA

VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI

VTTLF
VTTLF
VTTLF

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1

B22
B21
A21

BF21
BH20
BG20
BF20

K47

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

12

C1512

C1512

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1D05V_VCC_AXF

1D8V_VCC_SM_CK

1D05V_VCC_DMI

VTTLF1
VTTLF2
VTTLF3

1

1

2

2

12

12

12

C1505

C1505

C1502

C1502

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP

+1.05V_VCCP

12

C1534

C1534

C1518

C1518

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

1

1

C1524

C1524

C1525

C1525

2

2

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

12

C1509

C1509

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SDMK0340L-7-F-GP

SDMK0340L-7-F-GP

12

DY

DY

C1527

C1527

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C1508

C1508

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

+VCC_PEG

12

C1532

C1532

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1

1

C1501

C1501

2

2

SCD47U6D3V2KX-GP

SCD47U6D3V2KX-GP

12

12

TC1501

TC1501

EC1501

EC1501

DY

DY

SC1U10V3KX-3GP

SC1U10V3KX-3GP

ST220U2D5VBM-LGP

ST220U2D5VBM-LGP

+3.3V_RUN

R1510

D1501

D1501

12

R1503

R1503
1R3F-GP

1R3F-GP

1 2

C1510

C1510
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1 2

12

12

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

R1510

KA

10R2J-2-GP

10R2J-2-GP

+1.05V_VCCP

R1509

R1509

1 2

0R3-0-U-GP

0R3-0-U-GP

C1526

C1526
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+1.8V_SUS

R1502

R1502

1 2

0R5J-5-GP

0R5J-5-GP

C1533

C1533
SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

+VCC_PEG

R1505

R1505

1 2

0R3-0-U-GP

0R3-0-U-GP

C1517

C1517
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

Custom

Custom

Custom

12

+3.3V_RUN

+1.05V_VCCP

R1506

R1506

1 2

0R3-0-U-GP

0R3-0-U-GP

R1507

R1507

1 2

0R3-0-U-GP

0R3-0-U-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Cantiga-Power/Filter(6/6)

Cantiga-Power/Filter(6/6)

Cantiga-Power/Filter(6/6)

Alba Discrete

Alba Discrete

Alba Discrete

12

C1528

C1528
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

X01 20081215

15 59Monday, March 23, 2009

15 59Monday, March 23, 2009

15 59Monday, March 23, 2009

SB

SB

SB

U1001H

U1001H

B27

VCCA_CR T_DAC

A26

VCCA_CR T_DAC

A25

VCCA_DA C_BG

B25

VSSA_DA C_BG

+1.05V_VCCP_VCCA_DPLL

12

G/P

G/P

C1538

C1538

C1539

C1539

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

For Discrete

12

C1530

C1530
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

TC1502

TC1502

DY

DY

C1504

C1504

ST100U6D3VBM-5GP

ST100U6D3VBM-5GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

DY

DY

C1511

C1511

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

1 2

12

C1520

C1520

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

M_VCCA_HPLL

M_VCCA_MPLL

VCCA_PEG_BG

1D05V_RUN_PEGPLL

1D05V_SM

12

12

C1503

C1503

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

1D05V_SM_CK

12

12

C1513

C1513

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

VCCD_TVDAC

R1514

R1514
0R2J-2-GP

0R2J-2-GP

1D5VRUN_QDAC

1D05V_RUN_HPLL

1D05V_RUN_PEGPLL

C1529

C1529

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C1507

C1507

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

C1515

C1515

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

F47

VCCA_DP LLA

L48

VCCA_DP LLB

AD1

VCCA_HP LL

AE1

VCCA_MP LL

J48

VCCA_LV DS

J47

VSSA_LV DS

AD48

VCCA_PE G_BG

414uA

AA48

VCCA_PE G_PLL

AR20

VCCA_SM

AP20

VCCA_SM

AN20

VCCA_SM

AR17

VCCA_SM

AP17

C1506

C1506

SC1U10V3KX-3GP

SC1U10V3KX-3GP

VCCA_SM

AN17

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AP16

VCCA_SM

AP28

VCCA_SM _CK

AN28

VCCA_SM _CK

AP25

VCCA_SM _CK

AN25

VCCA_SM _CK

AN24

VCCA_SM _CK

AM28

VCCA_SM _CK_NCTF

AM26

VCCA_SM _CK_NCTF

AM25

VCCA_SM _CK_NCTF

AL25

VCCA_SM _CK_NCTF

AM24

VCCA_SM _CK_NCTF

AL24

VCCA_SM _CK_NCTF

AM23

VCCA_SM _CK_NCTF

AL23

VCCA_SM _CK_NCTF

B24

VCCA_TV _DAC

A24

VCCA_TV _DAC

A32

VCC_HDA

M25

VCCD_TV DAC

L28

VCCD_QD AC

AF1

VCCD_HP LL

AA47

VCCD_PE G_PLL

M38

VCCD_LV DS

L37

VCCD_LV DS

CANTIGA-GM-GP-U-NF

CANTIGA-GM-GP-U-NF

60.31mA

64.8mA

24mA

139.2mA

13.2mA

720mA

37.5mA

50mA

2mA

157.2mA

50mA

79mA

35mA

50mA

CRTPLLA PEGA SM

CRTPLLA PEGA SM

A LVDS

A LVDS

POWER

POWER

A CK

A CK

118.8mA

TV

TV

HDA

HDA

D TV/CRT

D TV/CRT

LVDS

LVDS

5

SSID = MEMORY

M_A_DQS#[7..0]12

D D

+1.8V_SUS

DY

DY

12

C1620

C1620

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

12

DY

DY

C1627

C1627

C1610

C1610

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C C

+0.9V_DDR_VTT

B B

A A

M_A_DQ[63..0]12

M_A_DM[7..0]12

M_A_DQS[7..0]12

M_A_A[14..0]12

Layout Note:
Place near DM1

12

DY

DY

DY

DY

12

12

12

C1616

C1616

DY

DY

DY

DY

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

12

C1630

C1630

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C1621

C1621

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

C1605

C1605

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

12

C1619

C1619

DY

DY

C1622

C1622

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_ DDR_VTT.

12

12

C1608

C1608

C1611

C1611

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

5

C1607

C1607

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

DY

DY

C1606

C1606

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

C1613

C1613

12

C1614

C1614

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

DY

DY

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

4

12

C1609

C1609

C1612

C1612

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C1618

C1618

C1617

C1617

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+V_DDR_MCH_REF

12

C1626

C1626

4

DY

DY

3

DM1

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14

M_A_BS#212

M_A_BS#012
M_A_BS#112

12

TC1601

TC1601

ST220U2D5VBM-LGP

ST220U2D5VBM-LGP

12

12

12

C1628

C1628

C1629

C1629

C1615

C1615

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

M_ODT011
M_ODT111

12

C1625

C1625

DY

DY

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

M_A_BS#2

M_A_BS#0
M_A_BS#1

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_ODT0
M_ODT1

102
101
100

105

116

107
106

123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

129
146
167
186

131
148
169
188

114
119

202

3

DM1

A0
A1
A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9
A10/AP

90

A11

89

A12
A13

86

A14

84

A15

85

A16/BA2

BA0
BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

11

/DQS0

29

/DQS1

49

/DQS2

68

/DQS3
/DQS4
/DQS5
/DQS6
/DQS7

13

DQS0

31

DQS1

51

DQS2

70

DQS3
DQS4
DQS5
DQS6
DQS7

ODT0
ODT1

1

VREF

2

VSS

GND

DDR2-200P-10-U1

DDR2-200P-10-U1

62.10017.881

62.10017.881

VDDSPD

NC#50
NC#69
NC#83

NC#120

NC#163/T EST

Height 6.5mm

/RAS

/WE

/CAS

/CS0
/CS1

CKE0
CKE1

CK0

/CK0

CK1

/CK1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SDA

SCL

SA0
SA1

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

108
109
113

110
115

79
80

30
32

164
166

10
26
52
67
130
147
170
185

195
197

199

198
200

50
69
83
120
163

81
82
87
88
95
96
103
104
111
112
117
118

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

201

M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR1
M_CLK_DDR#1

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

ICH_SMBDATA
ICH_SMBCLK

+1.8V_SUS

2

M_A_RAS# 12

M_A_WE# 12

M_A_CAS# 12

M_CS0# 11

M_CS1# 11

M_CKE0 11

M_CKE1 11

M_CLK_DDR0 11
M_CLK_DDR#0 11

M_CLK_DDR1 11
M_CLK_DDR#1 11

ICH_SMBDATA 7,17,20,43
ICH_SMBCLK 7,17,20,43

ALBA X00

PM_EXTTS#0 11

2

1

put near connector

M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1

12

RN1606

RN1606

RN1607

RN1607

12

C1623

C1623

C1604

C1604

1

DUMMY-C2

DUMMY-C2

DUMMY-C2

DUMMY-C2

M_CKE0

4

M_A_BS#2

M_A_A13

M_A_A3

8

M_A_A1

7

M_A_A10

6

M_A_BS#0

M_A_A7

1

M_A_A11

2

M_A_A14

3

M_CKE1

45

16 59Monday, March 23, 2009

16 59Monday, March 23, 2009

16 59Monday, March 23, 2009

12

C1603

C1603

DUMMY-C2

DUMMY-C2

+3.3V_RUN

12

12

DY

DY

C1602

C1602

C1601

C1601

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

Layout Note:
Place these resistors close to DM1,
all trace length Max=1.5".

+0.9V_DDR_VTT

RN1605

RN1601

Custom

Custom

Custom

RN1601

1

8

2

7

3

6

4 5

SRN56J-5-GP

SRN56J-5-GP

RN1602

RN1602

1

8

2

7

3

6

4 5

SRN56J-5-GP

SRN56J-5-GP

RN1603

RN1603

1

8

2

7

3

6

4 5

SRN56J-5-GP

SRN56J-5-GP

RN1604

RN1604

1

8

2

7

3

6

4 5

SRN56J-5-GP

SRN56J-5-GP

DDRII-SODIMM SLOT1

DDRII-SODIMM SLOT1

DDRII-SODIMM SLOT1

M_A_A5
M_A_A8
M_A_A9
M_A_A12

M_ODT0
M_CS0#
M_A_BS#1
M_A_RAS#

M_ODT1
M_CS1#
M_A_CAS#
M_A_WE#

M_A_A0
M_A_A2
M_A_A4
M_A_A6

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

RN1605

1
2 3

SRN56J-4-GP

SRN56J-4-GP

1 2

R1663 56R2J-4-GPR1663 56R2J-4-GP

1
2
3
4 5

SRN56J-5-GP

SRN56J-5-GP

8
7
6

SRN56J-5-GP

SRN56J-5-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

12

C1624

C1624

DUMMY-C2

DUMMY-C2

SB

SB

SB

5

SSID = MEMORY

M_B_DQS#[7..0]12

D D

+1.8V_SUS

C C

+0.9V_DDR_VTT

12

DY

DY

B B

A A

12

C1716

C1716

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

12

C1726

C1726

C1729

C1729

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

M_B_DQ[63..0]12

M_B_DM[7..0]12

M_B_DQS[7..0]12

M_B_A[14..0]12

Layout Note:
Place near DM2

12

12

C1707

C1707

DY

DY

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT.

12

DY

DY

C1728

C1728

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

5

12

C1712

C1712

C1711

C1711

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

12

C1725

C1725

C1727

C1727

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

12

C1710

C1710

SC1U10V3KX-3GP

SC1U10V3KX-3GP

12

C1723

C1723

C1722

C1722

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

C1714

C1714

DY

DY

C1717

C1717

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

12

C1706

C1706

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

4

M_B_BS#212

M_B_BS#012
M_B_BS#112

12

12

C1709

C1709

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

12

DY

DY

C1724

C1724

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

4

C1715

C1715

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C1713

C1713

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

+V_DDR_MCH_REF

DY

DY

12

C1705

C1705

TC1701

TC1701

ST220U2D5VBM-LGP

ST220U2D5VBM-LGP

12

DY

DY

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

12

12

C1721

C1721

C1708

C1708

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

C1730

C1730
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

M_ODT211

M_ODT311

12

C1720

C1720
SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14

M_B_BS#2

M_B_BS#0
M_B_BS#1

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_ODT2
M_ODT3

3

3

DM2

DM2

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16/BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

11

DQS0#

29

DQS1#

49

DQS2#

68

DQS3#

129

DQS4#

146

DQS5#

167

DQS6#

186

DQS7#

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

ODT0

119

ODT1

1

VREF

2

VSS

NP1

NP1

NP2

NP2

DDR2-200P-33-GP

DDR2-200P-33-GP

VDDSPD

NC#120

NC#163/TEST

Height 11mm

RAS#

WE#

CAS#

CS0#
CS1#

CKE0
CKE1

CK0

CK0#

CK1

CK1#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SDA
SCL

SA0
SA1

NC#50
NC#69
NC#83

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND
GND

108
109
113

110
115

79
80

M_CLK_DDR2

30

M_CLK_DDR#2

32

M_CLK_DDR3

164

M_CLK_DDR#3

166

M_B_DM0

10

M_B_DM1

26

M_B_DM2

52

M_B_DM3

67

M_B_DM4

130

M_B_DM5

147

M_B_DM6

170

M_B_DM7

185

ICH_SMBDATA

195
197

199

198
200

50
69
83
120
163

+1.8V_SUS

81
82
87
88
95
96
103
104
111
112
117
118

3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196

201
202

ICH_SMBCLK

ALBA X00

PM_EXTTS#1 11

2

2

M_B_RAS# 12

M_B_WE # 12

M_B_CAS# 12

M_CS2# 11

M_CS3# 11

M_CKE2 1 1

M_CKE3 1 1

M_CLK_DDR2 11
M_CLK_DDR#2 11

M_CLK_DDR3 11
M_CLK_DDR#3 11

ICH_SMBDATA 7,16,20,43
ICH_SMBCLK 7,16,20,4 3

+3.3V_RUN

1

put near connec tor

M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3

12

12

C1703

C1703

C1704

C1704

DUMMY-C2

DUMMY-C2

DUMMY-C2

DUMMY-C2

+3.3V_RUN

12

12

DY

DY

C1701

C1701

C1702

C1702

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

Layout Note:
Place these resistors close to DM2,
all trace length Max=1.5".

+0.9V_DDR_VTT

RN1701

M_B_A8
M_B_A5 M_B_A14
M_B_A1
M_B_A3

M_ODT3
M_CS3#
M_B_A0

M_B_A10
M_B_BS#0
M_B_WE #
M_B_CAS# M_B_A13

<Core Design>

<Core Design>

<Core Design>

Title

Title

Title

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

RN1701

1

8

2

7

3

6

4 5

SRN56J-5-GP

SRN56J-5-GP

RN1702

RN1702

1

8

2

7

3

6

4 5

SRN56J-5-GP

SRN56J-5-GP

RN1703

RN1703

1

8

2

7

3

6

4 5

SRN56J-5-GP

SRN56J-5-GP

DDRII-SODIMM SLOT2

DDRII-SODIMM SLOT2

DDRII-SODIMM SLOT2

Alba Discrete

Alba Discrete

Alba Discrete

RN1704

RN1704

1
2
3
4 5

SRN56J-5-GP

SRN56J-5-GP

RN1705

RN1705

1
2
3
4 5

SRN56J-5-GP

SRN56J-5-GP

RN1706

RN1706

1
2
3
4 5

SRN56J-5-GP

SRN56J-5-GP

RN1707

RN1707

1
2
3
4 5

SRN56J-5-GP

SRN56J-5-GP

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, H sin Tai Wu Rd., Hsich ih,

21F, 88, Sec.1, H sin Tai Wu Rd., Hsich ih,

21F, 88, Sec.1, H sin Tai Wu Rd., Hsich ih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

12

12

C1719

C1719

C1718

C1718

DUMMY-C2

DUMMY-C2

M_CKE3

8
7

M_B_A11

6

M_B_A6

M_B_A7

8

M_B_A4

7

M_B_A2

6

M_B_BS#1

M_B_RAS#

8

M_ODT2

7

M_CS2#

6

M_B_A12

8

M_B_BS#2

7

M_B_A9

6

M_CKE2

17 59Monday, March 23, 2009

17 59Monday, March 23, 2009

17 59Monday, March 23, 2009

DUMMY-C2

DUMMY-C2

SB

SB

SB

5

4

3

2

1

SSID = ICH

ICH_RTCX1

12

C1806

C1806

SC12P50V3JN-GP

SC12P50V3JN-GP

ICH_RTCRST#

21

G1801

G1801
GAP-OPEN

GAP-OPEN

C1808

C1808
SC1U10V3KX-3GP

SC1U10V3KX-3GP

ICH_SDIN_CODEC22

ICH_RTCX2

ICH_RTCRST#
SRTCRST#
SM_INTRUDER#

ICH_INTVRMEN
LAN100_SLP

R1821

R1821

GPIO56

1 2

DY

DY

GLAN_COMP

10KR2J-3-GP

10KR2J-3-GP

ACZ_BIT_CLK
ACZ_SYNC_R

ACZ_RST#_R

Removed

X01 20081208

ACZ_SDATAOUT_R

SATA_LED#

SATA_ITXN0_HRXN0_C
SATA_ITXP0_HRXP0_C

SATA_ITXN1_ORXN1_C
SATA_ITXP1_ORXP1_C

U1801A

U1801A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST #

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_ SLP

E25

GLAN_CL K

C13

LAN_RST SYNC

F14

LAN_RXD 0

G13

LAN_RXD 1

D14

LAN_RXD 2

D13

LAN_TXD 0

D12

LAN_TXD 1

E13

LAN_TXD 2

B10

GLAN_DO CK#/GPIO56

B28

GLAN_CO MPI

B27

GLAN_CO MPO

AF6

HDA_BIT_C LK

AH4

HDA_SYNC

AE7

HDA_RST #

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDO UT

AG7

HDA_DOC K_EN#/GPIO33

AE8

HDA_DOC K_RST#/GPIO34

AG8

SATALED #

AJ16

SATA0RX N

AH16

SATA0RX P

AF17

SATA0TX N

AG17

SATA0TX P

AH13

SATA1RX N

AJ13

SATA1RX P

AG14

SATA1TX N

AF14

SATA1TX P

ICH9M-GP-NF

ICH9M-GP-NF

1 OF 6

1 OF 6

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

IHDA

IHDA

SATA

SATA

FWH 0/LAD0
FWH 1/LAD1
FWH 2/LAD2
FWH 3/LAD3

FWH 4/LFRAME#

LDRQ0#

LDRQ1#/G PIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPW RGD

IGNNE#

INIT#

INTR

RCIN#

NMI

SMI#

STPCLK#

THRMTRIP#

PECI

SATA4RX N
SATA4RX P
SATA4TX N
SATA4TX P

SATA5RX N
SATA5RX P
SATA5TX N
SATA5TX P

SATA_CL KN
SATA_CL KP

SATARBIAS #

SATARBIAS

LPC_LAD0

K5

LPC_LAD1

K4

LPC_LAD2

L6

LPC_LAD3

K2

K3

J3
J1

N7
AJ27

H_DPRSTP#

AJ25
AE23

H_FERR#_R

AJ26

AD22

AF25

AE22
AG25
L3

AF23
AF24

AH27

H_THERMTRIP_R

AG26

AG27

Placed Within 2" from SB.

AH11
AJ11
AG12
AF12

AH9
AJ9
AE10
AF10

AH18
AJ18

SATARBIAS

AJ7
AH7

Place within 500 mils from SB.

R1812 10MR2J-L-GPR1812 10MR2J-L-GP

1 2

X1801

X1801

1

4

D D

SC12P50V3JN-GP

SC12P50V3JN-GP

X02 20090219 X02 20090219

C C

+1.5V_RUN

ICH_AZ_CODEC_BITCLK22

ICH_AZ_CODEC_SYNC22

ICH_AZ_CODEC_RST#22

ICH_SDOUT_CODEC22

X01 20081208

SATA_IRXN0_HTXN0_C44

HDD

B B

ODD

SATA_IRXP0_HTXP0_C44

SATA_ITXN0_HRXN044
SATA_ITXP0_HRXP044

SATA_IRXN1_OTXN1_C44
SATA_IRXP1_OTXP1_C44

SATA_ITXN1_ORXN144
SATA_ITXP1_ORXP144

ICH_AZ_CODEC_BITCLK

12

C1807

C1807

X-32D768KHZ-38GPU

X-32D768KHZ-38GPU

+RTC_CELL

+RTC_CELL

R1814

R1814

1 2

20KR2F-L-GP

20KR2F-L-GP

C1801

C1801

SC1U10V3KX-3GP

SC1U10V3KX-3GP

R1815

R1815

1 2

20KR2F-L-GP

20KR2F-L-GP

Place within 500 mil of SB.

R1811 24D9R2F-L-GPR1811 24D9R2F-L-GP

1 2

1 2

1 2

1 2

1 2

33R2J-2-GPR1822 33R2J-2-GPR1822

33R2J-2-GPR1823 33R2J-2-GPR1823

33R2J-2-GPR1824 33R2J-2-GPR1824

33R2J-2-GPR1825 33R2J-2-GPR1825

TP1801TP1801

23

12

12

C1802 SCD01U50V2KX-1GPC1802 SCD01U50V2KX-1GP

1 2

C1803 SCD01U50V2KX-1GPC1803 SCD01U50V2KX-1GP

1 2

C1804 SCD01U50V2KX-1GPC1804 SCD01U50V2KX-1GP

1 2

C1805 SCD01U50V2KX-1GPC1805 SCD01U50V2KX-1GP

1 2

LPC_LFRAME#

LPC_LAD3

LPC_LAD2

LPC_LAD1

LPC_LAD0

1 2

R1804 56R2J-4-GPR1804 56R2J-4-GP

1 2

R1803 54D9R2F-L1-GPR1803 54D9R2F-L1-GP

1 2

R1806 24D9R2F-L-GPR1806 24D9R2F-L-GP

LPC_LAD[0..3]

LPC_LFRAME# 26

KA20GATE 26
H_A20M# 8

H_DPRSTP# 8,11,34
H_DPSLP# 8

H_PWRGOOD 8,30

H_IGNNE# 8

H_INIT# 8
H_INTR 8

H_NMI 8
H_SMI# 8

H_STPCLK# 8

CLK_PCIE_SATA# 7
CLK_PCIE_SATA 7

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

0R2J-2-GP

H_THERMTRIP_1

R1816

DY

DY
DY

DY
DY

DY
DY

DY
DY

DY

R1816

R1817

R1817

R1818

R1818

R1819

R1819

R1820

R1820

12

12

12

12

12

LPC_LFRAME#_IN

LPC_LAD3_IN

LPC_LAD2_IN

LPC_LAD1_IN

LPC_LAD0_IN

For MINICARD debug board.

LPC_LAD[0..3] 26

+3.3V_RUN

R1810

R1810

1 2

DY

DY

10KR2J-3-GP

10KR2J-3-GP

+1.05V_VCCP

R1801

R1801

1 2

56R2J-4-GP

56R2J-4-GP

R1807

R1807

1 2

DY

DY

10KR2J-3-GP

10KR2J-3-GP

+1.05V_VCCP

R1802

R1802

1 2

56R2J-4-GP

56R2J-4-GP

1 2

R1805 0R2J-2-GPR1805 0R2J-2-GP

H_FERR# 8

+3.3V_RUN

KBRCIN# 26

H_THRMTRIP# 8,11,26,30,54

LPC_LFRAME#_IN 43

LPC_LAD3_IN 43

LPC_LAD2_IN 43

LPC_LAD1_IN 43

LPC_LAD0_IN 43

Removed

X01 20081208

12

EC1802

EC1802

DY

DY

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

Lay Out Close U1801

+RTC_CELL

R1813

R1813

330KR2F-L-GP

A A

330KR2F-L-GP

R1809

R1809

330KR2F-L-GP

330KR2F-L-GP

R1808

R1808

1MR2J-1-GP

1MR2J-1-GP

12

12

12

5

ICH_INTVRMEN

LAN100_SLP

SM_INTRUDER#

integrated VccSus1_05,VccSus1_5,VccCL1_5

INTVRMEN

High=Enable Low=Disable

integrated VccLan1_05VccCL1_05

LAN100_SLP

High=Enable Low=Disable

4

<Core Design>

<Core Design>

<Core Design>

Wistron Corporation

Wistron Corporation

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Title

Title

ICH9-LAN/HDA/SATA/LPC(1/4)

ICH9-LAN/HDA/SATA/LPC(1/4)

ICH9-LAN/HDA/SATA/LPC(1/4)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Taipei Hsien 221, Taiwan, R.O.C.

Alba Discrete

Alba Discrete

Alba Discrete

1

SB

SB

18 59Monday, March 23, 2009

18 59Monday, March 23, 2009

18 59Monday, March 23, 2009

SB