Dell 13-7370, 13-7570, 13-7373, 13-7573 Schematic
5
D D
4
3
2
1
KyloRen 13" Schematics
KabyLake-R
C C
2017-06-29
REV : -1
B B
A A
DY : None Installed
UMA: UMA only installed
OPS: DISCRTE OPTIMUS installed
5
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Cover Page
Cover Page
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Cover Page
KyloRen 13"
KyloRen 13"
KyloRen 13"
1 106
1 106
1 106
1
A00
A00
A00
5
4
3
2
1
KBL-U(R) 13" CPU 15W Block Diagram
Project code: 4PD0B5010001
PCB P/N: 16839
Revision: -1
Channel A
D D
HDMI V2.0
HDMI 2.0
57
HDMI Converter
Parade
PS175
57
DP1.2
Intel CPU
Kaby Lake U
Channel B
13.3"
eDP
Kaby Lake R
15W (UMA)
(HD/FHD)
Touch panel
M.2 SSD
55
63
SATA/PCIex2/PCIEx4(Optane)
USB3.0 Port2
USB PowerShare
C C
Power share
36
TI
TPS2544RTER
USB3.0
34
I2C
USB3.0 LANE1
USB2.0
USB2.0 LANE1
KBL PCH-LP
10 USB 2.0/1.1 ports
6 USB 3.0 ports
High Definition Audio
3 SATA ports
6 PCIE ports
LPC I/F
ACPI 5.0
USB2.0
DP
USB3.0
USB3.0 LANE4
USB2.0 LANE8
USB2.0 LANE4
1Rx16
1Rx16
MUX and Redriver
TI
TUSB546
USB2.0 x 1
I2C
DDR4
DDR4 13X16 Memory Down
CC
Cypress
CCG4
CardReader
SD 3.0
Realtak
RTS5176E
X16 Memory Down
DP/USB 3.0
38
CC1/CC2
12
USB3.0 type c
Port1
3837
SD Card Slot
Clamshell
Finger Printer
92
USB2.0 LANE9
USB2.0 x 1
PCIE LANE5
USB2.0 LANE6
PCIe
USB2.0
NGFF WLAN
IO Board
Sensor BD on
Panel side
USB 3.0
re-driver
TI
HPA02232ARGER
USB2.0
Camera (HD/IR)
D-MIC
SMBUS
HDA
CODEC
Realtek
ALC3254
USB2.0 LANE3
55
27
MIC_IN/GND
USB3.0
USB3.0 LANE3
2CH SPEAKER
(2CH 2W/4ohm)
USB3.0 Port3
I2C
68
Free fall
Gsensor
ST
LNG2DMTR
70
eSPI
USB3.0
USB2.0 x 1
USB2.0 LANE5
USB3.0 LANE3
Accelerometer
E-compass
ST
2 in 1
B B
LIS3MDL
Gyro+G
ST
LSM6DS3
eSPI debug port
HDA
Thermal
NUVOTON
NCT7718W
Fan Control
PWM
26
SMBUS
FAN DETECT
KB SCAN
INTERFACE
KBC
MICROCHIP
MEC1416
PS2
24
TPM
NUVOTON NPCT650
SPI
Flash ROM
91
16MB
Quad Read
2526
A A
FAN
5
Int.
KB
Touch PAD
Image sensor
4
I2C
HP_R/L
Universal Jack
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Block Diagram
Block Diagram
Block Diagram
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
A00
A00
2 106Thursday, June 29, 2017
2 106Thursday, June 29, 2017
2 106Thursday, June 29, 2017
A00
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
C
C
C
(Reserved)
(Reserved)
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
A00
A00
3 106Thursday, June 29, 2017
3 106Thursday, June 29, 2017
1
3 106Thursday, June 29, 2017
A00
5
4
3
2
1
SSID = CPU
+VCCST_CPU
12
R419
1KR2J-1-GP
+VCCSTG
D D
[PECI] and [PROCHOT#]
Impedance control: 50 ohm
PECI24
H_PROCHOT#24,44,46
TOUCH_PANEL_INTR#55
3D3V_S5_PCH
C C
R404
1 2
DY
100KR2J-1-GP
12
Rb
+VCCSTG = 1.0 V +VCCSTG = 1.0 V
PCH_THERMTRIP#
12
R401
1KR2J-1-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TOUCH_PANEL_PD#55
1 2
R403499R2F-2-GP
Ra
TPAD14-OP-GP
XDP_BPM099
XDP_BPM199
TP403
TOUCH_PAD_INTR#
TP401
TPAD14-OP-GP
TP402
TP407
TP408
1
R41249D9R2F-GP
R41349D9R2F-GP
R41449D9R2F-GP
R41549D9R2F-GP
H_CATERR#
1
H_PROCHOT#_R
PCH_THERMTRIP#
1
SKTOCC#
XDP_BPM2
1
XDP_BPM3
1
GPP_E3/CPU_GP0
CPU_POPIRCOMP
12
PCH_POPIRCOMP
12
EDRAM_OPIO_RCOMP
12
EOPIO_RCOMP
12
CPU1D
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
SKYLAKE-U-GP
SKYLAKE_ULT
CPU MISC
4 OF 20
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
XDP_TCK_JTAGX
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
XDP_TRST#
EC401
DY
AZ5725-01FDR7G-GP
20160812 EMI
PCH_JTAG_TCK 99
PCH_JTAG_TDI 99
PCH_JTAG_TDO 99
PCH_JTAG_TMS 99
XDP_TRST# 99
XDP_TCK_JTAGX 99
#544669 CRB Rev0.52
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
XDP_TCK_JTAGX
XDP_TRST#
PCH_JTAG_TCK
1 2
XDP
1 2
100R2F-L1-GP-U
R417 51R2J-2-GP
R402 51R2J-2-GP
R407 51R2J-2-GP
XDP
1 2
XDP
1 2
XDP
1 2
DY
1 2
DY
+VCCSTG
R40851R2J-2-GP
R409
R41651R2J-2-GP
071.SKYLA.000U
R410
TP_WAKE_KBC#24,65
1 2
0R0402-PAD
2016/12/28
(#543016) PROCHOT# Routing Guidelines
B B
M1,2,3,4,5: <3 inches
M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(JTAG/CPU SIDE BAND)
CPU_(JTAG/CPU SIDE BAND)
CPU_(JTAG/CPU SIDE BAND)
KyloRen 13"
KyloRen 13"
KyloRen 13"
4 106Thursday, June 29, 2017
4 106Thursday, June 29, 2017
4 106Thursday, June 29, 2017
1
A00
A00
A00
SSID = CPU
5
4
3
2
1
DDR4 ball type: Non-Interleaved Type
D D
M_A_DQ012
M_A_DQ112
M_A_DQ212
M_A_DQ[0:7]
M_A_DQ[8:15]
M_A_DQ[16:23]
M_A_DQ[24:31]
C C
M_A_DQ[32:39]
M_A_DQ[40:47]
M_A_DQ[48:55]
M_A_DQ[56:63]
DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
B B
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential
clock pair to clock pair swapping within a channel is not allowed.
M_A_DQ312
M_A_DQ412
M_A_DQ512
M_A_DQ612
M_A_DQ712
M_A_DQ812
M_A_DQ912
M_A_DQ1012
M_A_DQ1112
M_A_DQ1212
M_A_DQ1312
M_A_DQ1412
M_A_DQ1512
M_A_DQ1612
M_A_DQ1712
M_A_DQ1812
M_A_DQ1912
M_A_DQ2012
M_A_DQ2112
M_A_DQ2212
M_A_DQ2312
M_A_DQ2412
M_A_DQ2512
M_A_DQ2612
M_A_DQ2712
M_A_DQ2812
M_A_DQ2912
M_A_DQ3012
M_A_DQ3112
M_A_DQ3212
M_A_DQ3312
M_A_DQ3412
M_A_DQ3512
M_A_DQ3612
M_A_DQ3712
M_A_DQ3812
M_A_DQ3912
M_A_DQ4012
M_A_DQ4112
M_A_DQ4212
M_A_DQ4312
M_A_DQ4412
M_A_DQ4512
M_A_DQ4612
M_A_DQ4712
M_A_DQ4812
M_A_DQ4912
M_A_DQ5012
M_A_DQ5112
M_A_DQ5212
M_A_DQ5312
M_A_DQ5412
M_A_DQ5512
M_A_DQ5612
M_A_DQ5712
M_A_DQ5812
M_A_DQ5912
M_A_DQ6012
M_A_DQ6112
M_A_DQ6212
M_A_DQ6312
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
CPU1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[8]
AF64
DDR1_DQ[1]/DDR0_DQ[9]
AK65
DDR1_DQ[2]/DDR0_DQ[10]
AK64
DDR1_DQ[3]/DDR0_DQ[11]
AF66
DDR1_DQ[4]/DDR0_DQ[12]
AF67
DDR1_DQ[5]/DDR0_DQ[13]
AK67
DDR1_DQ[6]/DDR0_DQ[14]
AK66
DDR1_DQ[7]/DDR0_DQ[15]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
SKYLAKE-U-GP
SKYLAKE_ULT
DDR0_DQ[16]
DDR0_DQ[17]
DDR0_DQ[18]
DDR0_DQ[19]
DDR0_DQ[20]
DDR0_DQ[21]
DDR0_DQ[22]
DDR0_DQ[23]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
071.SKYLA.000U
2 OF 20
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR1_DQSN[0]/DDR0_DQ[2]
DDR1_DQSP[0]/DDR0_DQ[2]
DDR1_DQSN[1]/DDR0_DQ[3]
DDR1_DQSP[1]/DDR0_DQ[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60
AW50
AT52
AY67
AY68
BA67
AW67
M_A_A5
M_A_A9
M_A_A6
M_A_A8
M_A_A7
M_A_A12
M_A_A11
M_A_A13
M_A_A15
M_A_A14
M_A_A16
M_A_A2
M_A_A10
M_A_A1
M_A_A0
M_A_A3
M_A_A4
M_A_DQS_DN0
M_A_DQS_DP0
M_A_DQS_DN1
M_A_DQS_DP1
M_A_DQS_DN2
M_A_DQS_DP2
M_A_DQS_DN3
M_A_DQS_DP3
M_A_DQS_DN4
M_A_DQS_DP4
M_A_DQS_DN5
M_A_DQS_DP5
M_A_DQS_DN6
M_A_DQS_DP6
M_A_DQS_DN7
M_A_DQS_DP7
SM_PGCNTL
M_A_CLK#0 12
M_A_CLK0 12
M_A_CKE0 12
M_A_CS#0 12
M_A_DIMA_ODT0 12
M_A_A5 12
M_A_A9 12
M_A_A6 12
M_A_A8 12
M_A_A7 12
M_A_BG0 12
M_A_A12 12
M_A_A11 12
M_A_ACT_N 12
M_A_BG1 12
M_A_A13 12
M_A_A15 12
M_A_A14 12
M_A_A16 12
M_A_BA0 12
M_A_A2 12
M_A_BA1 12
M_A_A10 12
M_A_A1 12
M_A_A0 12
M_A_A3 12
M_A_A4 12
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_ALERT_N 12
M_A_PARITY 12
V_SM_VREF_CNTA 12
V_SM_VREF_CNTB 13
CPU1C
M_B_DQ013
M_B_DQ113
M_B_DQ213
M_B_DQ313
M_B_DQ413
M_B_DQ513
M_B_DQ613
M_B_DQ713
M_B_DQ813
M_B_DQ913
M_B_DQ1013
M_B_DQ1113
M_B_DQ1213
M_B_DQ1313
M_B_DQ1413
M_B_DQ1513
M_B_DQ1613
M_B_DQ1713
M_B_DQ1813
M_B_DQ1913
M_B_DQ2013
M_B_DQ2113
M_B_DQ2213
M_B_DQ2313
M_B_DQ2413
M_B_DQ2513
M_B_DQ2613
M_B_DQ2713
M_B_DQ2813
M_B_DQ2913
M_B_DQ3013
M_B_DQ3113
M_B_DQ3213
M_B_DQ3313
M_B_DQ3413
M_B_DQ3513
M_B_DQ3613
M_B_DQ3713
M_B_DQ3813
M_B_DQ3913
M_B_DQ4013
M_B_DQ4113
M_B_DQ4213
M_B_DQ4313
M_B_DQ4413
M_B_DQ4513
M_B_DQ4613
M_B_DQ4713
M_B_DQ4813
M_B_DQ4913
M_B_DQ5013
M_B_DQ5113
M_B_DQ5213
M_B_DQ5313
M_B_DQ5413
M_B_DQ5513
M_B_DQ5613
M_B_DQ5713
M_B_DQ5813
M_B_DQ5913
M_B_DQ6013
M_B_DQ6113
M_B_DQ6213
M_B_DQ6313
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKYLAKE-U-GP
SKYLAKE_ULT
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR CH - B
071.SKYLA.000U
Design Guideline:
1D2V_S3 3D3V_S0
12
G
R506
220KR2F-GP
SM_RCOMP keep routing length less than 500 mils.
3 OF 20
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7
M_B_A12
M_B_A11
M_B_ACT_N
M_B_A13
M_B_A15
M_B_A14
M_B_A16
M_B_A2
M_B_A10
M_B_A1
M_B_A0
M_B_A3
M_B_A4
M_B_DQS_DN0
M_B_DQS_DP0
M_B_DQS_DN1
M_B_DQS_DP1
M_B_DQS_DN2
M_B_DQS_DP2
M_B_DQS_DN3
M_B_DQS_DP3
M_B_DQS_DN4
M_B_DQS_DP4
M_B_DQS_DN5
M_B_DQS_DP5
M_B_DQS_DN6
M_B_DQS_DP6
M_B_DQS_DN7
M_B_DQS_DP7
SM_DRAMRST#
SM_RCOMP_0
SM_RCOMP_0
SM_RCOMP_1
#543016
SM_RCOMP_2
M_B_CLK#0 13
M_B_CLK0 13
M_B_CKE0 13
M_B_CS#0 13
M_B_DIMB_ODT0 13
M_B_A5 13
M_B_A9 13
M_B_A6 13
M_B_A8 13
M_B_A7 13
M_B_BG0 13
M_B_A12 13
M_B_A11 13
M_B_ACT_N 13
M_B_BG1 13
M_B_A13 13
M_B_A15 13
M_B_A14 13
M_B_A16 13
M_B_BA0 13
M_B_A2 13
M_B_BA1 13
M_B_A10 13
M_B_A1 13
M_B_A0 13
M_B_A3 13
M_B_A4 13
M_B_ALERT_N 13
M_B_PARITY 13
R501
1 2
1 2
1 2
1 2
121R2F-GP
DDP
200R2F-L-GP
R507
SDP
R502 80D6R2F-L-GP
R503 100R2F-L1-GP-U
DDP R501:121
SDP R507:200
2016/11/28
Layout Note:
1D2V_S3
12
R505
470R2F-GP
1 2
R504
0R0402-PAD
DDR4_DRAMRST# 12,13
12
C501
SCD1U25V2KX-1-DL-GP
SM_PGCNTL
Q501
DMN5L06K-7-GP
DS
SM_PGCNTL_R 51
2015/11/18 Modify
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
A A
5
4
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
M_A_DQS_DN[7:0] 12
M_A_DQS_DP[7:0] 12
3
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
M_B_DQS_DN[7:0] 13
M_B_DQS_DP[7:0] 13
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(DDR)
CPU_(DDR)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(DDR)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
5 106Thursday, June 29, 2017
5 106Thursday, June 29, 2017
5 106Thursday, June 29, 2017
A00
A00
A00
SSID = CPU
5
4
3
2
1
CPU1S
D D
C C
PCH strap pin:
CFG3
DY
CFG[19:0]99
12
R604
1KR2J-1-GP
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
12
R60149D9R2F-GP
ITP_PMODE99
RSVD_TP_BA70
1
1
TP601TPAD14-OP-GP
TP602TPAD14-OP-GP
RSVD_F65
1
RSVD_G65
1
TP612TPAD14-OP-GP
TP613TPAD14-OP-GP
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
AY2
AY1
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
F65
G65
F61
E61
E8
D1
D3
J71
J68
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKYLAKE-U-GP
071.SKYLA.000U
[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
CFG[3]
0 : ENABLED
SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
RESERVED SIGNALS-1
SKYLAKE_ULT
RSVD_TP_AW71
RSVD_TP_AW70
19 OF 20
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
TP5
TP6
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
TP4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
TP1
TP2
VSS_AY71
ZVM#
RSVD_AW71
RSVD_AW70
MSM#
PROC_SELECT#
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
TP5_AU5
TP6_AT5
TP4_BB5
TP1_AY4
TP2_BB3RSVD_TP_BA68
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
1
1
1
1
1
1
1
1
1
1 2
R602 0R0402-PAD
1
1
1
1
1 2
R603
100KR2J-1-GP
2016/01/11 modify
TP603 TPAD14-OP-GP
TP604 TPAD14-OP-GP
TP605 TPAD14-OP-GP
TP606 TPAD14-OP-GP
TP607 TPAD14-OP-GP
TP608 TPAD14-OP-GP
TP609 TPAD14-OP-GP
TP610 TPAD14-OP-GP
TP611 TPAD14-OP-GP
TP618
TPAD14-OP-GP
TP614 TPAD14-OP-GP
TP615 TPAD14-OP-GP
TP617 TPAD14-OP-GP
DY
#54469 CRB.
+VCCST_CPU
1 : DISABLED
CFG4
B B
12
R605
1KR2J-1-GP
(#543016)
DISPLAY PORT PRESENCE STRAP
CFG[4]
0 : ENABLED
An external Display Port device is connected to the Embedded Display Port.
1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.
SKL(#543016):
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(RESERVED)
CPU_(RESERVED)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
CPU_(RESERVED)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
6 106Thursday, June 29, 2017
6 106Thursday, June 29, 2017
6 106Thursday, June 29, 2017
A00
A00
A00
SSID = CPU
5
4
3
2
1
A48
A53
A58
A62
A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
U42
R736
1 2
D0002R5J-GP- U
U42
R743
1 2
D0002R5J-GP- U
CPU1M
CPU POWER 2 OF 4
VCCGT
SKYLAKE_ULT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
SKYLAKE-U-GP
071.SKYLA.000U
13 OF 20
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
U22
R742
1 2
D0002R5J-GP- U
+VCCGT
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
For U42 only
AU63
BB57
BB66
AK62
AL61
GTX_CORE
GTX_CORE
GTX_CORE
SC10U6D3V3MX- DL-GP
#544669 CRB.
+VDDQ_CPU _CLK1D2V_S3
R705
1 2
0R0805-PAD
2016/02/16 modify
2017/01/18
DY
2017/06/28
VCC_CORE
+VCCGT
1D2V_S3
DY
12
12
12
12
12
12
12
12
12
C719
SC1U10V2KX-1D LGP
+VDDQ_CPU _CLK
C715
+VCCST_CP U
C716SC1U10V2KX-1D LGP
+VCCSTG
C717SC1U10V2KX-1D LGP
1D2V_S3
C718SC1U10V2KX-1D LGP
+VCCSFR
C720
SCD1U25V2KX-1-DL-GP
1 2
R719
100R2F-L1-GP- U
R720
100R2F-L1-GP- U
R721
100R2F-L1-GP- U
R722
100R2F-L1-GP- U
CPU1N
CPU POWER 3 OF 4
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
0.04 A
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
0.12 A
12
C721
SC1U10V2KX-1DLGP
SKYLAKE-U-GP
071.SKYLA.000U
VCC_SENSE 7,46
VSS_SENSE 7,46
Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil
VCCGT_SEN SE 7,46
VSSGT_SENSE 7,46
SKYLAKE_ULT
14 OF 20
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
VCCSA_SENS E
VSSSA_SENSE
+VCCIO
+VCCIO(ICCMAX.=2.73A
+VCCSA
+VCCSA
12
R735
100R2F-L1-GP- U
12
R734
100R2F-L1-GP- U
VSSSA_SENSE 46
VCCSA_SENS E 46
AM32
AM33
AM35
AM37
AM38
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AK32
AB62
AC63
AE63
AE62
AG62
AL63
AJ62
A30
A34
A39
A44
G30
K32
P62
V62
H63
G61
CPU1L
VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
VCCG0
RSVD_AK32
VCCG1
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
SKYLAKE-U-GP
CPU POWER 1 OF 4
SKYLAKE_ULT
VCC_CORE VCC_CORE
D D
1
+VCCCOR EG0
TP701TPAD14-OP-GP
1
+VCCCOR EG1
TP707TPAD14-OP-GP
3A
+V_EDRAM_VR
140mA
+V1.8S_EDRAM
SEN_EDRAM
3A
+V_EOPIO_VR
SEN_EOPIO
12 OF 20
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
H_CPU_SVIDALR T#
H_CPU_SVIDC LK
H_CPU_SVIDD AT
+VCCFUSE PRG
VCC_SENSE 7,46
VSS_SENSE 7,46
1 2
R703
0R0603-PAD
+VCCGT
1 2
R738
DY
0R2J-2-GP
+VCCSTG
U22_POWER _K52
For U22 & U42
GT_CORE
+VCCGT
GT_CORE
+VCCGT
GT_CORE
+VCCGT
071.SKYLA.000U
VCCGT_SEN SE7,46
VSSGT_SENSE7,46
VCC_CORE GT_CORE +VCCGT
C C
VCC_CORE GTX_CORE
Layout Note:
SVID_543016:
B B
CLOSE TO CPU
H_CPU_SVIDD AT
+VCCST_CP U
12
R726
100R2F-L1-GP- U
SVID CLOCK
H_CPU_SVIDC LK
A A
SVID DATA
H_CPU_SVIDALR T#
5
R728
220R2J-L2-GP
4
The total Length of Data and Clock (from CPU to each VR) must be equal (Ā±0.1 inch).
Route the Alert signal between the Clock and the Data signals.
#544669
1 2
12
R709
0R0402-PAD
1 2
R732
0R0402-PAD
+VCCST_CP U
12
R727
56R2J-4-GP
+VCCST_CP U
12
DY
#544669
CLOSE TO CPU
R723
54D9R2F-L1-G P
VR_SVID_ALERT# 46
VR_SVID_DATA 46
#544669
CLOSE TO VR
VR_SVID_CLK 46
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
1
Taipei Hsie n 221, Taiwan, R.O. C.
CPU(VCC_CORE)
CPU(VCC_CORE)
CPU(VCC_CORE)
KyloRen 13"
KyloRen 13"
KyloRen 13"
7 106
7 106
7 106
A00
A00
A00
5
4
3
2
1
SSID = CPU
D D
CPU1A
DP_DATA0_N57
DP_DATA0_P57
DP_DATA1_N57
DP_DATA1_P57
DP to HDMI2.0
DP for Type-C Mux
2016/11/01modify
3D3V_S0
C C
3D3V_S0
SRN2K2J-1-GP
1
2 3
RN801
RN803
2 3
1
SRN2K2J-1-GP
CPU_DP1_CTRL_DATA
4
CPU_DP1_CTRL_CLK
CPU_DP2_CTRL_DATA
CPU_DP2_CTRL_CLK
4
DP to HDMI2.0 DP to HDMI2.0
+VCCIO
R801
1 2
24D9R2F-L-GP
DP_DATA2_N57
DP_DATA2_P57
DP_DATA3_N57
DP_DATA3_P57
PCH_DPC_N038
PCH_DPC_P038
PCH_DPC_N138
PCH_DPC_P138
PCH_DPC_N238
PCH_DPC_P238
PCH_DPC_N338
PCH_DPC_P338
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK SIO_EXT_SMI#
CPU_DP2_CTRL_DATA
2016/11/07
EDP_COMP
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKYLAKE-U-GP
071.SKYLA.000U
(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.
SKYLAKE_ULT
DDI
DISPLAY SIDEBANDS
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
1 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
EDP_DISP_UTIL
CPU_DP2_HPD
EDP_TX0_DN 55
EDP_TX0_DP 55
EDP_TX1_DN 55
EDP_TX1_DP 55
EDP_TX2_DN 55
EDP_TX2_DP 55
EDP_TX3_DN 55
EDP_TX3_DP 55
EDP_AUX_DN 55
EDP_AUX_DP 55
1
TP801 TPAD14-OP-GP
HDMI_AUXN 57
HDMI_AUXP 57
DPB_AUXN 38
DPB_AUXP 38
CPU_DP1_HPD 57
EDP_HPD 55
L_BKLT_CTRL 55
EDP_VDD_EN 55
2016/11/01modify
for HDMI2.0
for Type-C Mux
L_BKLT_EN 24
2016/11/07
(#543016) eDP_RCOMP Guideline
Signal Trace
Width
eDP_RCOMP 20 mils 25 mils 24.9 Ī© Ā±1%
B B
Isolation
Spacing
Resistor
Value
Length
Max = 100 mils
(#543016) DDI Disabling and Termination Guidelines
Touch_panel _Resert Remove
3D3V_S0
CPU_DP2_HPD
TypeC
1 2
R804
1 2
0R0402-PAD
2016/12/28
R803
100KR2J-1-GP
CPU_DP_HPD_R 37,38
DP for Type-C Mux
Port Strap Enable Port Disable Port
Port 1
Port 2
A A
DDPB_CTRLDATA
DDPC_CTRLDATA
PU to 3.3 V with 2.2-k
Ā±5% resistor
PU to 3.3 V with 2.2-k
Ā±5% resistor
NC
NC
SIO_EXT_SMI#
1 2
R802 10KR2J-3-GP
<Core Design>
<Core Design>
<Core Design>
Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 Ā±1% Ī© resistor.
5
4
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(DISPLAY)
CPU_(DISPLAY)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
CPU_(DISPLAY)
KyloRen 13"
KyloRen 13"
KyloRen 13"
8 106Thursday, June 29, 2017
8 106Thursday, June 29, 2017
8 106Thursday, June 29, 2017
1
A00
A00
A00
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
(Reserved)
(Reserved)
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
9 106Thursday, June 29, 2017
9 106Thursday, June 29, 2017
9 106Thursday, June 29, 2017
1
A00
A00
A00
A00
A00
A00
10 106Thursday, June 29, 2017
10 106Thursday, June 29, 2017
10 106Thursday, June 29, 2017
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
<Core Design>
<Core Design>
<Core Design>
2
Title
Title
Title
1
KyloRen 13"
KyloRen 13"
KyloRen 13"
CPU_(Power CAP1)
CPU_(Power CAP1)
CPU_(Power CAP1)
A2
A2
A2
Size Document Number Rev
Date: Sheet of
Size Document Number Rev
Date: Sheet of
Size Document Number Rev
Date: Sheet of
2
SC10U6D3V2MX-2-GP
PC1083
12
3
U42
SC10U6D3V2MX-2-GP
PC1082
12
U42
SC10U6D3V2MX-2-GP
PC1081
12
U42
SC10U6D3V2MX-2-GP
PC1080
12
U42
SC10U6D3V2MX-2-GP
PC1035
12
U42
SC10U6D3V2MX-2-GP
PC1079
12
U42
SC10U6D3V2MX-2-GP
PC1033
12
U42
SC10U6D3V2MX-2-GP
PC1093
12
U42
SC10U6D3V2MX-2-GP
PC1092
12
U42
SC10U6D3V2MX-2-GP
PC1091
12
U42
SC10U6D3V2MX-2-GP
PC1090
12
U42
SC10U6D3V2MX-2-GP
PC1086
12
U42
SC10U6D3V2MX-2-GP
PC1085
12
U42
SC10U6D3V2MX-2-GP
PC1084
12
U42
3
2016/11/7modify
VCC_CORE
SC10U6D3V2MX-2-GP
PC1087
12
4
2017/01/182017/01/18
2017/04/26
5
22U 0603 x 30
U-line 22 15W
IccMax current-10ms max = 31 A
VCC_CORE
10U 0402 x 2 (2DY)
DY
SC10U6D3V2MX-2-GP
PC1032
12
DY
SC10U6D3V3MX-DL-GP
PC1020
12
DY
SC10U6D3V3MX-DL-GP
PC1017
12
DY
SC22U6D3V3MX-1-DL-GP
PC1011
12
SC22U6D3V3MX-1-DL-GP
PC1010
12
SC22U6D3V3MX-1-DL-GP
PC1009
12
SC22U6D3V3MX-1-DL-GP
PC1008
12
SC22U6D3V3MX-1-DL-GP
PC1007
12
SC22U6D3V3MX-1-DL-GP
PC1006
DY
12
SC22U6D3V3MX-1-DL-GP
PC1005
12
SC22U6D3V3MX-1-DL-GP
PC1004
12
SC22U6D3V3MX-1-DL-GP
PC1003
12
SC22U6D3V3MX-1-DL-GP
PC1002
12
DY
2017/04/26
SC22U6D3V3MX-1-DL-GP
PC1023
12
SC22U6D3V3MX-1-DL-GP
PC1022
12
SC22U6D3V3MX-1-DL-GP
PC1021
12
SC22U6D3V3MX-1-DL-GP
PC1019
12
SC22U6D3V3MX-1-DL-GP
PC1018
12
SC22U6D3V3MX-1-DL-GP
PC1016
12
SC22U6D3V3MX-1-DL-GP
PC1015
12
SC22U6D3V3MX-1-DL-GP
PC1014
2017/04/26
12
SC22U6D3V3MX-1-DL-GP
PC1013
12
SC22U6D3V3MX-1-DL-GP
PC1012
12
4
SC22U6D3V3MX-1-DL-GP
PC1001
SC22U6D3V3MX-1-DL-GP
PC1070
12
U42
SC22U6D3V3MX-1-DL-GP
PC1069
12
2017/04/26
SC22U6D3V3MX-1-DL-GP
PC1036
DY
DY
DY
12
SC22U6D3V3MX-1-DL-GP
PC1034
DY
12
SC22U6D3V3MX-1-DL-GP
PC1031
12
SC22U6D3V3MX-1-DL-GP
PC1030
12
SC22U6D3V3MX-1-DL-GP
PC1029
12
DY
SC22U6D3V3MX-1-DL-GP
PC1028
12
SC22U6D3V3MX-1-DL-GP
PC1027
12
SC22U6D3V3MX-1-DL-GP
PC1026
DY
12
SC22U6D3V3MX-1-DL-GP
PC1025
12
SC22U6D3V3MX-1-DL-GP
PC1024
12
VCCGT
22U 0603 x 30 (3 DY)
U-line 22 15W
IccMax current-10ms max[A] = 64 A
U42
SC22U6D3V3MX-1-DL-GP
PC1046
12
SC22U6D3V3MX-1-DL-GP
PC1045
12
SC22U6D3V3MX-1-DL-GP
PC1044
12
SC22U6D3V3MX-1-DL-GP
PC1043
12
SC22U6D3V3MX-1-DL-GP
PC1042
12
SC22U6D3V3MX-1-DL-GP
PC1041
12
SC22U6D3V3MX-1-DL-GP
PC1040
12
SC22U6D3V3MX-1-DL-GP
PC1039
12
SC22U6D3V3MX-1-DL-GP
PC1038
12
SC22U6D3V3MX-1-DL-GP
PC1037
12
SC22U6D3V3MX-1-DL-GP
PC1056
12
SC22U6D3V3MX-1-DL-GP
PC1055
12
SC22U6D3V3MX-1-DL-GP
PC1054
12
SC22U6D3V3MX-1-DL-GP
PC1053
12
SC22U6D3V3MX-1-DL-GP
PC1052
12
SC22U6D3V3MX-1-DL-GP
PC1051
12
SC22U6D3V3MX-1-DL-GP
PC1050
12
SC22U6D3V3MX-1-DL-GP
PC1049
12
SC22U6D3V3MX-1-DL-GP
PC1048
12
SC22U6D3V3MX-1-DL-GP
PC1047
12
12
DY
SC22U6D3V3MX-1-DL-GP
PC1068
12
DY
SC22U6D3V3MX-1-DL-GP
PC1067
12
DY
SC22U6D3V3MX-1-DL-GP
PC1066
12
SC22U6D3V3MX-1-DL-GP
PC1065
12
SC22U6D3V3MX-1-DL-GP
PC1064
12
SC22U6D3V3MX-1-DL-GP
PC1063
12
SC22U6D3V3MX-1-DL-GP
PC1062
12
SC22U6D3V3MX-1-DL-GP
PC1061
12
SC22U6D3V3MX-1-DL-GP
PC1060
12
SC22U6D3V3MX-1-DL-GP
PC1059
12
SC22U6D3V3MX-1-DL-GP
PC1058
12
SC22U6D3V3MX-1-DL-GP
PC1057
12
VCCSA
SC22U6D3V3MX-1-DL-GP
PC1078
12
DY
SC22U6D3V3MX-1-DL-GP
PC1077
12
SC22U6D3V3MX-1-DL-GP
PC1076
12
SC22U6D3V3MX-1-DL-GP
PC1075
12
DY
SC22U6D3V3MX-1-DL-GP
PC1074
12
DY
SC22U6D3V3MX-1-DL-GP
PC1073
12
SC22U6D3V3MX-1-DL-GP
PC1072
12
SC22U6D3V3MX-1-DL-GP
PC1071
12
5
22U 0603 x 5 (3DY)
SSID = CPU
VCC_CORE
D D
C C
+VCCGT
B B
+VCCSA
A A
SSID = CPU
5
4
3
2
1
PCH DERIVED RAILS
1D0V_S5
D D
2017/05/08
UNSLICED GT
+VCCGT
VCCIO
+VCCIO
+VCCIO(ICCMAX.=2.73A)
1 2
R1101
0R1206-PAD
1 2
R1102
0R0603-PAD
+VCCPRIM_CORE
+V1.00A_SIP
C1112
SC22U6D3V3MX-1-GP
12
12
12
C1103
C1102
DY
DY
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
Dummy : 20150123 Dummy : 20150123
12
C1104
DY
SC1U10V2KX-1DLGP
12
C1105
SC1U10V2KX-1DLGP
12
C1106
DY
SC1U10V2KX-1DLGP
12
C1107
1U 0402 x 6
SC1U10V2KX-1DLGP
DY
12
C1108
SC1U10V2KX-1DLGP
12
C1109
SC1U10V2KX-1DLGP
12
C1110
SC1U10V2KX-1DLGP
12
C1111
SC1U10V2KX-1DLGP
DY
3D3V_S5_PCH +V3.3A_SIP
1 2
C C
R1103
0R0603-PAD
C1113
SC22U6D3V3MX-1-GP
12
+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)
DY
Layout Note:
+V1.8A +V1.8A_SIP
R1104
12
0R0603-PAD
12
DY
+VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP
C1117
C1115
DY
SC22U6D3V3MX-1-GP
12
C1116
SC1U10V2KX-1DLGP
12
C1114
SC1U10V2KX-1DLGP
12
C1122
SC22U6D3V3MX-1-GP
SC1U10V2KX-1DLGP
12
C1118
12
DY
C1119
SC22U6D3V3MX-1-GP
SC1U10V2KX-1DLGP
12
SC10U6D3V3MX-DL-GP
C1120
12
C1121
SC1U10V2KX-1DLGP
12
DY
1uF:
C1174 near N15
C1180 near K15
C1173 near AF20
C1172 near N18
C1175 near AB19
22uF :
C1182 C1184 near N15
10uF:
C1176 near N15
+VCCIO
+VCCPRIM_CORE
+VCCIO(ICCMAX.=2.73A)
C1134
C1133
12
SC22U6D3V3MX-1-DL-GP
B B
12
C1135
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
12
C1128
12
C1129
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
12
1D2V_S3
DY
12
C1130
12
12
12
C1139SCD1U25V2KX-1-DL-GP
C1140SCD1U25V2KX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
EC1102
SC2D2U6D3V2MX-DL-GP
12
12
12
DY
C1141SCD1U25V2KX-1-DL-GP
EC1103
SC2D2U6D3V2MX-DL-GP
C1142SCD1U25V2KX-1-DL-GP
12
DY
VCC_CORE
2017/01/17
1U 0402 x 5
+V3.3A_SIP
SC10U6D3V3MX-DL-GP
C1123
12
C1132
12
12
C1137
C1138
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
C1131
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
12
DY
C1136
SC10U6D3V3MX-DL-GP
DY
12
DY
A A
U-line 23e 28W
IccMax current-10ms max = 34 A
DY
12
C1124
SC1U10V2KX-1DLGP
DY
5
12
C1125
SC1U10V2KX-1DLGP
DY
12
C1126
SC1U10V2KX-1DLGP
DY
12
C1101
DY
SC1U10V2KX-1DLGP
12
C1127
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
SC1U10V2KX-1DLGP
RF request 2016/01/12 modify
Title
Title
Title
CPU_(Power CAP2)
CPU_(Power CAP2)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
4
3
2
CPU_(Power CAP2)
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
11 106Thursday, June 29, 2017
11 106Thursday, June 29, 2017
11 106Thursday, June 29, 2017
1
A00
A00
A00
SSID = MEMORY
5
4
3
2
1
1D2V_S3
U1204
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
D D
2D5V_S3
M_A_A05,12
M_A_A15,12
M_A_A25,12
M_A_A35,12
M_A_A45,12
M_A_A55,12
M_A_A65,12
M_A_A75,12
M_A_A85,12
M_A_A95,12
M_A_A105,12
M_A_A115,12
M_A_A125,12
M_A_A135,12
M_A_A145,12
M_A_A155,12
M_A_A165,12
M_A_CS#05,12
DDR4_DR AMRST#5,12,13
M_A_ACT_N5,12
M_A_ALERT_N5,12
M_A_CLK05,12
M_A_CLK#05,12
M_A_CKE05,12
M_A_BA05,12
M_A_BA15,12
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
VREFCA
NC#T7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
C7
C2
C8
D3
D7
B7
A7
G3
M_A_DQS_DN1
F3
E2
E7
K3
ODT
F9
ZQ
M1
M2
BG0
N9
TEN
T3
PAR
T7
B2
VSS
E1
VSS
M_A_BG1_E9_1
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M_A_BG1_M9_R
M9
VSS
N1
VSS
T1
VSS
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
M_A_DQS_DP0
M_A_DQS_DN0
M_A_DQS_DP1
TEST_MODE_1
M_A_DQ8 5
M_A_DQ9 5
M_A_DQ10 5
M_A_DQ11 5
M_A_DQ12 5
M_A_DQ13 5
M_A_DQ14 5
M_A_DQ15 5
M_A_DQ0 5
M_A_DQ1 5
M_A_DQ2 5
M_A_DQ3 5
M_A_DQ4 5
M_A_DQ5 5
M_A_DQ6 5
M_A_DQ7 5
M_A_DIMA_ODT0 5,12
M_A_BG0 5,12
M_A_PARITY 5,12
A_ZQ_RAM4
M_VREF_CA_D IMMA
1
TP1201
TPAD14-OP-G P
2016/11/29
1D2V_S3
240R2D-GP
C1201
SCD047U25V2KX-4-GP
R1201
1 2
12
M_A_A05,12
M_A_A15,12
M_A_A25,12
M_A_A35,12
M_A_A45,12
M_A_A55,12
M_A_A65,12
M_A_A75,12
M_A_A85,12
M_A_A95,12
M_A_A105,12
M_A_A115,12
M_A_A125,12
M_A_A135,12
DDR4_DR AMRST#5,12,13
M_A_ACT_N5,12
M_A_ALERT_N5,12
2017/05/10
1D2V_S3
C C
2D5V_S3
M_A_A05,12
M_A_A15,12
M_A_A25,12
M_A_A35,12
M_A_A45,12
M_A_A55,12
M_A_A65,12
M_A_A75,12
M_A_A85,12
M_A_A95,12
M_A_A105,12
M_A_A115,12
M_A_A125,12
M_A_A135,12
M_A_A145,12
M_A_A155,12
M_A_A165,12
M_A_CS#05,12
DDR4_DR AMRST#5,12,13
M_A_ACT_N5,12
M_A_ALERT_N5,12
M_A_CLK05,12
M_A_CLK#05,12
M_A_CKE05,12
M_A_BA05,12
B B
M_A_BA15,12
SDP & DDP SETTING
M_A_BG1_E9_1
M_A_BG1_E9_2
M_A_BG1_E9_3
M_A_BG1_E9_4
M_A_BG1_E9_1
M_A_BG1_E9_2
M_A_BG1_E9_3
M_A_BG1_E9_4
M_A_BG15
A A
5
1 2
R1212 240R2F-1-GP
DDP
1 2
R1213 240R2F-1-GP
DDP
1 2
R1214 240R2F-1-GP
DDP
1 2
R1215 240R2F-1-GP
DDP
1 2
R1216 0R2J-2-GP
SDP
1 2
R1217 0R2J-2-GP
SDP
1 2
R1218 0R2J-2-GP
SDP
1 2
R1219 0R2J-2-GP
SDP
DDP
1 2
R1220 0R2J-2-GP
1 2
R1221 0R2J-2-GP
SDP
M_A_BG1_M9_R
U1201
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
B7
UDQS_T
A7
UDQS_C
G3
LDQS_T
F3
LDQS_C
E2
E7
K3
ODT
F9
ZQ
M1
VREFCA
M2
BG0
N9
TEN
T3
PAR
T7
NC#T7
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
CTRL/CKE/CMD
M_A_DQS_DP7
M_A_DQS_DN7
M_A_DQS_DP6
M_A_DQS_DN6
TEST_MODE_2
M_A_BG1_E9_3
M_A_BG1_M9_R
CLK
M_A_DQ53 5
M_A_DQ51 5
M_A_DQ55 5
M_A_DQ50 5
M_A_DQ48 5
M_A_DQ52 5
M_A_DQ54 5
M_A_DQ49 5
M_A_DQ61 5
M_A_DQ57 5
M_A_DQ58 5
M_A_DQ63 5
M_A_DQ60 5
M_A_DQ56 5
M_A_DQ59 5
M_A_DQ62 5
M_A_DIMA_ODT0 5,12
M_A_BG0 5,12
M_A_PARITY 5,12
2016/11/29
A_ZQ_RAM1
1
TP1202
TPAD14-OP-G P
2016/11/29
M_A_CLK#0
M_A_CLK0
M_A_BG1_M9_R
2016/11/25
M_A_CKE0
M_A_A12
M_A_A3
M_A_ACT_N
M_A_BG0
M_A_A5
M_A_A2
M_A_BA1
M_A_A6
M_A_A7
M_A_A0
M_A_A13
M_A_A11
M_A_A9
M_A_A8
M_A_PARITY
M_A_A1
M_A_BA0
M_A_A4
M_A_A14
M_A_A10
M_A_A16
M_A_A15
M_A_DIMA_ODT0
M_A_CS#0
1D2V_S3
M_VREF_CA_D IMMA
SCD047U25V2KX-4-GP
12
C1236
R1226 36R2F-1-GP
R1225 36R2F-1-GP
1 2
R1224 36R2F-1-GP
R1211 36R2F-1-GP
1 2
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
4
240R2D-GP
R1205
1 2
1 2
DDP
RN1202
SRN36J-GP
RN1203
SRN36J-GP
RN1204
SRN36J-GP
RN1205
1
2
3
4 5
SRN36J-GP
RN1206
1
2
3
4 5
SRN36J-GP
RN1207
1
2
3
4 5
SRN36J-GP
M_A_A05,12
M_A_A15,12
M_A_A25,12
M_A_A35,12
M_A_A45,12
12
0D6V_S0
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
M_A_A55,12
M_A_A65,12
M_A_A75,12
M_A_A85,12
M_A_A95,12
M_A_A105,12
M_A_A115,12
M_A_A125,12
M_A_A135,12
M_A_A145,12
DDR4_DR AMRST#5,12,13
M_A_ACT_N5,12
M_A_ALERT_N5,12
ALERT
M_A_A155,12
M_A_A165,12
2D5V_S3
M_A_A145,12
M_A_A155,12
M_A_A165,12
M_A_CS#05,12
M_A_CLK05,12
M_A_CLK#05,12
M_A_CKE05,12
M_A_BA05,12
M_A_BA15,12
1D2V_S3
2D5V_S3
M_A_CS#05,12
M_A_CLK05,12
M_A_CLK#05,12
M_A_CKE05,12
M_A_BA05,12
M_A_BA15,12
M_A_ALERT_N
2016/11/25 DY
3
1D2V_S3
U1203
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
U1202
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
R1208
1 2
49D9R2F-GP
close to cpu
C1285
M_A_CLK0 M_A_CLK0
1 2
SC3300P50V2KX-1D LGP
DY
C1287
M_A_CLK#0 M_A_CLK#0
1 2
SC3300P50V2KX-1D LGP
DY
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
NF#E2/UDM#/UDBI#
NF#E7/LDM#/LDBI#
VREFCA
NC#T7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
NF#E2/UDM#/UDBI#
NF#E7/LDM#/LDBI#
VREFCA
NC#T7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1D2V_S3
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
C7
C2
C8
D3
D7
B7
A7
G3
F3
E2
E7
K3
ODT
F9
ZQ
M1
M2
BG0
N9
TEN
T3
PAR
T7
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
C7
C2
C8
D3
D7
B7
A7
G3
F3
E2
E7
K3
ODT
F9
ZQ
M1
M2
BG0
N9
TEN
T3
PAR
T7
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
M_A_DQS_DP2
M_A_DQS_DN2
M_A_DQS_DP3
M_A_DQS_DN3
TEST_MODE_3
M_A_BG1_E9_2
M_A_BG1_M9_R
M_A_DQS_DP4
M_A_DQS_DN4
M_A_DQS_DP5
M_A_DQS_DN5
TEST_MODE_4
M_A_BG1_E9_4
M_A_BG1_M9_R
M_A_DQ24 5
M_A_DQ25 5
M_A_DQ26 5
M_A_DQ27 5
M_A_DQ28 5
M_A_DQ29 5
M_A_DQ30 5
M_A_DQ31 5
M_A_DQ16 5
M_A_DQ17 5
M_A_DQ18 5
M_A_DQ19 5
M_A_DQ20 5
M_A_DQ21 5
M_A_DQ22 5
M_A_DQ23 5
M_A_DIMA_ODT0 5,12
M_A_BG0 5,12
M_A_PARITY 5,12
2016/11/29
M_A_DQ40 5
M_A_DQ41 5
M_A_DQ47 5
M_A_DQ42 5
M_A_DQ44 5
M_A_DQ45 5
M_A_DQ43 5
M_A_DQ46 5
M_A_DQ33 5
M_A_DQ37 5
M_A_DQ34 5
M_A_DQ35 5
M_A_DQ36 5
M_A_DQ32 5
M_A_DQ38 5
M_A_DQ39 5
M_A_DIMA_ODT0 5,12
M_A_BG0 5,12
M_A_PARITY 5,12
2016/11/29
A_ZQ_RAM3
M_VREF_CA_D IMMA
1
TP1203
TPAD14-OP-G P
A_ZQ_RAM2
M_VREF_CA_D IMMA
1
TP1204
TPAD14-OP-G P
1D2V_S3
1K8R2F-GP
R1222
1 2
1 2
R1223
1K8R2F-GP
2016/11/25
1D2V_S3
240R2D-GP
12
R1204
12
SCD047U25V2KX-4-GP
C1203
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
1D2V_S3
240R2D-GP
12
R1234
12
SCD047U25V2KX-4-GP
C1286
M_A_DQS_DN[7: 0] 5
M_A_DQS_DP[7:0] 5
1D2V_S3
VDDQ/VDD 1uF x32
12
12
C1204
SC1U10V2KX-1DLGP
12
C1220
SC1U10V2KX-1DLGP
1D2V_S3
VDDQ/VDD 10uF x10
12
C1237
SC10U6D3V3MX-DL-GP
VPP 1uF x16
2D5V_S3
2017/01/17
C1205
DY
SC1U10V2KX-1DLGP
12
C1221
SC1U10V2KX-1DLGP
12
C1238
SC10U6D3V3MX-DL-GP
12
C1206
SC1U10V2KX-1DLGP
12
C1222
12
12
C1207
DY
SC1U10V2KX-1DLGP
12
C1223
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
DY
C1239
SC10U6D3V3MX-DL-GP
12
12
C1208
C1209
SC1U10V2KX-1DLGP
12
12
C1224
C1225
SC1U10V2KX-1DLGP
DY
DY
C1240
12
12
C1241
SC10U6D3V3MX-DL-GP
2017/01/17
12
12
12
12
12
C1260
C1259
SC1U10V2KX-1DLGP
2D5V_S3
DY
C1268
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
VPP 10uF x5
12
C1279
12
SC10U6D3V3MX-DL-GP
DY
C1261
C1275
12
C1269
C1262
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
C1276
12
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
M_VREF_CA_D IMMA
12
C1210
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
C1226
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
SC10U6D3V3MX-DL-GP
12
C1270
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
DY
C1277
12
C1278
SC10U6D3V3MX-DL-GP
2017/03/07
1 2
12
C1211
SC1U10V2KX-1DLGP
12
C1227
SC1U10V2KX-1DLGP
C1242
SC10U6D3V3MX-DL-GP
2017/01/17
DY
12
C1263
SC1U10V2KX-1DLGP
SC10U6D3V3MX-DL-GP
R1202
2D7R2F-1-G P
12
C1212
SC1U10V2KX-1DLGP
12
C1228
SC1U10V2KX-1DLGP
DY
12
C1243
SC10U6D3V3MX-DL-GP
12
C1264
SC1U10V2KX-1DLGP
0D6V_S0
DY
C1202
SCD022U16V2KX -3DLGP
2 1
+V_VREF_PATH 1
12
R1203
24D9R2F-L-G P
12
12
C1213
C1214
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
DY
C1230
C1229
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
2017/01/17
DY
12
C1244
SC10U6D3V3MX-DL-GP
DY
12
12
C1271
C1265
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
VTT 10uF x4
12
12
C1288
C1289
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
V_SM_VREF_CN TA 5
12
12
12
12
C1217
12
C1233
12
C1218
C1219
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
DY
C1235
C1234
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
C1215
12
C1231
C1216
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
C1232
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
DY
12
12
C1245
C1246
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
DY
DY
DY
12
12
12
12
C1266
12
12
C1273
C1274
C1267
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
C1291
SC10U6D3V3MX-DL-GP
C1272
12
SC1U10V2KX-1DLGP
C1290
SC10U6D3V3MX-DL-GP
2017/01/17
0D6V_S0
VTT 1uF x16
2017/01/17
DY
DY
DY
12
12
12
12
C1257
C1255
C1258
C1280
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2
2017/01/17
DY
DY
C1281
DY
12
12
C1282
C1283
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
DY
DY
12
12
12
12
C1284
C1293
C1294
C1292
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
2017/01/172017/03/07
DY
DY
12
12
12
C1297
C1296
C1295
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
KyloRen 13"
KyloRen 13"
KyloRen 13"
SC1U10V2KX-1DLGP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
12
C1298
SC1U10V2KX-1DLGP
DY
12
C1299
SC1U10V2KX-1DLGP
12 106
12 106
12 106
A00
A00
A00
SSID = MEMORY
5
4
3
2
1
1D2V_S3
D D
2D5V_S3
M_B_A05,13
M_B_A15,13
M_B_A25,13
M_B_A35,13
M_B_A45,13
M_B_A55,13
M_B_A65,13
M_B_A75,13
M_B_A85,13
M_B_A95,13
M_B_A105,13
M_B_A115,13
M_B_A125,13
M_B_A135,13
M_B_A145,13
M_B_A155,13
M_B_A165,13
M_B_CS#05,13
DDR4_DR AMRST#5,12,13
M_B_ACT_N5,13
M_B_ALERT_N5,13
M_B_CLK05,13
M_B_CLK#05,13
M_B_CKE05,13
M_B_BA05,13
M_B_BA15,13
C C
1D2V_S3
2D5V_S3
M_B_A05,13
M_B_A15,13
M_B_A25,13
M_B_A35,13
M_B_A45,13
M_B_A55,13
M_B_A65,13
M_B_A75,13
M_B_A85,13
M_B_A95,13
M_B_A105,13
M_B_A115,13
M_B_A125,13
M_B_A135,13
M_B_A145,13
M_B_A155,13
M_B_A165,13
M_B_CS#05,13
B B
DDR4_DR AMRST#5,12,13
M_B_ACT_N5,13
M_B_ALERT_N5,13
M_B_CLK05,13
M_B_CLK#05,13
M_B_CKE05,13
M_B_BA05,13
M_B_BA15,13
SDP & DDP SETTING
M_B_BG1_E9_1
M_B_BG1_E9_2
M_B_BG1_E9_3
M_B_BG1_E9_4
M_B_BG1_E9_1
M_B_BG1_E9_2
M_B_BG1_E9_3
M_B_BG1_E9_4
M_B_BG15
A A
1 2
R1331 240R2F-1-GP
1 2
R1332 240R2F-1-GP
1 2
R1333 240R2F-1-GP
1 2
R1334 240R2F-1-GP
1 2
R1335 0R2J-2-GP
1 2
R1336 0R2J-2-GP
1 2
R1337 0R2J-2-GP
1 2
R1338 0R2J-2-GP
1 2
R1339 0R2J-2-GP
1 2
R1340 0R2J-2-GP
5
DDP
DDP
DDP
DDP
SDP
SDP
SDP
SDP
DDP
SDP
M_B_BG1_M9_R
U1302
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
U1304
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
ODT
ZQ
VREFCA
BG0
TEN
PAR
NC#T7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
ODT
ZQ
VREFCA
BG0
TEN
PAR
NC#T7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2017/05/10
G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7
B7
A7
G3
F3
E2
E7
K3
F9
M1
M2
N9
T3
T7
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7
B7
A7
G3
F3
E2
E7
K3
F9
M1
M2
N9
T3
T7
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
M_B_DQS_DP0
M_B_DQS_DN0
M_B_DQS_DP1
M_B_DQS_DN1
M_B_BG1_E9_1
M_B_BG1_M9_R
M_B_DQS_DP4
M_B_DQS_DN4
M_B_DQS_DP5
M_B_DQS_DN5
TEST_MODE_6
M_B_BG1_E9_3
M_B_BG1_M9_R
M_B_DQ10 5
M_B_DQ15 5
M_B_DQ14 5
M_B_DQ11 5
M_B_DQ12 5
M_B_DQ13 5
TEST_MODE_5
M_B_DQ41 5
M_B_DQ47 5
M_B_DQ45 5
M_B_DQ46 5
M_B_DQ40 5
M_B_DQ42 5
M_B_DQ44 5
M_B_DQ43 5
M_B_DQ37 5
M_B_DQ39 5
M_B_DQ36 5
M_B_DQ34 5
M_B_DQ33 5
M_B_DQ32 5
M_B_DQ38 5
M_B_DQ35 5
M_B_PARITY 5,13
M_B_DQ9 5
M_B_DQ8 5
M_B_DQ5 5
M_B_DQ2 5
M_B_DQ0 5
M_B_DQ3 5
M_B_DQ4 5
M_B_DQ1 5
M_B_DQ6 5
M_B_DQ7 5
M_B_DQS_DP0 5
M_B_DQS_DN0 5
M_B_DQS_DP1 5
M_B_DQS_DN1 5
M_B_DIMB_ODT0 5,13
M_B_BG0 5,13
M_B_PARITY 5,13
2016/11/29
M_B_DQS_DP4 5
M_B_DQS_DN4 5
M_B_DQS_DP5 5
M_B_DQS_DN5 5
M_B_DIMB_ODT0 5,13
M_VREF_CA_D IMMB
M_B_BG0 5,13
1
2016/11/29
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
B_ZQ_RAM2
M_VREF_CA_D IMMB
1
TP1301
TPAD14-OP-G P
C1301
B_ZQ_RAM4
TP1302
TPAD14-OP-G P
C1343
4
1D2V_S3
R1301 240R2D-G P
12
SCD047U25V2KX-4-GP
1D2V_S3
R1305
1 2
240R2D-GP
12
SCD047U25V2KX-4-GP
1 2
M_B_DQS_DN[7: 0] 5
M_B_DQS_DP[7:0] 5
ALERT
M_B_A05,13
M_B_A15,13
M_B_A25,13
M_B_A35,13
M_B_A45,13
M_B_A55,13
M_B_A65,13
M_B_A75,13
M_B_A85,13
M_B_A95,13
M_B_A105,13
M_B_A115,13
M_B_A125,13
M_B_A135,13
M_B_A145,13
DDR4_DR AMRST#5,12,13
M_B_ACT_N5,13
M_B_ALERT_N
M_B_A155,13
M_B_A165,13
M_B_ALERT_N5,13
DDR4_DR AMRST#5,12,13
M_B_ACT_N5,13
1D2V_S3
2D5V_S3
M_B_CS#05,13
M_B_CLK05,13
M_B_CLK#05,13
M_B_CKE05,13
M_B_BA05,13
M_B_BA15,13
2D5V_S3
M_B_A05,13
M_B_A15,13
M_B_A25,13
M_B_A35,13
M_B_A45,13
M_B_A55,13
M_B_A65,13
M_B_A75,13
M_B_A85,13
M_B_A95,13
M_B_A105,13
M_B_A115,13
M_B_A125,13
M_B_A135,13
M_B_A145,13
M_B_A155,13
M_B_A165,13
M_B_CS#05,13
M_B_ALERT_N5,13
M_B_CLK05,13
M_B_CLK#05,13
M_B_CKE05,13
M_B_BA05,13
M_B_BA15,13
R1330
1 2
49D9R2F-GP
3
1D2V_S3
B3
B9
D1
G7
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
B1
R9
P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8
M8
P1
P9
K7
K8
K2
N2
N8
U1301
VDD
VDD
VDD
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
J2
VDDQ
J8
VDDQ
VPP
VPP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
L2
WE#/A14
CAS#/A15
L8
RAS#/A16
L7
CS#
RESET#
L3
ACT#
ALERT#
CK_T
CK_C
CKE
BA0
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
UDQS_T
UDQS_C
LDQS_T
LDQS_C
NF#E2/UDM#/UDBI#
NF#E7/LDM#/LDBI#
VREFCA
2017/05/10
U1303
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
1D2V_S3
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
M_B_DQS_DP2
B7
M_B_DQS_DN2
A7
M_B_DQS_DP3
G3
M_B_DQS_DN3
F3
E2
E7
K3
ODT
F9
ZQ
M1
M2
BG0
N9
TEN
T3
PAR
T7
NC#T7
B2
VSS
E1
VSS
M_B_BG1_E9_2
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M_B_BG1_M9_R
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
B7
UDQS_T
A7
UDQS_C
G3
LDQS_T
F3
LDQS_C
E2
E7
K3
ODT
F9
ZQ
M1
VREFCA
M2
BG0
N9
TEN
T3
PAR
T7
NC#T7
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
CLK
CTRL/CKE/CMD
TEST_MODE_7
M_B_DQS_DP6
M_B_DQS_DN6
M_B_DQS_DP7
M_B_DQS_DN7
TEST_MODE_8
M_B_BG1_E9_4
M_B_BG1_M9_R
M_B_DQ25 5
M_B_DQ29 5
M_B_DQ30 5
M_B_DQ27 5
M_B_DQ24 5
M_B_DQ28 5
M_B_DQ31 5
M_B_DQ26 5
M_B_DQ18 5
M_B_DQ20 5
M_B_DQ22 5
M_B_DQ16 5
M_B_DQ23 5
M_B_DQ17 5
M_B_DQ21 5
M_B_DQ19 5
M_B_DQS_DP2 5
M_B_DQS_DN2 5
M_B_DQS_DP3 5
M_B_DQS_DN3 5
M_B_DIMB_ODT0 5,13
M_B_BG0 5,13
M_B_PARITY 5,13
2016/11/29
M_B_DQ58 5
M_B_DQ60 5
M_B_DQ62 5
M_B_DQ61 5
M_B_DQ57 5
M_B_DQ56 5
M_B_DQ63 5
M_B_DQ59 5
M_B_DQ51 5
M_B_DQ49 5
M_B_DQ55 5
M_B_DQ52 5
M_B_DQ54 5
M_B_DQ48 5
M_B_DQ53 5
M_B_DQ50 5
M_B_DIMB_ODT0 5,13
M_B_PARITY 5,13
2016/11/29
2016/11/28
M_B_BG1_M9_R
M_B_CKE0
M_B_A15
M_B_A16
M_B_A14
M_B_CS#0
M_B_A4
M_B_A6
M_B_A0
M_B_PARITY
M_B_A13
M_B_A9
M_B_A1
M_B_A5
M_B_ACT_N
M_B_DIMB_ODT0
M_B_A10
M_B_BA0
M_B_A3
M_B_BA1
M_B_BG0
M_B_A12
M_B_A11
M_B_A2
M_B_A8
M_B_A7
B_ZQ_RAM1
1
TPAD14-OP-G P
M_B_DQS_DP6 5
M_B_DQS_DN6 5
M_B_DQS_DP7 5
M_B_DQS_DN7 5
M_B_BG0 5,13
2016/11/29
M_B_CLK0
M_B_CLK#0
1D2V_S3
1 2
M_VREF_CA_D IMMB
R1304
240R2D-GP
TP1303
12
C1303
SCD047U25V2KX-4-GP
1D2V_S3
R1306
240R2D-GP
B_ZQ_RAM3
1 2
M_VREF_CA_D IMMB
1
TP1304
12
TPAD14-OP-G P
SCD047U25V2KX-4-GP
C1336
R1313 36R2F-1-GP
1 2
R1314 36R2F-1-GP
1 2
DDP
R1312 36R2F-1-GP
1 2
R1311 36R2F-1-GP
1 2
RN1302
1
8
2
7
3
6
4 5
SRN36J-GP
RN1303
1
8
2
7
3
6
4 5
SRN36J-GP
RN1304
1
8
2
7
3
6
4 5
SRN36J-GP
RN1305
1
8
2
7
3
6
4 5
SRN36J-GP
RN1306
1
8
2
7
3
6
4 5
SRN36J-GP
RN1307
1
8
2
7
3
6
4 5
SRN36J-GP
1D2V_S3
2016/11/25
0D6V_S0
2
1K8R2F-GP
R1320
1 2
1 2
R1321
1K8R2F-GP
2017/03/07
M_VREF_CA_D IMMB
2D5V_S3
0D6V_S0
1 2
1D2V_S3
VDDQ/VDD 1uF x32
12
C1304
SC1U10V2KX-1DLGP
12
C1320
SC1U10V2KX-1DLGP
1D2V_S3
VDDQ/VDD 10uF x10
12
C1390
SC10U6D3V3MX-DL-GP
2D5V_S3
VPP 1uF x16
12
C1337
DY
SC1U10V2KX-1DLGP
VPP 10uF x5
12
C1371
SC10U6D3V3MX-DL-GP
VTT 1uF x16
DY
12
12
C1354
C1355
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2016/11/25 DY
R1302
2D7R2F-1-G P
C1302
SCD022U16V2KX -3DLGP
2 1
+V_VREF_PATH 2
12
R1303
24D9R2F-L-G P
12
C1305
SC1U10V2KX-1DLGP
12
C1321
SC1U10V2KX-1DLGP
12
12
C1307
C1306
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
C1322
C1323
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
12
12
DY
DY
C1391
C1392
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
12
C1338
SC1U10V2KX-1DLGP
12
12
C1340
C1339
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
12
12
DY
C1372
12
C1373
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
DY
DY
12
12
12
C1357
C1356
C1358
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
close to cpu
C1388
M_B_CLK0 M_B_CLK0
1 2
SC3300P50V2KX-1D LGP
DY
C1389
M_B_CLK#0 M_B_CLK#0
1 2
SC3300P50V2KX-1D LGP
DY
2017/01/17
12
C1308
SC1U10V2KX-1DLGP
DY
12
C1324
SC1U10V2KX-1DLGP
DY
2017/01/17
12
C1393
SC10U6D3V3MX-DL-GP
DY
12
C1341
SC1U10V2KX-1DLGP
DY
C1374
SC10U6D3V3MX-DL-GP
12
V_SM_VREF_CN TB 5
12
C1309
SC1U10V2KX-1DLGP
DY
12
C1325
SC1U10V2KX-1DLGP
DY
12
C1394
SC10U6D3V3MX-DL-GP
12
C1342
SC1U10V2KX-1DLGP
12
C1375
SC10U6D3V3MX-DL-GP
DY
12
C1360
C1359
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
2017/01/17
12
12
C1310
12
C1311
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
C1327
C1326
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
C1312
SC1U10V2KX-1DLGP
12
C1328
SC1U10V2KX-1DLGP
12
12
12
12
12
C1313
SC1U10V2KX-1DLGP
12
C1329
SC1U10V2KX-1DLGP
C1314
SC1U10V2KX-1DLGP
12
C1330
SC1U10V2KX-1DLGP
C1315
SC1U10V2KX-1DLGP
12
C1331
SC1U10V2KX-1DLGP
DY
DY
C1316
SC1U10V2KX-1DLGP
12
C1332
SC1U10V2KX-1DLGP
DY
C1317
SC1U10V2KX-1DLGP
12
C1333
SC1U10V2KX-1DLGP
DY
12
12
C1318
C1319
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
C1334
C1335
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
2017/01/17
DY
12
12
C1396
C1395
SC10U6D3V3MX-DL-GP
DY
12
12
C1397
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
C1398
12
C1399
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
DY
DY
12
12
12
C1345
C1344
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
C1346
SC1U10V2KX-1DLGP
12
C1347
SC1U10V2KX-1DLGP
0D6V_S0
12
12
C1348
C1349
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
VTT 10uF x4
12
12
C1350
C1351
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
12
12
C1353
C1352
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
DY
DY
12
C1376
SC10U6D3V3MX-DL-GP
DY
12
12
12
C1377
C1379
C1378
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
DY
DY
DY
12
C1361
SC1U10V2KX-1DLGP
DY
12
12
12
C1363
C1364
C1362
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
DY
DY
DY
12
12
12
C1365
SC1U10V2KX-1DLGP
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
C1367
C1366
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
1
12
C1369
C1368
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
KyloRen 13"
KyloRen 13"
KyloRen 13"
13 106
13 106
13 106
A00
A00
A00
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
(Reserved)_SODIMM _SODIMM4
(Reserved)_SODIMM _SODIMM4
(Reserved)_SODIMM _SODIMM4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
14 106Thursday, June 29, 2017
14 106Thursday, June 29, 2017
14 106Thursday, June 29, 2017
1
5
4
3
2
1
SSID = PCH
3D3V_S0
CPU1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
D D
C C
C38
D38
C36
D36
A38
B38
C31
D31
C33
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3
CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
SKYLAKE-U-GP
SKYLAKE_ULT
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
9 OF 20
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
EMMC_RCOMP
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
DC resistance < 0.5ohm.
CSI2_COMP
1 2
R1501 100R2F-L1-GP-U
WIFI_RF_EN 66
GPP_F: VCCPGPPF = 1.8V Only
R1502
EMMC_RCOMP
1 2
200R2F-L-GP
WIFI_RF_EN
071.SKYLA.000U
R1503
12
DY
10KR2J-3-GP
Change to Dummy 20150402
[#545659 Rev0.7]
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(CS-2/EMMC)
CPU_(CS-2/EMMC)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(CS-2/EMMC)
KyloRen 13"
KyloRen 13"
KyloRen 13"
15 106Thursday, June 29, 2017
15 106Thursday, June 29, 2017
15 106Thursday, June 29, 2017
1
A00
A00
A00
5
4
3
2
1
SSID= PCH
#543016:
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2.
GPU
D D
Swap Net follow DELL HSIO 20161025
LAN
WLAN
WLAN_PC IE_RX_N66
WLAN_PC IE_RX_P66
WLAN_PC IE_TX_N66
WLAN_PC IE_TX_P66
C1601
C1602
1 2
1 2
SCD1U25V2KX- 1-DL-GP
WLAN_PC IE_TX_N_C
WLAN_PC IE_TX_P_C
SCD1U25V2KX- 1-DL-GP
HDD1
MSATA_PCIE_RX_N 963
MSATA_PCIE_RX_P963
MSATA_PCIE_TX_N 963
MSATA_PCIE_TX_P963
MSATA_PCIE_RX_N 1063
MSATA_PCIE_RX_P1 063
MSATA_PCIE_TX_N 1063
MSATA_PCIE_TX_P1063
SSD
C C
+V1.8A_SIP
1 2
R1607 10KR2J-3-GP
XDP_PRDY#99
XDP_PREQ#99
MSATA_PCIE_RX_N 1163
MSATA_PCIE_RX_P1 163
MSATA_PCIE_TX_N 1163
MSATA_PCIE_TX_P1163
MSATA_SATA_R X_N263
MSATA_SATA_R X_P263
MSATA_SATA_TX _N263
MSATA_SATA_TX _P263
Layout Note:
PIRQA#
1 2
R1604
100R2F-L1-GP- U
1. Trace Width: 4 mils min (breakout) 12-15 mils (trace)
Note: Must maintain low DC resistance routing (<0.1 ohm).
2. Isolation Spacing: At least 12 mils to any adjacent
high speed I/O.
PCIE_RCOMPN
PCIE_RCOMPP
PIRQA#
CPU1H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKYLAKE-U-GP
071.SKYLA.000U
SKYLAKE_ULT
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
8 OF 20
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
DC resistance < 0.5ohm.
AB6
USBCOMP
USB2_ID
AG3
USB2_VBUSSEN SE
AG4
A9
C9
USB_OC2#
D9
USB_OC3#
B9
J1
SIO_EXT_SCI#
J2
J3
GPP_E0/SATAXPC IE0/SATAGP0
H2
GPP_E1/SATAXPC IE1/SATAGP1
H3
G4
H1
USB1_USB20_N 34
USB1_USB20_P 34
USB2_USB20_N 66
USB2_USB20_P 66
TYPEC_USB20_N 3 8
TYPEC_USB20_P 38
CCD_USB20_ N 55
CCD_USB20_ P 5 5
CARD1_USB 20_N 66
CARD1_USB 20_P 66
BT_USB20_N 66
BT_USB20_P 66
FP1_USB20_N 92
FP1_USB20_P 92
1 2
R1603 1 13R2F-GP
USB_OC0# 34,35
USB_OC1# 66
SSD_DEVSLP 63
1
1
USB1_USB30_RX _N1 36
USB1_USB30_RX _P1 36
USB1_USB30_TX _N1 36
USB1_USB30_TX _P1 36
USB2_USB30_RX _N3 66
USB2_USB30_RX _P3 66
USB2_USB30_TX _N3 66
USB2_USB30_TX _P3 66
TYPEC_USB30_RX _N4 38
TYPEC_USB30_RX _P4 38
TYPEC_USB30_TX _N4 38
TYPEC_USB30_TX _P4 38
Follow SKL PDG design guide
(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND
using 8.2 KĪ© to 10 KĪ© on the motherboard.
Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable.
(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
For power share
USB3.0
IO board USB3.0
Type-c Full
For power share
USB3.0
IO board USB3.0
Type-c Full
CAMERA
Card Reader
Swap Net follow DELL HSIO 20161025
WLAN (BT)
Touch Panel
Fingerprint Reader
Remove Sensor HUB
(#543016) When used as DEVSLP, no external pull-up or pull-down
termination required from SATA Host DEVSLP.
TP1602 TPAD14-OP-GP
TP1603 TPAD14-OP-GP
M2_SSD_PEDET 63
SATA_LED# 64
USB2_ID
USB2_VBUSSEN SE
R1601 0R0402-PAD
1 2
R1602 0R0402-PAD
1 2
2016/12/28
USB_OC2#
USB_OC3#
USB_OC0#
USB_OC1#
SIO_EXT_SCI#
RN1601
8
7
6
SRN10KJ-6-G P
R1608 10KR2J-3-GP
3D3V_S5_PCH
1
2
3
45
3D3V_S0
12
3D3V_S0
R1606
SATA_LED#
(#543611)
The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kĪ© to 10 kĪ©) to Vcc3_3.
12
10KR2J-3-GP
USB 2.0 Table
Pair
Device
USB3.0 port1
1
N/A
2
USB3.0 Port2 (IOBD)
3
Type-c
4
CAMERA
5
WLAN
6
Touch Panel
7
8
#545659 (SKL_PCH_U_Y_EDS Rev0.7)
B B
Card Reader
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Taipei Hsie n 221, Taiwan, R.O. C.
CPU_(PCIE/SATA/USB)
CPU_(PCIE/SATA/USB)
CPU_(PCIE/SATA/USB)
KyloRen 13"
KyloRen 13"
KyloRen 13"
16 106Thursday, June 29, 2017
16 106Thursday, June 29, 2017
16 106Thursday, June 29, 2017
A00
A00
A00
SSID = PCH
5
4
3
2
1
3D3V_S5
D D
C C
RTC_AUX_S5
+V3.3A_SIP
R1709,R1723,R1703,R1724 merge to RN1704
RN1704
1
2
3
4 5
SRN10KJ-6-GP
R1730
330KR2J-L1-GP
1 2
R1731
20KR2J-L2-GP
RN1703
1
2 3
SRN10KJ-5-GP
DY
EXT_PW R_GATE#
4
12
1 2
R1717 10KR2J-3-GP
AC_PRESENT
8
PCIE_WAKE#_CPU
7
PCH_BATLOW#
6
GPD11/LANPHYPC
GPD11 pull high by Intel PDG1.3 request
#544669 (CRB): 330k.
SM_INTRUDER#
[#543016 Rev0.7]
EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k
pull-down that is active during the early portion of the power up sequence
PM_RSMRST#
PM_PCH_PWROK
SYS_PWROK
#544669 Rev0.52 CRB:
No PL resistor on THERMTRIP#.
H_CPUPW RGD
R1714
10KR2J-3-GP
12
DY
EC1701
AZ5725-01FDR7G-GP
EMI DVT1 0210
2016/12/29
+V1.8A_SIP
+VCCPDSW_3P33D3V_S5
1 2
R1711
0R0603-PAD
Layout note: 3 PAD SHARING
XDP_DBRESET#99
SYS_PWROK24,99
12
DY
ME_SUS_PWR_ACK_R SUSACK#_R
RESET_OUT#24,26
PCIE_WAKE#_CPU24
+VCCPDSW_3P3
1 2
0R0402-PAD
2016/12/28
+V3.3A_SIP
12
R1701
10KR2J-3-GP
H_VCCST_PWRGD99
1 2
R1706 0R0402-PAD
1 2
R1704 0R0402-PAD
2016/12/28
1 2
R1707
10KR2J-3-GP
(PDG#543016)
WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.
R1708
1
TP1705TPAD14-OP-GP
2017/04/24
PCH_PLTRST#
PM_RSMRST#
H_CPUPW RGD
SYS_PWROK
PM_PCH_PWROK
PCH_DPW ROKPM_RSMRST#
ME_SUS_PWR_ACK_R
SUSACK#_R
LAN_WAKE#
GPD11/LANPHYPC
CPU1K
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/USB2_WAKEOUT#
SKYLAKE-U-GP
SYSTEM POWER MANAGEMENT
SKYLAKE_ULT
071.SKYLA.000U
11 OF 20
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
AC_PRESENT
PCH_BATLOW#
SM_INTRUDER#
EXT_PW R_GATE#
VRALERT#
AUX_EN_WOW L 24,61
1
SIO_SLP_S0# 24,40,91
SIO_SLP_S3# 24,40,51
SIO_SLP_S4# 40,54
SIO_PWRBTN# 24,99
TP1708 TPAD14-OP-GP
BATLOW#:
Pull-up required even if not implemented.
AC_PRESENT
EC1707
12
DY
SCD1U16V2KX-3GP
Dis-wire with XDP_PM_RSMRST_PWRGD_XDP
3D3V_S0
1 2
12
R1718
100KR2F-L1-GP
R1719
47KR2F-GP
H_VCCST_PWRGD
12
DY
C1711
SCD1U25V2KX-1-DL-GP
2016/12/07 for power sequence
XDP_DBRESET#
SYS_PWROK
PLT_RST#
RESET_OUT#
3V_5V_POK
12
EC1705
DY
AZ5725-01FDR7G-GP
12
EC1708
DY
AZ5725-01FDR7G-GP
EMI DVT1 0210
3D3V_AUX_S5
PLT_RST#26,63,66,91,99
100KR2J-1-GP
R1722 & EC1708 modify to 100k and 0.01uF at DVT1
#543016 Rev0.7
1. VCCST_PWRGD is only 1.0 V tolerant.
2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
4th = 84.DMN66.03F
3rd = 75.00601.07C
2nd = 84.2N702.E3F
84.2N702.A3F
Q1702
2N7002KDW-GP
34
2
5
R1737
1 2
NON DS3
100KR2J-1-GP
PM_RSMRST#_M
NON DS3
6
1
R1713
1 2
0R0402-PAD
12
12
R1715
DY
DY
D1701
RB751V-40H-GP
C1701
SC220P50V2KX-3GP
83.R2004.G8F
PM_RSMRST#_R PM_RSMRST#
R1720
1 2
0R0402-PAD
PCH_PLTRST#
KA
ACOK_IN_M 43,44
AC_PRESENT
2016/12/28
R1724
R1735
ME_SUS_PWR_ACK_R
+VCCMPHYGTAON_1P0_LS_SIP
12
C1704
SC10U6D3V3MX-DL-GP
RUNPWROK24,40
EMI DVT1 0210
EC1706
12
DY
SC1KP50V2KX-1GP
2017/03/16
12
EC1709
DY
AZ5725-01FDR7G-GP
ED1701
AZ5125-02S-R7G-GP
2
1
3
75.05125.07D
1 2
R1716
100KR2F-L1-GP
DY
12
EC1704
DY
AZ5725-01FDR7G-GP
1 2
R1738 10KR2J-3-GP
DY
AOZ Power switch, P/N: 074.01334.0093
Low Rds(on)= 5m Ohm
Turn on rise time = 10us
+VCCMPHYGTAON_1P0
SKL: 1.0V
+VCCMPHYGTAON_1P0(ICCMAX.=3.5A)
1D0V_S5
EC1710
SC2D2U6D3V2MX-DL-GP
B B
RF request 2016/01/12 modify
2017/05/08
12
1 2
0R0805-PAD
DY
1 2
0R0805-PAD
Follow Iris SKL
2015/11/30 modify
Reserve by NON DS3 function 20150413
2017/05/05
3D3V_AUX_S5
R1726
10KR2J-3-GP
1 2
A A
R1727
100KR2J-1-GP
1 2
NON DS3
3V_5V_POK#
Q1701
4 3
S2
G2
6
D1
PJT138KA-GP
1KR2J-1-GP
PM_RSMRST#
D2
3V_5V_POK_C
25
G1
1
S1
R1702
1 2
R1728
1 2
0R0402-PAD
2016/12/28
PCH_RSMRST# 24,99
3V_5V_POK 40,45,52,54
12
DY
C1710
EC1712
12
DY
075.00138.0A7C
2017/03/09
5
SCD47U10V2KX-GP
Dummy C1710 by it's useless
SCD1U16V2KX-3GP
EC1711 modify to 100k and 0.01uF at DVT1 20150203
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(POWER MANAGEMENT)
CPU_(POWER MANAGEMENT)
CPU_(POWER MANAGEMENT)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
17 106Thursday, June 29, 2017
17 106Thursday, June 29, 2017
17 106Thursday, June 29, 2017
A00
A00
A00
5
SSID = PCH
D D
3D3V_S5_PCH
+V1.8A_SIP
C C
R1835 and R1834 merge to RN1802
2015/10/06 modify
1
2 3
R1820
1 2
10KR2J-3-GP
R1821
1 2
10KR2J-3-GP
SERIRQ PH:
PDG: 8.2k
CRB: 10k
RN1802
SRN1KJ-7-GP
SPI_HOLD_ROM
4
SPI_WP_ROM
SIO_RCIN#
ESPI_ALERT#
SPI_CLK_ROM25,91
SPI_SO_ROM25,91
SPI_SI_ROM25,91
SPI_WP_ROM25,99
SPI_HOLD_ROM25
SPI_CS_ROM_N025
SPI_CS_ROM_N291
2016/11/25 change to CS2
2017/05/08
FFS_INT170
91
RCIN#:
Frequency to Avoid: 33 MHz
2016/11/4
SPI_SI_XDP99
R1806,R1807,R1808,R1809 merge to RN1803
2015/10/06 modify
RN1803
1
2
3
4 5
SRN10J-1-GP
1 2
1 2
1 2
TPM
TPM_SPI_IRQ#
ESPI_ALERT#24
For eSPI
3D3V_S5_PCH
12
R1822
1KR2J-1-GP
PLACE WITHIN 1.1 INCH OF PCH
8
7
6
SPI_CLK_CPU
SPI_SO_CPU
SPI_SI_CPU
SPI_WP_CPU
R181110R2F-L-GP
R18120R0402-PAD
R18380R2J-2-GP
TP1804TPAD14-OP-GP
TP1805TPAD14-OP-GP
TP1806TPAD14-OP-GP
4
R9935
1 2
XDP
SPI_HOLD_CPU
SPI_CS_CPU_N0
SPI_CS_CPU_N2
CPU_D4_TP
1
CPU_D5_TP
1
CPU_D6_TP
1
SIO_RCIN#
1KR2J-1-GP
PCH strap pin:
BOOT HALT
SPI0_MOSI
This signal has a weak internal pull-up.
(#543016)Optional, can be left as OPEN/No-Connect.
SPI_SI_CPU
CPU1E
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
AW13
AY11
M2
M3
J4
V1
V2
M1
G3
G2
G1
SPI - FLASH
SPI0_CLK
SPI0_MISO
Strap
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
SKYLAKE-U-GP
071.SKYLA.000U
0 = ENABLED
1 = DISABLED
WEAK INTERNAL PU
SKYLAKE_ULT
LPC
3
For eSPI
5 OF 20
SMBUS, SMLINK
Strap
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
20140820 DAIVD
SPI_SI_CPU
ESPI_IO[3..0]24,68
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
MEM_SMBCLK
MEM_SMBDATA
SMB_ALERT#
SML0_SMBCLK
SML0_SMBDATA
SML0_ALERT#
SML1_SMBCLK
SML1_SMBDATA
SML1ALERT#
PCH_ESPI_IO0
PCH_ESPI_IO1
PCH_ESPI_IO2
PCH_ESPI_IO3
PCH_ESPI_CLK
PCH Prim
3D3V_S5_PCH
12
DY
12
DY
ESPI_IO[3..0]
R1824
1KR2J-1-GP
R1825
1KR2J-1-GP
ESPI_IO3
ESPI_IO1
ESPI_IO2
ESPI_IO0
SML1_SMBCLK 24,26
SML1_SMBDATA 24,26
RN1806
6
7
8
SRN15J-GP
CLKRUN#
2
PCH_ESPI_CLK
R1818
8K2R2F-1-GP
1 2
DY
PCH_ESPI_IO3
PCH_ESPI_IO1
PCH_ESPI_IO2
PCH_ESPI_IO0
+V1.8A_SIP
45
3
2
1
ESPI_CS# 24,68
ESPI_RESET# 24,68
CLKRUN# 24
2016/10/31modify
1 2
R1805 15R2F-2-GP
EC1801
12
DY
MEM_SMBDATA
84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
MEM_SMBCLK
DVT1 0210, Reserve by Intel MOW
SC10P50V2JN-4GP
SML1_SMBDATA
SML1_SMBCLK
SML0_SMBDATA
SML0_SMBCLK
SML1ALERT#
SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
ESPI_CLK 24,68
3D3V_S0
2N7002KDW-GP
6
5
Q1801
1
3D3V_S5_PCH
RN1807
1
8
2
7
3
6
45
SRN2K2J-4-GP
12
R1837150KR2J-GP
R1836
12
2K2R2J-2-GP
SRN2K2J-1-GP
23
1
4
RN1811
RN1810
23
3D3V_S0
1
4
SRN10KJ-5-GP
1
2
34
PCH_SMBDATA 99
PCH_SMBCLK 99
SML0_ALERT#
B B
PCH strap pin:
eSPI or LPC
SML0ALERT# /
GPP_C5
Sampled at rising edge of RSMRST#
This signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.
12
DY
R1823
1KR2J-1-GP
SC1P50V2CN-3-GP
2017/03/15
C1804
R1815 10MR2J-L-GP
2 3
1 2
1 2
X1802
41
XTAL-32D768KHZ-68-GP
82.30001.G01
This signal has a weak internal pull-down.
CPU1J
3D3V_S0
RN1813
1
2
3
4 5
SRN10KJ-6-GP
A A
2017/04/24
CLK_PCIE_NVME_REQ#
8
CLK_PCIE_SD_REQ#
7
CLK_PCIE_TBT_REQ#
6
CLK_PCIE_WLAN_REQ#
2016/11/04
GPU
WLAN
LAN
2016/11/04
SSD
WLAN_CLK_CPU#66
WLAN_CLK_CPU66
CLK_PCIE_WLAN_REQ#66
2016/11/04
2017/04/24
MSATA_CLK_CPU#63
MSATA_CLK_CPU63
CLK_PCIE_NVME_REQ#63
2017/04/24
CLK_PCIE_SD_REQ#
CLK_PCIE_TBT_REQ#
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKYLAKE-U-GP
071.SKYLA.000U
CLOCK SIGNALS
SKYLAKE_ULT
10 OF 20
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
SUSCLK_R
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTC_X1
RTC_X2
SRTC_RST#
RTC_RST#
1 2
R1813
0R0402-PAD
1 2
R1803
2K7R2F-GP
Intel recommend: 2.71k ohm 1%
RTCRST_ON24
+V1.00A_SIP
12
R1816
10KR2J-3-GP
PCIE_CLK_XDP_N 99
PCIE_CLK_XDP_P 99
SUS_CLK 24
+V1.05S_AXCK_LCPLL
Q1802
G
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
(#514849)
RTC_AUX_S5
D
21
12
G1801
GAP-OPEN
C1806
SC1U10V2KX-1DLGP
Layout: Place at the open door area.
5
4
3
2
RTC_X1
RTC_X2
12
C1803
SC1P50V2CN-3-GP
2017/03/15
1
23
RN1801
SRN20KJ-1-GP
4
12
C1805
SC1U10V2KX-1DLGP
2017/03/17
XTAL24_IN XTAL24_IN_R
R1839
1 2
0R0402-PAD-2-GP
2017/05/09
0R0402-PAD-2-GP
SUSCLK_R
1 2
PESD5V0U1BL-GP-U1
R1840
1 2
SRTC_RST#
RTC_RST#
20160816 EMI
ED1802
DY
PESD5V0U1BL-GP-U1
ED1801
DY
XTAL24_OUT
1 2
2016/12/14 vendor suggest
C1801
12
R1802
1MR2J-1-GP
XTAL24_OUT_L
12
U22
1 2
0R0402-PAD
X1801
U22
INPUT/OUTPUT#1
INPUT/OUTPUT#3
XTAL-24MHZ-135-GP
R1810
NC#2
XTAL24_OUT_R
1
2
3
082.30006.0041
SC18P50V2JN-1DLGP
U22
C1802
12
SC18P50V2JN-1DLGP
U22
EC1803
DY
1 2
SC4D7P50V2BN-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(LPC/SPI/SMBUS/CL/CLK)
CPU_(LPC/SPI/SMBUS/CL/CLK)
CPU_(LPC/SPI/SMBUS/CL/CLK)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
18 106Thursday, June 29, 2017
18 106Thursday, June 29, 2017
18 106Thursday, June 29, 2017
A00
A00
A00
5
4
3
2
1
SSID = PCH
Strap pin:
Port B /
Port C Detected
DDPB_CTRLDATA
D D
DDPC_CTRLDATA
These two signals have weak internal pull-down.
3D3V_S5
12
R1910
10KR2J-3-GP
fTPM
TPM_ID
12
R1911
10KR2J-3-GP
TPM
C C
Sampled at rising edge of PCH_PWROK
0 = Port B is not detected.
1 = Port B is detected.
*
0 = Port C is not detected.
1 = Port C is detected.
*
HDA_SYNC
HDA_BITCLK
HDA_SDOUT
HDA_SDIN027
HDA_RST#
TPAD14-OP-GP
TP1903
SPKR27
1
PROJECT_ID1
PROJECT_ID0
PROJECT_ID2
PROJECT_ID3
TPM_ID
CPU1G
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
AUDIO
SKYLAKE_ULT
7 OF 20
SDIO/SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
SD_RCOMP
1 2
R1901
200R2F-L-GP
KB_LED_BL_DET 65
2016/12/20
PCH strap pin:
Flash Descriptor Security Overide/
Intel ME Debug Mode
HDA_SDOUT
Low = Default
High = Enable
The internal pull-down is disabled after
PLTRST# deasserts
B B
1 2
EC1901
1 2
DY
SC10P50V2JN-4DLGP
HDA_RST#
ED1901
PESD5V0U1BL-GP-U1
DY
*
HDA_CODEC_BITCLK
2017/03/17
PCH strap pin:
NO REBOOT
Low = Enable (Default)
HDA_SPKR
The internal pull-down is disabled after
PLTRST# deasserts
*
HDA_CODEC_SYNC27
HDA_CODEC_BITCLK27
HDA_CODEC_SDOUT27
ME_FWP24
High = Disable
R1907,R1912 merge to RN1902
2015/10/06 modify
3D3V_S0
1 2
R1908 0R0402-PAD
SRN33J-5-GP-U
2 3
1
RN1902
1 2
R1909 1KR2J-1-GP
4
1 2
SKYLAKE-U-GP
1KR2J-1-GP
R2006
DY
HDA_SYNC
HDA_BITCLK
HDA_SDOUT
071.SKYLA.000U
SPKR
2016/11/01modify
2016/11/25 modify power rail
+V1.8A_SIP +V1.8A_SIP +V1.8A_SIP +V1.8A_SIP
3000/7000
12
12
5000
R1913
10KR2J-3-GP
PROJECT_ID0 PROJECT_ID1 PROJECT_ID2 PROJECT_ID3
R1912
10KR2J-3-GP
3000/5000
12
R1915
10KR2J-3-GP
12
R1914
10KR2J-3-GP
7000
Inspiron/Latitude
12
R1917
10KR2J-3-GP
12
R1916
10KR2J-3-GP
Vostro
Inspiron/Vostro
12
R1919
10KR2J-3-GP
12
R1918
10KR2J-3-GP
Latitude
HDA_CODEC_SDOUT
SC33P50V2JN-3DLGP
12
A A
DY
EC1903
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(AUDIO/SDIO/SDXC)
CPU_(AUDIO/SDIO/SDXC)
20160812 EMI
5
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(AUDIO/SDIO/SDXC)
KyloRen 13"
KyloRen 13"
KyloRen 13"
19 106Thursday, June 29, 2017
19 106Thursday, June 29, 2017
19 106Thursday, June 29, 2017
1
A00
A00
A00
5
SSID = PCH
3D3V_S0
D D
1 2
DEBUG
1 2
DEBUG
1 2
DY
1 2
1 2
1 2
1 2
3D3V_S5_PCH
1 2
R2040 10KR2J-3-GP
1 2
R2041 10KR2J-3-GP
C C
R204851KR2J-1-GP
R204951KR2J-1-GP
R204210KR2J-3-GP
R204310KR2J-3-GP
R204410KR2J-3-GP
R204510KR2J-3-GP
R204610KR2J-3-GP
UART_2_CRXD_DTXD
UART_2_CTXD_DRXD
BLUETOOTH_EN
DBC_PANEL_EN
FFS_INT2
KB_DET#
IR_CAM_DET#
RTC_DET#
SIO_EXT_W AKE#
2016/11/02 modify
Change to Dummy 20150402
2016/11/02 modify
Touch panel
10KR2J-3-GP
SPK_ID
10KR2J-3-GP
TOUCH_DETECT55
2016/12/23
PTP
3D3V_S0
R2047
SPK_ID1
R2036
SPK_ID2
RAM ID
Samsung
Hynix
MEM_CONFIG [0]Vender CapacityMfr. PN
0
0
MEM_CONFIG[1:2] MEM_CONFIG[3:4]
01 00 K4AAG165WB-BCRC 16G
01 16G10 H5ANAG6NAMR-UHC
DBC_PANEL_EN55
TP2018
TPAD14-OP-GP
SPK_ID29
BLUETOOTH_EN66
1 2
R2039
DY
0R2J-2-GP
UART_2_CRXD_DTXD68
UART_2_CTXD_DRXD68
SIO_EXT_W AKE#24
KB_DET#65
I2C0_SDA_TCH_PAD65
I2C0_SCL_TCH_PAD65
I2C0_SDA_TCH_PNL55
I2C0_SCL_TCH_PNL55
2017/04/24
12
12
for 15"
1
4
VRAM_ID1
NRB_BIT
GPP_B22
MEM_CONFIG0
MEM_CONFIG1
MEM_CONFIG2
MEM_CONFIG3
MEM_CONFIG4
MEM_CHA_EN
TOUCH_DETECT_R
BOARD_ID2
CPU1F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
SKYLAKE-U-GP
071.SKYLA.000U
Wistron. P/N
TBD
TBD
3
LPSS ISH
Strap
1.8V Only
SKYLAKE_ULT
GPP_D10/ISH_SPI_CLK
GPP_D11/ISH_SPI_MISO
GPP_D12/ISH_SPI_MOSI
GPP_D5/ISH_I2C0_SDA
1.8V Only
GPP_D13/ISH_UART0_RXD/SML0BDATA
GPP_D14/ISH_UART0_TXD/SML0BCLK
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
10KR2J-3-GP
MEM_CONFIG0 MEM_CONFIG1
10KR2J-3-GP
GPP_D7/ISH_I2C1_SDA
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D15/ISH_UART0_RTS#
GPP_A12/BM_BUSY#/ISH_GP6
12
R2016
SDP
12
R2015
DDP
6 OF 20
GPP_D9/ISH_SPI_CS#
GPP_D6/ISH_I2C0_SCL
GPP_D8/ISH_I2C1_SCL
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
USB_UART_SEL_D9
RTC_DET#
ISH_I2C0_SDA
ISH_I2C0_SCL
I2C1_SDA
I2C1_SCL
MEM_CHB_EN
2017/04/24
VRAM_ID2
UART0_RTS#
UART0_CTS#
BOARD_ID1
UART1_RTS#
UART1_CTS#
ISH_KB_DISABLE
GSEN_INT1_ISH
GSEN_INT2_ISH
GSEN2_INT1_ISH
GSEN2_INT2_ISH
GYRO_INT_ISH
GYRO_DRDY_ISH
R2018
10KR2J-3-GP
R2017
10KR2J-3-GP
1
R2021
R2020
1
1
1
1
12
8GB
12
4GB/16GB
TP2006 TPAD14-OP-GP
1 2
0R0402-PAD
1 2
0R0402-PAD
2016/12/28
TP2012 TPAD14-OP-GP
TP2014 TPAD14-OP-GP
FFS_INT2 70
TP2016 TPAD14-OP-GP
TP2017 TPAD14-OP-GP
R2023
1 2
R2024
1 2
1 2
R2025 0R2J-2-GP
1 2
R2026 0R2J-2-GP
1 2
R2027 0R2J-2-GP
1 2
R2028 0R2J-2-GP
DY
2017/05/08
MEM_CONFIG2
2
IR_CAM_DET# 55
RTC_DET# 25
SENSOR_I2C_SDA 55,70
SENSOR_I2C_SCL 55,70
2017/03/15
0R0402-PAD
0R0402-PAD
R2029
10KR2J-3-GP
R2022
10KR2J-3-GP
+V1.8A+V1.8A+V1.8A
12
16GB
12
4GB/8GB
3D3V_S0
RN2007
ISH_I2C0_SCL
ISH_I2C0_SDA
I2C1_SDA
I2C1_SCL
(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
to the same voltage rail as the device/end point.
GYRO_DRDY_ISH
GSEN_INT1 55
GSEN_INT2 55
GSEN2_INT1_C 70
GSEN2_INT2_C 70
GYRO_INT_C 70
GYRO_DRDY 55
3D3V_S5
12
2IN1
(PDG#543016) If the UART/GPIO functionality is also not used,
the signals can be left as no-connect.
R2001
10KR2F-2-GP
KB_DISABLE_CPU_R
SRN1KJ-7-GP
1
2 3
SRN2K2J-1-GP
2 3
1
RN2008
R2052
10KR2J-3-GP
R2051
10KR2J-3-GP
Vth(max)=1.1V
Q2001
6
D1
G2
4 3
S2
PJT138KA-GP
DY
1D8V_S0
12
DY
12
DY
2IN1
S1
G1
D2
4
4
2017/03/17
1
25
1
ISH_KB_DISABLE
NB_MODE# 24
075.00138.0A7C
3D3V_S5
R2050
Micron
Samsung
Hynix
B B
Micron
Samsung
Hynix
Micron
PCH strap pin:
No Reboot
GSPI0_MOSI /
A A
GPP_B18
0
1
01 01 MT40A1G16WBU-083E 16G
10 00
1 10
1 10
1
1
1
Sampled at rising edge of PCH_PWROK
0 = Disable āNo Rebootā mode.
1 = Enable āNo Rebootā mode (PCH will disable the TCO
Timer system reboot feature). This function is useful
when running ITP/XDP.
00
00
00
072.40116.0B0U
K4A8G165WB-BCRC
10
01
00
10
01
PCH Prim
3D3V_S5_PCH 3D3V_S0 3D3V_S0
12
R2007
DY
1KR2J-1-GP
H5AN8G6NAFR-UHC
MT40A512M16JY-083E
K4A4G165WE-BCRC
H5AN4G6NBJR-UHC*
MT40A256M16GE-083E
2IN1
TBD
TBD
072.40512.0B0U
072.44165.0B0U
TBD
072.40256.0A0U
12
R2005
10KR2J-3-GP
8G
8G
8G
4G
4G
4G
12
KBL-U
R2010
10KR2J-3-GP
MEM_CONFIG3 MEM_CONFIG4
+V1.8A +V1.8A
12
R2011
10KR2J-3-GP
10KR2J-3-GP
Hynix
12
R2012
Samsung/Micron
12
R2013
10KR2J-3-GP
Micron
12
R2014
10KR2J-3-GP
Samsung/Hynix
2016/11/07 modify
3D3V_S0
12
UMA Board /4GB VRAM
R2038
10KR2J-3-GP
MEM_CHA_EN
MEM_CHB_EN
R2031
10KR2J-3-GP
R2030
10KR2J-3-GP
R2033
10KR2J-3-GP
R2032
10KR2J-3-GP
+V1.8A
12
12
DY
+V1.8A
12
12
DY
3D3V_S0
12
UMA Board
R2035
10KR2J-3-GP
NB_MODE#
2IN1
CLAM
10KR2J-3-GP
1 2
R2002
10KR2J-3-GP
1 2
The signal has a weak internal pull-down.
<Core Design>
<Core Design>
NRB_BIT
12
R2019
DY
1KR2J-1-GP
5
4
BOARD_ID2
CLAM
12
R2008
10KR2J-3-GP
BOARD_ID1
KBL-R
12
R2009
10KR2J-3-GP
VRAM_ID2
12
R2037
10KR2J-3-GP
2GB VRAM
3
VRAM_ID1
4GB VRAM
2
12
R2034
10KR2J-3-GP
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(LPSS/ISH)
CPU_(LPSS/ISH)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(LPSS/ISH)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
20 106Thursday, June 29, 2017
20 106Thursday, June 29, 2017
20 106Thursday, June 29, 2017
A00
A00
A00
5
4
3
2
1
SSID = PCH
For eSPI
D D
EC2101
12
+V3.3A_SIP
C C
C2120
SCD1U25V2KX-1-DL-GP
DY
12
R2101
0R0402-PAD
SC1U10V2KX-1DLGP
+VCCMPHYGTAON_1P0_LS_SIP
+VCCAMPHYPLL_1P0
1 2
+VCCMPHYGTAON_1P0_LS_SIP
+VCCMPHYGTAON_1P0_LS_SIP
+V1.00A_SIP
+VCCPRIM_CORE
+VCCDSW _1P0
+V1.00A_SIP
+VCCAPLL_1P0
+V1.00A_SIP
+VCCPDSW_3P3
+VCCPAZIO
+V3.3A_SIP
+V3.3A_SIP
+V1.00A_SIP
2.57A
CPU1O
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
SKYLAKE-U-GP
CPU POWER 4 OF 4
SKYLAKE_ULT
1.8V Only
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCRTCPRIM_3P3
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
071.SKYLA.000U
15 OF 20
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCATS_1P8
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
+V1.8A_SIP
+V3.3A_SIP
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+V1.8A_SIP
+V3.3A_SIP
+V1.00A_SIP
+V1.8A_SIP
+V3.3A_SIP
VCCRTCEXT
+V1.00A_SIP
+VCCCLK2
+V1.00A_SIP
+VCCCLK4
+VCCCLK5
+V1.00A_SIP
V0.85A_VID0
V0.85A_VID1
+VCCPRTC_3P3
1 2
C2112 SCD1U25V2KX-1-DL-GP
1
1
DELETE, 20160810 Nick
TP2101 TPAD14-OP-GP
TP2102 TPAD14-OP-GP
+VCCPRTC_3P3
1 2
Layout Note:
0.1uF:
C2117
C2118
SCD1U25V2KX-1-DL-GP
SC1U10V2KX-1DLGP
12
C2118 near AK19
1uF:
C2117 near Ak19
+VCCPRTC_3P3RTC_AUX_S5
1 2
R2106
0R0603-PAD
1 2
R2107
0R0603-PAD
1 2
R2108
0R0603-PAD
1 2
R2109
0R0603-PAD
1 2
R2110
0R0603-PAD
1 2
R2111
0R0603-PAD
+VCCAMPHYPLL_1P0+VCCMPHYGTAON_1P0_LS_SIP
+VCCAPLL_1P0+V1.00A_SIP
+VCCCLK2+V1.00A_SIP
+VCCCLK4+V1.00A_SIP
+VCCCLK5+V1.00A_SIP
+V3.3A_SIP
B B
C2105
12
SC1U10V2KX-1DLGP
12
+VCCAMPHYPLL_1P0
C2106
SC1U10V2KX-1DLGP
C2107
12
C2113
SC22U6D3V3MX-1-GP
12
C2109
SC1U10V2KX-1DLGP
12
Layout Note:
22uF:
C2113 near K15
SC1U10V2KX-1DLGP
C2110
SCD1U25V2KX-1-DL-GP
12
12
DY
A A
5
Layout Note:
1uF:
C2111
SCD1U25V2KX-1-DL-GP
C2105 near V19
C2106 near AK17
C2107 near AG15
C2109 near Y16
C2110 near T16
C2111 near AJ19
+VCCAPLL_1P0 +V1.00A_SIP
12
C2114
SC22U6D3V3MX-1-GP
Layout Note:
22uF:
C2113 near K15
DY
4
+V1.8A_SIP
12
C2108
SC1U10V2KX-1DLGP
DY
+VCCCLK2
C2116
SC1U10V2KX-1DLGP
12
+VCCDSW _1P0
C2103
+VCCCLK4
12
12
C2119
SC1U10V2KX-1DLGP
+VCCCLK5
SC22U6D3V3MX-1-GP
12
C2102
SC1U10V2KX-1DLGP
12
C2115
SC22U6D3V3MX-1-GP
12
+V1.00A_SIP+VCCPRIM_CORE
C2101
SC1U10V2KX-1DLGP
C2104
12
SC1U10V2KX-1DLGP
12
12
C2121
SC1U10V2KX-1DLGP
Layout Note:
1uF:
C2101 near AB19
C2104 near K17
C2116 near A10
C2121 near AL1
Layout Note:
1uF:
SC22U6D3V3MX-1-GP
3
C2116 near A10
22uF:
C2115 near K19
C2119 near N20
C2122 near L19
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(POWER1)
CPU_(POWER1)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU_(POWER1)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
21 106Thursday, June 29, 2017
21 106Thursday, June 29, 2017
21 106Thursday, June 29, 2017
A00
A00
A00
C2122
5
4
3
2
1
SSID = PCH
D D
CPU1T
SKYLAKE_ULT
SPARE
AW69
AW68
AU56
AW48
XTAL24_OUT_U42
C C
C7
U12
U11
H11
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11
SKYLAKE-U-GP
20 OF 20
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
F6
E3
C11
B11
A11
D12
C12
F52
XTAL24_IN_U42
071.SKYLA.000U
XTAL24_IN_U42
R2203
1 2
0R0402-PAD-2-GP
2017/05/09
XTAL24_IN_U42_R
R2201
1MR2J-1-GP
12
U42
X2201
U42
INPUT/OUTPUT#1
NC#2
INPUT/OUTPUT#3
XTAL-24MHZ-135-GP
U42
1
2
3
082.30006.0041
C2201
12
SC15P50V2JN-DL-GP
2017/03/07
B B
XTAL24_OUT_U42
A A
5
4
R2204
1 2
0R0402-PAD-2-GP
XTAL24_OUT_U42_L
3
R2202
1 2
0R0402-PAD
U42
XTAL24_OUT_R_U42
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
C2202
12
SC15P50V2JN-DL-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(RSVD)
CPU_(RSVD)
CPU_(RSVD)
KyloRen 13"
KyloRen 13"
KyloRen 13"
A00
A00
A00
22 106Thursday, June 29, 2017
22 106Thursday, June 29, 2017
22 106Thursday, June 29, 2017
1
SSID = PCH
5
4
3
2
1
CPU1Q
CPU1P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND 1 OF 3
SKYLAKE_ULT
D D
A5_TP
A67_TP
A70_TP
A67
A70
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
A5
TP2309TPAD14-OP-GP
TP2311TPAD14-OP-GP
TP2310TPAD14-OP-GP
C C
B B
1
1
1
16 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AV1_TP
TP2307TPAD14-OP-GP
TP2304TPAD14-OP-GP
TP2312TPAD14-OP-GP
TP2305TPAD14-OP-GP
TP2306TPAD14-OP-GP
1
1
1
1
1
AV71_TP
B71_TP
BA1_TP
BA2_TP
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKYLAKE-U-GP
SKYLAKE_ULT
17 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
BA71_TP
BB67_TP
BB70_TP
C1_TP
E71_TP
1
TP2303 TPAD14-OP-GP
1
TP2302 TPAD14-OP-GP
1
TP2301 TPAD14-OP-GP
1
TP2308 TPAD14-OP-GP
1
TP2313 TPAD14-OP-GP
CPU1R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKYLAKE-U-GP
GND 3 OF 3
SKYLAKE_ULT
G10
G22
G43
G45
G48
G5
G52
G55
G58
G6
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
F8
071.SKYLA.000U
18 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
071.SKYLA.000U
SKYLAKE-U-GP
071.SKYLA.000U
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(VSS)
CPU_(VSS)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(VSS)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
23 106Thursday, June 29, 2017
23 106Thursday, June 29, 2017
23 106Thursday, June 29, 2017
A00
A00
A00
SSID = KBC
5
3D3V_S5 3D3V_S5_KBC 3D3V_S5_KBC
1D0V_S5
1 2
R2402
0R0402-PAD
Just for Starload placement
2015/09/23 modify
8
KSO3
7
KSO1
6
KSO2
KSO0
8
KSO5
7
KSO4
6
KSO7
KSO6
8
KSO11
7
KSO10
6
KSO12
KSO8
8
KSO15
7
KSO13
6
KSO14
KSO16
2016/12/23
12
R2465
10KR2F-2-GP
DY
FPR_SCAN#
10KR2F-2-GP
Layout Note:
Need very close to EC
3D3V_S5_KBC
10KR2F-2-GP
2017/03/14
D D
3D3V_S5_KBC
RN2412
1
2
3
4 5
SRN100KJ-5-G P
RN2409
1
2
3
4 5
SRN100KJ-5-G P
RN2410
1
2
3
4 5
SRN100KJ-5-G P
RN2411
1
2
3
4 5
SRN100KJ-5-G P
C C
2016/12/13
3D3V_S0 3D 3V_S5
12
R2458
12
R2460
DY
2016/12/22
RUNPWROK assert,
delay 10ms; PCH_PWROK assert.
RN2403
1
2
3
4 5
SRN10KJ-6-G P
RN2404
1
2
3
4 5
SRN10KJ-6-G P
SIO_SLP_S0#17,40,91
For eSPI
FPR_SCAN#92
12
VREF_CPU
8
7
6
8
7
6
PRIM_PWRG D40,54
PCH_RSMRS T#17,99
C2406
SCD1U25V2KX-1-DL-GP
KSI2
KSI1
KSI3
KSI0
KSI7
KSI6
KSI4
KSI5
2016/11/4
2017/01/24
12
12
C2421
C2416
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
1 2
0R0402-PAD
2016/12/28
CLKRUN#18
USB_POW ERSHARE_VB US_EN34
SUS_CLK18
2016/12/22
12
12
C2412
C2411
SCD1U25V2KX-1-DL-GP
Just for Starload placement
2015/09/23 modify
RTCRST_O N18
AC_DIS43
TP_WAKE_K BC#4,65
RUNPW ROK17,40
RESET_OUT #17,26
R2461 0R2J-2- GP
R2481
CCG4_I2C_INT#37
C2420
SCD1U25V2KX-1-DL-GP
ESPI_CS#18,68
MASK_SATA_LED#64
ESPI_CLK18,68
ESPI_ALERT#18
ESPI_RESET#18,68
LID_CL_SIO#70
SYS_PWROK17,99
PBAT_PRES#43,44
2016/12/22
12
B B
For eSPI
GPIO123 (BSS_STRAP)GPIO102 (CR_STRAP)
3D3V_S5_KBC
Already pull low
1 2
DY
1 2
R2452
100KR2J-1-GP
KSO9
R2453
100KR2J-1-GP
TP2402
on CPU side
PCH_RSMRS T#
1
TPAD14-OP-G P
ESPI_ALERT#
1 2
R2464 10KR2J -3-GP
2017/05/08
1 2
R2446
0R0603-PAD
12
12
12
C2414
C2410
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
KSO[0..16]65
KSI[0..7]65
CLK_TP_SIO65
DAT_TP_SIO65
SIO_PWRBTN #17,99
ESPI_IO[3..0]18,68
1 2
R2439 10KR2F- 2-GP
DY
2017/03/14
2017/03/14
1 2
DY
X2401
41
2 3
XTAL-32D768KH Z-68-GP
82.30001.G01
C2425
SC6P50V2CN- 1-NL-GP
Microchip: Use CL=9p Xtalļ¼C = 10p
PANEL_BKEN55
1D8V_S5_KBC
DY
2017/03/21
C2413
12
EC2403
EC2402
DY
DY
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
C2428
SCD1U25V2KX-1-DL-GP
12
2
KSO0
14
KSO1
15
KSO2
16
KSO3
37
KSO4
38
KSO5
39
KSO6
50
KSO7
46
KSO8
68
KSO9
72
KSO10
74
KSO11
75
KSO12
76
KSO13
77
KSO14
86
KSO15
92
KSO16
CAP_LED#
93
98
KSI0
99
KSI1
6
KSI2
7
KSI3
104
KSI4
105
KSI5
107
KSI6
108
KSI7
78
79
52
EC_SLP_S0IX#
88
ESPI_IO0
59
ESPI_IO1
60
ESPI_IO2 ICSP_DAT
61
ESPI_IO3
62
58
56
57
CLKRUN#_EC
63
55
10
TP_EN#
49
53
66
32
28
29
30
31
27
BKLT_IN_EC
67
69
71
42
33
3
USB_EN#
13
48
73
MEC_XTAL2
125
MEC_XTAL1_R
123
C2424
SC6P50V2CN- 1-NL-GP
R2498 0R2J-2- GP
12
12
12
2016/12/29
83.R2004.G8F
83.R2004.G8F
4
If don't need RTC alarm wake up,
can change to 3D3V_AUX_S5
RTC_AUX_S5
R2472
0R0402-PAD
1 2
+RTC_CELL_V BAT
PANEL_BKEN_EC
2017/03/07
L_BKLT_EN_L
VSS_VBAT
84
124
1 2
0R0402-PAD
DY
R2440
122
R2445
1 2
0R2J-2-GP
1 2
KBC24
GPIO027/KSO00/PVT_IO1
GPIO015/KSO01/PVT_CS#
GPIO016/KSO02/PVT_SCLK
GPIO017/KSO03/PVT_IO0
GPIO045/BCM_INT1#/KSO04
GPIO046/BCM_DAT1/KSO05
GPIO047/BCM_CLK1/KSO06
GPIO025/KSO07/PVT_IO2
GPIO055/PWM2/KSO08/PVT_IO3
GPIO102/KSO09/CR_STRAP
GPIO106/KSO10
GPIO110/KSO11
GPIO111/KSO12
GPIO112/PS2_CLK1A/KSO13
GPIO113/PS2_DAT1A/KSO14
GPIO125/KSO15
GPIO132/KSO16
GPIO140/KSO17
GPIO143/KSI0/DTR#
GPIO144/KSI1/DCD#
GPIO005/SMB00_DATA/SMB00_DATA18/KSI2
GPIO006/SMB00_CLK/SMB00_CLK18/KSI3
GPIO147/KSI4/DSR#
GPIO150/KSI5/RI#
GPIO151/KSI6/RTS#
GPIO152/KSI7/CTS#
GPIO114/PS2_CLK0
GPIO115/PS2_DAT0
GPIO026/PS2_CLK1B
GPIO127/PS2_DAT1B
GPIO040/LAD0/ESPI_IO0
GPIO041/LAD1/ESPI_IO1
GPIO042/LAD2/ESPI_IO2
GPIO043/LAD3/ESPI_IO3
GPIO044/LFRAME#/ESPI_CS#
GPIO064/LRESET#
GPIO034/PCI_CLK/ESPI_CLK
GPIO067/CLKRUN#
GPIO063/SER_IRQ/ESPI_ALERT#
GPIO011/SMI#/EMI_INT#
GPIO060/KBRST
GPIO061/LPCPD#/ESPI_RESET#
GPIO100/EC_SCI#
GPIO126/SHD_SCLK
GPIO133/SHD_IO0
GPIO134/SHD_IO1
GPIO135/SHD_IO2
GPIO136/SHD_IO3
GPIO123/SHD_CS#
GPIO101/SPI_CLK
GPIO103/SPI_IO0
GPIO105/SPI_IO1
GPIO052/SPI_IO2
GPIO062/SPI_IO3
GPIO001/SPI_CS#/32KHZ_OUT
RESET_IN#/GPIO014
GPIO057/VCC_PWRGD
GPIO107/RESET_OUT#
XTAL2
XTAL1
MEC1416-NU- D0-GP
1 2
DY
D2401
K A
RB751V-40H-G P
DY
D2404
K A
RB751V-40H-G P
R2499
1 2
DY
2KR2F-L1-GP
BKLT_IN_EC
2017/03/14
For eSPI
+V1.8A
43
103
VTR5VTR19VTR
VTR65VTR82VTR
VBAT
GPIO007/SMB01_DATA/SMB01_DATA18
GPIO010/SMB01_CLK/SMB01_CLK18
GPIO012/SMB02_DATA/SMB02_DATA18
GPIO013/SMB02_CLK/SMB02_CLK18
GPIO130/SMB03_DATA/SMB03_DATA18
GPIO131/SMB03_CLK/SMB03_CLK18
GPIO141/SMB04_DATA/SMB04_DATA18
GPIO142/SMB04_CLK/SMB04_CLK18
VSS17VSS51AVSS
VSS
VSS64VSS
100
GPIO050/TACH0
GPIO051/TACH1
GPIO053/PWM0
GPIO054/PWM1
GPIO056/PWM3
GPIO030/BCM_INT0#/PWM4
GPIO031/BCM_DAT0/PWM5
GPIO032/BCM_CLK0/PWM6
GPIO002/PWM7
GPIO157/LED0/TST_CLK_OUT
GPIO156/LED1
GPIO104/LED2
GPIO116/TFDP_DATA/UART_RX
GPIO117/TFDP_CLK/UART_TX
GPIO035/SB-TSI_CLK
GPIO033/PECI_DAT/SB_TSI_DAT
GPIO145/ICSP_CLOCK
GPIO146/ICSP_DATA
BGPO/GPIO004
SYSPWR_PRES/GPIO003
VCI_OUT/GPIO036
VCI_IN1#/GPIO162
VCI_IN0#/GPIO163
VCI_OVRD_IN/GPIO164
GPIO160/DAC_0
GPIO161/DAC_1
GPIO124/CMP_VOUT0
GPIO020/CMP_VIN0
GPIO165/CMP_VREF0
GPIO120/CMP_VOUT1
GPIO021/CMP_VIN1
GPIO166/CMP_VREF1/UART_CLK
GPIO024/ADC7
GPIO023/ADC6/A20M
GPIO022/ADC5
GPIO153/ADC4
GPIO154/ADC3
GPIO155/ADC2
GPIO122/ADC1
GPIO121/ADC0
VR_CAP
18
112
EC_AGND
VR_CAP
C2418
SC1U10V2KX-1DLGP
12
Layout Note:
EC_AGND
Connect GND and AGND planes via either
0R resistor or connect directly.
2016/12/28 modify follow 15"
eDP backlight
Control from EC
R2427
0R0402-PAD
2017/05/08
1D8V_S5_KBC
R2462
12
0R0402-PAD
12
C2423
SCD1U25V2KX-1-DL-GP
54
VTR_33_18
8
9
11
12
89
91
96
97
40
41
44
45
47
34
35
36
4
1
106
70
80
81
90
94
95
VREF_CPU
101
102
87
ICSP_MCLR
119
120
121
126
127
128
23
24
22
DAC_VREF
85
20
25
83
21
26
118
117
116
109
110
111
113
114
115
ADC_VREF
L_BKLT_EN 8,24
eDP backlight
Control from PCH
L_BKLT_EN 8,24
12
R2455
100KR2J-1-GP
GPU_THM_SMBD AT
GPU_THM_SMBC LK
TYPEC_SMBDA
TYPEC_SMBCLK
FAN1_TACH
SIO_SLP_S4#_EC
SIO_SLP_S3#_EC
PCIE_WAKE#
BAT2_LED#
BAT1_LED#
H_PECI
VREF_CPU
ICSP_CLK
ICSP_CLR
SYSPWR_PR ES
ALWON
POWER_S W_IN#
HW_ACA VIN_NB
CMP_VOUT0
CMP_VIN0
VCREF0
PROCHOT
CMP_VIN1
LCD_TST
PANEL_BKEN_EC
MODEL_ID
I_ADP
BOARD_ID
I_BATT
3D3V_S5_KBC
12
C2422
EC_AGND
SCD1U25V2KX-1-DL-GP
3
2016/11/08modify
VOLTAGEPULL-HIGH RESISTORPULL-LOW RESISTORBOARD_ID VERSION A/D
3.0V
2.801V
2.598V
2.402V
2.201V
2.001V
1.808V
1.594V100.0K
1.299V
1.100V
Change symbol part number, because origin symbol is DELL OBS part
D2403
RB751V-40H-G P
KA
FAN_TACH 1 26
83.R2004.G8F
+RTC_CELL_V BAT
R2497
100KR2J-1-GP
EC_VCIN1#EC_VCIN1#
USB_EN#
HW_ACA VIN_NB
I_ADP
12
EC_AGND
CMP_VIN1
12
DY
C2436
1 2
R2401 0R2J-2- GP
R2421
330R2J-3-GP
C2435
SC2200P50V2KX-2D LGP
SC2200P50V2KX-2GP
20150116 2040Change symbol part number, because origin symbol is DELL OBS part
DY
R2475
0R0402-PAD
12
12
12
12
DY
PR2455
150KR2F-L-GP
12
DY
R2457
115KR2F-GP
EC_AGNDEC _AGND
1 2
Vref = 1.117
temp around 85
12
R2448
10KR2F-2-GP
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
D2402
RB751V-40H-G P
K A
R2430
10KR2J-3-GP
3D3V_AUX_S5
DY
A00
BOARD_ID
C2408
TBD,20160518 TBD,20160518
CPU/ Thermal
For CCG4/I2C/USB Mux
1 2
R2409 0R2J-2- GP
DY
1 2
R2479 0R2J-2- GP
DY
R2406
1 2
0R0402-PAD
2016/12/28
1 2
R2437
SC100P50V2JN-3DLGP
43R2J-GP
C2405
12
DY
Need very close to EC, PDG: <0.5 inches.
SCD1U25V2KX- 1-DL-GP
C2429
1 2
R2470 0R0402-P AD
12
12
R2494 0R2J- 2-GP
DY
Reserve resistor, 20141118
PCB_REV
12
R2443
82K5R2F-GP
2017/05/02
12
SCD1U25V2KX-1-DL-GP
R2444
12
100KR2F-L1-GP
EC_AGND
PBAT_CHG_SM BDAT 43,44
PBAT_CHG_SM BCLK 43,44
AUX_EN_W OWL 17,61
KB_LED_PW M 65
BEEP 27
FAN1_PWM 26
SIO_SLP_S3# 17,4 0,51
PS_ID 43
PCIE_WAKE#_C PU 17
BREATH_LED # 66
ME_FWP 19
HOST_DEBU G_TX 68
PTP_DIS# 65
PECI 4
NB_MUTE# 27
ALWON 40
HW_ACA V_IN 44
3D3V_S5_KBC
CMP_VOUT0 26
CMP_VIN0_R 24,26
LCD_TST 55
USB_PWR _SHR_EN_L# 34
SIO_EXT_WAKE # 20
CMP_VIN0_R 24,26
LCD_VCC_T EST_EN 55
I_BATT AD_IA
12
C2441
SC2200P50V2KX-2D LGP
DY
EC_AGND
KyloRen_X00
KyloRen_X01
KyloRen_X02
KyloRen_X03
KyloRen_X04
KyloRen_X05
KyloRen_A00
KyloRen_A01
KyloRen_A02
KyloRen_A03
BATTER /CHARGER
NB_MODE# 20
LID_CL_SIO_TAB# 70
3D3V_S5_KBC
R2424
20KR2F-L-GP
12
C2409
SCD01U50V2KX-1DLGP
R2423
12
DY
330R2J-3-GP
Layout Note:
Need very close to EC
Need very close to EC
LID_CL_SIO#
83.R2004.G8F
10.0K
17.8K
27.0K
37.4K
49.9K
64.9K
82.5K
107K
154K
200KK
3D3V_S0
1 2
2017/03/09
12
R2463
1KR2J-1-GP
12
R2454
100KR2J-1-GP
TOUCH_R EPORT_SW 55
2
MODEL_ID
Nick 2016/05/16 modify
3D3V_S5
12
R2434
100KR2J-1-GP
USB_EN# 35,66
AC_IN#_G 43
DC_IN_OK 43
2017/05/10For Typec charge detect modify
AD_IA 44
3D3V_S5
12
MODEL_ID
C2407
SCD1U25V2KX-1-DL-GP
12
12
EC_AGND
CHG_AMBER_L ED#64
Q2412 and Q2413 merge
24014/12/23 modify
GPU_THM_SMBD AT
GPU_THM_SMBC LK
CCG4_I2C_SDA37
CCG4_I2C_SCL37
MODEL_ID_DET(GPIO07) PULL-HIGH RESISTORPULL-LOW RESISTOR
TBD
KyloRen 13" UMA Clamshell
KyloRen 13" UMA 2in1
R2442
27KR2F-L-GP
R2441
100KR2F-L1-GP
TBD
KyloRen 15" UMA Clamshell
KyloRen 15" UMA 2in1
TBD
KyloRen 15" DIS Clamshell
KyloRen 15" DIS 2in1
2016/11/07modify
2016/12/06 follow 15"
1 2
R2447
R2459
R2489
100KR2J-1-GP
1
2
3 4
S
G
Q2414
1 2
2016/12/28
1 2
Q2416
6
5
2N7002KDW -GP
84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
D
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
0R0402-PAD
0R0402-PAD
3 4
2
1
BAT2_LED#
3D3V_S5 3D3V_S5
3D3V_S0
CAP_LED#
3D3V_S0
84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
LID_CL_SIO_TAB#
2N7002K-2-GP
84.2N702.J31
SML1_SMBDATA
SML1_SMBCLK
3D3V_S5_KBC
Q2605
5
TypeC
6
2N7002KDW -GP
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K 154K()
100.0K 200K()
17.8K()
27.0K()
37.4K() 2.402V
49.9K()
82.5K()
107K()
3D3V_S5
R2496
100KR2J-1-GP
1 2
BATT_WH ITE_LED# 64
BAT1_LED#
Reserve by NON DS3 function 20150413
1
LID_CL_SIO#
TP_EN#65
CAP_LED#_R 65
SML1_SMBDATA 18,26
SML1_SMBCLK 18,26
RN2604
SRN2K2J-1-G P
VOLTAGE
3.0V10.0K(64.10025.6DL)
2.801V
2.598V
2.201V
2.001V64.9K()
1.808V
1.594V
1.299V
1.100V
3D3V_S5_KBC
1
23
TypeC
4
RN2405
1
2
3
4 5
SRN100KJ-5-G P
3D3V_S5
8
7
6
TYPEC_SMBDA 38
TYPEC_SMBCLK 38
A A
R2418
0R2J-2-GP
1 2
R2417
100KR2J-1-GP
PROCHOT
12
DY
DY
Q2408
G
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
D
5
2015/09/22 modify
12
ED2403
DY
AZ5725-01FDR7G-GP
H_PROCHO T# 4,44,46
2017/03/17
PBAT_CHG_SM BCLK
PBAT_CHG_SM BDAT
USB_PWR _SHR_EN_L#
PBAT_PRES#
RN2402
4
SRN4K7J-8-G P
1 2
R2473 10KR2J-3- GP
1 2
R2415 10KR2J-3- GP
Just for Starload placement
2015/09/23 modify
3D3V_S5_KBC
23
1
3D3V_S5_KBC
4
3D3V_S5_KBC
3D3V_S5_KBC
DY
R2414
1 2
R2480
100KR2J-1-GP
ICSP_CLK
ICSP_DAT
1 2
HOST_DEBU G_TX
4K7R2J-2-GP
ICSP_CLR
3D3V_S5_KBC
DB3
7
1
2
3
LPC
4
5
6
8
20.K0691.006
ACES-CON 6-58-GP
Power Switch Logic(PSL)
KBC_PWR BTN#66
3
R2432
1KR2J-1-GP
12
12
C2427
SC2D2U10V3KX- 1DLGP-U
2017/05/15
2016/12/20 modify
+RTC_CELL_V BAT
R2451
100KR2J-1-GP
1 2
POWER_S W_IN#
12
C2426
SC1U10V2KX-1D LGP
<Core Desig n>
<Core Desig n>
DY
2
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
KBC Nuvoton NPCE285PA0DX
KBC Nuvoton NPCE285PA0DX
KBC Nuvoton NPCE285PA0DX
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Taipei Hsie n 221, Taiwan, R.O. C.
24 106
24 106
24 106
A00
A00
A00
5
SSID = SPI Flash
4
3D3V_S5_PCH
3
2
1
12
R2515
SPI Flash ROM(8M) for PCH
3D3V_SPIVCC13D3V_S5_PCH
0R0402-PAD
72.12873.001
72.25128.0E1
D D
SC10U10V5KX-2DLGP
R2501
4K7R2J-2-GP
1 2
SPI25
SPI_CS_ROM_N018
SPI_WP_ROM_R
12
SC4D7P50V2BN-GP
R2506
1 2
C C
SPI_SO_ROM18,91
SPI_WP_ROM18,99
10R2J-2-GP
R2507
10R2J-2-GP
1 2
SPI_SO_ROM_R
SPI_WP_ROM_R
EC2502
DY
1
CS#
2
SO/SIO1
3
SIO2
4
GND
MX25L12873FM2I-10G-GP
SI/SIO0
72.12873.001
2nd = 72.25128.0E1
VCC
SIO3
SCLK
8
7
6
5
SPI_HOLD_ROM_RSPI_SO_ROM_R
SPI_CLK_ROM_R
SPI_SI_ROM_R
3D3V_SPIVCC1
12
DY
EC2501
SC4D7P50V2BN-GP
12
C2501
DY
R2503 10R2F-L-GP
12
DY
12
C2502
SCD1U16V2KX-3DLGP
DY
1 2
SPI_CLK_ROM_R
SPI_SI_ROM_R
EC2503
SC10P50V2JN-4GP
Change to Dummy 20150402
SPI_HOLD_ROM 18
R2508
R2509
1 2
1 2
10R2J-2-GP
10R2J-2-GP
2016/12/28
SPI_CLK_ROM 18,91
SPI_SI_ROM 18,91
QUAD/DUAL fast read DUAL fast readSource
O
O
O
O
O O
SFDP
O
O
O
2016/12/28
Main Func = RTC
Delivery Voltage 3.19V
3D3V_AUX_S5
12
R2505
1K6R2F-GP
B B
3D3V_RTC_SYS
12
R2517
47KR2F-GP
D2501
1
2
BAS40C-2-GP
75.00040.07D
2nd = 75.00040.C7D
3rd = 75.00040.A7D
A A
12
R2504
10MR2J-L-GP
5
4
Q2505
G
D
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
RTC_AUX_S5+RTC_VCC
3
12
C2503
SCD47U25V3KX-1-DL-GP
<Core Design>
<Core Design>
<Core Design>
RTC_DET# 20
3
Title
Title
Title
Flash/RTC
Flash/RTC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Flash/RTC
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
25 106
25 106
25 106
1
5
4
3
2
1
SSID = Thermal Sensor
3D3V_S0 3D3V_S0
1
23
RN2602
SRN2K2J-1-GP
3D3V_S0
SML1_SMBDATA18,24
12
12
D D
DY
C2601
C2602
SCD1U25V2KX-1-DL-GP
84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
7718
SC10U6D3V3MX-GP
2016/12/21 change PN
84.T3904.K11
7718
C
Q2603
E
B
NCT7718_DXP
12
C2606
SC470P50V3JN-2GP
DY
NCT7718_DXN
7718
12
C2607
SC2200P50V2KX-2DLGP
2.System Sensor, Put on palm rest
MMBT3904-5-GP-U
Layout Note:
C2607 close THM2601
Layout Note:
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.
3D3V_S0
C C
1 2
R2603 7K5R2F-1-GP
7718
1 2
R2604 7K5R2F-1-GP
7718
R2601
0R2J-2-GP
ALERT#
T_CRIT#
12
DY
T_CRIT#
RESET_OUT#17,24
SML1_SMBCLK18,24
THM261
1
VDD
2
D+
3
DĀT_CRIT#4GND
NCT7718W-GP
74.07718.0B9
PLT_RST#17,63,66,91,99
THERM_SYS_SHDN#
SCL
7718
SDA
ALERT#
R2617
1 2
0R0402-PAD
2016/12/28
8
7
6
5
R2616
0R2J-2-GP
1 2
6
5
ALERT#
DY
RESET_OUT#_G
2N7002KDW-GP
1
7718
2
34
Q2601
7718
4
DY
Q2602
G
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
THM_SML1_DATA
THM_SML1_CLK
THM_SML1_CLK
THM_SML1_DATA
12
12
DY
C2608
C2609
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
D
12
DY
C2610
SCD1U16V2KX-3GP
RESET_OUT#_G
12
DY
DY
CMP_VOUT0
1 2
R2615 0R2J-2-GP
KBC T8
C2614
SCD1U16V2KX-3GP
PURE_HW _SHUTDOWN# 40
DVT1 0210, for T8 function
3D3V_S5
1 2
R2607 10KR2J-3-GP
1 2
R26020R0402-PAD
2016/12/28
FAN_TACH124
FAN1_PW M24
Close to KBC
2017/05/08
5V_S0
EC2602
SC10P50V2JN-4GP
12
DY
CMP_VOUT0 24
1 2
R2612
0R0402-PAD
EC2601
SC10P50V2JN-4GP
12
DY
VD_IN1 for system thermal sensorClose to Thermal sensor
3D3V_S5_KBC3D3V_S0
DY
12
R2609
10R2F-L-GP
12
R2608
27KR2F-L-GP
DVT1 0210, for T8 function
PWM FAN1
FAN_VCC_1
D2601
KA
C2605
SCD1U25V2KX-1-DL-GP
C2604
12
SC4D7U6D3V3KX-DLGP
12
1 2
R26130R0402-PAD
1 2
R26140R0402-PAD
83.R5003.H8H
DY
AFTP2604
12
DY
RB551V30-GP
FAN_VCC_1
FAN_TACH1_C
FAN_PW M1_C
FAN_TACH1_C
FAN_PW M1_C
FAN_VCC_1
Layout Note:
Signal Routing Guideline:
Trace width = 15mil
C2603
SC2200P50V2KX-2GP
FAN1
5
1
2
3
4
6
1
FCN-CON4-1-GP
020.F000G.0004
2017/03/15
1
AFTP2601
1
AFTP2602
1
AFTP2603
12
R2610
NTC-100K-8-GP
B B
A A
12
C2612
SCD1U25V2KX-1-DL-GP
VD_IN1_C
12
C2613
SC100P50V2JN-3DLGP
CMP_VIN0_R 24
1 2
R2611
0R0402-PAD
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
THERMAL NCT7718W/Fan
THERMAL NCT7718W/Fan
THERMAL NCT7718W/Fan
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
26 106
26 106
26 106
A00
A00
A00
SSID = Audio
5
4
3
2
1
+3V_1D8V_AVDD
RN1812
HDA_CODEC_BITCLK19
HDA_CODEC_SDOUT19
HDA_CODEC_SYNC19
3D3V_S0
4
1
2 3
HDA_SDIN019
2016/11/2modify
3D3V_AUX_S5
RTC_AUX_S5
12
R2728
1 2
R2754
1 2
1 2
R2727 0R0402-PAD
1 2
R2740 0R0402-PAD
1 2
R2730 0R0402-PAD
1 2
R2746 0R2J-2-GP
+3V_1D8V_AVDD_IO
C2722
SCD1U25V2KX-1-DL-GP
0R2J-2-GP
DY
0R2J-2-GP
DY
+5V_AVDD
CPVDD
+5V_PVDD
+5V_PVDD
AUX_MODE
HDA_CODEC_SYNC
CODEC_BITCLK_R
CODEC_SDOUT_R
HDA_CODEC_SDIN0
DVSS
D D
1D8V_S0
2017/05/08
3D3V_S0
1 2
0R0603-PAD
R2748 0R3J-0-U-GP
R2749
1 2
DY
+3V_1D8V_AVDD
C2729
1 2
SRN2K2J-1-GP
Close pin6 pin7
SPK_I2C_DATA29
C2743
12
SPK_I2C_CLK29
2017/03/02
Layout Note:
Place close to Pin 1
AUD_SENSE29
12
R2743
10KR2J-3-GP
NB_MUTE#24
SPKR19
BEEP24
0R0402-PAD
200KR2F-L-GP
R2738
1 2
1 2
R2721
R2737
1 2
2016/12/28
2 3
1
SRN1KJ-7-GP
R2741
RN2702
12
0R0402-PAD
0R0402-PAD
EAPD#
4
AUD_SENSE_A
Audio_47
DMIC_DATA_R
DMIC_CLK_R
HDA_SPKR_R
KBC_BEEP_R
1D8V_S0
3D3V_S0
2017/03/02
R2750 0R3J-0-U-GP
R2751
1 2
0R0603-PAD
1 2
DY
SCD1U25V2KX-1-DL-GP
+3V_1D8V_AVDD_IO
C2744
12
SC10U6D3V3MX-DL-GP
C2745
12
+3V_1D8V_AVDD
DMIC_DATA55
DMIC_CLK55
SC10P50V2JN-4DLGP
R2744
C2738
DY
1 2
12
100KR2J-1-GP
+3V_1D8V_AVDD
Close pin5
C C
2.5A
5V_S0 +5V_PVDD
R2707
1 2
0R0805-PAD
R2712
1 2
0R0805-PAD
SCD1U25V2KX-1-DL-GP
+3V_1D8V_AVDD
C2742
C2732
12
12
C2714
C2733
12
12
R2742
1 2
100KR2J-1-GP
SC10U6D3V3MX-DL-GP
AUD_SENSE_A
12
C2746
DY
2017/03/02
SC10U6D3V3MX-DL-GP
Layout Note:
Close pin41
SC10U6D3V3MX-DL-GP
SCD1U25V2KX-1-DL-GP
Layout Note:
Close pin46
SCD1U25V2KX-1-DL-GP
SCD1U16V2KX-3DLGP
2nd = 83.R2003.W81
3rd = 75.00054.A7D
4th = 83.R2003.V81
HDA27
3
DVDD
18
DVDD-IO
40
AVDD1
20
CPVDD/AVDD2
41
PVDD1
46
PVDD2
33
5VSTB/AUX_MODE
6
I2C-DATA
7
I2C-CLK
15
AUDIOLINK_SYNC
14
AUDIOLINK_BCLK
17
AUDIOLINK_SDATA-OUT
16
AUDIOLINK_SDATA-IN
13
DC-DET/EAPD
11
I2S-MCLK
10
I2S-BCLK
12
I2S-LRCK
8
I2S-IN
9
I2S-OUT
48
HP/LINE1-JD(JD1)
47
I2S-IN/I2S-OUT-JD(JD2)
4
GPIO0/DMIC-DATA12
5
GPIO1/DMIC-CLK
1
DMIC-CLK-IN/I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34
2
PDB
ALC3254-CG-GP
D2702
2
1
BAT54C-7-F-3-GP
75.00054.E7D
AUD_PC_BEEP_C
3
12
C2726
1 2
R2745
2K2R2J-2-GP
MIC2-L(PORT-F-L)/RING2
MIC2-R(PORT-F-R)/SLEEVE
LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
MIC2-VREFO-L
MIC2-VREFO-R
AUD_PC_BEEP_R
SCD1U25V2KX-1-DL-GP
PCBEEP
SPK-OUT-L+
SPK-OUT-L-
SPK-OUT-R+
SPK-OUT-R-
VREF
LDO1-CAP
LDO2-CAP
LDO3-CAP
MIC2-CAP
CPVEE
CBP
CBN
AVSS1
AVSS2
GND
34
30
31
36
35
42
43
45
44
27
26
38
39
21
19
28
29
32
25
23
24
37
22
49
AUD_SPK_L+
AUD_SPK_LĀAUD_SPK_R+
AUD_SPK_R-
AUD_VREF
LDO1_CAP
LDO2_CAP
LDO3_CAP
MIC_CAP
CPVEE
CBP
CBN
C2734 SC10U6D3V3MX-DL-GP
C2736 SC10U6D3V3MX-DL-GP
2016/11/3
C2721
SCD1U25V2KX-1-DL-GP
2016/12/28
R2729
1 2
0R0402-PAD
AUD_SPK_L+ 29
AUD_SPK_L- 29
AUD_SPK_R+ 29
AUD_SPK_R- 29
AUD_HP1_JACK_L 29
AUD_HP1_JACK_R 29
12
C2737 SC2D2U10V3KX-1DLGP-U
12
1 2
MIC2_VREFO_L 29
MIC2_VREFO_R 29
1 2
C2735 SC10U6D3V3MX-DL-GP
C2741
1 2
C2739
1 2
12
12
C2727
Layout Note:
Place close to Pin 40
AUD_AGND
SC10U6D3V3MX-DL-GP
RING2 29
SLEEVE 29
LINE1_L 29
LINE1_R 29
SC1U50V3KX-1-GP
SC1U50V3KX-1-GP
moat
2017/05/08
R2705
1 2
0R0603-PAD
AUD_PC_BEEP_RAUD_PC_BEEP
Layout Note:
Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
5V_S0+5V_AVDD
Width>40mil, to improve Headpohone Crosstalk noise
Change it to sharp will be better.
Add 2 vias (>0.5A) when trace layer change.
12
C2731
SC10U6D3V3MX-DL-GP
12
R2747100KR2J-1-GP
AUD_AGND
moat
2017/05/08
1D8V_S0
R2724
1 2
B B
A A
0R0603-PAD
C2740
1 2
AUD_AGND
SCD1U25V2KX-1-DL-GP
CPVDD
12
AUD_AGND
C2730
SC10U6D3V3MX-DL-GP
Close pin 20
EC2711
1 2
EC2710
1 2
1 2
EC2713 SCD1U25V2KX-1-DL-GP
DY
EC2709
1 2
1 2
EC2712 SCD1U25V2KX-1-DL-GP
DY
DY
AUD_AGND
AUD_AGND
1 2
EC2714 SCD1U25V2KX-1-DL-GP
R2739
1 2
0R0805-PAD
Layout Note:
R2739 should place nearby codec IC.
2017/05/04
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Audio Codec ALC3254
Audio Codec ALC3254
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Audio Codec ALC3254
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
27 106Thursday, June 29, 2017
27 106Thursday, June 29, 2017
27 106Thursday, June 29, 2017
A00
A00
A00
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
(Reserved)
(Reserved)
(Reserved)
28 106Thursday, June 29, 2017
28 106Thursday, June 29, 2017
28 106Thursday, June 29, 2017
1
A00
A00
A00
5
SSID = Audio
4
3
2
1
Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power
(
EL2902 BLM15PD121SN1D-GP
EL2901 BLM15PD121SN1D-GP
EL2904 BLM15PD121SN1D-GP
EL2903 BLM15PD121SN1D-GP
(
(
(
(
AUD_SPK_L-_C
AUD_SPK_L+_C
AUD_SPK_R-_C
AUD_SPK_R+_C
AUD_HP1_JACK_L1
AUD_HP1_JACK_R1
SC680P50V2KX-2DLGP
EC2908
C2907
C2908
AUD_SPK_L+27
AUD_SPK_L-27
AUD_SPK_R+27
AUD_SPK_R-27
20160812 EMI
1 2
1 2
LINE1-L_C
SC10U6D3V3MX-DL-GP
LINE1-L_R
SC10U6D3V3MX-DL-GP
12
EC2901
SC1KP50V2KX-1DLGP
RN2901
1
2 3
SRN2K2J-1-GP
0R0402-PAD
0R0402-PAD
2017/03/02
12
EC2902
SC1KP50V2KX-1DLGP
4
R29070R0603-PAD
1 2
R2922
1 2
R29090R0603-PAD
1 2
R2921
1 2
12
EC2903
SC1KP50V2KX-1DLGP
12
EC2904
SC1KP50V2KX-1DLGP
D D
C C
MIC2_VREFO_R27
MIC2_VREFO_L27
AUD_HP1_JACK_L27
AUD_HP1_JACK_R27
RING227
LINE1_L27
LINE1_R27
SLEEVE27
12
(
at high frequencies
Resistance element becomes dominant
12
(
12
(
at high frequencies
Resistance element becomes dominant
12
at high frequencies
Resistance element becomes dominant
at high frequencies
Resistance element becomes dominant
SPK_ID20
2016/11/02 modify
3D3V_S0
1
1
1
1
AFTP2901
AFTP2902
AFTP2903
AFTP2904
Universal Jack (Moved to I/O Board)
SC680P50V2KX-2DLGP
12
SC680P50V2KX-2DLGP
EC2907
EC2906
12
12
SC680P50V2KX-2DLGP
EC2905
12
AUD_SPK_L+_C
AUD_SPK_L-_C
AUD_SPK_R+_C
AUD_SPK_R-_C
R2915
1 2
SPK_DET
0R2J-2-GP
R2914
1 2
EEPROM_SPK
0R2J-2-GP
2017/03/02
Speaker
R29060R0603-PAD
1 2
1 2
R290810R2F-L-GP
1 2
R291010R2F-L-GP
R29110R0603-PAD
1 2
SPK_I2C_CLK27
SPK_I2C_DATA27
SPK_DET#_CON
RING2_R
AUD_PORTA_L_R_B
AUD_PORTA_R_R_B
SLEEVE_R
SPK1
9
1
2
3
4
5
6
7
8
10
FCN-CON8-GP
020.F0701.0008
2016/12/28 change PN
RING2_R
AUD_PORTA_L_R_B
JACK_PLUG
JACK_PLUG_DET
AUD_PORTA_R_R_B
SLEEVE_R
CONN Pin
Pin1
Pin2 SPK_L-_C
Pin3
Pin4
Pin5
Pin6
Pin7 SPK_I2C_DATA
Pin8
HPMIC1
3
1
5
6
2
4
MS
AUDIO-JK569-GP
022.10002.00U1
Net name
SPK_L+_C
SPK_R+_C
SPK_R-_C
GND
SPK_I2C_CLK
SPK_DET#_CON
AUD_AGND
Layout Note:
EC2908 EC2907 should place nearby codec IC.
B B
AUD_AGNDAUD_AGND
20160812 EMI
CLOSS TO HPMIC1
AUD_PORTA_R_R_B
SLEEVE_R
JACK_PLUG_DET
JACK_PLUG
AUD_PORTA_L_R_B
RING2_R
2
2
1
ED2901
A A
3
5
AZ5125-02S-R7G-GP
1
ED2902
AZ5125-02S-R7G-GP
3
2
1
ED2903
AZ5125-02S-R7G-GP
3
20160812 EMI
4
JACK_PLUG_DET
10 mils
3
2017/03/02
R2905
0R0402-PAD
1 2
AUD_AGND
Delay circuit
(JACK_PLUG_DET: on IO Board)
2017/03/02
JACK_PLUG
2
1 2
0R0603-PAD
R2923
10 mils10 mils
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Audio IO
Audio IO
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Audio IO
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
1
AUD_SENSE 27
29 106
29 106
29 106
A00
A00
A00
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
(Reserved)
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
Thursday, June 29, 2017
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
30 106
30 106
30 106
1
Loading...