Page 1
5
D D
4
3
2
1
KyloRen 13" Schematics
KabyLake-R
C C
2017-06-29
REV : -1
B B
A A
DY : None Installed
UMA: UMA only installed
OPS: DISCRTE OPTIMUS installed
5
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Cover Page
Cover Page
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Cover Page
KyloRen 13"
KyloRen 13"
KyloRen 13"
1 106
1 106
1 106
1
A00
A00
A00
Page 2
5
4
3
2
1
KBL-U(R) 13" CPU 15W Block Diagram
Project code: 4PD0B5010001
PCB P/N: 16839
Revision: -1
Channel A
D D
HDMI V2.0
HDMI 2.0
57
HDMI Converter
Parade
PS175
57
DP1.2
Intel CPU
Kaby Lake U
Channel B
13.3"
eDP
Kaby Lake R
15W (UMA)
(HD/FHD)
Touch panel
M.2 SSD
55
63
SATA/PCIex2/PCIEx4(Optane)
USB3.0 Port2
USB PowerShare
C C
Power share
36
TI
TPS2544RTER
USB3.0
34
I2C
USB3.0 LANE1
USB2.0
USB2.0 LANE1
KBL PCH-LP
10 USB 2.0/1.1 ports
6 USB 3.0 ports
High Definition Audio
3 SATA ports
6 PCIE ports
LPC I/F
ACPI 5.0
USB2.0
DP
USB3.0
USB3.0 LANE4
USB2.0 LANE8
USB2.0 LANE4
1Rx16
1Rx16
MUX and Redriver
TI
TUSB546
USB2.0 x 1
I2C
DDR4
DDR4 13X16 Memory Down
CC
Cypress
CCG4
CardReader
SD 3.0
Realtak
RTS5176E
X16 Memory Down
DP/USB 3.0
38
CC1/CC2
12
USB3.0 type c
Port1
3837
SD Card Slot
Clamshell
Finger Printer
92
USB2.0 LANE9
USB2.0 x 1
PCIE LANE5
USB2.0 LANE6
PCIe
USB2.0
NGFF WLAN
IO Board
Sensor BD on
Panel side
USB 3.0
re-driver
TI
HPA02232ARGER
USB2.0
Camera (HD/IR)
D-MIC
SMBUS
HDA
CODEC
Realtek
ALC3254
USB2.0 LANE3
55
27
MIC_IN/GND
USB3.0
USB3.0 LANE3
2CH SPEAKER
(2CH 2W/4ohm)
USB3.0 Port3
I2C
68
Free fall
Gsensor
ST
LNG2DMTR
70
eSPI
USB3.0
USB2.0 x 1
USB2.0 LANE5
USB3.0 LANE3
Accelerometer
E-compass
ST
2 in 1
B B
LIS3MDL
Gyro+G
ST
LSM6DS3
eSPI debug port
HDA
Thermal
NUVOTON
NCT7718W
Fan Control
PWM
26
SMBUS
FAN DETECT
KB SCAN
INTERFACE
KBC
MICROCHIP
MEC1416
PS2
24
TPM
NUVOTON NPCT650
SPI
Flash ROM
91
16MB
Quad Read
2526
A A
FAN
5
Int.
KB
Touch PAD
Image sensor
4
I2C
HP_R/L
Universal Jack
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Block Diagram
Block Diagram
Block Diagram
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
A00
A00
2 106Thursday, June 29, 2017
2 106Thursday, June 29, 2017
2 106Thursday, June 29, 2017
A00
Page 3
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
C
C
C
(Reserved)
(Reserved)
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
A00
A00
3 106Thursday, June 29, 2017
3 106Thursday, June 29, 2017
1
3 106Thursday, June 29, 2017
A00
Page 4
5
4
3
2
1
SSID = CPU
+VCCST_CPU
12
R419
1KR2J-1-GP
+VCCSTG
D D
[PECI] and [PROCHOT#]
Impedance control: 50 ohm
PECI24
H_PROCHOT#24,44,46
TOUCH_PANEL_INTR#55
3D3V_S5_PCH
C C
R404
1 2
DY
100KR2J-1-GP
12
Rb
+VCCSTG = 1.0 V +VCCSTG = 1.0 V
PCH_THERMTRIP#
12
R401
1KR2J-1-GP
TPAD14-OP-GP
TPAD14-OP-GP
TPAD14-OP-GP
TOUCH_PANEL_PD#55
1 2
R403499R2F-2-GP
Ra
TPAD14-OP-GP
XDP_BPM099
XDP_BPM199
TP403
TOUCH_PAD_INTR#
TP401
TPAD14-OP-GP
TP402
TP407
TP408
1
R41249D9R2F-GP
R41349D9R2F-GP
R41449D9R2F-GP
R41549D9R2F-GP
H_CATERR#
1
H_PROCHOT#_R
PCH_THERMTRIP#
1
SKTOCC#
XDP_BPM2
1
XDP_BPM3
1
GPP_E3/CPU_GP0
CPU_POPIRCOMP
12
PCH_POPIRCOMP
12
EDRAM_OPIO_RCOMP
12
EOPIO_RCOMP
12
CPU1D
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
SKYLAKE-U-GP
SKYLAKE_ULT
CPU MISC
4 OF 20
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
XDP_TCK_JTAGX
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
XDP_TRST#
EC401
DY
AZ5725-01FDR7G-GP
20160812 EMI
PCH_JTAG_TCK 99
PCH_JTAG_TDI 99
PCH_JTAG_TDO 99
PCH_JTAG_TMS 99
XDP_TRST# 99
XDP_TCK_JTAGX 99
#544669 CRB Rev0.52
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
XDP_TCK_JTAGX
XDP_TRST#
PCH_JTAG_TCK
1 2
XDP
1 2
100R2F-L1-GP-U
R417 51R2J-2-GP
R402 51R2J-2-GP
R407 51R2J-2-GP
XDP
1 2
XDP
1 2
XDP
1 2
DY
1 2
DY
+VCCSTG
R40851R2J-2-GP
R409
R41651R2J-2-GP
071.SKYLA.000U
R410
TP_WAKE_KBC#24,65
1 2
0R0402-PAD
2016/12/28
(#543016) PROCHOT# Routing Guidelines
B B
M1,2,3,4,5: <3 inches
M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(JTAG/CPU SIDE BAND)
CPU_(JTAG/CPU SIDE BAND)
CPU_(JTAG/CPU SIDE BAND)
KyloRen 13"
KyloRen 13"
KyloRen 13"
4 106Thursday, June 29, 2017
4 106Thursday, June 29, 2017
4 106Thursday, June 29, 2017
1
A00
A00
A00
Page 5
SSID = CPU
5
4
3
2
1
DDR4 ball type: Non-Interleaved Type
D D
M_A_DQ012
M_A_DQ112
M_A_DQ212
M_A_DQ[0:7]
M_A_DQ[8:15]
M_A_DQ[16:23]
M_A_DQ[24:31]
C C
M_A_DQ[32:39]
M_A_DQ[40:47]
M_A_DQ[48:55]
M_A_DQ[56:63]
DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
B B
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential
clock pair to clock pair swapping within a channel is not allowed.
M_A_DQ312
M_A_DQ412
M_A_DQ512
M_A_DQ612
M_A_DQ712
M_A_DQ812
M_A_DQ912
M_A_DQ1012
M_A_DQ1112
M_A_DQ1212
M_A_DQ1312
M_A_DQ1412
M_A_DQ1512
M_A_DQ1612
M_A_DQ1712
M_A_DQ1812
M_A_DQ1912
M_A_DQ2012
M_A_DQ2112
M_A_DQ2212
M_A_DQ2312
M_A_DQ2412
M_A_DQ2512
M_A_DQ2612
M_A_DQ2712
M_A_DQ2812
M_A_DQ2912
M_A_DQ3012
M_A_DQ3112
M_A_DQ3212
M_A_DQ3312
M_A_DQ3412
M_A_DQ3512
M_A_DQ3612
M_A_DQ3712
M_A_DQ3812
M_A_DQ3912
M_A_DQ4012
M_A_DQ4112
M_A_DQ4212
M_A_DQ4312
M_A_DQ4412
M_A_DQ4512
M_A_DQ4612
M_A_DQ4712
M_A_DQ4812
M_A_DQ4912
M_A_DQ5012
M_A_DQ5112
M_A_DQ5212
M_A_DQ5312
M_A_DQ5412
M_A_DQ5512
M_A_DQ5612
M_A_DQ5712
M_A_DQ5812
M_A_DQ5912
M_A_DQ6012
M_A_DQ6112
M_A_DQ6212
M_A_DQ6312
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
CPU1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[8]
AF64
DDR1_DQ[1]/DDR0_DQ[9]
AK65
DDR1_DQ[2]/DDR0_DQ[10]
AK64
DDR1_DQ[3]/DDR0_DQ[11]
AF66
DDR1_DQ[4]/DDR0_DQ[12]
AF67
DDR1_DQ[5]/DDR0_DQ[13]
AK67
DDR1_DQ[6]/DDR0_DQ[14]
AK66
DDR1_DQ[7]/DDR0_DQ[15]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
SKYLAKE-U-GP
SKYLAKE_ULT
DDR0_DQ[16]
DDR0_DQ[17]
DDR0_DQ[18]
DDR0_DQ[19]
DDR0_DQ[20]
DDR0_DQ[21]
DDR0_DQ[22]
DDR0_DQ[23]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
071.SKYLA.000U
2 OF 20
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR1_DQSN[0]/DDR0_DQ[2]
DDR1_DQSP[0]/DDR0_DQ[2]
DDR1_DQSN[1]/DDR0_DQ[3]
DDR1_DQSP[1]/DDR0_DQ[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60
AW50
AT52
AY67
AY68
BA67
AW67
M_A_A5
M_A_A9
M_A_A6
M_A_A8
M_A_A7
M_A_A12
M_A_A11
M_A_A13
M_A_A15
M_A_A14
M_A_A16
M_A_A2
M_A_A10
M_A_A1
M_A_A0
M_A_A3
M_A_A4
M_A_DQS_DN0
M_A_DQS_DP0
M_A_DQS_DN1
M_A_DQS_DP1
M_A_DQS_DN2
M_A_DQS_DP2
M_A_DQS_DN3
M_A_DQS_DP3
M_A_DQS_DN4
M_A_DQS_DP4
M_A_DQS_DN5
M_A_DQS_DP5
M_A_DQS_DN6
M_A_DQS_DP6
M_A_DQS_DN7
M_A_DQS_DP7
SM_PGCNTL
M_A_CLK#0 12
M_A_CLK0 12
M_A_CKE0 12
M_A_CS#0 12
M_A_DIMA_ODT0 12
M_A_A5 12
M_A_A9 12
M_A_A6 12
M_A_A8 12
M_A_A7 12
M_A_BG0 12
M_A_A12 12
M_A_A11 12
M_A_ACT_N 12
M_A_BG1 12
M_A_A13 12
M_A_A15 12
M_A_A14 12
M_A_A16 12
M_A_BA0 12
M_A_A2 12
M_A_BA1 12
M_A_A10 12
M_A_A1 12
M_A_A0 12
M_A_A3 12
M_A_A4 12
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_ALERT_N 12
M_A_PARITY 12
V_SM_VREF_CNTA 12
V_SM_VREF_CNTB 13
CPU1C
M_B_DQ013
M_B_DQ113
M_B_DQ213
M_B_DQ313
M_B_DQ413
M_B_DQ513
M_B_DQ613
M_B_DQ713
M_B_DQ813
M_B_DQ913
M_B_DQ1013
M_B_DQ1113
M_B_DQ1213
M_B_DQ1313
M_B_DQ1413
M_B_DQ1513
M_B_DQ1613
M_B_DQ1713
M_B_DQ1813
M_B_DQ1913
M_B_DQ2013
M_B_DQ2113
M_B_DQ2213
M_B_DQ2313
M_B_DQ2413
M_B_DQ2513
M_B_DQ2613
M_B_DQ2713
M_B_DQ2813
M_B_DQ2913
M_B_DQ3013
M_B_DQ3113
M_B_DQ3213
M_B_DQ3313
M_B_DQ3413
M_B_DQ3513
M_B_DQ3613
M_B_DQ3713
M_B_DQ3813
M_B_DQ3913
M_B_DQ4013
M_B_DQ4113
M_B_DQ4213
M_B_DQ4313
M_B_DQ4413
M_B_DQ4513
M_B_DQ4613
M_B_DQ4713
M_B_DQ4813
M_B_DQ4913
M_B_DQ5013
M_B_DQ5113
M_B_DQ5213
M_B_DQ5313
M_B_DQ5413
M_B_DQ5513
M_B_DQ5613
M_B_DQ5713
M_B_DQ5813
M_B_DQ5913
M_B_DQ6013
M_B_DQ6113
M_B_DQ6213
M_B_DQ6313
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKYLAKE-U-GP
SKYLAKE_ULT
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR CH - B
071.SKYLA.000U
Design Guideline:
1D2V_S3 3D3V_S0
12
G
R506
220KR2F-GP
SM_RCOMP keep routing length less than 500 mils.
3 OF 20
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7
M_B_A12
M_B_A11
M_B_ACT_N
M_B_A13
M_B_A15
M_B_A14
M_B_A16
M_B_A2
M_B_A10
M_B_A1
M_B_A0
M_B_A3
M_B_A4
M_B_DQS_DN0
M_B_DQS_DP0
M_B_DQS_DN1
M_B_DQS_DP1
M_B_DQS_DN2
M_B_DQS_DP2
M_B_DQS_DN3
M_B_DQS_DP3
M_B_DQS_DN4
M_B_DQS_DP4
M_B_DQS_DN5
M_B_DQS_DP5
M_B_DQS_DN6
M_B_DQS_DP6
M_B_DQS_DN7
M_B_DQS_DP7
SM_DRAMRST#
SM_RCOMP_0
SM_RCOMP_0
SM_RCOMP_1
#543016
SM_RCOMP_2
M_B_CLK#0 13
M_B_CLK0 13
M_B_CKE0 13
M_B_CS#0 13
M_B_DIMB_ODT0 13
M_B_A5 13
M_B_A9 13
M_B_A6 13
M_B_A8 13
M_B_A7 13
M_B_BG0 13
M_B_A12 13
M_B_A11 13
M_B_ACT_N 13
M_B_BG1 13
M_B_A13 13
M_B_A15 13
M_B_A14 13
M_B_A16 13
M_B_BA0 13
M_B_A2 13
M_B_BA1 13
M_B_A10 13
M_B_A1 13
M_B_A0 13
M_B_A3 13
M_B_A4 13
M_B_ALERT_N 13
M_B_PARITY 13
R501
1 2
1 2
1 2
1 2
121R2F-GP
DDP
200R2F-L-GP
R507
SDP
R502 80D6R2F-L-GP
R503 100R2F-L1-GP-U
DDP R501:121
SDP R507:200
2016/11/28
Layout Note:
1D2V_S3
12
R505
470R2F-GP
1 2
R504
0R0402-PAD
DDR4_DRAMRST# 12,13
12
C501
SCD1U25V2KX-1-DL-GP
SM_PGCNTL
Q501
DMN5L06K-7-GP
DS
SM_PGCNTL_R 51
2015/11/18 Modify
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
A A
5
4
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
M_A_DQS_DN[7:0] 12
M_A_DQS_DP[7:0] 12
3
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
M_B_DQS_DN[7:0] 13
M_B_DQS_DP[7:0] 13
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(DDR)
CPU_(DDR)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(DDR)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
5 106Thursday, June 29, 2017
5 106Thursday, June 29, 2017
5 106Thursday, June 29, 2017
A00
A00
A00
Page 6
SSID = CPU
5
4
3
2
1
CPU1S
D D
C C
PCH strap pin:
CFG3
DY
CFG[19:0]99
12
R604
1KR2J-1-GP
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
12
R60149D9R2F-GP
ITP_PMODE99
RSVD_TP_BA70
1
1
TP601TPAD14-OP-GP
TP602TPAD14-OP-GP
RSVD_F65
1
RSVD_G65
1
TP612TPAD14-OP-GP
TP613TPAD14-OP-GP
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
AY2
AY1
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
F65
G65
F61
E61
E8
D1
D3
J71
J68
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKYLAKE-U-GP
071.SKYLA.000U
[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
CFG[3]
0 : ENABLED
SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
RESERVED SIGNALS-1
SKYLAKE_ULT
RSVD_TP_AW71
RSVD_TP_AW70
19 OF 20
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
TP5
TP6
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
TP4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
TP1
TP2
VSS_AY71
ZVM#
RSVD_AW71
RSVD_AW70
MSM#
PROC_SELECT#
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
TP5_AU5
TP6_AT5
TP4_BB5
TP1_AY4
TP2_BB3RSVD_TP_BA68
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
1
1
1
1
1
1
1
1
1
1 2
R602 0R0402-PAD
1
1
1
1
1 2
R603
100KR2J-1-GP
2016/01/11 modify
TP603 TPAD14-OP-GP
TP604 TPAD14-OP-GP
TP605 TPAD14-OP-GP
TP606 TPAD14-OP-GP
TP607 TPAD14-OP-GP
TP608 TPAD14-OP-GP
TP609 TPAD14-OP-GP
TP610 TPAD14-OP-GP
TP611 TPAD14-OP-GP
TP618
TPAD14-OP-GP
TP614 TPAD14-OP-GP
TP615 TPAD14-OP-GP
TP617 TPAD14-OP-GP
DY
#54469 CRB.
+VCCST_CPU
1 : DISABLED
CFG4
B B
12
R605
1KR2J-1-GP
(#543016)
DISPLAY PORT PRESENCE STRAP
CFG[4]
0 : ENABLED
An external Display Port device is connected to the Embedded Display Port.
1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.
SKL(#543016):
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(RESERVED)
CPU_(RESERVED)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
CPU_(RESERVED)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
6 106Thursday, June 29, 2017
6 106Thursday, June 29, 2017
6 106Thursday, June 29, 2017
A00
A00
A00
Page 7
SSID = CPU
5
4
3
2
1
A48
A53
A58
A62
A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
U42
R736
1 2
D0002R5J-GP- U
U42
R743
1 2
D0002R5J-GP- U
CPU1M
CPU POWER 2 OF 4
VCCGT
SKYLAKE_ULT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
SKYLAKE-U-GP
071.SKYLA.000U
13 OF 20
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
U22
R742
1 2
D0002R5J-GP- U
+VCCGT
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
For U42 only
AU63
BB57
BB66
AK62
AL61
GTX_CORE
GTX_CORE
GTX_CORE
SC10U6D3V3MX- DL-GP
#544669 CRB.
+VDDQ_CPU _CLK1D2V_S3
R705
1 2
0R0805-PAD
2016/02/16 modify
2017/01/18
DY
2017/06/28
VCC_CORE
+VCCGT
1D2V_S3
DY
12
12
12
12
12
12
12
12
12
C719
SC1U10V2KX-1D LGP
+VDDQ_CPU _CLK
C715
+VCCST_CP U
C716SC1U10V2KX-1D LGP
+VCCSTG
C717SC1U10V2KX-1D LGP
1D2V_S3
C718SC1U10V2KX-1D LGP
+VCCSFR
C720
SCD1U25V2KX-1-DL-GP
1 2
R719
100R2F-L1-GP- U
R720
100R2F-L1-GP- U
R721
100R2F-L1-GP- U
R722
100R2F-L1-GP- U
CPU1N
CPU POWER 3 OF 4
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
0.04 A
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
0.12 A
12
C721
SC1U10V2KX-1DLGP
SKYLAKE-U-GP
071.SKYLA.000U
VCC_SENSE 7,46
VSS_SENSE 7,46
Layout Note:
1. Place close to CPU
2. VCC_SENSE/ VSS_SENSE
impedance=50 ohm
3. Length match<25mil
VCCGT_SEN SE 7,46
VSSGT_SENSE 7,46
SKYLAKE_ULT
14 OF 20
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
VCCSA_SENS E
VSSSA_SENSE
+VCCIO
+VCCIO(ICCMAX.=2.73A
+VCCSA
+VCCSA
12
R735
100R2F-L1-GP- U
12
R734
100R2F-L1-GP- U
VSSSA_SENSE 46
VCCSA_SENS E 46
AM32
AM33
AM35
AM37
AM38
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AK32
AB62
AC63
AE63
AE62
AG62
AL63
AJ62
A30
A34
A39
A44
G30
K32
P62
V62
H63
G61
CPU1L
VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
VCCG0
RSVD_AK32
VCCG1
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
SKYLAKE-U-GP
CPU POWER 1 OF 4
SKYLAKE_ULT
VCC_CORE VCC_CORE
D D
1
+VCCCOR EG0
TP701TPAD14-OP-GP
1
+VCCCOR EG1
TP707TPAD14-OP-GP
3A
+V_EDRAM_VR
140mA
+V1.8S_EDRAM
SEN_EDRAM
3A
+V_EOPIO_VR
SEN_EOPIO
12 OF 20
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
H_CPU_SVIDALR T#
H_CPU_SVIDC LK
H_CPU_SVIDD AT
+VCCFUSE PRG
VCC_SENSE 7,46
VSS_SENSE 7,46
1 2
R703
0R0603-PAD
+VCCGT
1 2
R738
DY
0R2J-2-GP
+VCCSTG
U22_POWER _K52
For U22 & U42
GT_CORE
+VCCGT
GT_CORE
+VCCGT
GT_CORE
+VCCGT
071.SKYLA.000U
VCCGT_SEN SE7,46
VSSGT_SENSE7,46
VCC_CORE GT_CORE +VCCGT
C C
VCC_CORE GTX_CORE
Layout Note:
SVID_543016:
B B
CLOSE TO CPU
H_CPU_SVIDD AT
+VCCST_CP U
12
R726
100R2F-L1-GP- U
SVID CLOCK
H_CPU_SVIDC LK
A A
SVID DATA
H_CPU_SVIDALR T#
5
R728
220R2J-L2-GP
4
The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).
Route the Alert signal between the Clock and the Data signals.
#544669
1 2
12
R709
0R0402-PAD
1 2
R732
0R0402-PAD
+VCCST_CP U
12
R727
56R2J-4-GP
+VCCST_CP U
12
DY
#544669
CLOSE TO CPU
R723
54D9R2F-L1-G P
VR_SVID_ALERT# 46
VR_SVID_DATA 46
#544669
CLOSE TO VR
VR_SVID_CLK 46
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
1
Taipei Hsie n 221, Taiwan, R.O. C.
CPU(VCC_CORE)
CPU(VCC_CORE)
CPU(VCC_CORE)
KyloRen 13"
KyloRen 13"
KyloRen 13"
7 106
7 106
7 106
A00
A00
A00
Page 8
5
4
3
2
1
SSID = CPU
D D
CPU1A
DP_DATA0_N57
DP_DATA0_P57
DP_DATA1_N57
DP_DATA1_P57
DP to HDMI2.0
DP for Type-C Mux
2016/11/01modify
3D3V_S0
C C
3D3V_S0
SRN2K2J-1-GP
1
2 3
RN801
RN803
2 3
1
SRN2K2J-1-GP
CPU_DP1_CTRL_DATA
4
CPU_DP1_CTRL_CLK
CPU_DP2_CTRL_DATA
CPU_DP2_CTRL_CLK
4
DP to HDMI2.0 DP to HDMI2.0
+VCCIO
R801
1 2
24D9R2F-L-GP
DP_DATA2_N57
DP_DATA2_P57
DP_DATA3_N57
DP_DATA3_P57
PCH_DPC_N038
PCH_DPC_P038
PCH_DPC_N138
PCH_DPC_P138
PCH_DPC_N238
PCH_DPC_P238
PCH_DPC_N338
PCH_DPC_P338
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK SIO_EXT_SMI#
CPU_DP2_CTRL_DATA
2016/11/07
EDP_COMP
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKYLAKE-U-GP
071.SKYLA.000U
(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.
SKYLAKE_ULT
DDI
DISPLAY SIDEBANDS
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
1 OF 20
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
EDP_DISP_UTIL
CPU_DP2_HPD
EDP_TX0_DN 55
EDP_TX0_DP 55
EDP_TX1_DN 55
EDP_TX1_DP 55
EDP_TX2_DN 55
EDP_TX2_DP 55
EDP_TX3_DN 55
EDP_TX3_DP 55
EDP_AUX_DN 55
EDP_AUX_DP 55
1
TP801 TPAD14-OP-GP
HDMI_AUXN 57
HDMI_AUXP 57
DPB_AUXN 38
DPB_AUXP 38
CPU_DP1_HPD 57
EDP_HPD 55
L_BKLT_CTRL 55
EDP_VDD_EN 55
2016/11/01modify
for HDMI2.0
for Type-C Mux
L_BKLT_EN 24
2016/11/07
(#543016) eDP_RCOMP Guideline
Signal Trace
Width
eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1%
B B
Isolation
Spacing
Resistor
Value
Length
Max = 100 mils
(#543016) DDI Disabling and Termination Guidelines
Touch_panel _Resert Remove
3D3V_S0
CPU_DP2_HPD
TypeC
1 2
R804
1 2
0R0402-PAD
2016/12/28
R803
100KR2J-1-GP
CPU_DP_HPD_R 37,38
DP for Type-C Mux
Port Strap Enable Port Disable Port
Port 1
Port 2
A A
DDPB_CTRLDATA
DDPC_CTRLDATA
PU to 3.3 V with 2.2-k
±5% resistor
PU to 3.3 V with 2.2-k
±5% resistor
NC
NC
SIO_EXT_SMI#
1 2
R802 10KR2J-3-GP
<Core Design>
<Core Design>
<Core Design>
Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor.
5
4
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(DISPLAY)
CPU_(DISPLAY)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
CPU_(DISPLAY)
KyloRen 13"
KyloRen 13"
KyloRen 13"
8 106Thursday, June 29, 2017
8 106Thursday, June 29, 2017
8 106Thursday, June 29, 2017
1
A00
A00
A00
Page 9
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
(Reserved)
(Reserved)
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
9 106Thursday, June 29, 2017
9 106Thursday, June 29, 2017
9 106Thursday, June 29, 2017
1
A00
A00
A00
Page 10
A00
A00
A00
10 106Thursday, June 29, 2017
10 106Thursday, June 29, 2017
10 106Thursday, June 29, 2017
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
<Core Design>
<Core Design>
<Core Design>
2
Title
Title
Title
1
KyloRen 13"
KyloRen 13"
KyloRen 13"
CPU_(Power CAP1)
CPU_(Power CAP1)
CPU_(Power CAP1)
A2
A2
A2
Size Document Number Rev
Date: Sheet of
Size Document Number Rev
Date: Sheet of
Size Document Number Rev
Date: Sheet of
2
SC10U6D3V2MX-2-GP
PC1083
12
3
U42
SC10U6D3V2MX-2-GP
PC1082
12
U42
SC10U6D3V2MX-2-GP
PC1081
12
U42
SC10U6D3V2MX-2-GP
PC1080
12
U42
SC10U6D3V2MX-2-GP
PC1035
12
U42
SC10U6D3V2MX-2-GP
PC1079
12
U42
SC10U6D3V2MX-2-GP
PC1033
12
U42
SC10U6D3V2MX-2-GP
PC1093
12
U42
SC10U6D3V2MX-2-GP
PC1092
12
U42
SC10U6D3V2MX-2-GP
PC1091
12
U42
SC10U6D3V2MX-2-GP
PC1090
12
U42
SC10U6D3V2MX-2-GP
PC1086
12
U42
SC10U6D3V2MX-2-GP
PC1085
12
U42
SC10U6D3V2MX-2-GP
PC1084
12
U42
3
2016/11/7modify
VCC_CORE
SC10U6D3V2MX-2-GP
PC1087
12
4
2017/01/182017/01/18
2017/04/26
5
22U 0603 x 30
U-line 22 15W
IccMax current-10ms max = 31 A
VCC_CORE
10U 0402 x 2 (2DY)
DY
SC10U6D3V2MX-2-GP
PC1032
12
DY
SC10U6D3V3MX-DL-GP
PC1020
12
DY
SC10U6D3V3MX-DL-GP
PC1017
12
DY
SC22U6D3V3MX-1-DL-GP
PC1011
12
SC22U6D3V3MX-1-DL-GP
PC1010
12
SC22U6D3V3MX-1-DL-GP
PC1009
12
SC22U6D3V3MX-1-DL-GP
PC1008
12
SC22U6D3V3MX-1-DL-GP
PC1007
12
SC22U6D3V3MX-1-DL-GP
PC1006
DY
12
SC22U6D3V3MX-1-DL-GP
PC1005
12
SC22U6D3V3MX-1-DL-GP
PC1004
12
SC22U6D3V3MX-1-DL-GP
PC1003
12
SC22U6D3V3MX-1-DL-GP
PC1002
12
DY
2017/04/26
SC22U6D3V3MX-1-DL-GP
PC1023
12
SC22U6D3V3MX-1-DL-GP
PC1022
12
SC22U6D3V3MX-1-DL-GP
PC1021
12
SC22U6D3V3MX-1-DL-GP
PC1019
12
SC22U6D3V3MX-1-DL-GP
PC1018
12
SC22U6D3V3MX-1-DL-GP
PC1016
12
SC22U6D3V3MX-1-DL-GP
PC1015
12
SC22U6D3V3MX-1-DL-GP
PC1014
2017/04/26
12
SC22U6D3V3MX-1-DL-GP
PC1013
12
SC22U6D3V3MX-1-DL-GP
PC1012
12
4
SC22U6D3V3MX-1-DL-GP
PC1001
SC22U6D3V3MX-1-DL-GP
PC1070
12
U42
SC22U6D3V3MX-1-DL-GP
PC1069
12
2017/04/26
SC22U6D3V3MX-1-DL-GP
PC1036
DY
DY
DY
12
SC22U6D3V3MX-1-DL-GP
PC1034
DY
12
SC22U6D3V3MX-1-DL-GP
PC1031
12
SC22U6D3V3MX-1-DL-GP
PC1030
12
SC22U6D3V3MX-1-DL-GP
PC1029
12
DY
SC22U6D3V3MX-1-DL-GP
PC1028
12
SC22U6D3V3MX-1-DL-GP
PC1027
12
SC22U6D3V3MX-1-DL-GP
PC1026
DY
12
SC22U6D3V3MX-1-DL-GP
PC1025
12
SC22U6D3V3MX-1-DL-GP
PC1024
12
VCCGT
22U 0603 x 30 (3 DY)
U-line 22 15W
IccMax current-10ms max[A] = 64 A
U42
SC22U6D3V3MX-1-DL-GP
PC1046
12
SC22U6D3V3MX-1-DL-GP
PC1045
12
SC22U6D3V3MX-1-DL-GP
PC1044
12
SC22U6D3V3MX-1-DL-GP
PC1043
12
SC22U6D3V3MX-1-DL-GP
PC1042
12
SC22U6D3V3MX-1-DL-GP
PC1041
12
SC22U6D3V3MX-1-DL-GP
PC1040
12
SC22U6D3V3MX-1-DL-GP
PC1039
12
SC22U6D3V3MX-1-DL-GP
PC1038
12
SC22U6D3V3MX-1-DL-GP
PC1037
12
SC22U6D3V3MX-1-DL-GP
PC1056
12
SC22U6D3V3MX-1-DL-GP
PC1055
12
SC22U6D3V3MX-1-DL-GP
PC1054
12
SC22U6D3V3MX-1-DL-GP
PC1053
12
SC22U6D3V3MX-1-DL-GP
PC1052
12
SC22U6D3V3MX-1-DL-GP
PC1051
12
SC22U6D3V3MX-1-DL-GP
PC1050
12
SC22U6D3V3MX-1-DL-GP
PC1049
12
SC22U6D3V3MX-1-DL-GP
PC1048
12
SC22U6D3V3MX-1-DL-GP
PC1047
12
12
DY
SC22U6D3V3MX-1-DL-GP
PC1068
12
DY
SC22U6D3V3MX-1-DL-GP
PC1067
12
DY
SC22U6D3V3MX-1-DL-GP
PC1066
12
SC22U6D3V3MX-1-DL-GP
PC1065
12
SC22U6D3V3MX-1-DL-GP
PC1064
12
SC22U6D3V3MX-1-DL-GP
PC1063
12
SC22U6D3V3MX-1-DL-GP
PC1062
12
SC22U6D3V3MX-1-DL-GP
PC1061
12
SC22U6D3V3MX-1-DL-GP
PC1060
12
SC22U6D3V3MX-1-DL-GP
PC1059
12
SC22U6D3V3MX-1-DL-GP
PC1058
12
SC22U6D3V3MX-1-DL-GP
PC1057
12
VCCSA
SC22U6D3V3MX-1-DL-GP
PC1078
12
DY
SC22U6D3V3MX-1-DL-GP
PC1077
12
SC22U6D3V3MX-1-DL-GP
PC1076
12
SC22U6D3V3MX-1-DL-GP
PC1075
12
DY
SC22U6D3V3MX-1-DL-GP
PC1074
12
DY
SC22U6D3V3MX-1-DL-GP
PC1073
12
SC22U6D3V3MX-1-DL-GP
PC1072
12
SC22U6D3V3MX-1-DL-GP
PC1071
12
5
22U 0603 x 5 (3DY)
SSID = CPU
VCC_CORE
D D
C C
+VCCGT
B B
+VCCSA
A A
Page 11
SSID = CPU
5
4
3
2
1
PCH DERIVED RAILS
1D0V_S5
D D
2017/05/08
UNSLICED GT
+VCCGT
VCCIO
+VCCIO
+VCCIO(ICCMAX.=2.73A)
1 2
R1101
0R1206-PAD
1 2
R1102
0R0603-PAD
+VCCPRIM_CORE
+V1.00A_SIP
C1112
SC22U6D3V3MX-1-GP
12
12
12
C1103
C1102
DY
DY
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
Dummy : 20150123 Dummy : 20150123
12
C1104
DY
SC1U10V2KX-1DLGP
12
C1105
SC1U10V2KX-1DLGP
12
C1106
DY
SC1U10V2KX-1DLGP
12
C1107
1U 0402 x 6
SC1U10V2KX-1DLGP
DY
12
C1108
SC1U10V2KX-1DLGP
12
C1109
SC1U10V2KX-1DLGP
12
C1110
SC1U10V2KX-1DLGP
12
C1111
SC1U10V2KX-1DLGP
DY
3D3V_S5_PCH +V3.3A_SIP
1 2
C C
R1103
0R0603-PAD
C1113
SC22U6D3V3MX-1-GP
12
+VCCMPHYGTAON_1P0(ICCMAX.=2.12A)
DY
Layout Note:
+V1.8A +V1.8A_SIP
R1104
12
0R0603-PAD
12
DY
+VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP+VCCMPHYGTAON_1P0_LS_SIP
C1117
C1115
DY
SC22U6D3V3MX-1-GP
12
C1116
SC1U10V2KX-1DLGP
12
C1114
SC1U10V2KX-1DLGP
12
C1122
SC22U6D3V3MX-1-GP
SC1U10V2KX-1DLGP
12
C1118
12
DY
C1119
SC22U6D3V3MX-1-GP
SC1U10V2KX-1DLGP
12
SC10U6D3V3MX-DL-GP
C1120
12
C1121
SC1U10V2KX-1DLGP
12
DY
1uF:
C1174 near N15
C1180 near K15
C1173 near AF20
C1172 near N18
C1175 near AB19
22uF :
C1182 C1184 near N15
10uF:
C1176 near N15
+VCCIO
+VCCPRIM_CORE
+VCCIO(ICCMAX.=2.73A)
C1134
C1133
12
SC22U6D3V3MX-1-DL-GP
B B
12
C1135
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
12
C1128
12
C1129
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
12
1D2V_S3
DY
12
C1130
12
12
12
C1139SCD1U25V2KX-1-DL-GP
C1140SCD1U25V2KX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
EC1102
SC2D2U6D3V2MX-DL-GP
12
12
12
DY
C1141SCD1U25V2KX-1-DL-GP
EC1103
SC2D2U6D3V2MX-DL-GP
C1142SCD1U25V2KX-1-DL-GP
12
DY
VCC_CORE
2017/01/17
1U 0402 x 5
+V3.3A_SIP
SC10U6D3V3MX-DL-GP
C1123
12
C1132
12
12
C1137
C1138
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
C1131
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
12
DY
C1136
SC10U6D3V3MX-DL-GP
DY
12
DY
A A
U-line 23e 28W
IccMax current-10ms max = 34 A
DY
12
C1124
SC1U10V2KX-1DLGP
DY
5
12
C1125
SC1U10V2KX-1DLGP
DY
12
C1126
SC1U10V2KX-1DLGP
DY
12
C1101
DY
SC1U10V2KX-1DLGP
12
C1127
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
SC1U10V2KX-1DLGP
RF request 2016/01/12 modify
Title
Title
Title
CPU_(Power CAP2)
CPU_(Power CAP2)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
4
3
2
CPU_(Power CAP2)
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
11 106Thursday, June 29, 2017
11 106Thursday, June 29, 2017
11 106Thursday, June 29, 2017
1
A00
A00
A00
Page 12
SSID = MEMORY
5
4
3
2
1
1D2V_S3
U1204
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
D D
2D5V_S3
M_A_A05,12
M_A_A15,12
M_A_A25,12
M_A_A35,12
M_A_A45,12
M_A_A55,12
M_A_A65,12
M_A_A75,12
M_A_A85,12
M_A_A95,12
M_A_A105,12
M_A_A115,12
M_A_A125,12
M_A_A135,12
M_A_A145,12
M_A_A155,12
M_A_A165,12
M_A_CS#05,12
DDR4_DR AMRST#5,12,13
M_A_ACT_N5,12
M_A_ALERT_N5,12
M_A_CLK05,12
M_A_CLK#05,12
M_A_CKE05,12
M_A_BA05,12
M_A_BA15,12
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
VREFCA
NC#T7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
C7
C2
C8
D3
D7
B7
A7
G3
M_A_DQS_DN1
F3
E2
E7
K3
ODT
F9
ZQ
M1
M2
BG0
N9
TEN
T3
PAR
T7
B2
VSS
E1
VSS
M_A_BG1_E9_1
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M_A_BG1_M9_R
M9
VSS
N1
VSS
T1
VSS
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
M_A_DQS_DP0
M_A_DQS_DN0
M_A_DQS_DP1
TEST_MODE_1
M_A_DQ8 5
M_A_DQ9 5
M_A_DQ10 5
M_A_DQ11 5
M_A_DQ12 5
M_A_DQ13 5
M_A_DQ14 5
M_A_DQ15 5
M_A_DQ0 5
M_A_DQ1 5
M_A_DQ2 5
M_A_DQ3 5
M_A_DQ4 5
M_A_DQ5 5
M_A_DQ6 5
M_A_DQ7 5
M_A_DIMA_ODT0 5,12
M_A_BG0 5,12
M_A_PARITY 5,12
A_ZQ_RAM4
M_VREF_CA_D IMMA
1
TP1201
TPAD14-OP-G P
2016/11/29
1D2V_S3
240R2D-GP
C1201
SCD047U25V2KX-4-GP
R1201
1 2
12
M_A_A05,12
M_A_A15,12
M_A_A25,12
M_A_A35,12
M_A_A45,12
M_A_A55,12
M_A_A65,12
M_A_A75,12
M_A_A85,12
M_A_A95,12
M_A_A105,12
M_A_A115,12
M_A_A125,12
M_A_A135,12
DDR4_DR AMRST#5,12,13
M_A_ACT_N5,12
M_A_ALERT_N5,12
2017/05/10
1D2V_S3
C C
2D5V_S3
M_A_A05,12
M_A_A15,12
M_A_A25,12
M_A_A35,12
M_A_A45,12
M_A_A55,12
M_A_A65,12
M_A_A75,12
M_A_A85,12
M_A_A95,12
M_A_A105,12
M_A_A115,12
M_A_A125,12
M_A_A135,12
M_A_A145,12
M_A_A155,12
M_A_A165,12
M_A_CS#05,12
DDR4_DR AMRST#5,12,13
M_A_ACT_N5,12
M_A_ALERT_N5,12
M_A_CLK05,12
M_A_CLK#05,12
M_A_CKE05,12
M_A_BA05,12
B B
M_A_BA15,12
SDP & DDP SETTING
M_A_BG1_E9_1
M_A_BG1_E9_2
M_A_BG1_E9_3
M_A_BG1_E9_4
M_A_BG1_E9_1
M_A_BG1_E9_2
M_A_BG1_E9_3
M_A_BG1_E9_4
M_A_BG15
A A
5
1 2
R1212 240R2F-1-GP
DDP
1 2
R1213 240R2F-1-GP
DDP
1 2
R1214 240R2F-1-GP
DDP
1 2
R1215 240R2F-1-GP
DDP
1 2
R1216 0R2J-2-GP
SDP
1 2
R1217 0R2J-2-GP
SDP
1 2
R1218 0R2J-2-GP
SDP
1 2
R1219 0R2J-2-GP
SDP
DDP
1 2
R1220 0R2J-2-GP
1 2
R1221 0R2J-2-GP
SDP
M_A_BG1_M9_R
U1201
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
B7
UDQS_T
A7
UDQS_C
G3
LDQS_T
F3
LDQS_C
E2
E7
K3
ODT
F9
ZQ
M1
VREFCA
M2
BG0
N9
TEN
T3
PAR
T7
NC#T7
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
CTRL/CKE/CMD
M_A_DQS_DP7
M_A_DQS_DN7
M_A_DQS_DP6
M_A_DQS_DN6
TEST_MODE_2
M_A_BG1_E9_3
M_A_BG1_M9_R
CLK
M_A_DQ53 5
M_A_DQ51 5
M_A_DQ55 5
M_A_DQ50 5
M_A_DQ48 5
M_A_DQ52 5
M_A_DQ54 5
M_A_DQ49 5
M_A_DQ61 5
M_A_DQ57 5
M_A_DQ58 5
M_A_DQ63 5
M_A_DQ60 5
M_A_DQ56 5
M_A_DQ59 5
M_A_DQ62 5
M_A_DIMA_ODT0 5,12
M_A_BG0 5,12
M_A_PARITY 5,12
2016/11/29
A_ZQ_RAM1
1
TP1202
TPAD14-OP-G P
2016/11/29
M_A_CLK#0
M_A_CLK0
M_A_BG1_M9_R
2016/11/25
M_A_CKE0
M_A_A12
M_A_A3
M_A_ACT_N
M_A_BG0
M_A_A5
M_A_A2
M_A_BA1
M_A_A6
M_A_A7
M_A_A0
M_A_A13
M_A_A11
M_A_A9
M_A_A8
M_A_PARITY
M_A_A1
M_A_BA0
M_A_A4
M_A_A14
M_A_A10
M_A_A16
M_A_A15
M_A_DIMA_ODT0
M_A_CS#0
1D2V_S3
M_VREF_CA_D IMMA
SCD047U25V2KX-4-GP
12
C1236
R1226 36R2F-1-GP
R1225 36R2F-1-GP
1 2
R1224 36R2F-1-GP
R1211 36R2F-1-GP
1 2
1
2
3
4 5
1
2
3
4 5
1
2
3
4 5
4
240R2D-GP
R1205
1 2
1 2
DDP
RN1202
SRN36J-GP
RN1203
SRN36J-GP
RN1204
SRN36J-GP
RN1205
1
2
3
4 5
SRN36J-GP
RN1206
1
2
3
4 5
SRN36J-GP
RN1207
1
2
3
4 5
SRN36J-GP
M_A_A05,12
M_A_A15,12
M_A_A25,12
M_A_A35,12
M_A_A45,12
12
0D6V_S0
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
M_A_A55,12
M_A_A65,12
M_A_A75,12
M_A_A85,12
M_A_A95,12
M_A_A105,12
M_A_A115,12
M_A_A125,12
M_A_A135,12
M_A_A145,12
DDR4_DR AMRST#5,12,13
M_A_ACT_N5,12
M_A_ALERT_N5,12
ALERT
M_A_A155,12
M_A_A165,12
2D5V_S3
M_A_A145,12
M_A_A155,12
M_A_A165,12
M_A_CS#05,12
M_A_CLK05,12
M_A_CLK#05,12
M_A_CKE05,12
M_A_BA05,12
M_A_BA15,12
1D2V_S3
2D5V_S3
M_A_CS#05,12
M_A_CLK05,12
M_A_CLK#05,12
M_A_CKE05,12
M_A_BA05,12
M_A_BA15,12
M_A_ALERT_N
2016/11/25 DY
3
1D2V_S3
U1203
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
U1202
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
R1208
1 2
49D9R2F-GP
close to cpu
C1285
M_A_CLK0 M_A_CLK0
1 2
SC3300P50V2KX-1D LGP
DY
C1287
M_A_CLK#0 M_A_CLK#0
1 2
SC3300P50V2KX-1D LGP
DY
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
NF#E2/UDM#/UDBI#
NF#E7/LDM#/LDBI#
VREFCA
NC#T7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
NF#E2/UDM#/UDBI#
NF#E7/LDM#/LDBI#
VREFCA
NC#T7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1D2V_S3
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
C7
C2
C8
D3
D7
B7
A7
G3
F3
E2
E7
K3
ODT
F9
ZQ
M1
M2
BG0
N9
TEN
T3
PAR
T7
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
C7
C2
C8
D3
D7
B7
A7
G3
F3
E2
E7
K3
ODT
F9
ZQ
M1
M2
BG0
N9
TEN
T3
PAR
T7
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
M_A_DQS_DP2
M_A_DQS_DN2
M_A_DQS_DP3
M_A_DQS_DN3
TEST_MODE_3
M_A_BG1_E9_2
M_A_BG1_M9_R
M_A_DQS_DP4
M_A_DQS_DN4
M_A_DQS_DP5
M_A_DQS_DN5
TEST_MODE_4
M_A_BG1_E9_4
M_A_BG1_M9_R
M_A_DQ24 5
M_A_DQ25 5
M_A_DQ26 5
M_A_DQ27 5
M_A_DQ28 5
M_A_DQ29 5
M_A_DQ30 5
M_A_DQ31 5
M_A_DQ16 5
M_A_DQ17 5
M_A_DQ18 5
M_A_DQ19 5
M_A_DQ20 5
M_A_DQ21 5
M_A_DQ22 5
M_A_DQ23 5
M_A_DIMA_ODT0 5,12
M_A_BG0 5,12
M_A_PARITY 5,12
2016/11/29
M_A_DQ40 5
M_A_DQ41 5
M_A_DQ47 5
M_A_DQ42 5
M_A_DQ44 5
M_A_DQ45 5
M_A_DQ43 5
M_A_DQ46 5
M_A_DQ33 5
M_A_DQ37 5
M_A_DQ34 5
M_A_DQ35 5
M_A_DQ36 5
M_A_DQ32 5
M_A_DQ38 5
M_A_DQ39 5
M_A_DIMA_ODT0 5,12
M_A_BG0 5,12
M_A_PARITY 5,12
2016/11/29
A_ZQ_RAM3
M_VREF_CA_D IMMA
1
TP1203
TPAD14-OP-G P
A_ZQ_RAM2
M_VREF_CA_D IMMA
1
TP1204
TPAD14-OP-G P
1D2V_S3
1K8R2F-GP
R1222
1 2
1 2
R1223
1K8R2F-GP
2016/11/25
1D2V_S3
240R2D-GP
12
R1204
12
SCD047U25V2KX-4-GP
C1203
M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
1D2V_S3
240R2D-GP
12
R1234
12
SCD047U25V2KX-4-GP
C1286
M_A_DQS_DN[7: 0] 5
M_A_DQS_DP[7:0] 5
1D2V_S3
VDDQ/VDD 1uF x32
12
12
C1204
SC1U10V2KX-1DLGP
12
C1220
SC1U10V2KX-1DLGP
1D2V_S3
VDDQ/VDD 10uF x10
12
C1237
SC10U6D3V3MX-DL-GP
VPP 1uF x16
2D5V_S3
2017/01/17
C1205
DY
SC1U10V2KX-1DLGP
12
C1221
SC1U10V2KX-1DLGP
12
C1238
SC10U6D3V3MX-DL-GP
12
C1206
SC1U10V2KX-1DLGP
12
C1222
12
12
C1207
DY
SC1U10V2KX-1DLGP
12
C1223
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
DY
C1239
SC10U6D3V3MX-DL-GP
12
12
C1208
C1209
SC1U10V2KX-1DLGP
12
12
C1224
C1225
SC1U10V2KX-1DLGP
DY
DY
C1240
12
12
C1241
SC10U6D3V3MX-DL-GP
2017/01/17
12
12
12
12
12
C1260
C1259
SC1U10V2KX-1DLGP
2D5V_S3
DY
C1268
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
VPP 10uF x5
12
C1279
12
SC10U6D3V3MX-DL-GP
DY
C1261
C1275
12
C1269
C1262
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
C1276
12
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
M_VREF_CA_D IMMA
12
C1210
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
C1226
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
SC10U6D3V3MX-DL-GP
12
C1270
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
DY
C1277
12
C1278
SC10U6D3V3MX-DL-GP
2017/03/07
1 2
12
C1211
SC1U10V2KX-1DLGP
12
C1227
SC1U10V2KX-1DLGP
C1242
SC10U6D3V3MX-DL-GP
2017/01/17
DY
12
C1263
SC1U10V2KX-1DLGP
SC10U6D3V3MX-DL-GP
R1202
2D7R2F-1-G P
12
C1212
SC1U10V2KX-1DLGP
12
C1228
SC1U10V2KX-1DLGP
DY
12
C1243
SC10U6D3V3MX-DL-GP
12
C1264
SC1U10V2KX-1DLGP
0D6V_S0
DY
C1202
SCD022U16V2KX -3DLGP
2 1
+V_VREF_PATH 1
12
R1203
24D9R2F-L-G P
12
12
C1213
C1214
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
DY
C1230
C1229
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
2017/01/17
DY
12
C1244
SC10U6D3V3MX-DL-GP
DY
12
12
C1271
C1265
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
VTT 10uF x4
12
12
C1288
C1289
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
V_SM_VREF_CN TA 5
12
12
12
12
C1217
12
C1233
12
C1218
C1219
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
DY
C1235
C1234
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
C1215
12
C1231
C1216
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
C1232
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
DY
12
12
C1245
C1246
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
DY
DY
DY
12
12
12
12
C1266
12
12
C1273
C1274
C1267
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
C1291
SC10U6D3V3MX-DL-GP
C1272
12
SC1U10V2KX-1DLGP
C1290
SC10U6D3V3MX-DL-GP
2017/01/17
0D6V_S0
VTT 1uF x16
2017/01/17
DY
DY
DY
12
12
12
12
C1257
C1255
C1258
C1280
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2
2017/01/17
DY
DY
C1281
DY
12
12
C1282
C1283
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
DY
DY
12
12
12
12
C1284
C1293
C1294
C1292
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
2017/01/172017/03/07
DY
DY
12
12
12
C1297
C1296
C1295
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
KyloRen 13"
KyloRen 13"
KyloRen 13"
SC1U10V2KX-1DLGP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
12
C1298
SC1U10V2KX-1DLGP
DY
12
C1299
SC1U10V2KX-1DLGP
12 106
12 106
12 106
A00
A00
A00
Page 13
SSID = MEMORY
5
4
3
2
1
1D2V_S3
D D
2D5V_S3
M_B_A05,13
M_B_A15,13
M_B_A25,13
M_B_A35,13
M_B_A45,13
M_B_A55,13
M_B_A65,13
M_B_A75,13
M_B_A85,13
M_B_A95,13
M_B_A105,13
M_B_A115,13
M_B_A125,13
M_B_A135,13
M_B_A145,13
M_B_A155,13
M_B_A165,13
M_B_CS#05,13
DDR4_DR AMRST#5,12,13
M_B_ACT_N5,13
M_B_ALERT_N5,13
M_B_CLK05,13
M_B_CLK#05,13
M_B_CKE05,13
M_B_BA05,13
M_B_BA15,13
C C
1D2V_S3
2D5V_S3
M_B_A05,13
M_B_A15,13
M_B_A25,13
M_B_A35,13
M_B_A45,13
M_B_A55,13
M_B_A65,13
M_B_A75,13
M_B_A85,13
M_B_A95,13
M_B_A105,13
M_B_A115,13
M_B_A125,13
M_B_A135,13
M_B_A145,13
M_B_A155,13
M_B_A165,13
M_B_CS#05,13
B B
DDR4_DR AMRST#5,12,13
M_B_ACT_N5,13
M_B_ALERT_N5,13
M_B_CLK05,13
M_B_CLK#05,13
M_B_CKE05,13
M_B_BA05,13
M_B_BA15,13
SDP & DDP SETTING
M_B_BG1_E9_1
M_B_BG1_E9_2
M_B_BG1_E9_3
M_B_BG1_E9_4
M_B_BG1_E9_1
M_B_BG1_E9_2
M_B_BG1_E9_3
M_B_BG1_E9_4
M_B_BG15
A A
1 2
R1331 240R2F-1-GP
1 2
R1332 240R2F-1-GP
1 2
R1333 240R2F-1-GP
1 2
R1334 240R2F-1-GP
1 2
R1335 0R2J-2-GP
1 2
R1336 0R2J-2-GP
1 2
R1337 0R2J-2-GP
1 2
R1338 0R2J-2-GP
1 2
R1339 0R2J-2-GP
1 2
R1340 0R2J-2-GP
5
DDP
DDP
DDP
DDP
SDP
SDP
SDP
SDP
DDP
SDP
M_B_BG1_M9_R
U1302
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
U1304
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
ODT
ZQ
VREFCA
BG0
TEN
PAR
NC#T7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS_T
UDQS_C
LDQS_T
LDQS_C
ODT
ZQ
VREFCA
BG0
TEN
PAR
NC#T7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2017/05/10
G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7
B7
A7
G3
F3
E2
E7
K3
F9
M1
M2
N9
T3
T7
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7
B7
A7
G3
F3
E2
E7
K3
F9
M1
M2
N9
T3
T7
B2
E1
E9
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
M_B_DQS_DP0
M_B_DQS_DN0
M_B_DQS_DP1
M_B_DQS_DN1
M_B_BG1_E9_1
M_B_BG1_M9_R
M_B_DQS_DP4
M_B_DQS_DN4
M_B_DQS_DP5
M_B_DQS_DN5
TEST_MODE_6
M_B_BG1_E9_3
M_B_BG1_M9_R
M_B_DQ10 5
M_B_DQ15 5
M_B_DQ14 5
M_B_DQ11 5
M_B_DQ12 5
M_B_DQ13 5
TEST_MODE_5
M_B_DQ41 5
M_B_DQ47 5
M_B_DQ45 5
M_B_DQ46 5
M_B_DQ40 5
M_B_DQ42 5
M_B_DQ44 5
M_B_DQ43 5
M_B_DQ37 5
M_B_DQ39 5
M_B_DQ36 5
M_B_DQ34 5
M_B_DQ33 5
M_B_DQ32 5
M_B_DQ38 5
M_B_DQ35 5
M_B_PARITY 5,13
M_B_DQ9 5
M_B_DQ8 5
M_B_DQ5 5
M_B_DQ2 5
M_B_DQ0 5
M_B_DQ3 5
M_B_DQ4 5
M_B_DQ1 5
M_B_DQ6 5
M_B_DQ7 5
M_B_DQS_DP0 5
M_B_DQS_DN0 5
M_B_DQS_DP1 5
M_B_DQS_DN1 5
M_B_DIMB_ODT0 5,13
M_B_BG0 5,13
M_B_PARITY 5,13
2016/11/29
M_B_DQS_DP4 5
M_B_DQS_DN4 5
M_B_DQS_DP5 5
M_B_DQS_DN5 5
M_B_DIMB_ODT0 5,13
M_VREF_CA_D IMMB
M_B_BG0 5,13
1
2016/11/29
M_B_DQS_DN0
M_B_DQS_DN1
M_B_DQS_DN2
M_B_DQS_DN3
M_B_DQS_DN4
M_B_DQS_DN5
M_B_DQS_DN6
M_B_DQS_DN7
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_B_DQS_DP3
M_B_DQS_DP4
M_B_DQS_DP5
M_B_DQS_DP6
M_B_DQS_DP7
B_ZQ_RAM2
M_VREF_CA_D IMMB
1
TP1301
TPAD14-OP-G P
C1301
B_ZQ_RAM4
TP1302
TPAD14-OP-G P
C1343
4
1D2V_S3
R1301 240R2D-G P
12
SCD047U25V2KX-4-GP
1D2V_S3
R1305
1 2
240R2D-GP
12
SCD047U25V2KX-4-GP
1 2
M_B_DQS_DN[7: 0] 5
M_B_DQS_DP[7:0] 5
ALERT
M_B_A05,13
M_B_A15,13
M_B_A25,13
M_B_A35,13
M_B_A45,13
M_B_A55,13
M_B_A65,13
M_B_A75,13
M_B_A85,13
M_B_A95,13
M_B_A105,13
M_B_A115,13
M_B_A125,13
M_B_A135,13
M_B_A145,13
DDR4_DR AMRST#5,12,13
M_B_ACT_N5,13
M_B_ALERT_N
M_B_A155,13
M_B_A165,13
M_B_ALERT_N5,13
DDR4_DR AMRST#5,12,13
M_B_ACT_N5,13
1D2V_S3
2D5V_S3
M_B_CS#05,13
M_B_CLK05,13
M_B_CLK#05,13
M_B_CKE05,13
M_B_BA05,13
M_B_BA15,13
2D5V_S3
M_B_A05,13
M_B_A15,13
M_B_A25,13
M_B_A35,13
M_B_A45,13
M_B_A55,13
M_B_A65,13
M_B_A75,13
M_B_A85,13
M_B_A95,13
M_B_A105,13
M_B_A115,13
M_B_A125,13
M_B_A135,13
M_B_A145,13
M_B_A155,13
M_B_A165,13
M_B_CS#05,13
M_B_ALERT_N5,13
M_B_CLK05,13
M_B_CLK#05,13
M_B_CKE05,13
M_B_BA05,13
M_B_BA15,13
R1330
1 2
49D9R2F-GP
3
1D2V_S3
B3
B9
D1
G7
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
B1
R9
P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8
M8
P1
P9
K7
K8
K2
N2
N8
U1301
VDD
VDD
VDD
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
J2
VDDQ
J8
VDDQ
VPP
VPP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
L2
WE#/A14
CAS#/A15
L8
RAS#/A16
L7
CS#
RESET#
L3
ACT#
ALERT#
CK_T
CK_C
CKE
BA0
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
UDQS_T
UDQS_C
LDQS_T
LDQS_C
NF#E2/UDM#/UDBI#
NF#E7/LDM#/LDBI#
VREFCA
2017/05/10
U1303
B3
VDD
B9
VDD
D1
VDD
G7
VDD
J1
VDD
J9
VDD
L1
VDD
L9
VDD
R1
VDD
T9
VDD
A1
VDDQ
A9
VDDQ
C1
VDDQ
D9
VDDQ
F2
VDDQ
F8
VDDQ
G1
VDDQ
G9
VDDQ
J2
VDDQ
J8
VDDQ
B1
VPP
R9
VPP
NF#E2/UDM#/UDBI#
P3
A0
NF#E7/LDM#/LDBI#
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC#
T8
A13
L2
WE#/A14
M8
CAS#/A15
L8
RAS#/A16
L7
CS#
P1
RESET#
L3
ACT#
P9
ALERT#
K7
CK_T
K8
CK_C
K2
CKE
N2
BA0
N8
BA1
MT40A256M16GE-083E- B-COLAY1-GP
ZZ.00PAD.0Q2
2017/05/10
1D2V_S3
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
M_B_DQS_DP2
B7
M_B_DQS_DN2
A7
M_B_DQS_DP3
G3
M_B_DQS_DN3
F3
E2
E7
K3
ODT
F9
ZQ
M1
M2
BG0
N9
TEN
T3
PAR
T7
NC#T7
B2
VSS
E1
VSS
M_B_BG1_E9_2
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M_B_BG1_M9_R
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
G2
DQ0
F7
DQ1
H3
DQ2
H7
DQ3
H2
DQ4
H8
DQ5
J3
DQ6
J7
DQ7
A3
DQ8
B8
DQ9
C3
DQ10
C7
DQ11
C2
DQ12
C8
DQ13
D3
DQ14
D7
DQ15
B7
UDQS_T
A7
UDQS_C
G3
LDQS_T
F3
LDQS_C
E2
E7
K3
ODT
F9
ZQ
M1
VREFCA
M2
BG0
N9
TEN
T3
PAR
T7
NC#T7
B2
VSS
E1
VSS
E9
VSS
G8
VSS
K1
VSS
K9
VSS
M9
VSS
N1
VSS
T1
VSS
A2
VSSQ
A8
VSSQ
C9
VSSQ
D2
VSSQ
D8
VSSQ
E3
VSSQ
E8
VSSQ
F1
VSSQ
H1
VSSQ
H9
VSSQ
CLK
CTRL/CKE/CMD
TEST_MODE_7
M_B_DQS_DP6
M_B_DQS_DN6
M_B_DQS_DP7
M_B_DQS_DN7
TEST_MODE_8
M_B_BG1_E9_4
M_B_BG1_M9_R
M_B_DQ25 5
M_B_DQ29 5
M_B_DQ30 5
M_B_DQ27 5
M_B_DQ24 5
M_B_DQ28 5
M_B_DQ31 5
M_B_DQ26 5
M_B_DQ18 5
M_B_DQ20 5
M_B_DQ22 5
M_B_DQ16 5
M_B_DQ23 5
M_B_DQ17 5
M_B_DQ21 5
M_B_DQ19 5
M_B_DQS_DP2 5
M_B_DQS_DN2 5
M_B_DQS_DP3 5
M_B_DQS_DN3 5
M_B_DIMB_ODT0 5,13
M_B_BG0 5,13
M_B_PARITY 5,13
2016/11/29
M_B_DQ58 5
M_B_DQ60 5
M_B_DQ62 5
M_B_DQ61 5
M_B_DQ57 5
M_B_DQ56 5
M_B_DQ63 5
M_B_DQ59 5
M_B_DQ51 5
M_B_DQ49 5
M_B_DQ55 5
M_B_DQ52 5
M_B_DQ54 5
M_B_DQ48 5
M_B_DQ53 5
M_B_DQ50 5
M_B_DIMB_ODT0 5,13
M_B_PARITY 5,13
2016/11/29
2016/11/28
M_B_BG1_M9_R
M_B_CKE0
M_B_A15
M_B_A16
M_B_A14
M_B_CS#0
M_B_A4
M_B_A6
M_B_A0
M_B_PARITY
M_B_A13
M_B_A9
M_B_A1
M_B_A5
M_B_ACT_N
M_B_DIMB_ODT0
M_B_A10
M_B_BA0
M_B_A3
M_B_BA1
M_B_BG0
M_B_A12
M_B_A11
M_B_A2
M_B_A8
M_B_A7
B_ZQ_RAM1
1
TPAD14-OP-G P
M_B_DQS_DP6 5
M_B_DQS_DN6 5
M_B_DQS_DP7 5
M_B_DQS_DN7 5
M_B_BG0 5,13
2016/11/29
M_B_CLK0
M_B_CLK#0
1D2V_S3
1 2
M_VREF_CA_D IMMB
R1304
240R2D-GP
TP1303
12
C1303
SCD047U25V2KX-4-GP
1D2V_S3
R1306
240R2D-GP
B_ZQ_RAM3
1 2
M_VREF_CA_D IMMB
1
TP1304
12
TPAD14-OP-G P
SCD047U25V2KX-4-GP
C1336
R1313 36R2F-1-GP
1 2
R1314 36R2F-1-GP
1 2
DDP
R1312 36R2F-1-GP
1 2
R1311 36R2F-1-GP
1 2
RN1302
1
8
2
7
3
6
4 5
SRN36J-GP
RN1303
1
8
2
7
3
6
4 5
SRN36J-GP
RN1304
1
8
2
7
3
6
4 5
SRN36J-GP
RN1305
1
8
2
7
3
6
4 5
SRN36J-GP
RN1306
1
8
2
7
3
6
4 5
SRN36J-GP
RN1307
1
8
2
7
3
6
4 5
SRN36J-GP
1D2V_S3
2016/11/25
0D6V_S0
2
1K8R2F-GP
R1320
1 2
1 2
R1321
1K8R2F-GP
2017/03/07
M_VREF_CA_D IMMB
2D5V_S3
0D6V_S0
1 2
1D2V_S3
VDDQ/VDD 1uF x32
12
C1304
SC1U10V2KX-1DLGP
12
C1320
SC1U10V2KX-1DLGP
1D2V_S3
VDDQ/VDD 10uF x10
12
C1390
SC10U6D3V3MX-DL-GP
2D5V_S3
VPP 1uF x16
12
C1337
DY
SC1U10V2KX-1DLGP
VPP 10uF x5
12
C1371
SC10U6D3V3MX-DL-GP
VTT 1uF x16
DY
12
12
C1354
C1355
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2016/11/25 DY
R1302
2D7R2F-1-G P
C1302
SCD022U16V2KX -3DLGP
2 1
+V_VREF_PATH 2
12
R1303
24D9R2F-L-G P
12
C1305
SC1U10V2KX-1DLGP
12
C1321
SC1U10V2KX-1DLGP
12
12
C1307
C1306
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
C1322
C1323
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
12
12
DY
DY
C1391
C1392
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
12
C1338
SC1U10V2KX-1DLGP
12
12
C1340
C1339
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
12
12
DY
C1372
12
C1373
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
DY
DY
12
12
12
C1357
C1356
C1358
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
close to cpu
C1388
M_B_CLK0 M_B_CLK0
1 2
SC3300P50V2KX-1D LGP
DY
C1389
M_B_CLK#0 M_B_CLK#0
1 2
SC3300P50V2KX-1D LGP
DY
2017/01/17
12
C1308
SC1U10V2KX-1DLGP
DY
12
C1324
SC1U10V2KX-1DLGP
DY
2017/01/17
12
C1393
SC10U6D3V3MX-DL-GP
DY
12
C1341
SC1U10V2KX-1DLGP
DY
C1374
SC10U6D3V3MX-DL-GP
12
V_SM_VREF_CN TB 5
12
C1309
SC1U10V2KX-1DLGP
DY
12
C1325
SC1U10V2KX-1DLGP
DY
12
C1394
SC10U6D3V3MX-DL-GP
12
C1342
SC1U10V2KX-1DLGP
12
C1375
SC10U6D3V3MX-DL-GP
DY
12
C1360
C1359
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
2017/01/17
12
12
C1310
12
C1311
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
C1327
C1326
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
C1312
SC1U10V2KX-1DLGP
12
C1328
SC1U10V2KX-1DLGP
12
12
12
12
12
C1313
SC1U10V2KX-1DLGP
12
C1329
SC1U10V2KX-1DLGP
C1314
SC1U10V2KX-1DLGP
12
C1330
SC1U10V2KX-1DLGP
C1315
SC1U10V2KX-1DLGP
12
C1331
SC1U10V2KX-1DLGP
DY
DY
C1316
SC1U10V2KX-1DLGP
12
C1332
SC1U10V2KX-1DLGP
DY
C1317
SC1U10V2KX-1DLGP
12
C1333
SC1U10V2KX-1DLGP
DY
12
12
C1318
C1319
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
12
12
C1334
C1335
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
2017/01/17
DY
12
12
C1396
C1395
SC10U6D3V3MX-DL-GP
DY
12
12
C1397
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
C1398
12
C1399
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
DY
DY
12
12
12
C1345
C1344
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
C1346
SC1U10V2KX-1DLGP
12
C1347
SC1U10V2KX-1DLGP
0D6V_S0
12
12
C1348
C1349
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
VTT 10uF x4
12
12
C1350
C1351
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
12
12
C1353
C1352
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2017/01/17
DY
DY
12
C1376
SC10U6D3V3MX-DL-GP
DY
12
12
12
C1377
C1379
C1378
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2017/01/17
DY
DY
DY
12
C1361
SC1U10V2KX-1DLGP
DY
12
12
12
C1363
C1364
C1362
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DY
DY
DY
DY
12
12
12
C1365
SC1U10V2KX-1DLGP
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
Date: Sheet of
12
C1367
C1366
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
DDR3-SODIMM1
DDR3-SODIMM1
DDR3-SODIMM1
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
1
12
C1369
C1368
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
KyloRen 13"
KyloRen 13"
KyloRen 13"
13 106
13 106
13 106
A00
A00
A00
Page 14
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
(Reserved)_SODIMM _SODIMM4
(Reserved)_SODIMM _SODIMM4
(Reserved)_SODIMM _SODIMM4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
14 106Thursday, June 29, 2017
14 106Thursday, June 29, 2017
14 106Thursday, June 29, 2017
1
Page 15
5
4
3
2
1
SSID = PCH
3D3V_S0
CPU1I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
D D
C C
C38
D38
C36
D36
A38
B38
C31
D31
C33
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3
CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
SKYLAKE-U-GP
SKYLAKE_ULT
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
9 OF 20
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
EMMC_RCOMP
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
DC resistance < 0.5ohm.
CSI2_COMP
1 2
R1501 100R2F-L1-GP-U
WIFI_RF_EN 66
GPP_F: VCCPGPPF = 1.8V Only
R1502
EMMC_RCOMP
1 2
200R2F-L-GP
WIFI_RF_EN
071.SKYLA.000U
R1503
12
DY
10KR2J-3-GP
Change to Dummy 20150402
[#545659 Rev0.7]
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(CS-2/EMMC)
CPU_(CS-2/EMMC)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(CS-2/EMMC)
KyloRen 13"
KyloRen 13"
KyloRen 13"
15 106Thursday, June 29, 2017
15 106Thursday, June 29, 2017
15 106Thursday, June 29, 2017
1
A00
A00
A00
Page 16
5
4
3
2
1
SSID= PCH
#543016:
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2.
GPU
D D
Swap Net follow DELL HSIO 20161025
LAN
WLAN
WLAN_PC IE_RX_N66
WLAN_PC IE_RX_P66
WLAN_PC IE_TX_N66
WLAN_PC IE_TX_P66
C1601
C1602
1 2
1 2
SCD1U25V2KX- 1-DL-GP
WLAN_PC IE_TX_N_C
WLAN_PC IE_TX_P_C
SCD1U25V2KX- 1-DL-GP
HDD1
MSATA_PCIE_RX_N 963
MSATA_PCIE_RX_P963
MSATA_PCIE_TX_N 963
MSATA_PCIE_TX_P963
MSATA_PCIE_RX_N 1063
MSATA_PCIE_RX_P1 063
MSATA_PCIE_TX_N 1063
MSATA_PCIE_TX_P1063
SSD
C C
+V1.8A_SIP
1 2
R1607 10KR2J-3-GP
XDP_PRDY#99
XDP_PREQ#99
MSATA_PCIE_RX_N 1163
MSATA_PCIE_RX_P1 163
MSATA_PCIE_TX_N 1163
MSATA_PCIE_TX_P1163
MSATA_SATA_R X_N263
MSATA_SATA_R X_P263
MSATA_SATA_TX _N263
MSATA_SATA_TX _P263
Layout Note:
PIRQA#
1 2
R1604
100R2F-L1-GP- U
1. Trace Width: 4 mils min (breakout) 12-15 mils (trace)
Note: Must maintain low DC resistance routing (<0.1 ohm).
2. Isolation Spacing: At least 12 mils to any adjacent
high speed I/O.
PCIE_RCOMPN
PCIE_RCOMPP
PIRQA#
CPU1H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKYLAKE-U-GP
071.SKYLA.000U
SKYLAKE_ULT
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
8 OF 20
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
DC resistance < 0.5ohm.
AB6
USBCOMP
USB2_ID
AG3
USB2_VBUSSEN SE
AG4
A9
C9
USB_OC2#
D9
USB_OC3#
B9
J1
SIO_EXT_SCI#
J2
J3
GPP_E0/SATAXPC IE0/SATAGP0
H2
GPP_E1/SATAXPC IE1/SATAGP1
H3
G4
H1
USB1_USB20_N 34
USB1_USB20_P 34
USB2_USB20_N 66
USB2_USB20_P 66
TYPEC_USB20_N 3 8
TYPEC_USB20_P 38
CCD_USB20_ N 55
CCD_USB20_ P 5 5
CARD1_USB 20_N 66
CARD1_USB 20_P 66
BT_USB20_N 66
BT_USB20_P 66
FP1_USB20_N 92
FP1_USB20_P 92
1 2
R1603 1 13R2F-GP
USB_OC0# 34,35
USB_OC1# 66
SSD_DEVSLP 63
1
1
USB1_USB30_RX _N1 36
USB1_USB30_RX _P1 36
USB1_USB30_TX _N1 36
USB1_USB30_TX _P1 36
USB2_USB30_RX _N3 66
USB2_USB30_RX _P3 66
USB2_USB30_TX _N3 66
USB2_USB30_TX _P3 66
TYPEC_USB30_RX _N4 38
TYPEC_USB30_RX _P4 38
TYPEC_USB30_TX _N4 38
TYPEC_USB30_TX _P4 38
Follow SKL PDG design guide
(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND
using 8.2 KΩ to 10 KΩ on the motherboard.
Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable.
(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
For power share
USB3.0
IO board USB3.0
Type-c Full
For power share
USB3.0
IO board USB3.0
Type-c Full
CAMERA
Card Reader
Swap Net follow DELL HSIO 20161025
WLAN (BT)
Touch Panel
Fingerprint Reader
Remove Sensor HUB
(#543016) When used as DEVSLP, no external pull-up or pull-down
termination required from SATA Host DEVSLP.
TP1602 TPAD14-OP-GP
TP1603 TPAD14-OP-GP
M2_SSD_PEDET 63
SATA_LED# 64
USB2_ID
USB2_VBUSSEN SE
R1601 0R0402-PAD
1 2
R1602 0R0402-PAD
1 2
2016/12/28
USB_OC2#
USB_OC3#
USB_OC0#
USB_OC1#
SIO_EXT_SCI#
RN1601
8
7
6
SRN10KJ-6-G P
R1608 10KR2J-3-GP
3D3V_S5_PCH
1
2
3
45
3D3V_S0
12
3D3V_S0
R1606
SATA_LED#
(#543611)
The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.
12
10KR2J-3-GP
USB 2.0 Table
Pair
Device
USB3.0 port1
1
N/A
2
USB3.0 Port2 (IOBD)
3
Type-c
4
CAMERA
5
WLAN
6
Touch Panel
7
8
#545659 (SKL_PCH_U_Y_EDS Rev0.7)
B B
Card Reader
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Taipei Hsie n 221, Taiwan, R.O. C.
CPU_(PCIE/SATA/USB)
CPU_(PCIE/SATA/USB)
CPU_(PCIE/SATA/USB)
KyloRen 13"
KyloRen 13"
KyloRen 13"
16 106Thursday, June 29, 2017
16 106Thursday, June 29, 2017
16 106Thursday, June 29, 2017
A00
A00
A00
Page 17
SSID = PCH
5
4
3
2
1
3D3V_S5
D D
C C
RTC_AUX_S5
+V3.3A_SIP
R1709,R1723,R1703,R1724 merge to RN1704
RN1704
1
2
3
4 5
SRN10KJ-6-GP
R1730
330KR2J-L1-GP
1 2
R1731
20KR2J-L2-GP
RN1703
1
2 3
SRN10KJ-5-GP
DY
EXT_PW R_GATE#
4
12
1 2
R1717 10KR2J-3-GP
AC_PRESENT
8
PCIE_WAKE#_CPU
7
PCH_BATLOW#
6
GPD11/LANPHYPC
GPD11 pull high by Intel PDG1.3 request
#544669 (CRB): 330k.
SM_INTRUDER#
[#543016 Rev0.7]
EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k
pull-down that is active during the early portion of the power up sequence
PM_RSMRST#
PM_PCH_PWROK
SYS_PWROK
#544669 Rev0.52 CRB:
No PL resistor on THERMTRIP#.
H_CPUPW RGD
R1714
10KR2J-3-GP
12
DY
EC1701
AZ5725-01FDR7G-GP
EMI DVT1 0210
2016/12/29
+V1.8A_SIP
+VCCPDSW_3P33D3V_S5
1 2
R1711
0R0603-PAD
Layout note: 3 PAD SHARING
XDP_DBRESET#99
SYS_PWROK24,99
12
DY
ME_SUS_PWR_ACK_R SUSACK#_R
RESET_OUT#24,26
PCIE_WAKE#_CPU24
+VCCPDSW_3P3
1 2
0R0402-PAD
2016/12/28
+V3.3A_SIP
12
R1701
10KR2J-3-GP
H_VCCST_PWRGD99
1 2
R1706 0R0402-PAD
1 2
R1704 0R0402-PAD
2016/12/28
1 2
R1707
10KR2J-3-GP
(PDG#543016)
WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns.
R1708
1
TP1705TPAD14-OP-GP
2017/04/24
PCH_PLTRST#
PM_RSMRST#
H_CPUPW RGD
SYS_PWROK
PM_PCH_PWROK
PCH_DPW ROKPM_RSMRST#
ME_SUS_PWR_ACK_R
SUSACK#_R
LAN_WAKE#
GPD11/LANPHYPC
CPU1K
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/USB2_WAKEOUT#
SKYLAKE-U-GP
SYSTEM POWER MANAGEMENT
SKYLAKE_ULT
071.SKYLA.000U
11 OF 20
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
AC_PRESENT
PCH_BATLOW#
SM_INTRUDER#
EXT_PW R_GATE#
VRALERT#
AUX_EN_WOW L 24,61
1
SIO_SLP_S0# 24,40,91
SIO_SLP_S3# 24,40,51
SIO_SLP_S4# 40,54
SIO_PWRBTN# 24,99
TP1708 TPAD14-OP-GP
BATLOW#:
Pull-up required even if not implemented.
AC_PRESENT
EC1707
12
DY
SCD1U16V2KX-3GP
Dis-wire with XDP_PM_RSMRST_PWRGD_XDP
3D3V_S0
1 2
12
R1718
100KR2F-L1-GP
R1719
47KR2F-GP
H_VCCST_PWRGD
12
DY
C1711
SCD1U25V2KX-1-DL-GP
2016/12/07 for power sequence
XDP_DBRESET#
SYS_PWROK
PLT_RST#
RESET_OUT#
3V_5V_POK
12
EC1705
DY
AZ5725-01FDR7G-GP
12
EC1708
DY
AZ5725-01FDR7G-GP
EMI DVT1 0210
3D3V_AUX_S5
PLT_RST#26,63,66,91,99
100KR2J-1-GP
R1722 & EC1708 modify to 100k and 0.01uF at DVT1
#543016 Rev0.7
1. VCCST_PWRGD is only 1.0 V tolerant.
2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
4th = 84.DMN66.03F
3rd = 75.00601.07C
2nd = 84.2N702.E3F
84.2N702.A3F
Q1702
2N7002KDW-GP
34
2
5
R1737
1 2
NON DS3
100KR2J-1-GP
PM_RSMRST#_M
NON DS3
6
1
R1713
1 2
0R0402-PAD
12
12
R1715
DY
DY
D1701
RB751V-40H-GP
C1701
SC220P50V2KX-3GP
83.R2004.G8F
PM_RSMRST#_R PM_RSMRST#
R1720
1 2
0R0402-PAD
PCH_PLTRST#
KA
ACOK_IN_M 43,44
AC_PRESENT
2016/12/28
R1724
R1735
ME_SUS_PWR_ACK_R
+VCCMPHYGTAON_1P0_LS_SIP
12
C1704
SC10U6D3V3MX-DL-GP
RUNPWROK24,40
EMI DVT1 0210
EC1706
12
DY
SC1KP50V2KX-1GP
2017/03/16
12
EC1709
DY
AZ5725-01FDR7G-GP
ED1701
AZ5125-02S-R7G-GP
2
1
3
75.05125.07D
1 2
R1716
100KR2F-L1-GP
DY
12
EC1704
DY
AZ5725-01FDR7G-GP
1 2
R1738 10KR2J-3-GP
DY
AOZ Power switch, P/N: 074.01334.0093
Low Rds(on)= 5m Ohm
Turn on rise time = 10us
+VCCMPHYGTAON_1P0
SKL: 1.0V
+VCCMPHYGTAON_1P0(ICCMAX.=3.5A)
1D0V_S5
EC1710
SC2D2U6D3V2MX-DL-GP
B B
RF request 2016/01/12 modify
2017/05/08
12
1 2
0R0805-PAD
DY
1 2
0R0805-PAD
Follow Iris SKL
2015/11/30 modify
Reserve by NON DS3 function 20150413
2017/05/05
3D3V_AUX_S5
R1726
10KR2J-3-GP
1 2
A A
R1727
100KR2J-1-GP
1 2
NON DS3
3V_5V_POK#
Q1701
4 3
S2
G2
6
D1
PJT138KA-GP
1KR2J-1-GP
PM_RSMRST#
D2
3V_5V_POK_C
25
G1
1
S1
R1702
1 2
R1728
1 2
0R0402-PAD
2016/12/28
PCH_RSMRST# 24,99
3V_5V_POK 40,45,52,54
12
DY
C1710
EC1712
12
DY
075.00138.0A7C
2017/03/09
5
SCD47U10V2KX-GP
Dummy C1710 by it's useless
SCD1U16V2KX-3GP
EC1711 modify to 100k and 0.01uF at DVT1 20150203
4
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(POWER MANAGEMENT)
CPU_(POWER MANAGEMENT)
CPU_(POWER MANAGEMENT)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
17 106Thursday, June 29, 2017
17 106Thursday, June 29, 2017
17 106Thursday, June 29, 2017
A00
A00
A00
Page 18
5
SSID = PCH
D D
3D3V_S5_PCH
+V1.8A_SIP
C C
R1835 and R1834 merge to RN1802
2015/10/06 modify
1
2 3
R1820
1 2
10KR2J-3-GP
R1821
1 2
10KR2J-3-GP
SERIRQ PH:
PDG: 8.2k
CRB: 10k
RN1802
SRN1KJ-7-GP
SPI_HOLD_ROM
4
SPI_WP_ROM
SIO_RCIN#
ESPI_ALERT#
SPI_CLK_ROM25,91
SPI_SO_ROM25,91
SPI_SI_ROM25,91
SPI_WP_ROM25,99
SPI_HOLD_ROM25
SPI_CS_ROM_N025
SPI_CS_ROM_N291
2016/11/25 change to CS2
2017/05/08
FFS_INT170
91
RCIN#:
Frequency to Avoid: 33 MHz
2016/11/4
SPI_SI_XDP99
R1806,R1807,R1808,R1809 merge to RN1803
2015/10/06 modify
RN1803
1
2
3
4 5
SRN10J-1-GP
1 2
1 2
1 2
TPM
TPM_SPI_IRQ#
ESPI_ALERT#24
For eSPI
3D3V_S5_PCH
12
R1822
1KR2J-1-GP
PLACE WITHIN 1.1 INCH OF PCH
8
7
6
SPI_CLK_CPU
SPI_SO_CPU
SPI_SI_CPU
SPI_WP_CPU
R181110R2F-L-GP
R18120R0402-PAD
R18380R2J-2-GP
TP1804TPAD14-OP-GP
TP1805TPAD14-OP-GP
TP1806TPAD14-OP-GP
4
R9935
1 2
XDP
SPI_HOLD_CPU
SPI_CS_CPU_N0
SPI_CS_CPU_N2
CPU_D4_TP
1
CPU_D5_TP
1
CPU_D6_TP
1
SIO_RCIN#
1KR2J-1-GP
PCH strap pin:
BOOT HALT
SPI0_MOSI
This signal has a weak internal pull-up.
(#543016)Optional, can be left as OPEN/No-Connect.
SPI_SI_CPU
CPU1E
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
AW13
AY11
M2
M3
J4
V1
V2
M1
G3
G2
G1
SPI - FLASH
SPI0_CLK
SPI0_MISO
Strap
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
SKYLAKE-U-GP
071.SKYLA.000U
0 = ENABLED
1 = DISABLED
WEAK INTERNAL PU
SKYLAKE_ULT
LPC
3
For eSPI
5 OF 20
SMBUS, SMLINK
Strap
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
20140820 DAIVD
SPI_SI_CPU
ESPI_IO[3..0]24,68
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
MEM_SMBCLK
MEM_SMBDATA
SMB_ALERT#
SML0_SMBCLK
SML0_SMBDATA
SML0_ALERT#
SML1_SMBCLK
SML1_SMBDATA
SML1ALERT#
PCH_ESPI_IO0
PCH_ESPI_IO1
PCH_ESPI_IO2
PCH_ESPI_IO3
PCH_ESPI_CLK
PCH Prim
3D3V_S5_PCH
12
DY
12
DY
ESPI_IO[3..0]
R1824
1KR2J-1-GP
R1825
1KR2J-1-GP
ESPI_IO3
ESPI_IO1
ESPI_IO2
ESPI_IO0
SML1_SMBCLK 24,26
SML1_SMBDATA 24,26
RN1806
6
7
8
SRN15J-GP
CLKRUN#
2
PCH_ESPI_CLK
R1818
8K2R2F-1-GP
1 2
DY
PCH_ESPI_IO3
PCH_ESPI_IO1
PCH_ESPI_IO2
PCH_ESPI_IO0
+V1.8A_SIP
45
3
2
1
ESPI_CS# 24,68
ESPI_RESET# 24,68
CLKRUN# 24
2016/10/31modify
1 2
R1805 15R2F-2-GP
EC1801
12
DY
MEM_SMBDATA
84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
MEM_SMBCLK
DVT1 0210, Reserve by Intel MOW
SC10P50V2JN-4GP
SML1_SMBDATA
SML1_SMBCLK
SML0_SMBDATA
SML0_SMBCLK
SML1ALERT#
SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
ESPI_CLK 24,68
3D3V_S0
2N7002KDW-GP
6
5
Q1801
1
3D3V_S5_PCH
RN1807
1
8
2
7
3
6
45
SRN2K2J-4-GP
12
R1837150KR2J-GP
R1836
12
2K2R2J-2-GP
SRN2K2J-1-GP
23
1
4
RN1811
RN1810
23
3D3V_S0
1
4
SRN10KJ-5-GP
1
2
34
PCH_SMBDATA 99
PCH_SMBCLK 99
SML0_ALERT#
B B
PCH strap pin:
eSPI or LPC
SML0ALERT# /
GPP_C5
Sampled at rising edge of RSMRST#
This signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.
12
DY
R1823
1KR2J-1-GP
SC1P50V2CN-3-GP
2017/03/15
C1804
R1815 10MR2J-L-GP
2 3
1 2
1 2
X1802
41
XTAL-32D768KHZ-68-GP
82.30001.G01
This signal has a weak internal pull-down.
CPU1J
3D3V_S0
RN1813
1
2
3
4 5
SRN10KJ-6-GP
A A
2017/04/24
CLK_PCIE_NVME_REQ#
8
CLK_PCIE_SD_REQ#
7
CLK_PCIE_TBT_REQ#
6
CLK_PCIE_WLAN_REQ#
2016/11/04
GPU
WLAN
LAN
2016/11/04
SSD
WLAN_CLK_CPU#66
WLAN_CLK_CPU66
CLK_PCIE_WLAN_REQ#66
2016/11/04
2017/04/24
MSATA_CLK_CPU#63
MSATA_CLK_CPU63
CLK_PCIE_NVME_REQ#63
2017/04/24
CLK_PCIE_SD_REQ#
CLK_PCIE_TBT_REQ#
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKYLAKE-U-GP
071.SKYLA.000U
CLOCK SIGNALS
SKYLAKE_ULT
10 OF 20
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
SUSCLK_R
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTC_X1
RTC_X2
SRTC_RST#
RTC_RST#
1 2
R1813
0R0402-PAD
1 2
R1803
2K7R2F-GP
Intel recommend: 2.71k ohm 1%
RTCRST_ON24
+V1.00A_SIP
12
R1816
10KR2J-3-GP
PCIE_CLK_XDP_N 99
PCIE_CLK_XDP_P 99
SUS_CLK 24
+V1.05S_AXCK_LCPLL
Q1802
G
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
(#514849)
RTC_AUX_S5
D
21
12
G1801
GAP-OPEN
C1806
SC1U10V2KX-1DLGP
Layout: Place at the open door area.
5
4
3
2
RTC_X1
RTC_X2
12
C1803
SC1P50V2CN-3-GP
2017/03/15
1
23
RN1801
SRN20KJ-1-GP
4
12
C1805
SC1U10V2KX-1DLGP
2017/03/17
XTAL24_IN XTAL24_IN_R
R1839
1 2
0R0402-PAD-2-GP
2017/05/09
0R0402-PAD-2-GP
SUSCLK_R
1 2
PESD5V0U1BL-GP-U1
R1840
1 2
SRTC_RST#
RTC_RST#
20160816 EMI
ED1802
DY
PESD5V0U1BL-GP-U1
ED1801
DY
XTAL24_OUT
1 2
2016/12/14 vendor suggest
C1801
12
R1802
1MR2J-1-GP
XTAL24_OUT_L
12
U22
1 2
0R0402-PAD
X1801
U22
INPUT/OUTPUT#1
INPUT/OUTPUT#3
XTAL-24MHZ-135-GP
R1810
NC#2
XTAL24_OUT_R
1
2
3
082.30006.0041
SC18P50V2JN-1DLGP
U22
C1802
12
SC18P50V2JN-1DLGP
U22
EC1803
DY
1 2
SC4D7P50V2BN-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(LPC/SPI/SMBUS/CL/CLK)
CPU_(LPC/SPI/SMBUS/CL/CLK)
CPU_(LPC/SPI/SMBUS/CL/CLK)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
18 106Thursday, June 29, 2017
18 106Thursday, June 29, 2017
18 106Thursday, June 29, 2017
A00
A00
A00
Page 19
5
4
3
2
1
SSID = PCH
Strap pin:
Port B /
Port C Detected
DDPB_CTRLDATA
D D
DDPC_CTRLDATA
These two signals have weak internal pull-down.
3D3V_S5
12
R1910
10KR2J-3-GP
fTPM
TPM_ID
12
R1911
10KR2J-3-GP
TPM
C C
Sampled at rising edge of PCH_PWROK
0 = Port B is not detected.
1 = Port B is detected.
*
0 = Port C is not detected.
1 = Port C is detected.
*
HDA_SYNC
HDA_BITCLK
HDA_SDOUT
HDA_SDIN027
HDA_RST#
TPAD14-OP-GP
TP1903
SPKR27
1
PROJECT_ID1
PROJECT_ID0
PROJECT_ID2
PROJECT_ID3
TPM_ID
CPU1G
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
AUDIO
SKYLAKE_ULT
7 OF 20
SDIO/SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
SD_RCOMP
1 2
R1901
200R2F-L-GP
KB_LED_BL_DET 65
2016/12/20
PCH strap pin:
Flash Descriptor Security Overide/
Intel ME Debug Mode
HDA_SDOUT
Low = Default
High = Enable
The internal pull-down is disabled after
PLTRST# deasserts
B B
1 2
EC1901
1 2
DY
SC10P50V2JN-4DLGP
HDA_RST#
ED1901
PESD5V0U1BL-GP-U1
DY
*
HDA_CODEC_BITCLK
2017/03/17
PCH strap pin:
NO REBOOT
Low = Enable (Default)
HDA_SPKR
The internal pull-down is disabled after
PLTRST# deasserts
*
HDA_CODEC_SYNC27
HDA_CODEC_BITCLK27
HDA_CODEC_SDOUT27
ME_FWP24
High = Disable
R1907,R1912 merge to RN1902
2015/10/06 modify
3D3V_S0
1 2
R1908 0R0402-PAD
SRN33J-5-GP-U
2 3
1
RN1902
1 2
R1909 1KR2J-1-GP
4
1 2
SKYLAKE-U-GP
1KR2J-1-GP
R2006
DY
HDA_SYNC
HDA_BITCLK
HDA_SDOUT
071.SKYLA.000U
SPKR
2016/11/01modify
2016/11/25 modify power rail
+V1.8A_SIP +V1.8A_SIP +V1.8A_SIP +V1.8A_SIP
3000/7000
12
12
5000
R1913
10KR2J-3-GP
PROJECT_ID0 PROJECT_ID1 PROJECT_ID2 PROJECT_ID3
R1912
10KR2J-3-GP
3000/5000
12
R1915
10KR2J-3-GP
12
R1914
10KR2J-3-GP
7000
Inspiron/Latitude
12
R1917
10KR2J-3-GP
12
R1916
10KR2J-3-GP
Vostro
Inspiron/Vostro
12
R1919
10KR2J-3-GP
12
R1918
10KR2J-3-GP
Latitude
HDA_CODEC_SDOUT
SC33P50V2JN-3DLGP
12
A A
DY
EC1903
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(AUDIO/SDIO/SDXC)
CPU_(AUDIO/SDIO/SDXC)
20160812 EMI
5
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(AUDIO/SDIO/SDXC)
KyloRen 13"
KyloRen 13"
KyloRen 13"
19 106Thursday, June 29, 2017
19 106Thursday, June 29, 2017
19 106Thursday, June 29, 2017
1
A00
A00
A00
Page 20
5
SSID = PCH
3D3V_S0
D D
1 2
DEBUG
1 2
DEBUG
1 2
DY
1 2
1 2
1 2
1 2
3D3V_S5_PCH
1 2
R2040 10KR2J-3-GP
1 2
R2041 10KR2J-3-GP
C C
R204851KR2J-1-GP
R204951KR2J-1-GP
R204210KR2J-3-GP
R204310KR2J-3-GP
R204410KR2J-3-GP
R204510KR2J-3-GP
R204610KR2J-3-GP
UART_2_CRXD_DTXD
UART_2_CTXD_DRXD
BLUETOOTH_EN
DBC_PANEL_EN
FFS_INT2
KB_DET#
IR_CAM_DET#
RTC_DET#
SIO_EXT_W AKE#
2016/11/02 modify
Change to Dummy 20150402
2016/11/02 modify
Touch panel
10KR2J-3-GP
SPK_ID
10KR2J-3-GP
TOUCH_DETECT55
2016/12/23
PTP
3D3V_S0
R2047
SPK_ID1
R2036
SPK_ID2
RAM ID
Samsung
Hynix
MEM_CONFIG [0]Vender CapacityMfr. PN
0
0
MEM_CONFIG[1:2] MEM_CONFIG[3:4]
01 00 K4AAG165WB-BCRC 16G
01 16G10 H5ANAG6NAMR-UHC
DBC_PANEL_EN55
TP2018
TPAD14-OP-GP
SPK_ID29
BLUETOOTH_EN66
1 2
R2039
DY
0R2J-2-GP
UART_2_CRXD_DTXD68
UART_2_CTXD_DRXD68
SIO_EXT_W AKE#24
KB_DET#65
I2C0_SDA_TCH_PAD65
I2C0_SCL_TCH_PAD65
I2C0_SDA_TCH_PNL55
I2C0_SCL_TCH_PNL55
2017/04/24
12
12
for 15"
1
4
VRAM_ID1
NRB_BIT
GPP_B22
MEM_CONFIG0
MEM_CONFIG1
MEM_CONFIG2
MEM_CONFIG3
MEM_CONFIG4
MEM_CHA_EN
TOUCH_DETECT_R
BOARD_ID2
CPU1F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
SKYLAKE-U-GP
071.SKYLA.000U
Wistron. P/N
TBD
TBD
3
LPSS ISH
Strap
1.8V Only
SKYLAKE_ULT
GPP_D10/ISH_SPI_CLK
GPP_D11/ISH_SPI_MISO
GPP_D12/ISH_SPI_MOSI
GPP_D5/ISH_I2C0_SDA
1.8V Only
GPP_D13/ISH_UART0_RXD/SML0BDATA
GPP_D14/ISH_UART0_TXD/SML0BCLK
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
10KR2J-3-GP
MEM_CONFIG0 MEM_CONFIG1
10KR2J-3-GP
GPP_D7/ISH_I2C1_SDA
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D15/ISH_UART0_RTS#
GPP_A12/BM_BUSY#/ISH_GP6
12
R2016
SDP
12
R2015
DDP
6 OF 20
GPP_D9/ISH_SPI_CS#
GPP_D6/ISH_I2C0_SCL
GPP_D8/ISH_I2C1_SCL
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
USB_UART_SEL_D9
RTC_DET#
ISH_I2C0_SDA
ISH_I2C0_SCL
I2C1_SDA
I2C1_SCL
MEM_CHB_EN
2017/04/24
VRAM_ID2
UART0_RTS#
UART0_CTS#
BOARD_ID1
UART1_RTS#
UART1_CTS#
ISH_KB_DISABLE
GSEN_INT1_ISH
GSEN_INT2_ISH
GSEN2_INT1_ISH
GSEN2_INT2_ISH
GYRO_INT_ISH
GYRO_DRDY_ISH
R2018
10KR2J-3-GP
R2017
10KR2J-3-GP
1
R2021
R2020
1
1
1
1
12
8GB
12
4GB/16GB
TP2006 TPAD14-OP-GP
1 2
0R0402-PAD
1 2
0R0402-PAD
2016/12/28
TP2012 TPAD14-OP-GP
TP2014 TPAD14-OP-GP
FFS_INT2 70
TP2016 TPAD14-OP-GP
TP2017 TPAD14-OP-GP
R2023
1 2
R2024
1 2
1 2
R2025 0R2J-2-GP
1 2
R2026 0R2J-2-GP
1 2
R2027 0R2J-2-GP
1 2
R2028 0R2J-2-GP
DY
2017/05/08
MEM_CONFIG2
2
IR_CAM_DET# 55
RTC_DET# 25
SENSOR_I2C_SDA 55,70
SENSOR_I2C_SCL 55,70
2017/03/15
0R0402-PAD
0R0402-PAD
R2029
10KR2J-3-GP
R2022
10KR2J-3-GP
+V1.8A+V1.8A+V1.8A
12
16GB
12
4GB/8GB
3D3V_S0
RN2007
ISH_I2C0_SCL
ISH_I2C0_SDA
I2C1_SDA
I2C1_SCL
(PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
to the same voltage rail as the device/end point.
GYRO_DRDY_ISH
GSEN_INT1 55
GSEN_INT2 55
GSEN2_INT1_C 70
GSEN2_INT2_C 70
GYRO_INT_C 70
GYRO_DRDY 55
3D3V_S5
12
2IN1
(PDG#543016) If the UART/GPIO functionality is also not used,
the signals can be left as no-connect.
R2001
10KR2F-2-GP
KB_DISABLE_CPU_R
SRN1KJ-7-GP
1
2 3
SRN2K2J-1-GP
2 3
1
RN2008
R2052
10KR2J-3-GP
R2051
10KR2J-3-GP
Vth(max)=1.1V
Q2001
6
D1
G2
4 3
S2
PJT138KA-GP
DY
1D8V_S0
12
DY
12
DY
2IN1
S1
G1
D2
4
4
2017/03/17
1
25
1
ISH_KB_DISABLE
NB_MODE# 24
075.00138.0A7C
3D3V_S5
R2050
Micron
Samsung
Hynix
B B
Micron
Samsung
Hynix
Micron
PCH strap pin:
No Reboot
GSPI0_MOSI /
A A
GPP_B18
0
1
01 01 MT40A1G16WBU-083E 16G
10 00
1 10
1 10
1
1
1
Sampled at rising edge of PCH_PWROK
0 = Disable “No Reboot” mode.
1 = Enable “No Reboot” mode (PCH will disable the TCO
Timer system reboot feature). This function is useful
when running ITP/XDP.
00
00
00
072.40116.0B0U
K4A8G165WB-BCRC
10
01
00
10
01
PCH Prim
3D3V_S5_PCH 3D3V_S0 3D3V_S0
12
R2007
DY
1KR2J-1-GP
H5AN8G6NAFR-UHC
MT40A512M16JY-083E
K4A4G165WE-BCRC
H5AN4G6NBJR-UHC*
MT40A256M16GE-083E
2IN1
TBD
TBD
072.40512.0B0U
072.44165.0B0U
TBD
072.40256.0A0U
12
R2005
10KR2J-3-GP
8G
8G
8G
4G
4G
4G
12
KBL-U
R2010
10KR2J-3-GP
MEM_CONFIG3 MEM_CONFIG4
+V1.8A +V1.8A
12
R2011
10KR2J-3-GP
10KR2J-3-GP
Hynix
12
R2012
Samsung/Micron
12
R2013
10KR2J-3-GP
Micron
12
R2014
10KR2J-3-GP
Samsung/Hynix
2016/11/07 modify
3D3V_S0
12
UMA Board /4GB VRAM
R2038
10KR2J-3-GP
MEM_CHA_EN
MEM_CHB_EN
R2031
10KR2J-3-GP
R2030
10KR2J-3-GP
R2033
10KR2J-3-GP
R2032
10KR2J-3-GP
+V1.8A
12
12
DY
+V1.8A
12
12
DY
3D3V_S0
12
UMA Board
R2035
10KR2J-3-GP
NB_MODE#
2IN1
CLAM
10KR2J-3-GP
1 2
R2002
10KR2J-3-GP
1 2
The signal has a weak internal pull-down.
<Core Design>
<Core Design>
NRB_BIT
12
R2019
DY
1KR2J-1-GP
5
4
BOARD_ID2
CLAM
12
R2008
10KR2J-3-GP
BOARD_ID1
KBL-R
12
R2009
10KR2J-3-GP
VRAM_ID2
12
R2037
10KR2J-3-GP
2GB VRAM
3
VRAM_ID1
4GB VRAM
2
12
R2034
10KR2J-3-GP
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(LPSS/ISH)
CPU_(LPSS/ISH)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(LPSS/ISH)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
20 106Thursday, June 29, 2017
20 106Thursday, June 29, 2017
20 106Thursday, June 29, 2017
A00
A00
A00
Page 21
5
4
3
2
1
SSID = PCH
For eSPI
D D
EC2101
12
+V3.3A_SIP
C C
C2120
SCD1U25V2KX-1-DL-GP
DY
12
R2101
0R0402-PAD
SC1U10V2KX-1DLGP
+VCCMPHYGTAON_1P0_LS_SIP
+VCCAMPHYPLL_1P0
1 2
+VCCMPHYGTAON_1P0_LS_SIP
+VCCMPHYGTAON_1P0_LS_SIP
+V1.00A_SIP
+VCCPRIM_CORE
+VCCDSW _1P0
+V1.00A_SIP
+VCCAPLL_1P0
+V1.00A_SIP
+VCCPDSW_3P3
+VCCPAZIO
+V3.3A_SIP
+V3.3A_SIP
+V1.00A_SIP
2.57A
CPU1O
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
SKYLAKE-U-GP
CPU POWER 4 OF 4
SKYLAKE_ULT
1.8V Only
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCRTCPRIM_3P3
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
071.SKYLA.000U
15 OF 20
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCATS_1P8
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
+V1.8A_SIP
+V3.3A_SIP
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+V1.8A_SIP
+V3.3A_SIP
+V1.00A_SIP
+V1.8A_SIP
+V3.3A_SIP
VCCRTCEXT
+V1.00A_SIP
+VCCCLK2
+V1.00A_SIP
+VCCCLK4
+VCCCLK5
+V1.00A_SIP
V0.85A_VID0
V0.85A_VID1
+VCCPRTC_3P3
1 2
C2112 SCD1U25V2KX-1-DL-GP
1
1
DELETE, 20160810 Nick
TP2101 TPAD14-OP-GP
TP2102 TPAD14-OP-GP
+VCCPRTC_3P3
1 2
Layout Note:
0.1uF:
C2117
C2118
SCD1U25V2KX-1-DL-GP
SC1U10V2KX-1DLGP
12
C2118 near AK19
1uF:
C2117 near Ak19
+VCCPRTC_3P3RTC_AUX_S5
1 2
R2106
0R0603-PAD
1 2
R2107
0R0603-PAD
1 2
R2108
0R0603-PAD
1 2
R2109
0R0603-PAD
1 2
R2110
0R0603-PAD
1 2
R2111
0R0603-PAD
+VCCAMPHYPLL_1P0+VCCMPHYGTAON_1P0_LS_SIP
+VCCAPLL_1P0+V1.00A_SIP
+VCCCLK2+V1.00A_SIP
+VCCCLK4+V1.00A_SIP
+VCCCLK5+V1.00A_SIP
+V3.3A_SIP
B B
C2105
12
SC1U10V2KX-1DLGP
12
+VCCAMPHYPLL_1P0
C2106
SC1U10V2KX-1DLGP
C2107
12
C2113
SC22U6D3V3MX-1-GP
12
C2109
SC1U10V2KX-1DLGP
12
Layout Note:
22uF:
C2113 near K15
SC1U10V2KX-1DLGP
C2110
SCD1U25V2KX-1-DL-GP
12
12
DY
A A
5
Layout Note:
1uF:
C2111
SCD1U25V2KX-1-DL-GP
C2105 near V19
C2106 near AK17
C2107 near AG15
C2109 near Y16
C2110 near T16
C2111 near AJ19
+VCCAPLL_1P0 +V1.00A_SIP
12
C2114
SC22U6D3V3MX-1-GP
Layout Note:
22uF:
C2113 near K15
DY
4
+V1.8A_SIP
12
C2108
SC1U10V2KX-1DLGP
DY
+VCCCLK2
C2116
SC1U10V2KX-1DLGP
12
+VCCDSW _1P0
C2103
+VCCCLK4
12
12
C2119
SC1U10V2KX-1DLGP
+VCCCLK5
SC22U6D3V3MX-1-GP
12
C2102
SC1U10V2KX-1DLGP
12
C2115
SC22U6D3V3MX-1-GP
12
+V1.00A_SIP+VCCPRIM_CORE
C2101
SC1U10V2KX-1DLGP
C2104
12
SC1U10V2KX-1DLGP
12
12
C2121
SC1U10V2KX-1DLGP
Layout Note:
1uF:
C2101 near AB19
C2104 near K17
C2116 near A10
C2121 near AL1
Layout Note:
1uF:
SC22U6D3V3MX-1-GP
3
C2116 near A10
22uF:
C2115 near K19
C2119 near N20
C2122 near L19
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(POWER1)
CPU_(POWER1)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CPU_(POWER1)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
21 106Thursday, June 29, 2017
21 106Thursday, June 29, 2017
21 106Thursday, June 29, 2017
A00
A00
A00
C2122
Page 22
5
4
3
2
1
SSID = PCH
D D
CPU1T
SKYLAKE_ULT
SPARE
AW69
AW68
AU56
AW48
XTAL24_OUT_U42
C C
C7
U12
U11
H11
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11
SKYLAKE-U-GP
20 OF 20
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
F6
E3
C11
B11
A11
D12
C12
F52
XTAL24_IN_U42
071.SKYLA.000U
XTAL24_IN_U42
R2203
1 2
0R0402-PAD-2-GP
2017/05/09
XTAL24_IN_U42_R
R2201
1MR2J-1-GP
12
U42
X2201
U42
INPUT/OUTPUT#1
NC#2
INPUT/OUTPUT#3
XTAL-24MHZ-135-GP
U42
1
2
3
082.30006.0041
C2201
12
SC15P50V2JN-DL-GP
2017/03/07
B B
XTAL24_OUT_U42
A A
5
4
R2204
1 2
0R0402-PAD-2-GP
XTAL24_OUT_U42_L
3
R2202
1 2
0R0402-PAD
U42
XTAL24_OUT_R_U42
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
C2202
12
SC15P50V2JN-DL-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU_(RSVD)
CPU_(RSVD)
CPU_(RSVD)
KyloRen 13"
KyloRen 13"
KyloRen 13"
A00
A00
A00
22 106Thursday, June 29, 2017
22 106Thursday, June 29, 2017
22 106Thursday, June 29, 2017
1
Page 23
SSID = PCH
5
4
3
2
1
CPU1Q
CPU1P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND 1 OF 3
SKYLAKE_ULT
D D
A5_TP
A67_TP
A70_TP
A67
A70
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
A5
TP2309TPAD14-OP-GP
TP2311TPAD14-OP-GP
TP2310TPAD14-OP-GP
C C
B B
1
1
1
16 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AV1_TP
TP2307TPAD14-OP-GP
TP2304TPAD14-OP-GP
TP2312TPAD14-OP-GP
TP2305TPAD14-OP-GP
TP2306TPAD14-OP-GP
1
1
1
1
1
AV71_TP
B71_TP
BA1_TP
BA2_TP
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKYLAKE-U-GP
SKYLAKE_ULT
17 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
BA71_TP
BB67_TP
BB70_TP
C1_TP
E71_TP
1
TP2303 TPAD14-OP-GP
1
TP2302 TPAD14-OP-GP
1
TP2301 TPAD14-OP-GP
1
TP2308 TPAD14-OP-GP
1
TP2313 TPAD14-OP-GP
CPU1R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKYLAKE-U-GP
GND 3 OF 3
SKYLAKE_ULT
G10
G22
G43
G45
G48
G5
G52
G55
G58
G6
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
F8
071.SKYLA.000U
18 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
071.SKYLA.000U
SKYLAKE-U-GP
071.SKYLA.000U
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CPU_(VSS)
CPU_(VSS)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_(VSS)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
23 106Thursday, June 29, 2017
23 106Thursday, June 29, 2017
23 106Thursday, June 29, 2017
A00
A00
A00
Page 24
SSID = KBC
5
3D3V_S5 3D3V_S5_KBC 3D3V_S5_KBC
1D0V_S5
1 2
R2402
0R0402-PAD
Just for Starload placement
2015/09/23 modify
8
KSO3
7
KSO1
6
KSO2
KSO0
8
KSO5
7
KSO4
6
KSO7
KSO6
8
KSO11
7
KSO10
6
KSO12
KSO8
8
KSO15
7
KSO13
6
KSO14
KSO16
2016/12/23
12
R2465
10KR2F-2-GP
DY
FPR_SCAN#
10KR2F-2-GP
Layout Note:
Need very close to EC
3D3V_S5_KBC
10KR2F-2-GP
2017/03/14
D D
3D3V_S5_KBC
RN2412
1
2
3
4 5
SRN100KJ-5-G P
RN2409
1
2
3
4 5
SRN100KJ-5-G P
RN2410
1
2
3
4 5
SRN100KJ-5-G P
RN2411
1
2
3
4 5
SRN100KJ-5-G P
C C
2016/12/13
3D3V_S0 3D 3V_S5
12
R2458
12
R2460
DY
2016/12/22
RUNPWROK assert,
delay 10ms; PCH_PWROK assert.
RN2403
1
2
3
4 5
SRN10KJ-6-G P
RN2404
1
2
3
4 5
SRN10KJ-6-G P
SIO_SLP_S0#17,40,91
For eSPI
FPR_SCAN#92
12
VREF_CPU
8
7
6
8
7
6
PRIM_PWRG D40,54
PCH_RSMRS T#17,99
C2406
SCD1U25V2KX-1-DL-GP
KSI2
KSI1
KSI3
KSI0
KSI7
KSI6
KSI4
KSI5
2016/11/4
2017/01/24
12
12
C2421
C2416
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
1 2
0R0402-PAD
2016/12/28
CLKRUN#18
USB_POW ERSHARE_VB US_EN34
SUS_CLK18
2016/12/22
12
12
C2412
C2411
SCD1U25V2KX-1-DL-GP
Just for Starload placement
2015/09/23 modify
RTCRST_O N18
AC_DIS43
TP_WAKE_K BC#4,65
RUNPW ROK17,40
RESET_OUT #17,26
R2461 0R2J-2- GP
R2481
CCG4_I2C_INT#37
C2420
SCD1U25V2KX-1-DL-GP
ESPI_CS#18,68
MASK_SATA_LED#64
ESPI_CLK18,68
ESPI_ALERT#18
ESPI_RESET#18,68
LID_CL_SIO#70
SYS_PWROK17,99
PBAT_PRES#43,44
2016/12/22
12
B B
For eSPI
GPIO123 (BSS_STRAP)GPIO102 (CR_STRAP)
3D3V_S5_KBC
Already pull low
1 2
DY
1 2
R2452
100KR2J-1-GP
KSO9
R2453
100KR2J-1-GP
TP2402
on CPU side
PCH_RSMRS T#
1
TPAD14-OP-G P
ESPI_ALERT#
1 2
R2464 10KR2J -3-GP
2017/05/08
1 2
R2446
0R0603-PAD
12
12
12
C2414
C2410
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
KSO[0..16]65
KSI[0..7]65
CLK_TP_SIO65
DAT_TP_SIO65
SIO_PWRBTN #17,99
ESPI_IO[3..0]18,68
1 2
R2439 10KR2F- 2-GP
DY
2017/03/14
2017/03/14
1 2
DY
X2401
41
2 3
XTAL-32D768KH Z-68-GP
82.30001.G01
C2425
SC6P50V2CN- 1-NL-GP
Microchip: Use CL=9p Xtal，C = 10p
PANEL_BKEN55
1D8V_S5_KBC
DY
2017/03/21
C2413
12
EC2403
EC2402
DY
DY
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
C2428
SCD1U25V2KX-1-DL-GP
12
2
KSO0
14
KSO1
15
KSO2
16
KSO3
37
KSO4
38
KSO5
39
KSO6
50
KSO7
46
KSO8
68
KSO9
72
KSO10
74
KSO11
75
KSO12
76
KSO13
77
KSO14
86
KSO15
92
KSO16
CAP_LED#
93
98
KSI0
99
KSI1
6
KSI2
7
KSI3
104
KSI4
105
KSI5
107
KSI6
108
KSI7
78
79
52
EC_SLP_S0IX#
88
ESPI_IO0
59
ESPI_IO1
60
ESPI_IO2 ICSP_DAT
61
ESPI_IO3
62
58
56
57
CLKRUN#_EC
63
55
10
TP_EN#
49
53
66
32
28
29
30
31
27
BKLT_IN_EC
67
69
71
42
33
3
USB_EN#
13
48
73
MEC_XTAL2
125
MEC_XTAL1_R
123
C2424
SC6P50V2CN- 1-NL-GP
R2498 0R2J-2- GP
12
12
12
2016/12/29
83.R2004.G8F
83.R2004.G8F
4
If don't need RTC alarm wake up,
can change to 3D3V_AUX_S5
RTC_AUX_S5
R2472
0R0402-PAD
1 2
+RTC_CELL_V BAT
PANEL_BKEN_EC
2017/03/07
L_BKLT_EN_L
VSS_VBAT
84
124
1 2
0R0402-PAD
DY
R2440
122
R2445
1 2
0R2J-2-GP
1 2
KBC24
GPIO027/KSO00/PVT_IO1
GPIO015/KSO01/PVT_CS#
GPIO016/KSO02/PVT_SCLK
GPIO017/KSO03/PVT_IO0
GPIO045/BCM_INT1#/KSO04
GPIO046/BCM_DAT1/KSO05
GPIO047/BCM_CLK1/KSO06
GPIO025/KSO07/PVT_IO2
GPIO055/PWM2/KSO08/PVT_IO3
GPIO102/KSO09/CR_STRAP
GPIO106/KSO10
GPIO110/KSO11
GPIO111/KSO12
GPIO112/PS2_CLK1A/KSO13
GPIO113/PS2_DAT1A/KSO14
GPIO125/KSO15
GPIO132/KSO16
GPIO140/KSO17
GPIO143/KSI0/DTR#
GPIO144/KSI1/DCD#
GPIO005/SMB00_DATA/SMB00_DATA18/KSI2
GPIO006/SMB00_CLK/SMB00_CLK18/KSI3
GPIO147/KSI4/DSR#
GPIO150/KSI5/RI#
GPIO151/KSI6/RTS#
GPIO152/KSI7/CTS#
GPIO114/PS2_CLK0
GPIO115/PS2_DAT0
GPIO026/PS2_CLK1B
GPIO127/PS2_DAT1B
GPIO040/LAD0/ESPI_IO0
GPIO041/LAD1/ESPI_IO1
GPIO042/LAD2/ESPI_IO2
GPIO043/LAD3/ESPI_IO3
GPIO044/LFRAME#/ESPI_CS#
GPIO064/LRESET#
GPIO034/PCI_CLK/ESPI_CLK
GPIO067/CLKRUN#
GPIO063/SER_IRQ/ESPI_ALERT#
GPIO011/SMI#/EMI_INT#
GPIO060/KBRST
GPIO061/LPCPD#/ESPI_RESET#
GPIO100/EC_SCI#
GPIO126/SHD_SCLK
GPIO133/SHD_IO0
GPIO134/SHD_IO1
GPIO135/SHD_IO2
GPIO136/SHD_IO3
GPIO123/SHD_CS#
GPIO101/SPI_CLK
GPIO103/SPI_IO0
GPIO105/SPI_IO1
GPIO052/SPI_IO2
GPIO062/SPI_IO3
GPIO001/SPI_CS#/32KHZ_OUT
RESET_IN#/GPIO014
GPIO057/VCC_PWRGD
GPIO107/RESET_OUT#
XTAL2
XTAL1
MEC1416-NU- D0-GP
1 2
DY
D2401
K A
RB751V-40H-G P
DY
D2404
K A
RB751V-40H-G P
R2499
1 2
DY
2KR2F-L1-GP
BKLT_IN_EC
2017/03/14
For eSPI
+V1.8A
43
103
VTR5VTR19VTR
VTR65VTR82VTR
VBAT
GPIO007/SMB01_DATA/SMB01_DATA18
GPIO010/SMB01_CLK/SMB01_CLK18
GPIO012/SMB02_DATA/SMB02_DATA18
GPIO013/SMB02_CLK/SMB02_CLK18
GPIO130/SMB03_DATA/SMB03_DATA18
GPIO131/SMB03_CLK/SMB03_CLK18
GPIO141/SMB04_DATA/SMB04_DATA18
GPIO142/SMB04_CLK/SMB04_CLK18
VSS17VSS51AVSS
VSS
VSS64VSS
100
GPIO050/TACH0
GPIO051/TACH1
GPIO053/PWM0
GPIO054/PWM1
GPIO056/PWM3
GPIO030/BCM_INT0#/PWM4
GPIO031/BCM_DAT0/PWM5
GPIO032/BCM_CLK0/PWM6
GPIO002/PWM7
GPIO157/LED0/TST_CLK_OUT
GPIO156/LED1
GPIO104/LED2
GPIO116/TFDP_DATA/UART_RX
GPIO117/TFDP_CLK/UART_TX
GPIO035/SB-TSI_CLK
GPIO033/PECI_DAT/SB_TSI_DAT
GPIO145/ICSP_CLOCK
GPIO146/ICSP_DATA
BGPO/GPIO004
SYSPWR_PRES/GPIO003
VCI_OUT/GPIO036
VCI_IN1#/GPIO162
VCI_IN0#/GPIO163
VCI_OVRD_IN/GPIO164
GPIO160/DAC_0
GPIO161/DAC_1
GPIO124/CMP_VOUT0
GPIO020/CMP_VIN0
GPIO165/CMP_VREF0
GPIO120/CMP_VOUT1
GPIO021/CMP_VIN1
GPIO166/CMP_VREF1/UART_CLK
GPIO024/ADC7
GPIO023/ADC6/A20M
GPIO022/ADC5
GPIO153/ADC4
GPIO154/ADC3
GPIO155/ADC2
GPIO122/ADC1
GPIO121/ADC0
VR_CAP
18
112
EC_AGND
VR_CAP
C2418
SC1U10V2KX-1DLGP
12
Layout Note:
EC_AGND
Connect GND and AGND planes via either
0R resistor or connect directly.
2016/12/28 modify follow 15"
eDP backlight
Control from EC
R2427
0R0402-PAD
2017/05/08
1D8V_S5_KBC
R2462
12
0R0402-PAD
12
C2423
SCD1U25V2KX-1-DL-GP
54
VTR_33_18
8
9
11
12
89
91
96
97
40
41
44
45
47
34
35
36
4
1
106
70
80
81
90
94
95
VREF_CPU
101
102
87
ICSP_MCLR
119
120
121
126
127
128
23
24
22
DAC_VREF
85
20
25
83
21
26
118
117
116
109
110
111
113
114
115
ADC_VREF
L_BKLT_EN 8,24
eDP backlight
Control from PCH
L_BKLT_EN 8,24
12
R2455
100KR2J-1-GP
GPU_THM_SMBD AT
GPU_THM_SMBC LK
TYPEC_SMBDA
TYPEC_SMBCLK
FAN1_TACH
SIO_SLP_S4#_EC
SIO_SLP_S3#_EC
PCIE_WAKE#
BAT2_LED#
BAT1_LED#
H_PECI
VREF_CPU
ICSP_CLK
ICSP_CLR
SYSPWR_PR ES
ALWON
POWER_S W_IN#
HW_ACA VIN_NB
CMP_VOUT0
CMP_VIN0
VCREF0
PROCHOT
CMP_VIN1
LCD_TST
PANEL_BKEN_EC
MODEL_ID
I_ADP
BOARD_ID
I_BATT
3D3V_S5_KBC
12
C2422
EC_AGND
SCD1U25V2KX-1-DL-GP
3
2016/11/08modify
VOLTAGEPULL-HIGH RESISTORPULL-LOW RESISTORBOARD_ID VERSION A/D
3.0V
2.801V
2.598V
2.402V
2.201V
2.001V
1.808V
1.594V100.0K
1.299V
1.100V
Change symbol part number, because origin symbol is DELL OBS part
D2403
RB751V-40H-G P
KA
FAN_TACH 1 26
83.R2004.G8F
+RTC_CELL_V BAT
R2497
100KR2J-1-GP
EC_VCIN1#EC_VCIN1#
USB_EN#
HW_ACA VIN_NB
I_ADP
12
EC_AGND
CMP_VIN1
12
DY
C2436
1 2
R2401 0R2J-2- GP
R2421
330R2J-3-GP
C2435
SC2200P50V2KX-2D LGP
SC2200P50V2KX-2GP
20150116 2040Change symbol part number, because origin symbol is DELL OBS part
DY
R2475
0R0402-PAD
12
12
12
12
DY
PR2455
150KR2F-L-GP
12
DY
R2457
115KR2F-GP
EC_AGNDEC _AGND
1 2
Vref = 1.117
temp around 85
12
R2448
10KR2F-2-GP
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
D2402
RB751V-40H-G P
K A
R2430
10KR2J-3-GP
3D3V_AUX_S5
DY
A00
BOARD_ID
C2408
TBD,20160518 TBD,20160518
CPU/ Thermal
For CCG4/I2C/USB Mux
1 2
R2409 0R2J-2- GP
DY
1 2
R2479 0R2J-2- GP
DY
R2406
1 2
0R0402-PAD
2016/12/28
1 2
R2437
SC100P50V2JN-3DLGP
43R2J-GP
C2405
12
DY
Need very close to EC, PDG: <0.5 inches.
SCD1U25V2KX- 1-DL-GP
C2429
1 2
R2470 0R0402-P AD
12
12
R2494 0R2J- 2-GP
DY
Reserve resistor, 20141118
PCB_REV
12
R2443
82K5R2F-GP
2017/05/02
12
SCD1U25V2KX-1-DL-GP
R2444
12
100KR2F-L1-GP
EC_AGND
PBAT_CHG_SM BDAT 43,44
PBAT_CHG_SM BCLK 43,44
AUX_EN_W OWL 17,61
KB_LED_PW M 65
BEEP 27
FAN1_PWM 26
SIO_SLP_S3# 17,4 0,51
PS_ID 43
PCIE_WAKE#_C PU 17
BREATH_LED # 66
ME_FWP 19
HOST_DEBU G_TX 68
PTP_DIS# 65
PECI 4
NB_MUTE# 27
ALWON 40
HW_ACA V_IN 44
3D3V_S5_KBC
CMP_VOUT0 26
CMP_VIN0_R 24,26
LCD_TST 55
USB_PWR _SHR_EN_L# 34
SIO_EXT_WAKE # 20
CMP_VIN0_R 24,26
LCD_VCC_T EST_EN 55
I_BATT AD_IA
12
C2441
SC2200P50V2KX-2D LGP
DY
EC_AGND
KyloRen_X00
KyloRen_X01
KyloRen_X02
KyloRen_X03
KyloRen_X04
KyloRen_X05
KyloRen_A00
KyloRen_A01
KyloRen_A02
KyloRen_A03
BATTER /CHARGER
NB_MODE# 20
LID_CL_SIO_TAB# 70
3D3V_S5_KBC
R2424
20KR2F-L-GP
12
C2409
SCD01U50V2KX-1DLGP
R2423
12
DY
330R2J-3-GP
Layout Note:
Need very close to EC
Need very close to EC
LID_CL_SIO#
83.R2004.G8F
10.0K
17.8K
27.0K
37.4K
49.9K
64.9K
82.5K
107K
154K
200KK
3D3V_S0
1 2
2017/03/09
12
R2463
1KR2J-1-GP
12
R2454
100KR2J-1-GP
TOUCH_R EPORT_SW 55
2
MODEL_ID
Nick 2016/05/16 modify
3D3V_S5
12
R2434
100KR2J-1-GP
USB_EN# 35,66
AC_IN#_G 43
DC_IN_OK 43
2017/05/10For Typec charge detect modify
AD_IA 44
3D3V_S5
12
MODEL_ID
C2407
SCD1U25V2KX-1-DL-GP
12
12
EC_AGND
CHG_AMBER_L ED#64
Q2412 and Q2413 merge
24014/12/23 modify
GPU_THM_SMBD AT
GPU_THM_SMBC LK
CCG4_I2C_SDA37
CCG4_I2C_SCL37
MODEL_ID_DET(GPIO07) PULL-HIGH RESISTORPULL-LOW RESISTOR
TBD
KyloRen 13" UMA Clamshell
KyloRen 13" UMA 2in1
R2442
27KR2F-L-GP
R2441
100KR2F-L1-GP
TBD
KyloRen 15" UMA Clamshell
KyloRen 15" UMA 2in1
TBD
KyloRen 15" DIS Clamshell
KyloRen 15" DIS 2in1
2016/11/07modify
2016/12/06 follow 15"
1 2
R2447
R2459
R2489
100KR2J-1-GP
1
2
3 4
S
G
Q2414
1 2
2016/12/28
1 2
Q2416
6
5
2N7002KDW -GP
84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
D
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
0R0402-PAD
0R0402-PAD
3 4
2
1
BAT2_LED#
3D3V_S5 3D3V_S5
3D3V_S0
CAP_LED#
3D3V_S0
84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
LID_CL_SIO_TAB#
2N7002K-2-GP
84.2N702.J31
SML1_SMBDATA
SML1_SMBCLK
3D3V_S5_KBC
Q2605
5
TypeC
6
2N7002KDW -GP
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K
100.0K 154K()
100.0K 200K()
17.8K()
27.0K()
37.4K() 2.402V
49.9K()
82.5K()
107K()
3D3V_S5
R2496
100KR2J-1-GP
1 2
BATT_WH ITE_LED# 64
BAT1_LED#
Reserve by NON DS3 function 20150413
1
LID_CL_SIO#
TP_EN#65
CAP_LED#_R 65
SML1_SMBDATA 18,26
SML1_SMBCLK 18,26
RN2604
SRN2K2J-1-G P
VOLTAGE
3.0V10.0K(64.10025.6DL)
2.801V
2.598V
2.201V
2.001V64.9K()
1.808V
1.594V
1.299V
1.100V
3D3V_S5_KBC
1
23
TypeC
4
RN2405
1
2
3
4 5
SRN100KJ-5-G P
3D3V_S5
8
7
6
TYPEC_SMBDA 38
TYPEC_SMBCLK 38
A A
R2418
0R2J-2-GP
1 2
R2417
100KR2J-1-GP
PROCHOT
12
DY
DY
Q2408
G
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
D
5
2015/09/22 modify
12
ED2403
DY
AZ5725-01FDR7G-GP
H_PROCHO T# 4,44,46
2017/03/17
PBAT_CHG_SM BCLK
PBAT_CHG_SM BDAT
USB_PWR _SHR_EN_L#
PBAT_PRES#
RN2402
4
SRN4K7J-8-G P
1 2
R2473 10KR2J-3- GP
1 2
R2415 10KR2J-3- GP
Just for Starload placement
2015/09/23 modify
3D3V_S5_KBC
23
1
3D3V_S5_KBC
4
3D3V_S5_KBC
3D3V_S5_KBC
DY
R2414
1 2
R2480
100KR2J-1-GP
ICSP_CLK
ICSP_DAT
1 2
HOST_DEBU G_TX
4K7R2J-2-GP
ICSP_CLR
3D3V_S5_KBC
DB3
7
1
2
3
LPC
4
5
6
8
20.K0691.006
ACES-CON 6-58-GP
Power Switch Logic(PSL)
KBC_PWR BTN#66
3
R2432
1KR2J-1-GP
12
12
C2427
SC2D2U10V3KX- 1DLGP-U
2017/05/15
2016/12/20 modify
+RTC_CELL_V BAT
R2451
100KR2J-1-GP
1 2
POWER_S W_IN#
12
C2426
SC1U10V2KX-1D LGP
<Core Desig n>
<Core Desig n>
DY
2
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
KBC Nuvoton NPCE285PA0DX
KBC Nuvoton NPCE285PA0DX
KBC Nuvoton NPCE285PA0DX
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
A1
A1
A1
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Taipei Hsie n 221, Taiwan, R.O. C.
24 106
24 106
24 106
A00
A00
A00
Page 25
5
SSID = SPI Flash
4
3D3V_S5_PCH
3
2
1
12
R2515
SPI Flash ROM(8M) for PCH
3D3V_SPIVCC13D3V_S5_PCH
0R0402-PAD
72.12873.001
72.25128.0E1
D D
SC10U10V5KX-2DLGP
R2501
4K7R2J-2-GP
1 2
SPI25
SPI_CS_ROM_N018
SPI_WP_ROM_R
12
SC4D7P50V2BN-GP
R2506
1 2
C C
SPI_SO_ROM18,91
SPI_WP_ROM18,99
10R2J-2-GP
R2507
10R2J-2-GP
1 2
SPI_SO_ROM_R
SPI_WP_ROM_R
EC2502
DY
1
CS#
2
SO/SIO1
3
SIO2
4
GND
MX25L12873FM2I-10G-GP
SI/SIO0
72.12873.001
2nd = 72.25128.0E1
VCC
SIO3
SCLK
8
7
6
5
SPI_HOLD_ROM_RSPI_SO_ROM_R
SPI_CLK_ROM_R
SPI_SI_ROM_R
3D3V_SPIVCC1
12
DY
EC2501
SC4D7P50V2BN-GP
12
C2501
DY
R2503 10R2F-L-GP
12
DY
12
C2502
SCD1U16V2KX-3DLGP
DY
1 2
SPI_CLK_ROM_R
SPI_SI_ROM_R
EC2503
SC10P50V2JN-4GP
Change to Dummy 20150402
SPI_HOLD_ROM 18
R2508
R2509
1 2
1 2
10R2J-2-GP
10R2J-2-GP
2016/12/28
SPI_CLK_ROM 18,91
SPI_SI_ROM 18,91
QUAD/DUAL fast read DUAL fast readSource
O
O
O
O
O O
SFDP
O
O
O
2016/12/28
Main Func = RTC
Delivery Voltage 3.19V
3D3V_AUX_S5
12
R2505
1K6R2F-GP
B B
3D3V_RTC_SYS
12
R2517
47KR2F-GP
D2501
1
2
BAS40C-2-GP
75.00040.07D
2nd = 75.00040.C7D
3rd = 75.00040.A7D
A A
12
R2504
10MR2J-L-GP
5
4
Q2505
G
D
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
RTC_AUX_S5+RTC_VCC
3
12
C2503
SCD47U25V3KX-1-DL-GP
<Core Design>
<Core Design>
<Core Design>
RTC_DET# 20
3
Title
Title
Title
Flash/RTC
Flash/RTC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Flash/RTC
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
25 106
25 106
25 106
1
Page 26
5
4
3
2
1
SSID = Thermal Sensor
3D3V_S0 3D3V_S0
1
23
RN2602
SRN2K2J-1-GP
3D3V_S0
SML1_SMBDATA18,24
12
12
D D
DY
C2601
C2602
SCD1U25V2KX-1-DL-GP
84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
7718
SC10U6D3V3MX-GP
2016/12/21 change PN
84.T3904.K11
7718
C
Q2603
E
B
NCT7718_DXP
12
C2606
SC470P50V3JN-2GP
DY
NCT7718_DXN
7718
12
C2607
SC2200P50V2KX-2DLGP
2.System Sensor, Put on palm rest
MMBT3904-5-GP-U
Layout Note:
C2607 close THM2601
Layout Note:
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.
3D3V_S0
C C
1 2
R2603 7K5R2F-1-GP
7718
1 2
R2604 7K5R2F-1-GP
7718
R2601
0R2J-2-GP
ALERT#
T_CRIT#
12
DY
T_CRIT#
RESET_OUT#17,24
SML1_SMBCLK18,24
THM261
1
VDD
2
D+
3
DT_CRIT#4GND
NCT7718W-GP
74.07718.0B9
PLT_RST#17,63,66,91,99
THERM_SYS_SHDN#
SCL
7718
SDA
ALERT#
R2617
1 2
0R0402-PAD
2016/12/28
8
7
6
5
R2616
0R2J-2-GP
1 2
6
5
ALERT#
DY
RESET_OUT#_G
2N7002KDW-GP
1
7718
2
34
Q2601
7718
4
DY
Q2602
G
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
THM_SML1_DATA
THM_SML1_CLK
THM_SML1_CLK
THM_SML1_DATA
12
12
DY
C2608
C2609
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
D
12
DY
C2610
SCD1U16V2KX-3GP
RESET_OUT#_G
12
DY
DY
CMP_VOUT0
1 2
R2615 0R2J-2-GP
KBC T8
C2614
SCD1U16V2KX-3GP
PURE_HW _SHUTDOWN# 40
DVT1 0210, for T8 function
3D3V_S5
1 2
R2607 10KR2J-3-GP
1 2
R26020R0402-PAD
2016/12/28
FAN_TACH124
FAN1_PW M24
Close to KBC
2017/05/08
5V_S0
EC2602
SC10P50V2JN-4GP
12
DY
CMP_VOUT0 24
1 2
R2612
0R0402-PAD
EC2601
SC10P50V2JN-4GP
12
DY
VD_IN1 for system thermal sensorClose to Thermal sensor
3D3V_S5_KBC3D3V_S0
DY
12
R2609
10R2F-L-GP
12
R2608
27KR2F-L-GP
DVT1 0210, for T8 function
PWM FAN1
FAN_VCC_1
D2601
KA
C2605
SCD1U25V2KX-1-DL-GP
C2604
12
SC4D7U6D3V3KX-DLGP
12
1 2
R26130R0402-PAD
1 2
R26140R0402-PAD
83.R5003.H8H
DY
AFTP2604
12
DY
RB551V30-GP
FAN_VCC_1
FAN_TACH1_C
FAN_PW M1_C
FAN_TACH1_C
FAN_PW M1_C
FAN_VCC_1
Layout Note:
Signal Routing Guideline:
Trace width = 15mil
C2603
SC2200P50V2KX-2GP
FAN1
5
1
2
3
4
6
1
FCN-CON4-1-GP
020.F000G.0004
2017/03/15
1
AFTP2601
1
AFTP2602
1
AFTP2603
12
R2610
NTC-100K-8-GP
B B
A A
12
C2612
SCD1U25V2KX-1-DL-GP
VD_IN1_C
12
C2613
SC100P50V2JN-3DLGP
CMP_VIN0_R 24
1 2
R2611
0R0402-PAD
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
THERMAL NCT7718W/Fan
THERMAL NCT7718W/Fan
THERMAL NCT7718W/Fan
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
26 106
26 106
26 106
A00
A00
A00
Page 27
SSID = Audio
5
4
3
2
1
+3V_1D8V_AVDD
RN1812
HDA_CODEC_BITCLK19
HDA_CODEC_SDOUT19
HDA_CODEC_SYNC19
3D3V_S0
4
1
2 3
HDA_SDIN019
2016/11/2modify
3D3V_AUX_S5
RTC_AUX_S5
12
R2728
1 2
R2754
1 2
1 2
R2727 0R0402-PAD
1 2
R2740 0R0402-PAD
1 2
R2730 0R0402-PAD
1 2
R2746 0R2J-2-GP
+3V_1D8V_AVDD_IO
C2722
SCD1U25V2KX-1-DL-GP
0R2J-2-GP
DY
0R2J-2-GP
DY
+5V_AVDD
CPVDD
+5V_PVDD
+5V_PVDD
AUX_MODE
HDA_CODEC_SYNC
CODEC_BITCLK_R
CODEC_SDOUT_R
HDA_CODEC_SDIN0
DVSS
D D
1D8V_S0
2017/05/08
3D3V_S0
1 2
0R0603-PAD
R2748 0R3J-0-U-GP
R2749
1 2
DY
+3V_1D8V_AVDD
C2729
1 2
SRN2K2J-1-GP
Close pin6 pin7
SPK_I2C_DATA29
C2743
12
SPK_I2C_CLK29
2017/03/02
Layout Note:
Place close to Pin 1
AUD_SENSE29
12
R2743
10KR2J-3-GP
NB_MUTE#24
SPKR19
BEEP24
0R0402-PAD
200KR2F-L-GP
R2738
1 2
1 2
R2721
R2737
1 2
2016/12/28
2 3
1
SRN1KJ-7-GP
R2741
RN2702
12
0R0402-PAD
0R0402-PAD
EAPD#
4
AUD_SENSE_A
Audio_47
DMIC_DATA_R
DMIC_CLK_R
HDA_SPKR_R
KBC_BEEP_R
1D8V_S0
3D3V_S0
2017/03/02
R2750 0R3J-0-U-GP
R2751
1 2
0R0603-PAD
1 2
DY
SCD1U25V2KX-1-DL-GP
+3V_1D8V_AVDD_IO
C2744
12
SC10U6D3V3MX-DL-GP
C2745
12
+3V_1D8V_AVDD
DMIC_DATA55
DMIC_CLK55
SC10P50V2JN-4DLGP
R2744
C2738
DY
1 2
12
100KR2J-1-GP
+3V_1D8V_AVDD
Close pin5
C C
2.5A
5V_S0 +5V_PVDD
R2707
1 2
0R0805-PAD
R2712
1 2
0R0805-PAD
SCD1U25V2KX-1-DL-GP
+3V_1D8V_AVDD
C2742
C2732
12
12
C2714
C2733
12
12
R2742
1 2
100KR2J-1-GP
SC10U6D3V3MX-DL-GP
AUD_SENSE_A
12
C2746
DY
2017/03/02
SC10U6D3V3MX-DL-GP
Layout Note:
Close pin41
SC10U6D3V3MX-DL-GP
SCD1U25V2KX-1-DL-GP
Layout Note:
Close pin46
SCD1U25V2KX-1-DL-GP
SCD1U16V2KX-3DLGP
2nd = 83.R2003.W81
3rd = 75.00054.A7D
4th = 83.R2003.V81
HDA27
3
DVDD
18
DVDD-IO
40
AVDD1
20
CPVDD/AVDD2
41
PVDD1
46
PVDD2
33
5VSTB/AUX_MODE
6
I2C-DATA
7
I2C-CLK
15
AUDIOLINK_SYNC
14
AUDIOLINK_BCLK
17
AUDIOLINK_SDATA-OUT
16
AUDIOLINK_SDATA-IN
13
DC-DET/EAPD
11
I2S-MCLK
10
I2S-BCLK
12
I2S-LRCK
8
I2S-IN
9
I2S-OUT
48
HP/LINE1-JD(JD1)
47
I2S-IN/I2S-OUT-JD(JD2)
4
GPIO0/DMIC-DATA12
5
GPIO1/DMIC-CLK
1
DMIC-CLK-IN/I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34
2
PDB
ALC3254-CG-GP
D2702
2
1
BAT54C-7-F-3-GP
75.00054.E7D
AUD_PC_BEEP_C
3
12
C2726
1 2
R2745
2K2R2J-2-GP
MIC2-L(PORT-F-L)/RING2
MIC2-R(PORT-F-R)/SLEEVE
LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)
MIC2-VREFO-L
MIC2-VREFO-R
AUD_PC_BEEP_R
SCD1U25V2KX-1-DL-GP
PCBEEP
SPK-OUT-L+
SPK-OUT-L-
SPK-OUT-R+
SPK-OUT-R-
VREF
LDO1-CAP
LDO2-CAP
LDO3-CAP
MIC2-CAP
CPVEE
CBP
CBN
AVSS1
AVSS2
GND
34
30
31
36
35
42
43
45
44
27
26
38
39
21
19
28
29
32
25
23
24
37
22
49
AUD_SPK_L+
AUD_SPK_LAUD_SPK_R+
AUD_SPK_R-
AUD_VREF
LDO1_CAP
LDO2_CAP
LDO3_CAP
MIC_CAP
CPVEE
CBP
CBN
C2734 SC10U6D3V3MX-DL-GP
C2736 SC10U6D3V3MX-DL-GP
2016/11/3
C2721
SCD1U25V2KX-1-DL-GP
2016/12/28
R2729
1 2
0R0402-PAD
AUD_SPK_L+ 29
AUD_SPK_L- 29
AUD_SPK_R+ 29
AUD_SPK_R- 29
AUD_HP1_JACK_L 29
AUD_HP1_JACK_R 29
12
C2737 SC2D2U10V3KX-1DLGP-U
12
1 2
MIC2_VREFO_L 29
MIC2_VREFO_R 29
1 2
C2735 SC10U6D3V3MX-DL-GP
C2741
1 2
C2739
1 2
12
12
C2727
Layout Note:
Place close to Pin 40
AUD_AGND
SC10U6D3V3MX-DL-GP
RING2 29
SLEEVE 29
LINE1_L 29
LINE1_R 29
SC1U50V3KX-1-GP
SC1U50V3KX-1-GP
moat
2017/05/08
R2705
1 2
0R0603-PAD
AUD_PC_BEEP_RAUD_PC_BEEP
Layout Note:
Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
5V_S0+5V_AVDD
Width>40mil, to improve Headpohone Crosstalk noise
Change it to sharp will be better.
Add 2 vias (>0.5A) when trace layer change.
12
C2731
SC10U6D3V3MX-DL-GP
12
R2747100KR2J-1-GP
AUD_AGND
moat
2017/05/08
1D8V_S0
R2724
1 2
B B
A A
0R0603-PAD
C2740
1 2
AUD_AGND
SCD1U25V2KX-1-DL-GP
CPVDD
12
AUD_AGND
C2730
SC10U6D3V3MX-DL-GP
Close pin 20
EC2711
1 2
EC2710
1 2
1 2
EC2713 SCD1U25V2KX-1-DL-GP
DY
EC2709
1 2
1 2
EC2712 SCD1U25V2KX-1-DL-GP
DY
DY
AUD_AGND
AUD_AGND
1 2
EC2714 SCD1U25V2KX-1-DL-GP
R2739
1 2
0R0805-PAD
Layout Note:
R2739 should place nearby codec IC.
2017/05/04
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Audio Codec ALC3254
Audio Codec ALC3254
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Audio Codec ALC3254
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
27 106Thursday, June 29, 2017
27 106Thursday, June 29, 2017
27 106Thursday, June 29, 2017
A00
A00
A00
Page 28
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
(Reserved)
(Reserved)
(Reserved)
28 106Thursday, June 29, 2017
28 106Thursday, June 29, 2017
28 106Thursday, June 29, 2017
1
A00
A00
A00
Page 29
5
SSID = Audio
4
3
2
1
Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power
(
EL2902 BLM15PD121SN1D-GP
EL2901 BLM15PD121SN1D-GP
EL2904 BLM15PD121SN1D-GP
EL2903 BLM15PD121SN1D-GP
(
(
(
(
AUD_SPK_L-_C
AUD_SPK_L+_C
AUD_SPK_R-_C
AUD_SPK_R+_C
AUD_HP1_JACK_L1
AUD_HP1_JACK_R1
SC680P50V2KX-2DLGP
EC2908
C2907
C2908
AUD_SPK_L+27
AUD_SPK_L-27
AUD_SPK_R+27
AUD_SPK_R-27
20160812 EMI
1 2
1 2
LINE1-L_C
SC10U6D3V3MX-DL-GP
LINE1-L_R
SC10U6D3V3MX-DL-GP
12
EC2901
SC1KP50V2KX-1DLGP
RN2901
1
2 3
SRN2K2J-1-GP
0R0402-PAD
0R0402-PAD
2017/03/02
12
EC2902
SC1KP50V2KX-1DLGP
4
R29070R0603-PAD
1 2
R2922
1 2
R29090R0603-PAD
1 2
R2921
1 2
12
EC2903
SC1KP50V2KX-1DLGP
12
EC2904
SC1KP50V2KX-1DLGP
D D
C C
MIC2_VREFO_R27
MIC2_VREFO_L27
AUD_HP1_JACK_L27
AUD_HP1_JACK_R27
RING227
LINE1_L27
LINE1_R27
SLEEVE27
12
(
at high frequencies
Resistance element becomes dominant
12
(
12
(
at high frequencies
Resistance element becomes dominant
12
at high frequencies
Resistance element becomes dominant
at high frequencies
Resistance element becomes dominant
SPK_ID20
2016/11/02 modify
3D3V_S0
1
1
1
1
AFTP2901
AFTP2902
AFTP2903
AFTP2904
Universal Jack (Moved to I/O Board)
SC680P50V2KX-2DLGP
12
SC680P50V2KX-2DLGP
EC2907
EC2906
12
12
SC680P50V2KX-2DLGP
EC2905
12
AUD_SPK_L+_C
AUD_SPK_L-_C
AUD_SPK_R+_C
AUD_SPK_R-_C
R2915
1 2
SPK_DET
0R2J-2-GP
R2914
1 2
EEPROM_SPK
0R2J-2-GP
2017/03/02
Speaker
R29060R0603-PAD
1 2
1 2
R290810R2F-L-GP
1 2
R291010R2F-L-GP
R29110R0603-PAD
1 2
SPK_I2C_CLK27
SPK_I2C_DATA27
SPK_DET#_CON
RING2_R
AUD_PORTA_L_R_B
AUD_PORTA_R_R_B
SLEEVE_R
SPK1
9
1
2
3
4
5
6
7
8
10
FCN-CON8-GP
020.F0701.0008
2016/12/28 change PN
RING2_R
AUD_PORTA_L_R_B
JACK_PLUG
JACK_PLUG_DET
AUD_PORTA_R_R_B
SLEEVE_R
CONN Pin
Pin1
Pin2 SPK_L-_C
Pin3
Pin4
Pin5
Pin6
Pin7 SPK_I2C_DATA
Pin8
HPMIC1
3
1
5
6
2
4
MS
AUDIO-JK569-GP
022.10002.00U1
Net name
SPK_L+_C
SPK_R+_C
SPK_R-_C
GND
SPK_I2C_CLK
SPK_DET#_CON
AUD_AGND
Layout Note:
EC2908 EC2907 should place nearby codec IC.
B B
AUD_AGNDAUD_AGND
20160812 EMI
CLOSS TO HPMIC1
AUD_PORTA_R_R_B
SLEEVE_R
JACK_PLUG_DET
JACK_PLUG
AUD_PORTA_L_R_B
RING2_R
2
2
1
ED2901
A A
3
5
AZ5125-02S-R7G-GP
1
ED2902
AZ5125-02S-R7G-GP
3
2
1
ED2903
AZ5125-02S-R7G-GP
3
20160812 EMI
4
JACK_PLUG_DET
10 mils
3
2017/03/02
R2905
0R0402-PAD
1 2
AUD_AGND
Delay circuit
(JACK_PLUG_DET: on IO Board)
2017/03/02
JACK_PLUG
2
1 2
0R0603-PAD
R2923
10 mils10 mils
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Audio IO
Audio IO
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Audio IO
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
1
AUD_SENSE 27
29 106
29 106
29 106
A00
A00
A00
Page 30
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
(Reserved)
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
Thursday, June 29, 2017
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
30 106
30 106
30 106
1
Page 31
5
D D
4
3
2
1
C C
B B
(Blanking)
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
LAN RTL8106
LAN RTL8106
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
LAN RTL8106
KyloRen 13"
KyloRen 13"
KyloRen 13"
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
31 106Thursday, June 29, 2017
31 106Thursday, June 29, 2017
31 106Thursday, June 29, 2017
1
Page 32
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
XFOM&RJ45
XFOM&RJ45
XFOM&RJ45
32 106Thursday, June 29, 2017
32 106Thursday, June 29, 2017
32 106Thursday, June 29, 2017
1
A00
A00
A00
Page 33
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Card Reader-RTS5170
Card Reader-RTS5170
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
Card Reader-RTS5170
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
33 106Thursday, June 29, 2017
33 106Thursday, June 29, 2017
33 106Thursday, June 29, 2017
1
Page 34
5
4
3
2
1
SSID = USB3.0 Port1
D D
USB Charger Port1
5V_S5
C3402
12
USB_OC0# 16,35
C3403
12
12
C3401
USB30_VCCA
SC1U10V2KX-1DLGP
12
C3404
C3405
SC22U6D3V3MX-1-DL-GP
SC22U6D3V3MX-1-DL-GP
12
2016/01/11 modify
1
9
12
C C
USB_POWERSHARE_VBUS_EN24
USB_PWR_SHR_EN_L#24
5V_S5
X02 0414
1 2
R3405 0R0402-PAD
1 2
R3403 20KR2F-L-GP
R3404 22K1R2F-L-GP
DY
1 2
X02 0414
1 2
R3401 0R0402-PAD
1 2
5V_S5
R3406 0R0402-PAD
1 2
R3402 0R0402-PAD
ILIM_SEL
ILIM_LO
ILIM_HI
TPS2544RTER-GP
74.02544.073
U3401
SCD1U25V2KX-1-DL-GP
5
EN
4
ILIM_SEL
15
ILIM_LO
16
ILIM_HI
CTL1
CTL2
CTL3
13
IN
NC#9
FAULT#
CTL16CTL27CTL38GND
14
OUT
DP_OUT
DM_OUT
DP_IN
DM_IN
GND
17
3
2
10
11
SCD1U25V2KX-1-DL-GP
USB1_USB20_P 16
USB1_USB20_N 16
USB_PP0_R 36
USB_PN0_R 36
CDP
DCP Auto
Device Control Pins
CTL1
(EC control)
1 1
0
CTL3CTL2
1
1
ILIM_SEL
1
X1
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
34 106Thursday, June 29, 2017
34 106Thursday, June 29, 2017
34 106Thursday, June 29, 2017
1
A00
A00
A00
Page 35
5
SSID = USB3.0 Port1
U S B P o r t 1 T y p e - C U S B 3 . 0 P o r t 3
4
3
2
1
D D
5V_S5 USB30_VCCB
5
12
C3502
SC1U10V2KX-1DLGP
TypeC
C3503
12
DY
Active Low
4
2017/04/21
U3501
TypeC
IN
EN#
SY6288DAAC-GP
OUT
GND
OC#
1
2
3
USB_OC0# 16,34,35USB_EN#24,35,66
074.06288.009B
USB30_VCCB
USB_OC0# 16,34,35
2017/04/28
SCD1U16V2KX-3DLGP
USB_EN#24,35,66
Active Low
U3502
TypeC
5
IN
4
EN#
SY6288DAAC-GP
OUT
GND
OC#
1
2
3
074.06288.009B
C C
USB30_VCCB
12
R3501
DY
C3507
TypeC
USB3.0 Port1
C3508
SC1U10V2KX-1DLGP
12
TypeC
12
C3512
3A
12
TypeC
C3513
12
TypeC
C3514
Layout Note: Close USB3
12
12
TC3501
SC100U6D3V6MX-GP
DY
78.10710.52L
TypeC
USB3.0 Port3
100KR2J-1-GP
B B
SCD1U25V2KX-1-DL-GP
A A
5
SC22U6D3V5MX-2DLGP
SC10U6D3V3MX-DL-GP
for starlord placement modify
SC10U6D3V3MX-DL-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
USB switch
USB switch
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
USB switch
KyloRen 13"
KyloRen 13"
KyloRen 13"
A00
A00
A00
35 106Thursday, June 29, 2017
35 106Thursday, June 29, 2017
35 106Thursday, June 29, 2017
1
Page 36
5
SSID = USB3.0 Port1
4
3
2
1
USB2.0 Port2 and USB2.0 Port3 are on IOBD
USB3.0 Port1
D D
USB_PP0_R34
2017/03/17
EL3603
4 3
1 2
COIL-90OHM-100MHZ-5-GP
2nd: = 68.01012.20B
68.00396.001
USB_PN0_R34
USB20_DP0_C
USB20_DN0_C
ED3602
1
I/O1
2
GND
I/O23I/O3
AZC099-04S-1-GP
I/O4
VDD
6
5
4
75.09904.07C
2nd = 75.02304.07C
USB20_DP0_CUSB20_DN0_C
USB30_VCCA
USB30_VCCA
EC3601
SCD1U25V2KX-1-DL-GP
12
EMI 20160812
2016/12/29
USB30_VCCA
USB30_RXDN1_C
USB30_RXDP1_C
USB30_TXDN1_C
USB30_TXDP1_C
USB2
1
VBUS
5
STDA_SSRX-
6
STDA_SSRX+
8
STDA_SSTX-
9
STDA_SSTX+
12
CHASSIS#12
13
CHASSIS#13
SKT-USB13-18-GP-U
22.10339.331
USB20_DN0_C
USB20_DP0_C
2016/12/07 add AFTP
D+
GND_DRAIN
GND
GND
GND
1
AFTP3601
1
AFTP3602
USB20_DN0_C
2
D-
3
7
10
11
4
USB20_DP0_C
2016/12/29 change PN
2017/03/02
R3609
USB1_USB30_RX_N116
C C
1 2
0R0402-PAD
USB30_RXDN1_C
2017/03/16
R3610
USB1_USB30_RX_P116
1 2
0R0402-PAD
USB30_RXDP1_C
USB 3.0 Connector
Pin definition
1
POWER
2
USB 2.0 DUSB 2.0 D+
3
GND
4
StdA_SSRX-
5
6
StdA_SSRX+
GND
7
StdA_SSTX-
8
9
StdA_SSTX+
SuperSpeed RX
SuperSpeed TX
2017/03/02
C3601
USB1_USB30_TX_N116
B B
USB1_USB30_TX_P116
1 2
SCD1U25V2KX-1-DL-GP
C3602
1 2
SCD1U25V2KX-1-DL-GP
USB30_TX_CPU_N1_M
R3605
1 2
0R0402-PAD
2017/03/16
R3606
1 2
0R0402-PAD
2017/03/02
USB30_TXDN1_C
USB30_TXDP1_CUSB30_TX_CPU_P1_M
USB30_RXDP1_C
USB30_TXDP1_C
USB30_TXDN1_C
ED3601
1
2
3 8
4
5 6
L05ESDL5V0NA-4-GP
075.00550.0071
10
9
7
USB30_RXDP1_C
USB30_RXDN1_CUSB30_RXDN1_C
USB30_TXDP1_C
USB30_TXDN1_C
2017/03/17
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
USB30
USB30
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
USB30
KyloRen 13"
KyloRen 13"
KyloRen 13"
A00
A00
A00
36 106Thursday, June 29, 2017
36 106Thursday, June 29, 2017
36 106Thursday, June 29, 2017
1
Page 37
5
SSID = CCG4
2017/05/08
12
C3719
5V_VCONN_P1_IN
12
C3718
TypeC
SC10U6D3V3MX-DL-GP
TypeC
SCD1U25V2KX-1-DL-GP
12
2017/04/28
TypeC
R3734
1 2
100KR2F-L1-GP
5V_S5
D D
R3740
1 2
0R0603-PAD
VDDD
TypeC
1 2
TypeC
C3701
1 2
TypeC
C3702
C3705
TypeC
SCD1U25V2KX-1-DL-GP
12
2017/01/18
C3704
SC10U6D3V3MX-DL-GP
1 2
C3703
DY
4
VCC3PD VDDD VDDIO
R3732
1 2
0R0603-PAD
R3733
1 2
0R0402-PAD
2017/05/08
5V_VCONN_EN
U3703
2
IN
OUT_0
OUT_1
TypeC
4
FAULT#
3
EN
AP2151DFMG-7-GP-U
GND
PAD
5V_VCONN_P1
6
5
1
7
074.02151.0073
VCCPD_VBUS
TypeC
1 2
R3730 100KR2F-L1-GP
1 2
R3726 10KR2F-2-GP
VBUS monitor for OVP
TypeC
C3717 SCD1U25V2KX-1-DL-GP
12
TypeC
3
VDDIO VDDD
U3701
CCG4 40-QFN
31
VDDD
32
VDDIO
PD_VCCD
12
TypeC
5V_VCONN_P1
CCG4_FLIP#38
C3715
SC1U10V2KX-1DLGP
PD_VBUS_R
33
VCCD
8
V5V_P1
23
NC#23
3
I2C_SDA_SCB2_AR/VSEL_1_P1
4
I2C_SCL_SCB2_AR
5
I2C_INT_AR_P1
6
GPIO#6
13
VBUS_MON_P1/GPIO
37
GPIO#37
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
VBUS_P_CTRL_P1
VBUS_C_CTRL_P1
VBUS_DISCHARGE_P1
HPD_P1/GPIO
CC2_P1
CC1_P1
SDA_4/MUX_CTRL_2_P1
SCL_4/MUX_CTRL_1_P1
2
11
12
20
CPU_DP_HPD_MUX
18
PD_CC2
7
PD_CC1
9
26
28
29
2017/03/02
R3729
1 2
R3727
1 2
0R0402-PAD
R3728
1 2
0R0402-PAD
PD Function
PD_VBUS_P_CTRL1 43
PD_VBUS_C_CTRL1 43
PD_VBUS_DISCHG 43
R3725
10KR2F-2-GP
0R0402-PAD
I2C_DATA_PD 38
I2C_CLK_PD 38
I2C to MUX
1
VDDD
12
DY
PL 100K to GND
on CPU side
CPU_DP_HPD_R 8,38
USBC1_CC2_CONN 38
USBC1_CC1_CONN 38
DOCK_USB_EN_A 38
C C
SC1U10V2KX-1DLGP
VDDD
12
CCG4_ID_2
12
12
TypeC
TypeC
1 2
2017/03/02
R3731
1 2
0R0402-PAD
R3741
10KR2F-2-GP
R3742
30KR2F-GP
Q3701_G
VDDD
12
TypeC
R3724
4K7R2J-2-GP
C3716
1 2
TypeC
SCD1U25V2KX-1-DL-GP
Q3701
G
S
TypeC
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
TPAD14-OP-GP
5V_VCONN_P1
I2C_CLK_PD
I2C_DATA_PD CCG4_I2C_INT#_R
12
R3706
1MR2J-1-GP
R3735
2MR2-GP
TypeC
12
TypeC
For Dead Battery modify
2016/11/25 change PN follow 15"
D3701
SBA0520Q-R1-00001-GP-U
VCC3PD
TypeC
U3702
1
VIN
2
TPS70933_EN
GND
3
EN
AP2204K-ADJTRG1-GP
74.02204.03F
TypeC
Vout=1.215*(1+19.6/10)=3.5964
D3702
AK
SBA0520Q-R1-00001-GP-U
TypeC
5
OUT
ADJ
VREG3PD
4
TypeC
ADJ
12
R3701
19K6R2F-GP
12
R3702
10KR2F-2-GP
12
2017/01/24
CCG4_I2C_INT#24
2017/04/21
VDDD
12
DY
CCG4_ID_1
12
TypeC
C3710
TypeC
CCG4_I2C_SDA24
CCG4_I2C_SCL24
CCG4_OVP_TRIP_P143
TypeC
R3736
30KR2F-GP
R3737
10KR2F-2-GP
TypeC
R3738
10KR2J-3-GP
C3720
SCD22U10V2KX-2-GP
TypeC
SC2D2U10V3KX-1DLGP-U
12
R3707
2K2R2J-2-GP
SCD1U25V2KX-1-DL-GP
2 3
1
2 3
1
CCG4_I2C_INT#_R
VDDD
VDDD
3D3V_S5_KBC
TypeC
B B
SCD1U25V2KX-1-DL-GP
RN3701
TypeC
SRN2K2J-1-GP
RN3702
TypeC
SRN2K2J-1-GP
4
4
2017/01/24
CCG4_I2C_SCL
CCG4_I2C_SDA
From System
3D3V_S5
A K
VCCPD_VBUS
VBUS to 3.3V
A A
C3707
SC1U50V3KX-1-GP
1 2
TypeC
2016/12/21 modify
PD_SWD_IO
PD_SWD_CLK
VCONN_MON_P1
CCG4_ID_1
CCG4_ID_2
TP3704
1
PD_XRES
VCCPD_VBUS3D3V_S5
D
GPIO_21
12
R3739
100KR2J-1-GP
TypeC
TPS70933_EN
1
SWD_IO/AR_RST#
2
SWD_CLK/I2C_CFG_EC
15
I2C_INT_EC
16
I2C_SDA_SCB1_EC
17
I2C_SCL_SCB1_EC
19
VCONN_MON_P1/GPIO
14
OVP_TRIP_P1
25
SCL_3
27
GPIO#27
21
GPIO#21
10
XRES
CYPD4125-40LQXIT-8-GP
071.04125.0003
2017/05/04
GPIO#30
GPIO#34
GPIO#35
GPIO#36
GPIO#38
GPIO#39
GPIO#40
For Dead Battery modify
5
4
3
NC#22
NC#24
GND
30
22
24
34
35
36
For Debug
TP3701 TPAD14-OP-GP
TP3702 TPAD14-OP-GP
TP3703 TPAD14-OP-GP
DOCK_USB_EN_B 38
2017/01/24 modify by vendor
38
39
40
41
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
1
1
1
(Reserved)
(Reserved)
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
PD_SWD_IO
PD_SWD_CLK
PD_XRES
USBC1_CC1_CONN
USBC1_CC2_CONN
12
TypeC
12
C3711
SC390P50V2KX-1-GP
C3712
SC390P50V2KX-1-GP
TypeC
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
37 106Thursday, June 29, 2017
37 106Thursday, June 29, 2017
37 106Thursday, June 29, 2017
1
A00
A00
A00
Page 38
5
SSID = TYPEC MUX
4
3
3D3V_MUX
2
1
12
R3818
10KR2J-3-GP
C3801
C3802
3D3V_MUX_R
R3845
1KR2J-1-GP
R3846
1KR2J-1-GP
DY
L3801
1 2
TypeC
BLM15AX221SN1D-GP
DPB_AUXP 8
DPB_AUXN 8
I2C_CLK_PD 37
I2C_DATA_PD 37
C3815
3D3V_MUX
SCD1U25V2KX-1-DL-GP
C3816
1 2
TypeC
SCD1U25V2KX-1-DL-GP
C3817
1 2
TypeC
3D3V_MUX
DisplayPort Source
PCH_DPC_P08
D D
PCH_DPC_N08
PCH_DPC_P18
PCH_DPC_N18
PCH_DPC_P28
PCH_DPC_N28
PCH_DPC_P38
PCH_DPC_N38
USB HOST
TYPEC_USB30_RX_P416
TYPEC_USB30_RX_N416 CPU_DP_HPD_R 8,37
TYPEC_USB30_TX_P416
TYPEC_USB30_TX_N416
3D3V_MUX
TypeC
1 2
R3801 100KR2J-1-GP
1 2
R3802 100KR2J-1-GP
TypeC
TypeC
C3812 SCD1U25V2KX-1-DL-GP
1 2
TypeC
C3813 SCD1U25V2KX-1-DL-GP
1 2
TypeC
C3814 SCD1U25V2KX-1-DL-GP
1 2
TypeC
C3807 SCD1U25V2KX-1-DL-GP
1 2
TypeC
C3809 SCD1U25V2KX-1-DL-GP
1 2
TypeC
C3808 SCD1U25V2KX-1-DL-GP
1 2
TypeC
C3811 SCD1U25V2KX-1-DL-GP
1 2
TypeC
C3810 SCD1U25V2KX-1-DL-GP
1 2
TypeC
SCD1U25V2KX-1-DL-GP
1 2
C3805
TypeC
SCD1U25V2KX-1-DL-GP
1 2
C3806
TypeC
C3803 SCD1U25V2KX-1-DL-GP
1 2
TypeC
SCD1U25V2KX-1-DL-GP
1 2
C3804
DPB_AUXN_C
DPB_AUXP_C
PCH_DPC_P0_C
PCH_DPC_N0_C
PCH_DPC_P1_C
PCH_DPC_N1_C
PCH_DPC_P2_C
PCH_DPC_N2_C
PCH_DPC_P3_C
PCH_DPC_N3_C
MUX_TYPEC_RXP1
MUX_TYPEC_RXN1
MUX_TYPEC_RXP2
MUX_TYPEC_RXN2
MUX_TYPEC_TXP1
MUX_TYPEC_TXN1
MUX_TYPEC_TXP2
MUX_TYPEC_TXN2
TYPEC_USB30_RX_P4_C
TYPEC_USB30_RX_N4_C
TYPEC_USB30_TX_P4_C
TYPEC_USB30_TX_N4_C
U3801
1
VCC
6
VCC
20
VCC
28
VCC
9
DP0P
10
DP0N
12
DP1P
13
DP1N
15
DP2P
16
DP2N
18
DP3P
19
DP3N
30
RX1P
31
RX1N
40
RX2P
39
RX2N
33
TX1P
34
TX1N
37
TX2P
36
TX2N
5
SSRXP
4
SSRXN
8
SSTXP
7
SSTXN
TUSB546-DCIRNQR-GP
HPDIN/DCI_CLK
CAD_SNK/DCI_DAT
TypeC
071.00546.0003
2016/11/25 change PN
EQ0
EQ1
I2C_EN
SBU1
SBU2
AUXP
AUXN
DPEQ0/A1
DPEQ1
SSEQ0/A0
SSEQ1
FLIP/SCL
CTL0/SDA
CTL1/HPDIN
GND
38
EQ0
35
EQ1
32
HPDIN
CAD_SNK
29
17
I2CEN
USBC_DPAUX1
27
USBC_DPAUX2
26
DPB_AUXP_C
24
DPB_AUXN_C
25
DPEQ0_A1
14
2
DPEQ1
SSEQ0_A0
11
3
SSEQ1
I2C_CLK_PD_MUX
21
I2C_DATA_PD_MUX
22
MUX_HPD_PD
23
41
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
2017/03/02
R3814 0R0402-PAD
R3816 0R0402-PAD
R3849 0R0402-PAD
3D3V_S5
2016/10/31modify
3D3V_MUX 3D3V_MUX 3D3V_MUX3D3V_MUX 3D3V_MUX3D3V_MUX
C C
DY
TypeC
12
12
R3842
1KR2J-1-GP
R3843
1KR2J-1-GP
3D3V_MUX
12
DY
12
TypeC
R3840
1KR2J-1-GP
R3841
1KR2J-1-GP
12
TypeC
12
DY
R3874
1KR2J-1-GP
R3873
1KR2J-1-GP
12
DY
12
TypeC
R3847
1KR2J-1-GP
R3870
1KR2J-1-GP
12
DY
12
TypeC
R3871
1KR2J-1-GP
R3872
1KR2J-1-GP
12
R3852
DY
1KR2J-1-GP
SSEQ1DPEQ1EQ0 EQ1 I2CEN
12
TypeC
R3844
1KR2J-1-GP
TypeC
1 2
1 2
TypeC
1 2
1 2
1 2
2017/05/08
1 2
0R0603-PAD
SSEQ0_A0DPEQ0_A1
CAD_SNK
HPDIN
R3850
12
DY
12
TypeC
SCD1U25V2KX-1-DL-GP
C3818
1 2
TypeC
SCD1U25V2KX-1-DL-GP
12
TypeC
C3819
1 2
TypeC
R3821
4K7R2J-2-GP
TypeC
12
SC10U6D3V3MX-DL-GP
MUX_TYPEC_TXP1
MUX_TYPEC_TXN1
MUX_TYPEC_RXP1
MUX_TYPEC_RXN1
MUX_TYPEC_RXP2
MUX_TYPEC_RXN2
MUX_TYPEC_TXP2
MUX_TYPEC_TXN2
TypeC
C3864 SCD1U25V2KX-1-DL-GP
C3863 SCD1U25V2KX-1-DL-GP
TypeC
12
12
2017/03/02
2017/03/16
R3834 0R0402-PAD
1 2
R3835 0R0402-PAD
1 2
2017/03/16
R3836 0R0402-PAD
1 2
R3837 0R0402-PAD
1 2
TypeC
C3861 SCD1U25V2KX-1-DL-GP
C3862 SCD1U25V2KX-1-DL-GP
TypeC
12
12
MUX_TYPEC_TXP1_C
MUX_TYPEC_TXN1_C
TYPEC_CON_RXP1
TYPEC_CON_RXN1
TYPEC_CON_RXP2
TYPEC_CON_RXN2
MUX_TYPEC_TXP2_C
MUX_TYPEC_TXN2_C
2017/03/16
R3832 0R0402-PAD
1 2
R3833 0R0402-PAD
1 2
TYPEC_CON_TXN1
TYPEC_CON_TXP1
TYPEC_CON_RXN1
TYPEC_CON_RXP1
2017/03/17
TYPEC_CON_RXP2
TYPEC_CON_RXN2
TYPEC_CON_TXN2
R3838 0R0402-PAD
1 2
R3839 0R0402-PAD
1 2
2017/03/16
TYPEC_CON_TXP1
TYPEC_CON_TXN1
TYPEC_CON_TXP2
TYPEC_CON_TXN2
ED3801
1
2
3 8
4
5 6
L05ESDL5V0NA-4-GP
075.00550.0071
TypeC
ED3802
1
2
3 8
4
5 6
L05ESDL5V0NA-4-GP
075.00550.0071
TypeC
TYPEC_CON_TXN1
10
9
TYPEC_CON_RXN1
7
TYPEC_CON_RXP2
10
TYPEC_CON_RXN2
9
TYPEC_CON_TXP2TYPEC_CON_TXP2
7
TYPEC_CON_TXN2
TYPEC_CON_TXP1
TYPEC_CON_RXP1
ED3803
3
TypeC
AZ5315-02F-GP
2
1
USBC_DPAUX1
USBC_DPAUX2
83.05315.0A0
B B
TYPEC_USB20_P16
TYPEC_USB20_N16
TYPEC_SMBCLK24
TYPEC_SMBDA24
2017/05/17
CCG4_FLIP#37 USBC1_CC1_CONN37 USBC1_CC2_CONN 37
3D3V_MUX2
12
C3865
SCD1U25V2KX-1-DL-GP
TypeC
R3853 0R0402-PAD
1 2
R3854 0R0402-PAD
1 2
R3855 0R0402-PAD
1 2
R3856 0R0402-PAD
1 2
R3857 0R0402-PAD
1 2
R3858 0R0402-PAD
1 2
R3848
1 2
0R0603-PAD
2017/05/08
3D3V_MUX2
MUX_INB_P
MUX_INB_N
MUX_SAI
MUX_SBI
MUX_SAO
MUX_SBO
2017/03/02
3D3V_MUX23D3V_S5
U3802
13
VCC
1
INA+
2
INA-
3
INB+
4
INB-
14
SAI
12
SBI
15
SAO
11
SBO
TS3DS10224RUKR-GP
OUTA0+
OUTA0-
OUTA1+
OUTA1-
OUTB0+
OUTB0-
OUTB1+
OUTB1-
ENA
ENB
GND
GND
18
17
20
19
8
9
6
7
16
10
5
21
TOP_MUX_P_L
TOP_MUX_N_L
BOT_MUX_P_L
BOT_MUX_N_L
MUX_ENA_L
MUX_ENB_L
R3859 0R0402-PAD
1 2
R3860 0R0402-PAD
1 2
2017/03/02
DOCK_USB_EN_A 37
DOCK_USB_EN_B 37
071.10224.0003
TypeC
2017/03/16
A A
TOP_MUX_N_L
TOP_MUX_P_L
EL3801
1 2
TypeC
4 3
COIL-90OHM-100MHZ-5-GP
68.00396.001
2nd: = 68.01012.20B
TOP_MUX_N
TOP_MUX_P
BOT_MUX_N_L
BOT_MUX_P_L
2017/03/16
EL3802
1 2
TypeC
4 3
COIL-90OHM-100MHZ-5-GP
68.00396.001
2nd: = 68.01012.20B
BOT_MUX_N
BOT_MUX_P
ED3804
3
TypeC
AZ5315-02F-GP
83.05315.0A0
2016/12/07 add AFTP
VCCPD_VBUS
USBC1_CC1_CONN
USBC_DPAUX1
USBC1_CC2_CONN
USBC_DPAUX2
VCCPD_VBUS
2
1
TOP_MUX_P
TOP_MUX_N
12
R3830
2MR2F-GP
TypeC
VCCPD_VBUS
SCD1U25V2KX-1-DL-GP
1
1
1
1
1
1
12
C3821
TypeC
TYPEC_CON_TXP1
TYPEC_CON_TXN1
TOP_MUX_P
TOP_MUX_N
USBC_DPAUX1
TYPEC_CON_RXN2
TYPEC_CON_RXP2
AFTP3801
AFTP3802
AFTP3803
AFTP3804
AFTP3805
AFTP3806
2016/12/16 add AFTP
5
4
3
2
TypeC
ED3805
3
AZ5315-02F-GP
83.05315.0A0
VCCPD_VBUS
2
1
BOT_MUX_P
BOT_MUX_N
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
16
17
18
19
USB1
GND
SSTXP1
SSTXN1
VBUS#A4
CC1
DP1
DN1
RFU1
VBUS#A9
SSRXN2
SSRXP2
GND
GROUND
GROUND
GROUND
GROUND
SKT-USB34-20-GP-U
TypeC
CHASSIS#13
CHASSIS#14
CHASSIS#15
CHASSIS#20
CHASSIS#21
CHASSIS#22
SSTXP2
SSTXN2
VBUS#B4
RFU2
VBUS#B9
SSRXN1
SSRXP1
022.10005.M022
2017/05/04
VCCPD_VBUS
B1
GND
B2
B3
B4
B5
CC2
B6
DP2
B7
DN2
B8
B9
B10
B11
B12
GND
13
14
15
20
21
22
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
ED3806
3
TypeC
AZ5315-02F-GP
83.05315.0A0
(Reserved)
(Reserved)
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
USBC1_CC1_CONN
2
USBC1_CC2_CONN
1
TYPEC_CON_TXP2
TYPEC_CON_TXN2
BOT_MUX_P
BOT_MUX_N
USBC_DPAUX2
TYPEC_CON_RXN1
TYPEC_CON_RXP1
R3831
2MR2F-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
1
TypeC
38 106Thursday, June 29, 2017
38 106Thursday, June 29, 2017
38 106Thursday, June 29, 2017
12
A00
A00
A00
Page 39
5
D D
4
3
2
1
(Blanking)
C C
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
39 106Thursday, June 29, 2017
39 106Thursday, June 29, 2017
39 106Thursday, June 29, 2017
1
Page 40
5
SSID = Power Plane & Sequence
3D3V_S0
3D3V_S0
5V_S5
5V_S5
2016/12/16 add AFTP
ROSA Run Power
2016/12/07 for power sequence
D4005
83.R2004.G8F
K A
D D
SIO_SLP_S3#17,24,40,51
2016/11/28 for power sequence
DY
RB751V-40H-GP
2017/03/02
R4010
1 2
0R0402-PAD
C4003
3V5V_S0_ON
5V_S5
SCD22U10V2KX-2-GP
DY
1 2
3D3V_S5
5V_S5
U4001
4
VBIAS
1
IN1#1
2
IN1#2
3
EN1
6
IN2#6
7
IN2#7
5
EN2
G5016KD1U-GP
074.05016.0093
OUT1#13
OUT1#14
CT1
OUT2#8
OUT2#9
CT2
GND
GND
13
14
12
8
9
10
11
15
3V5V_CT1
3V5V_CT2
4
1
AFTP4001
1
AFTP4002
1
AFTP4003
1
AFTP4004
2017/05/08
PWR_3D3V_S0
PWR_5V_S0
C4001
SCD01U50V2KX-1DLGP
SCD01U50V2KX-1DLGP
C4002
12
12
12
C4004
SC10U25V5KX-DL-GP
R4012
1 2
0R0603-PAD
12
C4005
SC10U25V5KX-DL-GP
R4013
1 2
0R0603-PAD
3D3V_S0
5V_S0
3
D4002
K A
DY
D4003
K A
R4011
1 2
0R0402-PAD
RB751V-40H-GP
83.R2004.G8F
Power Good
RSMRST_PWRGD#
SIO_SLP_S3#
83.R2004.G8F
1D2V_VTT_PWRGD51
[#543016] Optional, Added for addition system robustness
2017/01/24
1D0V_S5_PWRGD52
PRIM_PWRGD24,54
3V_5V_POK17,45,52,54
NON DS3: PH 3V_5V_POK to 3D3V_AUX_S5 at page17
1 2
R4029 0R0402-PAD
1 2
R4030 0R0402-PAD
1 2
R4033
0R2J-2-GP
2016/12/29
RB751V-40H-GP
DY
2
R4031
100KR2J-1-GP
2016/12/13
3D3V_S0
12
12
R4005
100KR2J-1-GP
3D3V_S5_KBC3D3V_S5
2017/03/16
1 2
R4002 0R0402-PAD
12
R4032
100KR2J-1-GP
DY
RSMRST_PWRGD#
1
RUNPWROK 17,24
VR_EN 46
5V_S0
2016/12/06 for power sequence
5V_S0 Comsumption
Peak current 5A
3D3V_S0
3D3V_S0 Comsumption
Peak current 2.5A
D4001
2
1
C C
20KR2F-L-GP
R4006
12
1 2
R4009 10KR2J-3-GP
C4009
SC10U6D3V3MX-DL-GP
12
DVT1 0210
modify at DVT1 power sequence 20150203
EOPIO and EDRAM
B B
MANAGEMENT RAIL POWER GENERATION
3
LBAS16LT1G-GP
83.00016.P11
PURE_HW _SHUTDOWN# 263V_5V_EN45
ALWON 24
+V_EDRAM_VR
Voltage = 1.0 V ± 50 mV
Imax = 3.2 A
TRISE = 240 us
VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization.
VCCIO and VCCSTG
D4004
83.R2004.G8F
K A
RB751V-40H-GP
2016/12/29
R4017
1 2
DY
47KR2J-L2-GP
3D3V_S5
U4007
SIO_SLP_S3#17,24,40,51
SIO_SLP_S0#17,24,91
1
2
3
TC7SZ08FU-LJ-CT-GP
5
4
VCCSTG_EN_L
073.7SZ08.000G
DY
2016/12/16 DY
+V_EOPIO_VR
Voltage = 1.0 V ± 50 mV
Imax = 2.8 A
TRISE = 240 us
+V1.8V_S0
2016/12/29
3D3V_S0
12
R4003
100KR2J-1-GP
5V_S5
C4032
SC1U10V2KX-1DLGP
12
R4037
1 2
0R2J-2-GP
DY
VCCSTG_EN_R
12
C4033
DY
SCD1U25V2KX-1-DL-GP
2016/12/07 for power sequence
SCD1U25V2KX-1-DL-GP
SIO_SLP_S3#17,24,40,51
1D0V_S5
G
S
C4006
SC10U6D3V3MX-DL-GP
12
1
2
3
4
C4037
Q4001
2N7002K-2-GP
C4035
SC22U6D3V3MX-1-DL-GP
12
12
U4002
VIN
VOUT#8
VIN
VOUT#7
VBIAS
VOUT#6
EN
APE8939GN3-GP
074.08939.0093
12
GND
D
C4036
SC22U6D3V3MX-1-DL-GP
VIN
12
R4034
10KR2J-3-GP
1D8V_EN#
8
7
6
5
9
R4035
1 2
20KR2J-L2-GP
150mA
C4038
12
SC1U10V2KX-1DLGP
1D8V_EN_R#
2017/05/08
R4045
1 2
0R1206-PAD
R4042
1 2
0R0603-PAD
12
C4007
SCD1U25V2KX-1-DL-GP
Q4002
DMP2130L-7-GP
S
D
G
G
84.02130.031
2nd = 84.00102.031
3rd = 84.03413.B31
+VCCIO+VCCIO_SIP
+VCCSTG
D
DY
1D8V_S0+V1.8A
12
C4039
SCD1U16V2KX-3GP
1D0V_S5
12
SC10U25V5KX-DL-GP
A A
2016/12/12 for power sequence
R4024
SIO_SLP_S4#17,54
5
1 2
0R0402-PAD
C4034
SCD1U25V2KX-1-DL-GP
C4013
U4006
1
VIN
VCCSTU_EN_R U4006_CT
5V_S5
12
DY
DY
12
SC1U10V2KX-1GP
2
3
C4031
VOUT#8
VIN
VOUT#7
EN
VBIAS4GND
APE8937GN2-GP-U
CT
GND
074.08937.0093
+V1.00U_CPU
8
7
6
5
9
12
DY
4
C4012
SC10U6D3V3MX-DL-GP
12
C4017
SCD1U16V2KX-3GP
2017/05/08
R4036
1 2
0R0603-PAD
R4038
1 2
0R0603-PAD
+VCCST_CPU
+VCCSFR
0.04 A
3
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Power Plane Enable
Power Plane Enable
Power Plane Enable
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
40 106
40 106
40 106
A00
A00
A00
Page 41
5
4
SSID = Power Plane & Sequence
3
2
1
3D3V_S5 3D3V_S5_PCH
2017/03/02
D D
C C
R4101
1 2
0R0805-PAD
Reserve by NON DS3 function 20150413
DS3
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Connected_Standby(1/2)+DS3
Connected_Standby(1/2)+DS3
Connected_Standby(1/2)+DS3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
41 106Thursday, June 29, 2017
41 106Thursday, June 29, 2017
41 106Thursday, June 29, 2017
1
Page 42
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Connected_Standby(2/2)
Connected_Standby(2/2)
Connected_Standby(2/2)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
Thursday, June 29, 2017
2
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
42 106
42 106
42 106
1
Page 43
5
Main Func = ADT Input
4
5V_S5
3
2
1
2016/12/21 change PN
200KR2F-L-GP
TypeC
PQ4311
5
6
VBUS overvoltage
output indicator
(active LOW)
ED4302
LBAV99LT1G-1-GP
75.00099.O7D
2
12
PR4303
10KR2J-3-GP
PS_ID_R1
12
PC4302
SCD1U50V3KX-DL-GP
PQ4305
R2
1
R1
LTA024EUB-FS8-GP
84.00024.01K
VCCPD_VBUS
12
PR4343
TypeC
12
PC4315
34
2
1
PC4314
TypeC
2nd = 75.00099.K7D
3rd = 75.00099.Q7D
4th = 75.00099.D7D
PR4305
1 2
33R2J-2-GP
2
AD_OFF_R
3
IE_DELAY_G
IE_DELAY_S
SC1U25V2KX-4-GP
12
TypeC
PD_VBUS_C_CTRL1_A
CCG4_OVP_TRIP_P1
PBAT_PRES1#
3
ED4303
LBAV99LT1G-1-GP
1
2
SC1U50V3KX-1-GP
PC4301
12
PQ4313
3 4
2
1
2N7002KDW-GP
84.2N702.A3F
PR4344
680KR2J-GP
TypeC
1 2
200KR2F-L-GP
2017/03/21
75.00099.O7D
3D3V_S5_KBC
3
PR4302
15KR2F-GP
1 2
PQ3802_1
PR4309
1
PD4303
L30ESD24VC3-2-GP
KA
KA
3D3V_S5
DC_IN_OK#
100KR2J-1-GP
1 2
2016/11/29 SC要follow 15"
AC_DIS_R
12
R4303
1KR2F-3-GP
B
Layout Note:
PSID Layout width > 25mil
D D
20140815 david
2017/03/16
JGND
Pin Definition: TBD
DCIN1
9
1
2
3
4
5
6
7
8
10
020.F000F.0008
C C
FCN-CON8-1-GP
2017/03/15
PS_ID_R +DC_IN_C
EC4311
12
SCD1U25V2KX-GP
DY
2016/01/07 mofiy
2016/12/06 follow 15"
12
DY
JGND JGND
EL4304
1 2
0R0805-PAD
EL4303
1 2
0R0805-PAD
1
1
+DC_IN_C
12
EC4301
SC10U25V5KX-DL-GP
JGND JGND
EC4312
EC4313
12
SCD1U25V2KX-GP
DY
AFTP4301
AFTP4302
PD4301
12
P6SMB27A-GP
EC4302
A K
SCD1U25V2KX-1-DL-GP
83.P6SMB.JAG
2017/03/15
SCD1U25V2KX-GP
1 2
1 2
PS_ID_R
60ohm@100MHz
DCR=0.02 ohm
Max current = 6000mA
2017/03/16
EL4301
0R0805-PAD
12
TypeC
PR4312
EL4302
0R0805-PAD
AC_IN#_G
PR4313
84K5R2F-GP
TypeC
470KR2F-GP
12
AC_DIS24
DC_IN_OK
PR4317
1 2
0R0603-PAD
2017/06/20
PU4307
1
NC#1
2
A
3
GND
SN74AUP1G04DRYR-GP
2
1 2
R4305
0R2J-2-GP
PD4307
RB751V-40H-GP
PD4308
RB751V-40H-GP
VCC
NC#5
Y
PS_ID_R2
3
DY
6
5
4
84.T3904.K11
E
B
PQ4302
MMBT3904-5-GP-U
C
PSID_DISABLE#_R_C
G
D S
PQ4301
DMN5L06K-7-GP
PR4306
1 2
DY
33R2J-2-GP
PQ4304
C
R1
E
R2
LMUN5212T1G-GP
84.05212.B11
84.05067.031
AD_OFF_L
SC100P50V2JN-3DLGP
73.01G04.01V
+DC_IN_C
AFTP4303
AFTP4304
AFTP4305
AFTP4316
B B
2017/04/25
Main Func = M-BAT Input
BT+
SCD1U50V3KX-DL-GP
A A
1
1
1
1
2017/03/08
IC_DELAY
12
PC4307
SC1KP50V2KX-1DLGP
TypeC
EC4308
2017/01/24
PBAT_CHG_SMBCLK24,44
PBAT_CHG_SMBDAT24,44
PBAT_PRES#24,44
PS_ID_R
+DC_IN_C
+DC_IN_C
AC_IN#_G 24
U4302
5
SENSE
4
TypeC
CD
OUT
VDD
VSS
1
2
3
074.01004.00BF
VBUS_C_CTRL = 1 (Consumer Path ON)
VBUS_C_CTRL = 0/Z (Consumer Path OFF)
2017/03/07
12
12
EC4307
SCD1U25V2KX-1-DL-GP
EC4309
EC4310
12
SC10P50V2JN-4GP
SC10P50V2JN-4GP
DY
5
12
DY
3D3V_S5
12
EC4306
DY
1 2
2017/06/20
PR4335
10KR2J-3-GP
DC_IN_OK
PD_VBUS_C_CTRL137
RN4302
4 5
3
2
1
SRN100J-4-GP
SC10P50V2JN-4GP
6
7
8
DC_IN_OK
DC_IN_OK 24
G
S
PR4323
100KR2F-L1-GP
PQ4306
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
12
TypeC
Batt Connecter
PBAT_SMBCLK1
PBAT_SMBDAT1
PBAT_PRES1#
1 2
R4301
0R0402-PAD
SYS_PRES1#
1
1
1
PD_VBUS_C_CTRL1_A
D
G
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.2N702.W31
BATT1
1
NP1
2
3
4
5
6
7
8
9
10
NP2
HIG-CON10-2-GP
020.F0867.0010
AFTP4306
AFTP4307
AFTP4308
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
SYS_PRES1#
VCC3PD
TypeC
PR4337
1 2
240KR2F-L-GP
VBUS_PRODECT#
PQ4312
VCC3PD
TypeC
D
12
PR4342
100KR2F-L1-GP
PD_VBUS_C_CTRL1_R
2N7002KDW-GP
84.2N702.A3F
TypeC
Placement: Close to Batt Connector
PBAT_SMBDAT1
3
1
2nd = 75.00099.K7D
3rd = 75.00099.Q7D
4th = 75.00099.D7D
2nd = 75.00099.K7D
3rd = 75.00099.Q7D
4th = 75.00099.D7D
1
1
1
1
BT+
1
BT+
1
BT+
1
4
3
1
AFTP4309
AFTP4310
AFTP4311
AFTP4312
AFTP4313
AFTP4314
AFTP4315
PBAT_SMBCLK1
2
ED4301
LBAV99LT1G-1-GP
75.00099.O7D
3D3V_S5
1
2
PD4302
LBAV99LT1G-1-GP
75.00099.O7D
2nd = 75.00099.K7D
3
3rd = 75.00099.Q7D
4th = 75.00099.D7D
20161226
+DC_IN AD+
12
240KR3-GP
PR4307
12
47KR2F-GP
PR4308
2017/04/21
TypeC
PBAT_PRES#
5
6
PD_VBUS_C_CTRL1_A
VCCPD_VBUS
12
PR4319
TypeC
12
PC4311
SC100P50V2JN-3DLGP
TypeC
PD_VBUS_P_CTRL137
VCCPD_VBUS
DY
PR4329
100KR2F-L1-GP
DY
PU4301
S
1
S
2
S
3
G D
4 5
AON7403-GP-U
84.07403.037
TypeC
PQ4307
5
6
2N7002KDW-GP
84.2N702.A3F
PD_VBUS_P_CTRL1 = 1 (Provider Path ON)
PD_VBUS_P_CTRL1 = 0/Z (Provider Path OFF)
2017/05/10
12
PR4331
137KR2F-1-GP
U4301_IN VBUS_PRODECT
12
3D3V_S5
12
PR4304
2K2R2J-2-GP
PS_ID 24
D
8
D
7
D
6
VCCPD_VBUS
PR4336
PR4322
34
2
1
PD_VBUS_C_CTRL1_R
VCCPD_VBUS
PR4310
1KR2J-1-GP
1 2
TypeC
100KR2F-L1-GP
5
SENSE
4
CD
DY
12
DY
TypeC
680KR2J-GP
1 2
12
TypeC
10KR2F-2-GP
PR4324
TypeC
DY
U4301
OUT
VDD
VSS
PC4305
USB_TYPEC_R
USB_TYPEC_SW
1
2
3
SCD01U50V2KX-1DLGP
PD_VBUS_P_CTRL1_R
12
VCC3PD
12
TypeC
TypeC
1 2
PR4334
12
PC4303
DY
SCD01U50V2KX-1DLGP
PC4310
1 2
SC100P50V2JN-3DLGP
DC_IN_OK
USB_TYPEC_DIS
PR4338
100R2512J-1-GP
1 2
TYPEC_5V_L
TYPEC_5V_L
240KR2F-L-GP
need check
VCC3PD
074.01004.00BF
VCCPD_VBUS>5.4V VBUS_PRODECT=H
VCCPD_VBUS<5.4V VBUS_PRODECT=L
20161031
12
PC4306
PC4304
SC10U25V5KX-DL-GP
SCD01U50V2KX-1DLGP
PQ4310
5
6
2N7002KDW-GP
84.2N702.A3F
SI7625DN-T1-GE3-GP
84.07625.037
PQ4309
5
6
2N7002KDW-GP
84.2N702.A3F
Id=115mA
TypeC
Vth(max)=1V
G
TypeC
12
PR4316
20KR2J-L2-GP
TypeC
PU4303
S
1
S
2
S
3
G D
4 5
AON7403-GP-U
84.07403.037
34
2
1
PU4305
D
8
D
7
D
6
D
5
TypeC
TYPEC_5V
34
CCG4_OVP_TRIP_P1_G
2
1
DS
2
2017/06/20
DC_IN_OK
PD_VBUS_P_CTRL1
12
PR4311
100KR2F-L1-GP
NON_TypeC
DC_IN_OK
RB751V-40H-GP
NON_TypeC
1 2
PR4315
18K7R2F-GP
20161226
D
8
D
7
D
6
+SDC_IN_SW_R1
12
TypeC
S
1
S
2
S
3
G
4
TYPEC_5V_SW_R
PR4340
100KR2F-L1-GP
PD_VBUS_P_CTRL1_R
DY
Q4301
DMN5L06K-7-GP
84.05067.031
AC_IN#_G
PD4304
1
3
2
BAT54C-7-F-3-GP
75.00054.E7D
20161226
PU4302
S
D
8
7
6
S
D
S
D
GD
AON7403-GP-U
84.07403.037
NON_TypeC
PD4305
2016/12/27 change PN
KA
If=0.3A
USB_ADT
PD_VBUS_DISCHG 37
PR4332
PD_VBUS_DISCHG = 1 (VBUS
100KR2F-L1-GP
Discharging)
PD_VBUS_DISCHG = 0/Z (VBUS not
discharging)
64K9R2F-1-GP
12
TypeC
TypeC
PU4304
D
8
D
7
D
6
AON7403-GP-U
84.07403.037
TYPEC_5V_SW
PR4330
TypeC
1 2
12
PR4339
TypeC
PC4313
SCD1U25V2KX-GP
1 2
2017/05/12
2017/06/17
240KR2F-L-GP
DY
R4302
DY
0R2J-2-GP
1 2
12
1
2
3
45
ACOK_IN_M 17,43,44
+SDC_IN_SW_R1
2017/06/12
S
1
S
2
S
3
GD
45
TypeC
USB_ADT_SW_R
DC_IN_OK_R
SCD1U25V2KX-1-DL-GP
PC4312
1 2
TypeC
20161226
2017/03/02
PR4341
1 2
0R0402-PAD
VBUS overvoltage
output indicator
(active LOW)
DC_IN_OK_R
R4304
1MR2J-1-GP
+SDC_IN
12
PR4318
100KR2J-1-GP
PU4306
+SDC_IN
5
6
RB751V-40H-GP
TypeC
D
8
D
7
D
6
D
5
+SDC_IN_SW
USB_ADT_R1
PD4306
KA
If=0.3A
USB30_VCCB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
DCIN
DCIN
DCIN
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
USB_ADT
TypeC
PR4327
10KR2F-2-GP
ACOK_IN_M 17,43,44
20KR2F-L-GP
43 106Thursday, June 29, 2017
43 106Thursday, June 29, 2017
43 106Thursday, June 29, 2017
PR4328
TypeC
1 2
12
1 2
PR4333
10KR2F-2-GP
+SDC_IN
12
TypeC
PR4320
240KR2F-L-GP
USB_ADT_SW
12
PR4321
47KR2F-GP
PQ4308
3 4
2
1
2N7002KDW-GP
84.2N702.A3F
TypeC
S
1
S
2
S
3
G
TypeC
4
SI7625DN-T1-GE3-GP
84.07625.037
CCG4_OVP_TRIP_P1 37
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
A00
A00
A00
Page 44
5
4
3
2
1
Main Func = Charger
75.87333.071 CSD87330
HSVgs @ 5V,
Id = 15A,
Rds(on) = 9.45mohm,
LS-
PU4403
8
D
AON7380-GP
SSS
123
20170309
8
D
SSS
123
PC4439
SC1U50V3KX-1- GP
Vgs @ 5V,
Id = 15A,
Rds(on) = 3.6mohm,
12
12
PC4405
PC4404
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
2.2uH,
DCR=14~16.5mohm,
Idc=8.5A, Isat=11A
10.3*11.2*2.4mm
PL4401
1 2
12
COIL-2D2UH- 72-GP
PR4416
DY
2D2R5J-1-GP
PWR_CHG_SNB
12
PC4435
SC1KP50V2KX-1D LGP
DY
PWR_CH G_LGATE2
PR4408
2D2R3-1-U- GP
PWR_CH G_BT2_R
12
12
AD_IA 24
PU4405
567
8
DDD
D
AON7380-GP
G
SSS
PU4406
AON7380-GP
123
PWR_CH G_PHASE2
567
8
DDD
D
G
SSS
123
PC4423
SCD22U25V3KX- DL-GP
1 2
20170309
20170309
Check with DELL
4
PWR_CHG_HG2_R
4
2017/03/02
PR4420
1 2
0R0805-PAD
2017/05/08
PC4424
SC1U50V3KX-1- GP
DY
1 2
1 2
DY
PC4426
SC1U50V3KX-1- GP
12
12
PC4406
SCD1U25V2KX-1-DL-GP
PR4424
1R2F-GP
12
PC4425
SC1U10V2KX-1D LGP
PR4425
1R2F-GP
PC4407
SC10U25V5KX-DL-GP
PWR_CHG_CSOP_R
12
PWR_CHG_CSON_R
12
12
12
PC4408
SC10U25V5KX-DL-GP
GAP-CLOSE-P WR-3-G P
GAP-CLOSE-P WR-3-G P
PC4409
SC10U25V5KX-DL-GP
PG4405
PG4406
12
12
12
PC4410
SC10U25V5KX-DL-GP
12
12
12
PC4411
SC10U25V5KX-DL-GP
PR4407
D01R3721F-GP -U
PWR_CH G_VBATIN
12
PC4427
SC10U25V5KX-DL-GP
12
12
PC4412
PC4413
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
84.07121.037 SI7121DN
Rds(on) = 24~30 mohm,
Vgs=10V, I-D = 12A,
Qg = 43nC
Vgs=± 25V, Vds=-30V,
I-D=-16A
PC4428
SC10U25V5KX-DL-GP
12
PC4429
SC4700P25V2KX-4- GP
20161214
12
PC4414
SC10U25V5KX-DL-GP
PU4412
1
S
S
2
S
3
G D
4 5
AON7401-GP
84.07401.037
20161214
12
DY
+SDC_IN 20V_DCBATOUT
PR4401
D02R6F-GP
20161027
PC4401
12
SC10U25V5KX-DL-GP
D D
20161103 20161103
PD4408
402KR2F-GP
PR4404
1 2
PR4427
2
VDD
12
100KR2F-L2-GP
ACOK#
AD+USB_ADT
1
2016/12/29 change PN
3
DCBATOUT
2016/12/29 change PN
AD+
USB_ADT
75.00054.E7D
2nd = 83.R2003.W81
PWR_CHG_AIN
3rd = 75.00054.A7D
4th = 83.R2003.V81
12
12
PR4406
100KR2F-L1-GP
100KR2F-L1-GP
PWR_CH G_PROCH OT#
PG4408
GAP-CLOSE-P WR-3-G P
83.R2004.G8F
PD4407
RB751V-40H-G P
PD4401
1
2
BAT54C-7-F- 3-GP
PR4417
1 2
3D3V_AUX_S5
12
12
KA
3
PWR_CH G_VDDP
PR4429
100KR2F-L2-GP
PWR_CHG_DCIN_R
SC1U50V3KX-1- GP
PR4405
4D7R2F-GP
1 2
PC4422
SC4D7U6D3V 3KX-DLGP
PBAT_PRES#24,43
PR4403
2D2R5J-1-GP
PC4419
VDD
12
+SDC_IN
12
12
PR4409
100KR2F-L1-GP
SC10P50V2JN-4D LGP
2016/12/29 change PN
BAT54C-7-F- 3-GP
75.00054.E7D
2nd = 83.R2003.W81
3rd = 75.00054.A7D
4th = 83.R2003.V81
C C
PC4420
SCD1U25V2KX- 1-DL-GP
PBAT_CHG_SM BDAT24,43
PBAT_CHG_SM BCLK24,43
PQ4415
HW_ACA V_IN24
ACOK_IN_M17,4 3
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
6
2N7002KDW -GP
84.2N702.A3F
2345
1
SC1U25V2KX-4- GP
PWR_CH G_DCIN
PWR_CH G_ACIN
PWR_CH G_OTGEN
PWR_CH G_ACOK
074.09538.0073
12
PC4430
PC4416
ISL9538HRTZ-GP -U
12
12
12
1 2
PU4401
17
DCIN
18
VDD
19
ACIN
20
CMIN
21
SDA
22
SCL
23
PROCHOT#
24
ACOK
20161031
PR4410
105KR2F-1-GP
TP8304
TPAD14-OP-G P
1 2
PG4401
GAP-CLOSE-P WR-3-G P
PG4402
GAP-CLOSE-P WR-3-G P
PWR_CHG_CSIP_R
20161031
PR4422
3D3R2F-GP
12
PC4415
SC4D7U6D3V 2MX-1-GP
20161214
TP4401
TPAD28-2-GP
1
PWR_CHG_CSIN
PWR_CHG_CSIP
PWR_CHG_BOOT1
PWR_CHG_ASGATE
16
15
14
13
12
ADP
CSIP
CSIN
ASGATE
BATGONE25PROG27CMOUT26COMP28AMON/BMON29PSYS30VBAT31BGATE
PWR_CHG_COMP
PWR_CHG_PROG
PWR_CHG_AMON
PWR_CHG_OTGPG
PWR_CHG_BATGONE
1 2
1
1 2
12
12
PWR_CHG_CSIN_R
20161031
12
PR4423
3D3R2F-GP
1 2
PR4402
2D2R3-1-U- GP
PWR_CHG_UGATE1
PWR_CHG_PHASE1
10
9
11
BOOT1
LGATE1
PHASE1
UGATE1
32
PWR_CHG_BGATE
PWR_CHG_VBAT1
P_SYS
PR4412
0R0402-PAD
PC4432
SC1KP50V2KX-1D LGP
PC4417
SC1U25V2KX-4- GP
2017/03/02
PR4414
1 2
0R0805-PAD
PWR_CHG_BT1_R
12
8
VDDP
7
LGATE2
6
PHASE2
5
UGATE2
4
BOOT2
3
VSYS
2
CSOP
1
CSON
33
PGND
PC4440
SC1U50V3KX-1- GP
12
1 2
PR4413
1 2
6K04R2F-GP
2017/03/02
12
PC4402
SC10U25V5KX-DL-GP
PWR_CHG_HG1_R
PC4436
SCD22U25V3KX- DL-GP
20170309
AON7380-GP
PWR_CH G_LGATE1
PWR_CH G_VDDP
PWR_CH G_PHASE2
PWR_CH G_UGATE2
PWR_CH G_BOOT2
PWR_CH G_CSOP
PWR_CH G_CSON
20161031
PR4478
100R2F-L1-GP- U
12
PC4403
SC10U25V5KX-DL-GP
567
G
4
12
567
PU4404
G
4
PC4421
SC4D7U6D3V 3KX-DLGP
1 2
DDD
DDD
PC4418
SC22U25V5MX-GP
DCBATOUT
12
12
PC4437
PC4434
DY
DY
SC22U25V5MX-GP
SC22U25V5MX-GP
BT+
8
D
D
7
D
6
PR4411
499R2F-2-GP
PC4431
SCD01U50V2KX- 1DLGP
20161031
20161031
3
PR4477
0R0402-PAD
2
L1SS355T1G-GP
PD4403_K
1 2
DCBATOUT
PR4436
1MR2J-1-GP
PD4404
PD4403_A
AK
PQ4408
MMBT3906-4-GP
84.T3906.A11
2nd = 84.03906.P11
680KR2F-GP
PR4475
AD+
PR4473
100KR2J-1-GP
12
12
DY
PQ4408_E
E
B
C
PQ4408_C
12
CHECK EE
follow custormer circuits.
H_PROCHO T# 4,24,44,46
PR4462
0R0402-PAD
0R2J-2-GP
PR4463
PR4476
0R0402-PAD
1 2
PQ4405_3
PQ4405_2
12
12
DY
PWR_CHG_ACOK
PQ4405
3 4
2
1
2N7002KDW -GP
84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
5
6
PR4450
10KR2F-2-GP
3D3V_S5
PQ4405_5
12
PC4438
SC1U10V2KX-1DLGP
PQ4405_6
12
PR4474
100KR2F-L1-GP
1 2
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
Taipei Hsie n 221, Taiwan, R.O. C.
Charger
Charger
Charger
KyloRen 13"
KyloRen 13"
KyloRen 13"
A00
A00
44 106Thursday, June 29, 2017
44 106Thursday, June 29, 2017
44 106Thursday, June 29, 2017
A00
B B
A A
PR4472
100KR2F-L3-GP
3D3V_S5
12
PWR_CH G_PROCH OT#_R
5
PU +VCCSTG = 1.0 V on CPU side
H_PROCHO T#4,24,44,46
PQ4416
6
2N7002KDW -GP
84.2N702.A3F
2nd = 75.00601.07C
2345
1
PR4435
100KR2F-L3-GP
3D3V_S5
12
SC1KP50V2KX-1D LGP
PWR_CH G_PROCH OT#
4
PC4433
12
DY
12
PWR_CH G_COMP_R
12
Page 45
5
4
3
2
1
SSID = PWR.Plane.Regulator_5V
3D3V_AUX_S5
12
PR4503
0R2J-2-GP
12
PC4519
SC10U25V5KX-DL-GP
PR4513
1MR2J-1-GP
PC4530
SCD1U25V2KX-GP
DY
PR4515
0R0402-PAD
1 2
PWR_5V_PG
PWR_5V_VCC
10
16
17
12
11
2
3
4
5
PU4502
IN#2
IN#3
IN#4
IN#5
NC#10
NC#16
VCC
EN1
EN2
PR4504
1 2
0R0402-PAD
PR4516
1 2
0R0402-PAD
GND7GND8GND
PWR_5V_EN1PWR_5V_EN1_R
PWR_3D3V_EN1
PG
BS
LX#6
LX#19
LX#20
OUT
FF
LDO
GND
SY8288CRAC-GP
18
21
PWR_5V_PG
9
1
PWR_5V_PH
6
19
20
Trace used 10 mil
PWR_5V_VOUT
14
PWR_5V_FB
13
PWR_5V_LDO
15
SC4D7U6D3V3KX-DLGP
5V_AUX_S5
DY
PR4502
1 2
0R0603-PAD
PC4526
SC1KP50V2KX-1DLGP
1 2
12
PC4520
PR4510
100KR2J-1-GP
12
1 2
PWR_5V_BOOT_APWR_5V_BOOT
PWR_5V_FB_A
PG4528
GAP-CLOSE-PWR-3-GP
1 2
20161226
3V_5V_POK
PG4529
GAP-CLOSE-PWR-3-GP
PC4521
SCD1U25V2KX-1-DL-GP
1 2
PR4507
1KR2F-3-GP
1 2
17,40,45,52,54
PWR_5V_FB
12
PR4551
348KR2F-GP
Cyntec. 6.95 x 6.4 x 2.4mm
DCR: 11.2~13.5mOhm
Idc : 9A , Isat : 16A
PL4502
COIL-1UH-57-GP
PG4527
GAP-CLOSE-PWR-3-GP
1 2
5V_AUX_S5
12
DY
12
PC4518
SCD1U16V2KX-3GP
12
PC4514
SC22U6D3V5MX-2DLGP
Design Current=7A
10.5A<OCP>12.6A
PWR_5V
12
PC4516
SC22U6D3V5MX-2DLGP
12
PC4517
SC22U6D3V5MX-2DLGP
DY
12
PC4527
DY
12
PC4515
SC22U6D3V5MX-2DLGP
2017/05/08
PWR_5V 5V_S5
12
12
SC22U6D3V5MX-2DLGP
PC4528
SCD1U25V2KX-1-DL-GP
PC4529
SC22U6D3V5MX-2DLGP
PG4522
GAP-CLOSE-PWR-3-GP
1 2
PG4523
GAP-CLOSE-PWR-3-GP
1 2
PG4524
GAP-CLOSE-PWR-3-GP
1 2
PG4525
GAP-CLOSE-PWR-3-GP
1 2
PG4512
GAP-CLOSE-PWR-3-GP
1 2
PG4511
GAP-CLOSE-PWR-3-GP
1 2
PG4510
GAP-CLOSE-PWR-3-GP
1 2
PG4513
GAP-CLOSE-PWR-3-GP
1 2
PR4530
0R2J-2-GP
DY
D D
PG4501
GAP-CLOSE-PWR-3-GP
1 2
PG4502
GAP-CLOSE-PWR-3-GP
1 2
PG4503
GAP-CLOSE-PWR-3-GP
1 2
PG4504
GAP-CLOSE-PWR-3-GP
1 2
PG4505
GAP-CLOSE-PWR-3-GP
1 2
PG4506
GAP-CLOSE-PWR-3-GP
1 2
EN rating 25V
EN Rising Threshold : 0.8V
Ilimt : 8A
C C
PWR_DCBATOUT_5VDCBATOUT
3V_5V_EN40
12
PC4524
SC2D2U10V3KX-1DLGP-U
DCBATOUT
PWR_DCBATOUT_5V
12
PC4522
SCD1U25V2KX-1-DL-GP
PWR_5V_EN1
PR4511
1KR2F-3-GP
1 2
PC4523
12
PR4512
200KR2F-L1-GP
SC10U25V5KX-DL-GP
12
DY
DY
12
PC4505
12
PC4531
SCD1U25V2KX-GP
20161226
12
SC10U25V5KX-DL-GP
DY
12
PWR_5V_EN
DY
12
SSID = PWR.Plane.Regulator_3D3V
B B
DCBATOUT
A A
EC4534
12
SC2D2U10V2KX-GP
DY
DCBATOUT PWR_DCBATOUT_3D3V
PG4515
GAP-CLOSE-PWR-3-GP
1 2
PG4516
GAP-CLOSE-PWR-3-GP
1 2
PG4517
GAP-CLOSE-PWR-3-GP
1 2
PG4518
GAP-CLOSE-PWR-3-GP
1 2
EN rating 25V
EN Rising Threshold : 0.8V
Ilimt : 8A
PWR_DCBATOUT_3D3V
PWR_3D3V_EN1
12
3D3V_AUX_S5
3V_5V_POK17,40,45,52,54
DY
PC4532
12
SCD1U25V2KX-GP
PC4501
SCD1U25V2KX-1-DL-GP
DCBATOUT
12
1 2
1 2
12
PC4502
PC4503
SC10U25V5KX-DL-GP
PR4509
1KR2F-3-GP
1 2
PR4505
100KR2J-1-GP
PG4531
GAP-CLOSE-PWR-3-GP
20161226
12
PC4504
DY
SC10U25V5KX-DL-GP
12
DY
SC10U25V5KX-DL-GP
12
PR4508
200KR2F-L1-GP
PR4514
1MR2J-1-GP
DY
PU4501
2
IN#2
3
IN#3
4
IN#4
5
IN#5
12
EN1
11
EN2
1
BS
9
PG
13
FF
14
OUT
17
LDO
SY8286BRAC-GP
PR4501
1 2
0R0603-PAD
LX#6
LX#19
LX#20
NC#10
NC#15
NC#16
GND
GND
GND
GND
6
19
20
10
15
16
7
8
18
21
PWR_3V_PG
PWR_3D3V_LDO
PWR_3D3V_BOOT PWR_3D3V_BOOT_A
PWR_3D3V_EN
PWR_3D3V_BOOT
PWR_3V_PG
PWR_3D3V_FB
PWR_3D3V_LDO
Trace used 10 mil
PWR_3D3V_VOUT
12
PC4508
SCD1U25V2KX-GP
PC4533
1 2
SC1KP50V2KX-1DLGP
PWR_3D3V_FB2
PC4506
SCD1U25V2KX-1-DL-GP
1 2
PWR_3D3V_PH
12
PC4507
SC4D7U6D3V3KX-DLGP
PL4501
IND-2D2UH-162-GP-U
2017/05/08
PG4519
GAP-CLOSE-PWR-3-GP
1 2
PR4506
1KR2F-3-GP
12
1 2
3D3V_AUX_S5
PG4530
GAP-CLOSE-PWR-3-GP
1 2
Cyntec. 6.95 x 6.4 x 2.4mm
DCR: 23~28mOhm
Idc : 7A , Isat : 14A
PC4513
12
12
SCD1U25V2KX-1-DL-GP
PC4509
SC22U6D3V5MX-2DLGP
12
Design Current=5A
7.5A<OCP>9A
PWR_3D3V
12
12
PC4510
SC22U6D3V5MX-2DLGP
12
PC4525
PC4511
SC22U6D3V5MX-2DLGP
SC22U6D3V5MX-2DLGP
DY
20161226
DY
PC4512
SC22U6D3V5MX-2DLGP
2017/05/08
PWR_3D3V 3D3V_S5
PG4526
GAP-CLOSE-PWR-3-GP
1 2
PG4520
GAP-CLOSE-PWR-3-GP
1 2
PG4521
GAP-CLOSE-PWR-3-GP
1 2
PG4509
GAP-CLOSE-PWR-3-GP
1 2
PG4508
GAP-CLOSE-PWR-3-GP
1 2
PG4507
GAP-CLOSE-PWR-3-GP
1 2
<Core Design>
<Core Design>
<Core Design>
RF request 2016/01/12 modify
5
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
A00
A00
45 106Thursday, June 29, 2017
45 106Thursday, June 29, 2017
45 106Thursday, June 29, 2017
A00
Page 46
5
Main Func = CPU_CORE
4
+VCCST_CPU
3
2
1
+VCCST_CPU
D D
20161229
U22:64.90925.6DL,U42:64.95325.6DL
20170307
C C
VCC_CORE
B B
PC4614 470p(78.47124.2FLDL)330P(78.33124.2FLDL)
PC4618
PC4625
PC4626
PR4669
PR4635
PR4642
A A
PC4630
PC4628
PC4654
PC4653
PR4633
PR4608
U22:78.33124.2FLDL,U42:78.47124.2FLDL
DY
PR4631
100R2F-L1-GP-U
12
PR4665
0R0402-PAD-1-GP
VCC_SENSE7
VSS_SENSE7
PWR_VCCGT_ISUMP48
PWR_VCCGT_ISUMN_P_2
PWR_VCCGT_ISUMN48
1 2
PR4666
0R0402-PAD-1-GP
1 2
DY
PR4639
100R2F-L1-GP-U
12
PC4622
SCD01U50V2KX-1DLGP
12
12
PR4641
2K61R2F-1-GP
PR4643
11KR2F-L-GP
12
PR4646
NTC-10K-26-GP-U
B=3370K
Place near Phase1
choke
U22 U42
1KP(78.10224.2FLDL) 470p(78.47124.2FLDL)
DY
DY
0.022u(78.22321.2FLDL)
0.022u(78.22321.2FLDL)
DY
1K(64.10015.6DL) DY
357(64.35705.6DL) 464 (64.46405.6DL)
47nF(078.47322.02FD) 47nF(078.47322.02FD)
22nF(78.22321.2FLDL)
22nF(78.22321.2FLDL)
10nF(78.10324.2FLDL) 10nF(78.10324.2FLDL)
DY
1.54K(64.15415.6DL)
90.9K(64.90925.6DL)
47nF(078.47322.02FD)
3.01K(64.30115.6DL)
95.3K (64.95325.6DL)
5
PR4608
90K9R2F-GP
1 2
PC4604
SC330P50V2KX-3-DL-GP
1 2
B=3940K Place near high side MOSFET of
Phase1
PR4617
NTC-470K-8-GP-U
12
PR4621
27K4R2F-GP
1 2
12
PC4651
12
12
SC1KP50V2KX-1DLGP
PC4612
SC2200P50V2KX-2DLGP
PWR_VCCGT_COMP1
12
PC4614
SC330P50V2KX-3-DL-GP
DY
PC4615
SCD01U50V2KX-L-GP
DY
PC4619
SC1KP50V2KX-L-1-GP
PWR_VCCGT_FB1
12
20170307
PWR_VCCGT_FB2
20161031
PC4654
SCD01U50V2KX-1DLGP
12
12
12
2 1
1 2
PC4633
SCD1U25V2KX-1-DL-GP
DY
12
PC4628
PC4653
SCD022U16V2KX-3DLGP
U42
PWR_VCCGT_ISUMN_P_1
PR4647
0R0402-PAD-1-GP
2017/04/25
2017/02/21
2017/06/06
2017/04/25
PWR_VCCGT_NTC1
PR4630
2KR2F-L1-GP
1 2
U22:64.15415.6DL,U42:64.30115.6DL
PR4633
1K54R2F-GP
1 2
PC4618
SC1KP50V2KX-1DLGP
PWR_VCCGT_FB_RC
12
U22:78.10224.2FLDL,U42:78.47124.2FLDL
1 2
SCD047U25V2KX-4-GP
12
PC4630
SCD047U25V2KX-4-GP
PWR_VCCGT_ISUMN_RC
12
PWR_VCCGT_FCCM#48
PWR_VCCGT_PWMA48
PWR_VCCGT_PWMB48
PWR_VCCGT_ISEN148
PWR_VCCGT_ISEN248
20170307
H_PROCHOT#4,24,44
PR4616
10KR2F-L1-GP
12
PC4610
SC33P50V2JN-3DLGP
1 2
PR4626
3K3R2F-2-GP
1 2
PR4636
499R2F-2-GP
1 2
PC4623
SC2200P50V2KX-2DLGP
12
PR4642
357R2F-GP
U22:64.35705.6DL,U42:64.46405.6DL
PR4645
1KR2F-L1-GP
20161027
12
PC4638
SC330P50V2KX-3-DL-GP
PR4669
0R2J-L-GP
DY
1 2
2017/02/21
12
PR4661
88K7R2F-GP
4
2016/12/20
U42
PR4655
1 2
2 1
12
23K2R2F-GP
5V_S5
12
PR4635
1KR2F-3-GP
U22
12
PR4662
10KR2F-L1-GP
PWR_VCORE_NTC1
20170307
12
PR4654
NTC-470K-8-GP-U
Place near high side MOSFET of
Phase1
B=3940K
DY
12
PR4603
1KR2F-3-GP
10KR2F-L1-GP
1
TP4601
TPAD14-OP-GP
VR_EN40
DY
PR4614
0R2J-L-GP
12
PWR_VCCGT_IMON
PWR_VCCGT_NTC
PWR_VCCGT_COMP
PWR_VCCGT_FB
PWR_VCCGT_RTN
PWR_VCCGT_ISUMP
PWR_VCCGT_ISUMNB
PWR_VCCGT_ISEN1
PWR_VCCGT_ISEN2
PC4625
PC4626
SCD022U16V2KX-3DLGP
SCD022U16V2KX-3DLGP
U42
2 1
PR4656
2K87R2F-1-GP
12
PWR_VCORE_COMP1
PC4639
SC33P50V2JN-3DLGP
12
PC4640
SC2200P50V2KX-2DLGP
PR4607
100R2F-L3-GP
1 2
3D3V_S0
PR4609
VR_RDY
PSYS
10
41
12
PR4657
2KR2F-L1-GP
PWR_VCORE_FB1
12
PC4641
SC330P50V2KX-3-DL-GP
20170307
12
DY
1
2
3
4
5
6
7
8
9
PU4601
PSYS
IMON_B
NTC_B
COMP_B
FB_B
RTN_B
ISUMP_B
ISUMN_B
ISEN1_B
ISEN2_B
GND
12
PWR_VCORE_FB2
PR4660
1K91R2F-1-GP
PR4606 45D3R2F-L-GP
PR4605 75R2F-2-GP
PR4604 100R2F-L3-GP
12
12
12
12
DY
PR4623 0R0402-PAD-1-GP
PR4624 49D9R2F-L1-GP
PR4622 10R2F-L1-GP
12
12
12
PWR_VCORE_SCLK
PWR_VCORE_SDIO
PWR_VCORE_ALERT#
PWR_VCORE_VRHOT#
PWR_VCORE_VCC
PWR_VCORE_VIN
33
34
35
36
38
39
40
37
SDA
VCC
SCLK
ALERT#
VR_HOT#
VR_READY
VR_ENABLE
FCCM_B11PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A16FB_A17RTN_A18ISUMP_A19ISUMN_A
PWR_VCORE_IMON
PWR_VCORE_COMP
PWR_VCORE_FB
PWR_VCORE_NTC
PWR_VCORE_RTN
12
PR4658
499R2F-2-GP
PWR_VCORE_FB_RC
12
12
PC4643
SC1KP50V2KX-1DLGP
PC4602
SCD1U25V2KX-1-DL-GP
VR_SVID_CLK 7
VR_SVID_DATA 7
DCBATOUT
PWR_VCORE_PROG1
PWR_VCORE_PROG2
32
VIN
PROG231PROG1
PWM_C
FCCM_C
ISUMN_C
ISUMP_C
RTN_C
FB_C
COMP_C
IMON_C
PWM_A
FCCM_A
ISL95859AHRTZ-T-GP
20
074.95859.0B33
PWR_VCORE_ISUMNA
PWR_VCORE_ISUMP
PC4632
SC2200P50V2KX-2DLGP
PWR_VCORE_ISUMN_RC
12
PC4637
SCD01U50V2KX-1DLGP
1 2
PR4659
100R2F-L1-GP-U
12
DY
DY
PC4642
SC1KP50V2KX-L-1-GP
DY
PR4663
100R2F-L1-GP-U
12
3
VR_SVID_ALERT# 7
5V_S5
12
12
12
12
30
29
28
27
26
25
24
23
22
21
PR4610
PR4612
1R2J-GP
0R0402-PAD-1-GP
PC4606
SCD22U25V3KX-DL-GP
12
PC4607
SC1U10V2KX-1DLGP
12
PR4628
PR4629
9K31R2F-GP
88K7R2F-GP
PWR_VCCSA_ISUMNB
PWR_VCCSA_ISUMP
PWR_VCCSA_RTN
PWR_VCCSA_FB
PWR_VCCSA_COMP
PWR_VCCSA_IMON
PR4648
357R2F-GP
1 2
PR4668
0R0402-PAD-1-GP
PR4667
0R0402-PAD-1-GP
DY
PC4644
SCD01U50V2KX-L-GP
1 2
PWR_VCCSA_PWM 50
PWR_VCCSA_FCCM 50
PR4651
1KR2F-L1-GP
1 2
SCD047U25V2KX-4-GP
PC4634
12
12
+VCCGT
PWR_VCORE_PWM 47
PWR_VCORE_FCCM# 47
12
PC4631
SCD1U25V2KX-1-DL-GP
PWR_VCORE_ISUMN_P_1
12
VSSGT_SENSE 7
VCCGT_SENSE 7
20161229
12
PR4620
464R2F-GP
PC4652
SCD022U16V2KX-3DLGP
2 1
PR4632
301R2F-GP
PR4640
2K49R2F-2-L-GP
1 2
PR4649
1 2
12
DY
12
PR4615
1KR2F-3-GP
PWR_VCCSA_ISUMN_RC
DY
PC4611
SC2K2P50V2KX-L-GP
1 2
PWR_VCCSA_FB_RC
12
0R0402-PAD-1-GP
1 2
PC4635
SCD01U50V2KX-1DLGP
2
20161031
PC4605
12
SCD047U25V2KX-4-GP
PC4617
SC1KP50V2KX-1DLGP
1 2
PR4637
1K69R2F-2-GP
1 2
DY
PR4638
2KR2F-L1-GP
PR4652
PWR_VCCSA_FB1
12
PWR_VCCSA_COMP_RC
PC4624
SC33P50V2JN-3DLGP
1 2
12
PR4650
NTC-10K-26-GP-U
11KR2F-L-GP
B=3370K
Place near Phase1
choke
PR4653
2K61R2F-1-GP
1 2
DY
12
PR4613
0R2J-L-GP
PWR_VCCSA_ISUMN_P_1
20161031
21
PC4608
SCD022U16V2KX-3DLGP
PWR_VCCSA_FB2
PC4601
SC2200P50V2KX-2DLGP
1 2
PR4644
1 2
113KR2F-1-GP
PWR_VCORE_ISUMN 47
PWR_VCORE_ISUMN_P_2
PWR_VCORE_ISUMP 47
12
1 2
DY
PR4627
100R2F-L1-GP-U
DY
12
PC4616
SC1KP50V2KX-L-1-GP
DY
12
PC4620
SCD01U50V2KX-L-GP
DY
PC4621
SC680P50V2KX-2GP
12
12
20170307
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PC4629
SC330P50V2KX-3-DL-GP
PC4603
SCD1U25V2KX-1-DL-GP
PWR_VCCSA_ISUMN 50
12
PR4611
NTC-10K-26-GP-U
B=3370K
Place near Phase1
PR4618
choke
11KR2F-L-GP
A2
A2
A2
PWR_VCCSA_ISUMN_P_2
PR4625
2K61R2F-1-GP
1 2
PC4613
SCD01U50V2KX-1DLGP
1 2
12
NCP81208MN_CPU_VCORE(1/3)
NCP81208MN_CPU_VCORE(1/3)
NCP81208MN_CPU_VCORE(1/3)
PWR_VCCSA_ISUMP 50
PR4602
0R0402-PAD-1-GP
1 2
PR4601
0R0402-PAD-1-GP
1 2
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
VSSSA_SENSE 7
VCCSA_SENSE 7
46 106Thursday, June 29, 2017
46 106Thursday, June 29, 2017
46 106Thursday, June 29, 2017
A00
A00
A00
Page 47
5
SSID = CPU_CORE
4
3
2
1
PWR_DCBATOUT_VCOREDCBATOUT
D D
C C
PWR_VCORE_FCCM#46
SC1U10V2KX-1DLGP
B B
PC4708
PG4701
1 2
GAP-CLOSE-PWR-3-GP
PG4702
1 2
GAP-CLOSE-PWR-3-GP
PG4703
1 2
GAP-CLOSE-PWR-3-GP
PG4704
1 2
GAP-CLOSE-PWR-3-GP
PG4705
1 2
GAP-CLOSE-PWR-3-GP
PG4706
1 2
GAP-CLOSE-PWR-3-GP
PR4706
0R0402-PAD-1-GP
5V_S5
PR4704
2D2R2F-GP
1 2
12
12
PWR_VCORE_FCCM#_R
PWR_VCORE_VCC_R
PWR_VCORE_SW
PWR_DCBATOUT_VCORE
PC4701
12
PU4701
1
SKIP#
2
VDD
3
PGND
4
VSW
CSD97396Q4M-GP
12
SC10U25V5KX-DL-GP
074.97396.0043
PC4702
SC10U25V5KX-DL-GP
PWM
BOOT
BOOT_R
VIN
PGND
PC4703
12
12
SC10U25V5KX-DL-GP
PWR_VCORE_PWM_R
8
PWR_VCORE_BOOT
7
PWR_VCORE_BOOTR
6
5
9
PC4704
SC10U25V5KX-DL-GP
PWR_DCBATOUT_VCORE
PR4702
0R0402-PAD-1-GP
1 2
12
PR4712
5K11R2F-L1-GP
PWR_VCORE_PWM 46
PWR_VCORE_BOOT_RC
12
PR4705
2D2R3F-L-GP
12
12
PR4703
2D2R6J-3-GP
DY
PWR_VCORE_SNB
12
PC4706
SC1KP50V2KX-L-1-GP
DY
PC4707
SCD22U25V3KX-DL-GP
Cyntec. 6.8mm x7.6mmx2.4mm
DCR: 0.92m Ohm +/- 7%
Idc : 32A , Isat : 41A
PL4701
1 2
COIL-D15UH-8-GP
PG4707
GAP-CLOSE-PWR-3-GP
1 2
PWR_VCORE_ISUMP_G PWR_VCORE_ISUMN_G
PG4708
GAP-CLOSE-PWR-3-GP
1 2
SKL_U22_15W
Icc(max)=29A
TDC=21A
Confirm with EE
22uF/0805 total 33pcs
(78.22610.L2L)
+VCCGT
12
PT4701
SE330U2VDM-4-GP
PANASONIC
ESR: 9 mohm
12
PR4708
3K65R2F-1-GP
PWR_VCORE_ISUMP46
PWR_VCORE_ISUMN46
A A
5
4
3
2
12
PR4701
0R0402-PAD-1-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
NCP81382MN_CPU_VCORE(2/3)
NCP81382MN_CPU_VCORE(2/3)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
NCP81382MN_CPU_VCORE(2/3)
KyloRen 13"
KyloRen 13"
KyloRen 13"
47 106Thursday, June 29, 2017
47 106Thursday, June 29, 2017
47 106Thursday, June 29, 2017
1
A00
A00
A00
Page 48
5
Main Func = CPU_CORE
4
3
2
1
DCBATOUT
PG4802 GAP-CLOSE-PWR-3-GP
PG4803 GAP-CLOSE-PWR-3-GP
D D
PG4804 GAP-CLOSE-PWR-3-GP
PG4805 GAP-CLOSE-PWR-3-GP
PG4806 GAP-CLOSE-PWR-3-GP
C C
PWR_DCBATOUT_VCCGTA
12
12
12
12
12
PWR_VCCGT_FCCM#46,48
PWR_DCBATOUT_VCCGTA
PC4802
SC10U25V5KX-DL-GP
PR4806
0R0402-PAD-1-GP
PR4803
2D2R2F-GP
PC4809
12
PC4803
SC10U25V5KX-DL-GP
5V_S5
12
SC1U10V2KX-1DLGP
PC4804
12
PC4805
12
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
KBL_U42_15W
Icc(max)=64A
2016/12/29 DY
DCBATOUT
12
DY
PT4805
SE33U25VM-11-GP
12
DY
PT4806
SE33U25VM-11-GP
TDC=42A
PR4802
0R0402-PAD-1-GP
12
1 2
12
PWR_VCCGT_FCCM#_RA
PWR_VCCGT_VCCDA
PWR_VCCGT_SWA
PU4801
1
SKIP#
2
VDD
3
PGND
4
VSW
CSD97396Q4M-GP
PWM
BOOT
BOOT_R
VIN
PGND
8
7
6
5
9
1 2
PWR_VCCGT_PWMA_RA
PWR_VCCGT_BOOTA
PWR_VCCGT_BOOTRA
PWR_DCBATOUT_VCCGTA
074.97396.0043
PWR_VCCGT_PWMA 46
12
PR4817
5K11R2F-L1-GP
PWR_VCCGT_BOOTA_RC
12
PR4804
2D2R3-1-U-GP
12
PC4808
SCD22U25V3KX-DL-GP
12
PR4805
DY
2D2R6J-3-GP
PWR_VCCGT_SNB1
12
PC4810
SC1KP50V2KX-L-1-GP
DY
Cyntec. 6.8mm x7.6mmx2.4mm
DCR: 0.92m Ohm +/- 7%
Idc : 32A , Isat : 41A
1 2
PWR_VCCGT_ISUMP_GA
PL4801
1 2
COIL-D15UH-8-GP
PG4808
GAP-CLOSE-PWR-3-GP
Confirm with EE
22uF/0805 total 36pcs
(78.22610.L2L)
PG4809
GAP-CLOSE-PWR-3-GP
1 2
PWR_VCCGT_ISUMN_GA
VCC_CORE
12
PT4801
SE330U2VDM-4-GP
PANASONIC
ESR: 9 mohm
For acoustic noise
1 2
PWR_VCCGT_ISEN146,48
PWR_VCCGT_ISUMP46,48
PWR_VCCGT_ISUMN46,48
DCBATOUT PWR_DCBATOUT_VCCGTBPWR_DCBATOUT_VCCGTB
PG4810 GAP-CLOSE-PWR-3-GP
PG4816 GAP-CLOSE-PWR-3-GP
PG4811 GAP-CLOSE-PWR-3-GP
PG4812 GAP-CLOSE-PWR-3-GP
B B
PG4814 GAP-CLOSE-PWR-3-GP
12
12
12
12
12
PWR_VCCGT_FCCM#46,48
12
U42
SC1U10V2KX-1DLGP
PC4814
SC10U25V5KX-DL-GP
PR4813
2D2R2F-GP
PC4812
PC4815
12
SC10U25V5KX-DL-GP
U42
U42
PR4812
0R0402-PAD-1-GP
12
5V_S5
U42
1 2
12
U42
12
PC4816
SC10U25V5KX-DL-GP
12
U42
PC4817
SC10U25V5KX-DL-GP
PWR_VCCGT_FCCM#_RB
PWR_VCCGT_VCCDB
PWR_VCCGT_SWB
PU4802
1
SKIP#
2
VDD
3
PGND
4
U42
VSW
CSD97396Q4M-GP
PWM
BOOT
BOOT_R
PGND
8
7
6
5
VIN
9
PR4811
0R0402-PAD-1-GP
1 2
12
PR4818
U42
5K11R2F-L1-GP
PWR_VCCGT_PWMB_RA
PWR_VCCGT_BOOTB
PWR_VCCGT_BOOTRB
PWR_DCBATOUT_VCCGTB
PWR_VCCGT_PWMB 46
PWR_VCCGT_ISEN246,48
PWR_VCCGT_BOOTB_RC
12
PR4810
U42
2D2R3-1-U-GP
12
PC4811
SCD22U25V3KX-DL-GP
U42
074.97396.0043
A A
5
4
PWR_VCCGT_ISEN246,48
PWR_VCCGT_ISUMP46,48
PWR_VCCGT_ISUMN46,48
PWR_VCCGT_ISEN146,48
3
U42
PR4821
100KR2F-L1-GP
1 2
PR4808
3K65R2F-1-GP
12
PR4814
DY
2D2R6J-3-GP
PWR_VCCGT_SNB2
12
PC4813
SC1KP50V2KX-L-1-GP
DY
1 2
U42
PR4823
100KR2F-L1-GP
1 2
U42
PR4816
3K65R2F-1-GP
12
Cyntec. 6.8mm x7.6mmx2.4mm
DCR: 0.92m Ohm +/- 7%
Idc : 32A , Isat : 41A
1 2
PWR_VCCGT_ISUMP_GB
PL4802
1 2
U42
COIL-D15UH-8-GP
PG4813
GAP-CLOSE-PWR-3-GP
1 2
PWR_VCCGT_ISUMN_GB
12
U42
2
PR4809
10R2F-L1-GP
PG4815
GAP-CLOSE-PWR-3-GP
PR4815
10R2F-L1-GP
12
PR4822
100KR2F-L1-GP
DY
12
PR4824
100KR2F-L1-GP
DY
VCC_CORE
20161031
12
U42
PT4803
SE330U2VDM-4-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
NCP81382MN_CPU_VCCGT(3/3)
NCP81382MN_CPU_VCCGT(3/3)
NCP81382MN_CPU_VCCGT(3/3)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
48 106Thursday, June 29, 2017
48 106Thursday, June 29, 2017
48 106Thursday, June 29, 2017
A00
A00
A00
Page 49
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
NCP81210MN_CPU_VCCGTUS
NCP81210MN_CPU_VCCGTUS
NCP81210MN_CPU_VCCGTUS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
49 106Thursday, June 29, 2017
49 106Thursday, June 29, 2017
49 106Thursday, June 29, 2017
1
Page 50
5
SSID = CPU_CORE
4
3
2
1
PWR_DCBATOUT_VCCSA
1
AFTP5001
2016/12/14 remove PT5001
2017/03/16
D D
DCBATOUT
PG5002
GAP-CLOSE-PWR-3-GP
PWR_DCBATOUT_VCCSA
12
SKL_U22_15W
PG5003
GAP-CLOSE-PWR-3-GP
12
Icc(max)=4.5A
TDC=3.7A
Confirm with EE
22uF/0805 total 6pcs
(78.22610.L2L)
PWR_DCBATOUT_VCCSA
12
PC5002
SC10U25V5KX-DL-GP
678
PU5002
C C
PWR_VCCSA_BST_RC
AON7410-GP
DDD
12
PC5003
SC10U25V5KX-DL-GP
12
PC5004
SCD1U25V2KX-1-DL-GP
SSS
12
PR5001
2D2R3F-L-GP
PU5001
PWR_VCCSA_DRVH
PWR_VCCSA_BST
PWR_VCCSA_PWM46
1
UGATE
2
BOOT
3
PWM
4
GND
ISL95808HRZ-T-1-GP
PHASE
FCCM
VCC
LGATE
GND
PWR_VCCSA_SW
8
7
6
5
9
074.95808.0B73
12
PC5005
SCD22U25V3KX-DL-GP
5V_S5
12
PC5001
SC2D2U10V3KX-1DLGP-U
PWR_VCCSA_FCCM 46
AON7410-GP
PU5003
GD
4 5
GD
4 5
678
DDD
Cyntec. 7.3mm x6.8mm x2.4mm
123
SSS
123
DCR: 4.5~5.1 mohm
Idc : 15A , Isat : 22A
PL5001
1 2
COIL-D47UH-20-GP
PG5011
GAP-CLOSE-PWR-3-GP
1 2
PWR_VCCSA_ISUMP_R
2017/05/10
+VCCSA
PG5001
GAP-CLOSE-PWR-3-GP
1 2
PWR_VCCSA_ISUMN_R
If no need support PS4 mode
B B
please change to ISL6208C
PWR_VCCSA_DRVL
74.06208.B73
12
PR5003
3K65R2F-1-GP
PWR_VCCSA_ISUMP46
12
PR5004
0R0402-PAD-1-GP
PWR_VCCSA_ISUMN46
<Core Design>
<Core Design>
A A
5
4
3
2
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
VCCSA
VCCSA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
VCCSA
KyloRen 13"
KyloRen 13"
KyloRen 13"
50 106Thursday, June 29, 2017
50 106Thursday, June 29, 2017
50 106Thursday, June 29, 2017
1
A00
A00
A00
Page 51
5
SSID = PWR.Plane.Regulator_1D2V/0D6V
4
3
2
1
1 2
1 2
SC10U25V5KX-DL-GP
DY
PWR_DCBATOUT_VDDQ
12
PC5115
SC10U25V5KX-DL-GP
12
DY
PWR_VDDQ_VCC
12
PC5112
SC2D2U10V3KX-1DLGP-U
PR5103
0R2J-2-GP
1 2
DY
PR5106
DY
0R2J-2-GP
1 2
ILIM LOW , ILIM=10A
ILIM FLOAT , ILIM=12A
ILIM HIGH , ILIM=16A
PWR_VDDQ_VCC
PWR_VDDQ_BOOT
PWR_VDDQ_PG
PWR_VDDQ_EN
PWR_VDDQ_ILMT
3D3V_S5
SC1U10V2KX-1DLGP
PWR_VDDQ_FB
PC5110
PWR_VDDQ_VCC
SY8288RAC for 1D2V
PR5102
0R0603-PAD-1-GP-U
1 2
PU5101
17
VCC
2
IN#2
3
IN#3
4
IN#4
5
IN#5
1
BS
9
PG
11
EN
13
ILMT
14
FB
15
12
BYP
SY8288RAC-GP
074.08288.0043
LX#6
LX#19
LX#20
NC#10
NC#12
NC#16
GND
GND
GND
GND
PWR_VDDQ_BOOT_APWR_VDDQ_BOOT
6
19
20
10
12
16
7
8
18
21
PWR_VDDQ_PH
PWR_VDDQ_PG
PWR_VDDQ_VCC
PC5114
SCD1U25V2KX-1-DL-GP
1 2
SC470P50V2KX-3DLGP
Cyntec 6.86 x 6.47 x 2.4mm
DCR: 11.2~13.5mOhm
Idc :9A, Isat : 16A
PL5101
COIL-1UH-57-GP
1 2
GAP-CLOSE-PWR-3-GP
PC5113
Vout=0.6*(1+R1/R2)
=0.6*(1+20/20)
=1.2V
PG5113
PWR_VDDQ_FB_A
12
R1
R2
1 2
12
PR5107
20KR2F-L-GP
12
PR5101
20KR2F-L-GP
12
PC5104
SC22U6D3V5MX-2DLGP
Design Current=6A
7.8A < OCP < 10.4A
PC5105
12
12
SC22U6D3V5MX-2DLGP
1D2V_S3
PC5107
SC22U6D3V5MX-2DLGP
12
PC5109
SC22U6D3V5MX-2DLGP
2017/05/09
DCBATOUT
PG5105
D D
PWR_DCBATOUT_VDDQ
20160631 double pull high to DY
3D3V_S5
C C
1D2V_VTT_PWRGD40
GAP-CLOSE-PWR-3-GP
PG5110
GAP-CLOSE-PWR-3-GP
12
12
PC5116
PC5111
SCD1U25V2KX-1-DL-GP
PR5104
100KR2J-1-GP
1 2
DY
PG5114
GAP-CLOSE-PWR-3-GP
1 2
EE needs check it!!
PG5112
GAP-CLOSE-PWR-3-GP
PWR_2D5V_PG51,54
1 2
EE needs check it!!
PR5105
1MR2J-1-GP
EN rating 23V
EN Rising Threshold : 0.8V
20160614 modify to DY
B B
APL5338 for 0D6V
20161027
DDR_VREF_S3
PR5126
1 2
SIO_SLP_S3#17,24,40
SM_PGCNTL_R5
PWR_2D5V_PG51,54
A A
EE needs check it!!
5
4
DY
0R2J-2-GP
1 2
PR5125
0R0402-PAD
1 2
PR5114
0R0402-PAD
5V_S5
PR5118
0R0402-PAD
PWR_0D6V_S3EN
PWR_0D6V_S5EN
PWR_0D6V_VCNTL
12
12
PC5121
SC1U10V2KX-1DLGP
12
PC5123
SCD1U25V2KX-1-DL-GP
12
12
PC5119
DY
SCD1U16V2KX-3GP
DY
3
PC5120
SCD1U16V2KX-3GP
PU5102
6
VTTREF
7
S3
8
GND
9
S5
10
VCNTL
APL5338XAI-TRG-GP
74.05338.079
11
GND
VTTSEN
PGND
VREF
VTT
VIN
1D2V_S3
5
4
3
2
1
2017/05/09
PC5118
SCD1U25V2KX-1-DL-GP
12
0D6V_PW R
PC5122
SC10U6D3V3MX-DL-GP
12
12
PC5124
SC22U6D3V5MX-2DLGP
Design Current = 1470mA
2017/05/08
0D6V_PW R
PG5115
GAP-CLOSE-PWR-3-GP
1 2
PG5116
GAP-CLOSE-PWR-3-GP
1 2
2
0D6V_S0
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
51 106Thursday, June 29, 2017
51 106Thursday, June 29, 2017
51 106Thursday, June 29, 2017
A00
A00
A00
Page 52
5
SSID = PWR.Plane.Regulator_1D0V
4
3
2
1
2016/12/16
1D0V_PWR
PG5201
1 2
GAP-CLOSE-PWR-3-GP
PG5202
D D
C C
PWR_DCBATOUT_1D0V
DCBATOUT
PC5214 SCD1U50V3KX-DL-GP
12
PG5214
GAP-CLOSE-PWR-3-GP
1 2
PG5210
GAP-CLOSE-PWR-3-GP
1 2
PG5212
GAP-CLOSE-PWR-3-GP
1 2
PC5216 SC10U25V5KX-DL-GP
12
DY
PWR_DCBATOUT_1D0V
PC5211 SC10U25V5KX-DL-GP
12
12
DY
AOZ2262 for 1D0V
5V_S5
12
PC5202
SC1U10V2KX-1DLGP
PU5201
21
VCC
7
IN#7
PC5210 SC10U25V5KX-DL-GP
PC5209 SC10U25V5KX-DL-GP
12
PR5201
88K7R2F-GP
1 2
12
PR5203
100KR2F-L1-GP
PWR_1D0V_TON
PWR_1D0V_PG
PWR_1D0V_EN
PWR_1D0V_PFM
PWR_1D0V_SS
12
PC5213
SCD01U50V2KX-1DLGP
8
IN#8
9
IN#9
6
TON
1
PGOOD
2
EN
3
PFM#
22
SS
AOZ2262QI-10-GP-U
074.02262.0043
LX#18
LX#17
LX#16
LX#11
LX#10
BST
AGND
PGND
PGND
PGND
PGND
PGND
FB
PWR_1D0V_PH
18
17
16
11
10
PWR_1D0V_BT
20
PWR_1D0V_FB
5
4
19
14
13
12
15
PC5204
SCD1U25V2KX-1-DL-GP
1 2
Cyntec 7*7*2.4
DCR: 4.5m~5.1mOhm
Idc : 15 A , Isat : 22A
PL5201
1 2
COIL-D47UH-20-GP
GAP-CLOSE-PWR-6-GP
PG5223
PR5202
2K55R2F-GP
1 2
PWR_1D0V_FB_A
12
R1
12
PC5212
SC220P50V2KX-3DLGP
12
Design Current : 9A
11.25A<OCP>13.5A
PC5203
SC22U6D3V3MX-1-DL-GP
12
PC5205
PC5201
12
SC22U6D3V3MX-1-DL-GP
1D0V_PWR
PC5206
12
SC22U6D3V3MX-1-DL-GP
DY
PC5208
12
SC22U6D3V3MX-1-DL-GP
SCD1U25V2KX-1-DL-GP
DY
1 2
GAP-CLOSE-PWR-3-GP
PG5203
1 2
GAP-CLOSE-PWR-3-GP
PG5204
1 2
GAP-CLOSE-PWR-3-GP
PG5205
1 2
GAP-CLOSE-PWR-3-GP
PG5206
1 2
GAP-CLOSE-PWR-3-GP
PG5207
1 2
GAP-CLOSE-PWR-3-GP
PG5208
1 2
GAP-CLOSE-PWR-3-GP
PG5209
1 2
GAP-CLOSE-PWR-3-GP
PG5211
1 2
GAP-CLOSE-PWR-3-GP
1D0V_S5
B B
PR5204
10KR2F-2-GP
12
R2
20170307
Vo=0.8x(1+R1/R2)
=0.8x(1+2.55/10)
3D3V_S5
PR5208
100KR2J-1-GP
PR5209
PR5210
1 2
1 2
2017/03/02
1D0V_S5_PWRGD40
3V_5V_POK17,40,45,54
0R0402-PAD
0R0402-PAD
2016/11/25 modify power sequence
A A
5
PWR_1D0V_PG
PWR_1D0V_EN
12
PC5215
SCD1U16V2KX-3GP
DY
4
1 2
3
=1.004V
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
52 106Thursday, June 29, 2017
52 106Thursday, June 29, 2017
52 106Thursday, June 29, 2017
1
A00
A00
A00
Page 53
A
4 4
B
C
D
E
3 3
(Blanking)
2 2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
1 1
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
A
B
C
Date: Sheet of
D
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
53 106Thursday, June 29, 2017
53 106Thursday, June 29, 2017
53 106Thursday, June 29, 2017
E
Page 54
5
SSID = 2D5V/ 1D8V
4
3
2
1
2017/05/08
APL5930 for 2D5V
D D
3D3V_S5
12
PR5410
10KR2F-2-GP
PWR_2D5V_PG51
SIO_SLP_S4#17,40
1 2
PR5417 0R0402-PAD
2016/12/30
C C
20161214
PWR_2D5V_EN PWR_2D5V_FB
47KR2J-2-GP
12
DY
PR5409
5V_S5
PC5410
12
SC1U10V2KX-1DLGP
SCD1U25V2KX-1-DL-GP
12
DY
PC5427
20161027
3D3V_S5
20161214
12
PC5414
SC10U6D3V3MX-DL-GP
PU5403
5
VIN#5
GND
FB
4
3
2
1
6
VCNTL
7
POK
8
EN
9
VIN#9
APL5930KAI-TRG-GP
VOUT#4
VOUT#3
74.05930.03D
2ND = 74.G9731.03D
Vout=0.8V*(R1+R2)/R2
PR5419
R1
R2
29K4R2F-GP
12
12
PWR_2D5V 2D5V_S3
PG5401
GAP-CLOSE-PWR-3-GP
1 2
PG5402
GAP-CLOSE-PWR-3-GP
1 2
Design current = 700mA
PWR_2D5V
20161027
PC5411
SC68P50V2JN-1GP
DY
PR5420
13K7R2F-GP
12
12
PC5413
SC10U25V5KX-DL-GP
DY
12
PC5412
SC22U6D3V5MX-2GP
2017/05/08
1D8V_PWR +V1.8A
APL5930 for 1D8V_S5
5V_S5
20161214
3D3V_S5
PC5401
3D3V_S5
12
B B
2017/01/24
PR5408
PRIM_PWRGD24,40
3V_5V_POK17,40,45,52
1 2
0R0402-PAD
PR5406
1 2
0R0402-PAD
2017/03/02
PR5402
100KR2F-L1-GP
PH at Page40
DY
PR5401
47KR2J-2-GP
12
SC1U10V2KX-1DLGP
PWR_1D8V_POK
PWR_1D8V_EN
12
DY
12
DY
PC5406
20161214
12
PC5403
SC10U6D3V3MX-DL-GP
PU5401
5
VIN#5
FB
GND
4
3
2
1
PR5403
12
16K5R2F-2-GP
R1
1.8V_RUN_FB
12
PR5404
R2
13K3R2F-L1-GP
6
VCNTL
7
POK
8
EN
9
VIN#9
APL5930KAI-TRG-GP
VOUT#4
VOUT#3
74.05930.03D
SC4700P50V2KX-1GP
2ND = 74.G9731.03D
Design Current = 770mA
1D8V_PWR
PC5405
SC68P50V2JN-1GP
12
DY
DY
12
PC5404
SC22U6D3V5MX-2GP
12
PC5402
SC10U25V5KX-DL-GP
20161027
PG5403
GAP-CLOSE-PWR-3-GP
1 2
PG5404
GAP-CLOSE-PWR-3-GP
1 2
PG5405
GAP-CLOSE-PWR-3-GP
1 2
Vout=0.8V*(R1+R2)/R2
<Core Design>
<Core Design>
A A
5
4
3
2
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
54 106Thursday, June 29, 2017
54 106Thursday, June 29, 2017
54 106Thursday, June 29, 2017
1
A00
A00
A00
Page 55
5
4
3
2
1
SSID = LCD
Hi:2.0V
Panel / Camera/ DMIC
LCD1
51
53
1
D D
C C
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
54
52
IPEX-CON50-1-GP
DBC_EN_R
EDP_AUX
EDP_AUX#
LCD_TST_C
EDP_TX3#
EDP_TX3
EDP_TX2#
EDP_TX2
EDP_TX1#
EDP_TX1
EDP_TX0#
EDP_TX0
EDP_HPD_CONN
LCD_BRIGHTNESS
BLON_OUT_C
Camera
IR_CAMERA_DET#_R
R5503 0R0402-PAD
C5510 SCD1U25V2KX-1-DL-GP
C5511 SCD1U25V2KX-1-DL-GP
C5532 SCD1U25V2KX-1-DL-GP
C5531 SCD1U25V2KX-1-DL-GP
C5533 SCD1U25V2KX-1-DL-GP
C5519 SCD1U25V2KX-1-DL-GP
C5501 SCD1U25V2KX-1-DL-GP
C5504 SCD1U25V2KX-1-DL-GP
C5506 SCD1U25V2KX-1-DL-GP
C5509 SCD1U25V2KX-1-DL-GP
DCBATOUT_LCD
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
LCDVDD
1 2
R9937 0R0402-PAD
2016/11/4
DBC_PANEL_EN 20
EDP_AUX_DP 8
EDP_AUX_DN 8
EDP_TX3_DN 8
EDP_TX3_DP 8
EDP_TX2_DN 8
EDP_TX2_DP 8
EDP_TX1_DN 8
EDP_TX1_DP 8
EDP_TX0_DN 8
EDP_TX0_DP 8
UHD
UHD
UHD
UHD
CCD_USB20_CON_P
CCD_USB20_CON_N
DMIC_CLK_C
DMIC_DATA_C
3D3V_CAMERA_S0
For DCBATOUT_CAMERA
For 3D3V_CAMERA_S0
IR_CAM_DET# 20
MIC_GND
DCBATOUT_CAMERA
EDP_VDD_EN8
LCD_VCC_TEST_EN24
SCD1U25V2KX-1-DL-GP
C5507
LCD_TST_C
BLON_OUT_C
LCDVDD
1 2
R5504,R5505 merge to RN5503
2015/10/06 modify
020.F0574.0050
2016/12/29 change PN
MIC_GND
X02 0414
0R0402-PAD
1 2
R5501
2016/11/9
EDP_HPD_CONN
RN5502
1
2
3
4 5
SRN100KJ-5-GP
8
7
6
D5501
1
3
2
BAT54C-7-F-3-GP
75.00054.E7D
1 2
0R0603-PAD
C5508
SC1U10V2KX-1DLGP
1 2
BKLT_CTRL
DMIC_CLK_C
DMIC_DATA_C
R5543 100R2J-2-GP
1 2
1 2
R5544 100R2J-2-GP
R5545
1 2
100R2J-2-GP
R5506
1 2
100R2J-2-GP
LVDS_VDD_EN_R
BLON_OUT_C
BKLT_CTRL
EDP_HPD_CONN
LVDS_VDD_EN_R
2017/05/08
R5546
LCDVDD_R
R5502
0R2J-2-GP
1 2
DY
3
BAT54C-7-F-3-GP
75.00054.E7D
RN5503
1
2 3
SRN33J-5-GP-U
BKLT_CTRLLCD_BRIGHTNESS
12
DY
12
C5505
D5502
1
LCD_TST
2
4
12
DY
2017/03/21
LCD_TST 24
PANEL_BKEN 24
EDP_HPD 8
LCD_BRIGHTNESS
EC5501
SC8P50V2DN-1DL-GP
SC4D7U6D3V3KX-DLGP
Add 0ohm , 20141118
EC5503
EC5504
SC33P50V2JN-3DLGP
SC33P50V2JN-3DLGP
12
20160812 EMI
2016/12/28
L_BKLT_CTRL 8
DMIC_CLK 27
DMIC_DATA 27
2016/12/20 change to 8P DY
IR CAMERA Power
B B
SCD1U50V3KX-DL-GP
C5542
1 2
Sensor/ Touch Panel
TCBD1
21
1
2
3
4
5
6
7
8
9
10
11
12
2IN1_TPNL
020.K0032.0020
A A
13
14
15
16
17
18
19
20
22
HRS-CON20-12-GP
5
3D3V_SEN_S0
SENSOR_I2C_SDA 20,70
SENSOR_I2C_SCL 20,70
GSEN_INT1 20
GSEN_INT2 20
GYRO_INT 70
GYRO_DRDY 20
TCH_INTR#
TCH_I2C_SDA
TCH_I2C_SCL
TPAN_VDD
2017/04/24
I2C0_SCL_TCH_PNL
I2C0_SDA_TCH_PNL
DCBATOUTDCBATOUT_CAMERA
R5520
1 2
0R0603-PAD
12
C5534
SC1KP50V2KX-1DLGP
2017/05/08
2016/12/23
Touch Panel
1 2
R5523 0R0402-PAD
1 2
R5522 0R0402-PAD
1 2
R5521 0R0402-PAD
2017/03/02
R5517 4K7R2J-2-GP
R5518 4K7R2J-2-GP
4
2017/03/17
CCD_USB20_CON_N
CCD_USB20_CON_P
EL5501
12
COIL-90OHM-100MHZ-5-GP
68.00396.001
43
2nd: = 68.01012.20B
3D3V_S0
Touch Panel PH internally.
R5504
100KR2J-1-GP
1 2
TOUCH_DETECT 20
TOUCH_REPORT_SW 24
TOUCH_PANEL_PD# 4
TOUCH_PANEL_INTR# 4,55
I2C0_SDA_TCH_PNL 20
I2C0_SCL_TCH_PNL
20
2017/04/24
3D3V_S0
12
12
TOUCH_PANEL_INTR#4,55
TCH_INTR#
12
DY
2017/03/17
ED5502
AZ5725-01FDR7G-GP
83.05725.0A0
EMI 20160812
CCD_USB20_N 16
CCD_USB20_P 16
1 2
R5505 10KR2J-3-GP
R5507
1 2
3
DY
DY
2017/06/12
100KR2J-1-GP
12
C5520
SC10U10V5KX-2DLGP
3D3V_S0
ED5501
3
DY
AZ5315-02F-GP
83.05315.0A0
Lo:0.8V
LCDVDD Layout 80 mil
U5501
1
EN
2
GND
3
VOUT
RT9724GB-GP
74.09724.09F
2ND = 74.03514.07F
5V_S0
12
C5523
SC10U10V5KX-2DLGP
DY
2017/03/21
5V_S0
DY
EC5505
SCD1U50V3KX-DL-GP
1 2
CCD_USB20_CON_P
2
CCD_USB20_CON_N
1
2017/03/17
3D3V_S0
5
VIN#5
4
VIN#4
12
C5502
SC4D7U6D3V3KX-DLGP
2017/05/08
3D3V_S0
U5502
1
VIN
2
GND
DY
SHDN#3SET
APL5324BI-TRG-GP
Design Current = 125mA
Starload height limite change to 0603 package
2015/09/30 modify
2
2016/11/3
2016/12/20
F5502
1 2
POLYSW-1D1A6V-9-GP-U
69.48001.081
2017/05/08
DCBATOUT
R5514
DCBATOUT_LCD_R
1 2
0R0603-PAD
SENSOR POWER
DY
F5504
1 2
POLYSW-1D1A6V-9-GP-U
R5515
1 2
0R0603-PAD
69.48001.081
3D3V_SEN_S0_R
TOUCH PANEL POWER
2017/05/08
5V_S03D3V_S0
DY
1 2
POLYSW-1D1A6V-9-GP-U
R5509
0R3J-0-U-GP
5
VOUT
4
VOUT=0.8*(1+R1/R2)
CAMERA POWER
3D3V_CAMERA_S0_R
INVERTER POWER
F5503
12
POLYSW-1D1A24V-GP-U
69.50007.A31
2nd = 69.50007.D31
Starload height limite change to 0603 package
2015/09/24 modify
Add 0603 0ohm , 20141118
SC33P50V2JN-3GP
69.48001.081
F5501
R5508
1 2
0R0603-PAD
1 2
DY
12
R5519
31K6R2F-GP
DY
12
R5524
DY
10KR2F-2-GP
TPAN_VDD
3D3V_CAMERA_S03D3V_S0
2017/05/08
R5513
1 2
0R0603-PAD
12
C5503
SC4D7U6D3V3KX-DLGP
DCBATOUT_LCD
2016/12/21
SCD1U50V3KX-DL-GP
EC5506
A2
A2
A2
C5513
SC1KP50V2KX-1DLGP
12
12
12
C5514
SC10U25V5KX-DL-GP
3D3V_SEN_S0
12
12
C5515
DY
SC4D7U6D3V3KX-DLGP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
LCD&CAM&DMC&Touch
LCD&CAM&DMC&Touch
LCD&CAM&DMC&Touch
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
12
12
C5517
12
C5518
DY
SC10U6D3V3MX-DL-GP
C5516
55 106Thursday, June 29, 2017
55 106Thursday, June 29, 2017
55 106Thursday, June 29, 2017
SCD1U50V3KX-DL-GP
C5512
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
SC10U6D3V3MX-DL-GP
A00
A00
A00
Page 56
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
CRT
CRT
CRT
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
56 106Thursday, June 29, 2017
56 106Thursday, June 29, 2017
56 106Thursday, June 29, 2017
1
Page 57
5
SSID = HDMI
HDMI_AUXP_L HDMI_AUXN_L
1 2
DP_DATA0_N8
DP_DATA0_P8
DP_DATA1_N8
DP_DATA1_P8
DP_DATA2_N8
DP_DATA2_P8
DP_DATA3_N8
D D
DP_DATA3_P8
2016/11/01modify
HDMI_AUXP8
HDMI_AUXN8
CPU_DP1_HPD8
3D3V_S0 3D3V_S03D3V_S0
R5740
4K7R2J-2-GP
12
R5741
10KR2J-3-GP
1 2
SPI_CS_HDMI
SPI_D_IN_HDMI
SPI_WR_PROT_HDMI
C5731 SCD1U25V2KX-1-DL-GP
1 2
C5737 SCD1U25V2KX-1-DL-GP
1 2
C5734 SCD1U25V2KX-1-DL-GP
1 2
C5732 SCD1U25V2KX-1-DL-GP
1 2
C5727 SCD1U25V2KX-1-DL-GP
1 2
C5728 SCD1U25V2KX-1-DL-GP
1 2
C5733 SCD1U25V2KX-1-DL-GP
1 2
C5735 SCD1U25V2KX-1-DL-GP
1 2
C5738 SCD1U25V2KX-1-DL-GP
1 2
C5739 SCD1U25V2KX-1-DL-GP
1 2
R5760 1KR2F-3-GP
VCC
HOLD#
SCLK
SI/SIO0
C5726
1 2
8
7
6
5
1 2
SCD1U25V2KX-1-DL-GP
U5702
1
CS#
2
SO/SIO1
3
WP#
4
GND
MX25L2006EM1I-12G-GP-U
72.25200.001
HDMI_AUXP_L
HDMI_AUXN_L
R5742
4K7R2J-2-GP
HOLD#_HDMI
SPI_CK_OUT_HDMI
SPI_D_OUT_HDMI
R5743
4K7R2J-2-GP
1 2
DP_DATA0_N_R
DP_DATA0_P_R
DP_DATA1_N_R
DP_DATA1_P_R
DP_DATA2_N_R
DP_DATA2_P_R
DP_DATA3_N_R
DP_DATA3_P_R
1 2
C5740
1 2
C5741
CPU_DP1_HPD_R
SCD1U25V2KX-1-DL-GP
HDMI_AUXP_R
HDMI_AUXN_R
SCD1U25V2KX-1-DL-GP
PS175_GPIO2
DY
68R2F-GP
R5762
R5754
4K7R2J-2-GP
1 2
4
12
HDMI_AUXP_R
HDMI_AUXN_R
CPU_DP1_HPD_R
PS175_GPIO0
68R2F-GP
DP_DATA0_P_R
DP_DATA0_N_R
DP_DATA1_P_R
DP_DATA1_N_R
DP_DATA2_P_R
DP_DATA2_N_R
DP_DATA3_P_R
DP_DATA3_N_R
DY
1 2
R5763
R5735
4K7R2J-2-GP
12
U5701
A8
DRX0P
A7
DRX0N
A6
DRX1P
A5
DRX1N
A4
DRX2P
A3
DRX2N
A2
DRX3P
A1
DRX3N
C7
AUXP
C8
AUXN
B1
DP_HPD
SPI_CS_HDMI
SPI_D_IN_HDMI
SPI_D_OUT_HDMI
SPI_CK_OUT_HDMI
SPI_WR_PROT_HDMI
1D2V_HDMI_EN58
VDD33 VDDTX12
VDDA12
B2
G4
G2
VDD33
VDD33
VDD33
VDDTX12G7VDDTX12
SPI_CS#C1SPI_D_IN
SPI_D_OUTD1SPI_CK_OUTD2GPIO1
E2
C2
PS175_GPIO0
PS175_GPIO2
PS175_CEC_EN
VDD12 VDDRX12
F4
F5
D6
G5
B7
VDD12
VDD12
VDDA12
GPIO0
CONFIG1/GPIO3
GPIO2E3SPI_WR_PROT
F3
E7
C4
D3
3
2
1
2016/11/02modify
1 2
3D3V_S0 3D3V_S0
12
R5738
B5
GND
VDDRX12
VDDRX12
VDDRX12
CEC_EN/GPIO4
VDD12_ON
GPIO5D7HDMI_ID/GPIO6
E6
D8
G8
GND
GNDG3GND
CSCL
XTLI
CSDA
F6
E8
PS175_CSDA
PS175_CSCL
GND
XTLO
F8
C6
B6
GND
GND
GND
HDMI_CEC
HDMI_HPD
PD#
RESET#
B8
C3
PS175_RST#
PS175_PD#
REXT
XTLO_HDMI
XTLI_HDMI
HDMID2P
HDMID2N
HDMID1P
HDMID1N
HDMID0P
HDMID0N
HDMICKP
HDMICKN
DDC_SCL
DDC_SDA
TESTMODEBC5REXT
NC#F7
F7
D4
B3
B4
E5
G6
D5
E4
4K7R2J-2-GP
PS175_CSDA PS175_CSCL
HDMI_DATA2_L_C
H8
HDMI_DATA2#_L_C
H7
HDMI_DATA1_L_C
H6
HDMI_DATA1#_L_C
H5
HDMI_DATA0_L_C
H4
HDMI_DATA0#_L_C
H3
HDMI_CLK_L_C
H2
HDMI_CLK#_L_C
H1
HDMI_CEC HDMI_CEC_C
F2
DDC_CLK_HDMI
E1
DDC_DATA_HDMI
F1
HPD_HDMI_CON
G1
071.17564.0B0U
PS175HDMBGA64GTR2-B1-GP
R5761
1 2
DY
0R2J-2-GP
2017/03/10
3D3V_S0
12
R5736
10KR2J-3-GP
PS175_PD#
4D3KR2F-GP
R5739
4K7R2J-2-GP
REXT
R5734
12
12
HDMI_DATA2#_L_C HDMI_DATA2#_R_C
HDMI_DATA1_L_C HDMI_DATA1_R_C
HDMI_DATA1#_L_C HDMI_DATA1#_R_C
HDMI_DATA0_L_C HDMI_DATA0_R_C
HDMI_DATA0#_L_C HDMI_DATA0#_R_C
HDMI_CLK_L_C HDMI_CLK_R_C
HDMI_CLK#_L_C HDMI_CLK#_R_C
R5765 5D1R2F-GP
1 2
R5766 5D1R2F-GP
2017/03/16
1 2
R5767 5D1R2F-GP
1 2
R5768 5D1R2F-GP
2017/03/16
1 2
R5769 5D1R2F-GP
1 2
R5770 5D1R2F-GP
2017/03/16
1 2
R5771 5D1R2F-GP
1 2
R5772 5D1R2F-GP
2017/03/16
HDMI_DATA2_R_CHDMI_DATA2_L_C
C C
XTLI_HDMI
12
C5729
SC22P50V2JN-4DLGP
2016/12/14 vendor suggest
B B
DY
R5750
1 2
1MR2J-L3-GP
X5701
XTAL-27MHZ-187-GP
082.30008.0361
INPUT/OUTPUT#11NO_CONNECT2INPUT/OUTPUT#3
3
XTLO_HDMI
HDMI_27MHZ_OUT
12
R5748
1K5R2J-3-GP
12
C5730
2016/12/20
SC22P50V2JN-4DLGP
PS175_CEC_EN
PS175_RST#
4K7R2J-2-GP
4K7R2J-2-GP
10KR2J-3-GP
SC1U10V2KX-1DLGP
5V_S0 5V_HDMI_S5
F5701
POLYSW-1D1A6V-9-GP-U
1 2
69.48001.081
2nd = 69.50011.081
3D3V_S0
12
R5756
DY
12
R5757
DY
R5737
C5725
3D3V_S0
12
12
20150116 2037
5V_S0
3
2
DDC_CLK_PH1
R5755
2K2R2J-2-GP
D5701
BAW56-9-GP
75.00056.07D
1
DDC_DATA_PH2
12
12
R5751
2K2R2J-2-GP
DDC_DATA_HDMI
DDC_CLK_HDMI
SCD1U25V2KX-1-DL-GP
C5736
5V_HDMI_S5
1 2
HDMI_DATA0_R_C
HDMI_DATA0#_R_C
HDMI_DATA1_R_C
HDMI_DATA1#_R_C
HDMI_DATA2_R_C
HDMI_DATA2#_R_C
HDMI_CLK_R_C
HDMI_CLK#_R_C
2016/11/7modify
HDMI CONN
HDMI1
18
+5V_POWER
7
TMDS_DATA0+
9
TMDS_DATA0-
4
TMDS_DATA1+
6
TMDS_DATA1-
1
TMDS_DATA2+
3
TMDS_DATA2-
8
TMDS_DATA0_SHIELD
5
TMDS_DATA1_SHIELD
2
TMDS_DATA2_SHIELD
11
TMDS_CLOCK_SHIELD
10
TMDS_CLOCK+
12
TMDS_CLOCK-
SKT-HDMI23-167-GP-U
022.10025.00M1
DDC/CEC_GROUNG
HOT_PLUG_DETECT
RESERVED#14
HDMI
(A_Type)
2016/11/6modify
HDMI_CLK_L_C
12
C5724
DY
SCD75P50V1CN-GP
HDMI_CLK#_L_C
SCL
SDA
CEC
GND
GND
GND
GND
ED5701
1
2
15
16
13
17
19
14
20
21
22
23
DDC_CLK_HDMI
DDC_DATA_HDMI
HDMI_CEC_C
HPD_HDMI_CON
1 2
R5764
100KR2J-1-GP
3 8
4
5 6
L05ESDL5V0NA-4-GP
DY
ED5702
1
2
3 8
4
5 6
L05ESDL5V0NA-4-GP
10
9
7
10
9
7
DY
HDMI_DATA1#_R_C
HDMI_DATA1_R_C
HDMI_DATA2#_R_C
HDMI_DATA2_R_C
HDMI_DATA0_R_C
HDMI_DATA0#_R_C
HDMI_CLK#_R_C
HDMI_CLK_R_C
20160812 EMI
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
HDMI
HDMI
HDMI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
57 106
57 106
57 106
A00
A00
A00
Page 58
5
SSID = HDMI
4
3
2
1
C5843
SC10U6D3V3MX-DL-GP
VDD33
12
12
C5855
12
SC10U6D3V3MX-DL-GP
C5824
SCD1U25V2KX-1-DL-GP
for digital logic
12
C5828
SCD1U25V2KX-1-DL-GP
5V_S5
12
C5825
12
C5826
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
+V1.8A
2017/05/08
PG5801
GAP-CLOSE-PWR-3-GP
1 2
12
C5857
SC10U6D3V3MX-DL-GP
SC1U10V2KX-1DLGP
C5856
1 2
R5801
0R0402-PAD-1-GP
12
1D2V_HDMI_VIN
1D2V_HDMI_EN_R
12
C5858
AOZ2023 for HDMI 1D2V
U5801
5
4
VCNTL
3
VIN
2
EN
1
POK
SCD1U25V2KX-1-DL-GP
AOZ2023PI-GP
NC#5
VOUT
FB
GND
GND
6
1D2V_HDMI_FB
7
8
9
R5802
5K1R2F-2-GP
12
C5859
SC68P50V2JN-1GP
12
DY
Design Current = 550mA
PG5802
GAP-CLOSE-PWR-3-GP
1 2
2017/05/08
C5860
12
SC10U6D3V3MX-DL-GP
C5861
12
SC10U6D3V3MX-DL-GP
1D2V_HDMIPWR_1D2V
074.02023.0031
1D2V_HDMI_EN57
12
R5803
10KR2F-2-GP
12
C5829
12
C5832
SCD1U25V2KX-1-DL-GP
SCD01U50V2KX-1DLGP
12
C5833
SCD01U50V2KX-1DLGP
Vout=0.8V*(R1+R2)/R2
3D3V_S0
D D
C C
2017/05/08
R5806
1 2
0R0603-PAD
12
C5827
SCD47U25V3KX-1-DL-GP
1D2V_HDMI VDD12
12
VDD33_R
1 2
BLM18KG331SN1D-GP
C5831
SCD47U25V3KX-1-DL-GP
L5801
1 2
BLM18KG331SN1D-GP
L5802
1D2V_HDMI VDDA12
L5803
1 2
BLM18KG331SN1D-GP
12
C5836
SCD47U25V3KX-1-DL-GP
B B
1D2V_HDMI VDDRX12
L5804
1 2
BLM18KG331SN1D-GP
12
C5840
SCD47U25V3KX-1-DL-GP
12
12
for analog
C5844
SC10U6D3V3MX-DL-GP
12
C5834
12
SCD1U25V2KX-1-DL-GP
for DP receiver
C5845
12
SC10U6D3V3MX-DL-GP
C5838
SCD1U25V2KX-1-DL-GP
C5837
12
SCD01U50V2KX-1DLGP
C5839
12
SCD1U25V2KX-1-DL-GP
C5846
12
C5847
SCD1U25V2KX-1-DL-GP
12
C5841
SCD01U50V2KX-1DLGP
SCD01U50V2KX-1DLGP
12
C5842
SCD01U50V2KX-1DLGP
1D2V_HDMI VDDTX12
L5805
1 2
A A
BLM18KG331SN1D-GP
12
C5850
SCD47U25V3KX-1-DL-GP
5
12
for HDMI transmitter
C5853
SC10U6D3V3MX-DL-GP
12
C5848
12
SCD1U25V2KX-1-DL-GP
C5849
SCD1U25V2KX-1-DL-GP
<Core Design>
<Core Design>
12
C5851
SCD01U50V2KX-1DLGP
12
C5852
SCD01U50V2KX-1DLGP
4
3
2
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
58 106Thursday, June 29, 2017
58 106Thursday, June 29, 2017
58 106Thursday, June 29, 2017
1
A00
A00
A00
Page 59
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
(Reserved)
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
59 106Thursday, June 29, 2017
59 106Thursday, June 29, 2017
59 106Thursday, June 29, 2017
1
Page 60
5
E E
D D
4
3
2
1
C C
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A A
Title
Title
Title
SATA IF_HDD/ODD
SATA IF_HDD/ODD
SATA IF_HDD/ODD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
Thursday, June 29, 2017
2
KyloRen 13"
Taipei Hsien 221, Taiwan, R.O.C.
60 106
60 106
60 106
1
A00
A00
A00
Page 61
5
SSID = WLAN
4
3
2
1
3D3V_S03D3V_S5
D D
1A
12
C509
DY
SCD1U16V2KX-3DLGP
R516
AUX_EN_WOWL17,24
C C
AUX_EN_WOWL
0R2J-2-GP
DY
12
AUX_EN_WOWL_R
Q504
G
DY
S
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
D
12
R519
10KR2J-3-GP
DY
WLAN_EN#
R517
1 2
DY
20KR2J-L2-GP
12
C507
DY
SCD1U16V2KX-3DLGP
WLAN_EN_R#
2017/05/08
R512
1 2
0R0805-PAD
Q503
DMP2130L-7-GP
S
84.02130.031
G
DY
G
D
D
SCD1U16V2KX-3DLGP
2nd = 84.00102.031
3rd = 84.03413.B31
12
DY
C508
3D3V_WLAN
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
NGFF_WLAN CONN
NGFF_WLAN CONN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
NGFF_WLAN CONN
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
61 106Thursday, June 29, 2017
61 106Thursday, June 29, 2017
61 106Thursday, June 29, 2017
A00
A00
A00
Page 62
A
4 4
B
C
D
E
(Blanking)
3 3
2 2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
1 1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
A
B
C
Date: Sheet of
D
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
62 106Thursday, June 29, 2017
62 106Thursday, June 29, 2017
62 106Thursday, June 29, 2017
E
A00
A00
A00
Page 63
5
4
3
2
1
SSID = M.2
2017/05/08
3D3V_S0 3D3V_SSD
R6302
1 2
0R0603-PAD
R6306
1 2
0R0603-PAD
D D
C C
MSATA_SATA_TX_P2_C
MSATA_SATA_TX_N2_C
MSATA_SATA_RX_N2
MSATA_SATA_RX_P2
SC33P50V2JN-3DLGP
3D3V_SSD
C6305
12
DY
12
DY
12
SSD
R6303
10KR2J-3-GP
SSD_DEVSLP
R6304
10KR2J-3-GP
C6304
SC33P50V2JN-3DLGP
12
SSD
ED6301
1
2
3 8
DY
4
5 6
L05ESDL5V0NA-4-GP
075.00550.0071
C6308
C6307
C6306
SCD047U25V2KX-4-GP
12
SSD
10
9
7
SCD1U25V2KX-1-DL-GP
SCD047U25V2KX-4-GP
12
SSD
SSD
MSATA_SATA_TX_P2_C
MSATA_SATA_TX_N2_C
MSATA_SATA_RX_N2
MSATA_SATA_RX_P2
C6317
SC22U6D3V3MX-1-DL-GP
12
SSD
C6318
SC22U6D3V3MX-1-DL-GP
12
12
SSD
SSD M.2 CONN
3D3V_SSD
CLK_PCIE_NVME_REQ#18
PLT_RST#17,26,66,91,99
R6301
3D3V_SSD
MSATA_DEVSLP_R
3D3V_SSD
SSD_DEVSLP16
1 2
0R0402-PAD
SSD1
NP2
NP2
76
76
74
3_3VAUX
72
3_3VAUX
70
3_3VAUX
68
SUSCLK_32KHZ
58
NC#58
56
NC#56
54
PEWAKE#/NC#54
52
CLKREQ#/NC#52
50
PERST#/NC#50
48
NC#48
46
NC#46
44
NC#44
42
NC#42
40
NC#40
38
DEVSLP
36
NC#36
34
NC#34
32
NC#32
30
NC#30
28
NC#28
26
NC#26
24
NC#24
22
NC#22
20
NC#20
18
3_3VAUX
16
3_3VAUX
14
3_3VAUX
12
3_3VAUX
10
DAS/DSS#
8
NC#8
6
NC#6
4
3_3VAUX
2
3_3VAUX
SKT-MINI67P-43-GP
SSD
062.10007.0981
PEDET(OC_PCIE/GND_SATA)
D_PERP0/SATA_A+/H_PETP0
D_PERN0/SATA_A-/H_PETN0
D_PETP0/SATA_B-/H_PERP0
D_PETN0/SATA_B+/H_PERN0
D_PERP1/H_PETP1
D_PERN1/H_PETN1
D_PETP1/H_PERP1
D_PETN1/H_PERN1
D_PERP2/H_PETP2
D_PERN2/H_PETN2
D_PETN2/H_PERP2
D_PETP2/H_PERN2
D_PERP3/H_PETP3
D_PERN3/H_PETN3
D_PETN3/H_PERP3
D_PETP3/H_PERN3
NGFF_KEY_M 75P
NP1
GND
GND
GND
NC#67
GND
REFCLKP
REFCLKN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NP1
77
77
75
73
71
69
67
57
55
53
51
MSATA_SATA_TX_P2_C
49
MSATA_SATA_TX_N2_C
47
45
43
41
39
MSATA_PCIE_TX_P11_C
37
MSATA_PCIE_TX_N11_C
35
33
31
29
27
MSATA_PCIE_TX_P10_C
25
MSATA_PCIE_TX_N10_C
23
21
19
17
15
MSATA_PCIE_TX_P9_C
13
MSATA_PCIE_TX_N9_C
11
9
7
5
3
1
3D3V_S0
12
SSD
SSD
1 2
SSD
1 2
SSD
1 2
SSD
1 2
SSD
1 2
SSD
1 2
SSD
1 2
SSD
1 2
3D3V_SSD
MSATA_DEVSLP_R
M2_SSD_PEDET
R6305
100KR2F-L1-GP
M2_SSD_PEDET 16
C6302 SCD22U10V2KX-2-GP
C6303 SCD22U10V2KX-2-GP
C6311 SCD22U10V2KX-2-GP
C6312 SCD22U10V2KX-2-GP
C6313 SCD22U10V2KX-2-GP
C6314 SCD22U10V2KX-2-GP
C6315 SCD22U10V2KX-2-GP
C6316 SCD22U10V2KX-2-GP
1
AFTP6304
1
AFTP6301
1
AFTP6303
PCIE:1 SATA:0
MSATA_CLK_CPU 18
MSATA_CLK_CPU# 18
MSATA_SATA_TX_P2 16
MSATA_SATA_TX_N2 16
MSATA_SATA_RX_N2 16
MSATA_SATA_RX_P2 16
MSATA_PCIE_TX_P11 16
MSATA_PCIE_TX_N11 16
MSATA_PCIE_RX_P11 16
MSATA_PCIE_RX_N11 16
MSATA_PCIE_TX_P10 16
MSATA_PCIE_TX_N10 16
MSATA_PCIE_RX_P10 16
MSATA_PCIE_RX_N10 16
MSATA_PCIE_TX_P9 16
MSATA_PCIE_TX_N9 16
MSATA_PCIE_RX_P9 16
MSATA_PCIE_RX_N9 16
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
(Reserved)
(Reserved)
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
A00
A00
63 106Thursday, June 29, 2017
63 106Thursday, June 29, 2017
63 106Thursday, June 29, 2017
A00
Page 64
5
SSID = Power BTN
4
3
2
1
D D
(AMBER_LED)Battery LED1
Low actived from KBC GPIO
5V_S5
Q6402
R2
1 2
CHG_AMBER_LED#24
R6403
0R0402-PAD
CHG_AMBER_LED_R#
B
RN2418-GP
084.02418.0011
C C
BATT_WHITE_LED#24
1 2
R6404
0R0402-PAD
BATT_WHITE_LED_R#
Q6401
B
RN2418-GP
084.02418.0011
E
R1
C
AMBER_LED_BAT
R6401
12
499R2F-2-GP
12
ED6401
PESD5V0S1BB-GP-U
BAT_AMBER 65
AMBER
DY
5V_S5
R2
E
R1
C
WHITE_LED_BAT
2017/06/12
R6402
12
680R2F-GP
12
ED6402
PESD5V0S1BB-GP-U
BAT_WHITE 65
WHITE
DY
Battery LED2
(WHITE_LED)
Low actived from KBC GPIO
B B
2017/01/24
SATA LED
BATT_WHITE_LED_R#
Vth(max)=1V
HWHDLED
MASK_SATA_LED#24
SATA_LED#16
2017/01/24
1D8V_S0
R6120
1 2
A A
HWHDLED
10KR2J-3-GP
MASK_SATA_LED#
DS
Q6105
G
DMN5L06K-7-GP
84.05067.031
Add SATA LED solution by customer request 2016/02/03
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
LED Board&Power Button
LED Board&Power Button
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
LED Board&Power Button
64 106
64 106
64 106
1
A00
A00
A00
Page 65
5
4
3
2
1
SSID = TPADSSID = KB
+5V_KB_BL
TP_WAKE_KBC#4,24
PTP_DIS#24
AFTP6525
Keyboard
12
DY
2016/11/3
KB_LED_DET_C
C6506
SCD1U16V2KX-3DLGP
KB_BL_CTRL#
I2C0_SDA_R
I2C0_SCL_R
TPDATA_C
TPCLK_C
1
2016/12/07 change PN
KBBL1
5
1
2
3
4
6
ACES-CON4-90-GP-U
020.K0298.0004
TP1
10
8
7
6
5
4
3
2
1
9
PTWO-CON8-16-GP
020.K0255.0008
2016/12/28 change PN
PS2
I2C
3D3V_S5
TP_WAKE
Q6502
DMP2130L-7-GP
SCD1U25V2KX-1-DL-GP
C6502
TP_WAKE
TP_WAKE
TP_EN#24
CLK_TP_SIO24
DAT_TP_SIO24
I2C0_SCL_TCH_PAD20
I2C0_SDA_TCH_PAD20
1 2
R6504
20KR2F-L-GP
TP_VDD
23
TP_ON#_GATE
1
RN6501
SRN10KJ-5-GP
4
EC6502
EC6501
12
SC33P50V2JN-3DLGP
SC33P50V2JN-3DLGP
12
S
12
G
EC6503
EC6504
12
12
SC33P50V2JN-3DLGP
SC33P50V2JN-3DLGP
3D3V_S0 TP_VDD
NON TP_WAKE
R6502
0R3J-0-U-GP
Q6502_D
R6514
D
D
G
84.02130.031
2ND = 84.03413.A31
RN6502
SRN33J-5-GP-U
1
2 3
1 2
NON TP_WAKE
1 2
NON TP_WAKE
20160812 EMI
1 2
0R0603-PAD
2017/05/08
4
1 2
TPCLK_C
TPDATA_C
I2C0_SCL_R
R65050R2J-2-GP
I2C0_SDA_R
R65060R2J-2-GP
TP_VDD Discharge Circuit
TP_VDD
12
R6503
100R3J-4-GP
D
TP_WAKE
Q6205_Q
TP_ON#_GATE
Q6503
G
TP_WAKE
S
?
GPIO_TPAD: TBD
(Touch pad wake# for S3 wake up @ PCH GPIO??)
2N7002K-2-GP
84.2N702.J31
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
KSI[0..7]24
KSO[0..16]24
KB_DET#20
AFTP6502
AFTP6503
AFTP6505
AFTP6508
AFTP6506
D D
AFTP6501
AFTP6509
AFTP6512
AFTP6510
AFTP6514
AFTP6515
AFTP6517
AFTP6516
AFTP6518
AFTP6511
AFTP6513
AFTP6507
AFTP6519
AFTP6539
AFTP6524
AFTP6520
AFTP6521
AFTP6504
AFTP6522
AFTP6523
C C
CAP_LED
AFTP6538
BAT_AMBER64
BAT_WHITE64
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10
CAP_LED
1
LED1
5
1
2
3
4
6
PTWO-CON4-21-GP
KBBD1
32
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
PTWO-CON30-18-GP
020.K0210.0030
C6505
SCD1U25V2KX-1-DL-GP
TP_VDD
12
020.K0255.0004
2016/12/28 change PN
?
F6501
1 2
POLYSW-D5A6V-1-GP
KBBL
+5V_KB_BL_R
69.50007.921
KB Backlight Power Consumption: 285mA max.
B B
KBBL
KB_LED_PWM24
12
R6509
DY
100KR2J-1-GP
+5V_KB_BL
KB_BL_CTRL#
KB_BL_CTRL#
2016/10/31modify
DS
Q6501
G
1
1
DMN3404L-7-1-GP
084.03404.0A31
AFTP6529
AFTP6530
R6501
1 2
0R0603-PAD
12
KBBL
KB_LED_BL_DET19
2017/05/08
+5V_KB_BL5V_S0
C6501
SCD1U25V2KX-1-DL-GP
KBBL
R6507
1 2
KBBL
12
51KR2J-1-GP
R6508
100KR2J-1-GP
KB_LED_DET_C
12
C6504
SCD1U16V2KX-3DLGP
DY
I2C0_SCL_TCH_PAD
84.2N702.A3F
2nd = 84.2N702.E3F
3rd = 75.00601.07C
4th = 84.DMN66.03F
I2C0_SDA_TCH_PAD
Q6204_G
1
2
3 4
5V_S0
A00 0609
12
R6510
0R0402-PAD
Q6504
2N7002KDW-GP
6
5
TP_WAKE
DY
DY
DY
TP_VDD
TP_WAKE
I2C0_SCL_R
I2C0_SDA_R
1
23
4
DY
RN6503
SRN2K2J-1-GP
Need to check if it is Active High or Active Low
and check if there is PH on TPAD side.
R6511
10KR2J-3-GP
X02 0415
TP_WAKE_KBC#
TP_VDD
12
Pin number
1
2
3
4
5
6
7
8
TP_VDD
TPCLK_C
TPDATA_C
I2C0_SCL_R
I2C0_SDA_R
TP_WAKE_KBC#
PTP_DIS#
Change pindefine DVT1 0210 1330
Pin name
VDD
DAT(I2C)
CLK(I2C)
GND
ATTN
GPIO
DAT(PS2)
CLK(PS2)
1
AFTP6531
1
AFTP6532
1
AFTP6533
1
AFTP6534
1
AFTP6535
1
AFTP6536
1
AFTP6537
CAP LED Control
LOW actived from KBC GPIO
A A
X02 0414
1 2
CAP_LED#_R24
R6512
0R0402-PAD
5
CAP_LED_R#
Q6505
R2
B
R1
RN2418-GP
084.02418.0011
5V_S5
<Core Design>
<Core Design>
E
C
1 2
R6513 1KR2J-1-GP
CAP_LEDCAP_LED_Q
4
3
2
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
Key Board&Touch Pad
Key Board&Touch Pad
Key Board&Touch Pad
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
65 106
65 106
65 106
A00
A00
A00
Page 66
5
4
3
2
1
SSID = IO Connector
IOBD1
2016/11/07
D D
C C
51
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
54
52
CARD1_USB20_CON_P
CARD1_USB20_CON_N
BT_USB20_CON_N
BT_USB20_CON_P
USB2_USB20_CON_P
USB2_USB20_CON_N
2017/05/02
WLAN_PCIE_TX_P 16
WLAN_PCIE_TX_N 16
WLAN_PCIE_RX_N 16
WLAN_PCIE_RX_P 16
USB2_USB30_TX_P3 16
USB2_USB30_TX_N3 16
USB2_USB30_RX_P3 16
USB2_USB30_RX_N3 16
WLAN_CLK_CPU 18
WLAN_CLK_CPU# 18
5V_S5
3D3V_WLAN
3D3V_S5
+RTC_VCC
WLAN
IO board USB3.0
Card Reader
2016/11/09
BT
USB3.0 port3
BREATH_LED# 24
PLT_RST# 17,26,63,91,99
CLK_PCIE_WLAN_REQ# 18
WIFI_RF_EN 15
BLUETOOTH_EN 20
USB_OC1# 16
USB_EN# 24,35
DY
USB2_USB20_CON_P
USB2_USB20_CON_N
CARD1_USB20_CON_P
CARD1_USB20_CON_N
KBC_PWRBTN# 24
12
C6605
BT_USB20_CON_N
BT_USB20_CON_P
Change choke Height just for Starload
2015/09/23 modify
EL6601
1 2
4 3
COIL-90OHM-100MHZ-5-GP
68.00396.001
2nd: = 68.01012.20B
EL6602
1 2
4 3
COIL-90OHM-100MHZ-5-GP
68.00396.001
2nd: = 68.01012.20B
R6605
1 2
0R0402-PAD
R6606
1 2
0R0402-PAD
2017/03/16
USB2_USB20_P 16
USB2_USB20_N 16
CARD1_USB20_P 16
CARD1_USB20_N 16
BT_USB20_N 16
BT_USB20_P 16
STAR-CON50-2-GP-U
020.F0688.0050
SCD1U16V2KX-3DLGP
B B
CARD1_USB20_CON_P
CARD1_USB20_CON_N
BT_USB20_CON_P
BT_USB20_CON_N
USB2_USB20_CON_P
USB2_USB20_CON_N
3D3V_S5
5V_S5
1
AFTP6601
1
AFTP6602
1
AFTP6603
1
AFTP6604
1
AFTP6605
1
AFTP6606
1
AFTP6607
1
AFTP6608
2016/12/07 add AFTP
A A
5
4
KBC_PWRBTN#
1
2016/12/16 add AFTP
3
AFTP6609
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
IO Board Connector
IO Board Connector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
IO Board Connector
KyloRen 13"
KyloRen 13"
KyloRen 13"
66 106
66 106
66 106
1
A00
A00
A00
Page 67
5
D D
4
3
2
1
C C
B B
(Blanking)
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
67 106Thursday, June 29, 2017
67 106Thursday, June 29, 2017
67 106Thursday, June 29, 2017
1
A00
A00
A00
Page 68
5
4
3
2
1
SSID = Debug
D D
Debug Connector
DB1
15
1
ESPI_CLK18,24
C C
ESPI_IO[3..0]18,24
2016/11/29
3D3V_S0
HOST_DEBUG_TX24
UART_2_CTXD_DRXD20
UART_2_CRXD_DTXD20
2016/11/25
R6801
R6802 0R0402-PAD
R6803
ESPI_RESET#18,24
ESPI_CS#18,24
1 2
0R2J-2-GP
1 2
1 2
DY
0R0402-PAD
2017/03/02
ESPI_IO3
ESPI_IO2
ESPI_IO1
ESPI_IO0
HOST_DEBUG_TX_CON
UART_2_CTXD_DRXD_CON
UART_2_CRXD_DTXD_CON
2
3
4
5
6
7
8
9
10
11
12
13
14
16
20.F0765.014
ZZ.F0765.01401
DM-ACES-CON14-5-GP-01
2017/05/10
Use ZZ.F0765.01401 DUMMY PAD for MP
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Dubug connector
Dubug connector
Dubug connector
68 106Thursday, June 29, 2017
68 106Thursday, June 29, 2017
68 106Thursday, June 29, 2017
1
A00
A00
A00
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5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Reserved
Reserved
Reserved
69 106Thursday, June 29, 2017
69 106Thursday, June 29, 2017
69 106Thursday, June 29, 2017
1
A00
A00
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Page 70
5
SSID = Hall Sensor
4
3
2
1
3D3V_S5
R7001
2016/12/06 follow 15"
D D
LID_CL_SIO_TAB#24
100KR2J-1-GP
DY
1 2
12
DY
C C
LID sensor
C7001
SCD047U16V2KX-1-GP
100KR2J-1-GP
HALL1
1
OUT2
OUT1
GND2VDD
HGDEDM013A-GP
074.00013.00BJ
R7011
4
3
3D3V_S5
DY
1 2
LID_CL_SIO# 24
C7002
SCD1U25V2KX-1-DL-GP
3D3V_S5
GYRO_INT_C20
12
GYRO_INT_P11
INT2_SELECT
combine G
GYRO_INT_P11
1 2
DY
1 2
R7003
0R0402-PAD
D7001
1
DY
2
BAT54A-7-F-2-GP
75.00054.R7D
1 2
R7008 0R0402-PAD
R70020R2J-2-GP
3
GYRO_INT 55
FFS_INT2 20
Note:
2017/05/08
3D3V_S0 3D3V_GSEN2
11uA
R7004
1 2
0R0603-PAD
3D3V_GSEN2
B B
R7005 10KR2J-3-GP
R7007 0R0402-PAD
GSEN2_INT1_C20
GSEN2_INT2_C20
FFS_INT118
SENSOR_I2C_SCL20,55
SENSOR_I2C_SDA20,55
C7003
SCD1U25V2KX-1-DL-GP
1 2
DY
1 2
12
2IN1
C7004
near pin9
2IN1
12
C7004
SC10U6D3V3MX-DL-GP
SENSOR_I2C_SCL_2G
SENSOR_I2C_SDA_2G
GSENSOR_SDO
GSEN2_INT1_C
GSEN2_INT2_C
INT2_SELECT
R7014 0R0402-PAD
R7015 0R0402-PAD
R7009 0R0402-PAD
R7010 0R0402-PAD
R7012 0R0402-PAD
R7013 0R0402-PAD
1 2
1 2
2016/12/28
Free Fall Sensor + G Sensor
3D3V_GSEN2
U7001
9
VDD
10
VDD_IO
SCL/SPC
SDA/SDI/SDO
SDO/SA0
LNG2DMTR-GP
2IN1
1
4
3
074.LNG2D.00BZ
1 2
1 2
1 2
1 2
SENSOR_I2C_SCL_2G
SENSOR_I2C_SDA_2G
RES
INT1
INT2
GND
GND
GND
CS
2
5
12
11
6
7
8
GSEN2_INT1
GSEN2_INT2
GSENSOR_CS
GSEN2_INT1
GSEN2_INT2
1 2
R7006 10KR2J-3-GP
2IN1
Note:
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
- design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
Please help to close with U6602
3D3V_S0
12
R7018
100KR2J-1-GP
FALL_INT2
Q7001
2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
INT2_SELECT
1
2
34
5
6
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
(Reserved)
(Reserved)
(Reserved)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
70 106
70 106
70 106
A00
A00
A00
Page 71
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
RESERVED
RESERVED
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
RESERVED
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
71 106Thursday, June 29, 2017
71 106Thursday, June 29, 2017
71 106Thursday, June 29, 2017
1
Page 72
5
D D
4
3
2
1
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
USB3.0 PORT
USB3.0 PORT
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
USB3.0 PORT
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
72 106Thursday, June 29, 2017
72 106Thursday, June 29, 2017
72 106Thursday, June 29, 2017
1
Page 73
5
4
3
2
1
Main Func = dGPU
D D
C C
(Blanking)
B B
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
A A
Title
Title
Title
GPU(1/5)PEG
GPU(1/5)PEG
GPU(1/5)PEG
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
Thursday, June 29, 2017
2
KyloRen 13"
KyloRen 13"
KyloRen 13"
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
A00
A00
A00
73 106
73 106
73 106
1
Page 74
5
4
3
2
1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
GPU(2/5)DIGITALOUT
GPU(2/5)DIGITALOUT
GPU(2/5)DIGITALOUT
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
74 106
74 106
74 106
A00
A00
A00
Page 75
5
4
3
2
1
Main Func = dGPU
D D
C C
B B
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
GPU(3/5)VRAMI/F
GPU(3/5)VRAMI/F
GPU(3/5)VRAMI/F
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A1
A1
A1
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
1
Taipei Hsie n 221, Taiwan, R.O. C.
KyloRen 13"
KyloRen 13"
KyloRen 13"
75 106
75 106
75 106
A00
A00
A00
Page 76
5
4
3
2
1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
1
Taipei Hsien 221, Taiwan, R.O.C.
GPU(4/5)GPIO/STRAP
GPU(4/5)GPIO/STRAP
GPU(4/5)GPIO/STRAP
KyloRen 13"
KyloRen 13"
KyloRen 13"
76 106
76 106
76 106
A00
A00
A00
Page 77
5
4
3
2
1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU(5/5)PWR/GND
GPU(5/5)PWR/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
GPU(5/5)PWR/GND
KyloRen 13"
KyloRen 13"
KyloRen 13"
77 106
77 106
77 106
1
A00
A00
A00
Page 78
5
4
3
2
1
SSID = VRAM
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU-VRAM1,2 (1/4)
GPU-VRAM1,2 (1/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
GPU-VRAM1,2 (1/4)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
A00
A00
78 106Thursday, June 29, 2017
78 106Thursday, June 29, 2017
78 106Thursday, June 29, 2017
A00
Page 79
5
4
3
2
1
SSID = VRAM
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU-VRAM3,4 (2/4)
GPU-VRAM3,4 (2/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
GPU-VRAM3,4 (2/4)
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
A00
A00
79 106Thursday, June 29, 2017
79 106Thursday, June 29, 2017
79 106Thursday, June 29, 2017
A00
Page 80
5
4
3
2
1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU(5/5)PWR/GND
GPU(5/5)PWR/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
GPU(5/5)PWR/GND
KyloRen 13"
KyloRen 13"
KyloRen 13"
80 106
80 106
80 106
1
A00
A00
A00
Page 81
5
4
3
2
1
Main Func = dGPU
D D
C C
B B
<Core Design>
<Core Design>
A A
5
4
3
2
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU-VRAM1,2 (1/4)
GPU-VRAM1,2 (1/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
GPU-VRAM1,2 (1/4)
KyloRen 13"
KyloRen 13"
KyloRen 13"
81 106
81 106
81 106
1
A00
A00
A00
Page 82
5
4
3
2
1
Main Func = dGFX_CORE
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
RT8812_VGACORE
RT8812_VGACORE
RT8812_VGACORE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
82 106Thursday, June 29, 2017
82 106Thursday, June 29, 2017
82 106Thursday, June 29, 2017
A00
A00
A00
Page 83
5
4
3
2
1
Main Func = dGPU
D D
C C
B B
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
21F, 88, Sec.1, Hsin T ai Wu Rd ., Hsichih,
Taipei Hsie n 221, Taiwan, R.O. C.
Taipei Hsie n 221, Taiwan, R.O. C.
Title
Title
Title
DISCRETE VGA POWER
DISCRETE VGA POWER
DISCRETE VGA POWER
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
A1
A1
A1
KyloRen 13"
KyloRen 13"
KyloRen 13"
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
1
Taipei Hsie n 221, Taiwan, R.O. C.
83 106Thursday, June 29, 2017
83 106Thursday, June 29, 2017
83 106Thursday, June 29, 2017
A00
A00
A00
Page 84
5
4
3
2
1
Main Func = dGPU
D D
C C
B B
<Core Design>
<Core Design>
A A
5
4
3
2
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU-VRAM7,8 (4/4)
GPU-VRAM7,8 (4/4)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
GPU-VRAM7,8 (4/4)
KyloRen 13"
KyloRen 13"
KyloRen 13"
84 106
84 106
84 106
1
A00
A00
A00
Page 85
5
4
3
2
1
Main Func = dGFX_CORE
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
GPU CORE
GPU CORE
GPU CORE
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
85 106Thursday, June 29, 2017
85 106Thursday, June 29, 2017
85 106Thursday, June 29, 2017
A00
A00
A00
Page 86
5
4
3
2
1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
GPU Discrete Power
GPU Discrete Power
GPU Discrete Power
A2
A2
A2
KyloRen 13"
KyloRen 13"
KyloRen 13"
A00
A00
86 106Thursday, June 29, 2017
86 106Thursday, June 29, 2017
1
86 106Thursday, June 29, 2017
A00
Page 87
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
Reserved
1
87 106Thursday, June 29, 2017
87 106Thursday, June 29, 2017
87 106Thursday, June 29, 2017
A00
A00
A00
Page 88
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
Reserved
1
88 106Thursday, June 29, 2017
88 106Thursday, June 29, 2017
88 106Thursday, June 29, 2017
A00
A00
A00
Page 89
5
4
3
2
1
SSID = Unused Parts
2016/12/14 move from P.10 to P.89
34.4YW18.001
D D
SPR1
DY
SPRING-31-GP-U
1
34.49U24.001
SPR2
2017/03/21
DY
SPRING-31-GP-U
1
34.49U24.001
ZZ.00PAD.7F1
H2
HOLE335R178-GP
1
ZZ.00PAD.7F1
+VCCGT
2017/03/21
EC8905
DY
12
VCC_CORE
DY
EC8906
12
SC1U10V2KX-1DLGP
SCD1U25V2KX-L-GP
EMI reserve , 20141118
EC8902
EC8903
EC8904
12
SCD1U25V2KX-L-GP
SCD1U25V2KX-L-GP
DY
DY
12
12
SCD1U25V2KX-L-GP
DY
+VCCSA
DY
12
EC8907
SCD1U25V2KX-L-GP
DY
12
EC8901
SCD1U25V2KX-L-GP
H7
HOLE335R178-GP
1
ZZ.00PAD.7F1
H8
HOLE335R178-GP
1
ZZ.00PAD.7F1
H9
HOLE335R178-GP
1
ZZ.00PAD.7F1
H10
HOLE335R178-GP
1
ZZ.00PAD.7F1
Type-C
H1
HOLE335R178-GP
H3
HOLE335R178-GP
H5
HOLE335R178-GP
2016/11/7modify
C C
34.4SE26.201
HS1
STF237R113H62-10-GP
1
1
ZZ.00PAD.7F1
1
ZZ.00PAD.7F1
1
ZZ.00PAD.7F1
H6
HOLE335R178-GP
1
ZZ.00PAD.7F1
SSID = EMI
Mind the voltage rating of the caps.
12
EC8910
DY
SCD1U25V2KX-1-DL-GP
2017/03/21
EC8911
SCD1U25V2KX-1-DL-GP
12
12
DY
EC8912
SCD1U25V2KX-1-DL-GP
12
EC8913
SCD1U25V2KX-1-DL-GP
12
EC8914
EC8915
SCD1U25V2KX-1-DL-GP
12
DCBATOUT
EC8908
EC8909
SCD1U25V2KX-1-DL-GP
12
B B
SCD1U25V2KX-1-DL-GP
12
DY
SCD1U25V2KX-1-DL-GP
2017/03/21
EC8916
SCD1U25V2KX-1-DL-GP
12
12
EC8917
DY
5V_S5
SCD1U25V2KX-1-DL-GP
12
EC8918
SCD1U25V2KX-1-DL-GP
12
EC8919
EC8920
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
12
3D3V_S5
12
EC8921
SCD1U25V2KX-1-DL-GP
12
EC8922
SCD1U25V2KX-1-DL-GP
12
EC8923
SCD1U25V2KX-1-DL-GP
3D3V_S5
12
EC8924
SCD1U25V2KX-1-DL-GP
12
EC8925
SCD1U25V2KX-1-DL-GP
12
EC8926
SCD1U25V2KX-1-DL-GP
5V_S5
12
EC8927
EC8928
SCD1U25V2KX-1-DL-GP
12
EC8929
SCD1U25V2KX-1-DL-GP
12
1D2V_S3
EC8930
EC8931
EC8932
EC8933
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
12
SCD1U25V2KX-1-DL-GP
12
SCD1U25V2KX-1-DL-GP
12
12
EC8934
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
12
VCC_CORE
12
EC8937
SCD1U25V2KX-1-DL-GP
12
EC8938
SCD1U25V2KX-1-DL-GP
12
EC8936
SCD1U25V2KX-1-DL-GP
12
EC8935
SCD1U25V2KX-1-DL-GP
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
SSID = RF
DCBATOUT
12
FC8905
FC8906
SC4D7P50V2BN-2-GP
A A
3D3V_S5
FC8935
12
12
FC8936
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
12
FC8907
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
FC8937
SC4D7P50V2BN-2-GP
5
12
FC8909
FC8908
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
12
FC8939
FC8938
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
12
FC8910
FC8911
SC4D7P50V2BN-2-GP
12
12
FC8941
FC8943
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
12
FC8912
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
FC8940
SC4D7P50V2BN-2-GP
12
FC8913
FC8914
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
12
FC8944
FC8942
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
12
FC8915
FC8916
SC4D7P50V2BN-2-GP
4
12
12
FC8917
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
FC8918
FC8919
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
1D0V_S5
12
FC8945
SC4D7P50V2BN-2-GP
12
12
FC8920
FC8921
SC4D7P50V2BN-2-GP
12
12
FC8947
FC8946
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
12
12
FC8922
FC8923
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
FC8949
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
FC8948
SC4D7P50V2BN-2-GP
12
FC8924
SC4D7P50V2BN-2-GP
12
FC8951
FC8953
SC4D7P50V2BN-2-GP
12
12
FC8950
SC4D7P50V2BN-2-GP
3
12
12
FC8954
FC8952
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
5V_S5
12
FC8925
FC8926
SC4D7P50V2BN-2-GP
12
12
FC8927
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
12
12
FC8929
FC8928
FC8931
FC8933
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
2
12
12
12
FC8930
FC8934
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
SC4D7P50V2BN-2-GP
12
FC8932
SC4D7P50V2BN-2-GP
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
UNUSED PARTS/EMI Capacitors
UNUSED PARTS/EMI Capacitors
UNUSED PARTS/EMI Capacitors
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
89 106
89 106
89 106
1
A00
A00
A00
Page 90
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Reserved
Reserved
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
Reserved
1
90 106Thursday, June 29, 2017
90 106Thursday, June 29, 2017
90 106Thursday, June 29, 2017
A00
A00
A00
Page 91
5
4
3
2
1
SSID = TPM
3D3V_TPM
D D
1 2
3D3V_TPM
SPI_CS_ROM_N218
SPI_SO_ROM18,25
SPI_SI_ROM18,25
SPI_CLK_ROM18,25
R9140 10KR2J-3-GP
TPM2
1 2
R9130 0R2J-2-GP
TPM2
1 2
R9132 33R2J-2-GP
TPM2
1 2
R9133 33R2J-2-GP
TPM2
1 2
R9138 33R2J-2-GP
TPM2
SPI_CS2#_R_TPM2
SPI_SO_ROM_TPM2
SPI_SI_ROM_TPM2
SPI_CLK_ROM_TPM2
SPI_CS_ROM_N1
Q9103
S
DY
G
2N7002K-2-GP
12
R9125
DY
10KR2J-3-GP
D
TPM_GPIO2
TPM_GPIO2
R9124
10KR2J-3-GP
12
DY
84.2N702.J31
3D3V_TPM
R9149
DY
If not used, it is ok to left it unconnected
C C
3D3V_S0
3D3V_S5_PCH
R9145
TPM2
0R3J-0-U-GP
R9146
DY
0R3J-0-U-GP
12
12
12
TPM2
B B
2016/11/03
+UZ12_TPM
SC4D7U6D3V3KX-DLGP
C9109
3D3V_S5_PCH
D01R3F-L-GP
R9143
TPM2
3D3V_TPM
12
TPM2
R9144
12
SC4D7U6D3V3KX-DLGP
C9106
12
12
0R3J-0-U-GP
C9108
SCD1U16V2KX-3DLGP
TPM2
TPM2
TPM_VSB
3D3V_TPM
C9110
PLT_RST#17,26,63,66,99
12
TPM2
TPM_SPI_IRQ#
18
1 2
R9136 0R2J-2-GP
TPM2
10KR2J-3-GP
R9147 0R3J-0-U-GP
R9148 0R3J-0-U-GP
SCD1U16V2KX-3DLGP
2017/05/08
TPM2
TPM2
SPI_IRQ#_TPM2
12
12
12
1 2
R9137
0R2J-2-GP
+UZ12_TPM
TPM_VDD14
TPM_VDD22
SPI_SO_ROM_TPM2
SPI_SI_ROM_TPM2
TPM2
SPI_IRQ#_TPM2
PLT_RST#_Q_TPM2
SPI_CLK_ROM_TPM2
SPI_CS2#_R_TPM2
SERIRQ_TPM
EV Reseved for modern stanby
SIO_SLP_S0#17,24,40
U9102
8
VDD
1
VSB
14
VHIO
22
VHIO
24
LAD0/MISO
21
LAD1/MOSI
18
LAD2/SPI_IRQ#
15
LAD3
17
LRESET#/SPI_RST#/SRESET#
19
LCLK/SCLK
20
LFRAME#/SCS#
27
SERIRQ
28
LPCPD#
4
PP
5
TEST
12
RESERVED
CLKRUN#/GPIO4/SINT#
TPM2
DY
R9142
0R2J-2-GP
SDA/GPIO0
GPIO1/SCL
GPX/GPIO2
GPIO3/BADD
NC#2
NC#7
NC#10
NC#11
NC#25
NC#26
NC#31
GND
GND
GND
GND
GND
12
29
30
3
6
13
2
7
10
11
25
26
31
9
16
23
32
33
TPM_GPIO0
TPM_GPIO2
Q9102
DMP2130L-7-GP
D
D
G
DY
G
1 2
R9121
10KR2J-3-GP
1 2
R9120
10KR2J-3-GP
1 2
R9122
0R3J-0-U-GP
84.02130.031
Q9102.G
100R2F-L1-GP-U
TPM2
DY
S
DY
3D3V_TPM
1 2
R9123
DY
3D3V_S0
SPI_CS_ROM_N1TPM_GPIO4
SPI_CS_ROM_N1
12
R9141
10KR2J-3-GP
TPM2
A A
5
4
3
NPCT650JB2YX-GP
071.00650.0J03
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
TPM2.0
TPM2.0
TPM2.0
KyloRen 13"
KyloRen 13"
KyloRen 13"
A00
A00
A00
91 106Thursday, June 29, 2017
91 106Thursday, June 29, 2017
91 106Thursday, June 29, 2017
1
Page 92
5
4
3
2
1
SSID = FPR
FBR(finger Print Sensor)
FBR(Botton side finger Print Sensor)
2016/12/23 2016/12/23
3D3V_S53D3V_S0 3D3V_S53D3V_S0
2017/05/10
2016/11/03
R9203
DY
0R3J-0-U-GP
1 2
83.R2004.G8F
DY
D9201
RB751V-40H-GP
K A
FPR
1 2
R9204
D01R3F-L-GP
FPR_VDD1
D D
2016/12/09
C9907
12
SC1U10V2KX-1DLGP
FPR
FPR1
7
1
2
FPR
020.K0237.0006
C C
3
4
5
6
8
HRS-CON6-15-GP
FP1_USB20_CON_N
FP1_USB20_CON_P
FPR2
10
PWFPR
9
PTWO-CON8-11-GP
1
2
3
4
5
6
7
8
BFP1_USB20_CON_N
BFP1_USB20_CON_P
R9211
0R3J-0-U-GP
1 2
PWFPR
FPR_VDD2
12
PWFPR
FPR_SCAN# 24
2017/03/14
R9212
DY
0R3J-0-U-GP
1 2
2016/12/09
C9908
SC1U10V2KX-1DLGP
20.K0767.008
R9205
FP1_USB20_N16
FP1_USB20_P16
1 2
0R2J-2-GP
R9206
1 2
0R2J-2-GP
R9207
1 2
0R2J-2-GP
R9208
1 2
0R2J-2-GP
FPR
PWFPR
FPR
PWFPR
FP1_USB20_R_N
BFP1_USB20_R_N
FP1_USB20_R_P
BFP1_USB20_R_P
2016/12/15
B B
FP1_USB20_R_P
R9202
1 2
0R2J-2-GP
FPR
FP1_USB20_CON_P
BFP1_USB20_R_N
2017/03/16
FP1_USB20_R_N
R9201
1 2
0R2J-2-GP
FPR
FP1_USB20_CON_N
BFP1_USB20_R_P
R9209
1 2
0R2J-2-GP
PWFPR
2017/03/16
R9210
1 2
0R2J-2-GP
PWFPR
BFP1_USB20_CON_N
BFP1_USB20_CON_P
3
PWFPR
ED9202
2
1
AZ5315-02F-GP
83.05315.0A0
BFP1_USB20_CON_N
BFP1_USB20_CON_P
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
(Reserved)Finger Print
(Reserved)Finger Print
(Reserved)Finger Print
KyloRen 13"
KyloRen 13"
KyloRen 13"
92 106Thursday, June 29, 2017
92 106Thursday, June 29, 2017
92 106Thursday, June 29, 2017
1
A00
A00
A00
ED9201
FP1_USB20_CON_N
2
3
A A
FPR
1
AZ5315-02F-GP
FP1_USB20_CON_P
83.05315.0A0
5
4
3
Page 93
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
(Reserved)
1
93 106Thursday, June 29, 2017
93 106Thursday, June 29, 2017
93 106Thursday, June 29, 2017
A00
A00
A00
Page 94
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
(Reserved)
1
94 106Thursday, June 29, 2017
94 106Thursday, June 29, 2017
94 106Thursday, June 29, 2017
A00
A00
A00
Page 95
5
D D
4
3
2
1
C C
(Blanking)
B B
A A
5
4
3
2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
(Reserved)
1
95 106Thursday, June 29, 2017
95 106Thursday, June 29, 2017
95 106Thursday, June 29, 2017
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<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
(Reserved)
(Reserved)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
(Reserved)
1
96 106Thursday, June 29, 2017
96 106Thursday, June 29, 2017
96 106Thursday, June 29, 2017
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A00
A00
Page 97
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D D
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C C
(Blanking)
B B
<Core Design>
<Core Design>
A A
5
4
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<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
LVDS_Switch
LVDS_Switch
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
KyloRen 13"
KyloRen 13"
KyloRen 13"
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
LVDS_Switch
1
97 106
97 106
97 106
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A00
A00
Page 98
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D D
4
3
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C C
(Blanking)
B B
<Core Design>
<Core Design>
A A
5
4
3
2
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRT_Switch
CRT_Switch
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
CRT_Switch
KyloRen 13"
KyloRen 13"
KyloRen 13"
98 106
98 106
98 106
1
A00
A00
A00
Page 99
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SSID = Debug
D D
XDP_PREQ#
12
C9901
Layout Note:
ROUTE WITH MINIMAL STUB WITH RESPECT TO CFG<0>
CFG0
Layout Note:
ROUTE WITH MINIMAL STUB WITH RESPECT TO CFG<3>
CFG3
PCH_RSMRST#17,24
H_VCCST_PWRGD17
C C
SYS_PWROK17,24
SPI_SI_XDP
1 2
R9907
DY
R9902
1 2
XDP
1 2
R9904 1KR2J-1-GP
XDP
1 2
R9903 1KR2J-1-GP
DY
1 2
R9908 0R2J-2-GP
3D3V_S5
12
R9909
1K5R2J-3-GP
DY
12
R1828
1KR2J-1-GP
DY
FIVR_EN_R
1KR2J-1-GP
XDP_PRSNT_PIN1
1KR2J-1-GP
PM_RSMRST_PWRGD_XDP
DY
SCD1U16V2KX-3DLGP
CFG[19:0]6
PLACE WITHIN 1.1 INCH OF PCH
SPI_SI_XDP PCH_SPI_SI
PCH strap pin:
R1826
1 2
DY
1KR2J-1-GP
DY
11/27 JAIME
XDP_PREQ#16
XDP_PRDY#16
(#543016)Routing of this signal to CFG[0] is OPTIONAL.
(#543016)Optional, can be left as OPEN/No-Connect.
SIO_PWRBTN#17,24
XDP_PRDY#
CFG[19:0]
1
TP1021
C9903
12
SCD1U25V2KX-1-DL-GP
XDP
BOOT HALT
SPI0_MOSI
B B
This signal has a weak internal pull-up.
0 = ENABLED
1 = DISABLED
WEAK INTERNAL PU
1V_XDP_S5
12
DY
PCH_SMBDATA18
XDP_TCLK1
XDP_TCLK
XDP_TDO
01/27 JAIME
R9934
51R2J-2-GP
XDP_BPM04
XDP_BPM14
PCH_SMBCLK18
XDP_PRSNT_PIN1
CFG0
CFG1
CFG2
CFG3
XDP_BPM0
XDP_BPM1
CFG4
CFG5
CFG6
CFG7
PM_RSMRST_PWRGD_XDP
+V1.00A_CPU_XDP_AB
SPI_SI_XDP
XDP_TCLK1
XDP_TCLK
EE Note:
Use ZZ.00PAD.Q81 DUMMY PAD for MP.
(#544669)
1 2
R9914 0R2J-2-GP
XDP
1 2
R9915 0R2J-2-GP
XDP
1 2
R9920 0R2J-2-GP
CPU XDP
XDP1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
XDP
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
PAD-60P-GP
ZZ.00PAD.Q81
NP1
61
62
63
64
NP2
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
+V1.00A_CPU_XDP_AB
TP_PMODE_XDP_RST_R_NFIVR_EN_R
XDP_TDO
SPI_WP_XDP
2017/05/08
PCH_JTAG_TCK 4
XDP_TCK_JTAGX 4
PCH_JTAG_TDO 4
01/30 JAIME
PLACE WITHIN 1.1INCH NEAR CPU XDP CONNECTOR
PCIE_CLK_XDP_P 18
PCIE_CLK_XDP_N 18
XDP_TRST# 4
PCH_JTAG_TDI 4
PCH_JTAG_TMS 4
1 2
R1827 1KR2J-1-GP
XDP
1 2
SPI_WP_ROM 18,25
ITP_PMODE6
1D0V_S5
C9905
SCD1U25V2KX-1-DL-GP
XDP
XDP_DBRESET# 17
1V_XDP_S5
12
XDP
XDP
1 2
R9901 0R2J-2-GP
PH in P.17
R9932
1K5R2J-3-GP
PLT_RST#17,26,63,66,91
1V_XDP_S5
R9905
12
C9902
DY
SCD1U16V2KX-3DLGP
(#544669 Rev0.52) NC.
R9933
1 2
XDP
0R2J-2-GP
R9930
1 2
DY
1KR2J-1-GP
0R2J-2-GP
XDP
1 2
TP_PMODE_XDP_RST_R_N
+V1.00A_CPU_XDP_AB
Close to Pin43
XDP
01/27 JAIME
+VCCIO
12
R9906
150R2J-L1-GP-U
A A
5
DY
FIVR_EN_R
SPI_SI_XDP18
4
3
2
3D3V_S5
12
XDP
R9936
3KR2J-2-GP
C9906
XDP
SCD1U25V2KX-1-DL-GP
1 2
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Thursday, June 29, 2017
Thursday, June 29, 2017
Thursday, June 29, 2017
Date: Sheet of
Date: Sheet of
Date: Sheet of
CPU_XDP;PCH_XDP
CPU_XDP;PCH_XDP
CPU_XDP;PCH_XDP
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
99 106
99 106
99 106
A00
A00
A00
Page 100
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CLK Block Diagram
Intel CPU
D D
Haswell/Broadwell ULT
CK0
CK0#
M_A_DIMA_CLK_DDR0
M_A_DIMA_CLK_DDR#0
SA_CLK0
SA_CLK#0
DDR3L DIMM1
CK1
CK1# CLK_PCIE_WLAN_P3
M_A_DIMA_CLK_DDR1
M_A_DIMA_CLK_DDR#1
SA_CLK1
SA_CLK#1
CLKOUT_PCIE_P2
CLKOUT_PCIE_N2
CLK_PCIE_WLAN_N3
REFCLKP0
REFCLKN0
WLAN
NGFF
LAN
CLKOUT_PCIE_P3
C C
VRAM1
VRAM2
VRAM3
VRAM4
B B
CK
CK#
CK
CK#
CK
CK#
CK
CK#
FBA_CLK0P
FBA_CLK0N
FBA_CLK0P
FBA_CLK0N
FBA_CLK1P
FBA_CLK1N
FBA_CLK1P
FBA_CLK1N
‧
‧
‧
‧
VGA
N15V-GM-S-A2
GB2-64 (23x23)
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
PEX_REFCLK#
XTAL_IN
XTAL_OUT
CLK_PCIE_VGA#
CLK_PCIE_VGA
27MHZ_IN
27MHZ_OUT
X1901
32.768KHz
X7601
27MHz
RTC_X1
CLKOUT_PCIE_N3
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4PEX_REFCLK
HDA_BITCLK
RTCX1
CLK_PCIE_LAN_P4
CLK_PCIE_LAN_N4
X3001
25MHz
RN2102
SRN33J-5-GP-U
HDA_CODEC_BITCLK
LANXIN
LANXOUT
R5815
0R2J-2-GP
RTL8106E/RTL8111G
REFCLK_P
REFCLK_N
CKXTAL1
CKXTAL2
Audio
Realtek
BITCLKHDA_BCLK/I2S0_SCLK
SUSCLK_NGFF
ALC3223
SUS_CLK
NGFF
RTC_X2
XTAL24_IN
X1801
24MHz
XTAL24_OUT
A A
5
4
RTCX2
XTAL24_IN
XTAL24_OUT
KBC
NPCE285P
SUS_CLK_PCH
CLKOUT_LPC_1 LCLK/GPIOF5
CLKOUT_LPC_0 CLK_PCI_LPC
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
3
CLK_PCI_KBC_R
CLK_PCI_LPC_R
R1710
SUS_CLK
0R2J-2-GP
R1805
0R2J-2-GP
R1804
0R2J-2-GP
Test Point
2
‧
R2441
0R2J-2-GP
CLK_PCI_KBC
SUS_CLK_KBC
LPC
GPIO0/EXTCLK/F_SDIO3SUSCLK/GPIO62
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
CLK Block Diagram
CLK Block Diagram
CLK Block Diagram
KyloRen 13"
KyloRen 13"
KyloRen 13"
1
100 106Thursday, June 29, 2017
100 106Thursday, June 29, 2017
100 106Thursday, June 29, 2017
A00
A00
A00
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