Page 1
Features
Typ e R
DS(on)
VN750PS-E 60 mΩ 6A 36V
I
OUT
VN750PS-E
High-side driver
V
CC
■ ECOPACK
■ Automotive Grade: compliance with AEC
®
: lead free and RoHS compliant
guidelines
■ CMOS compatible input
■ On-state open-load detection
■ Off-state open-load detection
■ Shorted load protection
■ Undervoltage and overvoltage shutdown
■ Protection against loss of ground
■ Very low standby current
■ Reverse battery protection
SO-8
Description
The VN750PS-E is a monolithic device designed
in STMicroelectronics™ VIPower™ M0-3
Technology intended for driving any kind of load
with one side connected to ground.
Active V
against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
combined with thermal shutdown and automatic
restart help protect the device against overload.
The device detects open load condition in on and
off-state. Output shorted to V
off-state. Device automatically turns off in case of
ground pin disconnection.
pin voltage clamp protects the device
CC
is detected in the
CC
Table 1. Device summary
Order codes
Package
Tube Tape and reel
SO-8 VN750PS-E VN750PSTR-E
October 2010 Doc ID 16782 Rev 2 1/27
www.st.com
1
Page 2
Contents VN750PS-E
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
2.6 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9 SO-8 maximum demagnetization energy (V
= 13.5 V) . . . . . . . . . . . . . 19
CC
3 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27 Doc ID 16782 Rev 2
Page 3
VN750PS-E List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Electrical transient requirements on V
Table 8. Electrical transient requirements on V
Table 9. Electrical transient requirements on V
Table 10. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Doc ID 16782 Rev 2 3/27
Page 4
List of figures VN750PS-E
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. On-state resistance vs T
Figure 14. On-state resistance vs V
Figure 15. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Open-load off-state voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. I
lim
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
case
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. SO-8 maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 28. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 30. Thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 31. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
4/27 Doc ID 16782 Rev 2
Page 5
VN750PS-E Block diagram and pin description
1 Block diagram and pin description
Figure 1. Block diagram
V
CC
V
CC
CLAMP
OVERVOLTAGE
GND
INPUT
STATUS
OVER TEMPERATURE
DETECTION
LOGIC
AND OUTPUT SHORTED TO V
Figure 2. Configuration diagram (top view)
V
CC
OUTPUT
OUTPUT
V
CC
5
8
DETECTION
UNDERVOLTAGE
DETECTION
Power CLAMP
DRIVER
CURRENT LIMITER
ON-STATE OPEN-LOAD
DETECTION
OFF-STATE OPEN-LOAD
DETECTION
4
N.C.
STATUS
INPUT
1
GND
OUTPUT
CC
SO-8
Table 2. Suggested connections for unused and not connected pins
Connection/pin Status N.C. Output Input
Floating X X X X
To ground X Through 10 KΩ resistor
Doc ID 16782 Rev 2 5/27
Page 6
Electrical specifications VN750PS-E
2 Electrical specifications
Figure 3. Current and voltage conventions
I
S
V
I
IN
INPUT
I
STAT
STATUS
V
IN
V
STAT
2.1 Absolute maximum ratings
V
CC
GND
OUTPUT
I
GND
F
I
OUT
V
CC
V
OUT
Stress values that exceed those listed in the “Absolute maximum ratings” table can cause
permanent damage to the device. These are stress ratings only and operation of the device
at these or any other conditions greater than those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics sure program and
other relevant quality documents.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
-V
CC
-I
gnd
I
OUT
-I
OUT
I
IN
I
STAT
V
ESD
DC supply voltage 41 V
Reverse DC supply voltage - 0.3 V
DC reverse ground pin current - 200 mA
DC output current Internally limited A
Reverse DC output current - 6 A
DC input current +/-10 mA
DC status current +/- 10 mA
Electrostatic discharge
(human body model: R = 1.5 KΩ; C=100pF)
- Input
- Status
- Output
- V
CC
4000
4000
5000
5000
V
V
V
V
6/27 Doc ID 16782 Rev 2
Page 7
VN750PS-E Electrical specifications
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Maximum switching energy
E
MAX
P
T
T
(L = 1.8 mH; R
T
= 150 °C; IL=9A)
jstart
tot
T
j
c
stg
Power dissipation TC=25°C 4.2 W
Junction operating temperature Internally limited °C
Case operating temperature - 40 to 150 °C
Storage temperature - 55 to 150 °C
=0Ω; V
L
=13.5V;
bat
100 mJ
2.2 Thermal data
Table 4. Thermal data
Symbol Parameter Max. value Unit
R
thj-lead
R
thj-amb
1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected
to all VCC pins. Horizontal mounting and no artificial air flow.
2. When mounted on a standard single-sided FR-4 board with 2 cm2 of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.
Thermal resistance junction-lead 30 °C/W
(1)
93
Thermal resistance junction-ambient
82
(2)
°C/W
°C/W
Doc ID 16782 Rev 2 7/27
Page 8
Electrical specifications VN750PS-E
2.3 Electrical characteristics
Values specified in this section are for 8 V < VCC<36V; -40 °C < T
otherwise stated.
CC
OV
ON
S
IL
IL
IH
/dt
/dt
Operating supply voltage 5.5 13 36 V
Undervoltage shutdown 3 4 5.5 V
Undervoltage shutdown
hysteresis
Overvoltage shutdown 36 V
On-state resistance
Supply current
Off-state output current VIN=V
Off-state output current VIN=0V; V
Off-state output current
Off-state output current
=13V)
CC
Turn-on delay time
Turn-off delay time
Turn-on voltage slope
(on)
Turn-off voltage slope
(off)
Input low level 1.25 V
Low level input current VIN=1.25V 1 µA
Input high level 3.25 V
Table 5. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
Power
V
V
USD
V
USDhyst
V
R
I
I
L(off1)
I
L(off2)
I
L(off3)
I
L(off4)
Switching (V
t
d(on)
t
d(off)
dV
OUT
dV
OUT
Input pin
V
I
V
<150°C, unless
j
0.5 V
I
=2A; Tj=25°C;
OUT
>8V
V
CC
=2A; VCC>8 V 120 mΩ
I
OUT
Off-state; VCC=13V;
VIN=V
Off-state; V
V
IN=VOUT
On-state; V
VIN=5V; I
V
IN=VOUT
=125°C
T
j
V
IN=VOUT
=25°C
T
j
R
=6.5Ω from VIN rising
L
edge to V
=6.5Ω from VIN falling
R
L
edge to V
=6.5Ω from V
R
L
to V
OUT
R
=6.5Ω from V
L
to V
OUT
=0V
OUT
=13V;
CC
=0V; Tj= 25 °C
=13V;
CC
=0A
OUT
=0V 0 50 µA
OUT
=3.5V -75 0 µA
OUT
=0V; VCC=13V;
=0V; VCC=13V;
=1.3V
OUT
= 11.7 V
OUT
OUT
=10.4V
=1.3V
OUT
=1.3V
= 11.7 V
10 25 µA
10 20 µA
23.5mA
40 µs
30 µs
See Figure 21 V/µs
See Figure 22 V/µs
60 mΩ
5µA
3µA
8/27 Doc ID 16782 Rev 2
Page 9
VN750PS-E Electrical specifications
Table 5. Electrical characteristics (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
IH
V
hyst
V
ICL
V
output diode
CC
V
F
Status pin
V
STAT
I
LSTAT
C
STAT
V
SCL
Protections
T
TSD
T
R
T
hyst
t
SDL
High level input current VIN=3.25V 10 µA
Input hysteresis voltage 0.5 V
I
=1mA 6 6.8 8 V
Input clamp voltage
Forward on voltage -I
Status low output voltage I
Status leakage current Normal operation; V
Status pin input capacitance Normal operation; V
Status clamp voltage
(1)
IN
=-1mA -0.7 V
I
IN
= 1.3 A; Tj= 150 °C 0.6 V
OUT
=1.6mA 0.5 V
STAT
=5V 10 µA
STAT
= 5 V 100 pF
STAT
I
=1mA 6 6.8 8 V
STAT
I
=-1mA -0.7 V
STAT
Shutdown temperature 150 175 200 °C
Reset temperature 135 °C
Thermal hysteresis 7 15 °C
Status delay in overload
condition
T
j>Tjsh
20 ms
I
V
demag
lim
Current limitation
Turn-off output clamp
voltage
5V<V
I
OUT
<36 V 15 A
CC
=2A; VIN=0V;
L=6mH
-41 VCC-48 VCC-55 V
V
CC
Open-load detection
9V<VCC<36 V 6 9 15 A
I
OL
t
DOL(on)
V
OL
t
DOL(off)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device operates under abnormal conditions this software must
limit the duration and number of activation cycles.
Open-load on-state
detection threshold
Open-load on-state
detection delay
Open-load off-state voltage
detection threshold
Open-load detection delay at
turn-off
V
= 5 V 50 200 mA
IN
= 0 A 200 µs
I
OUT
=0V 1.5 3.5 V
V
IN
1000 µs
Doc ID 16782 Rev 2 9/27
Page 10
Electrical specifications VN750PS-E
Figure 4. Status timings
OPEN-LOAD STATUS TIMING (with external pull-up)
OL
I
OUT
t
DOL(on)
V
V
IN
STAT
t
DOL(off)
V
> V
OUT
Figure 5. Switching time waveforms
V
OUT
80%
dV
/dt
OUT
(on)
V
IN
t
d(on)
< I
OL
10%
V
OVERTEMP STATUS TIMING
Tj > T
V
IN
STAT
t
SDL
90%
dV
t
d(off)
OUT
jsh
t
SDL
/dt
(off)
t
Table 6. Truth table
Conditions Input Output Status
Normal operation
L
H
L
Current limitation
H
H
Over temperature
Undervoltage
Overvoltage
L
H
L
H
L
H
10/27 Doc ID 16782 Rev 2
t
L
H
L
X
X
L
L
L
L
L
L
(T
(T
< T
j
> T
j
H
H
H
TSD
H
L
X
X
H
H
TSD
) H
) L
Page 11
VN750PS-E Electrical specifications
Table 6. Truth table (continued)
Conditions Input Output Status
Output voltage > V
Output current < I
Table 7. Electrical transient requirements on VCC pin (part 1/3)
OL
OL
L
H
L
H
H
H
L
H
Test levels
ISO T/R 7637/1
test pulse
I II III IV
1 -25 V -50 V -75 V -100 V 2 ms 10 Ω
2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω
4 -4 V -5 V -6 V -7 V 100 ms, 0.01 Ω
5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2
Table 8. Electrical transient requirements on VCC pin (part 2/3)
ISO T/R 7637/1
test pulse
I II III IV
Test levels results
L
H
H
L
Delays and
impedance
Ω
1CCCC
2CCCC
3aCCCC
3bCCCC
4CCCC
5C E E E
Table 9. Electrical transient requirements on VCC pin (part 3/3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device is not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 16782 Rev 2 11/27
Page 12
Electrical specifications VN750PS-E
Figure 6. Waveforms
NORMAL OPERATION
INPUT
LOAD VOLTAGE
STATUS
UNDERVOLTAGE
V
CC
INPUT
LOAD VOLTAGE
V
USD
V
USDhyst
STATUS
V
CC
INPUT
LOAD VOLTAGE
STATUS
INPUT
LOAD VOLTAGE
STATUS
INPUT
LOAD VOLTAGE
STATUS
undefined
OVERVOLTAGE
V
CC<VOV
V
CC>VOV
OPEN LOAD with external pull-up
V
OUT>VOL
V
OL
OPEN LOAD without external pull-up
T
T
j
TSD
T
R
OVER TEMPERATURE
INPUT
LOAD CURRENT
STATUS
12/27 Doc ID 16782 Rev 2
Page 13
VN750PS-E Electrical specifications
2.4 Electrical characteristics curves
Figure 7. Off-state output current Figure 8. High level input current
IL(off1) (uA)
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-50 -25 0 25 50 75 100 125 150 175
Off state
Vcc=36V
Vin=Vout=0V
Tc (ºC)
Figure 9. Input clamp voltage Figure 10. Status leakage current
Vicl (V)
8
7.8
7.6
7.4
7.2
6.8
6.6
6.4
6.2
Iin=1mA
7
6
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Iih (uA)
7
6
Vin=3.25V
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
Ilstat (uA)
0.05
0.04
Vstat=5V
0.03
0.02
0.01
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 11. Status low output voltage Figure 12. Status clamp voltage
Vstat (V)
0.6
0.5
Istat=1.6mA
0.4
0.3
0.2
0.1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
Doc ID 16782 Rev 2 13/27
Vscl (V)
8
7.8
7.6
Istat=1mA
7.4
7.2
7
6.8
6.6
6.4
6.2
6
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Page 14
Electrical specifications VN750PS-E
Figure 13. On-state resistance vs T
case
Ron (mOhm)
140
120
100
80
60
40
20
0
-50 -25 0 25 50 75 100 125 150 175
Iout=2A
Vcc=8V; 13V; 36V
Tc (ºC)
Figure 15. Open-load on-state detection
threshold
Iol (mA)
220
200
180
160
140
120
100
80
60
40
20
0
-50 -25 0 25 50 75 100 125 150 175
Vcc=13V
Vin=5V
Tc (ºC)
Figure 14. On-state resistance vs V
CC
Ron (mOhm)
120
110
100
90
80
70
60
50
40
30
20
5 10152025303540
Iout=2A
Tc= 150°C
Tc= 125°C
Tc= 25°C
Tc= - 40°C
Vcc (V)
Figure 16. Input high level
Vih (V)
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
-50 -25 0 25 5 0 75 100 125 150 175
Tc (ºC)
Figure 17. Input low level Figure 18. Input hysteresis voltage
Vil (V)
2.8
2.6
2.4
2.2
2
1.8
1.6
14/27 Doc ID 16782 Rev 2
1.4
1.2
1
-50 -25 0 25 5 0 75 100 125 150 175
Tc (ºC)
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50 -25 0 25 5 0 75 100 125 1 50 175
Tc (ºC)
Page 15
VN750PS-E Electrical specifications
Figure 19. Overvoltage shutdown Figure 20. Open-load off-state voltage
detection threshold
Vov (V)
50
48
46
44
42
40
38
36
34
32
30
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Vol (V)
5
4.5
4
3.5
3
2.5
2
1.5
1
Vin=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope
dVout/dt/(on) (V/ms)
1000
900
800
700
600
500
400
300
200
100
Vcc=13V
Rl=6.5Ohm
0
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
dVout/dt(off) (V/ms)
500
450
400
350
300
250
200
150
100
50
0
-50 -25 0 25 50 75 100 125 150 17 5
Vcc=13V
Rl=6.5Ohm
Tc (ºC)
Figure 23. I
lim
vs T
case
Ilim (A)
20
18
16
14
12
10
8
6
4
2
0
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
Doc ID 16782 Rev 2 15/27
Page 16
Electrical specifications VN750PS-E
Figure 24. Application schematic
+5V
μ
C
+5V
GND
GND
V
CC
OUTPUT
D
GND
R
prot
STATUS
R
prot
INPUT
V
R
GND
2.5 GND protection network against reverse battery
Solution 1: resistor in the ground line (R
The following is an indication on how to dimension the R
1. R
2. R
where -I
≤ 600 mV / (I
GND
≥ (−VCC) / (−I
GND
is the DC reverse ground pin current and can be found in the absolute
GND
S(on)max
GND
).
)
maximum rating section of the device datasheet.
only). This can be used with any type of load.
GND
resistor.
GND
D
ld
Power dissipation in R
P
= (−VCC)2/R
D
GND
(when VCC< 0: during reverse battery situations) is:
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
produces a shift (I
GND
S(on)max
* R
GND
values. This shift varies depending on how many devices are on in the case of several high
side drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize solution 2 (see below).
Solution 2: diode (D
parallel to D
if the device drives an inductive load.
GND
) in the ground line A resistor (R
GND
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600 mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
16/27 Doc ID 16782 Rev 2
S(on)max
becomes the sum of the
) in the input thresholds and the status output
=1 kΩ) should be inserted in
GND
Page 17
VN750PS-E Electrical specifications
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
Series resistor in input and status lines are also required to prevent that, during battery
voltage transient, the current exceeds the absolute maximum rating.
Safest configuration for unused input and status pin is to leave them unconnected.
2.6 Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
V
max DC rating. The same applies if the device is subject to transients on the VCC line
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
2.7 Microcontroller I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the microcontroller I/O pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
) in line to
prot
-V
CCpeak/Ilatchup
≤ R
prot
≤ (V
OHµC-VIH-VGND
Calculation example:
For V
CCpeak
5kΩ ≤ R
Recommended values: R
= - 100 V and I
≤ 65 kΩ.
prot
latchup
=10kΩ.
prot
≥ 20 mA; V
2.8 Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between
output pin and a positive supply voltage (V
microprocessor.
The external resistor has to be selected according to the following requirements:
1. no false open-load indication when load is connected: in this case we have to avoid
V
to be higher than V
OUT
V
=(VPU/(RL+RPU))RL<V
OUT
2. no misdetection when load is disconnected: in this case the V
V
Because I
up resistor R
standby.
The values of V
; this results in the following condition RPU<(VPU–V
OLmax
may significantly increase if V
s(OFF)
should be connected to a supply that is switched off when the module is in
PU
, V
OLmin
OLmax
section.
; this results in the following condition
Olmin
and I
) / I
IHmax
≥ 4.5 V
OHµC
) like the +5V line used to supply the
PU
.
Olmin
has to be higher than
OUT
)/I
OLmax
is pulled high (up to several mA), the pull-
out
are available in the electrical characteristics
L(off2)
L(off2)
.
Doc ID 16782 Rev 2 17/27
Page 18
Electrical specifications VN750PS-E
Figure 25. Open-load detection in off-state
V batt. VPU
V
CC
R
PU
INPUT
STATUS
DRIVER
+
LOGIC
+
-
V
OL
GROUND
R
OUT
I
L(off2)
R
L
18/27 Doc ID 16782 Rev 2
Page 19
VN750PS-E Electrical specifications
2.9 SO-8 maximum demagnetization energy (VCC = 13.5 V)
Figure 26. SO-8 maximum turn-off current versus inductance
LMAX (A)
I
100
10
A
B
C
VIN, I
A: T
B: T
C: T
L
1
0.1 1 10 100
L(mH)
= 150 °C single pulse
jstart
= 100 °C repetitive pulse
jstart
= 125 °C repetitive pulse
jstart
Demagnetization Demagnetization Demagnetization
t
Note:
Values are generated with R
must not exceed the temperature specified above for curves A and B.
=0Ω.In case of repetitive pulses, T
L
(at beginning of each demagnetization) of every pulse
jstart
Doc ID 16782 Rev 2 19/27
Page 20
Package and PCB thermal data VN750PS-E
3 Package and PCB thermal data
3.1 SO-8 thermal data
Figure 27. PC board
Note:
Layout condition of R
thickness=35 µm, Copper areas: 0.14 cm
Figure 28. R
RT Hj _ a m b ( º C /W)
and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu
th
vs PCB copper area in open box free air condition
thj-amb
110
105
100
2
, 0.8 cm2, 2 cm2).
.
SO-8 at 2 pins connected to TAB
95
90
85
80
75
70
00.511.522.5
PCB Cu heatsink area (cm^2)
20/27 Doc ID 16782 Rev 2
Page 21
VN750PS-E Package and PCB thermal data
Figure 29. SO-8 thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
2
100
0.5 cm
2 cm
2
10
1
0.1
0.01
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Equation 1: pulse calculation formula
Z
THδ
where δ = t
Figure 30. Thermal fitting model of a single channel
R
TH
P
δ Z
/T
THtp
1 δ–()+⋅=
Doc ID 16782 Rev 2 21/27
Page 22
Package and PCB thermal data VN750PS-E
Table 10. Thermal parameter
Area/island (cm2)0.52
R1 (°C/W) 0.05
R2 (°C/W) 0.8
R3 (°C/W) 3.5
R4 (°C/W) 21
R5 (°C/W) 16
R6 (°C/W) 58 28
C1 (W·s/°C) 0.006
C2 (W·s/°C) 0.0026
C3 (W·s/°C) 0.0075
C4 (W·s/°C) 0.045
C5 (W·s/°C) 0.35
C6 (W·s/°C) 1.05 2
22/27 Doc ID 16782 Rev 2
Page 23
VN750PS-E Package and packing information
4 Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
4.1 SO-8 package information
Figure 31. SO-8 package dimensions
0016023 D
Doc ID 16782 Rev 2 23/27
Page 24
Package and packing information VN750PS-E
Table 11. SO-8 mechanical data
mm
Dim.
Min. Typ. Max.
A 1.75
A1 0.10 0.25
A2 1.25
b 0.28 0.48
c 0.17 0.23
(1)
D
E 5.80 6.00 6.20
(2)
E1
e 1.27
h 0.25 0.50
L 0.40 1.27
L1 1.04
k 0° 8°
ccc 0.10
4.80 4.90 5.00
3.80 3.90 4.00
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
24/27 Doc ID 16782 Rev 2
Page 25
VN750PS-E Package and packing information
4.2 SO-8 packing information
The devices can be packed in tube or tape and reel shipments (see the Device summary on
page 1).
Figure 32. SO-8 tube shipment (no suffix)
B
C
A
Figure 33. SO-8 tape and reel shipment (suffix “TR”)
Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A 3.2
B 6
C (± 0.1) 0.6
All dimensions are in mm.
Reel dimensions
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
All dimensions are in mm.
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (+0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
End
Start
Top
cover
tape
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
No componentsNo components Components
500mm min
Doc ID 16782 Rev 2 25/27
Page 26
Revision history VN750PS-E
5 Revision history
Table 12. Document revision history
Date Revision Changes
23-Nov-2009 1 Initial release.
Updated Table 4: Thermal data
15-Oct-2010 2
Updated following figure titles:
– Figure 21: Turn-on voltage slope
– Figure 22: Turn-off voltage slope
26/27 Doc ID 16782 Rev 2
Page 27
VN750PS-E
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Doc ID 16782 Rev 2 27/27
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