Datasheet VN5E050J-E Datasheet (ST)

Features

VN5E050J-E

Single channel high side driver for automotive applications

Max supply voltage V

Operating voltage range V

Max on-state resistance (per ch.) R

Current limitation (typ) I

Off state supply current I

1. Typical value with all loads connected.

■ General

CC

CC

ON

LIMH

S

4.5 to 28V

– Inrush current active management by

power limitation
– Very low stand-by current
– 3.0V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC

european directive

■ Diagnostic functions

– Open Drain status output
– On-state open load detection
– Off-state open load detection
– Output short to V

detection

CC

– Overload and short to ground (power

limitation) indication
– Thermal shutdown indication

■ Protections

– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self-limiting of fast thermal transients
– Protection against loss of ground and loss

of V

CC

– Over-temperature shutdown with

autorestart (thermal shutdown)

– Reverse battery protected

(a)

– Electrostatic discharge protection

41V

50 mΩ

27A

2 µA

(1)

PowerSSO-12

Application

■ All types of resistive, inductive and capacitive

loads.

Description

The VN5E050J-E is a single channel high-side
driver manufactured in the ST proprietary
VIPower M0-5 technology and housed in the tiny
PowerSSO-12 package.

The VN5E050J-E is designed to drive automotive
grounded loads delivering protection, diagnostics
and easy 3V and 5V CMOS-compatible interface
with any microcontroller.

The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, over-temperature shut-off with auto­restart and over-voltage active clamp.

A dedicated active low digital status pin is
associated with every output channel in order to
provide Enhanced diagnostic functions including
fast detection of overload and short-circuit to
ground, over-temperature indication, short-circuit
to V

diagnosis and ON & OFF state open-load

CC

detection.

The diagnostic feedback of the whole device can
be disabled by pulling the STAT_DIS pin up, thus
allowing wired-ORing with other similar devices.

a. See Application schematic.

February 2008 Rev 2 1/34

www.st.com

34

Contents VN5E050J-E

Contents

1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22

3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 22

3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 23

3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.4 Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 25

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2/34

VN5E050J-E List of tables

List of tables

Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7. Status pin (VSD=0V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 8. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 9. Openload detection (8V<V

Table 10. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 14. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CC

3/34

List of figures VN5E050J-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9. Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. Open Load with external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 12. Open Load without external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13. Short to V
Figure 14. T

evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

J

Figure 15. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 17. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20. Low level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 21. On state resistance vs T

Figure 22. High level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 23. On state resistance vs V

Figure 24. Low level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25. I

LIM

vs T

Figure 26. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 27. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 28. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 29. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 30. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 31. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 33. Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 34. Maximum turn-Off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 36. Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 26

Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 27

Figure 38. Thermal fitting model of a single channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 27

Figure 39. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 40. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

case

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

case

4/34

VN5E050J-E Block diagram and pin configuration

1 Block diagram and pin configuration

Figure 1. Block diagram

V

CC

Signal C lamp

Undervoltage

IN

ST_
DIS

ST

LOG IC

C ontrol & Diagnostic

DRIV ER

Over

te m p .

OVERLOAD PR OTECTION

(AC TIVE P OW ER LIMITATION)

Table 1. Pin function

Name Function

Current

L im itatio n

Power
Clamp

V

ON

L im ita tion

OFF State
Open load

ON State

Open load

OUT

GND

V

CC

Battery connection.

OUTPUT Power output.

GND

INPUT

Ground connection. Must be reverse battery protected by an external
diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible.
Controls output switch state.

STATUS Open Drain digital diagnostic pin.

STAT_DIS Active high CMOS compatible pin, to disable the STATUS pin.

5/34

Block diagram and pin configuration VN5E050J-E

Figure 2. Configuration diagram (top view)

TAB = V

NC

GND

INPUT

STAT_DIS

STATUS

N.C.

1
2
3
4
5

6

12
11
10

9
8
7

cc

N.C.
OUTPUT

OUTPUT
OUTPUT
OUTPUT

N.C.

Table 2. Suggested connections for unused and not connected pins

Connection / pin Status N.C. Output Input STAT_DIS

Floating X X X X X

To ground

Not

allowed

X

Not

allowed

Through 10KΩ

resistor

Through 10KΩ

resistor

6/34

VN5E050J-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

I

S

V

CC

V

V

F

CC

I

SD

V

Note: V

F

= V

OUT

- V

SD

CC

I

IN

V

IN

INPUT

during reverse battery condition.

2.1 Absolute maximum ratings

Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in the “Absolute maximum
ratings” tables for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.

Table 3. Absolute maximum ratings

GND

OUTPUT STAT_DIS

STATUS

I

GND

I

OUT

I

STAT

V

STAT

V

OUT

Symbol Parameter Value Unit

V

-V

-I

GND

I

OUT

-I

I

STAT

I

STAT_DIS

E

DC supply voltage 41 V

CC

Reverse DC supply voltage 0.3 V

CC

DC reverse ground pin current 200 mA

DC output current Internally limited A

Reverse DC output current 15 A

OUT

DC input current +10 / -1 mA

I

IN

DC status current +10 / -1 mA

DC status disable current +10 / -1 mA

Maximum switching energy

MAX

(L=3mH; R

=0Ω; V

L

=13.5V; T

bat

jstart

=150ºC; I

OUT

= I

limL

(Typ.) )

104 mJ

7/34

Electrical specifications VN5E050J-E

Table 3. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Electrostatic discharge
(Human Body Model: R=1.5KΩ; C=100pF)

4000
4000
4000
5000
5000

V
V
V
V
V

V

V

ESD

ESD

T

- INPUT

- STATUS

- STAT_DIS

- OUTPUT

- V

CC

Charge device model (CDM-AEC-Q100-011) 750 V

Junction operating temperature -40 to 150 °C

T

j

Storage temperature - 55 to 150 °C

stg

2.2 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

R

thj-case

R

thj-amb

Thermal resistance junction-case (max)
(with one channel ON)

2.7 °C/W

Thermal resistance junction-ambient (max) See Figure 36 °C/W

8/34

VN5E050J-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8V<VCC<28V; -40°C< Tj <150°C, unless otherwise
stated.

Table 5. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

USDhyst

R

V

clamp

Operating supply voltage 4.5 13 28 V

CC

Undervoltage shutdown 3.5 4.5 V

USD

Undervoltage shutdown
hysteresis

I

=2A; Tj=25°C

OUT

On state resistance

ON

=2A; Tj=150°C

I

OUT

I

=2A; VCC=5V; Tj=25°C

OUT

Clamp voltage IS = 20 mA 41 46 52 V

Off State; V
V

I

I

L(off1)

Supply current

S

Off state output current

IN=VOUT

On State; VIN=5V; VCC=13V;

=0A

I

OUT

V

IN=VOUT

Tj=25°C
V

IN=VOUT

Tj=125°C

V

1. PowerMOS leakage included.

Output - VCC diode voltage -I

F

=2A; Tj=150°C 0.7 V

OUT

Table 6. Switching (VCC=13V; Tj=25°C)

=13V;

CC

=0V; Tj=25°C

=0V; VCC=13V;

=0V; VCC=13V;

0.5 V

100

(1)

2

5

3

000.01 3

50

65

(1)

6µAmA

5

mΩ
mΩ
mΩ

µA
µA

Symbol Parameter Test conditions Min. Typ. Max. Unit

dV

dV

t

d(on)

t

d(off)

OUT

OUT

W

W

ON

OFF

Turn-On delay time RL=6.5Ω (see Figure 6.)20µs

Turn-Off delay time RL=6.5Ω (see Figure 6.)40µs

Turn-On voltage

/dt

(on)

slope

Turn-Off voltage

/dt

(off)

slope

Switching energy
losses during t

Switching energy
losses during twoff

=6.5Ω

R

L

=6.5Ω

R

L

RL=6.5Ω (see Figure 6.)0.21mJ

won

RL=6.5Ω (see Figure 6.)0.28mJ

See

Figure 26.

See

Figure 28.

V/µs

V/µs

9/34

Electrical specifications VN5E050J-E

Table 7. Status pin (VSD=0V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

STAT

I

LSTAT

C

STAT

V

Table 8. Protections

Status low output
voltage

Status leakage current

Status pin input
capacitance

Status clamp voltage

SCL

= 1.6 mA, VSD=0V 0.5 V

I

STAT

Normal operation or V

= 5V

V

STAT

Normal operation or VSD=5V,
V

= 5V

STAT

I

= 1mA

STAT

I

= - 1mA

STAT

(1)

SD

=5V,

5.5

10 µA

100 pF

7V

-0.7

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

limH

I

limL

T

TSD

T

T

T

HYST

t

SDL

V

DEMAG

DC short circuit
current

Short circuit current
during thermal cycling

=13V; 5V<VCC<28V

V

CC

=13V; TR<Tj<T

V

CC

TSD

Shutdown temperature 150 175 200 °C

Reset temperature

R

Thermal reset of

RS

STATUS

Thermal hysteresis
(T

Status delay in
overload conditions

Turn-off output voltage
clamp

TSD-TR

)

T

I

OUT

( see Figure 4.)20µs

j>TTSD

=2A; VIN=0; L=6mH

19 27 38

38

7A

TRS + 1

TRS + 5

135 °C

7°C

VCC-41

VCC-46

VCC-52

V

A
A

°C

V

=0.1A;

I

V

Output voltage drop

ON

limitation

OUT

Tj= -40°C...+150°C
(see Figure 5.)

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

10/34

25 mV

VN5E050J-E Electrical specifications

Table 9. Open load detection (8V<VCC<18V)

Symbol Parameter Test conditions Min Typ Max Unit

I

OL

t

DOL(on)

t

POL

V

OL

t

DSTKON

I

L(off2)

td_vol

Openload ON state
detection threshold

Openload ON state
detection delay

Delay between INPUT
falling edge and
STATUS rising edge in
openload condition

Openload OFF state
voltage detection
threshold

Output short circuit to
VCC detection delay at
turn Off

Off state output
current

Delay response from
output rising edge to
STATUS falling edge in
open load

VIN = 5V 10 70 mA

I

= 0A, VCC=13V

OUT

(see Figure 4.)

= 0A (see Figure 4.) 200 500 1200 µs

I

OUT

VIN = 0V 2 4 V

See Figure 4. 180 t

V

= 0V; V

IN

(see Section 3.4: Open load

OUT

= 4V

-75 0 µA

detection in Off state)

V

IN

= 0V; V

= 4V 20 µs

OUT

200 µs

POL

µs

Table 10. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

V

V

I(hyst)

V

V

I

SDL

V

I

SDH

V

SD(hyst)

V

SDCL

Input low level 0.9 V

IL

I

Low level input current VIN =0.9 V 1 µA

IL

Input high level 2.1 V

IH

High level input current VIN = 2.1 V 10 µA

I

IH

Input hysteresis voltage 0.25 V

I

= 1mA

Input clamp voltage

ICL

STAT_DIS low level voltage 0.9 V

SDL

Low level STAT_DIS current V

STAT_DIS high level voltage 2.1 V

SDH

High level STAT_DIS current V

IN

= -1mA

I

IN

= 0.9 V 1 µA

SD

= 2.1 V 10 µA

SD

5.5

-0.7

STAT_DIS hysteresis voltage 0.25 V

STAT_DIS clamp voltage

ISD= 1mA

ISD= -1mA

5.5

-0.7

7V

7V

V

V

11/34

Electrical specifications VN5E050J-E

Figure 4. Status timings

OPEN LOAD STATUS TIMING (without external pull-up)

I

< I

OUT

I

OUT

> I

OL

OL

V

OUT

t

POL

CC

V

t

DSTKON

OUT

< V

> V

OL

OL

V

V

V

V

IN

STAT

IN

STAT

t

DOL(on)

OUTPUT STUCK TO V

t

DOL(on)

OPEN LOAD STATUS TIMING (with external pull-up)

I

< I

OUT

OL

V

> V

OUT

V

V

IN

STAT

t

DOL(on)

OVER TEMP STATUS TIMING

Tj > T

V

V

IN

STAT

t

SDL

TSD

t

SDL

OL

Figure 5. Output voltage drop limitation

Vcc-V

out

Tj=150oC

V

on

Von/R

on(T)

T

=25oC

j

=-40oC

T

j

I

out

12/34

VN5E050J-E Electrical specifications

Figure 6. Switching characteristics

t

V

OUT

Won

80%

dV

/dt

OUT

(on)

t

r

INPUT

t

d(on)

10%

t

Woff

t

d(off)

90%

t

f

dV

OUT

/dt

(off)

Table 11. Truth table

Conditions INPUT OUTPUT STATUS (VSD=0V)

t

t

(1)

Normal Operation

Overtemperature

Undervoltage

L
H

L
H

L
H

H

Overload &

Short circuit to GND

Output voltage > V

Output current < I

1. If the VSD is high, the STATUS pin is in a high impedance.

2. The STATUS pin is low with a delay equal to t

3. The STATUS pin becomes high with a delay equal to t

OL

OL

H

L
H

L
H

DSTKON

(no power limitation)

after INPUT falling edge.

POL

L

H

L
L

L
L

X

Cycling

(power limitation)

H
H

L

H

after INPUT falling edge.

H
H

H

L

X
X

H

L

(2)

L

H

(3)

H

L

13/34

Electrical specifications VN5E050J-E

Table 12. Electrical transient requirements

ISO 7637-2:

2004(E)

Test pulse

Test levels

III IV

(1)

Number of

pulses or

test times

Burst cycle/pulse

repetition time

Delays and
impedance

1 -75 V -100 V

2a +37 V +50 V

5000

pulses

5000

pulses

0.5 s 5 s 2 ms, 10 Ω

0.2 s 5 s 50 µs, 2 Ω

3a -100 V -150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω

3b +75 V +100 V 1h 90 ms 100 ms 0.1 µs, 50 Ω

4 -6 V -7 V 1 pulse 100 ms, 0.01

(2)

5b

ISO 7637-2:

+65 V +87 V 1 pulse 400 ms, 2 Ω

Test level results

(1)

2004(E)

Tes t puls e

III IV

1C C

2a C C

3a C C

3b C C

4C C

5b

(2)

CC

Ω

1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

E

One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.

14/34

VN5E050J-E Electrical specifications

2.4 Waveforms

Figure 7. Normal operation

Normal operation

INPUT

Nominal load Nominal load

I

OUT

V

STATUS

V

ST_DIS

Figure 8. Undervoltage shutdown

Undervoltage shut-down

V

V

INPUT

I

V

STATUS

V

ST_DIS

CC

OUT

USD

V

USDhyst

UNDEFINED

15/34

Electrical specifications VN5E050J-E

Figure 9. Overload or Short to GND

Overload or Short to GND

INPUT

I

>

LimH

I

OUT

V

STATUS

V

ST_DIS

Power Limitation

Figure 10. Intermittent Overload

INPUT

I

>

LimH

I

OUT

Thermal cycling

I

>

LimL

Intermittent Overload

Overload

I

>

LimL

Nominal load

V

STATUS

V

ST_DIS

16/34

VN5E050J-E Electrical specifications

Figure 11. Open Load with external pull-up

Open Load

with external pull-up

INPUT

VPU> V

OL

V

t

DOL(on)

OL

V

OUT

I

OUT

V

STATUS

V

ST_DIS

Figure 12. Open Load without external pull-up

Open Load

without external pull-up

INPUT

V

I

V

STATUS

V

ST_DIS

OUT

OUT

I

OUT

t

DOL(on)

< I

OL

I

OL

t

POL

17/34

Electrical specifications VN5E050J-E

Figure 13. Short to V

INPUT

V

OUT

I

OUT

V

STATUS

V

ST_DIS

CC

Resistive

Short to V

V

> V

OUT

V

OL

I

> I

OUT

I

OL

t

DSTK(on)

Short to V

CC

Hard

CC

OL

OL

Short to V

V

> V

OUT

I

< I

OUT

t

DOL(on)

CC

OL

OL

Figure 14. TJ evolution in Overload or Short to GND

TJ evolution in

Overload or Short to GND

INPUT

I

OUT

T

J

Self-limitation of fast thermal transients

T

J_START

Power Limitation

I

>

LimH

T

T

TSD

R

< I

T

HYST

LimL

18/34

VN5E050J-E Electrical specifications

2.5 Electrical characteristics curves

Figure 15. Off state output current Figure 16. High level input current

Iloff (nA)

1500

1250

1000

750

500

Off State
Vcc=13V

Vin=Vout=0V

Iih (µA)

4,5

Vin=2.1V

4

3,5

3

250

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

2,5

2

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 17. Input clamp voltage Figure 18. Input high level

Vicl (V)

7

6,8

6,6

6,4

6,2

lin=1mA

6

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vih (V)

3

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 19. Input low level Figure 20. Low level STAT_DIS current

Vil (V)

2

1,8

1,6

1,4

1,2

1

0,8

0,6

0,4

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Isdl (µA)

5

4,5

3,5

2,5

1,5

Vsd= 0.9V

4

3

2

1

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

19/34

Electrical specifications VN5E050J-E

Figure 21. On state resistance vs T

Ron (mOhm)

120

100

80

60

40

20

0

Iout= 2A
Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 23. On state resistance vs V

Ron (mOhm)

100

80

60

40

20

0 5 10 15 20 25 30 35

Vcc (V)

case

CC

Tc=150°C

Tc=125°C

Tc=25°C

Tc=-40°C

Figure 22. High level STAT_DIS current

Isdh (µA)

5

4,5

3,5

2,5

Vsd= 2.1V

4

3

2

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 24. Low level input current

Iil (µA)

5

4,5

3,5

2,5

1,5

Vin=0.9V

4

3

2

1

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 25. I

Ilimh (A)

40

35

30

25

20

15

10

-50 -25 0 25 50 75 100 125 150

LIM

vs T

Vcc=13V

case

Tc (°C)

20/34

Figure 26. Turn-On voltage slope

(dVout/dt )On (V/ms)

800

Tc (°C)

Vcc=13V

RI=6.5 Ohm

700

600

500

400

300

200

-50 -25 0 25 50 75 100 125 150 175

VN5E050J-E Electrical specifications

Figure 27. Undervoltage shutdown Figure 28. Turn-Off voltage slope

Vusd (V)

7

(dVout/dt )Off (V/ms)

500

6

5

4

3

2

1

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

400

300

200

100

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vcc=13V

RI= 6.5 Ohm

Figure 29. STAT_DIS clamp voltage Figure 30. High level STAT_DIS voltage

Vsdcl(V)

10

9

8

7

6

5

4

Isd = 1 mA

VsdH(V)

3

2,5

2

1,5

1

0,5

3

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Figure 31. Low level STAT_DIS voltage

VsdL(V)

2,5

2

1,5

1

0,5

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

21/34

Application information VN5E050J-E

3 Application information

Figure 32. Application schematic

+5V

R

R

MCU

R

prot

prot

prot

+5V

STAT_DIS

INPUT

STATUS

V

GND

GND

R

GND

V

CC

OUTPUT

D

GND

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (R

GND

only)

D

ld

This solution can be used with any type of load.

The following is an indication on how to dimension the R

1. R

2. R

where -I

≤ 600mV / (I

GND

≥ (−VCC) / (-I

GND

is the DC reverse ground pin current and can be found in the absolute

GND

S(on)max

GND

).

)

maximum rating section of the device datasheet.

Power dissipation in R

P

= (-VCC)2/R

D

GND

(when VCC<0: during reverse battery situations) is:

GND

This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the
R

will produce a shift (I

GND

S(on)max

* R
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R

22/34

GND

resistor.

GND

S(on)max

) in the input thresholds and the status output

GND

becomes the sum of the

.

VN5E050J-E Application information

If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests Solution 2 is used (see below).

3.1.2 Solution 2: diode (D

A resistor (R

=1kΩ) should be inserted in parallel to D

GND

) in the ground line

GND

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (~600mV) in the input
threshold and in the status output values, if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to
V

max DC rating. The same applies if the device is subject to transients on the VCC line

CC

that are greater than the ones shown in the ISO T/R 7637/2 table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests that a resistor (R
to prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.

if the device drives an

GND

) be inserted in line

prot

-V

CCpeak/Ilatchup

≤ R

prot

Calculation example:

For V

5kΩ ≤ R

Recommended R

CCpeak

prot

≤ 180kΩ.

= - 100V and I

prot

≤ (V

OHµC-VIH-VGND

≥ 20mA; V

latchup

value is 10kΩ.

) / I

IHmax

OHµC

≥ 4.5V

23/34

Application information VN5E050J-E

3.4 Open load detection in Off state

Off-state open-load detection requires an external pull-up resistor (RPU) connected between
the OUTPUT pin and a positive supply voltage (V
microprocessor.

The external resistor has to be selected according to the following requirements:

1. No false open load indication when load is connected: in this case we have to avoid

V

to be higher than V

OUT

V

= (VPU/(RL+RPU))RL<V

OUT

; this results in the following condition

Olmin

Olmin.

2. No misdetection when load is disconnected: in this case the V

V

Because I
up resistor R

; this results in the following condition RPU<(V

OLmax

may significantly increase if V

s(OFF)

should be connected to a supply that is switched OFF when the module is in

PU

standby.

) like the +5V line used to supply the

PU

has to be higher than

OUT

PU–VOLmax

is pulled high (up to several mA), the pull-

out

)/I

L(off2)

.

The values of V

OLmin

, V

OLmax

and I

are available in the Electrical characteristics

L(off2)

section.

Figure 33. Open load detection in Off state

CC

V

IN P U T

STATUS

DRIVER

+

LOGIC

+

-

V

GROUND

V batt. VPU

L(off2)

I

OUT

R

OL

PU

R

L

R

24/34

VN5E050J-E Application information

3.5 Maximum demagnetization energy (VCC = 13.5V)

Figure 34. Maximum turn-Off current versus inductance

100

A

B

10

I (A)

1

0,1110100L (mH)

C

A: T

B: T

C: T

VIN, I

= 150°C single pulse

jstart

= 100°C repetitive pulse

jstart

= 125°C repetitive pulse

jstart

L

Demagnetization Demagnetization Demagnetization

Note: Values are generated with R

demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.

=0 Ω. In case of repetitive pulses, T

L

(at beginning of each

jstart

t

25/34

Package and PCB thermal data VN5E050J-E

4 Package and PCB thermal data

4.1 PowerSSO-12 thermal data

Figure 35. PowerSSO-12 PC board

Note: Layout condition of R

area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm

Figure 36. R

RTHj_amb(°C/W)

thj-amb

65

60

55

50

45

40

35

0246810

and Zth measurements (PCB: Double layer, Thermal Vias, FR4

th

2

).

Vs. PCB copper area in open box free air condition

PCB Cu heatsink area (cm^2)

26/34

VN5E050J-E Package and PCB thermal data

Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse

ZTH (°C/W)

100

10

1

0,1

0,001 0,01 0,1 1 10 100 1000

Time (s)

Equation 1: pulse calculation formula

Z

THδ

where δ = t

R

TH

P

/T

δ Z

THtp

1 δ–()+⋅=

Footprint

2 cm

8 cm

2

2

Figure 38. Thermal fitting model of a single channel HSD in PowerSSO-12

a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

(a)

27/34

Package and PCB thermal data VN5E050J-E

Table 13. Thermal parameter

Area/island (cm2)Footprint28

R1 (°C/W) 0.7

R2 (°C/W) 2.8

R3 (°C/W) 3

R4 (°C/W) 8 8 7

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1 (W.s/°C) 0.001

C2 (W.s/°C) 0.0025

C3 (W.s/°C) 0.0166

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

28/34

VN5E050J-E Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 Package mechanical data

Figure 39. PowerSSO-12 package dimensions

29/34

Package and packing information VN5E050J-E

Table 14. PowerSSO-12 mechanical data

Symbol

Min. Typ. Max.

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

Millimeters

k0° 8°

X 2.200 2.800

Y 2.900 3.500

ddd 0.100

30/34

VN5E050J-E Package and packing information

5.3 Packing information

Figure 40. PowerSSO-12 tube shipment (no suffix)

B

C

Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532

A

A1.85
B6.75
C (± 0.1) 0.6

All dimensions are in mm.

Figure 41. PowerSSO-12 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS

According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986

Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

Top

cover

tape

End

500mm min

Empty components pockets
saled with cover tape.

User direction of f eed

Start

No componentsNo components Components

500mm min

31/34

Order codes VN5E050J-E

6 Order codes

Table 15. Device summary

Package

Tube Tape and reel

PowerSSO-12 VN5E050J-E VN5E050JTR-E

Order codes

32/34

VN5E050J-E Revision history

7 Revision history

Table 16. Document revision history

Date Revision Changes

31-Aug-2007 1 Initial release.

Document restructured.
Changed Description on cover page.

<18V): added td_vol parameter.

CC

19-Feb-2008 2

Table 9: Open load detection (8V<V

Changed Section 2.4: Waveforms.
Added Section 2.5: Electrical characteristics curves.
Added Section 3.5: Maximum demagnetization energy (VCC = 13.5V).
Added Section 4.1: PowerSSO-12 thermal data.

33/34

VN5E050J-E

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34/34