The VN750, VN750S, VN750-B5 are a monolithic
device designed in STMicroelectronics VIPower
Technology, intended for driving any kind of load
with one side connected to ground.
Active V
pin voltage clamp protects the device
CC
against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
/ VN750S / VN750-B5
HIGH SIDE DRIVER
SO-8
ORDER CODES :
PENTAWATT
SO-8
P2PAK
combined with thermal shutdown and automatic
restart protect the device against overload.
The device detects open load condition both is on
and off state. Output shorted to VCCis detected in
the off state.Device automatically turns off in case
of ground pin disconnection.
PENTAWATT
P2PAK
VN750
VN750S
VN750-B5
BLOCK DIAGRAM
V
CC
V
CC
CLAMP
GND
INPUT
STATUS
(*) See application schematic at page 8
OVERTEMPERATURE
DETECTION
LOGIC
January 20001/15
OVERVOLTAGE
DETECTION
UNDERVOLTAGE
DETECTION
Power CLAMP
DRIVER
CURRENT LIMITER
ON STATE OPENLOAD
DETECTION
OFF STATE OPENLOAD
AND OUTPUT SHORTED TO V
DETECTION
OUTPUT
CC
1
Page 2
VN750 / VN750S / VN750-B5
ABSOLUTE MAXIMUM RATING
SymbolParameter
V
CC
-V
-I
gnd
I
OUT
-I
OUT
I
IN
I
STAT
V
ESD
P
T
T
T
stg
CONNECTION DIAGRAM (TOP VIEW)
DC Supply Voltage41V
Reverse DC Supply Voltage- 0.3V
CC
DC Reverse Ground Pin Current- 200mA
DC Output CurrentInternally LimitedA
Reverse DC Output Current- 6A
DC Input Current+/- 10mA
DC Status Current+/- 10mA
Electrostatic Discharge (R=1.5KΩ; C=100pF)2000V
Power Dissipation TC=25°C3.14242W
CAll functions of the device are performed as designed after exposure to disturbance.
EOne or more functions of the device is not performed as designed after exposure todisturbance
and cannot be returned to proper operation without replacing the device.
IIIIIIIV
IIIIIIIV
TEST LEVELS
Delays and
Impedance
TEST LEVELS RESULTS
6/15
1
Page 7
Figure1: Waveforms
INPUT
LOAD VOLTAGE
STATUS
V
CC
INPUT
LOAD VOLTAGE
STATUS
V
CC
INPUT
LOAD VOLTAGE
STATUS
NORMAL OPERATION
UNDERVOLTAGE
V
USD
OVERVOLTAGE
V
CC<VOV
V
USDhyst
undefined
VCC>V
VN750 / VN750S / VN750-B5
OV
INPUT
LOAD VOLTAGE
STATUS
INPUT
LOAD VOLTAGE
STATUS
T
j
INPUT
LOAD CURRENT
STATUS
OPEN LOAD with external pull-up
V
OUT>VOL
V
OL
OPEN LOAD without external pull-up
T
T
TSD
R
OVERTEMPERATURE
7/15
1
1
Page 8
VN750 / VN750S / VN750-B5
APPLICATION SCHEMATIC
+5V
µC
R
R
prot
prot
+5V
STATUS
INPUT
GNDPROTECTIONNETWORKAGAINST
REVERSE BATTERY
Solution 1: Resistor in the ground line (R
can be used with any type of load.
The following is an indication on how to dimension the
resistor.
R
GND
1) R
2) R
where -I
be found in the absolute maximum r ating section of the
≤ 600mV / (I
GND
≥ (−VCC) / (-I
GND
is theDC reverse groundpin current and can
GND
S(on)max
)
GND
).
device’s datasheet.
Power Dissipation in R
battery situa tions) is:
= (-VCC)2/R
P
D
GND
(when VCC<0: during reverse
GND
This resistor can be share d amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where I
sum of the maximum on-state c urrents of the different
S(on)max
devices.
Please note that if the microprocessor ground i s no t
common with the device ground then the R
produce a shift (I
and the status output values. This shift w ill vary
S(on)max*RGND
) in the i nput thresholds
depending on manydevices are ON in the caseof several
high side dr ivers sharing the same R
GND
If thecalculated power dissipation leads to a large resistor
or several device s h ave to share the same resistor then
the ST sugg ests to utilize Solution 2 (see below).
Solution 2: A diode (D
A resistor ( R
if the device will be d riving an inductive load.
D
GND
=1kΩ) should be inserted in parallel to
GND
) in the ground line.
GND
only). This
GND
becomes the
.
GND
will
V
CC
D
ld
OUTPUT
GND
R
V
GND
GND
D
GND
This small signal diode c an be safely shared amongst
several different HSD. Also in this case, the pre sence of
the grou nd network will produce a shift (j 600mV) in the
input threshold and the s tatus output values if the
microprocessor ground is not common with the device
ground. This shift wil l not var y if more than o ne HSD
shares the same diode/resistor ne twork.
LOAD DUMP PROT ECTION
Dldis necessary (Transil or MOV) if the load dump peak
voltage exceeds V
the device will be subject to transients on the V
are greater than the ones sho wn in the ISO T/R 7637/1
table.
max DC rating. The same applies if
CC
CC
µC I/Os PROTECTION:
If a ground protection network is used and ne gative
transients are present on the V
be pulled negative. ST suggests to insert a resistor (R
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is acompromise between the
leakage current of µ C and th e curr ent required by the
HSD I/Os (Input levels compatibility) with the latch-up limit
of µ C I/Os.
Information furnished is believed to be accurate and reliable. However,STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rightsof STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical componentsin life support devices or systems without express written approval of STMicroelectronics.
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta -