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DIFFERENTIAL DATA AND
CLOCK D FLIP-FLOP
SY10EL52
SY100EL52
FEATURES
■ 365ps propagation delay
■ 2.0GHz toggle frequency
■ Internal 75KΩ input pull-down resistors
■ Available in 8-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
1
DVCC
2
D
3
45
CLK
D
Flip-Flop
SOIC
TOP VIEW
8
7
Q
6
QCLK
V
EE
DESCRIPTION
The SY10/100EL52 are differential data, differential
clock D flip-flops. These devices are functionally
equivalent to the E452 devices, with higher performance
capabilities. With propagation delays and output transition
times significantly faster than the E452, the EL52 is ideally
suited for those applications which require the ultimate
in AC performance.
Data enters the master portion of the flip-flop when
the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock.
The differential clock inputs also allow the EL52 to be
used as a negative edge triggered device.
The EL52 employs input clamping circuitry so that,
under open input conditions (pulled down to VEE), the
outputs of the device will remain stable.
PIN NAMES
Pin Function
D Data Input
CLK Clock Input
Q Data Output
TRUTH TABLE
D CLK Q
LZL
HZH
NOTE:
1. Z = LOW-to-HIGH transition.
(1)
Rev.: F Amendment: /0
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Issue Date: August, 1998
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SY10EL52
Micrel
SY100EL52
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
EE Power Supply 10EL — 21 25 17 21 25 17 21 25 17 21 25 mA
I
Current 100EL — 21 25 17 21 25 17 21 25 19 24 29
EE Power Supply 10EL –4.75 –5.2 –5.5 –4.75 –5.2 –5.5 –4.75 –5.2 –5.5 –4.75 –5.2 –5.5 V
V
Voltage 100EL –4.20 –4.5 –5.5 –4.20 –4.5 –5.5 –4.20 –4.5 –5.5 –4.20 –4.5 –5.5
I
IH Input HIGH Current — — 150 — — 150 — — 150 — — 150 µA
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
MAX Maximum Toggle 1.8 2.5 — 2.2 2.8 — 2.2 2.8 — 2.2 2.8 — GHz
f
Frequency
PLH Propagation Delay to ps
t
tPHL Output CLK 235 335 515 275 365 465 275 365 465 320 410 510
tS Set-up Time 125 0 — 125 0 — 125 0 — 125 0 — ps
tH Hold Time 150 50 — 150 50 — 150 50 — 150 50 — ps
tPW Minimum Pulse Width 400 — — 400 — — 400 — — 400 — — ps
VPP Minimum Input Swing
CMR Common Mode Range
V
D (10EL) –0.4 — –1.6 –0.4 — –1.6 –0.4 — –1.6 –0.4 — –1.6
D (100EL) –0.4 — –1.2 –0.4 — –1.2 –0.4 — –1.2 –0.4 — –1.2
CLK (10EL) –0.6 —
CLK (100EL) –0.8 —
tr Output Rise/Fall Times Q 100 225 350 100 225 350 100 225 350 100 225 350 ps
tf (20% to 80%)
(1)
150 — — 150 — — 150 — — 150 — — mV
(2)
(3)
(3)
–0.6 —
–0.8 —
(3)
(3)
–0.6 —
–0.8 —
(3)
(3)
–0.6 —
–0.8 —
(3)
(3)
V
NOTES:
1. Minimum input swing for which AC parameters are guaranteed.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between VPP min. and 1V.
3. The lower end of the CMR range is dependent on VEE and is equal to VEE + 3.0V.
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10EL52ZC Z8-1 Commercial
SY10EL52ZCTR Z8-1 Commercial
SY100EL52ZC Z8-1 Commercial
SY100EL52ZCTR Z8-1 Commercial
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Micrel
8 LEAD SOIC .150" WIDE (Z8-1)
SY10EL52
SY100EL52
Rev. 03
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Micrel
SY10EL52
SY100EL52
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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