Datasheet MT89760B, MT89760BN, MT89760BS Datasheet (MITEL)

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Features

• Complete in terfac e to a bi direct iona l T1 link

• D3/D4 or ESF frami ng and S LC-96 comp atib le

• Two frame elastic buffer with 32µs j itter buffer

• Insertion and dete ction of A, B, C, D bits Signalling freeze , opt iona l debo unc e

• Selectable B8ZS, jammed bit (ZCS) or no zero code suppression

• Yellow and blue al arm signa l ca pabil ities

• Bipolar violation count, F

error count, CRC

error count

• Frame and superframe sync. signals, Tx and Rx

• Per channel , overa ll, and re mote l oop aro und

• 8 kHz synchronization output

• Digital phas e det ector betwe en T1 li ne and S TBUS

• ST-BUS compatible

• Pin compatible with the MH89760

• Inductorless clock recovery

• Loss of Sign al (LO S) indi cation

• Available in standard, narrow and surface mount form ats

Applications

• DS1/ESF digital trunk interfaces

• Computer to PBX interfaces (DMI and CPI)

• High speed comp uter t o com pute r data links

Descript io n

The MH89760B is a complete T1 interface solution, meeting the Extended Super Frame (ESF), D3/D4 and SLC-96 formats. The MH89760B interfaces to the DS11.544 Mbit/s ec digital trun k .

The MH89760B is a pin-compatible enhancement of the MH89760, permitting the removal of the tuneable inductor and inclusion of the external NAND gate used for generating RxD.

Figure 1 - Functional Block Diagram

TxSF

C2i

F0i

RxSF

DSTo

DSTi

CSTi0 CSTi1

CSTo

VDD

XCtl

XSt

C1.5i RxFDLClk

RxFDL TxFDLClk

TxFDL OUTA OUTB RxA RxT LOS RxR RxB

E1.5o

E8Ko

VSS

ST-BUS

Timing

Circuitry

Data

Interface

Serial

Control

Interface

Control

Logic

1544-2048

Two Frame

Elastic

Buffer

2048 - 1544

Converte r

ABCD

Signalling RAM

DS1

LINK

INTERFACE

Phase

Detector

DS1

Counter

Clock

Extractor

Receiver

Transmit ter

ISSUE 5 May 1995

Ordering Information

MH89760B 40 Pin DIL Hybrid 1.3" row pitch MH89760BN 40 Pin DIL Hybrid 0.8" row pitch MH89760BS 40 Pin Surface Mount Hybrid

0°C to 70°C

MH89760B

T1/ESF Framer & Interface

ST-BUS FAMILY

Preliminary Information

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MH89760B Preliminary Information

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

2NCNo Connection. 3E1.5o1.544 MHz Extracted Clock (Outpu t): This clock is ext racted by t he device from the

received DS1 signal. It is used internally to clock in data received at RxT and RxR.

System Power S up ply. +5V.

5RxA

Received A (Output): The bipolar DS1 signal received by the device at RxR and RxT is converted to a unipolar format and output at this pin.

6 7

RxT

RxR

Receive Tip and Ring Inputs: Bipolar split phase inputs designed to be connected directly to the input transformer. I mpe dance to ground is approximately 1kΩ. Impedance between pins=430Ω.

8RxB

Received B (Output): The bipolar DS1 signal received by the device at RxR and RxT is converted to a unipolar format and output at this pin.

9NCNo Connection.

10 CSTi1 Control ST-BUS Input #1: A 2048 kbit/s serial control stream which carries 24 per-

channel control words.

11 CSTi0 Control ST-BUS Input #0: A 2048 kbit/s serial contro l stream that contain s 24 per

channel control words and two master control words.

12 E8Ko 8 kHz Extracted Clock (Outp ut): This is an 8 kH z out put generated by dividing the

extracted 1.544 MHz clock by 193 and aligning it with the received DS1 frame. The 8 kHz signal can be used for synchronizing system clocks to the extracted 1.544 MHz clock. When digital loopback is enabled, the 8kHz is derived from C1.5.

13 XCtl External Control (Outpu t): This is an uncommitted externa l outpu t pin which is set or

reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated once per frame.

14 XSt External Status (Schmitt Trigger Input): The state of this pin is sampled once per

frame and the status is reported in bit 5 of Master Status Word 2 on CSTo.

15 CSTo Control ST-BUS Output: This is a 2048 kbit/s serial control stream which provides the

24 per-channel status words, and two master status words.

16 NC No Connection.

NC LOS NC TxFDL NC TxFDLClk VSS RxFDLClk DSTo RxFDL OUTB C1.5i RxSF TxSF OUTA NC NC NC VSS

E1.5o

VDD

RxA RxT RxR RxB

NC CSTi1 CSTi0

E8Ko

XCtl

XSt

CSTo

DSTi

C2i

E1.5o

F0i

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39

38 37 36

35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

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Preliminary Information MH89760B

Pin # Name Description

17 DSTi Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the 24

PCM or data channels to be transmitted on the T1 trunk.

18 C2i 2.048 MHz S ystem Clock (Inp ut ): This is the master cl oc k for the ST-BUS section of

the chip. All data on the ST-BUS is clocked in on the falling edge of C2i and out on the

rising edge. 19 E1.5o 1.544 MHz Extracted Clock (Outpu t): Internally connected t o Pin 3. 20 F0i

Frame Pulse Input: This is the frame synchronizati on si gnal which def ines the

beginning of the 32 channel ST-BUS frame. 21 V

System ground .

22-24 NC No Connec tion .

25 OUTA Output A (Open Collector Output): This is the output of the DS1 transmitter circuit. It is

suitable for use with an external pulse transformer to generate the transmit bipolar line

signal. 26 TxSF

Transmit Superframe Pulse Input: A low pulse applied at this pin will det erm ine the

start of the next transmit superframe as illustrated in Figure 20. The device will free run if

this pin is held high. 27 RxSF

Received Superframe Pulse Output: A pulse output on this pin indicates tha t the next

frame of data on the ST-BUS is from frame 1 of the received superframe. The period is

12 frames long in D3/D4 modes and 24 frames in ESF mode. Active only when device is

synchronized to received DS1 signal. 28 C1.5i 1.544 MHz Clock Input: The rising edge of this clock is used to output data on OUTA,

OUTB. C1.5i must be pha se -lo c ked to the C2i system cl o c k. 29 OUTB Output B (Open Collector Output): This is the output of the DS1 transmitter circuit. It is

suitable for use with an external pulse transformer to generate the transmit bipolar line

signal. 30 RxFDL Received Facility Data Link (Output): A 4 kbit/s serial output stream that is

demultiplexe d from the FDL bits in ESF mode, or the received F

bit pattern when in

SLC96 mode. It is clocked out on the rising edge of RxFDLClk. 31 DSTo Data ST-BUS Output: A 2048 kbit/s serial output stream which contains the 24 PCM or

data channels received from the DS1 line. 32 RxFDLClk Receive Facility Data Link Cl ock Ou tput: A 4 kHz clock used to output FDL

information on RxFDL. Dat a is clocked out on the rising edge of the clock. 33 V

No Connection.

34 TxFDLCl k Transmit Facility Data Link Clock Outp ut: A 4 kHz clock used to input FDL

information on TxFDL. Data is cloc ked in on the rising edge of the clock. 35 NC No Connection. 36 TxFDL Transmit Facility Data Link (Input)

: A 4 kbit/s serial input stream that is muxed into the

FDL bits in the ESF mode, or the F

pattern when in SLC96 mode. It is clocked in on the

rising edge of TxFDLClk. 37 NC No Connection. 38 LO S Loss of Signal (Output): This pin goes high when 128 contiguous ZEROs are received

on the RxT and RxR inputs. When LOS is high, RxA

and RxB are forced high. LOS is

reset when 48 ones are received in a two T1-frame period. 39 NC No Connection.

40 NC No Connection .

Pin Description (Contin ue d)

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MH89760B Preliminary Information

ST-BUS CHANNEL VERSUS DS1 CHANNEL TRANSMITTED

ST-BUS CHANNEL VERSUS DS1 CHA NNEL RECEIVED

PCCW=P er C hannel Con trol Word, M C W1 /2= M as te r C o ntrol Word 1/ 2

ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED

PCCW=Per Channel Control Word

ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED

PCSW=Per Channel Status Word, PSW=Phase Status Word, MSW=Master Status Word

ST-BUS VERSUS DS 1 CHANNEL STATUS

X = UNUSED

Figure 3 - ST-BUS Channel Allocations

DSTi 0

1234

5678

9 101112

13 14 15 16

17 18 19 20

21 22 23 24

25 26 27 28

29 30 31

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

DSTo 0

1234

5678

9101112

13 14 15 16

17 18 19 20

21 22 23 24

25 26 27 28

29 30 31

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CSTi0 0

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CSTi1

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CSTo 0

PCS

3PSW

PCS

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

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Preliminary Information MH89760B

Functional Description

The MH89760B is a thick film hybrid solution for a T1 interface. All of the formatting and signalling insertion and detection is done by the device. Various programmable options in the device include: ESF, D3/D4 or SLC-96 mode, common channel or robbed bit signalling, zero code suppression, alarms, and local and remote loopback. The MH89760B also has built in bipolar line drivers and receivers and a clock extraction circuit.

All data and control information is communicated to the MH89760B via 2048 kbit/s serial streams conforming to Mitel’s ST-BUS format.

The ST-BUS is a TDM serial bus that operates at 2048 kbits/s. The serial streams are divided into 125 µsec frames that are made up of 32 8-bit channels. A serial stream that is made up of these 32 8 bit channels is known as an ST-BUS stream, and one of these 64 kbit/s channels is known as an ST-BUS channel.

The system side of the MH89760B is made up of STBUS inputs and outputs, i.e., control inputs and outputs (CSTi/o) and data inputs and outputs (DSTi/ o). These signals are functionally represented in Figure 32. The DS1 line side of the device is made up of split phase inputs (RxT, RxR) and outputs (OUTA, OUTB) which can be connected to line coupling transformers. Functional transmit and receive timing is shown in Figures 33 and 34.

Data for transmission on the DS1 line is clocked serially into the device at the DSTi pin. The DSTi pin accepts a 32 channel time division multiplexed STBUS stream . Data i s clocked in wit h the falli ng edge of the C2i clock. ST-BUS frame boundaries are defined by the frame pulse applied at the F0i pin. Only 24 of the available 32 c hannels on the ST-BUS serial stream are actually transmitted on the DS1 side. The unused 8 channels are ignored by the device.

Data recei ved fr om the DS1 l ine i s cl o c ke d o ut of th e device in a similar manner at the DSTo pin. Data is clocked out on the rising edge of the C2i clock. Only 24 of the 32 channels output by the device contain the information from the DS1 line. The DSTo pin is, however, actively driven during the unused channel timeslots. Figure 3 shows the correspondence between the DS1 channels and the ST-BUS channels.

All control and monitoring of the device is accomplished through two ST-BUS serial control

inputs and one ser ial control outpu t. Control ST-BUS input number 0 (CSTi0) accepts an ST-BUS serial stream which contains the 24 per channel control words and two master control words. The per chan nel control words relate directly to the 24 information channels output on the DS 1 side. The master control words affect operation of the whole device. Control ST-BUS input number 1 (CSTi1) accepts an ST-BUS stream containing the A, B, C and D signalling bits. The relationship between the CSTi channels and the controlled DS0 channels is shown in Figure 3. Status and signalling inform ation is received from the device via the control ST-BUS output (CSTo). This serial outpu t stream contain s two m aster st atus wo rds, 24 per channel status words and one Phase Status Word. Figure 3 shows the correspondence between the received DS1 channels and the status words. Detailed information on the operation of the control interface is presented be low.

Program mabl e Feat ures

The main features in the device are programmed through two master control words which occupy channels 15 and 31 in Control ST-BUS input stream number 0 (CSTi0). These two eight bit words are used to:

• Select the di fferent op erati ng mo de s of the device ESF, D3/D4 or SLC-96.

• Activate th e fea tures th at are n ee ded in a certain application; common channel signalling, zero code supp ressi on, signal ling d eboun ce, etc.

• Turn on in service alarm s, d iagno stic lo op arounds, and the ext erna l cont rol funct ion.

Tables 1 and 2 contain a complete explanation of the function of the different bits in Master Control Words 1 and 2.

Major Operating Modes

The major operating modes of the device are enabled by bits 2 and 4 of Master Control Word 2. The Extended Superframe (ESF) mode is enabled when bit 4 is set high. Bit 2 has no effect in this mode. The ESF mode enables the t ransmission of the S bit pattern shown in Table 3. This includes the frame/superframe pattern, the CRC-6, and the Facility Data Link (FDL). The device generates the frame/multiframe pattern and calculates the CRC for each superframe. The data clocked into the device on the TxFDL pin is incorporated into the FDL. ESF mode will also insert A, B, C and D si gnalling bits into the 24 f rame multiframe. The DS1 frame begins after approximately 25 periods of the C1.5i clock from the F0i

frame pulse.

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MH89760B Preliminary Information

Table 1. Master Control Word 1 (Channel 15, CSTi0)

Table 2. Master Control Word 2 (Channel 31, CSTi0)

Bit Name Description

7 Debounce When set the received A, B, C and D signalling bits are reported directly in the per

channel status words output at CSTo. When clear, the signalling bits are debounced for 6 to 9 ms before they are placed on CSTo.

6 TSPZCS Transparent Zero Code Suppression. When this bit is set, no zero code suppression is

implemented.

5 B8Z S Bin ary Eig ht Zero Supp ressi on . When this bit is set, B8ZS zero code suppression is

enabled. When clear, bit 7 in data channels containing all zeros is forced high before being transmitted on the DS1 side. This bit is inactive if the TSPZCS bit is set.

4 8kHSel 8 kHz Output Select. Whe n set, the E8K o pin is held high. Whe n clear, the E8Ko

generates an 8 kHz output derived from the extracted 1.544 MHz clock or C1.5i clock (see Pin Description for E8Ko).

3 XC tl External Control Pin. When set, the XCtl pin is held high. Whe n clea r, XCtl is held low. 2 ESFYLW ESF Yellow Alarm. Valid only in ESF mode. When set, a sequence of eight 1’s followed

by eight 0’s is sent in the FDL bit positions. When clear , the FDL bit contains data input at the TxFDL pin.

1 Robbed bit When this bit is set, robbed bit signalling is disabled on all DS0 transmit channels. When

clear, A, B, C and D signalling bits are inserted into bit position 8 of all DS0 channels in every 6th frame.

0 YLALR Yellow Alarm. When set, bit 2 of all DS0 channels is set low. When clear, bit 2 operates

normally.

Bit Name Description

7 RMLOOP Remote Loopback. When set, the data received at RxR and RxT is looped back to OUTB

and OUTA respective ly. The data is clocked into t he device wit h the extracted 1.54 4 MHz clock. The device still monitors the received dat a and outpu ts it at DSTo. The device operates normally when the bit is clear.

6 DGLOOP Digital Loopback. When set, the data input on DSTi is looped around to DSTo. The

normal received data on RxR and RxT is ignored. However, t he dat a input at DSTi is still transmitted on OUTA and OUTB. The device frames up on the looped data using the C1.5i clock.

5 ALL1'S All One’s Alarm. When set, the chip transmits an unfram ed all 1's signal on OUTA and

OUTB.

4 ESF/D4 ESF/D4 Select. W hen set, the device is in ESF mode. When clear, the device is in D3/D4

mode.

3 ReFR Reframe. If set for at least one frame and then cleared, the chip will begi n to search for a

new frame position. Only the change from high to low will cause a reframe, not a continuous low level.

2 SLC-96 SLC-96 Mode Select. The chip is in SLC-96 mode when this bit is set. This enables input

and output of the F

bit pattern using the same pins as the facility data link in ESF mode. The chip will use the same framing algorithm as D3/D4 mo de. Th e user must insert the valid F

bits in 2 out of 6 superframes to allow the receiver to find superframe sync, and the transmitter to insert A and B bits in every 6th frame. The SLC-96 FDL completely replaces the F

pattern in the outgoing S bit po sition. I nacti ve in ESF mod e.

1 CRC/MIMIC In ESF mode, when set, the chip disregards the CRC calculation durin g synchroniza tion .

When clear, the device will check for a correct CRC before going into synchronization. In D3/D4 mode, when set, the device will synchronize on the first correct S-bit pattern detected. When this bit is clear, the device will not synchronize if it has detected more than one candidate for the fram e ali gnm ent pat te rn (i.e. , a mimic ).

0 Maint. Maintena nce M ode. When set, the device will declare itself out-of-sync if 4 out of 12

consecutive F

bits are in error. When clear, th e out-of -s ync thresh old is 2 errors in 4 FT

bits. In this mode, four consecutive bit s follo wing an errored F

bit are examined.

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Preliminary Information MH89760B

Table 3. ESF Fra me Pat ter n

† These signalling bits are only valid if the robbed bit signalli ng is active.

During synchronization the receiver locks on to the incoming frame, calculates the CRC and compares it to the CRC received in the next multiframe. The device will not declare itself to be in synchronization unless a valid framing pattern in the S-bit is detected and a correct CRC is received. The CRC check in this case provides protect ion against false framing. The CRC check can be turned off by setting bit 1 in Master Control Word 2.

The device can be forced to resynchronize itself. If Bit 3 in Master Cont rol Word 2 is set for one frame and then subsequently reset, the de vice will start to search for a new frame position. The decision to reframe is made by the user’s system processor on the basis of the status conditions detected in the received master status words. This may include consideration of the number of errors in the received CRC in conjunction with an indication of the presence of a mimic. When the device attains synchronization the mimic bit in Master Status Word 1 is set if the device found another possible candidate when it was searching for the framing pattern.

Note that the devi ce will r esync hroniz e auto matic ally if the errors in the terminal framing pattern (F

or FPS) exceed the threshold set with bit 0 in Master Control Word 2.

Frame # F PS F DL CRC Signalling

†

1X 2CB1 3X 40 5X 6 CB2 A 7X 80

9X 10 CB3 11 X 12 1 B 13 X 14 CB4 15 X 16 0 17 X 18 CB5 C 19 X 20 1 21 X 22 CB6 23 X 24 1 D

Table 4. D3/D4 Framer

† These signalling bits are only valid if the robbed bit signalling is active.

Standard D3/D4 framing is enabled when bit 4 of Master Control Word 2 is reset (logic 0). In this mode the device searches for and inserts the framing pattern shown in Table 4. This mode only supports AB bit signalling, and does not contain a CRC check.

The CRC/MIMIC bit in Master Control Word 2, when set high, allows the device to synchronize in the presence of a mimic. If this bit is reset, the device will not synchronize in the presence of a mimic. (Also refer t o section on Framing Algorit hm.)

In the D3/D4 mode the device can also be made compatible with SLC-96 by setting bit two of Master Control Word 2. This allows the user to insert and extract the signalling framing pattern on the DS1 bit stream using the FDL input and output pins. The user must format this 4 kbits of information exter nally to meet all of the requirements of the SLC-96 specification (see Table 5). The device multiplexes and demultiplexes this information into the proper position. This mode of operation can also be used for any other application that uses all or part of the signalling framing pattern. As long as the serial stream clocked into the TxFDL contains two proper sets of consecutive synchronization bits (as shown in Table 5 for fr am es 1 to 2 4) , the devic e will be able to insert and extract the A, B signalling bits. The TxSF

pin should be held high in this mode. Superframe boundaries cannot be defined by a pulse on this inpu t. The RxSF

output functions normally and indicates the superframe boundaries based on the synchronization pattern in the F

received bit

position.

Zero Code Suppression

The combination of bits 5 and 6 in Master Control Word 1 allow one of three zero code suppression schemes to be selected. The three choices are: none, binary 8 zero suppression (B8ZS), or jammed bit (bit 7 forced high). No zero code suppression

Frame # F

Signalling

†

11 20 30 40 51 61A 70 81 91

10 1

11 0

12 0 B

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MH89760B Preliminary Information

Table 5. SLC-9 6 Fram ing P attern

† Note: The FS pattern has to be supplied by the user.

Figure 4 - B8ZS Output Coding

Frame

†

Notes

Frame

†

Notes

Resynchronization

Data

Bits

37 1

X = Concentrator

Field Bits

20 38X 30 390 40 40X 51 411 60 42X 70 430 81 44X

91 451 10 1 46 X 11 0 47 0

S = Spoiler Bits

12 1 48 S 13 1 49 1 14 0 50 S 15 0 51 0 16 0 52 S 17 1 53 1 18 0 54 C

C = Maintenance

Field

Bits

19 0 55 0 20 1 56 C 21 1 57 1 22 1 58 C 23 0 59 0

A = Alarm Field

Bits

24 1 60 A 25 1

X =Concentrator

Fiel d Bi ts

61 1 26 X 6 2 A 27 0 63 0

L = Line Sw i tc h

Field Bits

28 X 6 4 L 29 1 65 1 30 X 6 6 L 31 0 67 0 32 X 6 8 L 33 1 69 1 34 X 7 0 L 35 0 71 0

S = Spoiler Bits

36 X 72 S

DATA

B8ZS

B0 00V

000

V = Violation B = Bipolar 0 = No Pulse

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Preliminary Information MH89760B

allows the device to interface with systems that have already applied some form of zero code suppression to the data input on DSTi. B8ZS zero code suppression replaces all strings of 8 zeros with a known bit pattern and a specific pattern of bipolar violations. This bit pattern and violation pattern is shown in Figure 4. The receiver monitors the received bit pattern and the bipolar violation pattern and replaces all matching strings with 8 zeros .

Loopback Modes

Remote and digital loopback modes are enabled by bits 6 and 7 in Master Cont rol Word 2. These modes can be used for diagnostics in locating the source of a fault condition. Remote loop around loops back data received at RxR and RxT back out on OUTA and OUTB, thus effectively sending the received DS1 data back to the far end unaltered so that the transmission line can be tested. The received signal with the appropriate received channels on the DS1 side made available in the proper format at DSTo.

The digital loop around mode diverts the data received at DSTi back out the DSTo pin. Data received on DSTi is, however, still t ransmitted out via OUTA and OUTB. This loop back mode can be used to test the near end interface equipment when there is no transmission line or when there is a suspected failure of the line.

The all ones transmit alarm (also known as the blue alarm or the keep alive signal) can be activated in conjunction with the digital loop around so that the transmission line sends an all 1's signal while the normal data is looped back locally.

The MH89760B also has a per channel loopback mode. See Table 6 and the following section for more information.

Per Channel Control Features

In addition to the two master control words in CSTi0 there are also 24 Per Channel Control Words. These control words only affect individual DS0 channels. The correspondence between the channels on CSTi0 and the affected DS0 channel is s hown in Fig.

3. Each control word has three bits that enable robbed bit signalling, DS0 channel loopback and inversion of the DS0 channel. A full description of each of the bits is provided in Table 6.

Transmit Signalling Bits

Control ST-BUS input number 1 (CSTi1) contains 24 additional per channel control words. These 24 STBUS channels c ont ain the A, B, C and D signalling bits that the device uses at transmit time. The position of these 24 per channel control words in the ST-BUS is

shown in Figure 3 and the position of the

ABCD signalling bits is shown in Table 7. Even though the device only inserts the signalling information in every 6th DS1 frame this information must be input every ST-B US frame.

Robbed bit signalling can be disabled for all channels on the DS1 link by bit 1 of M aster Control Word 1. It can also be disabled on a per channel basis by bit 0 in the Per Channel Control Word 1.

Table 6. Per Channel Control Word 1 Input at CSTi0

Table 7. Per Channel Control Word 2 Input at CSTi1

Bit Name Description

7-3 IC Internal Connections. Must be kept at 0 for normal operation.

2 Polarity When set, the applicable channel is not inverted on the transmit or the receive side of the device.

When clear, all the bits within the applicable channel are inverted both on transmit and receive side.

1 Loop Per Channel Loopback. When set, the received DS0 channel is replaced with the transmitted

DS0 channel. Only one DS0 channel may be looped back in this manner at a time. The transmitted DS0 channel remains unaffect ed. When clear the transmit and receive DS0 sections operate normally.

0 Data Data Channel Enable. When set, robbed bit si gnalling for the applicable channel is disabled.

When clear, every 6th DS1 frame is available for robbed bi t signalling. This feature is enabled only if bit 1 in Master Control Word is low.

Bit Name Description

7-4 Unused Keep at 0 for normal operation

3 2

1-0

A B

C, D

These are the 4 signalling bits inserted in the appropriate channels of the DS1 stream bei ng output from the chip, when in ESF mode. In D3/D4 modes where there are only two signalling bits, the values of C and D are ignored.

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MH89760B Preliminary Information

Table 8. Master Statu s Word 1 (Chan nel 15 , CSTo)

Table 9. Master Statu s Word 2 (Chan nel 31 , CSTo)

Table 10. Phase Status Word (Channel 3, CSTo)

Bit Name Description

7 YLALR Yellow Alarm Indication. This bit is set when the chip is receiving a 0 in bit position 2 of every

DS0 channel.

6MIMICThis bit is set if the frame search algorithm found more than one possible frame candidate when

it went into frame synchronization.

5 ERR Terminal Framing Bit Error. The state of this bit changes every time the chip detects 4 errors in

the F

or FPS bit pattern. The bit will not change state more than once every 96ms.

4 ESFYLW ESF Yellow Alarm. This bit is set when the devi ce has observed a sequence of eight one’s and

eight 0’s in the FDL bit positions.

3 MFSYNC

Multiframe Synchronization. This bit is cleared when D3/D4 multiframe synchronization has

been achieved. Applicable only in D3/D4 and SLC-96 modes of operation.

2 BPV Bipolar Violation Count. The state of this bit changes every time the device counts 256 bipolar

violations.

1 SLIP Slip Indication. This bit changes state every time the elastic buffer in the device performs a

controlled slip.

0SYN

Synchronization. This bit is set when t he device has not achieved synchronization. The bit is

clear when the device has synchronized to the received DS1 data stream.

Bit Na me Description

7 BlAlm Blue Alarm. This bit is set if the receiver has detected two frames of 1’s and an out of frame

condition. It is reset by any 250 microsecond interval that contains a zero.

6 FrCnt Frame Count. This is the ninth and most significant bit of the “Phase Status Word" (see Table

10). If the phase status word is incrementing, this bit will toggle when the phase reading exceeds channel 31, bit 7. If the phase word is decrementing, then this bit will toggle when the reading goes below channel 0, bit 0.

5 XSt External Status. T his bit reflects the state of the external status pin (XSt). The state of the XSt

pin is sampled once per frame.

4-3 BP VCnt Bipolar Violation Count. These two bits change state every 128 and every 64 bipolar vio lations,

respectively .

2-0 CRCCNT CRC Error Count. These three bits count recei ved CRC errors. The counter will reset to zero

when it reaches terminal count. Valid only in ESF mode.

Bit Name Description

7-3 ChannelCnt Channel Count. These five bits indicate the ST-BUS channel count between the ST-BUS frame

pulse and the rising edge of E8Ko.

2-0 BitCnt Bit Count. These three bits provide one bit resolution within the channel count described above.

Operating Status Information

Status Information regarding the operation of the device is output serially via the Control ST-BUS output (CSTo). The CSTo serial stream contains Master Stat us Words 1 and 2, 24 Per Channe l Status Words, and a Phase Status Word. The Mas ter Status Words contain all of the information needed to determ i n e th e st ate o f t he int e rf ace a nd ho w w e ll i t i s operating. The information provided includes frame and super frame synchronization, slip, bipolar violation counter, alarms, CRC error count, F

error count, synchronization pattern mimic and a phase status word. Tables 8 and 9 give a description of each

of the bits in M ast er Statu s Word s 1 and 2, and Table 10 gives a descripti on of the Pha se Sta tus Word .

In addition, the MH89760B has a Loss of Signal (LOS) pin that is set High when 128 consecutive ZEROs are recei ved . Wh ile LOS is set High , RxA

and

RxB

are forced High. The LOS signa l goes Low w he n a ONEs density on 12.5% of the bits (equivalent to 48 bits) occurs in a two DS1 frame period.

Page 11

4-65

Preliminary Information MH89760B

Table 11. Per Channel Status Word Output on CSTo

Bit Name Description

7-4 Unused Unused Bits. Will be output as 0’s.

3 2 1 0

A B C D

These are the 4 signalling bits as extracted from the received DS1 bit stream. The bits are debounced for 6 to 9 ms if the debounce feature is enabled via bit 7 in Master Control Word 1.

Alarm Detect ion

The device detects the yellow alarm for both D3/D4 frame format and ESF format. The D3/D4 yellow alarm will be activated if a ‘0‘ is received in bit position 2 of every DS0 channel for 600 msec. It will be released in 200 msec after the content s of the bit change. The alarm is detectable in the presence of errors on the line. The ESF yellow alarm will become active when the device has detected a string of eight 0’s followed by eight 1’s in the facility data link. It is not detectable in the presence of errors on the line. This means that the ESF yellow alarm will drop out for relatively short periods of time, so the system will have to integrate the ESF yellow alarm. The blue alarm signal, in Master Status Word 2, will also drop out if there are errors on the line.

Mimic Detect ion

The mimic bit in Ma ster Status Word 1 w ill be set if, during synchronization, a frame alignment pattern (F

or FPS bit pattern) was observed in more than one position, i.e., if more than one candidate for the frame synchronization position was observed. It will be reset w he n t he de vice resynchronizes. T h e mi mi c bit, the terminal framing error bit and the CRC error counter can be used separately or together to decide if the rec eiv e r s ho u ld b e fo r ced to r e fra me.

Bipolar Violation Counter

The Bipolar Violation bit in Master Status Word 1 will toggle after 256 violations have been detected in the received signal. It has a maximum refresh t ime of 96 ms. This means that the bit can not change state faster than once every 96 ms. For example, if there are 256 violations in 80 ms the BPV bit will not change state until 96 ms. Any more errors in that extra 16 ms are not counted. If there are 256 errors in 200 ms then the BPV bit will change state after 200 ms. In practical terms this puts an upper limit on the error rate that can be calculated from the BPV information, but this rate (1.7 X 10

-3

) is well above

any normal operating condition.

Bits 4 and 3 also provide bipolar violations information. Bit 4 will change state after 128 violations.

Bit 3 changes state after 64 bipolar violations. These bits are refreshed independently and are not subject to the 96 ms refresh rate described above.

DS1/ST-BUS Phase Difference

An indication of the phase difference between the ST-BUS and the DS1 frame can be ascertained from the information provided by the eight bit Phase Status Word and the F rame Count bit. Channel t hree on CSTo contains the Phase Status Word. Bits 7-3 in this word indicate the number of ST-BUS channels between the ST-BUS frame pulse and the rising edge of the E8Ko signal. The remaining three bits provide one bit resolution within the channel count indicated by bits 7-3. The frame count bit in Master Status Word 2 is the ninth and most significant bit of the phase status word. It will toggle when the phase status word increments above channel 31, bit 7 or decrements below channel 0, bit 0. The E8Ko signal has a specific relationship with received DS1 frame. The rising edge of E8Ko occurs during bit 2, channel 17 of the received DS1 frame. The Phase Status Word in conjunction with the frame count bit, can be used to monitor the phase relationship bet ween the received DS1 frame and the local ST-BUS frame.

The local 2.048 MHz ST-BUS c lock must be phaselocked to the 1.544 MHz clock extracted from the received data. When the two clocks are not phaselocked, the input data rate on the DS1 side will differ from the output data rate on the ST-BUS side. If the average input data rate is higher than the average output dat a rate, the channel c ount and bit count in the phase s tatus word will be seen t o decrease over time, indicating that the E8Ko rising edge, and therefore the DS1 frame boundary is moving with respect to the ST-BUS frame pulse. Conversely, a lower average input data rate will result in an increase in the phas e reading.

In an application where it is necessary to minimize jitter transfer from the received clock to the local system clock, a phase lock loop with a relatively large time constant can be implemented using information provided by the phase status word. In such a system, the local 2.048 MHz clock is derived from a precision VCO. Frequency corrections are made on the basis of the average trend observed in

Page 12

4-66

MH89760B Preliminary Information

the phase status word. For example, if the channel count in the phase status word is seen to increase over time, the feedback applied to the VCO is used to decrease the system clock frequency until a reversal in the trend is observed.

The elastic buffer in the MH89760B permits the device to handle eight channels of jitter/wander (see description of elastic buffer in the next section). In order to prevent slips from occurring, the frequency corrections would have to be implemented such that the deviation in the phase status word is limited to eight channels peak to peak. It is possible to use a more sophisticated protocol which would center the elastic buffer and permit more jitter/wander to be handled. However, for most applications, the eight channels of jitter/wander tolerance is acceptable.

Received Signalling Bits

The A, B, C and D signalling bits are output from the device in the 24 Per Channel Status Words. Their location in the serial steam output at CSTo is shown in Figure 3 and the bit positions are shown in Table

11. The internal debouncing of the signalling bits can be turned on or off by Mast er Control Word 1. In ESF mode, A, B, C and D bits are valid. Even though the signalling bits are only received once every six frames the device stores the information so that it is available on the ST-BUS every frame. The ST-BUS will always contain the most recent signalling bits. The state of the signalling bits is frozen if synchronization is lost.

In D3/D4 mode, only the A and B bits are valid. The state of the signalling bits is frozen when terminal frame synchronization is lost. The freeze is disabled when the device regains terminal frame synchronization. The signalling bits may go through a random transition stage until the device attains multifram e synchro nization .

Clock and Framing Signals

The MH89760B has a built in clock extraction circuit which creates a 1.544 MHz clock synchronized to the received DS1 signal. This clock is used internally by the MH89760B to clock in data received on RxT and RxR, and is also output at the E1.5o pin. The circuit has been designed to operate within the constraints imposed by the minimum 1’s density requirements, typically specified for T1 networks (maximum of 15 consecutive 0’s).

The extracted clock is internally divided by 193 and aligned with the received D S1 frame. The resulti ng 8

kHz signal is output at the E8Ko pin and can be used to phase lock the local system C2 and t he transmit C1.5 clo c ks to the extracted clock .

The MH89760B requires three clock signals which have to be generated externally. The ST-BUS interface on the device requires a 2.048 MHz signal which is applied at the C2i pin and an 8 kHz framing signal applied at the F0i

pin. The framing signal is used to delimit individual STBUS frames. Figure 19 illustrates the relationship between the C2i and F0i

signals. The F0i signal can be derived from the 2.048 MHz C2 clock. The transmit side of the DS1 interface requires a 1.544 MHz clo c k a ppl ied at C1.5i . Th e C1.5 and C 2 cl o c k s must be phase locked. There must be 193 clock cycles of the C1.5 clock for every 256 cycles of the C2 clock in order for the 2.048 to 1.544 rate converte r to fu ncti o n p rop er ly.

In synchronous operation the slave end of the link must have its C2 and C1.5 clocks phase locked to the extracted clock. In plesiochronous clocking applications where the master and slave end are operating under controlled slip conditions, phase locking to the extracted clock is generally not required.

Mitel’s MT8941 Digital Phase Lock Loop (DPLL) can be used to generate all timing signals requir ed by the MH89760B. The MT8941 has two DPLLs built into the device. Figure 5 shows how DPLL #1 can be set up to generate the C1.5 clock phase locked to the F0i

which in turn is derived from the same source as the C2 clock. Figure 5 also shows how DPLL #2 is set up to generate the ST-BUS clocks that are phase loc ked to th e r e cei ved d ata r a te. If E8 K o f ro m the MH89760B is connected to the C8Kb input on the MT8941, DPLL #2 in the device will generate the ST-B US clocks that are phase locked to the T1 line.

Figure 5 - M T894 1 Clock Ge nera tor

F0i C12i

MS1

C8Kb C16i MS0

MS2 MS3

F0b C4b C2o

ENC4o ENC2o

CVb

ENCv

C1.5 +5V

F0i C4i C2i

+5V

MT8941

DPLL #1

DPLL #2

Page 13

4-67

Preliminary Information MH89760B

Figure 6 - Input/Output Configuration

Extracted Clock

Received Data

Transmit Data

OUTA

+12V

OUTB

:0.5

L1 C1

EIT EIR

EA EB EC

SW RCLT RCHT RCLR

RCHR Ti Ri

E1.5o

RxA RxB

RxT

RxR

S1 S2

S4 S5

S6 S7

TxT TxR

TL RL

TR2

Line

Receiver

S1 S2 S4 S4 S5 S6 S7

0-150’

OPEN OPEN OPEN OPEN OPEN OPEN

150-450’

OPEN

450-655’

OPEN OPEN

OPEN

Equalizer settings

COMPONENT VALUES:

R1 = 150Ω 1% W C1 = 0.01 µF 5% 250V C2 = 0.47 µF 5% 100V L1 = 33 µH 130mA L2 = 33 µH 165 mA TR1 = 1:1:0.5 Filtran* Part # TFS2573 TR2 = 1:1:1 Filtran* Part # TFS2574

*Filtran Ltd. 229 Colonnade Road Nepean, Ontario Canada K2E 7K3 613-226-1626

Note: The equalizer has been optimized for 22 gauge ABAM cable. The exact distances may vary with the type of cable and the output transformer. D ifferent line length settings may be required if a transformer other than the Filtran TFS2573 is used.

1 4

+5V

MH89760B

MH89761

TR1

DS1 Line Interface

Line Transmitter

The transmit line interface is made up of two open collector drivers (OUTA and OUTB) that can be coupled to the line with a center tapped pulse transformer (see Figure 6). A step function is applied

to the transformer when either of the transistors is turned on. By operating in the transient portion of the inductance response, the secondary of the transformer produces an almost square pulse. The capacitor and inductor on the center tap of the transmit transformer shown in Figure 6 suppress transients in the 12 volt supply. The series RLC across the output of the transformer shape the pulse to meet the AT & T or CCITT pulse templates. A

Page 14

4-68

MH89760B Preliminary Information

detailed transformer specification is presented in the applications se ction of this data sheet.

To comp l ete the interface s to the transmit lin e , a p re equalizer and line impedance matching network is required. The pulse output at the transformer secondary must be pre-equalized to drive different lengths of cable. Mitel‘s MH89761 T1 Equalizer is configurable to provide pre-emphasis for 0-150, 150450 and 450-655 foot lengths of 22 AWG transmission line. A separate 6dB pad is also provided on the MH89761 for use in implementing external looparound. Both circuits have input and output impedance of 100Ω. Figure 6 shows how the equalizer is connected in a typical application. (Refer to the MH89761 data sheet for more details.)

Line Recei ver

The bipolar receiver inputs on the device, RxT and RxR, are intended to be coupled to the line through a center tapped pulse tr ansformer as shown in Figure

6. The device presents a 400Ω impedance to the receive transformer to permit matching to 100Ω twisted pair cable. The signal detect threshold level

of the receiver circuit is set at approximately 1.5V. There is no equalization of the received signal. The receiver circuit is designed to accurately decode a signal attenuated by a maximum of 3 dB from the digital crossconnect point. The MH89760B is not designed to directly accept a signal from the last network repeater. Interface to the public network generally requires a Channel Service Unit (CSU). The receiver decodes the bipolar signal into a split phase unipolar return to zero format. The two resulting unipolar signals are used for bipolar violation detection within the device and are also output at RxA

and RxB. The input jitter tolerance of

the MH89760B is shown in Figure 7.

Elastic Buffe r

The MH89760B has a two frame elastic buffer which absorbs jitter in the received DS1 signal. The buffer is also used in the rate conversion between the

1.544 Mbit/s DS1 rate and the 2.048 Mbit/s ST-BUS data rate.

Figure 7 - I npu t Jitte r Tolerance of the M H89 760B

120

40k

Typical input jitter tolerance of MH89760B receiver.

Minimum jitter tolerance specified by CCITT in Recommen dati on I.431.

➀ ➁

I T T E R

A M P L I T U D E

10010 1k 10k 100k

JITTER FREQUENCY (Hz)

(UI)

➀

➁

0.1

0.5

1.3

Page 15

4-69

Preliminary Information MH89760B

The received data is written into the elastic buffer with the extracted 1.544 MHz clock. The data is read out of the buffer on the ST-BUS side with the system

2.048 MHz clock. The maximum delay through the buffer is 1.3 ST-BUS frames (i.e., 42 ST-BUS channels). The minimum delay required to avoid bus contention in the buffer memory is two ST-BUS channels.

Under normal operating conditions, the system C2i clock is phase locked to the extracted E1.5o clock using external circuitry. If the two clocks are not phase-locked, then the rate at which the data is being written into the device on the DS1 side may differ from the rate at which it is being read out on the ST-BUS side. The buffer circuit will perform a controlled slip if the throughput delay conditions described above are violated. For example, if the data on the DS1 side is being written in at a rate slower than what it is being read out on the ST-B US side, the delay between the received DS1 write pointer and the ST-BUS read pointer will begin to decrease over time. When this delay approaches the minimum two channel threshold, the buffer will perform a controlled slip which will reset the internal ST-BUS read pointers so that there is exactly 34 channels delay between the two pointers. This will result in some ST-BUS channels containing information output in the previous frame. Repetition of up to one DS1 frame of information is possible.

Conversely, if the data on the DS1 side is being written into the buffer at a rate faster than that at which it is being read out on the ST-BUS side, the delay between the DS1 frame and the ST-BUS frame will increase over time. A controlled slip will be performed when the throughput delay exceeds 42 ST-BUS channels. This slip will reset the internal STBUS counters so that there is a 10 channel delay between the DS1 write pointer and the ST-BUS read pointer, resulting in loss of up to one frame of received DS1 data.

Note that when the device performs a controlled slip, the ST-BUS address pointers are repositioned so that there is either a 10 channel or a 34 channel delay between the input DS1 frame and the output ST-BUS frame. Since the buffer performs a controlled slip only if the delay exceeds 42 channels or is less than 2 channels, there is an 8 channel hysteresis built into the slip mechanism. The device can, therefore, absorb 8 channels or 32.5µs of jitter in the received signal.

There is no loss of frame sync, multiframe sync or any errors in the signalling bits when the device performs a slip. The information on the FDL pins in

ESF or SLC-96 mode will, however, undergo slips at the same time .

Framin g Algo ri t h m

A state diagram of the framing algorithm is shown in Figure 8. The dotted lines show which feature can be switched in and out depending upon the operating mode of th e device.

In ESF mode, the fr amer searches for the FPS bits. Once this pattern is detected and verified, bit 0 in Master Status Word 1 is cleared.

When the device is operating in the D3/D4 format, the framer searches for the F

pattern, i.e., a repeating 1010... pattern in a specific bit position every alternate frame. It will synchronize to this pattern and declare valid terminal frame synchronization by clearing bit 0 in Master Status Word 1. The device will subsequently initiate a search for the F

pattern to locate the signalling

frames (see Table 4). When a correct F

pattern has been located, bit 3 in Master Status Word 1 is cleared indicating that the device has achieved multiframe synchronization.

Note: the device will remain in terminal frame synchronization even if no F

pattern can be located.

In D3/D4 for mat, when the C RC/MI MIC bit i n M aster Control Word 1 is cleared, the device will not go into synchronization if more than one bit position in the

frame has a repeating 1010.... pattern, i.e., if more

than one candidate for the terminal framing position is located. The framer will continue to search until only one terminal framing pattern candidate is discovered. It is, therefore, possible that the device may not synchronize at all in the presence of PCM code sequences (e.g., sequences generated by some types of test signals) w hich contain mimics of the termin a l fra ming pattern .

Setting CRC/MIMIC bit high will force the framer to synchronize to the first terminal framing pattern detected. In s tandard D3/D4 applications, the user ’s system software should monitor the multiframe synchronization state indicated by bit 3 in Master Status Word 1. Failure of the device to achieve multiframe synchronization within 4.5ms of terminal frame synchronization, is an indication that the device has framed up to a terminal framing pattern mimic and should be forced to reframe.

One of the main features of the framer is that it performs its function "off line". That is, the framer repositions the receive circuit only when it has

Page 16

4-70

MH89760B Preliminary Information

Figure 8 - Off-L ine Fr amer Sta te Diagr am

Hunt Mode

False Candidate

False

Candidate

Forced

Reframe Out of Sync.

False Candidate

Candidate

CRC

Check

In sync

Candidate

Vali d Ca n didate

Resync

Receiver

Valid Candidate

New Frame Position

* Note: Only when in ESF mode and CRC option is enabled.

Maintenance

Verify

detected a val id frame positio n. When the framer exits maintenance mode the receive counters remain where they are until the framer has found a new frame position. This means that if the user forces a reframe when the device was really in the right place, there will not be any dis turbance in the circuit because the framer has no effect on the receiver until it has found synchronization.

The out of

synchronization criterion can be controlled by bit 0 in Master Control Word 2. This bit changes the out of frame conditions for the maintenance state.

The out of sync threshold can be changed from 2 out of 4 errors in F

(or FPS) to 4 out of 12 errors in F

(or FPS). The average reframe time is 24 ms for ESF mode, and 12ms for D3/D4 modes.

Figure 9 is a bar graph which shows the probability of achieving frame synchronization at a specific time .

The chart shows the results for ESF mode with CRC check, and D3/D4 modes of operation. The average reframe time with random data is 24 ms for ESF, and 13 ms for D3/D4 modes. The probability of a reframe time of 35 ms or less is 88% for ESF mode, and 97% for D3/D4 modes. In ESF mode it is recommended that the CRC check be enabled unless the line has a high error rate. With the CRC check disabled the average reframe time is greater because the framer m ust also check for mimics.

Page 17

4-71

Preliminary Information MH89760B

Figure 9 - Reframe Time

AAA

078 10 12 14161820222426 28 3032 34

Reframe Time (ms)

Percentage Reframe Time Probability Versus Reframe Time

With Pseudo Random Data

ESF

Applications

1. Ty pical T1 Application

Figure 10 shows the external components that are required in a typical T1 application using the MH89760B. The MT8980 is used to control and monitor the device as well as

switch data to DSTi and

DSTo (refer to Application Note MSAN-123 for more information on the operation of the MT8980). The MT8952, HDLC protocol controller, is shown in this application to illustrate how the data on the FDL could be used. The digital phase-locked loop, the MT8941, provides all the clocks necessary to make a functional interface. The 1.544 MHz clock extracted by the MH89760B is used to clock in data at RxT and RxR. It is also internally divided by 193 to obtain an 8 kHz clock which is output at E8Ko. The MT8941 uses this 8 kHz signal to provide a phase locked 2.048 MHz clock for the ST-BUS interface and a 1.544 MHz clock for the DS1 transmit side.

Note: the configurations shown in Figures 10 and 12 using the MT8941 may not meet specific jitter performance requirements. A more sophisticated PLL may be required for applications designed to meet specific standards. Please refer to the MT8941 data sheet for further details on its jitter performance.

The split phase unipolar signals output by the MT8976 at TxA and TxB are used by the line driver circuit to generate a bipolar AMI signal. The line driver is transformer coupled to an equalization circuit and the DS1 line. Equalization of the transmitted signal is required to meet AT & T specifications for crossconnect compatible equipment (see AT&T Technical Advisory #34). Specifications for the input and output transformers are shown in Figure 11. On the receive side the bipolar line signal is converted into a unipolar format by the line receiver circuit. The resulting split phase signals are input at the RxA

and RxB pins on the MT8976. The signals are combined to produce a composite return to zero signal which is clocked into the MT8976 at RxD.

2. Interfacing the MH89760B to a Parallel Bus

The MH89760B can be interfaced to a high speed parallel bus or to a microprocessor using the MT8920B Parallel Access Circuit (STPA). Fig. 12 shows the MT8976 interfaced to a parallel bus structure using two STPA‘s operating in modes 1 and

The first STPA operating in mode 2 (MMS = 0, MS1=1, 24

/32=0), routes data and/or voice information between the parallel telecom bus and the T1 or CEPT link via DSTi and DSTo. The second STPA, operating in mode 1 (MMS=1) provides access from

Page 18

4-72

MH89760B Preliminary Information

Figure 10 - Typical ESF Configuration

Figure 11 - Typ ical Pa ramete rs of the In put and Outp ut Transformers

From other interfaces

C8Kb

C2o

MT8941

C4b C2o F0b F0i CVb

16.384 MHz Osc.

12.352

MHz Osc.

To other interfaces

MT8980

STi2 STo3

STo0

STi0 STi1

STo2

C4i

F0i

STo1

STo7 STi7

MT8926

E8Ko

RxA RxB

EClk

F0i

C2i

CSTi1

E8Ki

CSTi0

FDLo DSTo

CSTo DSTi0 DSTi1

IRQ 1SEC

FDLi

RxA

µP

INT0 INT1

CDSTo

TxCEN

RxCEN

CDSTi

CKi

MT8952

RxB E1.5o F0i C2i CSTi1 E8Ko CSTo TxFDL DSTi CSTi0 DSTo RxFDLClk RxFDL TxFDLClk

MH89760B

C1.5i

OUTA

OUTB

RxT

RxR

+12V

:0.5

To/From Other Interfaces

EIT EIR EA EB EC SW

RCLT RCHT RCLR RCHR Ti Ri

}

To other T1 Interfaces

To other Interfaces

MH89761

TxT TxR

TL RL

TR1

TR2

C2 = 0.47µF, 5% 100V L1 = 33µH, 130mA

R1=150Ω, 1%, 1/4w

C1 = 0.01µF, 5% 250V

L2 = 33µH, 165mA

R2 = 4.7KΩ R3 =4.7KΩ

XSt LOS

LOS

T1 RECEIVE

T1 TRANSMIT

TR1 & TR2 see Figures 6 & 11

Paramete r Input Transformer Output Transformer Units

Line Impedance 100 100 Ω Inductance (1-8) >2.2 (4-8) 0.46 mH Turns Ra ti o (1-8) :( 3- 6) 1 :1

(1-8):(4-5) 1 :1

(1-5):(4-8) 1.89:1 (2-6):(4-8) 1.89:1

Isolation 1500 1500 V(rms)

Line Side

MH89760B

•

Line Side

MH89760B

•

Page 19

4-73

Preliminary Information MH89760B

Figure 12 - Using the MH 89 760B in a Para llel B us Env iron ment

MH89760B

MT8920B

(Mode 2)

0-D7

A0-A

CS R/W OE

MMS MS1 24/32

STo0

STi0

STo1

C4i

F0i

+5V

MT8976

E8Ko

RxD

RxB

RxA

TxB

TxA

E1.5i

C1.5i

C2i

F0i

CSTi1

CSTo

CSTi0

DSTo

DSTi

Clock

Extractor

MMS

High Speed

Parallel

Telecom Bus

Line

Driver

Line

Driver

OUTA

OUTB

RxT

RxR

EQU

DIP

Switch

MT8941

CVb F0i

C2o F0b C4b C8Kb

12.352 MHz Osc.

16.384 MHz Osc.

•

MH89761

Signalling and

Link Control

BUS

IACK

IRQ

DTACK

R/W

A0-A

D0-D

STo0

STi0

STo1

C4i

F0i

MT8920B

(Mode 1)

1.544 MHz

the signalling and link control bus to the MH89760B status and control channels. All signalling and link functions may be controlled easily through the STPA transmit RAM’s Tx0, Tx1, while status information is read at receive RAM Rx0. In addition, interrupts can be set up t o no tify the system in ca s e o f s l ips , lo s s of sync, alarms, violations, etc.

3. PCM/Voice Channel Ban k

The D3/D4 channel bank is one of the most widely used pieces of equipment in the North American network today. The D3/D4 channel converts 24 analog telephone lines into the 24 channels of a T1 serial stream. The channel bank is the int erface point between a digital switching or transmission system and the analog telephone loop. The industry is moving towards end-to-end digital connections (ISDN), but the analog channel bank will still be in use for ma ny y ea r s to come.

Figure 13 shows a block diagram of a channel bank that has been div ided into four sections, the analog line interface, signalling interface, switch matrix, and T1 interface. The subscriber line interface circuit (SLIC) provides interface to the telephone line, i.e., provides loop current and ringing voltage, and converts the analog voice signal into µ-Law PCM. The SLIC also detects the off-hook condition for conventional POTS (Plain Old Telephone Set) signalling.

Once the voice is encoded into digital format the switch matrix transfers the 24 consecutive channels that are received from the SLICs to the 24 valid channels used by the MH89760B. The MH89760B formats and transmits this information on the T1 line.

Signalling information from the telephone sets can be routed straight through to the output T1 channel, or it can be routed to the DTMF receiver pool. This is

Page 20

4-74

MH89760B Preliminary Information

Figure 13 - PCM/Voice Data Channel Bank

Switch Matrix

T1 Interface

Equal-

izer

12.352

MHz Osc.

16.384

MHz Osc.

MT8941

DPLL#1

CVb F0i

C12i

DPLL#2

F0b

C4b C2o

C8Kb

C16i

MH89760B

DSTi DSTo

CSTi0 CSTo CSTi1

C2i

F0i C1.5i

OUTA

OUTB

RxR

E8Ko

RxT

µP

MT8980

STo0 STi0 STo3

STi3

F0i C4i

STo1

STi1

STo2

STi2

STo4

C1.5i

C2i

C4i

F0i

Shift

Reg.

MT8870

MT8964

MT8870

MT8964

Shift

Reg.

CTLo OFHK

MUX

Signalling Interface

Analog Line Interface

SLIC #1

CTLi

OFHK

STD

D3 Do

STD

PCMi

PCMo

•

SLIC #24

easily accomplished by the MT8980 switch matrix once the SLIC has digit ized the analog signal.

Channel banks must be able to operate in a loop timed mode so that they meet the clock synchronization requirements of a level four entity. Phase-locked loop #2 of the MT8941 generates the ST-BUS clocks that are synchronized to the extracted 8kHz clock, and phase-locked loop #1 generates the transmit T1 clock synchronized to the ST-BUS.

4. ISDN Voice/Data Channel Bank/Concentrator

The ISDN channel bank is a term that is used in this context to describe a system that performs the s ame logical function as the D3/D4 channel bank. That is, it concentrates the subscribers digital loop into the primary digital transmission scheme, the T1 trunk.

The ISDN channel bank in Figure 14 is divided into four blocks, the digital line interface, the switch matrix, the D channel processing, and the T1 interface. Beg in n ing with th e digita l lin e interface, the MT8910 provides 2B+D 160k bit bidirectional communication over single twisted pair wiring. The MT8910 converts the 160kbit line signal into ST-B us format, where it can be manipulated by the MT8980 switch matrix. The data received from the MT8910 is then transferred to the D channel processor by the switch matrix. The D channel processor converts the 2B+D format used on the 160 kBit digital line into the 23B+D format used on the T1 Link.

Page 21

4-75

Preliminary Information MH89760B

Figure 14 - ISDN Voice Data Channel Bank

Digital Line Interface

Switch Matrix

T1 Interface

MT8910

MT8980

MT8910

MT8952 MT8952

MT8952

MT8941

DSTo DSTi

DSTo

DSTi

STi0 STo0

C4i F0i

STo1

STi1

STo2

STi3

STo3

D-Channel Processing

DSTi DSTo

CSTi0 CSTo

CSTi1

C2i

C1.5i

OUTA

OUTB

RxR

RxT

E8Ko

F0i

E8Ko

C4o

C2o

F0o

C1.5

Equal-

izer

µP

•

MH89760B

•

To control and monitor the MT8910s and the T1 interface the switch matrix operates some of its input and output streams in m essage mode. This enables the system to control all of the functions of the MT8910s and the T1 interface through the Control ST-BUS points, (CS Ti/o).

Clock synchronization is done by the MT8941. Phase-locked loop # 2 generates ST-BUS clocks that are synchronized to the extracted 8kHz output from the T1 interface. Phase-locked loop #1 generates the transmit T1 clock synchronized to the ST-BUS clocks, which are synchronized to the extracted T1 clock. This scheme will also allow the system to operate in a loop timed mode.

With appropriate multiplexing a single D channel processor can handle all 23 2B+D interfaces. If both B channels on all 24 lines are going to be used then it would be necessary to use two T1 trunk interfaces.

5. Digital Acc ess Cr oss Co nnect S ystem (DACS)

The Digital Access Cross Connect System (DACS) is a T1 switch with 127 T1 lines as input and output plus one T1 line that is reserved for test and maintenance purposes. A DACS is capable of switching any input channel on any T1 trunk to any output c hannel on any T1 trunk.

There are four main blocks in Figure 15, the T1 interfaces, the switch m atrix, the c ontrol matr ix, and the clock generator. The digital trunk interface is made up of the MH89760B plus the additional components required to interface to the transmission line. The MH89760B handles all of the required transmit and receive data formatting, and converts the 1.544 MHz serial stream into ST-BUS format so that it can be routed through the MT8980 synchronous s wi tch matrix.

Page 22

4-76

MH89760B Preliminary Information

The switch matrix can be built so that the maximum throughput delay is 1 frame +2 channels. The switch matrix will not only route data channels to their destination, but it will also route the received signalling bits through to the destination channel. This is necessary because the receiving MH89760B decodes the T1 stream, and the transmitting MH89760B has to reconstruct the outgoing T1 stream. In other words, there is no multiframe integrity between received data and transmitted data. The total throughput delay is one frame plus ten ST-BUS channels for the MH89760B receiver,

2.5 ST-B US channels for the MH89760B transmitter, and one frame plus two ST-BUS channels for the switch matrix for a total of 2.5 frames wo r st c a se.

The control block only interfaces with the switch matrix. Besides routing channels and signalling

through to the proper destination, the switch matrix must also supply the Master Control Words, and monitor the Master Status Words for each MH89760B.

The clock generation block supplies the ST-BUS clocks and the T1 transmit clocks that are synchronized to one of the T1 trunks. All of the extracted 8 kHz outputs are NANDed together before they are input to PLL #2 of the MT8941.

Phase-locked Loop #2 of the MT8941, will generate ST-BUS clock signals for the MH89760Bs and the MT8980s that are synchronized with the chosen T1 line. The E8Ko of all of the other MH89760Bs can be tristated from the Master Control Word, which allows the system controller to select any one of 128 T1 lines to act as the synchronization source. By

Figure 15 - Digital Access C ross Connec t System (DACS)

AAAA

Switch Matrix

M I C R O

Control Matrix

MT8980

MT8941

MH89760B

T1 Interfaces

Clock Generator

izer

Equal-

izer

DSTi DSTo

CSTi0 CSTo CSTi1

C2i

F0i C1.5i

OUTA

OUTB

RxT

RxR

E8Ko

DSTi DSTo

CSTi0 CSTo CSTi1

C2i

F0i C1.5i

OUTA

OUTB

RxT

RxR

E8Ko

STi7

STo7

STi0

STo0

F0i C4i

STi7

STo7

STi0

STo0

STo1 STo2

F0i

C4i C2i

C1.5i

CVb

F0i

F0b

C4b C20

DPLL #2

C12i

C16i

C8Kb

12.352

MHz Osc.

16.384

•

Equal-

DPLL #1

Page 23

4-77

Preliminary Information MH89760B

Figure 16 - Digital Multiplex Interface (DMI)

Asynchronous

Interface

Protocol Converter

Switch Matrix

T1 Interface

R S 2 3 2

ACIA

0-A7

D0-D

A0-A

D0-D

ACIA

Micro

68008

MT8952

0-D7

D0-D

A0-A

MT8941

STo3

STi2

STo2

STi1

STo1

C4i

F0i

STo0

STi0

F0i

C4i C2i

C2i

C1.5i

OUTA

OUTB

RxT

RxR

E8Ko

CSTi1

CSTo

CSTi0

DSTo

DSTi

izer

Equal-

CVb

C12iF0i

C4b

F0b

C20

C8Kb

DPLL #1

DPLL #2

12.352 MHz

Osc.

MHz

Osc.

16.384

•

R S 2 3 2

MT8980

MT89760B

connecting the frame pulse output, F0o, o f PLL #2 to F0i

of PLL # 1, the MT8941 will generate the T1

transmit clock that is phase-locked to F0o

, which i n turn is phase-locked to the master synchronization signal, E8Ko. If all of the T1 trunks are from the network any short term differences in the received data rate will be absorbed by the elastic buffer in the MH89760B.

6. Digital Multiplex Interface (DMI)

Figure 16 illustrates an implementation of the Digital Multiplex Interface (DMI) specification, which defines a computer to PBX interface. This interface can convert 300 baud to 64 kbaud asynchronous or synchronous data channels to T1 format with clear channel capabilities and common channel signalling.

Figure 16 is broken down into four functional blocks which are the asynchronous interface (ACIAs), the

protocol convert er (micro and MT8952s), the switch matrix (MT8980), and the T1 interface (MH89760B).

The Asynchronous Communications Interface Adapters (ACIA) provide a standard RS232 interface that is compatible with many off-the-shelf modems and data sets. A single microprocessor is capable of handling t he protocol conversion between the RS232 ports and the MT8952 HDLC protocol controller.

The MT8952 interfaces directly to the ST-BUS, which in turn interfaces directly to the T1 interface devices. Instead of the MT8952 operating at 64 kbit/s continuously, it operates at 2.048 Mbit/s and inputs/outputs an 8 bit burst every 125 µsec. This feature eliminates the need for an additional rate conversion circuit to multiplex the HDLC outputs up to the T1 data rate. Each of the HDLC chips is assigned a t imeslot on the ST-BUS in a manner that is similar to enabling a voice codec. When the MT8952 is not enabled the output driver is tris tated.

Page 24

4-78

MH89760B Preliminary Information

The channel assignment circuit is therefore very simple.

The switch matrix, in the message mode, passes monitor and control information between the microprocessor and the T1 interface over ST-BUS stream 0. The MT8980 is also used to reformat the ST-BUS data streams between the protocol converter and the MH89760B interface.

The MH89760B and the MT8941 form the T1 interface. The MH89760B converts the data received on the ST-BUS into a 1.544 MHz T1 stream. All of the formatting and decoding of the T1 signal is performed by this device. The MT8941 provides the clock synchronization required to operate in a loop timed mode. Digital phase-locked loop #2 provides ST-BUS clocks that are synchronized to the extracted 8kHz, and digital phase-locked loop #1 provides the transmit 1.544 MHz clock synchronized to the ST-BUS.

7. High Speed Data Transmission Link

High speed data links are becoming increasingly popular in private networks and computer

communications. The basic mode of transmission is to assemble data into packets (e.g., HDLC or ethernet) which are transported on a T1 link configured as a 1.536 Mbit/s serial channel. No T1 repeaters are required if the transmission link length is 1300 ft. or less (e.g., business complex or university). However, if the t ransmission link length is greater than 1300 ft., a repeatered T1 line must be leased from the local telephone operating company.

Figure 17 is divided into three functional blocks which are the protocol converter, switch matrix, and T1 interface. The protocol section is dependent on the particular format that is chosen. In this example it is assumed that the protocol is HDLC. The Transmit Clock Enable (TxCEN

) and the Receive Clock

Enable (RxCEN

) of the MT8952 are active for a period of 24 consecutive ST-BUS channels, and the clock speed is 2.048 MHz. This enables the protocol conversion section to interface directly to the switch matrix. The switch matrix switches the first 24 channels received from the protocol section into the 24 valid tim eslots used by the MH89760B. Once the data enters the T1 interface the MH89760B formats and transmits the data on the T1 line.

Figure 17 - Hig h Spee d D ata Transmissio n Link

Protocol Converter

MT8952

CDSTo

CDSTi

TxCEN

RxCEN

F0i

C4i

MICRO

MT8980

STi0 STo0

STo1

STi1

STo2

STi2

STo3

F0i C4i

•

MH89760B

DSTi DSTo CSTi1

CSTo CSTi0

C2i

C1.5i

OUTA

OUTB

RxT

RxR

E8Ko

F0i

MT8941

DPLL #1

CVb

C1.5i

C12i

DPLL #2

F0b

C4b C20

C8Kb

C16i

C4i C2i

F0i

EQUAL-

IZER

12.352

MHz Osc.

16.384

MHz Osc.

•

T1 Interface

Switch Matrix

Page 25

4-79

Preliminary Information MH89760B

Control and monitoring of the T1 interface is done through the MT8980 switch matrix. CSTi0 and CSTo1 are connected to the ST-BUS streams that are configured for message mode so the controlling microprocessor can access the Master Control Words and the Master Status Words.

The received portion of the T1 interf ace extracts the data from th e T1 stream an d formats it into ST-BUS channels. The MT8980 switches these ST-BUS channels into the first 24 consecutive channels of an ST-BUS stream, which is passed to the protocol conversion block. HDLC packets are disassembled from the incoming ST-BUS stream by the MT8952.

Clock generation and synchronization are handled by the MT8941. DPLL #2 generates ST-BUS clocks that are phase-locked to the extracted 8KHz, and DPLL #1 generates the transmit T1 clock that is phase-locked to the ST-BUS frame pulse. Therefore, the interface is operating in a loop t imed mode and there will be no loss of information due to slips. The MT8941 can also be configured to operate in a master timing mode.

8. T1 to CEPT Digita l Trunk Convert er

The two main digital trunk transmission formats in use today are T1 and CEPT. Mitel's T1 and CEPT interfaces convert the digital trunk format into STBUS format. The c ommon element between the two

systems is the S T-BU S. Therefore, a T1 to CEPT digital trunk converter can be realized.

Figure 18 shows five blocks which are the T1 interface, switch matrix, CEPT interface, clock generation and synchronization, and DSP Element. The T1 interface converts the 1.544 MHz serial stream into the ST-BUS format which interfaces to the switch m atrix through DSTi and DSTo. The CEPT interface converts the 2.048 MHz serial s tream into the ST-BUS format and interfaces to the switch matrix through the DSP element.

With both the T1 data and the CEPT data converted to the ST-BUS format, the two digital trunks can exchange information through the switch matrix. Unfortunately, the s ignalling informa tion from the tw o formats is not exchanged as easily. The T1 A and B signalling bits must be read by the controlling microprocessor and converted in software to the CEPT ABCD signalling bits, and vice versa. The circuit must also convert all the channels carrying voice data to the appropriate encoding scheme, (i.e., T1 µ-Law or CEPT A-Law). This is done by the block labelled DSP in Figure 18, Digital Signal Processor.

The final component of the system is the MT8941. The extracted 8 kHz outputs from the T1 and the CEPT interfaces are combined with an AND gate before being connected to the MT8941. One of the

Figure 18 - T1 to CEPT Digital Trunk Converter

CEPT Interface

MH89790B

DSP

Element

Switch Matrix T1 Interface

MT8980

MH89760B

MT89 41

Clock Generator

µP

E8Ki

DPLL #1

DPLL #2

C1.5o

F0o C2o

C4o

RxA

RxB

F0i

OUTA

OUTB

DSTi

DSTo CSTi0 CSTi1

CSTo

C2i

E8Ko

STi0 STo0

STo3 STo4

STi4 C4i F0i

STo1

STi1 STi2

STo2 STo3

DSTi DSTo CSTo

CSTi0 CSTi1

F0i C2i

C1.5i E8Ko

RxT

RxR

OUTA

OUTB

Page 26

4-80

MH89760B Preliminary Information

interfaces is selected as the synchronization source by enabling its output through the Master Control Word of the chosen interface. Phase-locked loop #2 will then generate ST-BUS clocks that are synchronized to either the T1 net work or the CEPT network. Phase-locked loop #1 is configured to generate the T1 transmit clock synchronized to the ST-BUS. Therefore, i f th e S T-BUS is synch ro ni ze d to one network then the elastic buffer in the opposite interfaces will perform controlled slips between that network a n d th e T 1 to CE PT co n ve rt er.

Magnetics Information

For supporting initial design activities, Mitel Semiconductor has available the MH89760B Magnetic Kit which contains the magnetics shown in Figure 11. Alternatively, they are available directly from the following manufacturer:

Filtran Ltd. 229 Colonnade Road Nepean, Ontario Canada K2E 7K3 Telephone: (613) 226-1626

Please refer to Figure 6 for the transformer part numbers.

Page 27

4-81

Preliminary Information MH89760B

* Exceeding these values may cause pe rman ent dama ge. Functi on al operati on under these co ndition s is not implie d.

‡ Typical figures are at 25° C and are for design aid only: not guaranteed and not subject to production testing.

† Timing is over recomm end ed temperatu re & powe r suppl y volt age s. ‡ Typical figures are at 25° C and are for design aid only: not guaranteed and not subject to production testing.

Absolute Maximum Ratings*

Parameter Symbol Min Max Units

1 Supply Voltage with respect to V

-0.3 7 V

2 Voltage on any pin other than supplies, OUTA or OUTB V

-0.3 VDD+0.3 V 3 Voltage on OUTA or OUTB 15 V 4 Current at any pin other than supplies, OUTA or OUTB 20 mA 5 Current at OUTA or OUTB 200 mW 6 Storage Tem perature T

-20 85 °C

Recommended Operating Conditions - Voltages are with respect to ground (V

) unless otherwise stated.

Parameters Sym Min Typ‡Max Units Test Conditions

I n p u

Operating Temperature T

070°C

2 Supply Voltage V

4.5 5.0 5.5 V

3 Input High Voltage V

2.4 V

V Digital Inputs

3.0 V Line Inputs

4 Input Low Voltage V

0.4 V Digital Inputs

0.3 V Line Inputs

DC Electrical Characteristics - Clo cked operat io n over recom men ded tem pera tu re ran ges.

Paramete rs Sym Min Ty p‡Max Units Test Condi tio ns

n p u

Supply Current I

12 25 mA Outputs Unloaded

2 Input High Voltage V

2.0 V Digital In put s

3 Input Low Voltage V

0.8 V Digital Input s

4 Input Leakage Current I

±1 ±10 µA Digital Inputs VIN=0 to V

p u

Output High Current I

7 20 mA Source Current VOH=2.4V

6 Output Low Current I

2 10 mA Sink Current VOL=0.4V

7 Output Low Voltage

OUTA or OUTB

0.25 V IOL=10mA

8 Input Impedance RxT to RxR

RxT or RxR to Gnd

400 Ω

1K Ω

9 Schmitt Trigger Input (XSt) V

T+

4.0 V

T-

1.5 V

AC Electrical Characteristics† - Capacitance

Characteristics Sym Min Typ

‡

Max Units Test Con di tions

1 Input Pin Capacitance C

10 pF

2 Output Pi n Ca pacit a n ce C

10 pF

Page 28

4-82

MH89760B Preliminary Information

NB: Fram e Pu ls e is r e pe ate d ev er y 1 25 µ s in synchronization with the clock. † Timing is over recommended temperature & power supply voltages.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Figure 19 - C lock & F ram e Alignm ent for ST-BUS Streams

Figure 20 - Clock & Frame Pulse Timing for ST-BUS Streams

AC Electrical Characteristics† - Clock Timing (Figures 19 & 20)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1 C2i Clock Period t

p20

400 488 600 ns

2 C2i Clock Width High or Low t

W20

200 244 300 ns t

P20

= 488 ns

3 Frame Pulse Setup Time t

FPS

50 ns

4 Frame Pulse Hold Time t

FPH

50 ns

5 Frame Pulse Width t

FPW

50 ns

6 RxSF

Output Delay t

FPOD

125 ns 50 pF Load

7TxSF

Hold Time t

TxSFH

0.5 124.5 µs

8TxSF

Setup Time t

TxSFS

0.5 124.5 µ s

F0i

RxSF

TxSF

C2i

ST-BUS BIT CELLS

Fram e 12/24

Frame 1

Frame 2

Bit7Bit6Bit5Bit

AAAA

C2i

F0i

RxSF

F0i

C2i

TxSF

P20

W20

FPS

FPH

FPS

FPOD

TxSFH

TxSFS

Fram e 12/24

Frame 1

FPW

W20

Page 29

4-83

Preliminary Information MH89760B

† Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25 °C and are for design aid only; not guaran tee d and not subject to producti on test ing.

Figure 21 - D S1 Re ceiv e Clock Tim ing

† Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25° C and are for desi gn aid only; not gua rantee d and not subje ct to producti on testing.

Figure 2 2 - ST-BUS Strea m Ti mi ng

AC Electrical Characteristics† - Timing For DS1 Link Bit Cells (Figure 21)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1 E1.50 Clock Period t

PEC

648 ns

2 E1.5o Clock Width High or Low t

WEC

324 ns

3 E1.5o Clock Rise Time t

REC

60 n s

4 E1.5o Clock Fall Time t

FEC

20 n s

AC Electrical Characteristics† - 2048 kbit/s ST-BUS Streams (Figure 22)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1 Serial Output Delay t

SOD

125 ns 150 pF load

2 Serial Input Setup Time t

SIS

15 ns

3 Serial Input Hold Time t

SIH

50 ns

DS1 BIT CELLS FOR RECEPTION

E1.5o

BIT CELL

R1EC

W1EC

P1EC

R1EC

W1EC

SOD

SIH

Bit Cell Boundari e s

C2i

DSTo or CSTo

DSTi, CSTi0/CSTi1

SIS

SOD

Page 30

4-84

MH89760B Preliminary Information

† Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25°C and are for design aid only; not gua rantee d and not subje ct to producti on testing.

AC Electrical Characteristics† - XCtl, XSt, & E8Ko (Figures 23, 24, & 25)

Parameters Sym Min Typ

‡

Max Units Test Cond itions

1 External Control Delay t

XCD

140 ns

2 External Status Setup Time t

XSS

100 ns

3 External Status Hold Time t

XSH

400 ns

4 8 kHz Output Delay t

8OD

150 ns

5 8 kHz Output Low Widt h t

8OL

78 µs

6 8 kHz Output High Widt h t

8OH

47 µs

7 8 kHz Rise Time t

10 ns

8 8 kHz Fall Time t

10 ns

Figure 23 - XCtl Timing

ST-BUS Bit Cell Boundary Between

Bit 0 Channel 15 and Bit 7 and Channel 16

C2i

XCtl

2.0V

0.8V

XCD

2.4V

0.4V

Figure 24 - XSt Timing

ST-BUS Bit Cell Bound ary Betwe en

Bit 2 Channel 30 and Bit 1 Channel 30

C2i

XSt

2.0V

0.8V

2.0V

0.8V

XSH

XSS

Figure 25 - E8Ko Timing

Received DS1 Bits

E1.5o

E8Ko

Channel 2

Bit 1

Channel 17

Bit 2

Chan nel 2

Bit 1

• • •

8OD

8OL

8OH

Page 31

4-85

Preliminary Information MH89760B

† Timing is over recommended operating temperature and power supply voltage ranges. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

Figure 26 - Transmi t Timin g for D S1 L ink

Figure 2 7 - Receive Timing for DS1 Link

AC Electrical Characteristics† - DS1 Link Timing (Figures 26 and 27)

Characteristics Sym Min Typ‡Max Un its Test Conditions

1 Transmit Steering Delay t

TSD

50 150 ns 150 pF Load

2 E1.5o Clock Period t

PEC

648 ns

3 E1.5o Clock Width High or Low t

WEC

324 ns

4 Receive Data Setup Time t

RDS

50 ns

5 Receive Data Hold Time t

RDH

50 ns

6 Receive Data Pulse Width t

RDW

324 ns

7 Receive Data Fall Time t

RDF

20 ns

8 Receive Data Rise Time t

RDR

20 ns

9 C1.5i Period t

PC1.5

500 648 800 ns

10 C1.5i Pulse Width High or Low t

WC1.5

250 324 ns

Transmitted DS1 Link Bit Cells

Bit Cell

C1.5i

OUTA

TSD

OUTB

PC1.5

WC1.5

Received DS1 Link Bit Cells

Bit Cell

E1.5o

RxA or

RxB

PEC

WEC

RDS

RDH

RDF

RDW

RDR

Page 32

4-86

MH89760B Preliminary Information

† Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25°C and are for design aid only; not gua rantee d and not subje ct to producti on testing

Figure 28 - Clock & Frame Alignment for RxFDL and TxFDL

Figure 29 - Facility Data Link Timing

AC Electrical Characteristics† - DS1 Link Timing (Figures 28 & 29)

Parameters Sym M i n Typ‡Max Units Test Conditions

1 Transm it FDL Setu p Time t

DLS

110 ns

2 Transmit FDL Hold Time t

DLH

70 ns

3 Receive FDL Output Delay t

DLOD

0 ns 50 pF Load

4 Receive FDL Clock Delay t

FRCD

185 50 pF Load

5 Transmit FDL Clock Delay t

TFCD

135 ns 50 pF Load

Frame 12/24

Frame 1

Frame 2

F0i

C2i

RxFDLClk

RxFDL

TxFDLClk

TxFDL

DLS

DLH

C2i

TxFDLClk

RxFDLClk

RxFDL

TxFDL

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

Frame

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

TFCD

RFCD

DLOD

Page 33

4-87

Preliminary Information MH89760B

Figure 30 - Format of 2048 kbit/s ST/BUS Streams

Figure 31 - DS1 L ink Frame Form at

Figure 32 - Functional ST-BUS Timing

Figure 33 - Functional DS1 Receive Timing

CHANNEL

030

NB: Numbering differs from Fig 31.

BIT 7

CHANNEL

31 0

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

• • • • • • • •

Most

Significant

Bit (First)

Least Significant Bit (Last)

125µs

(8/2.048)µ s

CHANNEL

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

NB: Numbering differs from Fig 30.

(1/1 .544)µs

S Bit

• • • • • •

Most

Significant

Bit (First)

Least Significan t Bit (Last)

125µs

(8/1.544)µs

C2i

DSTi

CSTi0/CSTi1

CSTo

DSTo

765 43210

••••• ••••••

765 43210 7

125µs

E1.5i

INT DATA

RxT/RxR

LINE SIGNAL

RxA

RxB

E8Ko

10111100

125µs

Page 34

4-88

MH89760B Preliminary Information

Figure 34 - DS1 Transmit Timing

C1.5i

INT DATA

OUTB

AMI LINE

OUTA

Packagin g

The MH89760B is available in three package options which are:

• The MH89760BS which is a surface mountable version of th e MH8 9760BN is sui table f or Infrared Reflow (I.R.) soldering. See Figure 35 for the dimensional drawing, and Figure 36 for the recommended footprint.

• The MH89760B which is pin compatible with the MH89760, has a ro w pitc h of 1.3” and is fitted with a plas tic lid. See Figur e 37 for the dimensiona l draw ing fo r this part .

• The MH89 760B N which is a narro w version of the MH89 76 0B an d has a r ow pi t ch of 0 .8” . See Figure 38 for t he di mens ional drawin g for thi s part.

Figure 35 - P hys ical Dim en sions for the 40 Pin Dual in L ine S.M .T. Hybrid

AAA

AAAA

AAA

0.020 + 0.002

(0.51 + 0.051)

0.10 +

0.01

(2.54 + 0.25)

MH89760BS

Note 1

Notes:

1) Pin 1 not fitted.

2) All dimensions are typical and in inches (mm).

3) Not to scale.

2.0

(50.8)

0.78

(19.81)

0.9

(22.86)

AAAA

0.25

(6.35)

0.125 (3.18)

0.06 (1.52)

0.125 (3.18)

Page 35

4-89

Preliminary Information MH89760B

Figure 36 - Recommended Footprint for the 40 Pin Dual in Line S.M.T. Hybrid

Figure 37 - Physica l Dimensions for the 40 Pin Dual in Line Hybrid 1.3" Row Pitch

0.760 (19.3)

Pin 2 position

0.040 (1.02)

0.060 (1.52)

0.090 (2.29)

AAAA

.31

(7.87)

0.260 (6.6)

0.09 (2.3)

0.020 +

0.002

(0.51 + 0.051)

0.10 +

0.01

(2.54 + 0.25)

MH89760B

Note 1

Notes:

1) Pin 1 not fitted.

2) Row pitch is to the centre of the pins.

3) All dimensions are typical and in inches (mm).

4) Not to scale.

2.12

(53.85)

1.3

(33.0)

Note 2

2.0

(50.8)

Page 36

4-90

MH89760B Preliminary Information

Figure 38 - Physica l Dimensions for the 40 Pin Dual in Line Hybrid 0.8" Row Pitch

AAA

AAAA

AAA

AAAA

MH89760BN

Note 1

Notes:

1) Pin 1 not fitted.

2) Row pitch is to the centre of the pins.

3) All dimensions are typical and in inches (mm).

4) Not to scale.

0.10 +

0.01

(2.54 +

0.25)

0.09 (2.3)

0.260 (6.6)

0.25

(6.35)

0.020 +

0.002

(0.51 +

0.051)

0.8

(20.32)

Note 2

2.0

(50.8)

Page 37

4-91

Preliminary Information MH89760B

Appendix

Control and Status Register Summary

Master Co ntro l Word 1 (C hann el 1 5, CSTi0)

Master Co ntro l Word 2 (C hann el 3 1, CSTi0)

Per Chan nel Co ntro l Words (A ll Chan nels on CSTi 0 Excep t Chan nels 3, 7, 11, 15, 19, 23 , 27 and 31)

Per Chan ne l C ont r ol Wo rd s (All Channels on CSTi1 Excep t Channels 3, 7, 11, 15, 19, 23, 27 & 31)

Master S tatus Wo rd 1 (Chan nel 15, CS To)

Master S tatus Wo rd 2 (Chan nel 31, CS To)

Phase Sta tus Word (Chan nel 3, CSTo)

Per Channel Status Word (All Channels on CSTo Except Ch annels 3, 7, 11, 15, 19, 23, 27, 31)

Note 1: I n ESF mode :

1: CRC calc. ignored during Sync. 0: CRC checked for Sync.

In D3/D4 mode:

1: Sync. t o first cor rec t S - bi t p at tern . 0: Will no t Sync. if M im ic d ete c ted .

76543210

Debounce

1 Disabled 0 Enabled

TSPZCS

1 Disabled 0 Enabled

B8ZS

1 B8ZS 0 Jammed

Bit

8KHSel

1 Disabled 0 Enabled

XCtI

1 Set High 0 Cleared

ESFYLW

1 Enabled 0 Disabled

Robbed Bit

1 Disabled 0 Enabled

YLALR

1 Enabled 0 Disabled

RMLOOP

1 Enabled 0 Disabled

DGLOOP

1 Enabled 0 Disabled

ALL1’s

1 Enabled 0 Disabled

ESF/D4

1 ESF 0 D3/D4

Reframe

Device

Reframes on

High to Low

Transition

SLC-96

1 Enabled 0 Disabled

CRC/MIMIC

See Note 1

Maint.

1 4/12 0 2/4

UNUSED - KEEP AT 0

Polarity

1 No Inversion 0 Inversion

Loop

1 Ch. looped

back

0 Normal

Data

1 Enabled 0 Disabled

UNUSED - KEEP AT 0

Txt. Sig. Bit

YLAIR

1 Detected

0 Normal

MIMIC

1 Detected

0Not

Detected

ERR

Error

Count

ESFYLW

1 Detected

0Not

Detected

MFSYNC

1 Not Detected

0 Detected

BPV

Bipolar

Violation

count

SLIP

Changes

State

when Slip

Performed

SYN

1 Out-of-Sync.

0 In-Sync

BlAlm

1 Detected 0 Not Detected

FrCnt

Frame

Count

XSt

1 Xst High 0 Xst Low

BIPOLAR VIOLATION COUNT CRC-ERROR COUNT

CHANNEL COUNT BIT COUNT

UNUSED

Rec’d. Sig. BitBRec’d. Sig. BitCRec’d. Sig. BitDRec’d. Sig. Bit

Page 38

4-92

MH89760B Preliminary Information

Notes:

Datasheet MT89760B, MT89760BN, MT89760BS Datasheet (MITEL)

Specifications and Main Features

Frequently Asked Questions

User Manual