Datasheet MT8930CE, MT8930CP, MT8930CC Datasheet (MITEL)

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CMOS ST-BUS  FAMILY

MT8930C

Subscriber Network Interface Circuit

Preliminary Information

Features

• ETS 300-012, CCITT I.430 and ANSI T1.605 S/T interface

• Full-duplex 2B+D, 192 kbit/s transmission

• Link activation/deactivation

• D-channel access contention resolution

• Point-to-point, point-to-multipoint and star configurations

• Master (NT)/Slave (TE) modes of operation

• Exceeds loop length requirements

• Complete loopback testing capabilities

• On chip HDLC D-channel protocoller

• 8 bit Motorola/Intel microprocessor interface

• Controllerless or microprocessor-controlled operation

• Mitel ST-BUS interface

• Low power CMOS technology

• Single 5 volt power supply

Applications

• ISDN NT1

• ISDN S or T interface

• ISDN Terminal Adaptor (TA)

• Digital sets (TE1) - 4 wire ISDN interface

• Digital PABXs, Digital Line Cards (NT2)

ISSUE 1 May 1995

Ordering Information

MT8930CC 28 Pin Ceramic DIP MT8930CE 28 Pin Plastic DIP MT8930CP 44 Pin PLCC

-40°C to +85°C

Description

The MT8930C Subscriber Network Interface Circuit (SNIC) implements the ETSI ETS 300-012, CCITT I.430 and ANSI T1.605 Recommendations for the ISDN S and T reference points. Providing point-topoint and poin t-to-multipoi nt digital tran smission, th e SNIC may be used at either end of the subscriber line (NT or TE).

An HDLC D-channel protocoller is included and controlled through a Motorola/Intel microprocessor port. A controllerless mode allows the SNIC to operate without a microprocessor.

The MT8930C is fabricated in Mitel’s CMOS process.

DSTi

DSTo

F0od

C4b

F0b

STAR/Rsto

CK/NT

Cmode

Rsti

ST-BUS

Interface

PLL

Timing

and

Control

HALF AD0-7 R/W/WR,

Figure 1 - Functional Bloc k Diagram

D-channel Priority

Mechanism

AFT/PRI

HDLC

Transceiver

Microprocessor Interface

DS/RD,

DinB

AS/ALE,

P/SC

CS,

DReq

S-Bus

Link

Interface

Link Activation Controller

IRQ

DCack

/NDA,

LTx

VBias

LRx

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MT8930C Preliminary Informatio n

LTx

AD1, IS1

AD2, SYNC/BA

39 38 37 36 35 34 33 32 31 30 29

LRx

NC STAR/Rsto Rsti

NC AD7, DR AD6, AR NC AD5, M/S AD4, MCH AD3, MFR NC

/WR, AFT/PRI

R/W

DS/RD

AS/ALE, P/SC

/NDA, DCack

IRQ

HALF

C4b

F0b F0od DSTi

DSTo

Cmode

CK/NT

, DinB

CS, DReq

VSS

1 2

3 4 5

6 7 8

9 10 11 12 13 14

28 PIN PDIP/CERDIP

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VDD VBias LTx LRx STAR/Rsto Rsti AD7, DR AD6, AR AD5, M/S AD4, MCH AD3, MFR AD2, SYNC/BA AD1, IS1 AD0, IS0

R/W

/WR, AFT/PRI

DS/RD

F0od DSTi

DSTo

NC NC NC

Cmode

CK/NT

, DinB

NCNCC4b

F0b

HALF

VDD

VBias

6 5 4 3 2 44434241 7 8 9 10 11 12 13 14 15 16

AS/ALE, P/SC

231819 2021 22 2425 2627 28

VSS

CS, DReq

/NDA, DCack IRQ

44 PIN PLCC

AD0, IS0

Figure 2 - Pin Connections

Pin Description

Pin #

DIP PLCC

12 HALFHALF Input/Output: this is an input in NT mode and an output in TE mode identifying

Name Description

which half of the S-interface frame is currently being written/read over the ST-BUS (HALF = 0 sampled on the falling edge of C4b

within the frame pulse low window, identifies the information to be transmitted/received in the first half of the S-Bus frame while HALF = 1 identifies the information to be transmitted/received into the second half of the S-Bus frame). Tying this pin to V

or V

free run. This signal can also be accessed from the ST-BUS C-channel.

in NT mode will allow the device to

2 3 C4b

4.096 MHz Clock: a 4.096 MHz ST-BUS Data Clock input in NT mode. In TE mode, a 4.096 MHz output clock phase-locked to the line data signal.

34 F0b

Frame Pulse: an active low frame pulse input indicating the beginning of active STBUS channel times in NT mode. Frame pulse output in TE mode.

47 F0od

Delayed Frame Pulse Output: an active low delayed frame pulse output indicating the end of active ST-BUS channels for this device. Can be used to daisy chain to other ST-BUS devices to share an ST-BUS stream.

5 8 DSTi Data ST-BUS Input: a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2

channels assigned to the first four timeslots. These channels contain data to be transmitted on the line and chip control information.

69 DSToData ST-BUS Output: a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and

B2 channels assigned to the first four timeslots respectively. The remaining timeslots are placed into high impedance. These channels contain data received from the line and chip status information.

713 CmodeController Mode Select Input: when high, microprocessor control is selected. When

low the controllerless mode is enabled and the microport pins are redefined as control inputs and status outputs.

8 14 CK/NT TE Clock/Network Termination Mode Select Input. For TE mode, this pin must be

tied to V applications). For NT mode, this pin must be tied to V

or to a 4.096 MHz clock (a clock is required for standard ISDN TE

. Refer to “ST-BUS Interface”

section for further explanation. A pull-up resistor is needed when driven by a TTL device.

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Preliminary Information MT8930C

Pin Description (continued)

Pin #

DIP PLCC

916R/W/WR

10 17 DS/RD

11 19 AS/ALE

Name Description

or Write Input (Cmode = 1): defines the data bus transfer as a read (R/

AFT/PRI

Read/Write

=1) or a write (R/W=0) in Motorola bus mode. Redefined to WR in Intel bus mode.

W Adaptive-Fixed Timing/Priority Select Input (Cmode=0): in NT mode, causes the PLL and Rx filters and peak detectors to be disabled in favour of fixed timing and fixed thresholds for short passive bus operation (0=fixed, 1=adaptive). In TE mode, this is the Priority input. High priority (PRI=1) is normally reserved for signalling.

Data Strobe/Read Input (Cmode = 1): active high input indicates to the SNIC that valid data is on the bus during a write operation or that the SNIC must output data during a read operation in Motorola bus mode. Redefined to RD

DinB

D-Channel in B1 Timeslot Input (Cmode = 0): active high input that causes all eight ST-BUS D-channel bits, instead of the usual two bits, to be routed to and from the S-interface B1 timeslot. When active, marks are transmitted in the S-interface D-channel.

Address Strobe/Address Latch Enable Input (Cmode = 1): in Motorola bus mode the falling edge is used to strobe the address into the SNIC during microprocessor access. Redefined to ALE in Intel bus mode.

P/SC

Parallel/Serial Control Input (Cmode = 0): determines if the serial C-channel

=0) or microport pins (P/SC=1) are the source of chip control when controllerless

(P/SC mode is selected. If the ST-BUS is chosen as the source, the dedicated Control input pins are ignored but the status output pins remain valid.

in Intel bus mode.

12 20 CS

DReq

13 21 IRQ

NDA

DCack

14 22 V

15-2224-26

AD0-7 Bidirectional Address/Data Bus (Cmode = 1): electrically and logically compatible to 30-32 34-35

15-1624-

IS0-IS1 Internal State Outputs (Cmode =0): Binary encoded state number outputs.

Chip Select Input (Cmode=1): active low input used to select the SNIC for microprocessor access. D-Channel Request Input (Cmode = 0): an active high input that in TE mode only causes the SNIC to transmit a “01111110” flag immediately if the D-channel is free, or wait until it becomes available and then transmit the flag. The DCack

signals the successful acquisition of the D-channel. If DReq is tied low, continuous ones are transmitted in the S-Bus D-channel. Internal Connection (Cmode = 0): tie to V

for normal operation in NT mode only.

Interrupt Request (Open Drain Output) (Cmode = 1): an output indicating an unmasked HDLC interrupt. The interrupt remains active until the microprocessor clears it by reading the HDLC Interrupt Status Register. This interrupt source is enabled with B2=0 of Master Control Register. New Data Available (Open Drain Output) (Cmode = 1): an active low output signal indicating availability of new data from the S-Bus. This signal is selected with B2=1 of Master Control Register. D-Channel Acknowledge (Open Drain Output) (Cmode = 0): in TE mode only indicates that the SNIC has gained access to the D-channel in response to a DReq and has transmitted the first zero of an opening flag. The user should immediately begin transmitting the rest of the packet over the ST-BUS D-channel. If this signal goes high in the middle of transmission, the TE has lost the bus and must regain access of the Dchannel before retransmitting the packet. Internal Connection (Open Drain Output) (C-mode=0). This pin is not used in NT mode and should be left disconnected. This pin must be tied to V

with a 10kΩ resistor.

Ground.

either Intel or Motorola micro-bus specifications. If DS/RD AS/ALE then the chip operates to Motorola specs. If DS/RD of AS/ALE Intel mode is selected. Taking Rsti

IS0 IS1 NT Mode TE Mode 0 0 deactivated deactivated 0 1 pending deactivation synchronized 1 0 pending activation activation request 1 1 activated activated

low sets Motorola mode.

is low on the rising edge of

is high on the rising edge

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MT8930C Preliminary Informatio n

Pin Description (continued)

Pin #

DIP PLCC

17 2 6 SYNC/B A Synchronization/Bus Activity Output (Cmode = 0): output indicating synchronization

18 30 MFR Multiframe Input/Output (Cmode=0): multi frame input in NT mode or output in TE

19 31 MCH Maintenance Channel (Q-channel) Input/Output (Cmode=0): an output in NT mode

20 32 M/S M/S Input/Output (Cmode=0): M/S bit input in NT mode or M/S bit output in TE mode.

21 34 AR Activate Request Input (Cmode = 0): asserting AR with DR = 0 will initiate the

22 35 DR Deactivate Request Input (Cmode = 0): asserting DR high will initiate the appropriate

Name Description

to incoming RX frames when activation request is asserted and the deactivation request is ’0’ (AR = 1 and DR = 0). Synchronization is declared once three successive frames conforming to the 14-bit bipolar violation criteria have been detected. If part is deactivated or activation request is ’0’ (AR = 0 or DR = 1), this pin indicates the presence of bus activity.

mode. Setting this pin to one in NT mode when HALF = 1, forces the F respectively. This pin going high in TE mode indicates that F received. This signal is updated on the rising edge of the HALF signal.

which is valid only in the frame following the transmission of MFR. In TE mode, this is the maintenance channel (Q-channel) input which is transmitted in the F following the reception of the multiframe signal. This input is sampled on the falling edge of the HALF signal.

M is read or written when HALF=1 while S is read or written when HALF=0.

appropriate S-interface activation sequence coded in the NT or TE activation/ deactivation controller.

S-interface deactivation sequence coded in the NT or TE activation/ deactivation controller.

, N pair to 1, 0

= 1 & N= 0 has been

and L bits

23 37 Rsti

Reset Input: Schmitt trigger reset input. If ’0’, sets all control registers to the default conditions, resets activation state machines to the deactivated state, resets HDLC, clears the HDLC FIFO‘s. Sets the microport to Motorola bus mode.

24 38 STAR/Rsto

Star/Reset (Open Drain Output): 192kbit/s Rx data output fixed relative to the STBUS timebase. A group of NTs, in fixed timing mode, can be wire or’ed together to create a Star configuration. Active low reset output in TE mode indicating 128 consecutive marks have been received. Can be connected directly to Rsti to reset all TEs on the bus. This pin must be tied to V

with a 10 kΩ resistor.

to allow NT

25 40 LRx Receive Line Signal Input: this is a high impedance input for the pseudoternary line

signal to be connected to the line through a 2:1 ratio transformer. See Figures 20 and

21. A DC bias level on this input equal to V

must be maintained.

Bias

26 42 LTx Transmit Line Signal Output: this is a current source output designed to drive a

nominal 50 ohm line through a 2:1 ratio transformer. See Figures 20 and 21.

27 43 V

Bias

Bias Voltage: analog ground for Tx and Rx transformers. This pin must be decoupled

through a 10µF capacitor with good high frequency characteristics (i.e.,

to V

tantalum).

28 44 V

1,5-6,1012,15,18,

23,27-

29, 33,

36, 39, 41

NC No Connection.

Power Supply Input.

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Preliminary Information MT8930C

Functional Description

The MT8930C Subscriber Network Interface Circuit (SNIC) is a multifunction transceiver providing a complete interface to the S/T Reference Point as specified in ETS 300-012, CCITT Recommendation I.430 and ANSI T1.605. Implementing both point-to-point and point-to-multipoint voice/data transmission, the SNIC may be used at either end of the digital subscriber loop. A pro grammable digital interface allows the MT8930C to be configured as a Network Termination (NT) or as a Terminal Equipment (TE) device.

The SNIC supports 192 kbit/s (2B+D + overhead) full duplex data transmission on a 4-wire balanced transmission line. Transmission capability for both B and D channels, as well as related timing and synchronization functions, are provided on chip. The signalling capability and procedures necessary to enable customer terminals (TEs) to be activated and deactivated, form part of the MT8930C’s functionality. The SNIC handles D-channel resource allocation and prioritization for access contention resolution and signa llin g re qui rem ents in pa ssive bus line configurations. Control and status information

allows implementation of maintenance functions and monitoring of the device and the subscriber loop.

An HDLC transc ei ve r is i n c lude d on th e S NI C for link access protocol handling via the D-channel. Depacketized data is passed to and from the transceiver via the micropro cessor port. Two 19 byte deep FIFOs, one for transmit and one for receive, are provided to bu ffer the da ta . The HD L C bl ock can be set up to transmit or receive to/from either the S-interface port or the ST-BUS port. Further, the transmit destination and receive source can be independe ntly selected, e.g., tran smit to S-interface while receiving from ST-BUS. The transmit and receive paths can be separately enabled or disabled. Both, one and two byte address recognition is supported by the SNIC. A transparent mode allows data to be passe d directly to the D channel without being packet ize d.

A block diagram of the MT8930C is shown in Figure

1. The SNIC has three interface ports: a 4-wire CCITT compatible S/T interface (subscriber loop interface), a 2048 kbit/s ST-BUS serial port, and a general purpose parallel microprocessor port. This 8-bit para lle l por t is comp ati ble with bot h Mo tor ola or

HALF

C4bi

F0bi

F0od

DSTi

DSTo

Cmode

/WR

R/W

DS/RD

AS/ALE

IRQ, NDA

VSS

HALF

C4bi

F0bi

F0od

DSTi

DSTo

Cmode

AFT

DinB

P/SC

VSS

NT MODE

1 2

3 4

5 6

7 8

9 10 11 12 13 14

NT MODE

9 10 11

13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VDD VBias LTx LRx STAR Rsti AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

VDD VBias LTx LRx STAR Rsti DR AR M/Si MCHo MFRi SYNC/BA IS1 IS0

CONTROLLER MODE

HALF

DSTo

Cmode

R/W

DS/RD

AS/ALE

IRQ, NDA

CONTROLLERLESS MODE

HALF

DSTo

Cmode

DReq

DCack

C4bo

F0bo F0od DSTi

/WR

VSS

C4bo

F0bo F0od DSTi

PRI

DinB

P/SC

VSS

TE MODE

1 2

3 4

5 6

7 8

9 10 11 12 13 14

TE MODE

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VDD VBias LTx LRx Rsto Rsti AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

VDD VBias LTx LRx Rsto Rsti DR AR M/So MCHi MFRo SYNC/BA IS1 IS0

Figure 3 - SNIC Pin Connections in Various Modes

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MT8930C Preliminary Informatio n

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SNIC also has provisions for a controllerless mode (Cmode=0), where the microprocessor port is redefined to allow access to the control/status registers via external hardware.

The three major blocks of the MT8930C, consisting of the system serial interface (ST-BUS), HDLC transceiver, and the digital subscriber loop interface (S-interface) are interconnected by high speed data busses. Data sent to and received from the S-interface port (B1, B2 and D channels) can be accessed from either the parallel microprocessor port or the serial ST-BUS port. This is also true for SNIC control and status information (C-channel). Depacketized D-channel information to and from the HDLC section can only be accessed through the parallel microprocessor port.

S-Bus Interface

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Intel microprocessor bus signals and timing. The

B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2

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B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2

The S-Bus is a four wire, full duplex, time division multiplexed transmission facility which exchanges information at 192 kbit/s rate inc luding two 64 kbit/s PCM voice or data channels, a 16 kbit/s signalling channel and 48 kbit/s for synchronization and overhead. The relative position of these channels with respect to the ST-BUS is shown in Figures 4 and 5.

Channel 1 (C) Channel 2 (B1) Channel 3 (B2)Channel 0 (D)

F0b

C7 C6 C5 C4 C3 C2 C1 C0

D0 D1 D2 D3 D4 D5 D6 D7

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DSTi

C7 C6 C5 C4 C3 C2 C1 C0

D0 D1 D2 D3 D4 D5 D6 D7

DSTo

Only valid with 64 kbit/s D-channel Output in high impedance state Don’t care

F0od

Figure 4 - ST-BUS Channel Assignment

The SNIC makes use of the first four channels on the ST-BUS to transmit and receive control/status and data to and from the S-interface port. These are the B, D and C-channels (see Figure 4).

The B1 and B2 channels each have a bandwidth of 64 kbit/s and are used to carry PCM voice or data across the network .

The D-channel is primarily intended to carry signalling information for circuit switching through the ISDN network. The SNIC provides the capability of having a 16 kbit/s or full 64 kbit/s D-channel by allocating the B1-channel timeslot to the D-channel. Access to the depacketized D-channel is only granted throug h the pa ral lel mi crop roce ss or por t.

The C-channel provides a means for the system to control and monitor the functionality of the SNIC. This control/status channel is accessed by the system through the ST-BUS or microprocessor port. The C-channel provides access to two registers which provide complete control over the state activation machine, the D-channel priority mechanism as well as the various maintenance functions. A detaile d de scri p tion of the s e regi ste rs i s discussed in the microprocessor port interface.

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Preliminary Information MT8930C

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B1 B1B1

62.5 µs Note: Shaded areas reveal data mapping

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B2 L LD1 B1B1 B1B1 B1 B1 B1 L D0 L B2 B2 B2 B2B1 B2 B2 B2 B2 L D1 LB2 L LD1 LFB1B1 B1 B1 B1 B1 B1 L D0 L Fa LB1 B2 B2 B2 B2 B2 B2 B2 FL

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B1 B1 B1B1 B1B1 EB1 D0 B2 B2 B2 B2 B2 B2 B2 B2 ES D1 L F L B1 B1FL B1B1 B1B1 B1B1 B1 E D0 A Fa NB2B2B2B2B1 B2 B2 B2 B2 E D1 M B1 B1 B1

62.5 µs

A = Activation bit

M = Multiframing bit

S = S-channel bit

B1 = Bit within B1-channel

B2 = Bit within B2-channel

Figure 5 - S-Bus Frame Structure and Functional Timing

62.5 µs

Fa & N (NT to TE) = Auxiliary framing bits

Fa (TE to NT) = Auxiliary framing bit or Q-channel bit

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F0b

DSTi

TEX

HALF

Output

NDA

F0b

NTR

DSTo

HALF

Input

F = Framing bit

L = DC balancing bit

D = Bit within D-channel

E = D-echo channel bit

9-41

F0b

NT to TE

NTX

Input

DSTi

HALF

NDA

F0b

DSTo

HALF

Output

TER

TE to NT

Page 8

MT8930C Preliminary Informatio n

Line Code

The line code used on the S-interface is a Pseudo ternary code with 100% pulse width as seen in Figure 6 below. Binary zeros are represented as marks on the line and successive marks will alternate in polarity.

BINARY

VALUE

LINE SIGNAL

0100010011

Violation

Figure 6 - Alternate Zero Inversion Line Code

A mark which does not adhere to the alternating polarity is kno wn as a bip olar viol atio n.

Framing

The valid frame structure transmitted by the NT and TE contains the following (refer Fig. 5):

NT to TE:

- Framing bit (F)

- B1 and B2 channels (B1,B2)

- DC balancing bits (L)

- D-channel bits (D0, D1)

- Auxiliary framing and N bit (Fa, N), N=Fa

- Activation bit (A)

- D-echo channel bits (E)

- Multiframing bit (M)

- S-channel bit

TE to NT:

- Framing bit (F)

- B1 and B2 channels (B1, B2)

- DC balancing bits (L)

- D-channel bits (D0, D1)

- Auxiliary framing bit (Fa) or Q-channel bit

The framing mechanism on the S-interface makes use of line code violations to identify frame boundaries. The F-bit violates the alternating line code sequence to allow for quick identification of the frame boundaries. To secure the frame alignment, the next mark following the frame balancing bit (L) will also produce a line code violation. If the data following the balancing bit is all binary ones, the zero in the auxiliary framing bit (Fa) or N-bit (for the direction NT to TE) will provide successive violations to ensure that the 14 bit

criterion (13 bit criterion in the direction TE to NT) specified in Recommendations I.430 and T1.605 is satisfied. If the B1-channel is not all binary ones, the first zero followin g the L-bit will violate th e line code sequence, thus allowing subsequent marks to alternate without bipolar violations.

The Fa and N bits can also be used to identify a multiframe structure (when this is done, the 14 bit criterion may not be met). This multiframe structure will make provisions for a low speed signalling channel to be used in the TE to NT direction (Q-channel). It will consist of a five frame multiframe which can be identified by the binary inversion of the Fa and N-bit on the first frame and consequently on every fifth f rame of the multifra me. Upon detection of the multiframe signal, the TE will replace the next Fa-bit to be transmitted with the Q-bit.

The DC balancing bits (L) are used to remove any DC content from the line. The balancing bit will be a mark if the number of preceding marks up to the previous balancing bit is odd. If the number of marks is even, the L-bit will be a space.

The A-bit is used by the NT during line activation procedures ( refer to stat e activa tion di agrams). The state of the A-bit will advise the TE if the NT has achieved syn c hr o ni zation.

The E-bit is the D-echo channel. The NT will reflect the binary value of the received D-channel into the E-bits. This is used to establish the access contention resolution in a point-to-multipoint configuration. This is described in more detail in the section of th e D- c h an ne l p rio r i ty m e chanism.

The M-bit is a second level of multiframing which is used for structuring the Q-bits. The frame with Mbit=1 identifies frame #1 in the twenty frame multiframe. The Q-channel is then received as shown in Table 1. All synchronization with the multiframes must be performed externally.

FRAME # Q-Bit M-Bit

1Q11

6Q20

11 Q3 0

16 Q4 0

Table 1. Q-channel Allocation

Bit Order

When using the B-channels for PCM v oice, the first bit to be transmitted on the S-Bus should be the sign bit. This complies with the existing telecom standards which transmit PCM voice as most significant bit first. However, if the B-channels are to

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Preliminary Information MT8930C

carry data, the bit ordering must be reversed to comply with the existing datacom standards (i.e., least signifi c an t bit fi rs t).

These contradicting standards place a restriction on all information input and output through the serial and parallel ports. Information transferred through the serial ports, will maintain the integrity of the bit order. Data sent to either serial port from the parallel port, will transmit the least significant bit first. Therefore, a PCM byte input through the microprocessor port must be reordered to have the sign bit as th e le a st s i gn i fic an t bi t.

When the microprocessor reads D, B1 or B2 channel data of eithe r ST-BUS or S-bus seria l port, the le ast significant bit read is the first bit received on that particular c h an ne l of either seri al p ort.

The D-channel received on the serial ST-BUS ports must be ordered with the least significant bit first as shown in Figure 4. This also applies to the D-channel directed to the ST-BUS from the microproces sor po rt.

The C-channel bit mapping from the parallel port to the ST-BUS is organized such that the most significant bit is transmitted or received first.

State Activation

The state activation controller activates or deactivates the SNIC in response to line activity or external command. The controller is completely hardware driven and need not be initialized by the microprocessor. The state diagram for initialization is shown in Figure 7.

The protocol used b y the state activati on co nt r oll er i s defined as follows:

1) In the deactivated state, neither the NT nor TE assert a signal on the line (Info0).

2) If the TE wants to initiate activation, it m ust begin transmitting a continuous signal consisting o f a po siti ve ze ro, a n ega tiv e ze ro followed by six ones (Info1).

3) Once the NT has detected Info1, it begins to transmit Info2 which consists of an S-Bus frame with zeros in the B and D-channel and the activation bi t (A -bit) s et to z e ro.

4) As soon as the TE synchronizes to Info2, it responds with a valid S-Bus frame with data in the B1, B2 and D-ch anne l (Info 3).

5) The NT will then transmit a valid frame with data in the B1, B2 and D-channel. It will also

set the activation bit (A) to binary one once synchronizatio n to Info 3 is ach ieve d.

If the NT wishes to ini ti a te the acti v at ion , st ep s 2 an d 3 are ignored and the NT starts sending Info2. To initiate a deactivation, either end begins to send Info0 (Idle line).

D-channel Priority Mechanism

The SNIC contains a hardware priority mechanism for D-channel contention resolution. All TEs connected in a point-to-multipoint configuration are allocated the D-channel using a systematic approach. Allocation of the D-channel is accomplished by monitoring the D-echo channel (E-bit) and incrementing the D-channel priority counter with every consecutive on e echoed back in the E bit. Any zero found on the D-echo channel will reset the prio rity co un te r.

There are two classes of priority within the SNIC, one user accessible and the other being strictly internal. The user accessible priority selects the class of operation and has precedence over the internal priority. The latter (internal priority), will select the level of priority within each class (i.e., the internal priority is a subsection of the user accessi ble priority). User accessible priorit y se lects th e t ermi nal count as 8/9 or 10/11 consecutive ones on the E-bit (8 being high priority while 10 being low priority). The internal priority selects the terminal between 8 or 9 for high class and 10 or 11 for low class. The first terminal equipment to attain the E-bit priority count will immediately take control of the D-channel by sending the opening flag. If more than one terminal has the same prio r it y, all but one of them will eventually detect a collision. The TEs that detect a collision will immediately stop trans-mitting on the Dchannel, ge nerate an int errupt throug h the Dcoll bit , reset the DCack bit on the next frame pulse, and restart the counting process. The remainder of the packet in the Tx FIFO is ignored.

After successfully completing a transmission, the internal priority level is reduced from high to low. The internal priority will only be increased once the terminal co unt for the respec tive level of priority has been achieved (e.g., if TE has high priority internally and externally, it must count 8 consecutive ones in the D-echo channel. Once this is achieved and successful transmission has been completed, the internal priority is reduced to a lower level (i.e., count = 9). This terminal will not return to the high internal priority until 9 consecutive ones have been monitored o n th e D-e c ho ch an ne l ) .

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MT8930C Preliminary Informatio n

(2)

Signals from NT to TE Signals from TE to NT

Info0

Info2

Info4

No Signal

Valid frame structure with all B, D, D-echo and A bits set to ‘0’

Valid frame with data in B, D, D-echo channels. Bit A is set to 1.

TE State Activation Diagram

DR = 1

Info0 No Signal

Info1 Continuous Signal of +‘0’, -‘0’

Info3 V a lid frame with data in B & D

AR = 1

and six ‘1’s

Bits

Activation Request

send Info1 if BA = 0 send Info0 if BA = 1

Where: BA

(1)

Note 1: signal is not timebase locked to NT. Note 2: Sync/BA bit of the Status Register

Sync = 1

= Bus Activity

DR = Deactivation Request AR = Activation Request

(2)

= Frame Sync Signal

Sync A = Activation bit

Time out = 32 ms Timer Signal

is configured as Sync bit when AR = 1 and DR = 0, or as BA bit when AR = 0 or DR = 1. A change in the state of the AR and/or DR bits will cause a change in the function of the Sync/BA bit in the following ST-BUS frame.

BA = 0

Deactivated

send Info0

NT State Activation Diagram

Pending

Activation

send Info2

DR = 1

BA = 0

BA = 1

AR = 1

Sync = 1

Sync = 0

Sync = 1

Activated

send Info3

Deactivated

send Info0

DR = 1

AR = 1

Activated

send Info4

Figure 7 - Link Activatio n Protocol, State Di agram

Line Wiring Configuratio n

The MT8930C can interface to any of the three wiring configurations which are specified by CCITT Recommendation I.430 and ANSI T1.605 (refer to Figs. 8 to 1 0). These co nsist of a point -to-point or one of the two point-to-multipoint configurations (i.e., short passive bus or the extended passive bus). The selection of line configurations is performed using the timing bit (B4 of NT Mode Control Register).

For the short passive bus, TE devices are connected at random points along the cable. However, for the extended passive bus all connection points are grouped at the far end of the cable from the NT.

Synchronized

send Info3 if Sync = 1

DR = 1

A = 1 &

Sync = 1

BA =0

send Info0 if Sync = 0

Sync = 0

A = 0

Time out

Pending

Deactivation

Send Info0

DR = 1

For an NT SNIC in fixed timing mode, the VCO and Rx filters/peak detectors are disabled and the threshold vo ltage is fixed. Howev er, for a TE SNIC or an NT SNIC (i n adaptive timing mode), the VCO and Rx filters/peak detectors are enabled. In this manner, the device can compensate for variable round trip delays and line attenuation using a threshold voltage set to a fixed percentage of the pulse peak amplitude.

Another operation can be implemented using the SNIC in the star configuration as shown in Figure 14. This mode allows multiple NTs, with physically independent S-Busses, to share a common input source and transfer information down the S-Bus to

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Preliminary Information MT8930C

0 - 1 Km

NT is operating in adaptive timing TR is the line termination resistor = 100 Ω

T R

Figure 8 - Point-to-Point Conf igurati on

NT is operating in fixed timing TR is the line termination resistor = 100 Ω

T R

Fiure 9 - Short Passive Bus Configuratio n, up to 8 TEs can be support ed

T R

0 - 10 m

100 m for 75 Ω impedance cable and 200 m for 150 Ω impedance cable

100 - 200 m

0 - 10 m

TE TE TE TE TE TE TE

0-500 m

0-50 m

T R

TE TE TE TE TE TE TE

NT is operating in adaptive timing TR is the line termination resistor = 100 Ω

Figure 10 - Extended Passive Bus Configuration, up to 8 TEs can be supported

all TEs . All NT devices connected into the star will receive the i nformation transmi tted by all TEs on al l branches of the sta r, exactly as if th ey were on the same physical S-Bus. All NTs in the star configuration mu st be ope rat ing in fi xed timing mode. Refer to the description of the star configuration in the ST-BUS section.

The SNIC has on e last mode of operati on called th e NT slave mode. T his has th e effect of op erati ng th e SNIC in network termination mode (CK/NT pin = 1) but having the frame structure and registers description defined by the TE mode. This can be used where multiple subscriber loops must carry a fixed phase relation between each line. A typical situation is when the system is trying to synchronize two nodes of a synchronous network. This allows multiple TEs to share a common ST-BUS timebase. The synchronization of the loops is established by using the clock signals produced by a local TE as an input timing source to the NT slave.

Adaptive Timing Operation

On power-up or after a r ese t, t he SNIC in N T mo de is set to operate in fixed timing. To switch to adaptive timing, th e use r s h ou ld :

1) set the DR b it to 1

2) set the Timing bit to 1 in the C-channel Control Register

3) wait for 100 ms period

4) proceed in using the AR and DR bits as desired

Switching from adaptive timing mode is completed by resetting the Timing bit.

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MT8930C Preliminary Informatio n

125 µs

Channel0Channel1Channel

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

•••

Figure 11 - ST-BUS Stream Forma t

F0b

C4b

ST-BUS BIT CELLS

Channel 31

Bit 0

Channel 0

Bit 7

Figure 12 - Clock & Frame Alignme nt for ST-BUS Streams

ST-BUS Interface

The ST-BUS is a synchronous time division multiplexed serial bussing scheme with data streams operating at 2048 kbit/s configured as 32, 64 kbit/s channels (refer to Fig. 11). Synchronization of the data transfer is provided from a frame pulse which identifies the frame boundaries and repeats at an 8 kHz rate. Figure 4 shows how the frame pulse

) defines the ST-BUS frame boundaries. All

(F0b data is clocke d into the d evice on t he rising edge of the 4096 kHz clock (C4b into the bit cell, while data is clocked out on the falling edge of the 4096 kHz clock at the start of the bit cell.

All timing signals (i.e. F0b bidirectional (denoted by the terminating b). The I/O configuration of these pins is controlled by the mode of opera tion (NT or TE). In the NT mode, all synchronized signals are supplied from an external source and the SNIC uses this timing while transferring information to and from the S or ST-BUS. In the TE mode, an on-board analog phase-locked loop extracts timing from the received data on the S-Bus and generates the system 4096 kHz ( C4b

) and frame pulse (F0b). The analog phase-locked loop also maintains proper phase relatio n between the ti ming signal s as well as filtering out jitter which may be present on the received line port.

) three quarters of the way

& C4b) are identified as

(8/2048) ms

Channel 0

Bit 6

Channel30Channel31Channel

Channel 0

Bit 5

Channel 0

Bit 4

When the TE mode is selected by tying the CK/NT pin low, a continuous INFO0 signal on the receiver will cause the PLL freq uency to drift from it s nomin al

4.096 MHz v alue (C4b

output). Hence, transmitted INFO1 from the TE will not be at 192 kbps as required in I. 430 an d T1.605. Howev er, if the user ’s application requires the transmission of INFO1 at exactly 192 kbit/s or the presence of an exact 4.096 MHz C4b

clock at all times , then a 4.096 MHz clock

should be connect ed to th e CK/N T pin.

This input clock serve s to co nfigu re th e devic e in TE mode and to train the PLL in the absence of an INFO2 or INFO4 signal on the line.

The SNIC uses the first four channels on the ST-BUS (as shown in Figure 4). To simplify the distribution of the serial stream, the SNIC provi des a delay ed fr ame pu lse (F0od

) to eliminate the need for a channel assignment circuit. This signal is used to drive subsequent devices in the daisy chain (refer Figure 13). In this type of arrangement, only the first SNIC in the chain will receive the system frame pulse (F0b

) with the following devices rece ivi ng i ts p rede ces sor’s del aye d output fram e pu lse (F0od

The SNIC makes efficient use of its TDM bus through the Star configuration. It does so by sharing four common ST-BUS channels to multiple NT devices.

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Preliminary Information MT8930C

ST-BUS Clock

ST-BUS Stream

System

Frame Pulse

System

Frame Pulse

Input

ST-BUS Stream

Active on

Channel 0 - 3

MT8930C

F0b

F0od

to TE to TE to TE to TE

MT8930C

F0b

Figure 13 - Daisy Chaining the SNIC

MT8930C

to TE

STAR

F0b

DSTi

MT8930C

STAR

F0b

DSTi

Active on

Channels 4 - 7

F0od

MT8930C

F0b

MT8930C

STAR F0b DSTi

DSTo

MT8930C

STAR F0b DSTi

Active on

Channels 8 - 11

F0od

Active on

Channels 12 - 15

MT8930C

F0b

F0od

to TE

Output

ST-BUS Stream

to TE

Figure 14 - NT in Star Config uration

Up to eight SNICs in NT mode with physically independent S-Busses can be connected in parallel to realize a star configuration, as shown in Figure 14. All devices connected into the star will carry the same input, thus information is sent to all TEs simultaneously. The 2B+D data received from every TE is transmitted to all NTs through the STAR pin. Consequently, all the DSTo streams will carry identical 2B+D data reflecting what is being transmitted by th e va r iou s T E s.

The flow of da ta in the d irection o f S-Bus to ST-BUS is transparent to the SNIC, regardless of the state machine status. On the other hand, the flow of data in the direction of ST-BUS to S-Bus becomes transparent only after the state machine is in the active state (IS0, IS1 =1, 1), in case of an NT, or in the synchroniza ti on s t at e ( IS 0, I S1 = 1), i n c as e o f a T E.

Microprocessor/Control Interface

The parallel port on the SNIC operates as either a general purpose microprocessor interface or as a hardwired control port.

In microprocessor control mode (Cmode = 1), the parallel port is compatible with either Motorola or

Intel multiplexed bus signals and timing. The MOTEL circuit (MOtorola and InTEL Compatible bu s ) us e s the le v el of the DS /RD

pin at the rising edge of AS/ALE to select the appropriate bus timing. If DS/RD

is low at the rising edge of AS/ALE (refer Fig. 26) then Motorola bus timing is selected. Conversely, if DS/RD

high at the rising edge of AS/ALE (refer Figs. 24 &

25), then Intel bus timing is selected. This has the effect of redefining the microprocessor port transparen tly to th e use r.

In this mode, the user has the option of writing to the C-channel Control or Diagnostic Register through the parallel port interface or through the C-channel on DSTi. Bit 0 of the Master Control Register provides this opti on.

The parallel port on the SNIC allows complete control of the HDLC transceiver and access to all data, control and status registers. The internal registers (defined in Table 2) can be accessed through the microprocessor port only when the Cmode pin is held high. Reading these registers allows the microprocessor to monitor incoming data on the S or ST-BUS without interrupting the normal data flow.

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MT8930C Preliminary Informatio n

Address Lines

A4 A3 A2 A1 A0

0 0 0 0 0 Master Control Register verify

A 0 0 0 0 1 ST-BUS Control Register verify S 0 0 0 1 0 HDLC Control Register 1 verify Y 0 0 0 1 1 HDLC Control Register 2 HDLC Status Register N 0 0 1 0 0 HDLC Interrupt Mask Register HDLC Interrupt Status Register C 0 0 1 0 1 HDLC Tx FIFO HDLC Rx FIFO

0 0 1 1 0 HDLC Address Byte #1 Register verify 0 0 1 1 1 HDLC Address Byte #2 Register verify 0 1 0 0 0 C-channel Control Register 0 1 0 0 1 C-channel Status Register 1 0 0 0 0 Control Register 1 Not available 1 0 0 1 0 Not Available Master Status Register 0 1 0 0 0 DSTi C-channel 01001 DSTo C-channel

S0 1 0 1 0 S-Bus Tx D-channel DSTi D-channel Y 0 1 0 1 1 DSTo D-channel S-Bus Rx D-channel N 0 1 1 0 0 S-Bus Tx B1-channel DSTi B1-channel C 0 1 1 0 1 DSTo B1-channel S-Bus Rx B1-channel

0 1 1 1 0 S-Bus Tx B2-channel DSTi B2-channel 0 1 1 1 1 DSTo B2-channel S-Bus Rx B2-channel

Table 2. SNIC Address Map

Write Read

Some registers are classified as asynchronous and others as synchronous. Synchronous registers are single-buffered and require synchronous access. Not all the synchronous registers have the same access times, but all can be accessed synchronously in the time during which the NDA (refer to Fig. 5). Therefore, it is recommended that the user make use of the NDA registers. Since the synchronous registers use common circuitry, it is essential that the register be read before being written. This sequence is important as a write cycle will overwrite the last data received. These parallel accesses must be refreshed every frame. Asynchronous registers, on the other hand, can be accessed at any time.

When the Cmode pin is low, controllerless mode is selected and the parallel port reverts to hardwired control/status pins. This allows the MT8930C to function without the need for a controlling microprocessor. In the controllerless mode, the parallel bus has direct connection to the relevant control/status registers (refer to Pin Description). Discrete logic can be used to drive/sense the respective pins. In this mode, pin 11

determines whether the microport pins or

(P/SC the C-channel bits on DSTi stream are the control source of the device. If the C-channel is selected to be the source, P/SC microport pins are ignored and the C-channel is loaded into th e C - cha nn el C on tr o l Re gi s t er.

signal to access these

is tied low, then the

signal is low

The data in TE or NT Mode Status Register, depending upon the mode selected, is always sent out on the C-channel of DSTo. However, in microproces sor control mo de the user can overwrite this data by writing to the DSTo C-channel Register. This access can be done anytime outside the frame pulse interv al of the ST-BUS frame. Data writt en in the current S T-BUS frame wil l only appear in t he Cchannel of the following frame.

The least significant bit (B0) of the C-channel Register, selects between the control register or the diagnostic register. Setting the B0 of the C-channel Register to ’0’ allow access to the control register. Setting the LSB of t he C-ch an ne l Re gist e r to ’ 1’ a llo w access to the d iagnostic reg ister. The interpretati on of each register is defined in Tables 13 and 14 for NT mode or Tables 16 and 17 for the TE mode.

It is important to note that in TE mode, the C-channel Diagnostic Register should be cleared while the device is not in the active state (IS0, IS1 is accomplished by setting the ClrDia bit of the Cchannel Control Register to 1 until the device is activated. In serial control mode, the C-channel on the ST-BUS is loaded into the C-channel Control Register in every ST-BUS frame; the user should make sure that a 1 is written to the ClrDia bit in every frame. However, in parallel control mode the user needs to set the ClrDia bit only once to keep the

≠ 1,1). This

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Preliminary Information MT8930C

Diagnostic Regi ster cleared. Once full activati on is achieved the Diagnostic Register can be written to in order to enable the various test functions.

HDLC Transceiver

The HDLC Transceiver handles the bit oriented protocol structure and formats the D-channel as per level 2 of the X.25 packet switching protocol defined by CCITT. It transmits and receives the packetized data (information or control) serially in a format shown in Figure 15, while providing data transparency by zero insertion and deletion. It generates and de tec ts the flag s, var iou s link ch anne l states and the abort sequence. Further, it provides a cyclic redundancy check on the data packets using the CCITT defined polynomial. In addition, it can recognize a single byte, dual byte or an all call address in the received frame. There is also a provision to disable the protocol functions and provide transparent access to either serial port through the microprocessor port. Other features provided by the HDLC include, independent port selection for transmit and received data (e.g. transmit on S-Bus and receive from ST-BUS), selectable 16 or 64 kbit/s D-channel as well as an HDLC loopback fro m t he tra ns mi t to th e re cei ve po rt. These features are enabled through the HDLC control registers (see Tables 6 and 7).

HDLC Frame Format

All frames start with an opening flag and end with a closing flag as shown in Figure 1 5. Between these two flags, a frame contains the data and the frame check sequence (FCS).

ii) Data

The data field refers to the Address, Control and Information fields defined in the CCITT recommendations. A valid frame should have a data field of at least 16 bits. The first and second byte in the data field is the address of the frame.

iii) Frame Check Sequence (FCS)

The 16 bits following the data field are the frame check seque nce bit s. The ge ne rator pol ynomi al is :

G(x)=x

16+x12+x5

The transmitter calculates the FCS on all bits of the data field and transmits the complement of the FCS with most significant bit first. The receiver performs a similar computation on all bits of the received data but also includes the FCS field. The generating polynomial will assure that if the integrity of of the transmitted data was maintained, the remainder will have a consistent pattern and this can be used to identify, with high probability, any bit errors occurred during transmission. The error status of the received packet is ind icated by B7 and B6 bits in the HDLC Status Reg i st er.

iv) Zero Insertion and Dele tion

The transmitter, while sending either data from the FIFO or the 16 bits FCS, checks the transmission on a bit-by-bit basis and inserts a ZERO after every sequence of fiv e cont ig uous ONEs (includ i ng the la s t five bits of FCS) to ensure that the flag sequence is not imitated. Similarly the receiver examines the incoming frame content and discards any ZERO directly foll owi ng the five co ntig uous ONE s.

FLAG D ATA FIELD FCS FLAG

One

Byte

n Bytes

(n ≥ 2)

Two

Bytes

One

Byte

Figure 15 - Frame Format

i) Flag

The flag is a unique pattern of 8 bits (01111110) defining the frame boundary. The transmit section generates the fl ags and ap pends them automa tically to the frame to be transmitted. Th e receive section searches the incoming packets for flags on a bit-by-bit basis and establishes frame synchronization. The flags are used only to identify and synchronize the received frame and are not transferred to the FIFO.

v) Abort

The transmitter aborts a frame by sending a zero followed by seven consecutive ONEs. The FA bit in the HDLC Control Re gist er 2 alo ng with a write to the HDLC Transmit FIFO enables the transmission of an abort sequence instead of the byte written to the register (to ha ve a vali d abort there mus t be at leas t two bytes in the packet). On the receive side, a frame abort is defined as s even or more con tiguous ONEs occurring after the start flag and before the end flag of a packet. An interrupt can be generated on reception of the abort sequence using FA bit in the HDLC Interrupt Mask/Vector Registers (refer to Tables 9 and 10).

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MT8930C Preliminary Informatio n

Interframe Time Fill

When the HDLC Tranceiver is not sending packets, the transmitter ca n be i n one of two states mentioned below depending on the status of the IFTF bit in the HDLC Control Register 1.

i) Idle State

The Idle state is defined as 15 or more contiguous ONEs. When the HDLC Protocoller is observing this condition on th e receiv ing chan nel, the Id le bit in the HDLC Status Registe r is set HIGH. On the transmi t side, the Protocoller ends the transmission of all ones (idle state) when data is loaded into the transmit FIFO.

CCITT I.430 Specification requires every TE that does not have layer 2 frames to transmit, to send binary ONEs on the D-channel. In this manner, other TEs on the line will have the opportunity to access the D-channel using the priority mechanism circuitry.

ii) Flag Fill State

The HDLC Protocoller transmits continuous flags (7E state when data is loaded into the transmit FIFO. The reception of the interframe time fill will have the effect of setting the idle bit in the HDLC Status Register is set to ’0’.

HDLC Transmitter

On power up, the HDLC transmitter is disabled and in the idle state. The transmitter is enabled by setting the TxEN bit in the HDLC Control Register 1. To start a packet, the data is written into the 19 byte Transmit FIFO starting with the address field. All the data must be written to the FIFO in a bytewide manner. When the data is detected in the transmit FIFO, the HDLC protocoller will pro cee d in one of the following ways:

1) If the transmitter is in idle state, the pre sent byte

2) If the transmitter is in the flag fill state, the

) in Interframe Time Fill state and ends this

Hex

of ones is completely transmitted before sending the opening flag. The data in the transmit FIFO is then transmitted. A TE transmitting on the Dchannel will use the contention circuitry described previously in

Mechanism

flag presently being transmitted is used as the opening flag for the packet stored in the transmit FIFO.

to access this channel.

D-channel Priority

3) If the HDLC transmitter is in transparent data mode, the protocol functions are disabled and the data in the transmit FIFO is transmitted without a framing structure.

To indicat e that the part icular byte is the last byte of the packet, the EOP bit i n th e HD LC Con tr o l Re gister 2 must be set befo re the last byte is written into th e transmit FIFO. The EOP bit is cleared automatically when the data byte is written to the FIFO. A fter the transmission of the l ast by te in the pa cket , the fr ame check sequence (16 bits) is sent followed by a closing flag . If th ere is any mor e da ta in the t ran smit FIFO, it is immediately sent after the closing flag. That is, the closing flag of a packet is also used as the opening flag the the next packet.

However, CCITT I.430 and ANSI T1.605 Recommendations state that after the successful transmission of a packet, a TE must lower its priority level within the specified priority class. The user can meet this require me nt by lo ad in g t he Tx FI FO wi th no more than one packet and then waiting for the DCack bit to go to zero, o r for an HDLC interrupt b y the TEOP bit in the HDLC I nterrupt Stat us Register, before attemp ting to load a new packet. If there i s no more data to be transmitted, the transmitter assumes the selected link channel state.

During the transmission of either the data or the frame check sequence, the Protocol Controller checks the transmitted information on a bit by bit basis to insert a ZERO after every sequence of five consecutive ONEs. This is required to eliminate the possibility of imitating the opening or closing flag, the idle code or an abort sequence.

i) Transmit Underr un

A transmit underrun occurs when the last byte loaded into the transmit FIFO was not ‘flagged’ with the ‘end of pack et’ (EOP) bit and t here are no more bytes in the FIFO. In such a situation, the Protocol Controller transmits the abort sequence (zero and seven ones) and moves to the selected link channel state.

Conversely, in the event that the tra nsm it FI F O is ful l, any further writes will overwrite the last byte in the Transmit FIFO.

ii) Abort Transmission

If it is desired to abort the packet currently being loaded into th e transmit FIFO, the next byte written to the FIFO should be ‘flagged’ to cause this to happen. The FA bit of the HDLC Control Register 2

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Preliminary Information MT8930C

must be set HIGH, before writing the next byte into the FIFO. Thi s bit is clea red automati cally once th e byte is written to the Transmit FIFO. When the ‘flagged’ byte reaches the bottom of the FIFO, a frame abort sequence is sent instead of the byte and the transmitter operation returns to normal. The frame abort sequence is ignored if the packet has less then two bytes.

iii) Transparent Data Transfer

The Trans bit (B4) in the HDLC Con trol Register 2 can be set to provide transparent data transfer by disabling the protocol functions. The transmitter no longer generates the Flag, Abort and Idle sequences nor does it in s ert the zeros a n d ca lc ul at e th e F CS .

It should be noted that none of the protocol related status or interr upt bits are applicable in tran sparent data transfer state. However, the FIFO related status and inte rrupt bits are pertinent an d carry the same meaning as they do while performing the protocol functions.

HDLC Receiver

After a reset on power up, the receive section is disabled. Address detection is also disabled when a reset occurs. If address detection is required, the Receiver Address Registers are loaded with the desired address and the ADRec bit in the HDLC Control Register 1 is set HIGH. The receive section can then be enabled by RxEN bit in this same Control Regist er 1. All HDLC int erru pts ar e m aske d, thus the desired interrupt signal must be unmasked through the HDLC Inter ru pt Ma sk Re gist er. All active interrupts are cleared by reading the HDLC Interrupt Status Registe r.

i) Normal P ack ets

After initialization as explained above, the serial data starts to be clocked in and the receiver checks for the idle channel and flags. If an idle channel is detected, the ‘Idle’ bit in the HDLC Status Register is set HIGH. Once a flag is detected, the receiver synchronizes itself in a bytewide manner to the incoming data stream. The receiver keeps resynchronizing to the flags until an incoming packet appears. The incoming packet is examined on a bit-by-bit basis, inserted zeros are deleted, the FCS is calculated and the data bytes are written into the 19 byte Rece ive FI FO. How ever, the FCS an d othe r control characters, i.e., flag and abort , are never stored in th e Re cei ve F IFO. If the add res s det ect ion is enabled, the address field following the flag is compared to the bytes in the Receive Address

Registers. If one byte address recognition is enabled, the address field is one byte long and it is compared with the six most significant bits in address recognition register 1. If two byte address recognition is enabled, the address field is two bytes long and is compared with the address recognition registers 1 and 2. The address byte can also be recognized if it is an all call address (i.e., seven most significant bits are 1). If a match is not found, the entire packet is ignored, nothing is written to the Receive FIFO and the receiver waits for the next packet. If the active addre s s byte is vali d, the packe t is received in normal fashion.

All the bytes written to the receive FIFO are flagged with two status bits. The status bits are found in the HDLC status register and indicate whether the byte to be read from the FIFO is the first byte of the packet, the middle of the packet, the last byte of the packet with good FCS or t he last byte of the packet with bad FCS. This status indication is valid for the byte which is to be read fro m the Rece ive FIFO.

The incoming data is always written to the FIFO in a bytewide manner. However, in the event of data sent not being a multiple of eight bits, the software associated with the receiver should be able to pick the data bits fro m the LSB positions of the last byte in the received data written to the FIFO. The Protocoller does not provide any ind i cation as to how many bits this might be.

ii) Invalid Packets

In TE mode, if there are less than 25 data bits between the opening and closing flags, the packet is considered invalid and the data never enters the receive FIFO (inserted zeros do not form part of the valid bit count). This is true even with data and the abort sequence, the total of which is less than 25 bits. The data packets that are at least 25 bits but less than 32 bits long are also invalid, but not ignored. They are clocked into the receive FIFO and tagged as having bad FCS.

In NT mode, however, all the data packets that are less than 32 bits long are considered invalid. They are clocked into the receive FIFO with “Bad FCS” status.

iii) Frame Abort

When a frame abort is received, the EOPD and FA bits in the HDLC Interrupt Status Register are set. The last byte o f the aborted packet is written to the FIFO with a status of “Packet Byte”. If there is more than one packet in the FIFO, the aborted packet is

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MT8930C Preliminary Informatio n

distinguished by the fact that it has no “Last Byte” status on any of i ts by te s .

iv) Idle Channel

While receiving the idle channel, the idle bit in the HDLC status register remains set.

v) Tran sparent Data Transfer

By setting the Trans bit in the HDLC Control Register 2 to select the transparent data transfer, the receive section will disable the protocol functions like Flag/ Abort/Idle detection, zero deletion, CRC calculation and address comparison. The received data is shifted in from the active port and written to receive FIFO in bytewide format.

It should be noted that none of the protocol related status or interr upt bits are applicable in tran sparent data transfer state. However, the FIFO related

status and in terrupt bits are pertinent an d carry the same meaning as they do while performing the protocol functions.

vi) Receive Overflow

Receive overflow occurs when the receive section attempts to load a byte to an already full receive FIFO. All attempts to write to the full FIFO will be ignored until the receive FIFO is read. When overflow occurs, the rest of the present packet is ignored as the receiver will be disabled until the reception of the next opening flag.

BIT NAME DESCRIPTION

B7 NA A ‘1’ will allow access to Control Register 1 and Master Status Register.

A ‘0’ will prevent it.

B6-B3 NA

B2 IRQ

(1)

Keep at ’0’ for normal operation.

/NDA The state of this pin will select the mode of the IRQ/NDA pin.

A ’0’ will enable the IRQ

pin for HDLC interrupts.

A ’1’ will enable the New Data Available signal which identifies the access time to the

is enabled, the HDLC interrupts are disabled.)

(2)

or S bit as selected in the NT Mode C-channel

B1 M

synchronous registers. (If NDA

/Sen A ’0’ will enable the transmission of the M

Register (refer to Table 13). The selection of M or S is determined by the HALF signal (refer to functional timing). A ’1’ will disable this feature forcing the M and S bits to binary zero.

B0 P/SC

The Parallel/Serial Control bit selects the source of the control channel. If ’0’, then the Cchannel Register is access through the ST-BUS stream. If ’1’, then the C-channel Register is accessed through the microprocessor port.

Table 3. Master Control Register (Read/Write Add. 00000

Note 1: These bits have no designated memory space and will read as the last v alues written to the microprocesso r port. Note 2: The transmission of M=1 is used for a second level of multiframing.

)

BIT NAME DESCRIPTION

B7 NA Keep at ‘0’ for normal operation. B6 RxDIS When set to ‘1’, this bit disables the S-Bus signal receiver. It can be used, for example, to

force INFO4 to INFO2 transition in the NT state machine while receiving INFO3 from the TE.

B5-B0 NA Keep at ‘0’ for normal operation.

Table 4. Control Register 1 (Write Add. 10000

9-52

)

Page 19

Preliminary Information MT8930C

BIT NAME DESCRIPTION

B7 CH3i

B6 CH2i

B5 CH1i

B4 CH0i

B3 CH3o

B2 CH2o

B1 CH1o

B0 CH0o

Note 3: All ST-BUS channels are enabled in controllerless mode.

(3)

If ’1’, then the ST-BUS channel 3 input port is enabled (B2-channel). If ’0’, then the channel is disabled, and will read FF

(3)

If ’1’, then the ST-BUS channel 2 input port is enabled (B1-channel). If ’0’, then the channel is disabled, and will read FF

(3)

If ’1’, then the ST-BUS channel 1 input port is enabled (C-channel). If ’0’, then the channel is disabled, and will read 00

(3)

If ’1’, then the ST-BUS channel 0 input port is enabled (D-channel). If ’0’, then the channel is disabled, and will read FF

(3)

If ’1’, then the ST-BUS channel 3 output port is enabled (B2-channel).

If ’0’, then the channel is disabled and it will be placed in High impedance.

(3)

If ’1’, then the ST-BUS channel 2 output port is enabled (B1-channel). If ’0’, then the channel is disabled and it will be placed in High impedance.

(3)

If ’1’, then the ST-BUS channel 1 output port is enabled (C-channel). If ’0’, then the channel is disabled and it will be placed in High impedance

(3)

If ’1’, then the ST-BUS channel 0 output port is enabled (D-channel). If ’0’, then the channel is disabled and it will be placed in High impedance.

Table 5. ST-BUS Control Register (Read/Write Add. 00001

)

BIT NAME DESCRIPTION

B7 TxEn A ’1’ enables the HDLC transmitter for the selected D-channel (i.e., ST-BUS or S-Bus).

A ’0’ disables the HDLC transmitter (i.e., an all 1s signal will be sent).

B6 RxEn A ’1’ enables the HDLC receiver for the selected D-channel (i.e., ST-BUS or S-Bus).

A ’0’ disables the HDLC receiver (i.e., an all 1s signal will be received).

B5 ADRec If ’1’, then the address recognition is enabled. This forces the receiver to recognize only

those packets having the unique address as programmed in the Receive Address Registers or if the address byte is the All-Call address (all 1s). If ’0’, then the address recognition is disabled and every valid packet is stored in the received FIFO.

B4 TxPrtSel This bit selects the port of the HDLC transmitted D-channel.

A’1’ selects the S-Bus port. A ’0’ selects the ST-BUS port.

B3 RxPrtSel This bit selects the port of the HDLC received D-channel.

A ’1’ selects the S-Bus port. A ’0’ selects the ST-BUS port.

B2 IFTF This bit selects the Inter Frame Time Fill.

A ’1’ selects continuous flags. A ’0’ selects an all 1’s idle state. B1 NA Keep at ’0’ for normal operation. B0 HLoop A ’1’ will activate the HDLC loopback where the transmitted D-channel is looped back to

the received D-channel

(1)

. In NT mode, the transmission of the packet is not affected. In TE Mode, however, the DReq bit of C-channel Control Register must be set to ‘1’ for the packet to be transmitted to the S-Bus. A ’0’ disables the loopback.

Table 6. HDLC Control Register 1 (Read/Write Add. 00010

Note 1: The HDLC receiver must be enabled as well as the designated channel.

)

9-53

Page 20

MT8930C Preliminary Informatio n

BIT NAME DESCRIPTION

B7-B5 NA Keep at ’0’ for normal operation.

B4 Trans A ’1’ will place the HDLC in a transparent mode. This will perform the serial to parallel or

parallel to serial conversion without inserting or deleting the opening and closing flags, CRC bytes or zero insertion. The source or destination of the data is determined by the port selection bits in the HDLC Control Register 1.

B3 RxRst A transition from ‘0’ to ’1’ will reset the receive FIFO. This causes the receiver to be

disabled until the reception of the next flag. (The status Register will identify the RxFIFO as being empty). The device resets this bit to ‘0’ immediately after clearing the receive FIFO.

B2 TxRst A transition from ‘0’ to ’1’ will reset the transmit FIFO. This causes the transmitter to

clear all data in the TxFIFO. The device resets this bit to ‘0’ immediately after clearing the transmit FIFO.

B1 FA

B0 EOP

(2)

A ’1’ will ’tag’ the next byte written to the transmit FIFO and cause an abort sequence to be transmitted once it reaches the bottom of the FIFO.

A ’1’ will ’tag’ the next byte written to the transmit FIFO and cause an end of packet sequence to be transmitted once it reaches the bottom of the FIFO.

Table 7. HDLC Control Register 2 (Write Add. 00011

Note 2: These bits will be reset after a write to the TxFIFO

BIT NAME DESCRIPTION

B7-B6 RxByte

Status

These two bits indicate the status of the received byte which is ready to be read from the 19 deep received FIFO. The status is encoded as follows:

B7 -B6 0 - 0 - Packet Byte 0 - 1 - First Byte 1 - 0 - Last Byte (Good FCS) 1 - 1 - Last Byte (Bad FCS)

B5-B4 RxFIFO

Status

These two bits indicate the status of the 19 deep receive FIFO. This status is encoded as follows:

B5 - B4 0 - 0 - Rx FIFO Empty 0 - 0 - ≤14 Bytes 1 - 0 - Rx FIFO Overflow 1 - 1 - ≥15 Bytes

)

B3-B2 TxFIFO

Status

These two bits indicate the status of the 19 deep transmit FIFO as follows:

B3 - B2 0 - 0 - Tx FIFO Full 0 - 1 - ≥5 Bytes 1 - 0 - Tx FIFO Empty

1 - 1 - ≤ Bytes B1 Idle If ’1’, an idle channel state has been detected. B0 Int If ’1’ an unmasked asynchronous interrupt has been detected.

Table 8. HDLC Status Register (Read Add. 00011

9-54

)

Page 21

Preliminary Information MT8930C

BIT NAME DESCRIPTION

B7 EnDcoll A ’1’ will enable the D-channel collision interrupt.

A ’0’ will disable it. This bit is available only in TE mode.

B6 EnEOPD A ’1’ will enable the received End of Packet interrupt.

A ’0’ will disable it.

B5 EnTEOP A ’1’ will enable the transmit End of Packet interrupt.

A ’0’ will disable it.

B4 EnFA A ’1’ will enable the Frame Abort interrupt.

A ’0’ will disable it.

B3 EnTxFL A ’1’ will enable the Transmit FIFO Low interrupt.

A ’0’ will disable it.

B2 EnTxFun A ’1’ will enable the Transmit FIFO Underrun interrupt.

A ’0’ will disable it.

B1 EnRxFF A ’1’ will enable the Receive FIFO Full interrupt.

A ’0’ will disable it.

B0 EnRxFov A ’1’ will enable the Receive FIFO Overflow interrupt.

A ’0’ will disable it.

Table 9. HDLC Interrupt Mask Register (Write Add. 00100

)

BIT NAME DESCRIPTION

(1)

B7 Dcoll

A ’1’ indicates that a collision has been detected on the D-channel (i.e., received E-bit does not match with transmitted D-bit). This bit is available only in TE mode and when the HDLC transmitter is enabled. It always reads ’0’ in NT mode.

(1)

B6 EOPD

A ’1’indicates that an end of packet has been detected on the HDLC receiver. This can be in the form of a flag, an abort sequence or as an invalid packet.

(1)

B5 TEOP

A ’1’ indicates that the transmitter has finished sending the closing flag of the last packet in the Tx FIFO, and the internal priority level is reduced from high to low.

B4 FA

(1)

A ’1’ indicates that the receiver has detected a frame abort sequence on the received data stream.

B3 TxFL

(1)

A ’1’ indicates that the device has only four Bytes remaining in the Tx FIFO. This bit has significance only when the Tx FIFO is being depleted and not when it is getting loaded.

(1)

B2 TxFun

A ’1’ indicates that the Tx FIFO is empty without being given the ’end of packet’ indication. The HDLC will transmit an abort sequence after encountering an underrun condition.

(1)

B1 RxFF

A ’1’ indicates that the HDLC controller has accumulated at least 15 bytes in the Rx FIFO.

B0 RxFov

(1)

A ’1’ indicates that the Rx FIFO has overflown (i.e., an attempt to write to a full Rx FIFO). The HDLC will always disable the receiver once the receive overflow has been detected. The receiver will be re-enabled upon detection of the next flag.

Table 10. HDLC Interrupt Status Register (Read Add. 00100

Note 1: All interrupts will be reset after a read to the HDLC Interrupt Status Register.

)

9-55

Page 22

MT8930C Preliminary Informatio n

BIT NAME DESCRIPTION

B7-B2 R1A7-R1A2 A six bit mask used to interrogate the first byte of the received address (where B7 is MSB).

If address recognition is enabled, any packet failing the address comparison will not be

stored in the Rx FIFO. B1 NA Not applicable to address recognition. B0 A1En If ’0’, the first byte of the address field will not be used during address recognition.

If ’1’ and the address recognition is enabled, the six most significant bits of the first

address byte will be compared with the first six bits of this register.

Table 11. HDLC Address Recognition Register 1 (Read/Write Add. 00110

BIT NAME DESCRIPTION

B7-B1 R2A7-R2A1 A seven bit mask used to interrogate the second byte of the received address (where B7 is

MSB). If address recognition is enabled, any packet failing the address comparison will not be stored in the Rx FIFO. This mask is ignored if the address is a Broadcast (i.e., R2A = 1111111).

B0 A2En If ’0’, the second byte of the address field will not be used during address recognition.

If ’1’ and the address recognition is enabled, the seven most significant bits of the second address byte will be compared with the first seven bits of this register.

Table 12. HDLC Address Recognition Register 2 (Read/Write Add. 00111

)

BIT NAME DESCRIPTION

B7 AR Setting this bit will initiate the activation of the S-Bus.

If ’0’, the device will remain in the present state.

B6 DR Setting this bit will initiate the deactivation of the S-Bus.

If ’0’, the device will remain in the present state. This bit has priority over AR.

B5 DinB If ’1’, the D-channel will be placed in the B1 timeslot allocating 64 kbit/s to the D-channel.

If ’0’, the D-channel will assume its position with a 16 kbit/s bandwidth.

(1)

B4 Timing A ’0’ will set the NT in a short passive bus configuration using a fixed timing source (no

compensation for line length). A ’1’ will set the NT in a point-to-point or extended passive bus configuration with adaptive timing compensation.

B3 M/S This bit represents the state of the transmitted M/S-bit. M when HALF=0 and S when

HALF=1.

B2 HALF The state of this bit identifies which half of the frame will be transmitted on the S-

Bus. The operation of this signal is similar to that of the HALF pin.

B1 TxMFR A ’1’ in this bit, while HALF = 0, will force the transmission of a multiframe sequence in the

Fa and N bits, i.e., Fa=1 and N=0. A ‘0’ will resume normal operation, i.e., Fa=0 and N=1.

B0 RegSel If the register select bit is set to ’1’, the control register is redefined as the diagnostic

Table 13. NT Mode C-channel Control Register

Note 1: Allow one ST-BUS frame to input the C-channel and one ST-BUS frame to establish the connection. Note 2: The C-channel Control Register is updated once every ST-BUS frame. Therefore, this register should not be written to

more than once per frame, otherwise, the last access will over ride previous on es.

(2)

(Write Add. 01000B and B0 = 0)

(1)

9-56

Page 23

Preliminary Information MT8930C

BIT NAME DESCRIPTION

B7-B6 Loop The status of these two bits determine which type of loopback is to be performed:

B7 - B6 0 - 0 - no loopback active 0 - 1 - near end loopback LTx to LRx 1 - 0 - digital loopback DSTi to DSTo 1 - 1 - remote loopback LRx to LTx

B5 FSync If ’1’, the device will maintain frame synchronization even after losing the framing

sequence (i.e., if the device is transmitting INFO2 or INFO4 and this bit is set, the same INFO signal will still be transmitted even if the frame sync sequence in the received signal is lost). If ’0’, synchronization will be declared when three consecutive framing sequences have been detected without error.

B4 FLv If ’1’, the frame sync sequence will violate the bipolar violation encoding rule.

If ’0’, the framing pattern resumes normal operation, i.e., Framing bit is a bipolar violation. B3 Idle Setting this bit to ’1’ will force an all 1s signal to be transmitted on the line. B2 Echo Setting this bit to ’1’ will force all D-echo bits (E) to zero. B1 Slave If ’1’, the device will operate in a NT slave mode. This allows the device to be used at the

terminal equipment end of the line while receiving its clocks from an external source. B0 RegSel If the register select bit is set to ’1’, the control register is redefined as the diagnostic

Table 14. NT Mode C-channel Diagnostic Register (Write Add. 01000

and B0 = 1)

BIT NAME DESCRIPTION

B7 Sync/BA This bit is set when the device has achieved frame synchronization while the activation

request is asserted (DR = 0 and AR = 1). If there is a deactivation request or AR is low

(1)

(DR = 1 or AR = 0), this bit indicates the presence of bus activity

. A bus activity identifies

the reception of INFO frames (INFO1 or INFO3).

B6-B5 IS0-IS1 Binary encoded state sequence.

IS0 - IS1

0 - 0 - deactivated 0 - 1 - pending deactivation 1 - 0 - pending activation 1 - 1 - activated

B4 RxMCH Following a ‘0’ input at the HALF pin or HALF bit in the C-channel Control Register, the

state of this bit reflects the received maintenance Q-channel (received in the Fa bit

position during multiframing).

This bit will always read ‘1’ if multiframing is not used.

B3-B0 NA These bits will read

Table 15. NT Mode Status Register

Note 1: Bus activity is set when three zeros are received in a time period equivalent to 48 bits or 250µs. It is reset when 128 Note 2: The Status Register is updated internally once every ST-BUS frame. Therefore, more than one read access per frame will

consecutive ones are received. return the same value.

’1’.

(2)

(Read Add. 01001

)

9-57

Page 24

MT8930C Preliminary Informatio n

BIT NAME DESCRIPTION

B7 AR Setting this bit will initiate the activation of the S-Bus.

If ’0’, the device will remain in the present state.

B6 DR Setting this bit will initiate the deactivation of the S-Bus.

If ’0’, the device will remain in the present state. This bit has priority over AR.

B5 DinB If ’1’, the D-channel will be placed in the B1 timeslot allocating 64 kbit/s to the

D-channel. If ’0’, the D-channel will assume its position with a 16 kbit/s bandwidth.

(1)

B4 Priority The status of this bit selects the priority class of the terminal equipment. A ’1’ selects the

high priority and a ’0’ selects the low priority.

B3 DReq This bit is used to request or relinquish the D-channel on the S-Bus when the D-channel

source is the ST-BUS. A ’1’ will request the D-channel, a ’0’ will relinquish it.

Keep at ’0’ when the D-channel source is the HDLC transmitter. B2 TxMCH The state of this bit will be transmitted in the maintenance channel (Q-channel). B1 ClrDia A ’1’ will clear the contents of the Diagnostics Register.

A ’0’ will enable the maintenance functions found in the Diagnostic Register.

This bit should be set to 1 as long as the device is not fully active (IS0, IS1 ≠ 1,1). B0 RegSel If the register select bit is set to ’1’, the control register is redefined as the diagnostic

Ta ble 16. TE M ode C-cha nnel Contro l Registe r

Note 1: Allow one ST-BUS frame to input the C-channel and one ST-BUS frame to establish the connection. Note 2: The C-c hannel Control Register is updated once ever y ST-BUS frame. Therefore, this register should not be written to

more than once per frame, otherwise, the last access will override previous ones.

(2)

(Write Add. 01000B and B0 = 0)

BIT NAME DESCRIPTION

B7-B6 Loop The status of these two bits determine which type of loopback is to be performed:

B7 - B6

0 - 0 - no loopback active 0 - 1 - near end loopback LTx to LRx 1 - 0 - digital loopback DSTi to DSTo 1 - 1 - remote loopback LRx to LTx

B5 FSync If ’1’, the device will maintain frame synchronization even after losing the frame sync

sequence (i.e., if the device is transmitting INFO3 and this bit is set, INFO3 will still be

transmitted even if the frame sync sequence in the received signal is lost).

If ’0’, synchronization will be declared when three consecutive framing sequences have

been detected. B4 FLv If ’1’, the frame sync sequence will violate the normal bipolar encoding rule.

If ’0’, the framing pattern resumes normal operation, i.e., framing bit will be a bipolar

violation. B3 Idle If ’1’, an all 1s signal is transmitted on the line.

If ’0’, the transmitter will resume normal operation.

B2-B1 NA Unused.

B0 RegSel If the register select bit is set to ’1’, the control register is redefined as the diagnostic

Table 17. TE Mode Diagnostic Register (Write Add. 01000

and B0 = 1)

9-58

Page 25

Preliminary Information MT8930C

BIT NAME DESCRIPTION

B7 Sync/BA This bit is set if the device has achieved frame synchronization while the activation request

is asserted (DR = 0 and AR = 1). If there is a deactivation request or that AR is low ( DR = 1 or AR = 0), this pin indicates the presence of bus activity reception of INFO frames (INFO2 or INFO4).

B6-B5 IS0-IS1 Binary encoded state sequence.

IS0 - IS1

0 - 0 - deactivated 0 - 1 - synchronized 1 - 0 - activation request 1 - 1 - activated

B4 M/S This bit respresents the state of the received M/S-bit. M when HALF=0 and S when

HALF=1

B3 HALF The state of this bit identifies which half of the S-Bus frame is currently being output on the

ST-BUS. B2 RxMFR A ’1’ when HALF=0 indicates that the multiframe pattern on Fa and N has been detected. B1 Priority The status of this bit indicates the internal priority of the device within the designated

priority class. If 1, then it has high priority within the priority class designated in B4 of

control register. If 0, then it has low priority within the priority class designated in B4 of

control register.

(1)

. A bus activity identifies the

B0 DCack A ’1’ indicates that the device has gained access to the D-channel and has transmitted an

opening flag. This bit is reset to ‘0’ when the closing flag of the last packet in the TxFIFO is

transmitted and the internal priority is reduced from high to low. A collision during

transmission will also reset this bit back to ‘0’.

Table 18. TE Mode S tatus Register

consecutive ones are received. return the same value.

(2)

(Read Add. 01001

)

BIT NAME DESCRIPTION

B7-B2 NA Not available.

B1* INFO1 In TE mode, this bit is set to ‘1’ only when the device is transmitting INFO1.

Not available in NT mode.

B0* INFO0 In NT or TE mode, this bit is set to ‘1’ only when the device is transmitting INFO0.

Table 19. Master Status Register (Read Add. 10010

* These two bits can be used along with status bits IS0 and IS1 to distinguish between states F6/F8 and F4/F5 of the device’s state machine

in TE mode. Please refer to “State Machine” section of Application Note MSAN-141 for further det ails.

)

9-59

Page 26

MT8930C Preliminary Informatio n

Applications

The MT8930C is useful in a wide variety of ISDN applications. Being used at both the Network Termination (NT) and Terminal Equipment (TE) ends of the line, the SNIC finds application on digital subscriber line cards and in full featured digital telephone sets.

The SNIC can be combined with the MT8971B/72B to implement an NT1 function(with biphase line code on the U interface) as shown in Figure 16. It can also be combined with the MT8910 to implement an ISDN NT1 function (with 2B1Q line code on the U interface) a s shown in Figure 17. The MT 8930C is configured i n NT mode, a cting as a ma ster to the S interface line, while the MT8971B/72B or the MT8910 operates in slave mode and derives its timing from the U-interface line originating from the central office. For Figure 16, communication between the two devices is done via the serial STBUS ports. Control and status of the SNIC is communicated with the MT8971B/72B through the C-channel of the ST-BUS.

Both the MT8930C and MT9094 are controlled and monitored by a microp roces sor to i mplem ent var ious features and control functions. Signalling may be performed by scanning the keypad and generating appropriate messages to be packetized by the HDLC section of the SNIC and transmitted via the Dchannel. A twelve segment, non-multiplexed LCD display can be connected directly to the S12-S1 outputs to provide various status and call progress indicators.

It must be noted, that the pseudo-ternary line code will tolerate lin e r eve rsals within the LRx and LTx pair between the NT and TE. However, reversal of the TE transmit pair between two or more TEs will make the S-inter face i n op er a bl e .

In multidrop applications, a powered-off TE must not load the line and prevent communications between the NT and other TEs. To avoid such a situation, one mechanical re lay should be us ed to disconnec t the LTx pin and th e LR x pi n from the l i ne tr a n sf or m e r s.

Interfacing to Non-Multiplexed Busses

Figure 18 illustrates the use of the SNIC in conjunction with the MT9094 to implement a 2B+ D, ISDN telephone set. The MT9094 provides such features as A/D and D/A conversion, handset interface, ha nds free opera tio n and tone r ing er. PCM encoded voice is passed from the MT9094 to the SNIC via the ST-BUS port for transmission on one of the B-channels. The second B-channel is available for transmission of data. These two devices have been designed to connect together with vir tually no interconnec tio n compo ne nts.

MT8930C MT8971B/72B

LTx

LRx

Bias

DSTo

DSTi

F0b

C4b

P/SC

Rsti

Star

mode

+5V

10kΩ

0.33 µF

1:2*

‡

1:2*

+5V

10 µF

The microprocessor interface for the SNIC was designed around a multiplexed bus architecture which may be found with most Intel processors/ controllers or a few Motorola processors. In the event that your choice of processors is restricted, a simple application circuit can convert the nonmultiplexed bussing to that of a multiplexed architecture . Figure 19 p rovides an to interface the MC6802 or the MC6809 microprocessors.

+5V

22 nF

2:1

1.0 µF

0.33 µF

33 pF

DSTi DSTo

F0b C4b

MS0 MS1 MS2

V V

0.33 µF

REF Bias

+5V

OUT

OSC1

OSC2

1.5 nF

390 Ω

47 Ω

10.24 MHz XTAL

33 pF

9-60

DC to DC Converter

Figure 16 - NT1 Function

‡

100Ω terminating resistor

Page 27

Preliminary Information MT8930C

Microprocessor

U Reference

Point

‡

Termination

Network

MH89101

out+

in+

in-

out-

MT8910-1

DSLIC

C4b F0b

DSTi

DSTo

C4b F0b

DSTo DSTi

MT8930C NT Mode

LTx

Bias

LRx

+5V

Power Supply

and

Power Feed

‡

100Ω terminating resistor

Figure 17 - NT1 using the MT8910-1 (DSLIC) and MT8930C (SNIC)

DSTi DSTo

F0i C4i

MT9094

HSPKR+

HSPKR-

M+

M-

MIC+

MIC-

SPKR+

SPKR-

1:2

2kΩ

MT8930C

DSTo

LTx

Bias

LRx

DSTi

F0b

C4b

mode

2:1

10µF

‡

2:1

S Reference

Point

Handset

Microphone

Speaker

DC to DC

Converter

‡

IRQ

+5V

10k

100Ω terminating resistor

Data Port

DATA1

SCLK

S12-1

8051

IRQ

Figure 18 - ISDN Digital Telephone Set

Display

456

789

K e y p a d

9-61

Page 28

MT8930C Preliminary Informatio n

MT8930C

AD0-AD7

CS DS

R/W

Connections to interface to MC6809

74HCT245

DIR B

DIR

Address Decoder

MC6802

(MC6809)

A0 - A7

VMA

D0 - D7 R/W

E EXTAL (Q)

Figure 19 - Interfacing to the MC6802 Microprocessor

ETS 300-012 NT&TE Line Interface

Figure 20 shows the recommended line interface circuit for meeting the ETS 300-012 requirements. This circuit assumes that test measurements are made using the "standard reference cord" which has the following specifications:

C = 315pF to 350pF R = 2.7Ω to 3.0Ω Z > 75Ω Length < 10m

In Figure 20, R 1 and D5,6 (germani um) ensure that the pulse shape lies within the center of the various pulse templates. D1-4 protect the MT8930C from line transients. C2,3 decouple the VBias voltage and optimize the recei ver sen s itivit y. R2 and C4 make up a lowpass filter recommended for delaying the signal in TE applications, this filter can also be used for NT application s allowing common hardwa re for TE and NT applications. K1 isolates the MT8930C from the line for multidrop applications in cases where the device is powere d down. L1 (eg., Filtran CTS4669 or VAC N4025-X034) is a 4-winding 5mH common mode choke to suppress EMI on the 4-wire line. T1,2 (Filtran TPW-3852-4) provide isolation, longitudinal balance, impedance matching and voltage level conversion.

The TPW-3852-4 is available from:

Filtran Ltd. 229 Colonnade Road Nepean, Ontario Canada Telephone: (613) 226-1626

Proprietary NT&TE Line Interface

For proprietary applications, where stringent requirements such as ETS 300-012 do not have to be met, the line interface circuit may be simpler and consequently les s ex pens ive. Fig ure 21 sho ws s uch a line interface circuit. R1 should be chosen according to the transformer selected and the desired outpu t signal lev el, typica l values of R1 may vary from 30Ω to 75Ω. Numerous types of transformers may be used, including the following:

APC 8016D (dual with common mode choke) Filtran TEW-5660 (surface mount) Filtran TPW-3852-4 (single) Pulse PE-65495 (dual) VAC L4097-X028-80 (single)

9-62

Page 29

Preliminary Information MT8930C

MT8930C

LTx

LRx

Bias

Tx+

Tx-

Rx-

Rx+

Parts Li st:

C1, 3 = 0.1µF Ceramic

C2 = 10µF Tantalum C4 = 22pF D1-4 = IN914 D5, 6 = IN270 Germanium D7 = IN4003

K1 = 2 Form A or C Relay (eg., Aromat TQ2E-5V) L1 = see circuit description R1 = 1Ω 1% R2 = 3k01 1% R3, 4 = 100Ω 1% T1, 2 = see circuit description

MT8930C

LTx

LRx

Bias

Figure 20 - ETS 300-012 NT & TE Line Interface

Tx+

Tx-

Rx-

Rx+

Parts List:

C1, 3 = 0 . 1 µF Ceramic C2 = 10µF Tan talum D1-4 = IN914 R1 = see circuit description R2 = 2k to 4k R3, 4 = 1 0 0 Ω T1, 2 = see circuit description

Figure 21 - Proprietary NT & TE Line Interfa ce

9-63

Page 30

MT8930C Preliminary Informatio n

Absolute Maximum Ratings*

Parameters Symbol Min Max Units

1 Supply Voltage V 2 Voltage on any I/O pin V 3 Current on any I/O pin I 4 Storage Temperature T 5 Package Power Dissipation P

* Exceeding these values may cause permanent damage. Func tional operation under these conditions is not implied.

DD I/O

I/O

Recommended Operating Conditions - Voltages are with respect to ground (V

Characteristics Sym Min Typ

1 Supply Voltage V 2 Input High Voltage* V 3 Input Low Voltage* V 4 Load Resistance (LTx) R 5 Load Capacitance (LTx) C 6 Operating Temperature T

‡ Typic a l figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Except for CK/NT p in. See below. ** Including the transformer DC resistance.

4.75 5.0 5.25 V

2.4 V

L L

0 0.4 V For 400mV noise margin

-40 85 °C

DC Electrical Characteristics - Voltages are with respect to ground (V

‡

Max Units Test Conditions

250** Ω With reference to V

32 pF With reference to V

) unless otherwise stated

-0.3 7.0 V

-0.3 VDD + 0.3 V

-65 150 °C

) unless otherwise stated

V For 400mV noise margin

Characteristics Sym Min Typ‡Max Units Test Conditions

20 mA

1000 mW

Bias Bias

1 Supply Current

NT Activated NT Deactivated TE Activated TE Deactivated

2 Input High Voltage except for pin

DDNA

DDND

DDTA

DDTD

2.0 V Digital inputs

8 16 10

11 25 14

mA mA mA mA

Outputs loaded Outputs unloaded Outputs loaded Outputs unloaded

CK/NT 3 Input High Voltage for pin CK/NT V 4 Input Low Voltage except for pin

4 V Digital input

0.8 V Digital inputs

CK/NT 5 Input Low Voltage for pin CK/NT V 6 Output High Current I 7 Output Low Current I 8 Input Leakage (except pin 8) I

OH OL

10 15 mA VOH=2.4V digital outputs

5 7.5 mA VOL=0.4V digital outputs

1 V Digital input

10 µAVIN = V

9 Input Current for pin 8 25 µAVIN = V

10 Output Leakage High Imped. I

‡ Typic a l figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics - Voltages are with respect to ground (V

10 µAV

) unless otherwise stated

OUT

Characteristics Sym Min Typ‡Max Units Test Conditions

1 Input Voltage (LRx) V 2 Input Current (LRx) I

1.5 V Peak with Ref. to V 70 µAVI=1.5Vp Ref. V

@ f=0 - 100 kHz 3 Output Voltage (LTx) V 4 Output Current (LTx) I 5 Input Impedance (LRx) Z

‡ Typic a l figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 9-64

20 kΩ f = 100 kHz

1.5 V Ref. V

7.5 mA VO=1.5Vp Ref. V

SS SS

= V

, RL=250Ω

Bias

to V to V

to V

DD DD

Bias

, RL=250Ω

Bias

Page 31

Preliminary Information MT8930C

AC Electrical Characteristics† - ST-BUS Timing NT Mode (Ref. Figure 22)

Characteristics Sym Min Typ‡Max Units Test Conditions

1F0b 2 Frame pulse (F0b 3 Frame pulse (F0b 4 C4b 5 C4b 6 C4b 7 F0od 8 F0od 9 Serial input set-up time t

10 Serial input hold time t

11 Serial output delay t

input pulse width t

) set-up time t

) hold time t input clock period t pulse width High or Low t transition time t

delay t pulse width t

FPW

FPS

FPH

P4o

C4W

C4T

DFD

DFW

SIS

SIH

SOD

122 244 ns

35 ns 50 ns

244 ns 122 ns

20 ns

20 87 ns 40 pF Load

244 ns

70 ns

0ns

160 320

nsns50 pF load

50 pF load (HDLC connected

to ST-BUS) 12 HALF input setup time t 13 HALF input hold time t

† Timing is over recommended temperature & power supply voltages ‡ Typic a l figures are at 25°C and are for design aid only: not guaranteed and not subject to production test ing.

HAS

HAH

0ns

200 ns

F0b

C4b

F0od

DSTi

DSTo

ST-BUS Bit Cell

FPW

C4W

SIS

P4o

C4W

SIH

DFD

DFW

FPS

HAS

C4T

SOD

HAH

FPH

HALF

Figure 22 - ST-BUS Timing NT Mode

9-65

Page 32

MT8930C Preliminary Informatio n

AC Electrical Characteristics† - ST-BUS Timing TE Mode (Ref. Figure 23)

Characteristics Sym Min Typ‡Max Units Test Conditions

1F0b 2 C4b 3 C4b 4 C4b 5 C4b 6 C4b 7 F0od 8 F0od 9 Serial input setup time t

10 Serial input hold time t

11 Serial output delay t

12 HALF output Delay t

† Timing is over recommended temperature & power supply voltages ‡ Typic a l figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

output pulse width t

to (F0b) delay t to (F0b) hold time t output clock period t pulse width High or Low t transition time t

delay t pulse width t

ST-BUS Bit Cell

FPW

CFD

CFH

P4o

C4W

C4T

DFD

DFW

SIS

SIH

SOD

HAD

244 ns 50 pF load

10 50 ns 50 pF load 10 50 ns 50 pF load

244 ns 50 pF load

110 122 ns 50 pF load (activated state)

20 ns 50 pF load

10 50 ns 220 244 ns 150 ns

0ns

125 ns 50 pF load 150 ns 50 pF load

F0b

C4b

F0od

DSTi

DSTo

HALF

FPW

SOD

HAD

CFH

CFD

C4W

SIS

P4o

C4W

C4T

SIH

DFD

DFW

9-66

Figure 23 - ST-BUS Timing TE Mode

Page 33

Preliminary Information MT8930C

AC Electrical Characteristics† - Intel Bus Interface Timing (Ref. Figure 24 & 25)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1 Chip select setup time t 2 Chip select hold time t 3 Address Latch pulse width t 4 Address setup time t 5 Address hold time t 6 Data setup time - Write t 7 Data hold time - Write t 8 Data output delay - Read t 9 Data hold time - Read t

10 Write pulse width t

11 RD

, WR delay t 12 Read pulse width t 13 Read setup time t

CSS

CSH

ALW

ADS

ADH

DWS

DHW

DOD

DHR

WPW

RWD

RPW

RDS

10 ns 25 ns 50 ns 20 ns 20 ns 35 ns 20 ns

240 ns 50 pF load 25 90 ns 50 pF load 60 ns 60 ns

240 ns

20 ns

† Timing is over recommended temperature & power supply voltages ‡ Typic a l figures are at 25°C and are for design aid only: not guaranteed and not subject to production test ing.

ALE

CSS

ALW

ADS

ADH

RWD

CSH

DHW

AD0-7

ALE

AD0-7

RDS

Address Data in

DWS

WPW

Figure 24 - Intel Bus Interface Timing (Write Cycle)

I/OH

I/OL

RDS

ALW

ADS

Address

ADH

CSS

RWD

DOD

Data out

RPW

CSH

DHR

Figure 25 - Intel Bus Interface Timing (Read Cycle)

9-67

Page 34

MT8930C Preliminary Informatio n

AC Electrical Characteristics† - Motorola Bus Interface Timing (Ref. Figure 26)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1 Chip select setup ti me t 2 Chip select hol d time t 3 Address strobe pulse width t 4 Data strobe setup time t 5 Data strobe hold t 6 Data strobe pulse width - Write

CSS

CSH

ASW

DSS

DSH

DSW

- Read 7 Read/Write setup time t 8 Read/Write hold time t 9 Address setup time t

10 Address hold time t

11 Data setup time - Write t 12 Data hold time - Write t 13 Data output delay t 14 Data hold time - Read t

† Characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ‡ Typic a l figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

RWS

RWH

ADS

ADH

DWS

DHW

DOD

DHR

10 n s 10 n s 50 ns 20 ns 20 ns

100 240

ns 40 ns 10 ns 20 ns 20 n s 35 ns 30 ns

240 ns 50 pF load

25 90 ns 50 pF load

R/W

AD0

-AD7

(Write)

CSS

ASW

DSS

ADS

DSH

RWS

ADH

Address Data Input

ADH

DOD

DSW

DWS

CSH

RWH

DHR

DHW

9-68

AD0

-AD7

(Read)

I/OH

I/OL

Address Data Output

Figure 26 - Motorola Bus Interface Timing

Page 35

Preliminary Information MT8930C

AC Electrical Characteristics† - Controllerless Mode Timing (Ref. Figure 27)

Characteristics Sym Min Typ

‡

Max Units Test Conditions

1C 2C 3C 4C 5C 6C

F0b

C4b

Inputs

Outputs

inputs setup time (TE Mode) t

mode

inputs setup time (NT Mode) t

mode

inputs hold time (TE Mode) t

mode

inputs hold time (NT Mode) t

mode

outputs delay (TE Mode) t

mode

outputs delay (NT Mode) t

mode

CIS

CIH

CIS

CIH

COD

120 ns 120 ns 120 ns 120 ns

240 ns 50 pF load 240 ns 50 pF load

Controllerless Inputs include:

MFR (NT Mode) MCH (TE Mode) M/S (NT Mode) AR DR

Controllerless Outpu ts inclu d e: IS0 & IS1

MFR (TE Mode) MCH (NT Mode) M/S (TE Mode)

Figure 27 - Controllerless Mode Timing

AC Electrical Characteristics† - IRQ, Rsti Timing (Ref. Figure 28)

Characteristics Sym Min Typ‡Max Units Test Conditions

1 Interrupt release delay t 2 Reset pulse width t

DS/RD

IRQ

Rsti

IRD

RSW

1 µs

100 ns

IRD

RSW

Figure 28 - INT & Rsti Timing

9-69

Page 36

MT8930C Preliminary Informatio n

Notes:

9-70