SHARP
1 To : ED1
SPECIFICATIONS.
ISPEC No.
ISSUE:
Sep. 2 1999
Product Type
Model No.
-X This specifications contains 22 pages including the cover and appendix.
If you have any objections, please contact us before issuing purchasing order.
CUSTOMERS ACCEPTANCE
DATE :
BY:
__-__---
_- --.-
LZ 9 G Series 1 6 0 0 Gates Gate Array
LZ9GFl6
PRESENTED
Dept.General Manager
REVIEWED BY:
Engineering Dept. 2
Display Device
System LSI Development Center
Integrated Circuits Group
SHARi CORPORATION -
PREPARED BY:
SHARP
LZ9GF16
@Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written
permission of the company.
@When using the products covered herein, please observe the conditions written herein and the precautions
outlined in the following paragraphs. In no event shall the company be liable for any damages
resulting from failure to strictly adhere to these conditions and precautions.
( 1 ) The products covered herein are designed and manufactured for the following application areas.
When using the products covered herein for the equipment listed in Paragraph (2 1, even for
the following application areas, be sure to observe the precautions given in Paragraph ( 2 ).
Never use the products for the equipment listed in Paragraph ( 3 ).
*Office electronics
. Instrumentation and measuring equipment
l
Machine tools
* Audiovisual equipment
l
Home appliances
* Communication equipment other than for trunk lines
( 2 > Those contemplating using the products covered herein for the following equipment which demands
high reliability, should first contact a sales representative of the company and then accept
responsibility for incorporating into the design fail-safe operation, redundancy, and other
appropriate measures for ensuring reliability and safety of the equipment and the overall system.
. Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
. Mainframe computers
. Traffic control systems
. Gas leak detectors and automatic cutoff devices
0 Rescue and security equipment
0 Other safety devices and safety equipment, etc.
( 3 ) Do not use the products covered herein for the following equipment which demands extremely
high performance in terms of functionality, reliability, or accuracy.
*Aerospace equipment
* Communications equipment for trunk lines
. ControI equipment for the nuclear power industry
*Medical equipment related to life support, etc.
( 4 )Please direct all queries and comments regarding the interpretation of the above three Paragraphs
to a sales representative of the company.
l Please direct all queries regarding the products covered herein to a sales representative of the
company.
LZ9GFi6
CONTENTS
1
1. Introduction
2. Feature
3. Pin Assignments
4. Explanation of Input / Output signal
5. Absolute Maximum Ratings
6. Electrical Specifications
7. Condition for signal circuit
8. Illustration of control circuit
9. Input / Output signal timing chart for above cases
10. OutIine dimension
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Page
02
92
l 3
l
4-5
-6
-6
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7-8
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9-11
’ 12-19
l
20
* SHARI=
1. Introduction
This data sheet is to introduce the specification of LZ9GF16,
timing control IC for TFT-LCD module.
The functions and the uses
Horizontal frequency driver(NTSC:600 divided frequency /PAL:604 divided frequency) and
phase comparator circuit for the PLL circuit are built in.
By adding voltage Controlled Oscillator(VC0) and Low Pass Filter(LPF) to this IC to make the
PLL circuit, following signals synchronized with input composite sync.
Signal(SYN1) and vertical sync. Signal(VIN) conforming to NTSC or PAL are generated.
.
LZ9GF16
Timing control IC for 5” size and 5.6” size TFTlLCD module
2
1) Driving signal for source driver
2) Control signal for source driver
3) Driving signal for gate driver
4) Control signal for gate driver
5) Control signal for gate driver power supply making
6) Polarity alternating signal for common electrode driving signal
7) Polarity alternating signal for video signal
8) Control signal for the backlight PWM brightness control
2. Feature
Process
Wafer substrate
Package
Operating Temperature : -30°C - +85”C
Propagation delay time
Illustration of control circuit
Input/Output signal timing chart for above cases
: CMOS
: P-type silicon substrate
(pin & type)
(material) : Plastics
(Condition
supply voltage=5V, Operating temperature Topr=25”C)
: Z-input NAND, Fanout=X, wire length=2mm,
: 48QFP (0.75mm pin pitch)
: 0. Snslgate
: CLD, SPD
: CTR, DIS
: CLS, SPS
: LOW0
: GPS
: FBPT
: FRPV
: CHK
: See fig. l-a - l-c
: See fig. 2-a - 2-j
*REMARK
Not designed or rated as radiation hardened.
You cannot rewrite the program.
SHARP
3. Pin Assignment
LZ9GF16
3
ICU
ICS
01M
02M
ORZ
ORZx2
TOlM
IOCUBM
IOCURZ
OSCB
osco
hD
GND
: Input buffer CMOS level with PULL UP resistance R=250k8
: Schmitt-trigger Input buffer CMOS level
: Output buffer I,=O.BmA
: Output buffer 1,,=1.61nA
: Slew rate controlled Output buffer
: Slew rate controlled Output buffer 1~,=16OflA .
* ORZx2 buffer is connected two ORZ buffer in parallel.
: Tri-state Output buffer 1,,,=0.8mA
: Bidirecional buffer CMOS level with PULL UP resistance R=250kQ, 1,~=1.6mA
: Slew rate controlled Bidirecional buffer CMOS level
with PULL UP resistance R=250kQ, IoL=80pA
: Oscillator Bidirecional buffer with oscillation stop control
: Oscillator Output buffer Io,=l.6mA
: Power supply pin
: Earth pin
I,,=BOfiA
10,=3. 2mA
SHARP
LZ9GF16
4
1
4. Explanation of Input / Output signal
?IN No.’
1 I
Signal Name
VIN Vertical sync. Signal input (Positive)
Explanation I/O
.
2 CVOP Vertical sync. Signal Output for Count Down circuit
3 CVIN Vertical sync. Signal input for Count Down circuit
4 DVOP Vertical sync. Signal output for digital separator circuit (Positive) 0
5
FBJT Polarity alternating signal output for common electrode driving signal 0
6 GPS Logic pals output for gate driver power supply making 0
7
a
GND
Ground
EXCL Input / Output for outside Clock signal
9 SYNI Composite sync. signal input
10 HSY Internal horizontal sync. signal output (Negative)
11 VSY Internal vertical sync. signal output (Negative)
12 DIS Control signal output for source driver
13
TEST0
Monitor signal output for test
14 NTPC Terminal for display mode change NTSC or PAL [Note11 I
15
16
17
ia
VRVC Input for the Vertical scanning direction setting (Note21
HRVC Input for the horizontal scanning direction setting (Note31
CHK Output for signal of backlight brightness control 0
TEST1
Input terminal for test (Note41
19 TEST0 Monitor signal output for test
20
21
22
23
24
25
26
27
28 ,
29 I
30 j
31 / GND I Ground
32 I
-__
33
---__
34
.__ -.- -
35 I
36 :
-~---
37 ’
_____.____~ __ ._~ ~..... ._ ~. .- __ ..-. ~-____-__
38
39 ; TEST1
_---
40 F---
.-.- ~~ A&y-:--.
41 ,Horlzontal scanning setting output for source driver
_-.------e-.---. --- -__--___
42 ~
IVB Scanning setting input for gate driver
_--
SPS Besetting signal output for gate driver
CLS
Clock signal output for gate driver
.__.
LOW0 Control signal output for gate driver 0
CT& Control signal output for source driver
--__
_____-
SPD Starting signal output for source driver
CLD Clock signal output for source driver
osco
osc I Input for clock oscillator circuit
SAM0 Control signal output for source driver
~----t---------.~... --.. ~__
bD
TEST1
7---./Input-f;;-ini fil ye;;7-;j-ga1
LOW1
--F-~~--~-‘--.-..-
__--_- _.-
Output for clock oscillator circuit
_---_ .---
..___- --._- . .._--.- ___IPower supply voltage
_ ._ ..-. -~- -- -..__--__ ~-______
f--------;. _- ---- --
IInput terminal for test(Note41
-
~~~--~
-____
-__
-__-
IPoIarlty alternating<ign&%$ut for video signa
RESH TGi%t!l-counter resetting input (Note51
PDP 1 o-
IOutput for_phasecomparative signal of PLL circuit
--.--
RESV /Vertical counter resetting input (Note61
TEST1 Input terminal for test (Note41
-I-
__-.._ . ~.---- ____---
IInput terminal for test (Note41
___. -_- .-. --.-__-__ -_.~
iHorizontal scanning setting output for source driver
- -.-.
_-__--~-~
-__
-------------,~ -
--j--‘-t
--
___-
CLOC
Input for EXCL si&l-outpu%etting (Note71
____
1-- --
--i--t-
VSY signal input / output setting (Note81
I
0
I
I/O
I
I/O
I/O
0
0
I
I
I
0
0
0
0
0
/ 0
/ I
_.-
-L--I .-
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LZ9GF16
.
5
(Note11
(Note21
[Note31
(Note41
(Note51
[Note61
(Note71
(Note81
(Note91
NTPH=H
NTPC=L
VRVC=H
VRVC=L
HRVC=H
HRVC=L
Normal state : H level
BESH=H
RESH=L
RESV=H
RESV=L : forcible reset
CLOC=H : L level output
CLOC=L
CLKC=H
CLKC=L
SAMC=H : It is the independent data-sampling timing at RGB
SAMC=L
: NTSC nethod
: MBK-PAL method
: Normally (Positive scanning)
: Reversal (Negative scanning)
: Normally (Positive scanning)
: Reversal (Negative scanning)
(Refer : 9, Scanning direction setting)
: Normally
: forcible reset
: Normally
: H level output
: EXCL, HSY, VSY terminals become output mode
: EXCL, HSY, VSY terminals become input mode
: It is the simultaneous data-sampling timing at RGB dots
(Note101
Horizontal display position is changed by delay time
SHARI=
LZ9GF16
6
5. Absolute Maximum Ratings
Parameter Symbo 1
Supply voltage
InDut V"'+a-
Output vo 1 tage
IOerating temperature 1 Topr 1
ptorage temperature 1 Tstg 1
6. Electrical
6-l
Operating conditions
Parameter Symbol min typ max
Supply voltage
Operating temperature Topt -30 -
[Note] Input/Output terminal of TESTI, TEST0 should be used under
Signal Name
TEST1 I
TEST0 0
fi-2 Electrical characteristics
Parameter
Specification
I/O
VDD
V,
I “0 I
VII0
Fixed H level
Connected GND by O.l,v capacitor
I Svmbl
Rating Unit
-0.3~t6.0 V
-0.3~vnrl+0.3
-u..J-
VDDTU.
J
-3o--+85
4.5 5.0 5.5 v
t85 “C
Used condition
V
“C -55-t150
Unit
the
lowing conditions.
IOutput “Low” voltage
IOutput “High” voltage j
I Output “Low” voltage !
jOutput
lOutput “High” voltage -IOutput “Low” voltage /
bms--;;i tagyi--
n--.r --
High voltage
Output”Low” voltage /
Jutput “Low” voltage I
~_- ---.
#l:
__.----
Applied to input pins (ICU) and Bidirecional pins (OSCB, IOCUZM, IOCURZ)
input mode
Applied to input pins (ICS)
Applied to input pins (ICS) and Ridirecional pin (OSCB) input mode
Applied to input pins (ICUJ and Bidirecional pins
Applied to output pin (OSCO)
(OSCO : under the condition the input level of OSCB (input mode) = VDD or OV 1
Applied to output pin (02M) and Bidirecional pin (IOCUZM) output mode
Applied to output pins (OlM, TOlM)
Applied to output pins (ORZ) and Bidirecional pins (IOCURZ) output mode
Applied to output pins (ORZx2)
Applied to Bidirecional pin (OSCB) output mode
Applied to output pin (TOtM)
VOM
(IOCU2M, IOCURZ) input mode
SHARP
7. Condition for signal input
7-l In case of using PLL circuit (CLKC=H)
Clock input : OSCI
Parameter
Input frequency
Duty ratio
Symbo 1
l/To
TOL~M
LZSGjF16
min
UP
max
9.4 MHZ
40160 so/50 60140
unit
%
7
remarks
Composite (Horizontal) sync. signal (Positive) : SW1
Input condition
Base on NTSC(M) system
Base
on PUB, 3) system
remarks
NTPC=H
NTPC=L
fsm125a ~MZ
f &304
600
I
16
58
Timing of VIN input to be specified. (See fig. 2-h)
fsyn=SYNI (composite sync. signal) input frequency (unit : kHz)
(Note31 In case of no VIN input, vertical counter inside of IC is reset
automatically based on f&284 (NTPC=H), fsun/344 (NTPC=L).
(Note41
After VSY falling, VIN input is invalid during the period of
192H(NTPC=H), 227H(NTPC=L). (lH=l/ fm)
However, the case of VSY falling by automatic reset is exceptional.
Input LOWI, RESH and RESV
Input VDI, through and integration circuit(Contro1 circuitry example : refernces)
with following value(z ,),
or please input the Low level after
jSymbol---
T”
i
min
20
DD turning on by this period system reset.
V
--___ _____
tYP
---~~--~.ioo~ ,
aax----
Unit 1
ms _J
kIi!?l
PS
PS
NTPC=H
NTPC=L
(Note1 1
’ SHARP
7-2 In case of input outside sync. signal (CLKC=L)
LZ9GF16
3) Vertical sync. signal (Negative) : VSY
Parameter
Input frequency
Pulse width
Symbol
fv1
TV1
min
50
1
VP
f&Z62
3 5
max
h/258
Unit
Hz
H
4) Input signal timing
Parameter
EXCL-HSY
HSY -VSY
Symbol
Data
setup time
Data hold time hOI
Data setup time
Data hold time
hll
hz
GIOZ
min typ max
25
25
1.0
1.0
Unit
ns
ns
remarks
(Note51
(Note61
(Note51 In case of outside sync. signal input mode, it show EXCL and HSY timing.
In this case HSY input signal is brought at the rising timing of EXCL input signal.
(Note61 In case of outside sync. signal input mode, it show HSY and VSY timing.
In this case VSY input signal is brought at the rising timing of HSY input signal.
remarks
SHARI=
LZ9GF16
9
I I I
I
I I I II II
I
I I I
I I 1
I I
r
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LZgGF”16
10
1
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LZ9GF16
11
1
I
I I I
r
I
I
I
9. Input / Output signal timing chart for above
OCR
cases
SOO(O)CK : NTPC = H (NTSC mode)
604(O)CK : NTPC = H (PAL mode)
,
HSY
SPD
CLD
QPS
CTR
CLS
FRPT
FRPV
BLKO
I(NTSC)
-O.WAL)
-----~,.-.-~ .-.......” ~-..._......_.-......_.~......~...~: . . ..~-..“‘\
---.---.f- ---.-..-..... _-- -... _
------
I
1
-0.6; II2 2
f
!
72
I
-0.6 i
!
i
1
i
!
I
i
,.- .._.--.._.-........ I _...._.__..........._. _ .._._..
i
-_
i .,...._ .._ . ..- . ...” ..-....
66 : 66
\
\ ..-... . .
SO
.._ I ..-..-....,
\
i
1045(SAMC=ll)
08 (SAMC=I )
\ I,
‘5
5
$
106 -0.6 !
I B
//
.._ -............ _ .._........._..........__.........~ - ..__......” .-..... _ ..__._.__._. - .._.__._.._. - _...._..-._ - _._..__. i.-_... _ .._________.._
..--...... _ -...... _._ -..._.. .._._.._..._ - . ..__.-.......- . ..-...........--...-..-....-..
..- _ ._..._ - ..__......_...___........-... ---.--.------.-.-----.---i- -._--. _-^
O(NTSC) 1
603.6(I’AL) 1
-0.6 1
!
j
i
i
(
I
!
I
i
_.-_--..-- .-_._ I_.-_ _ ___-_,__.__._._._,___
!
6(NTSC) i
I(I’AL) 1
(’ ’ 63
104.6(SAhlC=H)
112
72
I06
..l-_l_
60
DIS
63
I
Fig.?,-a Horizontal counter timing chart- 1 ( In case of using PLL circuit)
I
!
I
/
i
HSY
SPD
CLD
GPS
CTR
CIS
FRPT
FRPV
DIS
OCK
I
i
‘;
III
.-.--_, * . ...__,___..,_. _-__ .._ I: .._._.._............. .._.
_ -_____.
-._.----_..-.. ,. ._,. - .._.._... _....-.._..._...... -_. .._
i
i
I
I
i
__._._ -- _.._. ._ . .._ _ _ . . . . . . .
1-”
! \
I
I
!
I
i
i
1
I
I i
I
i
i
78 174
,
8’2
\
*. . . _.
74 166
I
Fig.2-b Horizontal counter timing chart-2
1200(O)CK
1199
(5
//
g
>
201
I20
. ,. . _ 5 -... .._ ..-....__.-_. .- _........r. _ .._... ..- _. .-._ - .._ - _..___........_...._ _ _....... -__-._-.___ .__. I ..__II__. fws
\$
>(
192
\I
1168
/ 6
//
,.. .._.... - ..__..........I..~......_._-......~.....-.......,. - ..__ - .__. -._- ..,......____,__., I -_______.__._-
I28
1.
i ..-..........-. _ .
$
.._.... i .._.....^._. _.._ .~....-...._.__...._._.....~~.......,..~__._... _ .._...._.._.. ._._.__.__.__....___.” _,_,_
z
5 i
( In case of input outside sync. signal akd SAMC = “H ” )
I
/
I
I
1
!
!
72
120
i
174
201
------_--_
---_-
1
!
i
!
I
I
!
I
I--i
i
82
128
..--. --__--_
-----_-
74
I
I
i
I
192
68
SHARP .
LZ9GF16
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v
\
e
hc
g - --.-.- -..
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_..-.. -..-.---.
SHARI=
LZ9GF16
15
--
1
L
-
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SHARP
LZ9GF16 ’
16
'i
VSY
626H (NTPC = H)
------- - -._G26H (NTPC = L)
CHK
‘(NTPC=H)
CHK
(NTPC=L)
VSY
HSY
CHK
106H 2
/
----
1 1
8911
./
._~_ ‘.
-__-.- --.--..-.._--____ _________
Expansion of time axis
1’
I I
--.-.. __--__----.-- -...--._ -_.-.~-._III I
L
uuJHluuuuuuhl
-
u
626Hm-TPC = II)
G26H (NTPC = L)
nH
/
U u u
.
,
I
u u u u u Ill
I I
106H (NTPC = H)
nH
Period of invecter okcillate
Fig.2-f Output signal timing of CHK (Control signal for the backlight PWM brightness control)
89H (NTPC = L)
----A-
eriod of invert& not oaciIIate
l
VSY
LOW1
‘LOW0
HSY
Fig.2-g Output signal timing of LOW0
VIN
HSY
SYNI
PDP
r
Pig.2-h Input signal timing of VIN (Using separated circuit of vertical sync. signal)
I
I I I .
‘r
I
I
I I I I I
II2 (fligh-impedance state )
Fig.24 Output signal timing of PDP
I
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LZ9GF16’
19
-
-
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10. Outline dimension
p-o.mTYP. 48-0.33kO.l
SEE DETAI
A
CJ ,I d,,
d +(
ii 2
- m
PKG. BASE PLANE 6 ? o
tl -11
7
I 1
P
DETAIL A
N
/
I
I *
5% / !I - Fikt j TIN-LEAI: #f&t
ME i QFP48-P-1010 LEAD FINISH i PLATING NOTE Plastic body dimensions do not include burr
*ia 1
DRAWING NO. i AA873 UNIT ! mm
1~~~7I/t7~-%~\ A9 $$~trrid~lfr, a
of resin.
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