Datasheet LZ2346 Datasheet (Sharp)

LZ2346

1/3 type B/W CCD Area Sensor for

DESCRIPTION

LZ2346 is 1 /3-type (6.0 mm) solid-state image sensor that consists of PN phote-diodes and CCDS (charge-coupled devices) driven by only positive voltages. Having approximately 220000 pixels (horizontal 384

vertical 582), the sensor

provides a stable B/W image.

FEATURES

●

Number of pixels : 362 (H) X 582 (V) Pixel pitch : 13.6 Number of optical black pixels

: Horizontal; front 2 and rear 20

●

Low fixed pattern noise and lag

●

No sticking and no image distortion

●

Blooming suppression structure

●

Built-in output amplifier

●

Variable electronic shutter (1/50 to 1/10 000 s)

●

Compatible with

●

Package : 16-pin

(H) x 6.3

standard

(V)

supply

V and +12

PIN CONNECTIONS

16-PIN

SDIP

GND 3

0s 4

H2 B 6

operation

TOP VIEW

16 TI

15 OFD

14

13 4V2

12

11 4V4

10 4V3

9 tiH1

—

BLOCK DIAGRAM

GND

0s

data Wks,

by device ~!ticatron

SHARP

In

order

OD RD

II

Horizontal Shift Register

OFD

any

in

any SHARPS device”

using any

SHARPS

PIN DESCRIPTION

SYMBOL

RD

0s

OFD

GND

PIN NAME

Reset transistor drain

Output transistor drain Video Reset transistor gate clock Vertical shift register gate clock

Horizontal shift register gate clock

Transfer gate clock Overflow drain

Test terminal

Ground

ABSOLUTE MAXIMUM RATINGS

PARAMETER

transistor drain

Reset transistor drain voltage

Test terminal, TI

Reset gate clock voltage

Vertical shift register clock voltage

Horizontal shift register clock voltage Transfer gate clock voltage Overflow drain voltage Storage temperature

ambient temperature

SYMBOL

VOD

Tstg Topr

RATING

+15

Oto Oto +15 Oto +15

–0.3 to +15 –0.3 to –0.3 to +15 –0,3 to +15

O to

–40 to

–20 to +70

(Ta

UNIT

v v v v v v v v

RECOMMENDED OPERATING CONDITIONS

Operating ambient temperature Output transistor drain voltage Reset transistor drain voltage

Overflow

drain voltage

Test terminal, T! Ground voltage

Transfer gate clock

Vertical register clock

Horizontal shift register clock

Reset gate

Vertical Horizontal shift register clock frequency Reset gate clock frequency Horizontal shift register clock phase

When DC is applied When pulse is applied

p-p level

LOW level HIGH level LOW level HIGH level LOW level HIGH level

level

LOW

level

HIGH

SYMBOL

MIN.

Topr 25.0

Voo

V

OFD

12,0 12.5

3.0

12,0 12.5 14.0

GND

v

TGL

v

– 0.05 0.0 0.05

12.0

–

0.05

4.7

0.0

V

RD – 6.0

twl ,

0.0

TYP.

MAX.

UNIT

14.0

Voo

12,0 v

Voo

0.0

12.5 14,0

0.0 0,05

5.0 6.0

0.05

5.0

15.63 6,75 MHz

6.75 MHz

6.0

-10.5 v

kHz

10.0

NOTE

‘c

v

1

v

2

v v v v v v v v

v

ns

3

NOTES :

1. When DC voltage is applied, shutter speed is 1 /50 seconds.

2. When pulse is applied, shutter spaed is less than 1/50 seconds.

3

“

-

ELECTRICAL CHARACTERISTICS (Drive method : Field Accumulation)

(Ta = 2SC, Operating conditions : typical values for the recommended operating conditions, Color temperature of light source :3200 K /

Photo response non-uniformity Saturation signal Dark output voltage Dark signal non-uniformity Sensitivity Smear ratio Image lag Blooming suppression ratio Output output impedance

drain current

cut-off filter (CM-500, 1

SYMBOL

PRNU

vast

Vdark DSNU

R

SMR – 85 – 76

Al

ABL 1000

Ro

MIN.

450

140

TYP. MAX.

15

5.0

15.0

1.5

5.0

200

1.0

2.5

400

5.0

UNIT NOTE

2

3 1, 4 1, 5

6

7

8

9

I

<

● The standard output voltage is defined as 150

average output voltage under uniform illumination.

● The standard exposure level is defined when the average

output voltage is 150

under uniform illumination.

by the

NOTES :

Ta : The image area is divided mto 10X 10 segments.

2

3

4 5

voltage is the average output voltage of all the

pixels within the segment. PRNU is defined by (Vmax –

the minimum values of each segment’s voltage respectively, when the average output voltage Vo is 150 mV. The image area is divided into 10x The saturation signal is defined as the minimum of each segment’s voltage which is the average output voltage of all the pixels within the segment, when the exposure level is The average output voltage under a The image area is defined by

where Vmax and Vmin are the maximum and

10 segments.

as 10 times, compared to standard level.

into 10x 10 segments. OSNU is

–

under the non-exposure con-

dition where Vdmax and Vdmin are the maximum and minimum values of each segment’s voltage, respective y, that is the average output voltage over al segment.

6.

The average output voltage when a 1 COO attached with a 90% reflector is imaged by a lens of f50 mm. The sensor is adjusted to position a V/l O square at the center of image area image area. SMR is defined by the ratio of the output voltage detected during the vertical blanking maximum of the pixel voltage in the V/l O square. The sensor is

ing to the standard condition preceding dition. Al is defined by the ratio between the output voltage measured at the 1st field during the non-exposure period and the standard output voltage.

9

The sensor is adjusted to position a V/l O square at the center of image area. ABL is the ratio between the

V is the

at the

is observed.

pixels in the

light source

length of the

level

to the

con-

PIXEL STRUCTURE

SPECTRAL

100

80

w >

OPTICAL BIACK

(2 PIXELS)

RESPONSE EXAMPLE

362 (H)

X 582

(v)

OPTICAL BLACK

(20 PIXELS)

20

0

400

800

1

1200

TIMING DIAGRAM EXAMPLE

3rd FIELD)

HD VD

V4

623

n

625 1

u

uuu

n

VERTICAL TRANSFER TIMING

5

n

u

u u

n

n n

n

u

n

nnn

uuu

n

u

n

n n

n

u

u u

n

n n

n

n n n n

u

n

u u

n n

u

u I

n

19

(2nd. 4th

0s

HD

VD

V2 V3

0s

582

311

n

nnn n

u u uuuuu

n

582

n n n

I

n

318

,

n n

n

u

u n

n

HORIZONTAL TRANSFER

nnnnn n

n

TIMING

nnn

uuu u

n

331

u

n

357

2468

n

u

u u u

n

n n n

246 +++

I

II

n

u

n

0s

. . . . . . . . . . . . . ...362

06(2)

. . . . . . . . . . . . . . . . . . . . . .

READOUT TIMING

(1S, 3rd

(2nd,

FIELD)

180

SYSTEM CONFIGURATION EXAMPLE

m

ll

181