Datasheet KH300 Datasheet (Fairchild Semiconductor)

Features

■

-3dB bandwidth of 85MHz

■

3000V/µsec slew rate

■

4ns rise and fall time

■

100mA output current

■

Low distortion, linear phase

Applications

■

Digital communications

■

Baseband and video communications

■

Instrument input/output amplifiers

■

Fast A to D, D to A conversion

■

Graphic CRT video drive amp

■

Coaxial cable line driver

General Description

The KH300 operational amplifier is a current feed­back amplifier that provides a DC-85MHz -3dB band­width that is virtually independent of gain setting.
Rise and fall times of 4ns and drive capability of
22Vppand 100mA add to the KH300’s impressive
specifications.

Using the KH300 is as easy as adding power supplies
and a gain-setting resistor. Unlike conventional op
amp designs in which optimum gain-bandwidth
product occurs at a high gain, minimum settling time
at a gain of -1, maximum slew rate at a gain of +1,
et cetera, the KH300 offers consistent performance
at gain settings from 1 to 40 inverting or non-inverting.
As a result, designing with the KH300 is greatly
simplified. And since no external compensation is
necessary, “tweeks” on the production line have been
eliminated, making the KH300 an efficient
component for use in production situations.

Flat gain and phase response from DC to 45MHz and
superior rise and fall times make the KH300 an ideal
amplifier for a broad range of pulse, analog, and
digital applications. A 45MHz full power bandwidth
(20V

pp

into 100Ω) and 3000V/µsec slew rate eliminate

the need for power buffers in many applications
such as driving “flash” A to D converters or line­driving. For applications requiring lower power
consumption, the KH300 can operate on supplies as
low as ±5V. Fast overload recovery (20ns) helps
prevent loss of data in communications applications
and flat phase response reduces distortion, even when
data must be sent over extended lengths of line.

The KH300A is packaged in a side-brazed 24-pin
ceramic DIP and is specified at 25°C.

KH300

Wideband, High-Speed Operational Amplifier

www.fairchildsemi.com

REV. 1A February 2001

KH300 Equivalent Circuit Diagram

Pin 11 provides access to a 1500Ω feedback
resistor which can be connected to the out­put or left open if an external feedback
resistor is desired. All undesignated pins are
internally unconnected.

16

+V

CC

6

V+

V-

+

12

V

o

8

-

1500

24

13

GND

-V

CC

R

11

f

2 REV. 1A February 2001

DATA SHEET KH300

magnitude of gain {|V

out/Vin

|]

4* 20 40

PARAMETERS CONDITIONS TYP MIN

2

TYP MAX

2

TYP UNITS

Frequency Domain Response

-3dB bandwidth Vo< 4V

pp

105 75 85 70 MHz

Vo= 20V

pp

45 45 45 MHz

gain flatness 100KHz to 20MHz ±0.25 ±0.08 ±0.3 ±0.25 dB

20MHz to 45MHz ±0.5 ±0.25 ±0.6 ±1 dB
phase shift 1 1.6 2 deg/MHz
deviation from linear phase DC to 45MHz 2 3 5 deg
reverse isolation 60 70 70 dB
distortion refer to graphs

Time Domain Response

rise and fall time 5V output step 3 4 5 ns

20V output step 7 7 7 ns
settling time to 0.8% 10V output step 20 20 25 ns
overshoot (input rise time ≤ 1ns) 5V output step 5 5 5 %
slew rate 3 3 3 V/

µs

overload recovery (200% od) < 50ns pulse width 20 20 20 ns

General Information CONDITIONS MIN

2

TYP MAX

2

UNITS

input offset voltage (drift) 10(25) 32 mV(µV/°C)
input bias current (drift) non-inverting 10(20) 30

µV(nA/°C)

inverting 30(50) 100

µV(nA/°C)

equivalent input noise

1

integrated 0.1 to 100MHz, 22 56 µV

(R

s

= 50Ω, gain = 20)

second/third harmonic distortion 20MHz, +10dBm 48 38 -dBc
input impedance non-inverting 100K/3

Ω/pF

power supply rejection ratio input referred 45 60 dB
common mode rejection ratio input referred 64 dB
output drive voltage,current 10, 100 V, mA
supply current 24 33 mA

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.

NOTES:

1) For Noise Figure, refer to Distortion and Noise section in text.

2) 100% tested at +25°C, A

V

= +20, RL= 100Ω, and VCC= ±15V.

* Refer to

Low Gain Operation section.

Absolute Maximum Ratings

supply voltage (±VCC) 16V (±5V min)
output current (I

o

) 100mA

input voltage (V

imax

) (|VCC| - 2.5)/A

V

common mode input voltage ±1/2 |VCC|
power dissipation refer to graph
junction temperature (T

J

) 150°C
storage temperature -55°C to +150°C
still air thermal resistance (

θca) +25°C/W

KH300 Electrical Characteristics

(25°C, VCC= ±15V, RL= 100Ω; unless noted)

KH300 DATA SHEET

REV. 1A February 2001 3

KH300 Performance Characteristics

(25°C, VCC= ±15V, RL= 100Ω; unless noted)

Non-Inverting Gain

Av = 4

Av = 20

Relative Gain (1dB/div)

0102030405060708090

Freguency (MHz)

Broadband Inverting & Non-Inverting Gain

Inverting

Relative Gain (10dB/div)

Av = 40

Av = 20

Non-inverting

Inverting Gain

Av = 20

Relative Gain (1dB/div)

100

0102030405060708090

Freguency (MHz)

Inverting & Non-Inverting Phase

0

°

-90

-180

°

°

Non-inverting

Av = 40

Inverting

Av = 4

Av = 20

100

-180

-270

-360

°

°

°

0 100 200 300 400 500 600 700 800 900

Freguency (MHz)

2nd & 3rd Harmonic Distortion Intercept

90

80

(I2)
2nd harmonic intercept
exceeds 90dBm below 10

70

60

50

Intercept Point (+dBm)

40

30

(I3)
3rd harmonic intercept
exceeds 64dBm below 10

4

10

5

10

6

10

Av = 20

5

Hz

5

Hz

10

Freguency (Hz)

Non-Inverting Small Signal Pulse Resp.

Av = 20

1GHz

0102030405060708090

100

Freguency (MHz)

2-Tone 3rd Order Intermod. Intercept

50

45

40

35

30

Intercept Point (+dBm)

7

8

10

25

0204060

Av = 20

80

100

Freguency (MHz)

Inverting Small Signal Pulse Response

Av = -20

Output Voltage (1V/div)

Time (5ns/div)

Output Voltage (1V/div)

Time (5ns/div)

DATA SHEET KH300

4 REV. 1A February 2001

KH300 Performance Characteristics

(25°C, VCC= ±15V, RL= 100Ω; unless noted)

Large Signal Pulse Response

Av = -20

Output Voltage (2V/div)

Time (5ns/div)

Relative Bandwidth vs. V

1.1

1.0

0.9

0.8

Relative Bandwidth

CC

Av = 20

Settling Time

0.4

0.2

0

-0.2

-0.4

Settling Error (%)

-0.6

-0.8
0 200 400 600

Time (ns)

Power Dissipation Derating

2.5

2.0

1.5

1.0

Ambient

10V step

= 20

A

v

800

150°C max T

VCC = ±15V

Case

1000

J

0.7
46 810

12

VCC (V)

Equivalent Input Noise

100

Inverting Current

10

Voltage Noise (nV/√Hz)

1

10210310410510610710

11pA/√Hz

Voltage

2.9nV/√Hz

Non-inverting Current

2.3pA/√Hz

Frequency (Hz)

Power Supply Rejection Ratio

80

70

60

50

CMRR (dB)

40

Circuit Power Dissipation (W)

0.5

14

16

-25 0 25 50

75

100

Temperature (°C)

Common Mode Rejection Ratio

100

80

Current Noise (pA/√Hz)

70

10

1

8

60

50

CMRR (dB)

40

30

10110210310410510610

7

Frequency (Hz)

30

1

10

10210310410510

6

Frequency (Hz)

KH300 DATA SHEET

REV. 1A February 2001 5

Layout Considerations

To assure optimum performance the user should follow
good layout practices which minimize the unwanted
coupling of signals between nodes. During initial bread­boarding of the circuit, use direct point to point wiring,
keeping lead lengths to less than 0.25”. The use of
solid, unbroken ground plane is helpful. Avoid wire-wrap
type pc boards and methods. Sockets with small, short
pin receptacles may be used with minimal performance
degradation although their use is not recommended.

Figure 1: Recommended Non-inverting Gain Circuit

Figure 2: Recommended Inverting Gain Circuit

During pc board layout keep all traces short and direct.
Rfand Rgshould be as close as possible to pin 8 to
minimize capacitance at that point. For the same reason,
remove ground plane from the vicinity of pins 8 and 6. In
other areas, use as much ground plane as possible on
one side of the pc board. It is especially important to
provide a ground return path for current from the load
resistor to the power supply bypass capacitors. Ceramic
capacitors of 0.01 to 0.1µF should be close to pins 13

and 16. Larger tantalum capacitors should also be
placed within one inch of these pins. To prevent signal
distortion caused by reflections from impedance mis­matches, use terminated microstrip or coaxial cable
when the signal must traverse more than a few inches.
Since the pc board forms such an important part of the
circuit, much time can be saved if prototype boards of
any high frequency sections are built and tested early in
the design phase.

Controlling Bandwidth and Passband Response

As with any op amp, the ratio of the two feedback resistors
Rfand Rg, determines the gain of the KH300. Unlike
conventional op amps, however, the closed loop pole­zero response of the KH300 is affected very little by the
value of Rg.Rgscales the magnitude of the gain, but
does not change the value of the feedback. Rfdoes
influence the feedback and so the KH300 has been
internally compensated for optimum performance with
Rf= 1500Ω, but any value of Rf> 500Ω may be used
with a single capacitor placed between pins 8 and 12 for
compensation. See table 1. As Rfdecreases, Ccmust
increase to maintain flat gain. Large values of Rfand
Cccan be used together or separately to reduce the
bandwidth. This may be desirable for reducing the noise
bandwidth in applications not requiring the full frequency
response available.

Table 1: Bandwidth vs. Rfand Cc(Av= +20)

R

f

C

c

f

±0.3dB

f

-3.0dB

(KΩ) (pF) (MHz) (MHz)

10.0 0 2 5

5.0 0 3 12

2.0 0 8 40

1.5 0 45 85

1.0 0.3 90 115

0.75 1.1 95 130

0.50 1.9 110 135

Low Gain Operation

The small amount of stray capacitance present at the
inverting input can cause peaking which increases with
decreasing gain. The gain setting resistor Rgis effectively
in parallel with this capacitance and so a frequency
domain pole results. With small Rg(Gain > 8), this pole
is at a high frequency and it affects the closed loop gain
of the KH300 only slightly. At lower values of gain, this
pole becomes significant. For example, at a gain of +2,
the gain may peak as much as 3dB at 75MHz, and have
a bandwidth exceeding 150MHz. The same behavior
does not exist for low inverting gains, however, since the
inverting input is a virtual ground which maintains a
constant voltage across the stray capacitance. Even at
inverting gains << 1, the frequency response remains
unchanged.

+15

22µF

16

6

+

11

R

g

-15

KH300

8

-

13

12

24

0.01µF22µF

R

o

1/2 V

o

50Ω

Av = 1 +

Rf = 1500Ω (internal)

R
50Ω

R
R

L

f

g

V

in

0.01µF

R

i

50Ω

+15

51

R

g

-15

22µF

6

8

16

+

KH300

-

13

11

24

R

o

1/2 V

12

50Ω

For Zin = 50Ω Select:

0.01µF22µF

Rg||Ri = 50

-Av =

R

= 1500Ω (internal)

f

o

R

L

50Ω

R

f

R

g

V

in

0.01µF

R

i

50Ω

DATA SHEET KH300

6 REV. 1A February 2001

To avoid the peaking at low non-inverting gains, place a
resistor Rpin series with the input signal path just ahead
of pin 6, the non-inverting input. This forms a low pass
filter with the capacitance at pin 6 which can be made to
cancel the peaking due to the capacitance at pin 8, the
inverting input. At a gain of +2, for example, choosing
Rpsuch that the source impedance in parallel with R

i

(see Figure 1), plus Rpequals 175Ω will flatten the
frequency response. For larger gains, Rpwill decrease.

Settling Time, Offset, and Drift

After an output transition has occurred, the output
settles

very rapidly to final value and no change occurs
for several microseconds. Thereafter, thermal gradients
inside the KH300 will cause the output to begin to drift.
When this can not be tolerated, or when the initial offset
voltage and drift is unacceptable, the use of a compos­ite amplifier is advised. This technique reduces the off­set and drift to that of a monolithic, low frequency op
amp, such as an LF356A. The composite amplifier
technique is fully described in the KH103 data sheet.

A simple offset adjustment can be implemented by con­necting the wiper of a potentiometer, whose end termi­nals connect to ±15V, through a 20K resistor to pin 8 of
the KH300.

Overload Protection

To avoid damage to the KH300, care must be taken to
insure that the input voltage does not exceed (|VCC| -

2.5)/AV. High speed, low capacitance diodes should be
used to limit the maximum input voltage to safe levels if
a potential for overload exists.

If in the non-inverting configuration the resistor Ri, which
sets the input impedance, is large, the bias current at
pin 6, which is typically a few pA but which may be as
large as 18µA, can create a large enough input voltage
to exceed the overload condition. It is therefore recom­mended that Ri < [(|VCC| -2.5)/ AV]/(18µA).

Distortion and Noise

The graphs of intercept point versus frequency on the
preceding page make it easy to predict the distortion at
any frequency, given the output voltage of the KH300.
First, convert the output voltage (Vo) to V

rms

= (Vpp/2√2)

and then to P = (10log10(20V

rms

2

)) to get output power in
dBm. At the frequency of interest, its 2nd harmonic will
be S2= (I2 - P) dB below the level of P. Its third harmonic
will be S3= 2 (l3= P) dB below P as will the two tone
third order intermodulation products. These approxima­tions are useful for P < -1dB compression levels.

Approximate noise figure can be determined for the
KH300 using the Equivalent Input Noise graph on the
preceding page. The following equation can be used to
determine noise figure (F) in dB:

Where vnis the rms noise voltage and in is the rms noise
current. Beyond the breakpoint at the curves (i.e., where
they are flat), broadband noise figure equals spot noise
figure, so ∆f should equal one (1) and vnand in should
be read directly off of the graph. Below the breakpoint,
the noise must be integrated and ∆f set to the appropriate
bandwidth.

22

iR

n

v

n

F

=+

10 1

log

2

+

kTR f

4

f

A

2

v

∆

s

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT
OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for
surgical implant into the body, or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support device or system whose
failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

KH300 Package Dimensions

DATA SHEET KH300

www.fairchildsemi.com © 2001 Fairchild Semiconductor Corporation

Pin #1

Index

b1

Q

b

e

D1

D

Symbol

Inches Milimeters

A

L

Minimun Maximum Minimum Maximum

A-Metal Lid 0.180 0.240 4.57 6.10

A-Ceramic Lid 0.195 0.255 4.95 6.48

A1-Metal Lid 0.145 0.175 3.68 4.45

A1-Ceramic Lid 0.160 0.190 4.06 4.83

b 0.014 0.026 0.36 0.66

b1 0.050 BSC 1.27 BSC

c 0.008 0.018 0.20 0.46

D 1.275 1.310 33.39 33.27

D1 1.095 1.105 27.81 28.07

E 0.785 0.815 19.94 20.70

E1 0.790 0.810 20.07 20.57

e 0.100 BSC 2.54 BSC

L 0.165 BSC 4.19 BSC

Q 0.015 0.075 0.38 1.91

NOTES:

Seal: seam weld (AM, AK), epoxy (AI)
Lead finish: gold finish

Package composition:

Package: ceramic
Lid: kovar/nickel (AM, AK),

Leadframe: alloy 42
Die attach: epoxy

E

A1

ceramic (AI)

C

E1