Datasheet FAN3506 Datasheet (Fairchild Semiconductor)

FAN3506

PC SMPS Secondar y Side Control IC

www.fairchildsemi.com

Features

• Few External Components

• Low Voltage Operation (Vcc_min=4.5V)

• Over Voltage Protection for 3.3V/5V/12V Output

• Two Protection Inputs (PT1, PT2)

• Fault Protection Output with Open Collector

• Power Supp ly on/off Delay Time Control (PSON)

• Latch Function Controlled by PSON and Protection

• Power Good Signal Genera tor with Hysteresis

• 300ms(Typ) Power Good Delay

• Programmable Shunt Regulator Trimmed to ±2%

• 16-Pin Dual In-line Package (16-DIP-300)

Block Diagram

V5

V33

1

V12

23

Description

The FAN3506 is complete housekeeping circuitry for use in
the secondary side of PC SMPS (Switched Mode Power
Supply). It contains various functions, which are over
voltage protection including two extra protection inputs,
power supply on/off delay control and power good signal
generator. Especially, it contains a programmable shunt
regulator for output feedback and the reference voltage is
trimmed to ±2%. The FAN3506 is available in 16-DIP.

16-DIP

1

FPO

5

V

CC

4

CC

R3

R4

R5

R6

V

CC

8

TPSON

1.26V

lon

+
+
+
+
+

_

V

V

_
+

COMP3

1.8V~0.6V

R1

PT1

13
14

PT2

PSON

7

©2002 Fairchild Semiconductor Corporation

R2

V

CC

lil

V

+
_

COMP2

3.2V

1.4V

CC

CC

S
R

1.26V

PG

9

Q3

IK

15

16

VREF

Q2

lchg

10

TPG

_
+

COMP6

1.8V~1.2V

V

R9

R7

R8

Q

V

CC

+

_

V

Rd

Q1

CC

loff

6

R11

R10

R12

11 12

PGI

CC

_

_
_

+

COMP4

1.32V~1.26V

_

+

COMP5

1.32V~1.26V

GND

3.9V

Rev. 1.0.2

FAN3506

Pin Description

No Name I/O Function

1 V33 I +3.3V Output Voltage of SMPS Secondary Side
2 V5 I +5V Output Voltage of SMPS Secondary Side
3 V12 I +12V Output Voltage of SMPS Secondary Side

Supply Voltage. +5Vsb(+5V Standby Supply) is Recommended for Vcc.

4V

CC

5FPOO

6Rd -

7PSON I

8TPSON -

9PGO

10 TPG -

11 PGI I
12 GND - Ground

13 PT1 I Protection Input 1. This can be Used for an Adjustable OVP or Another Protection Input.
14 PT2 I Protection Input 2. This can be Used for an Adjustable OVP or Another Protection Input.

15 IK I

16 V

REF

I

The Operating Range is 4.5V~15V. Vcc=5V, Ta=25°C at test.
Fault Protection Output(FPO) With Open Collector Structur e. This Signal Controls the

Primary Switch(PWM IC) Through an Opto-coupler. Maximum Current Rating is 20mA.
When FPO = "Low", the Main SMPS is Operational and if FPO = "High", the Main S MPS
is Turned-off.

OFF Delay Resistor. This Block is Made up of a Buffer With Vout = 1.258V. A Resistor
Should be Connected to the Pin6 for Determination of Off Delay Current. The
Recommended Value of Rd Resistor is 28kΩ at Ctpson=0.22uF. The off Delay Time is
Gotten by Following Equation. Toff = [ Ctpson * (V8max-VthL) ] / (1.258V/Rrd)

Power Supply On/Off (Remote On/Off) Inpu t. It is TTL Operation a nd its Threshold
Voltage is 1.4V. The Maximum Voltage of Pin7 is About 3.9V(Typ), With ABsolutely
Maximum Voltage, 5.25v. If Pson Is Low, Fpo Is Low, Too. That Means The main SMPS
is Operation(Active). When PSON is High, then FPO is High and the Main SMPS is off.

Power Supply On/Off Delay. Ton/Toff = 24ms/8ms(Typ) with Ctpson=0.22uF &
Rd=28kΩ. Its High/Low Threshold Voltages 1.8V/0.6V and the Maximum Voltage After
Full Charging is About 2.2V. So Vcharge = VthH = 1.8V and Vdischg = V8max - VthL =

1.6V.
Each Delay Time is Decided by the Following Equations, Ton = (Ctpson*VthH) / Ion, Toff
= [Ctpson*(V8max-VthL)] / (Vrd/Rrd) .

Power Good Signal Output with Open Collector. The Maximum Current Rating is 20mA.
PG High Means that the Power is Good for Operation and PG low Means Power Fail.

PG Delay. Td = 300ms(Typ) with Ctpg=2.2uF. Th e Threshold Voltage is 1.8V and the
Delay Time is Decided by the Following Equation, Td = (Ctpg * Vth) / Ichg = 1.8Ctpg /
Ichg.

Power Good Signal Input. Its Threshold Voltage is 1.26V When the PGI Voltage Drops
From High to Low.

Cathode of the Programmable Shunt Regulator. Absolute Min/Max Current Rating is
1mA/30mA.

Reference of Programmable Shunt Regulator. This Circuit is Prepared for Feedback of

I

Output Voltage as it Equals to KA431(LM431). It is Trimmed to ±2%.

2

FAN3506

Absolute Maximum Ratings

Parameter Symbol Value Unit

Supply Voltage V

CC

4.5 ~ 15 V
FPO (Fault Protection Output) Voltage VFPO 20 V
FPO Maximum Current IFPO 20 mA
PGI Maximum Voltage Vpgi 20 V
PG Output Maximum Current Io(PG) 20 mA
Cathode Voltage Vka 20 V
Cathode Current for IK IK 1 ~ 30 mA
Power Dissipation P
Operating Temperature Range T
Storage Temperature T

D
OPR
STG

1W

-25 ~ +80 °°°°C

-65 ~ +150 °°°°C

Electrical Characteristics

(V

= 5V, Ta = 25°°°°C, unless otherwise specified)

CC

Parameter Symbol Test Conditions Min. Typ. Max. Unit
PROTECTION SECTION

OVP Detecting Voltage for 3.3V V
OVP Detecting Voltage for 5V V
OVP Detecting Voltage for 12V V
Protection Input Voltage 1 V
Protection Input Voltage 2 V

POWER SUPPLY ON/OFF SECTION (PSON)

PSON Input Threshold Voltage V
PSON Input Open Voltage V
PSON Input Low Current lil PSON=0V 0 - -1 mA
PSON Delay Charging Current lon PSON=TPSON=0V -10 -16 -24 uA
Buffer Output Voltage VRd lsink=45uA, 200uA 1.21 1.26 1.31 V
Pin8 Clamping Voltage V
High Threshold for On/Off Delay (Note1) VthH TPSON : 0V to 2.2V 1.6 1.8 2.0 V
Low Threshold for On/Off Delay (Note2) VthL TPSON : 2.2V to 0V 0.4 0.6 0.8 V
Power Supply ON Delay Time (Note3) Ton Cpin8=0.22µF, Rd=28kΩ 16 26 36 msec
Power Supply OFF Delay Time (Note4) Toff Cpin8=0.22µF, Rd=28kΩ 4 8 14 msec
FPO Saturation Voltage V
FPO Leakage Current lleak(FPO) FPO=20V 0 0.01 1 uA

33 PSON=0V 3.9 4.1 4.3 V

OVP

5 PSON=0V 5.7 6.1 6.5 V

OVP

12 PSON=0V 13.6 14.3 15.0 V

OVP

1 PSON=0V 1.21 1.26 1.31 V

pt

2 PSON=0V 1.21 1.26 1.31 V

pt

th
ih

8max

(FPO) lo=10mA - 0.2 0.4 V

sat

PSON=0V : 0V to 2V 1 1.4 1.8 V
PSON : Open 2 - 5.25 V

PSON=0V 2.0 2.2 2.4 V

3

FAN3506

Electrical Characteristics

(Continued)

(VCC= 5V, Ta = 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min. Typ. Max. Unit
POWER GOOD SECTION

PGI Threshold Voltage V
V33 Under Voltage Level V
V5 Under Voltage Level V
V12 Under Voltage Level V
Pin10 Clamping Voltage V10

pgi

33 V33 : 3.3V to 2V 2.66 2.8 2.94 V

uv

uv

12 V12 : 12V to 9V 9.8 10.3 10.8 V

uv

max

PGI : 1.5V to 1V 1.21 1.26 1.31 V

5 V5 : 5V to 3.5V 4.1 4.3 4.5 V

TPG : Open 3.4 3.9 4.4 V
PG Delay Comparator Threshold Voltage Vth(TPG) TPG : 0V to 2.5V 1.5 1.8 2.1 V
PG Delay Comparator Hysteresis Voltage HY TPG : 2.5V to 0V 0.3 0.6 0.9 V
Charging Current for PG Delay lchg TPG = 0V -9 -15 -23 uA
PG Delay Time Td(PG) Cpin10 = 2.2uF 100 300 500 msec
PG Output Rising Time (Note5) Tr Cpin9 = 0.1uF - 1 - usec
PG Output Falling Time (Note6) Tf Cpin9 = 0.1uF - 1 - usec
PG Output Saturation Voltage Vsat(PG) lsink = 15mA - 0.2 0.4 V
PG Output Leakage Current lleak(PG) V(PG) = 20V 0 0.01 1 uA

PROGRAMMABLE SHUNT REGULATOR (KA431) SECTION

Reference Input Voltage V

ref

IK = V

, IK = 1mA 2.45 2.50 2.55 V

REF

Load Regulation Vref IK = 1mA to 10mA - 5 15 mV
Temperature Stability (Note7) ∆Vref/∆T Ta = -25 ~ +85°C-4.517mV
Output Sinking Current Capability lsink - 10 25 - mA
Gain Bandwidth (Note8) GBW GV = 1 - 1 - MHz

TOTAL DEVICE

Supply Current Icc PSON = 2V - 3 8 mA

Note :

1. Power Supply ON Delay (PSON :High → Low). Power Supply is Active when PSON is Low.

2. Power Supply OFF Delay (PSON :Low → High). Power Supply is Off when PSON is High.

3. Ton = (Cpin8 * Von) / lon = (Cpin8 * VthH) / lon

4. Toff = (Cpin8 * Voff) / loff = [Cpin8 * (V8max - VthL)] / (VRd / Rd)
5,6,7,8 : These parameters, although guaranteed, are but not 100% tested in production.

4

Block Description & Application Hints

1. OVP Block

FAN3506

R1

R2

V5

2

R3

R4 R6

V12

3

R5

1.26V

+
+

+

+
+

_

VCC

SET of Latch

COMP1

PT1

PT2

V33

1

13

14

OVP function is simply realized by connecting Pin1, Pin2, Pin3 to each secondary output. R1,2,3,4,5,6 are internal resistors of
the IC. Each OVP level is determined by resistor ratio and the typical values are 4V/6.1V/14.2V.

- OVP Detecting voltage for +3.3V
. Vovp33 = (R1+R2)/R2 * 1.26V = 4.1V(Typ)

- OVP Detecting voltage for +5V
. Vovp5 = (R3+R4)/R4 * 1.26V = 6.1V(Typ)

- OVP Detecting voltage for +12V
. Vovp12 = (R5+R6)/R6 * 1.26V = 14.3V(Typ)
Especially, Pin13 & Pin14 are prepared for extra OVP inputs or another protection signal, respectively. That is, if you want

over voltage protection of extra output voltage, then you can make a function with two external resistors.

- Threshold Voltage of Protection Input 1 : Vpt1 = 1.26V

- Threshold Voltage of Protection Input 2 : Vpt1 = 1.26V
OVP function operates without delay time. In the case of OVP, system designer should know a fact that the main power can be

dropped after a little time because of system delay, even if FPO is triggered by OVP.
So when the OVP level is tested with a set, you should check the secondary outputs(+3.3V/+5V/+12V) and FPO(Pin5)

simultaneously. you can know the each OVP level as checking each output voltage in just time that FPO is triggered from low
to high.

5

FAN3506

2. PSON & ON /OFF Delay Block

Toff

Ton

FPO

5

PSON

7

PSON

VCC

lil

3.2V

+
_

1.4V

FPO

VCC

COMP2

PG

OVP

S

Q

R

VCC

lon

VCC

_

+

COMP3

1.5V ~ 0.6V

8

TPSON Rd

C1
103

1.26V

VCC

+

_

Q1

VCC

loff

11

R1
27K

PSON & On/Off Delay Bloc k is co ntr ol le d by a Mic r op ro c e ssor.
If a high signal is supplied to the PSON(Pin7), the output of COMP2 becomes high status. The output signal is transferred to

On/Off delay block and PG block.
If no signal is supplied to Pin7, Pin7 maintains high status(=3.2V) for the internal pull-up resistor.
When PSON is high, it produces FPO(Pin5) "High" signal after OFF delay time (about 8ms) for stabilizing system.
Then, all outputs (+3.3V, +5V, +12V) are grounded.
When PSON is changed to "Low", it produces FPO "Low" signal after ON delay time (about 26ms) for stabilizing the
system.
If PSON is low, then FPO is lo w. That means the main SMPS is Active(operational). When PSON is high, FPO is high and the

main SMPS is turned-off.
On/Off Delay Time can be calculated by following e quation. 0. 22uF Capacitor is recomme nded for follo wing equatio ns.

- Ton = (Ctpson*VthH)/Ion=(0.22uF*1.8V)/16uA = 26ms

- T off = [Ctpson*(V8max-VthL)] / Io ff = [Ctpson*(V8ma x-VthL)] / (VRd/ R d )

Because Ion current for charging is fixed by internal current source, On delay time is varied by the capacitor value. On the con­trary, Off Delay time is decided by the Rd value. If the Rd is 27K(Recommended) and the Delay capacitor valuse is 0 .22uF,
Toff is 8ms(Typ).

6

3. Latch & FPO Output

OVP SET RESET Qn+1 Qn+1

LLLQnQn

LLHLH
HHL HL
HHH LH

+5Vsb

7

PWM IC

(KA38XX)

1

2

FAN3506

PC800-1

R8
1K

FPO

Q100

OVP

PSON

PC800-2

6

Q1

Power Good Signal Generator circuits generate "On & Off" signal depending on the status of output voltage to prevent the
malfunctions of following systems like microprocessor and etc. from unstable outputs at power on & off .
At Power On, it produces PG "High" signal after some delay (300ms_Typ) for stabilizing outputs.
At power Off, it produces PG "Low" signal without delay by sensing the status of power source for protecting following
systems. COMP6 creates PG "Low" without delay when + 5V output falls to less than 4.3V to prevent some malfunction at
transient status, thus it improves system stability. FAN3506 detects the Under Voltage level of three
outputs(+3.3V/+5V/+12V) and PGI, respectively.

- UV Deducing Level of +3.3V : Vuv33 = 2.8V(Typ)

- UV Deducing Level of +5V : Vuv5 = 4.3V(Typ)

- UV Deducing Level of +12V : Vuv12 = 10.3V(Typ)

- UV Deducing Level of PGI : Vpgi = 1.26V(Typ)
When PSON signal is high, it generates PG "Low" signal without delay. It means that PG becomes "Low" before main power

is grounded. PG delay time(Td(PG)) is determined by capacitor value, threshold voltage of COMP6 and the charging current
and its equation is as following.
Td(PG) = (Ctpg * VthH) / Ichg = 300ms(Typ)

7

FAN3506

4. Programmable Shunt Regulator

IK

15

(KA38XX)

1

PWM IC

V5

2

PC300-1

VREF

16

8

2

IK

15

R1

0.11k

C1
103

R2
1k

C2
224

R3
10k

V12

3

R4
39k

16

PC300-2

VREF

R5

4.7k

R6
1k

The core of the circuit equals to KA431(LM431) and Vref1 is trimmed to ±2% (2.45V ~ 2.55V) and it is for corrective output
voltages (+5V/+12V). + 5V/ + 12V output voltages are determined by the resistor ratio of R3, R4, R5, R6.
A photo coupler is used in order to control PWM IC in the primary side. R1 determines the bias current of the shunt regulator
and 110Ω is appropriate value. The resistor value can be changed by set condition and requirements.
C1 and R2 , C2 are the compensation circuit for stability.

8

Typical Application Circuit

#1

0.11K

PC300-1

10K

FAN3506

39K

+5Vsb

PC800-1

1K

+3.3V

+5V

+12V

Micom

224

FPO

27K

V33

V5

V12

F

VREF

IK

PT2

224

PT2

A

Vcc

FPO

N
3

PT1

GND

PT1

5

Rd

PSON

TPSON

[ Complete Housekeeping Circuit using the FAN3506 ]

L

I

O

+

0
6

+3.3V/+5V/+12V

PGI

TPG

PG

2.2uF

+

7

PWM IC

(KA38XX)

1

2

1K

103

5K

Det

V

=12V

Z

20K

8

1K

Micom

Q100

PC300-2

PC800-2

9

FAN3506

Typica l Perfo rmance Characteristics

Figure 1. Temperature Stab ility for VRd

Figure 3. Temperature Stability for Vref

Figure 2. Buffer Output Voltage vs. IRd

Figure 4. Current Stability of Vref

10

Figure 5. OVP Detecting Voltage for 3.3V

Figure 6. OVP Detecting Voltage for 5V

FAN3506

Typica l Performance Characteristics

Figure 7. OVP Detecting Voltage for 12V

(Continued)

Figure 8. Protection Input Voltage 1,2

Figure 9. PSON Input Threshold Voltag

Figure 11. FPO Saturati on Voltage

e

Figure 10. H igh/Low Threshold of On/Off Delay

Figure 12. PG I Threshold Voltage

11

FAN3506

Typica l Performance Characteristics

Figure 13. V33 Under Voltage Level

(Continued)

Figure 14. V5 Under Voltage Level

12

Figure 15. V12 Under Voltage Level

Figure 17. PG Saturation Voltage

Figure 16. High /Low Threshold of

PG Delay COMP

Figure 18. Supply Current of V

CC

FAN3506

Typica l Performance Characteristics

Figure 19. Power Supply On/Off Delay Time

(Continued)

Figure 20. PG Delay Time

13

FAN3506

Mechanical Dimensions

Package

6.40 ±0.20

0.252 ±0.008

16-DIP

Dimensions in millimeters

0.81

0.032

()

#1

#8

7.62

0.300

#16

#9

MAX

19.80

0.780

3.25 ±0.20

0.128 ±0.008

5.08

0.200

19.40 ±0.20

MAX

0.764 ±0.008

±0.10

0.46

0.018 ±0.004

2.54

0.100

0.38
MIN

0.014

3.30 ±0.30

0.130 ±0.012

1.50 ±0.10

0.059 ±0.004

14

0~15°

0.25

0.010

+0.10
–0.05

+0.004
–0.002

Ordering Information

Product Number Package Operating Temperature

FAN3506 16-DIP -25°C ~ +85°C

FAN3506

15

FAN3506

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURT HER NOTICE TO ANY
PRODUCTS HEREI N TO IMPROVE RELIABILITY, FUNCTIO N OR DESIGN. FAIRCH IL D DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER IT S PATENT RIGHTS, NOR THE RIGHTS OF OTHE RS.

LIFE SUPPORT POL I CY

FAIRCHILD’S PR ODUCTS ARE NOT AUTH ORIZED FOR USE AS C RITICAL COMPONENT S IN LIFE SUPPORT DE VICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein :

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with

2. A critical component in any component of a life support
device or sy stem whose fai lure to perform can be
reasonably expec ted to cause the failur e of the life support
device or system, or to affect its safety or effec t iv ene ss .

instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

www.fairchildsemi.com

11/15/02 0.0m 001

 2002 Fairchild Semiconductor Corporation

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