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E98920A8X-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Operating Conditions (Ta=25 °C)
Control voltage
Vctl (H)–Vctl (L): 2.5 to 5 V
Description
The CXG1068N is a high power antenna switch
MMIC for use in Dualband GSM handsets.
One antenna can be routed to either of the 2Tx or
2Rx ports. This IC is designed using the Sony’s
GaAs J-FET process which enable the CXG1068N
to be operated with low voltage.
Features
• Low control voltage
• Low insertion loss : 0.5 dB (Typ.) @900 MHz
0.65 dB (Typ.) @1.8 GHz
• Small package :
SSOP-20pin (Pin interval of 0.5 mm pitch)
• High power handling :
P1dB : 38 dBm (Typ.) 0/5 V control
• Harmonics :
–31 dBm (Max.) Pin=35 dBm, 0/5 V control
Applications
• Dualband GSM 900/GSM 1800 or GSM 900/GSM
1900 handsets.
• Dualmode GSM/DECT handsets.
Structure
GaAs J-FET MMIC
SP4T Antenna Switch for GSM Dual band
20 pin SSOP (Plastic)
CXG1068N
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
For the availability of this product, please contact the sales office.
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CXG1068N
Truth Table
ON Pass
Ant.-Tx1
Ant.-Tx2
Ant.-Rx1
Ant.-Rx2
CTL 1
H
L
L
L
CTL 2
L
H
L
L
CTL 3
L
L
H
L
CTL 3
H
H
L
H
CTL 4
L
L
L
H
CTL 4
H
H
H
L
Electrical Characteristics 1 (Ta=25 °C)
Insertion loss
Isolation
VSWR
Harmonics
1dB compression
Input power
Switching speed TSW
Control current
Bias current
Symbol
IL
ISO
VSWR
2fo
3fo
P1dB
TSW
Ictl
IDD
Port
Ant-Tx1, Tx2
Ant-Rx1, Rx2
Ant-Tx1, Tx2
Ant-Rx1, Rx2
Ant-Tx1, Tx2
Ant-Tx1, Tx2
Condition
∗
1
∗
2
∗
3
∗
4
∗
1, ∗3
∗
2, ∗4
∗
1, ∗3
∗
2, ∗4
∗
1
∗
2
∗
1
∗
2
Min. Typ. Max. Unit
0.5 0.7 dB
0.65 0.85 dB
0.6 0.8 dB
0.85 1.05 dB
20 24 dB
17 20 dB
25 30 dB
20 25 dB
1.2 1.4
–31 dBm
–31 dBm
35 38 dBm
34 37 dBm
100 500 ns
150 300 µA
60 120 µA
∗
1 : Pin=34.5 dBm, 880 to 915 MHz, VDD=5 V, 0/5 V Control
∗
2 : Pin=32 dBm, 1710 to 1785 MHz, VDD=5 V, 0/5 V Control
∗
3 : Pin=10 dBm, 925 to 960 MHz, VDD=3 V, 0/3 V Control
∗
4 : Pin=10 dBm, 1805 to 1880 MHz, VDD=3 V, 0/3 V Control
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CXG1068N
Electrical Characteristics 2 (Ta=–35 to +85 °C)
Insertion loss
Isolation
VSWR
Harmonics
1dB compression
Input power
Switching speed TSW
Control current
Bias current
Symbol
IL
ISO
VSWR
2fo
3fo
P1dB
TSW
Ictl
IDD
Port
Ant-Tx1, Tx2
Ant-Rx1, Rx2
Ant-Tx1, Tx2
Ant-Rx1, Rx2
Ant-Tx1, Tx2
Ant-Tx1, Tx2
Condition
∗
1
∗
2
∗
3
∗
4
∗
1, ∗3
∗
2, ∗4
∗
1, ∗3
∗
2, ∗4
∗
1
∗
2
∗
1
∗
2
Min. Typ. Max. Unit
0.5 0.9 dB
0.65 1.05 dB
0.6 1.0 dB
0.85 1.25 dB
20 24 dB
17 20 dB
25 30 dB
20 25 dB
1.2 1.4
–30 dBm
–30 dBm
35 38 dBm
34 37 dBm
100 500 ns
150 350 µA
60 150 µA
∗
1 : Pin=34.5 dBm, 880 to 915 MHz, VDD=5 V, 0/5 V Control
∗
2 : Pin=32 dBm, 1710 to 1785 MHz, VDD=5 V, 0/5 V Control
∗
3 : Pin=10 dBm, 925 to 960 MHz, VDD=3 V, 0/3 V Control
∗
4 : Pin=10 dBm, 1805 to 1880 MHz, VDD=3 V, 0/3 V Control
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CXG1068N
Package Outline/Pin Configuration
GND Tx1
GND GND
Ant Tx2
GND GND
VDD Rx1
GND GND
CTL1 Rx2
CTL2 GND
CTL3 CTL3
CTL4 CTL4
20 1
20pin SSOP Package
Block Diagram
Tx1Ant
CTL1
ON
Tx2
CTL2
ON
Rx1
CTL3
CTL3
ON
Rx2
CTL4
CTL4
ON
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CXG1068N
Recommended Circuit
56kΩ
L1
CRF (100pF)
56kΩ
L1
CRF (100pF)
Tx1
56kΩ
L1
CRF (100pF)
Tx2
L1
CRF (100pF)
Rx1
L1
Rx2
Ant
Cbypass
(100pF)
VDD
CTL1
RCTL (1kΩ)
Cbypass (100pF)
CTL2
RCTL (1kΩ)
Cbypass (100pF)
CTL3
RCTL (1kΩ)
Cbypass (100pF)
CTL3
RCTL (1kΩ)
Cbypass (100pF)
CTL4
RCTL (1kΩ)
Cbypass (100pF)
12
13
14
15
16
17
18
19
20
11
CXG1068N
CTL4
RCTL (1kΩ)
Cbypass (100pF)
1
2
3
4
5
6
7
8
9
10
∗ Recommended to use DC blocking capacitors (CRF) and bypass capacitors (Cbypass).
Rctl : This resistor is used to give improved ESD performance. 1 kΩ is recommended.
L1 : This inductor is used to give improved ESD performance.
Absolute Maximum Ratings (Ta=25 °C)
• Control voltage 7 V
• Operating temperature Topr –35 to +85 °C
• Storage temperature Tstg –65 to +150 °C
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SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER/PALLADIUM
COPPER ALLOY
PACKAGE STRUCTURE
PLATING
0.1g
SSOP-20P-L03
SSOP020-P-0044
20PIN SSOP(PLASTIC)
NOTE: Dimension “∗” does not include mold protrusion.
A
20
11
10
0.5
1
0.1
M
S A
A
1.25MAX
S
B
0° to 10°
(0.5)
0.6 ± 0.15
0.25
0.1 ± 0.1
DETAIL
A
0.1
0.1
∗5.0 ± 0.05
∗4.4 ± 0.05
6.4 ± 0.2
(0.15)
0.17 ± 0.03
(0.2)
b = 0.22 ± 0.05
DETAIL B : SOLDER
0.15 – 0.01
b = 0.2 ± 0.03
DETAIL B : PALLADIUM
0.1
S
b
+ 0.03
Package Outline Unit : mm
CXG1068N
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