Datasheet CXD3521GG Datasheet (Sony)

Interface and Driver IC for LCD

Description

The CXD3521GG is an interface and driver IC for

the color LCD module ACX704AKM/BKM.

Features

• Generates the color LCD module ACX70 4AKM/BKM

drive pulse.

• Supports standby mode

• Built-in 9-channel reference voltage driver

• Built-in common voltage driver

Applications

PDA, compact LCD monitor, etc.

Structure

Silicon gate CMOS IC

CXD3521GG

128 pin TFBGA (Plastic)

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage 1 VDD1 VSS – 0.3 to +4.6 V

• Supply voltage 2 VDD2 VSS – 0.3 to +6.0 V

• Input voltage VI VSS – 0.3 to VDD + 0.3 V

• Output voltage VO VSS – 0.3 to VDD + 0.3 V

• Storage temperature

Tstg –55 to +125 °C

Recommended Operating Conditions

• Supply voltage 1 VDD1 3.0 to 3.6 V

• Supply voltage 2 VDD2 4.7 to 5.3 V

• Operating temperature

Topr –25 to +75 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E01408-PS

Block Diagram

CXD3521GG

V

DD1

(3.3V)

V

SS1

(GND)

Hsync/DENB

V

DD2

(5.0V)

SS1

(GND)

V

R3 R2 R1 R0

G3 G2 G1 G0

B3 B2 B1 B0

MCK

PCI

SLIN

TESTP

TEST

Vsync

CLR

C10, J6, L11, M1

B11, G9, L2

H12 H11 H10 H9

J12 J11 J10

J9

K12 K11 K10 K9

L12 G11 G12 E10 M12 A12 G11

F9

B2, D2, D7

B4, D3, F4

Serial/Parallel Transform Block

Timing Generator Block

Power CTR.

H Counter

H Timing Pulse GEN.

V Counter

V Timing Pulse GEN.

M11, L10, M10, M9

J7, M6, L6, K6

F12, F11, E12, E11

D10, A9, B9, C9

L9, M8, L8, K8 M5, L5, K5, J5

B12, C12, D12, A11

D9, A8, B8, C8

J8, M7, L7, K7

M4, L4, M3, L3

C11, D11, A10, B10

D8, A7, B7, C7

E9

Delay

H4, H3 H2, H1

K2, K1

J2, J1

G4, G3, G2, G1

M2, L1

J4, J3

K4, K3

F10

F3

R31, R21, R11, R01 XR31, XR21, XR11, XR01 R32, R22, R12, R02 XR32, XR22, XR12, XR02 G31, G21, G11, G01 XG31, XG21, XG11, XG01 G32, G22, G12, G02 XG32, XG22, XG12, XG02 B31, B21, B11, B01 XB31, XB21, XB11, XB01 B32, B22, B12, B02 XB32, XB22, XB12, XB02

PCO HST1, XHST1 HST2, XHST2

HCK1, XHCK1 HCK2, XHCK2

OE1, XOE1, OE2, XOE2

VST, XVST VCK, XVCK ENB, XENB

TESTO

V0

VH1

VL1

VH2

VL2

VRFSTB

VH6

VL6

VH8

VL8

F2 F1

E1 E3

A1

C2 B1

A2 C4

Resistor Array Block

Reference Voltage Driver Block

– 2 –

E2

E4

D1

C1

D4

C3

B3

D5

A3

V1

V2

V3

V4

V5

V6

V7

V8

VCOM

Pin Configuration (Top View)

CXD3521GG

1

234567

8

9

10

11

12

A

VRFSTB

VH8

VCOM

TESTL1

TESTL7

TESTL5

XB22

XG22

XR22

B12

G02

TEST1

B

VL6

DD2

V

V7

V

SS2

TESTL8

TESTL4

XB12

XG12

XR12

B02

SS1

V

G32

C

V4

VH6

V6

VL8

TESTL2

TESTL6

XB02

XG02

XR02

DD1

V

B32

G22

D

V3

DD2

V

SS2

V5

V8

TESTL3

V

DD2

XB32

XG32

XR32

B22

G12

E

VH2

V1

VL2

V2

PCO

SLIN

R02

R12

F

VL1

VH1

V0

SS2

V

CLR

TESTO

R22

R32

G

XOE2

OE2

XOE1

OE1

SS1

V

PCI

Vsync

Hsync/ DENB

H

XHST2

HST2

XHST1

HST1

R0

R1

R2

R3

J

XHCK2

HCK2

XVCK

VCK

XG01

DD1

V

XR31

B31

G0

G1

G2

G3

K

XHCK1

HCK1

XENB

ENB

XG11

XR01

B01

G01

B0

B1

B2

B3

L

XVST

SS1

V

XB01

XB21

XG21

XR11

B11

G11

G31

R21

DD1

V

MCK

M

DD1

V

VST

XB11

XB31

XG31

XR21

B21

G21

R01

R11

R31

TESTP

– 3 –

Pin Description

CXD3521GG

Pin No.

B11

G9

L2

C10

J6

L11

M1

F9 H12 H11 H10

H9 J12 J11 J10

J9

SS1

V VSS1 VSS1 VDD1 VDD1 VDD1 VDD1 CLR R3 R2 R1 R0 G3 G2 G1 G0

Symbol

I/O

—

GND (Logic)

—

GND (Logic)

—

GND (Logic)

—

Power supply (3.3V)

—

Power supply (3.3V)

—

Power supply (3.3V)

—

Power supply (3.3V)

I

System reset (Cleared at 0V)

I

Red signal input (MSB)

I

Red signal input

I

Red signal input

I

Red signal input (LSB)

I

Green signal input (MSB)

I

Green signal input

I

Green signal input

I

Green signal input (LSB)

Description

Input pin for open status

— — — — — — —

∗

UP

— — — — — — —

— K12 K11 K10

K9 G12 G11

L12

G10

E10 F10

E9 M11

L10

M10

M9

L9

M8

B3 B2 B1 B0 Hsync/DENB Vsync MCK PCI SLIN TESTO PCO R31 R21 R11 R01 G31 G21

I

Blue signal input (MSB)

I

Blue signal input

I

Blue signal input

I

Blue pulse input (LSB)

I

Hsync pulse input/Data enable signal input

I

Vsync pulse input

I

Dot clock input

I

Power control signal input

I

Sync input signal mode selector switch

O

Test output (Leave it open.)

O

Power control signal output

O

Red signal output

O

Red signal output

O

Red signal output

O

Red signal output

O

Green signal output

O

Green signal output

— — — — — — — — — — — — — — — — —

L8

G11

K8

G01

J8

B31

∗

UP: Pull-up (typ. 160kΩ)

O

Green signal output

O

Green signal output

O

Blue signal output

— — —

– 4 –

CXD3521GG

Pin No.

M7

L7

K7

J7

M6

L6

K6

M5

L5

K5

J5

M4

L4

M3

L3

M12

A12

Symbol I/O Description

B21 B11 B01 XR31 XR21 XR11 XR01 XG31 XG21 XG11 XG01 XB31 XB21 XB11 XB01 TESTP TEST

O

Blue signal output

O

Blue signal output

O

Blue signal output

O

R31 signal inversion output

O

R21 signal inversion output

O

R11 signal inversion output

O

R01 signal inversion output

O

G31 signal inversion output

O

G21 signal inversion output

O

G11 signal inversion output

O

G01 signal inversion output

O

B31 signal inversion output

O

B21 signal inversion output

O

B11 signal inversion output

O

B01 signal inversion output

I

Test input (Connect to GND.)

I

Test input (Connect to GND.)

Input pin for open status

— — — — — — — — — — — — — — — —

∗

DWN

M2

L1 K4 K3

J4

J3 K2 K1

J2

J1 H4 H3 H2 H1 G4 G3 G2

VST XVST ENB XENB VCK XVCK HCK1 XHCK1 HCK2 XHCK2 HST1 XHST1 HST2 XHST2 OE1 XOE1 OE2

O

VST pulse output

O

VST pulse inversion output

O

ENB pulse output

O

ENB pulse inversion output

O

VCK pulse output

O

VCK pulse inversion output

O

HCK1 pulse output

O

HCK1 pulse inversion output

O

HCK2 pulse output

O

HCK2 pulse inversion output

O

HST1 pulse output

O

HST1 pulse inversion output

O

HST2 pulse output

O

HST2 pulse inversion output

O

OE1 pulse output

O

OE1 pulse inversion output

O

OE2 pulse output

— — — — — — — — — — — — — — — — —

G1

XOE2

D8

XB32

A7

XB22

∗

DWN: Pull-down (typ. 180kΩ)

O O O

OE2 pulse inversion output B32 signal inversion output B22 signal inversion output

– 5 –

— — —

CXD3521GG

Pin No.

B7 C7 D9 A8 B8 C8

D10

A9 B9 C9

C11 D11

A10 B10 B12

C12

Symbol I/O Description

XB12 XB02 XG32 XG22 XG12 XG02 XR32 XR22 XR12 XR02 B32 B22 B12 B02 G32 G22

O

B12 signal inversion output

O

B02 signal inversion output

O

G32 signal inversion output

O

G22 signal inversion output

O

G12 signal inversion output

O

G02 signal inversion output

O

R32 signal inversion output

O

R22 signal inversion output

O

R12 signal inversion output

O

R02 signal inversion output

O

Blue signal output

O

Blue signal output

O

Blue signal output

O

Blue signal output

O

Green signal output

O

Green signal output

Input pin for open status

— — — — — — — — — — — — — — — —

D12

A11 F12 F11 E12 E11

B4 D3

F4 B2 D2 D7 A4 C5 D6 B6 A6

G12 G02 R32 R22 R12 R02 VSS2 VSS2 VSS2 VDD2 VDD2 VDD2 TESTL1 TESTL2 TESTL3 TESTL4 TESTL5

O

Green signal output

O

Green signal output

O

Red signal output

O

Red signal output

O

Red signal output

O

Red signal output

—

GND (Analog)

—

GND (Analog)

—

GND (Analog)

—

Power supply (5.0V)

—

Power supply (5.0V)

—

Power supply (5.0V)

O

Test output (Leave it open.)

O

Test output (Leave it open.)

I

Test input (Connect to GND.)

I

Test input (Connect to GND.)

O

Test output (Leave it open.)

— — — — — — — — — — — — — —

DWN

— —

∗

A5

TESTL6

C6

TESTL7

B5

TESTL8

F3

V0

∗

DWN: Pull-down (typ. 180kΩ)

I I I

O

Test input (Connect to GND.) Test input (Connect to GND.) Test input (Connect to GND.) V0 output

– 6 –

— — — —

CXD3521GG

Pin No.

E2 E4 D1 C1 D4 C3 B3 D5 A3 A1

F2

F1 E1 E3 C2 B1

Symbol I/O Description

V1 V2 V3 V4 V5 V6 V7 V8 VCOM VRFSTB VH1 VL1 VH2 VL2 VH6 VL6

O

V1 output

O

V2 output

O

V3 output

O

V4 output

O

V5 output

O

V6 output

O

V7 output

O

V8 output

O

VCOM output

I

Reference voltage driver on/off selector switch

I

VH1 input

I

VL1 input

I

VH2 input

I

VL2 input

I

VH6 input

I

VL6 input

Input pin for open status

— — — — — — — — —

∗

DWN

— — — — — —

A2

VH8

C4

VL8

∗

DWN: Pull-down (typ. 180kΩ)

I I

VH8 input VL8 input

— —

– 7 –

CXD3521GG

Electrical Characteristics (Serial/parallel conversion block, timing generator block)

DC Characteristics (VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)

Item Symbol UnitMin.

Supply voltage Current

consumption

Input voltage 1

Input voltage 2

Input current 1

Input current 2

Input current 3

VDD1

IDD1

VIH1 VIL1

Vt+

Vt–

| IIL1 |

| IIH1 | | IIL2 |

| IIH2 | | IIL3 | | IIH3 |

VDD1

MCK, VRFSTB, TESTL1, TESTL2, TESTL3, TESTL4

All input pins excluding MCK, VRFSTB, TESTL1, TESTL2, TESTL3, TESTL4

R0, R1, R2, R3, G0, G1, G2, G3, B0, B1, B2, B3, Hsync/DENB, Vsync, MCK, PCI

CLR

TEST, TESTP, SLIN

—

No load, Ta = 25°C VDD1 = 3.3V, MCK: 5.62MHz

CMOS input cell

CMOS Schmitt trigger input cell

VI = 0V

VI = VDD VI = 0V

VI = VDD VI = 0V VI = VDD

R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31,

VOL1

XR02, XR12, XR22, XR32,

IOL1 = 4.0mA

G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31,

Output voltage 1

XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31,

VOH1

XB02, XB12, XB22, XB32,

IOH1 = –4.0mA VST, XVST, ENB, XENB, OE1, XOE1, OE2, XOE2, TESTO

3.0

—

0.7VDD1 —

—

0.15VDD1

—

10

— — 10

—

VDD – 0.8

Typ.

3.3

1.5

— —

—

— —

— — —

—

Max.ConditionsApplicable pins

3.6

—

0.2VDD1

0.75VDD1

—

1.0

100

3.0

100

0.2

—

V

mA

V

µA

V

Output voltage 2

Output voltage 3

VOL2 VOH2 VOL3

VOH3

HST1, XHST1, HST2, XHST2, VCK, XVCK, PCO

HCK1, XHCK1, HCK2, XHCK2

IOL2 = 6.0mA IOH2 = –6.0mA IOL3 = 10.0mA

IOH3 = –10.0mA

– 8 –

—

VDD – 0.8

—

VDD – 0.8

— — —

—

0.2 V

—

0.4 V

—

CXD3521GG

AC Characteristics (VDD = 3.0 to 3.6V, Ta = –25 to +75°C)

1

—

∗

—

15∗

2

ns

Item Symbol UnitMin. Typ. Max.Conditions

HCK/HST time difference

∆t

HST-HCKU

∆t

HST-HCKD

Applicable pins

HCK1, HCK2, XHCK1, XHCK2, HST1, HST2, XHST1, XHST2

R01, R11, R21, R31, R02, R12, R22, R32,

Data output rise time

tRD

XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32,

GND – VDD (0 – 90%)

—

35

G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31,

ns

XG02, XG12, XG22, XG32,

Data output fall time

tFD

B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31,

VDD – GND (100 – 10%)

—

35

XB02, XB12, XB22, XB32

Horizontal pulse output rise time

Horizontal pulse output fall time

Vertical pulse output rise time

Vertical pulse output fall time

tRHP tFHP tRVP tFVP

HCK1, HCK2, XHCK1, XHCK2, HST1, HST2, XHST1, XHST2

VCK, XVCK, VST, XVST, ENB, XENB, OE1, OE2, XOE1, XOE2, PCO, TESTO

GND – VDD (0 – 90%)

VDD – GND (100 – 10%)

GND – VDD (0 – 90%)

VDD – GND (100 – 10%)

—

35

50

HCK1, HCK2, XHCK1, XHCK2, R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31,

XR02, XR12, XR22, XR32, HCK1, HCK2, XHCK1, XHCK2/ DATA setup time

tSTP

G01, G11, G21, G31,

G02, G12, G22, G32,

XG01, XG11, XG21, XG31,

3

∗

35

55

100

XG02, XG12, XG22, XG32,

B01, B11, B21, B31,

B02, B12, B22, B32,

XB01, XB11, XB21, XB31,

XB02, XB12, XB22, XB32 HCK, VCK duty

1

∗

Load capacitance CL of each output pin is shown below.

dHCK dVCK

HCK1, HCK2, XHCK1,

XHCK2, VCK, XVCK

4

∗

48

50

52

• R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, OE1, XOE1, OE2, XOE2, TESTO, ENB, XENB : CL = 70pF

• HCK1, HCK2, XHCK1, XHCK2 : CL = 180pF

• VCK, XVCK : CL = 150pF

• HST1, HST2, XHST1, XHST2, VST, XVST, PCO : CL = 100pF

2

∗

Absolute value of the time difference of the change point at HST1, XHST1, HCK1 and XHCK1 (50%) is within 15ns. Similarly, absolute value of the time difference of the change point at HST2, XHST2, HCK2 and XHCK2 (50%) is within 15ns.

3

∗

tSTP: tST1D, tST1U, tST2D, tST2U

4

∗

dHCK = (tHH/(tHH + tHL)) × 100, dVCK = (tVH/(tVH + tVL)) × 100

– 9 –

ns

%

Timing Definition

Horizontal System

CXD3521GG

t

HH

HL

V

DD1

HCK1

XHCK1

HCK2

XHCK2

50%

∆t

H

50%

GND

DD1

V

50%

GND

∆t

H

V

DD1

50%

GND

DD1

V

50%

GND

H

∆t

H

HST1 (HST2)

XHST1 (XHST2)

HCK1 (HCK2)

XHCK1 (XHCK2)

50%

∆t

HST-HCKU

50%

– 10 –

∆t

HST-HCKD

DD1

V

GND V

DD1

GND

V

DD1

GND

V

DD1

GND

Vertical System

CXD3521GG

t

VH

VL

V

DD1

XVCK

DAT A

HCK1

XHCK1

VCK

50%

GND V

DD1

50%

GND

V

∆t

V

VDD1

50%

GND V

DD1

50% 50%

GND

HCK2

XHCK2

DATA

tST1D

tSTX1U

50%

tST2D

tSTX2U

– 11 –

50%

50% 50%

tST1U

tSTX1D

tST2U

tSTX2D

VDD1

GND

DD1

V

GND

V

DD1

GND

CXD3521GG

PCI, PCO

These pins control to turn power on/off of the ACX704AKM/BKM when the LCD is turned on/off. Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM/BKM.

Power-on Sequence

• Raise and fall VDD1 and VDD2 simultaneously (within 10ms)

1

• Input the input signal

∗

for 1 field (Min.), and then raise PCI.

• After PCI becomes high, latch is performed twice at Vsync. When both of them are high, PCO output is changed from low to high. (Turn the power on of the ACX704AKM/BKM at this timing.) Also, effective screen is displayed after two fields of entire white display from this timing.

±10ms

V

DD1

V

DD2

CLR

DD1

0

DD2

V 0

V

DD1

0

PCI

PCO

Pulse

DATA (out)

Vsync

DENB

MCK Hsync DATA (in)

1

∗

Hsync, Vsync, DENB, MCK, DATA

2

∗

HST1, XHST1, HST2, XHST2, HCK1, XHCK1, HCK2, XHCK2, VST, XVST, VCK, XVCK, ENB, XENB,

Low

∗

2

Low

1 field (min.) 1 field (min.) 2 fields

High21

High

Active

White Data Valid

Active

OE1, XOE1, OE2, XOE2, TESTO, (FRP)

– 12 –

Power-off Sequence (Standby)

CXD3521GG

• When LCD is off, LCD is turned off after entire white display.

PCO

V

DATA

Pulse

Vsync

DENB

PCI

DD1

DD2

High

High Low

Valid

∗

1

Active

All Data: High (XDATA: Low)

Low

Standby Mode

Low

±10ms

V

DD1

0

V

DD2

0

3 fields 10 fields

MCK Hsync DATA (in)

1

∗

HST1, XHST1, HST2, XHST2, HCK1, XHCK1, HCK2, XHCK2, VST, XVST, VCK, XVCK, ENB, XENB,

Active

Low

OE1, XOE1, OE2, XOE2, TESTO, (FRP)

SLIN

This is a selector switch for sync input signal mode.

SLIN: Low → Hsync + Vsync Mode. SLIN: High → DENB ONLY Mode. (Vsync is invalid.)

– 13 –

Horizontal Direction Input Signal Timing Chart

MCK

Hsync

310

1

∗

315 320 325 330

335 340 345 350

4 dots (min.)

05

352 dots

DENB

Hsync

– 14 –

DENB

DATA

MCK

DATA

∗

1

307 308 309 311 312 313 314 316 317 318 319 320310 315

thss

1

∗

1

∗

1

∗

Input either Hsync + Vsync or DENB as sync input signal.

thsw

16 dots 16 dots

32 dots

tdes

1 2 320

tdh

tds

tdeh

Input Signal AC Characteristics (VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)

Item Symbol Min. Typ. Max. MCK frequency MCK low, high pulse width DATA setup time DATA hold time DENB setup time DENB hold time Hsync setup time Hsync low pulse width

ftch

tch, tcl tds tdh tdes tdeh thss thsw

1 2 3 5 6 7 8 10 1149

tch tcl

tclk

3MHz

10ns 15ns 10ns 15ns 10ns 4tclk

—

5.58MHz

0.5

tclk

— — — — — —

8MHz

— — — — — —

tclk

16

CXD3521GG

Vertical Direction Input Signal Timing Chart

235

(1)

tvhde

– 15 –

Hsync

Vsync

DENB

Hsync

Vsync

230 245

∗

1

∗

1

∗1

240

264 lines

250 255 260 0 5 10 15

10 lines 14 lines

(2) (14) (15)

DENB

DATA

tvsw

∗1

1st Line

∗1

Input either Hsync + Vsync or DENB as sync input signal.

Input Signal AC Characteristics (VDD1 = 3.0 to 3.6V, Ta = –25 to +75°C)

Item Symbol Min. Typ. Max. Hsync falling edge

→ Vsync falling edge Vsync low pulse width

tvhde tvsw

3

tclk

2 lines

— —

352tclk

14 lines

CXD3521GG

Horizontal Direction Timing Chart

MCK

Hsync

DENB

DATA

InputOutput

– 16 –

R/G/B 01 to 31

R/G/B 02 to 32

HST1

XHST1

HCK1

XHCK1

HST2

XHST2

HCK2

XHCK2

XOE1

XOE2

XENB

270 272 274 278 282 284 288276 280 286 290 292 294 298 300 302 304 308296 306 314312 318

271 273 277 281 283 287 297 301 303 307 313311 317

OE1

OE2

ENB

VST

280 290 300 310 320

318

317

316

320

319

285

310 316

309

320

315 319269 275 279 291289 293 295 299 305

320 0

304

330 340 0 10 20

16 dots

32 dots

328 340

16 dots

4 dots

342

348344

4 dots

1

23456789

346

0

350

352 dots

24 8 1214 18620222410 16

1 3 7 1113 171921239155

XVST

VCK

XVCK

FRP

334

CXD3521GG

Vertical Direction Timing Chart

240 245

Hsync

Vsync

DENB

InputOutput

VST

XVST

VCK

264 lines

250 255 260 0 5 10 15 20

10 lines

14 lines

– 17 –

XVCK

ENB

XENB

OE1

XOE1

OE2

XOE2

FRP (O)

FRP (E)

1

∗

1

∗

CXD3521GG

1

∗

FRP (O): FRP pulse at odd field. FRP (E): FRP pulse at even field.

Reference Voltage Driver Block

CXD3521GG

Block Diagram

V

DD2

(5.0V)

V

DD2

V

SS2

Resistor array

VH0 VL0 VH1 VL1 VH2 VL2 VH3 VL3 VH4 VL4 VH5 VL5 VH6 VL6 VH7 VL7 VH8 VL8

V0

V1

V2

V3

V4

V5

V6

V7

V8

VCOM

VRFSTB

FRP

∗

1

V

SS2

Level Shift Level Shift

∗

1

Internal pulse of the logic block

Electrical Characteristics (Reference voltage driver block)

Resistor array output voltage (VDD1 = 3.3V, VDD2 = 5.0V, Ta = 25°C)

Item Min. Typ. Max. Unit Item Min. Typ. Max. Unit VH0 VH1 VH2 VH3 VH4 VH5 VH6

— — — — — — —

4.800

3.900

3.325

2.950

2.600

2.250

1.950

— — — — — — —

VL0 VL1 VL2 VL3

V

VL4 VL5 VL6

— — — — — — —

0.200

1.100

1.675

2.050

2.400

2.750

3.050

— — — — — — —

V

VH7 VH8

— —

1.500

0.500

— —

– 18 –

VL7 VL8

— —

3.500

4.500

— —

CXD3521GG

AC, DC Characteristics (VDD1 = 3.3V, VDD2 = 5.0V, Ta = –25 to +75°C)

Item Symbol

Supply voltage Current consumption VH, VL input current high

VH, VL input current low Voltage gain Output voltage high Output voltage low COM output voltage high COM output voltage low Offset voltage

Load regulation

Output impedance Settling time 1 Settling time 2 Settling time 3 Settling time 4

VDD2 IDD2 IIH

IIL AV VOH VOL VCOH VCOL VOFF

∆VO

RIMP

ts1 ts2 ts3 ts4

Conditions

—

Input voltage = 2.5V, During no load

Input voltage = 4.8V Input voltage = 0.2V Input voltage = 0.2 to 4.8V ISOURCE = 10mA ISINK = 10mA ISOURCE = 10mA ISINK = 10mA Rs = 10kΩ Input voltage = 0.2 to 4.8V

ISOURCE = 10mA ISINK = 10mA

V0 to V8 Measurement circuit 1 Measurement circuit 1 Measurement circuit 2 Measurement circuit 2

Min.

4.7 —

–0.15 –0.15

0.985

VDD2 – 1.0

—

VDD2 – 0.1

— —

—

— — — — —

Typ.

5.0

3.4 —

— — — — — — —

±5

15 — — — —

Max.

5.3

6.0

0.15

0.15 — —

GND + 1.0

—

GND + 0.1

20

±10

— 10 10

6 6

Unit

V

mA

µA µA

V/V

V V V V

mV

Ω

µs µs µs µs

– 19 –

Measurement Circuit

Measurement circuit 1

CXD3521GG

VH

4.8V

0.2V VL

Measurement circuit 2

5.0V

0V

FRP (internal pulse)

Output (V0 to V8)

50%

ts1

15Ω

VCOM

90%

V0 to V8

30nF

Measuring point

30nF

Measuring point

50%

ts2

10%

Output (VCOM)

10%

ts3

VRFSTB

This is a selector switch for reference voltage driver output on/off.

VRFSTB: Low → V0 to V8 and VCOM are GND level. VRFSTB: High → V0 to V8 and VCOM are active.

90%

ts4

– 20 –

Application Circuit

CXD3521GG

1

∗

VDD2

To ACX704AKM/BKM

A1 B1

B2 C1 C2 C3 D1 D2 D3 D4

E1

E2

E3

E4

F1

F2

F3

F4 G1 G2 G3 G4 H1 H2 H3 H4

J1

J2

J3

J4

K1

K2

VRFSTB VL7 V

DD2

V4 VH7 V6 V3 V

DD2

V

SS2

V5 VH2 V1 VL2 V2 VL0 VH0 V0

SS2

V XOE2 OE2 XOE1 OE1 XHST2 HST2 XHST1 HST1 XHCK2 HCK2 XVCK VCK XHCK1 HCK1

To ACX704AKM/BKM

A2 A3 B3 C4 D5 A4 C5 B4 B5 B6 D6 A5 C6 A6 D7 C7 B7 A7 D8 C8 B8 A8 D9 C9 B9 A9

V7

V8

VH8

VCOM

VL8

TESTL1

TESTL2

SS2

V

TESTL8

TESTL4

TESTL3

TESTL6

TESTL7

DD2

V

TESTL5

XB02

XB12

XB22

XB32

XG02

XG12

XG22

XG32

XR02

XR12

D10 B10 A10 D11 C11 C10

B02

B12

XR32

B22

XR22

B32

DD1

V

TEST

V

G02 G12 G22 G32 R02 R12 R22 R32

PCO

SLIN

CLR

TESTO

V

PCI

Vsync

Hsync/DENB

MCK V

V

DD1

A12 B11

SS1

A11 D12 C12 B12 E11 E12 F11 F12

E9

E10

F9

F10

G9

SS1

G10 G11 G12

H9

R0

H10

R1

H11

R2

H12

R3

J9

G0

J10

G1

J11

G2

J12

G3

K9

B0

K10

B1

K11

B2

K12

B3

L12 L11

DD1

To DC-DC Converter

Input To ACX704AKM/BKM

V

DD1

DD1VSS1

V

VST

XVST

ENB

XENB

XB01

XB11

XB21

XB31

XG01

XG11

XG21

XG31

M1

L2 M2 L1 K4 K3 L3 M3 L4 M4 J5 K5 L5 M5 K6 L6 M6 J7 J6 K7 L7 M7 J8 K8 L8 M8 L9 M9

∗1

Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM/BKM.

XR01

To ACX704AKM/BKM

XR11

XR21

XR31

DD1

V

B01

B11

B21

B31

G01

G11

G21

G31

R01

R11

R21

TESTP

R31

M10 L10 M11 M12

V

DD1

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 21 –

Package Outline Unit: mm

CXD3521GG

128PIN TFBGA (PLASTIC)

11.0

0.3

11.0

A

S

B S

0.3

x4

0.20

0.2

S

10.6 ± 0.1

S

0.1

S

0.8

1.1

A

1.2 MAX

0.4 ± 0.05

M L K J H

1.1

B

G

F E D

C

0.8

B A

SONY CODE EIAJ CODE JEDEC CODE

162738495101211

128 - φ 0.5 ± 0.05

TFBGA-128P-061

P-TFBGA128-11x11-0.8

φ 0.08

PACKAGE STRUCTURE

PACKAGE MATERIAL TERMINAL TREA TMENT

TERMINAL MATERIAL PACKAGE MASS

– 22 –

M

S

A

B

ORGANIC SUBSTRATE

SOLDER

0.22g

Sony Corporation