BECKHOFF EtherCAT IPCore Section III User Manual

Hardware Data Sheet Section III Addendum ET1810 / ET1811 / ET1812 and ET1815 / ET1816
Slave Controller
IP Core for Altera® and Xilinx® FPGAs
Section II – Register Description (Online at http://www.beckhoff.com)
Section III – Hardware Description (Online at http://www.beckhoff.com)

Section III – Addendum

Design Flow Compatibility, FPGA Device Support, Known issues
Version 2.1 Date: 2015-05-12
DOCUMENT ORGANIZATION
Version
Comment
1.0
Initial release
1.1
Update to EtherCAT IP Core V3.0.2/V3.00c
1.2
Update to EtherCAT IP Core V2.4.3/V2.04d
1.3
Update to Altera Quartus 13.0 SP1 and Xilinx Vivado 2013.2
1.4
Update to Altera Quartus 13.1, Xilinx Vivado 2013.3, and ISE14.7
1.5
Update to EtherCAT IP Core V3.0.5/V3.00f  Update to Xilinx Vivado 2013.4, editorial changes
1.6
Update to EtherCAT IP Core V3.0.6/V3.00g  Update to Xilinx Vivado 2014.1
1.7
Update to Altera Quartus 14.0, Xilinx Vivado 2014.2  Added Altera MAX10, Xilinx Kintex UltraScale, and Virtex UltraScale
1.8
Update to EtherCAT IP Core V3.0.9/V3.00j  Update to Xilinx Vivado 2014.3  Added known designflow issues chapters
1.9
Update to EtherCAT IP Core V3.0.9 Patch 1/V3.00j Patch 1
2.0
Update to EtherCAT IP Core V2.4.4/V2.04e and V3.0.10/V3.00k  Update to Altera Quartus 14.1, Xilinx Vivado 2014.4  Added Altera Arria 10
2.1
Update to Altera Quartus 15.0, Xilinx Vivado 2015.1
Trademarks
Beckhoff®, TwinCAT®, EtherCAT®, Safety over EtherCAT®, TwinSAFE® and XFC® are registered trademarks of and licensed by Beckhoff Automation GmbH & Co. KG. Other designations used in this publication may be trademarks whose use by third parties for their own purposes could violate the rights of the owners.
Patent Pending
The EtherCAT Technology is covered, including but not limited to the following German patent applications and patents: DE10304637, DE102004044764, DE102005009224, DE102007017835 with corresponding applications or registrations in various other countries.
Disclaimer
The documentation has been prepared with care. The products described are, however, constantly under development. For that reason the documentation is not in every case checked for consistency with performance data, standards or other characteristics. In the event that it contains technical or editorial errors, we retain the right to make alterations at any time and without warning. No claims for the modification of products that have already been supplied may be made on the basis of the data, diagrams and descriptions in this documentation.
Copyright
© Beckhoff Automation GmbH & Co. KG 05/2015. The reproduction, distribution and utilization of this document as well as the communication of its contents to others without express authorization are prohibited. Offenders will be held liable for the payment of damages. All rights reserved in the event of the grant of a patent, utility model or design.

DOCUMENT ORGANIZATION

The Beckhoff EtherCAT Slave Controller (ESC) documentation covers the following Beckhoff ESCs:
ET1200  ET1100  EtherCAT IP Core for Altera® FPGAs  EtherCAT IP Core for Xilinx® FPGAs  ESC20
The documentation is organized in three sections. Section I and section II are common for all Beckhoff ESCs, Section III is specific for each ESC variant.
The latest documentation is available at the Beckhoff homepage (http://www.beckhoff.com).
Section I – Technology (All ESCs)
Section I deals with the basic EtherCAT technology. Starting with the EtherCAT protocol itself, the frame processing inside EtherCAT slaves is described. The features and interfaces of the physical layer with its two alternatives Ethernet and EBUS are explained afterwards. Finally, the details of the functional units of an ESC like FMMU, SyncManager, Distributed Clocks, Slave Information Interface, Interrupts, Watchdogs, and so on, are described.
Since Section I is common for all Beckhoff ESCs, it might describe features which are not available in a specific ESC. Refer to the feature details overview in Section III of a specific ESC to find out which features are available.
Section II – Register Description (All ESCs)
Section II contains detailed information about all ESC registers. This section is also common for all Beckhoff ESCs, thus registers, register bits, or features are described which might not be available in a specific ESC. Refer to the register overview and to the feature details overview in Section III of a specific ESC to find out which registers and features are available.

DOCUMENT HISTORY

Section III – Hardware Description (Specific ESC)
Section III is ESC specific and contains detailed information about the ESC features, implemented registers, configuration, interfaces, pinout, usage, electrical and mechanical specification, and so on. Especially the Process Data Interfaces (PDI) supported by the ESC are part of this section.
Additional Documentation
Application notes and utilities can also be found at the Beckhoff homepage. Pinout configuration tools for ET1100/ET1200 are available. Additional information on EtherCAT IP Cores with latest updates regarding design flow compatibility, FPGA device support and known issues are also available.
Slave Controller – EtherCAT IP Core Data Sheet Addendum II

CONTENTS

CONTENTS 1 Overview 1 2 EtherCAT IP Core for Altera FPGAs 1
2.1 FPGA design tool compatibility 1
2.2 FPGA device compatibility 3
2.3 FPGA device license support 4
2.4 Known Designflow Issues 5
2.4.1 General Quartus issues 5
2.4.1.1 Qsys: Avalon read error 5
2.4.2 Quartus 14 5
2.4.2.1 Quartus 14.1 Arria 10: Tristate drivers are not properly connected 5
2.4.2.2 Quartus 14.0 and later: Cyclone III example designs are not synthesizable 5
2.4.2.3 Quartus 14.0 with EtherCAT IP Core V3.0.0-V3.0.6: DE2-115 example designs are not working 5
3 EtherCAT IP Core for Xilinx FPGAs 6
3.1 FPGA design tool compatibility 6
3.3.4 Vivado 2013 11
3.3.4.1 Vivado 2013.2 with EtherCAT IP Core until V3.00f: IP License issue 11
3.3.5 ISE/EDK/PlanAhead 14.7 12
3.3.5.1 ISE: Crash in libSecurity_FNP.dll 12
3.3.5.2 ISE/EDK/PlanAhead: Additional BUFG inserted 12
3.3.5.3 ISE/EDK/PlanAhead: CLOCK_DEDICATED_ROUTE=FALSE constraint required 12
4 Appendix 13
4.1 Support and Service 13
4.1.1 Beckhoff’s branch offices and representatives 13
4.2 Beckhoff Headquarters 13
3.2 FPGA device compatibility 7
3.3 Known Designflow Issues 8
3.3.1 General Vivado issues 8
3.3.1.1 Vivado Upgrade IP: Warning on port differences 8
3.3.1.2 The resource consumption of the EtherCAT IP Core is too high8
3.3.1.3 EtherCAT IP Core is not part of the IP Catalog 8
3.3.2 Vivado 2015 9
3.3.2.1 Vivado 2015.1: The resource consumption (Slice LUTs) of the EtherCAT IP Core is too high 9
3.3.2.2 Vivado 2015.1: ZC702_AXI_VIVADO example design invalid constraints 9
3.3.2.3 Vivado 2015.1: ZC702_AXI_VIVADO example design does not meet timing requirements 9
3.3.2.4 Vivado 2015.1: ZC702_AXI_VIVADO example design and EtherCAT IP cores outside the Zynq block design fails in SDK 9
3.3.3 Vivado 2014 10
3.3.3.1 Vivado 2014.4: ZC702_AXI_VIVADO example design and EtherCAT IP cores outside the Zynq block design fails in SDK10
3.3.3.2 Vivado 2014.3: Abnormal program termination (EXCEPTION_ACCESS_VIOLATION) 10
3.3.3.3 Vivado until 2014.3: Tri-state buffers inside EtherCAT IP Core10
3.3.3.4 Vivado until 2014.2: The resource consumption of the EtherCAT IP Core is too high 10
3.3.3.5 Vivado until 2014.1: The ZC702 AXI Vivado example design is not synthesizable 11
Slave Controller – EtherCAT IP Core Data Sheet Addendum III
Overview
IP Core version
Release date
Tool
compatibility
Version compatibility
SoPC Builder
Qsys
5.1 SP2
6.1
7.0
7.1 SP1
7.2 SP2
8.0
9.0 SP1
9.1
10.0
10.1
11.0
11.1 SP2
12.0 SP1
12.1 SP1
13.0 SP1
13.1.4
14.01
14.11
15.01
1.0.0
7/2006
- ●
1.1.0
11/2006
- ●
1.1.1
1/2007
- ● ● ● ●
2.0.0
8/2007
- ● ● ● ●
2.2.0
6/2008
- ● ● ● ● ● ●
2.2.1
6/2009
- - - - - - - ●
2.3.0
12/2009
- - - - - - - - ●
2.3.1
2/2010
- - - - - - - - ●
2.3.2
3/2010
- - - - - - - - ● ● ●
2.4.0
3/2011
- - - - - - - - - ● ●
-
2.4.0
Patch 5
6/2012
- - - - - - - - - ● ● ● ●
2.4.3
7/2013
- - - - - - - - - ● ● ● ●
2.4.4
1/2015
- - - - - - - - - ● ● ● ●
3.0.0
3/2013
- - - - - - - - - - ● ● ●
3.0.1
3/2013
- - - - - - - - - - ● ● ●
3.0.2
5/2013
- - - - - - - - - - ● ● ●
● ●
3.0.5
2/2014
- - - - - - - - - - ● ● ●
● ●
3.0.6
4/2014
- - - - - - - - - - ● ● ●
● ● ○
3.0.9
9/2014
- - - - - - - - - - ● ● ●
● ● ● ●
3.0.10
1/2015
- - - - - - - - - -
● ● ● ●
1

1 Overview

This document provides latest release notes, documentation addendum, supported IP Core design flows, and supported IP Core FPGA types for the following Beckhoff EtherCAT Slave Controllers:
EtherCAT IP Core for Altera® FPGAs (up to V2.4.3 / V3.0.10)  EtherCAT IP Core for Xilinx® FPGAs (up to V2.04d Patch 1 / V3.00k)
Refer to the ESC data sheets for further information. The ESC data sheets are available from the Beckhoff homepage (http://www.beckhoff.com).

2 EtherCAT IP Core for Altera FPGAs

2.1 FPGA design tool compatibility

Starting with V2.4.0, Qsys is supported (the example designs of V2.4.0 are SoPC builder based).
Table 1: EtherCAT IP Core for Altera FPGAs compatibility with Altera Quartus II / NIOS EDS
Cyclone III devices are not supported anymore by Quartus, corresponding example designs cannot be synthesized. Refer to known issues for more details.
Slave Controller – EtherCAT IP Core Data Sheet Addendum 1
EtherCAT IP Core for Altera FPGAs
Symbol
Description
Compatible
Synthesis possible, issues with some example designs
-
Incompatible
Not tested
Table 2: Version compatibility legend
Slave Controller – EtherCAT IP Core Data Sheet Addendum 2
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