BECKHOFF EtherCAT IP Core for Xilinx FPGAs User Manual

Hardware Data Sheet Section III ET1815 / ET1816

Slave Controller

IP Core for Xilinx® FPGAs Release 3.00k

Section I – Technology (Online at http://www.beckhoff.com)

Section II – Register Description (Online at http://www.beckhoff.com)

Section III – Hardware Description

Installation, Configuration, Resource

consumption, Interface specification

Version 1.0 Date: 2015-01-20

DOCUMENT ORGANIZATION

Trademarks

Beckhoff®, TwinCAT®, EtherCAT®, Safety over EtherCAT®, TwinSAFE® and XFC® are registered trademarks of and licensed by Beckhoff Automation GmbH & Co. KG. Other designations used in this publication may be trademarks whose use by third parties for their own purposes could violate the rights of the owners.

Patent Pending

The EtherCAT Technology is covered, including but not limited to the following German patent applications and patents: DE10304637, DE102004044764, DE102005009224, DE102007017835 with corresponding applications or registrations in various other countries.

Disclaimer

The documentation has been prepared with care. The products described are, however, constantly under development. For that reason the documentation is not in every case checked for consistency with performance data, standards or other characteristics. In the event that it contains technical or editorial errors, we retain the right to make alterations at any time and without warning. No claims for the modification of products that have already been supplied may be made on the basis of the data, diagrams and descriptions in this documentation.

© Beckhoff Automation GmbH & Co. KG 01/2015. The reproduction, distribution and utilization of this document as well as the communication of its contents to others without express authorization are prohibited. Offenders will be held liable for the payment of damages. All rights reserved in the event of the grant of a patent, utility model or design.

DOCUMENT ORGANIZATION

The Beckhoff EtherCAT Slave Controller (ESC) documentation covers the following Beckhoff ESCs:

 ET1200  ET1100  EtherCAT IP Core for Altera® FPGAs  EtherCAT IP Core for Xilinx® FPGAs  ESC20

The documentation is organized in three sections. Section I and section II are common for all Beckhoff ESCs, Section III is specific for each ESC variant.

The latest documentation is available at the Beckhoff homepage (http://www.beckhoff.com).

Section I – Technology (All ESCs)

Section I deals with the basic EtherCAT technology. Starting with the EtherCAT protocol itself, the frame processing inside EtherCAT slaves is described. The features and interfaces of the physical layer with its two alternatives Ethernet and EBUS are explained afterwards. Finally, the details of the functional units of an ESC like FMMU, SyncManager, Distributed Clocks, Slave Information Interface, Interrupts, Watchdogs, and so on, are described.

Since Section I is common for all Beckhoff ESCs, it might describe features which are not available in a specific ESC. Refer to the feature details overview in Section III of a specific ESC to find out which features are available.

Section II – Register Description (All ESCs)

Section II contains detailed information about all ESC registers. This section is also common for all Beckhoff ESCs, thus registers, register bits, or features are described which might not be available in a specific ESC. Refer to the register overview and to the feature details overview in Section III of a specific ESC to find out which registers and features are available.

Section III – Hardware Description (Specific ESC)

Section III is ESC specific and contains detailed information about the ESC features, implemented registers, configuration, interfaces, pinout, usage, electrical and mechanical specification, and so on. Especially the Process Data Interfaces (PDI) supported by the ESC are part of this section.

Additional Documentation

Application notes and utilities can also be found at the Beckhoff homepage. Pinout configuration tools for ET1100/ET1200 are available. Additional information on EtherCAT IP Cores with latest updates regarding design flow compatibility, FPGA device support and known issues are also available.

III-II Slave Controller – IP Core for Xilinx FPGAs

DOCUMENT HISTORY

Version

Comment

1.0

 Initial release EtherCAT IP Core for Xilinx FPGAs v3.00k

DOCUMENT HISTORY

Slave Controller – IP Core for Xilinx FPGAs III-III

CONTENTS

1 Overview 1

1.1 Frame processing order 2

1.2 Scope of this document 3

1.3 Scope of Delivery 3

1.4 Target FPGAs 4

1.5 Designflow requirements 4

1.6 Tested FPGA/Designflow combinations 5

1.7 Release Notes 6

1.7.1 Major differences between V2.04x and V3.00x 9

1.7.2 Reading IP Core version from device 9

1.8 Design flow 10

1.9 IP Core Evaluation 11

1.10 Simulation 12

2 Features and Registers 13

2.1 Features 13

2.2 Registers 16

2.3 Extended ESC Features in User RAM 19

3 IP Core Installation 23

3.1 Installation on Windows PCs 23

3.1.1 System Requirements 23

3.1.2 Installation 23

3.2 Installation on Linux PCs 24

3.2.1 System Requirements 24

3.2.2 Installation 24

3.3 Files located in the lib folder 24

3.4 License File 25

3.5 IP Core Vendor ID Package 25

3.6 RSA Decryption Keys 26

3.7 Environment Variable 26

3.8 Integrating the EtherCAT IP Core into the Xilinx Designflow 27

3.8.1 Software Templates for example designs with Microblaze/ARM processor (EDK) 27

3.8.2 Software Templates for example designs with ARM processor (Vivado) 27

3.9 EtherCAT Slave Information (ESI) / XML device description for example designs 27

4 IP Core Usage 28

4.1 IPCore_Config Tool 28

4.2 EDK designs with EtherCAT IP Core 29

4.3 Vivado designs with EtherCAT IP Core 33

5 IP Core Configuration 34

5.1.1 Product ID tab 35

III-IV Slave Controller – IP Core for Xilinx FPGAs

CONTENTS

5.1.2 Physical Layer tab 36

5.1.3 Internal Functions tab 38

5.1.4 Feature Details tab 40

5.1.5 Register: Process Data Interface tab 42

6 Example Designs 49

6.1 Avnet Xilinx Spartan-6 LX150T Development Kit with Digital I/O 50

6.1.1 Configuration and resource consumption 50

6.1.2 Functionality 50

6.1.3 Implementation 50

6.1.4 SII EEPROM 51

6.1.5 Downloadable configuration file 51

6.2 Avnet Xilinx Spartan-6 LX150T Development Kit with AXI 52

6.2.1 Configuration and resource consumption 52

6.2.2 Functionality 52

6.2.3 Implementation 53

6.2.4 SII EEPROM 53

6.2.5 Downloadable configuration file 53

6.3 Xilinx Zynq ZC702 Development Kit with AXI (Vivado based) 54

6.3.1 Configuration and resource consumption 54

6.3.2 Functionality 54

6.3.3 Implementation 55

6.3.4 SII EEPROM 55 7 FPGA Resource Consumption 56 8 IP Core Signals 59

8.1 General Signals 59

8.1.1 Clock source example schematics 60

8.2 SII EEPROM Interface Signals 61

8.3 LED Signals 61

8.4 Distributed Clocks SYNC/LATCH Signals 62

8.5 Physical Layer Interface 63

8.5.1 MII Interface 64

8.5.2 RMII Interface 66

8.5.3 RGMII Interface 67

8.6 PDI Signals 70

8.6.1 General PDI Signals 70

8.6.2 Digital I/O Interface 70

8.6.3 SPI Slave Interface 71

8.6.4 Asynchronous 8/16 Bit µController Interface 71

8.6.5 PLB Processor Local Bus 73

8.6.6 AXI4 / AXI4 LITE On-Chip Bus 76 9 Ethernet Interface 78

Slave Controller – IP Core for Xilinx FPGAs III-V

CONTENTS

9.1 PHY Management interface 78

9.1.1 PHY Management Interface Signals 78

9.1.2 PHY Address Configuration 78

9.1.3 Separate external MII management interfaces 79

9.1.4 MII management timing specifications 79

9.2 MII Interface 80

9.2.1 MII Interface Signals 81

9.2.2 TX Shift Compensation 82

9.2.3 MII Timing specifications 83

9.2.4 MII example schematic 84

9.3 RMII Interface 85

9.3.1 RMII Interface Signals 85

9.3.2 RMII example schematic 86

9.4 RGMII Interface 87

9.4.1 RGMII Interface Signals 87

9.4.2 RGMII example schematic 89

9.4.3 RGMII RX timing options 89

9.4.4 RGMII TX timing options 89 10 PDI Description 91

10.1 Digital I/O Interface 92

10.1.1 Interface 92

10.1.2 Configuration 93

10.1.3 Digital Inputs 93

10.1.4 Digital Outputs 93

10.1.5 Output Enable 94

10.1.6 SyncManager Watchdog 94

10.1.7 SOF 95

10.1.8 OUTVALID 95

10.1.9 Timing specifications 95

10.2 SPI Slave Interface 98

10.2.1 Interface 98

10.2.2 Configuration 98

10.2.3 SPI access 99

10.2.4 Address modes 99

10.2.5 Commands 100

10.2.6 Interrupt request register (AL Event register) 100

10.2.7 Write access 100

10.2.8 Read access 100

10.2.9 SPI access errors and SPI status flag 101

10.2.10 2 Byte and 4 Byte SPI Masters 102

10.2.11 Timing specifications 103 III-VI Slave Controller – IP Core for Xilinx FPGAs

CONTENTS

10.3 Asynchronous 8/16 bit µController Interface 109

10.3.1 Interface 109

10.3.2 Configuration 109

10.3.3 µController access 110

10.3.4 Write access 110

10.3.5 Read access 110

10.3.6 µController access errors 111

10.3.7 Connection with 16 bit µControllers without byte addressing 111

10.3.8 Connection with 8 bit µControllers 112

10.3.9 Timing Specification 113

10.4 PLB Slave Interface 117

10.4.1 Interface 117

10.4.2 Configuration 118

10.4.3 Timing specifications 119

10.5 AXI4/AXI4 LITE On-Chip Bus 121

10.5.1 Interface 121

10.5.2 Configuration 123

10.5.3 Interrupts 123

10.5.4 Timing specifications 124 11 Distributed Clocks SYNC/LATCH Signals 126

11.1 Signals 126

11.2 Timing specifications 126

12 SII EEPROM Interface (I²C) 127

12.1 Signals 127

12.2 EEPROM Emulation 127

12.3 Timing specifications 127 13 Electrical Specifications 128 14 Synthesis Constraints 129 15 Appendix 132

15.1 Support and Service 132

15.1.1 Beckhoff’s branch offices and representatives 132

15.2 Beckhoff Headquarters 132

Slave Controller – IP Core for Xilinx FPGAs III-VII

TABLES

Table 1: IP Core Main Features .............................................................................................................. 1

Table 2: Frame Processing Order ........................................................................................................... 2

Table 3: Tested FPGA/Designflow combinations .................................................................................... 5

Table 4: Release notes ............................................................................................................................ 6

Table 5: Register Revision (0x0001) ....................................................................................................... 9

Table 6: Register Build (0x0002:0x0003) ................................................................................................ 9

Table 7: IP Core Feature Details ........................................................................................................... 13

Table 8: Legend ..................................................................................................................................... 15

Table 9: Register availability.................................................................................................................. 16

Table 10: Legend ................................................................................................................................... 18

Table 11: Extended ESC Features (Reset values of User RAM – 0x0F80:0x0FFF) ............................ 19

Table 12: Contents of lib folder.............................................................................................................. 24

Table 13: Resource consumption Avnet LX150T example design ....................................................... 50

Table 14: Resource consumption Avnet LX150T example design ....................................................... 52

Table 15: Resource consumption Xilinx Zynq ZC702 example design ................................................. 54

Table 16: Approximate resource requirements for main configurable functions ................................... 57

Table 17: EtherCAT IP Core resource consumption for typical EtherCAT Devices .............................. 58

Table 18: General Signals ..................................................................................................................... 59

Table 19: SII EEPROM Signals ............................................................................................................. 61

Table 20: LED Signals ........................................................................................................................... 61

Table 21: DC SYNC/LATCH signals ..................................................................................................... 62

Table 22: Physical Layer General ......................................................................................................... 63

Table 23: PHY Interface MII .................................................................................................................. 64

Table 24: PHY Interface RMII................................................................................................................ 66

Table 25: PHY Interface RGMII ............................................................................................................. 67

Table 26: General PDI Signals .............................................................................................................. 70

Table 27: Digital I/O PDI ........................................................................................................................ 70

Table 28: SPI PDI .................................................................................................................................. 71

Table 29: 8/16 Bit µC PDI ...................................................................................................................... 71

Table 30: 8 Bit µC PDI ........................................................................................................................... 72

Table 31: 16 Bit µC PDI ......................................................................................................................... 72

Table 32: PLB PDI ................................................................................................................................. 73

Table 33: PLB PDI additional signals of XPS/EDK pcores ................................................................... 75

Table 34: AXI4 / AXI4 LITE PDI ............................................................................................................ 76

Table 35: AXI4 / AXI4 LITE PDI additional signals of XPS/EDK pcores ............................................... 77

Table 36: PHY management Interface signals ...................................................................................... 78

Table 37: MII management timing characteristics ................................................................................. 79

Table 38: MII Interface signals .............................................................................................................. 81

Table 39: MII TX Timing characteristics ................................................................................................ 83

Table 40: MII timing characteristics ....................................................................................................... 83

Table 41: RMII Interface signals ............................................................................................................ 85

Table 42: RGMII Interface signals ......................................................................................................... 88

Table 43: Available PDIs for EtherCAT IP Core .................................................................................... 91

Table 44: IP core digital I/O signals ....................................................................................................... 92

Table 45: Input/Output byte reference ................................................................................................... 92

Table 46: Digital I/O timing characteristics IP Core ............................................................................... 95

Table 47: SPI signals ............................................................................................................................. 98

Table 48: Address modes ...................................................................................................................... 99

Table 49: SPI commands CMD0 and CMD1 ....................................................................................... 100

Table 50: Interrupt request register transmission ................................................................................ 100

Table 51: Write access for 2 and 4 Byte SPI Masters ......................................................................... 102

Table 52: SPI timing characteristics IP Core ....................................................................................... 103

Table 53: Read/Write timing diagram symbols .................................................................................... 104

Table 54: µController signals ............................................................................................................... 109

Table 55: 8 bit µController interface access types .............................................................................. 110

Table 56: 16 bit µController interface access types ............................................................................ 110

Table 57: µController timing characteristics IP Core ........................................................................... 113

Table 58: PLB signals .......................................................................................................................... 117

Table 59: PLB clock period values for synchronous clocking ............................................................. 118

Table 60: PLB timing characteristics ................................................................................................... 119

III-VIII Slave Controller – IP Core for Xilinx FPGAs

TABLES

Table 61: AXI4 LITE signals ................................................................................................................ 121

Table 62: Additional AXI4 signals ........................................................................................................ 122

Table 63: AXI timing characteristics .................................................................................................... 124

Table 64: Distributed Clocks signals ................................................................................................... 126

Table 65: DC SYNC/LATCH timing characteristics IP Core ............................................................... 126

Table 66: I²C EEPROM signals ........................................................................................................... 127

Table 67: EEPROM timing characteristics IP Core ............................................................................. 127

Table 68: AC Characteristics ............................................................................................................... 128

Table 69: Forwarding Delays ............................................................................................................... 128

Table 70: EtherCAT IP Core constraints ............................................................................................. 129

Slave Controller – IP Core for Xilinx FPGAs III-IX

FIGURES

Figure 1: EtherCAT IP Core Block Diagram ............................................................................................ 1

Figure 2: Frame Processing .................................................................................................................... 2

Figure 3: Design flow ............................................................................................................................. 10

Figure 4: Files installed with EtherCAT IP core setup ........................................................................... 23

Figure 5: IPCore_Config Open Menu .................................................................................................... 28

Figure 6: IP Core generation successful ............................................................................................... 28

Figure 7: EDK – Overview ..................................................................................................................... 30

Figure 8: EDK – Configuration of IP Core ............................................................................................. 30

Figure 9: EDK – Configuration Dialog ................................................................................................... 31

Figure 10: EDK – System Assembly View, Addresses tab ................................................................... 31

Figure 11: EDK – System Assembly View, Ports tab ............................................................................ 32

Figure 12: EtherCAT IP Core Configuration Interface ........................................................................... 34

Figure 13: Product ID tab ...................................................................................................................... 35

Figure 14: Physical Layer tab ................................................................................................................ 36

Figure 15: Internal Functions tab ........................................................................................................... 38

Figure 16: Feature Details tab ............................................................................................................... 40

Figure 17: Available PDI Interfaces ....................................................................................................... 42

Figure 18: Register Process Data Interface .......................................................................................... 43

Figure 19: Register PDI – Digital I/O Configuration............................................................................... 44

Figure 20: Register PDI – µC-Configuration.......................................................................................... 45

Figure 21: Register PDI – SPI Configuration ......................................................................................... 46

Figure 22: Register PDI – PLB Interface Configuration ........................................................................ 47

Figure 23: Register PDI – AXI4/AXI4 LITE Interface Configuration ...................................................... 48

Figure 24: EtherCAT IP Core clock source (MII) ................................................................................... 60

Figure 25: EtherCAT IP Core clock source (RMII) ................................................................................ 60

Figure 26: EtherCAT IP Core clock source (RGMII) ............................................................................. 60

Figure 27: PHY management Interface signals..................................................................................... 78

Figure 28: Example schematic with two individual MII management interfaces ................................... 79

Figure 29: MII Interface signals ............................................................................................................. 81

Figure 30: MII TX Timing Diagram ........................................................................................................ 82

Figure 31: MII timing RX signals............................................................................................................ 83

Figure 32: MII example schematic......................................................................................................... 84

Figure 33: RMII Interface signals........................................................................................................... 85

Figure 34: RMII example schematic ...................................................................................................... 86

Figure 35: RGMII Interface signals ........................................................................................................ 88

Figure 36: RGMII example schematic ................................................................................................... 89

Figure 37: IP core digital I/O signals ..................................................................................................... 92

Figure 38: Digital Output Principle Schematic ....................................................................................... 94

Figure 39: Digital Input: Input data sampled at SOF, I/O can be read in the same frame .................... 96

Figure 40: Digital Input: Input data sampled with LATCH_IN ................................................................ 96

Figure 41: Digital Input: Input data sampled with SYNC0/1 .................................................................. 96

Figure 42: Digital Output timing ............................................................................................................. 97

Figure 43: OUT_ENA timing .................................................................................................................. 97

Figure 44: SPI master and slave interconnection.................................................................................. 98

Figure 45: Basic SPI_DI/SPI_DO timing (*refer to timing diagram for relevant edges of SPI_CLK) .. 104

Figure 46: SPI read access (2 byte addressing, 1 byte read data) with Wait State byte .................... 105

Figure 47: SPI read access (2 byte addressing, 2 byte read data) with Wait State byte .................... 106

Figure 48: SPI write access (2 byte addressing, 1 byte write data) .................................................... 107

Figure 49: SPI write access (3 byte addressing, 1 byte write data) .................................................... 108

Figure 50: µController interconnection ................................................................................................ 109

Figure 51: Connection with 16 bit µControllers without byte addressing ............................................ 111

Figure 52: Connection with 8 bit µControllers (BHE and DATA[15:8] should not be left open) .......... 112

Figure 53: Read access (without preceding write access) .................................................................. 114

Figure 54: Write access (write after rising edge nWR, without preceding write access) .................... 115

Figure 55: Sequence of two write accesses and a read access ......................................................... 115

Figure 56: Write access (write after falling edge nWR) ....................................................................... 116

Figure 57: PLB signals ........................................................................................................................ 117

Figure 58: PLB Read Access .............................................................................................................. 120

Figure 59: PLB Write Access ............................................................................................................... 120

Figure 60: AXI4 signals ....................................................................................................................... 121

III-X Slave Controller – IP Core for Xilinx FPGAs

FIGURES

Figure 61: AXI Read Access ............................................................................................................... 125

Figure 62: AXI Write Access ................................................................................................................ 125

Figure 63: Distributed Clocks signals .................................................................................................. 126

Figure 64: LatchSignal timing .............................................................................................................. 126

Figure 65: SyncSignal timing ............................................................................................................... 126

Figure 66: I²C EEPROM signals .......................................................................................................... 127

Slave Controller – IP Core for Xilinx FPGAs III-XI

ABBREVIATIONS

µC

Microcontroller

ADR

Address

Application Layer

AMBA®

Advanced Microcontroller Bus Architecture from ARM®

AXITM

Advanced eXtensible Interface Bus, an AMBA interconnect. Used as On-Chip-bus

BHE

Bus High Enable

BSP

Board Support Package

CMD

Command

Chip Select

Distributed Clock

DCM

Digital Clock Manager

Data Link Layer

ECAT

EtherCAT

EDK

Embedded Development Kit (Xilinx software)

EOF

End of Frame

ESC

EtherCAT Slave Controller

ESI

EtherCAT Slave Information

FMMU

Fieldbus Memory Management Unit

FPGA

Field Programmable Gate Array

GPI

General Purpose Input

GPO

General Purpose Output

HDL

Hardware Description Language

Intellectual Property

IRQ

Interrupt Request

ISE

Integrated Software Environment (Xilinx software)

Logic Element

Logic Cell

MAC

Media Access Controller

MDIO

Management Data Input / Output

MHS

Microprocessor Hardware Specification

(PHY) Management Interface

MII

Media Independent Interface

MISO

Master In – Slave Out

MOSI

Master Out – Slave In

MPD

Microprocessor Peripheral Specification

OPB

On-Chip Peripheral Bus

PAO

Peripheral Analyze Order

PDI

Process Data Interface

PLB

Processor Local Bus

PLD

Programmable Logic Device

PLL

Phase Locked Loop

RBF

Raw Binary File

Read

RMII

Reduced Media Independent Interface

SDK

Software Development Kit

SyncManager

SoC

System on a Chip

SOF

Start of Frame

SOPC

System on a programmable Chip

SPI

Serial Peripheral Interface

VHDL

Very High Speed Integrated Circuit Hardware Description Language

Write

ABBREVIATIONS

III-XII Slave Controller – IP Core for Xilinx FPGAs

Overview

Feature

IP Core configurable features

Ports

1-3 MII ports or 1-3 RGMII ports 1-2 RMII ports

FMMUs

0-8

SyncManagers

0-8

RAM

0-60 KB

Distributed Clocks

Yes, 32 bit or 64 bit

Process Data Interfaces

 32 Bit Digital I/O (unidirectional)  SPI Slave  8/16 bit asynchronous µController Interface  PLB v4.6 on-chip bus  AMBA® AXI4TM/AXI4 LITETM on-chip bus

Other features

 Example designs for easy start up included  Slave applications can run on-chip if the appropriate FPGAs with

sufficient resources are used

ECAT Processing Unit

AutoForwarder +

Loopback

SyncManager

FMMU

ESC address space

User RAMRegisters Process RAM

EEPROM

Distributed

Clocks

Monitoring Status

PHY

Management

SYNC LEDsI²C EEPROM

PHY MI

SPI / µC / Digital I/O /

PLB / AXI

0 2

Ethernet ports

LATCH

PDI

ECAT Interface PDI Interface

ResetReset

1 Overview

The EtherCAT IP Core is a configurable EtherCAT Slave Controller (ESC). It takes care of the EtherCAT communication as an interface between the EtherCAT fieldbus and the slave application. The EtherCAT IP Core is delivered as a configurable system so that the feature set fits the requirements perfectly and brings costs down to an optimum.

Table 1: IP Core Main Features

The general functionality of the EtherCAT IP Core is shown in Figure 1:

Slave Controller – IP Core for Xilinx FPGAs III-1

Figure 1: EtherCAT IP Core Block Diagram

Overview

Number of Ports

Frame processing order

0→EtherCAT Processing Unit→0

0→EtherCAT Processing Unit→1 / 1→0

0→EtherCAT Processing Unit→1 / 1→2 / 2→0 (log. ports 0,1, and 2)

Port 1

Auto-

Forwarder

Port 0

Auto-

Forwarder

Loopback function

EtherCAT

Processing Unit

Loopback function

EtherCAT IP Core

port 1 closed

port 1 open

port 0 open

or all ports

closed

port 0 closed

Port 2

Auto-

Forwarder

Loopback function

port 2 closed

port 2 open

1.1 Frame processing order

The frame processing order of the EtherCAT IP Core is as follows (logical port numbers are used):

Table 2: Frame Processing Order

Figure 2 shows the frame processing in general:

Figure 2: Frame Processing

Frame Processing Example with Ports 0 and 1

A frame received at port 0 goes via the Auto-Forwarder and the Loopback function to the EtherCAT Processing Unit which processes it. Then, the frame is sent to port 1. If port 1 is open, the frame is sent out at port 1. If it is closed, the frame is forwarded by the Loopback function to port 2. Since port 2 is not configured, the Loopback function of port 2 forwards the frame to the Loopback function of port 0, and then it is sent out at port 0 – back to the master.

III-2 Slave Controller – IP Core for Xilinx FPGAs

Overview

1.2 Scope of this document

Purpose of this document is to describe the installation and configuration of the EtherCAT IP Core for Xilinx FPGAs. Furthermore, the signals and registers of the IP Core depending on the chosen configuration are described.

This documentation was made with the assumption that the user is familiar with the handling of the Xilinx Development Environment.

1.3 Scope of Delivery

The EtherCAT IP Core installation file includes:

 EtherCAT IP Core (encrypted VHDL library)  Decryption keys for encrypted EtherCAT IP Core  IP Core Configuration Tool (IPCore_Config.exe)  Example designs

The following files which contain customer specific information are required to synthesize the IP Core. They are delivered independently of the installation file.

 License File to decrypt EtherCAT IP Core: iptb_ethercat_ipcore_<version>_flexlm.lic  Encrypted Vendor ID package: pk_ECAT_VENDORID_<company>_Xilinx_RSA.vhd

Slave Controller – IP Core for Xilinx FPGAs III-3

Overview

1.4 Target FPGAs

The EtherCAT IP Core for Xilinx® FPGAs is targeted at these FPGA families:

 Spartan®-6  Artix®-7, Artix-7 Low Voltage  KintexTM-7, Kintex-7 Low Voltage  Virtex®-6  Virtex®-7  Kintex® UltraScaleTM  Virtex® UltraScaleTM  Zynq®-7000

The EtherCAT IP Core is designed to support a wide range of FPGAs without modifications, because it does not instantiate dedicated FPGA resources, or rely on device specific features. Thus, the IP Core is easily portable to new FPGA families (e.g. Zynq UltraScale MPSoC).

The complexity of the IP Core is highly configurable, so its demands for logic resources, memory blocks, and FPGA speed cover a wide range. Thus, it is not possible to run any IP Core configuration on any target FPGA with any speed grade. I.e., there are IP Core configurations requiring a faster speed grade, or a larger FPGA, or even a more powerful FPGA family.

It is necessary to run through the whole synthesis process – including timing checks –, to evaluate if the selected FPGA is suitable for a certain IP Core configuration before making the decision for the FPGA. Please consider a security margin for the logic resources to allow for minor enhancements and bug fixes of the IP Core and the user logic.

1.5 Designflow requirements

For synthesis of the EtherCAT IP Core for Xilinx FPGAs, at least one of the following Xilinx design tools is needed:

 Xilinx Integrated Software Environment ISE 14.3 - 14.7  Xilinx Platform Studio 14.3 - 14.7  Xilinx PlanAhead 14.3 - 14.7  Xilinx Vivado 2013.1 - 2013.4, 2014.1 - 2014.3  Xilinx Vivado 2014.4 (Refer to the Hardware Data Sheet Section III Addendum for issues with the

Vivado example design)

Higher design tool versions are probably supported. Installation of the latest patches is recommended. A free version (“WebPack”) is available from Xilinx (http://www.xilinx.com).

Optionally for using the EtherCAT IP Core with embedded processor designs, you will need

 Xilinx SDK  Xilinx Vivado SDK

III-4 Slave Controller – IP Core for Xilinx FPGAs

Overview

IP Core

Family

Device

Designflow

Test

Used Example Designs

3.00k

Spartan-6

XC6SLX150T

ISE 14.7

Hardware

LX150T AXI / DIGI

Artix-7

XC7A100T

ISE 14.7

Synthesis

Kintex-7

XC7K70T

ISE 14.7

Synthesis

Virtex-6

XC6VLX75T

ISE 14.7

Synthesis

Virtex-7

XC7VX485T

ISE 14.7

Synthesis

Kintex UltraScale

XCKU035

Vivado 2014.3

Synthesis

Virtex UltraScale

XCVU080

Vivado 2014.4

Synthesis

Zynq 7020

XC7Z020

Vivado 2014.3

Hardware

ZC702 AXI Vivado

1.6 Tested FPGA/Designflow combinations

The EtherCAT IP Core has been synthesized successfully with different ISE/EDK versions and FPGA families. Table 3 lists combinations of FPGA devices and design tools versions which have been synthesized or even tested in real hardware. This list does not claim to be complete, it just illustrates that the EtherCAT IP Core is designed to comply with a broad spectrum of FPGAs.

Table 3: Tested FPGA/Designflow combinations

NOTE: Synthesis test means XST synthesis, implementation and programming file generation. Hardware test means the design was operational on hardware.

Refer to the Hardware Data Sheet Section III Addendum available at the Beckhoff homepage (http://www.beckhoff.com) for latest updates regarding device support, design flow compatibility, and known issues.

Slave Controller – IP Core for Xilinx FPGAs III-5

Overview

Version

Release notes

3.00c (5/2013)

 Update to ISE 14.3/14.4/14.5, Vivado 2013.1  Removed support for Spartan-3/-3E/-3A/-3AN/-3AN DSP, Virtex-4, and Virtex-5 due

to XST incompatibility

 Removed OPB support  Removed small/medium/large register sets, added updated preset configurations

Enhancements:

 Increased PDI performance  Support for 8/16/32/64 bit AXI4 and AXI4 Lite interface  Support for RGMII ports  Native support for FX PHYs  Support for individual PHY address configuration and reading out this configuration  Support for static or dynamic PHY address configuration  Support for 0 KB Process RAM, DC Sync/Latch signals individually configurable,

LED test added

 Support for PDI SyncManager/IRQ acknowledge by Write command  Device emulation is now configured in the GUI statically.  MI link detection: relaxed checking of PHY register 9 (1000Base-T Master-Slave

Control register) Restrictions of this version, which are removed in V3.00f:  The AXI PDI may occasionally write incorrect data if simultaneous read and write

accesses occur repeatedly.  RX FIFO size is not initialized by SII EEPROM

Restrictions of this version, which are removed in V3.00g:  The ERR LED does not allow overriding using the ERR LED Override register

0x0139 while AL Status register Error Indication bit 0x0130[4] is set  RMII is not supported because of wrong configuration by IPCore_Config tool

Restrictions of this version, which are removed in V3.00j:  The AXI PDI may not complete an access occasionally if overlapping read and write

accesses occur, causing the processor to wait endlessly.  The AXI PDI does not execute read accesses correctly if ARSIZE is smaller than

the AXI bus width. Restrictions of this version, which are removed in V3.00k:  The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60

Kbyte RAM configuration.  The AXI PDI may write to wrong bytes if the write data is valid before the address,

which is typically true for AXI4LITE.

 The AXI PDI may read additional bytes after the intended bytes.  The PLB PDI only supports peer-to-peer mode (C_SPLB_P2P=1), or a base

address of 0 (C_SPLB_BASEADDR=0x00000000).  The PLB PDI was generated with an invalid component declaration package.

1.7 Release Notes

EtherCAT IP Core updates deliver feature enhancements and removed restrictions. Feature enhancements are not mandatory regarding conformance to the EtherCAT standard. Restrictions have to be judged whether they are relevant in the user’s configuration or not, or if workarounds are possible.

Table 4: Release notes

III-6 Slave Controller – IP Core for Xilinx FPGAs

Overview

Version

Release notes

3.00f (2/2014)

Restrictions of previous versions which are removed in this version:  The AXI PDI writes correct data if simultaneous read and write accesses occur

repeatedly.  RX FIFO size is properly initialized by SII EEPROM

Restrictions of this version, which are removed in V3.00g:  The ERR LED does not allow overriding using the ERR LED Override register

0x0139 while AL Status register Error Indication bit 0x0130[4] is set  RMII is not supported because of wrong configuration by IPCore_Config tool

Restrictions of this version, which are removed in V3.00j:  The AXI PDI may not complete an access occasionally if overlapping read and write

accesses occur, causing the processor to wait endlessly.  The AXI PDI does not execute read accesses correctly if ARSIZE is smaller than

the AXI bus width. Restrictions of this version, which are removed in V3.00k:  The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60

Kbyte RAM configuration.  The AXI PDI may write to wrong bytes if the write data is valid before the address,

which is typically true for AXI4LITE.

 The AXI PDI may read additional bytes after the intended bytes.  The PLB PDI only supports peer-to-peer mode (C_SPLB_P2P=1), or a base

address of 0 (C_SPLB_BASEADDR=0x00000000).  The PLB PDI was generated with an invalid component declaration package.

3.00g (4/2014)

Enhancements:  The Sync/Latch PDI Configuration register 0x0151 shows the same value as

previous IP Core versions. The actual configuration is not affected, since it is fixed

by the IP Core configuration.

 Added support for unaligned AXI burst transfers.  Internal license attribute encoding updated (issues with Vivado 2012.x)

Restrictions of previous versions which are removed in this version:  The ERR LED allows overriding using the ERR LED Override register 0x0139 while

AL Status register Error Indication bit 0x0130[4] is set. The override flag is now

cleared upon a rising edge of 0x0130[4], and it can be set again afterwards.  RMII is now configured correctly by IPCore_Config tool

Restrictions of this version, which are removed in V3.00j:  The AXI PDI may not complete an access occasionally if overlapping read and write

accesses occur, causing the processor to wait endlessly.  The AXI PDI does not execute read accesses correctly if ARSIZE is smaller than

the AXI bus width. Restrictions of this version, which are removed in V3.00k:  The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60

Kbyte RAM configuration.  The AXI PDI may write to wrong bytes if the write data is valid before the address,

which is typically true for AXI4LITE.

 The AXI PDI may read additional bytes after the intended bytes.  The PLB PDI only supports peer-to-peer mode (C_SPLB_P2P=1), or a base

address of 0 (C_SPLB_BASEADDR=0x00000000).  The PLB PDI was generated with an invalid component declaration package.

Slave Controller – IP Core for Xilinx FPGAs III-7

Overview

Version

Release notes

3.00j (9/2014)

Enhancements:  An example design for the Xilinx Zynq ZC702 development kit using Vivado has

been added. A Vivado SDK template for this example design is included  The example designs using ISMNET PHY boards have been extended to support

COL and CRS signals, which are required for proper PHY configuration.  The PDI watchdog status 0x0110[1] now shows value ‘1’ (watchdog reloaded) if the

PDI watchdog is configured to be not available.  The ESI XML device description does not use special data types anymore.

Restrictions of previous versions which are removed in this version:

 The AXI PDI completes accesses if overlapping read and write accesses occur.  The AXI PDI executes read accesses correctly if ARSIZE is smaller than the AXI

bus width. Restrictions of this version, which are removed in V3.00k:  The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60

Kbyte RAM configuration.  The AXI PDI may write to wrong bytes if the write data is valid before the address,

which is typically true for AXI4LITE.

 The AXI PDI may read additional bytes after the intended bytes.  The PLB PDI only supports peer-to-peer mode (C_SPLB_P2P=1), or a base

address of 0 (C_SPLB_BASEADDR=0x00000000).  The PLB PDI was generated with an invalid component declaration package.

3.00k (1/2015)

The PlanAhead-based Xilinx Zynq ZC702 example design has been removed, because a Vivado based example design is available.

Enhancements:  For EEPROM Emulation, the CRC error bit 0x0502[11] can be written via PDI to

indicate CRC errors during a reload command.  The IPCore_Config tool optionally generates AXI/PLB configurations without the

XPS pcores folder structure (e.g. for Vivado).  The AXI4LITE PDI wrapper does no longer contain the unused REGION and QOS

signals. Restrictions of previous versions which are removed in this version:  The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) can be used in the 60 Kbyte

RAM configuration.  The AXI PDI does not write to wrong bytes if the write data is valid before the

address.

 The AXI PDI does not read additional bytes after the intended bytes.  The PLB PDI supports any base address.  The PLB PDI is generated with a valid component declaration package.

III-8 Slave Controller – IP Core for Xilinx FPGAs

Overview

Bit

Description

ECAT

PDI

Reset Value

7:0

IP Core major version X

r/-

IP Core dep.

Bit

Description

ECAT

PDI

Reset Value

3:0

IP Core maintenance version z r/-

r/-

IP Core dep.

7:4

IP Core minor version Y

r/-

IP Core dep.

15:8

Patch level: 0x00: original release 0x01-0x0F: patch level of original release

r/-

IP Core dep.

1.7.1 Major differences between V2.04x and V3.00x

The EtherCAT IP Core V3.00x versions have these advantages compared with the V2.04x versions:  Increased PDI performance (average latency internally at least by a factor of 2 faster; worst case

latency even better)

 Support for 8/16/32/64 bit AXI4TM and AXI4 LITETM interface  Support for RGMII ports  Native support for FX PHYs  Flexible PHY address configuration  Support for PDI SyncManager/IRQ acknowledge by Write command (required for wide on-chip-

busses)

 More detailed configuration The higher PDI performance increases the resource requirements of the V3.00x versions compared

with the V2.04x versions. New development is focused on the V3.00x versions.

1.7.2 Reading IP Core version from device

The IP Core version, denoted as X.Yz (e.g., 1.00a), consists of three values X, Y, and z. These values can be read out in registers 0x0001 and 0x0002. Value z is encoded like this: a=0, b=1, c=2, etc. .

Table 5: Register Revision (0x0001)

Table 6: Register Build (0x0002:0x0003)

Slave Controller – IP Core for Xilinx FPGAs III-9

Overview

IP Core

installation (eval)

Synthesis

User logic

Vendor ID package License file (full)

FPGA configuration file

Download

utility

FPGA

Buy-out license /

Quantity-based license

(license agreement)

grants permission

EvaluationDevelopment

Download

utility

MAC ID

Vendor

bit-

stream

Application

specific ESC

sources

VHDL

Verilog

Schematic

Production

FPGA

Download

utility

FPGA

encrypted

VHD

FPGA configuration file

bit-

stream

(timebomb)

FPGA

(timebomb)

IP Core

installation (full)

encrypted

VHDL

Customer

License file (eval)

MAC ID

1.8 Design flow

The design flow for creating an EtherCAT Slave Controller based on the EtherCAT IP Core is shown in the following picture:

Figure 3: Design flow

III-10 Slave Controller – IP Core for Xilinx FPGAs

Overview

1.9 IP Core Evaluation

The EtherCAT IP Core for Xilinx FPGAs supports IP core evaluation. A dedicated setup file containing the evaluation version of the IP Core is available, which also includes the decryption keys for the evaluation IP Core. Additionally, a special evaluation license file is required for IP core evaluation.

A design with the evaluation version of the EtherCAT IP Core is subject to some restrictions:

 The EtherCAT IP Core will discontinue its function after approximately one hour.  The evaluation version slightly increases the resource consumption of the IP Core.  The evaluation bitstream must not be distributed/sold.

A vendor ID package is required for both evaluation and full license. It is recommended to use an evaluation vendor ID (package) for evaluation, and the original vendor ID for production. The

evaluation vendor ID is beginning with “0xE.......” and ends with the original vendor ID digits.

Evaluation vendor IDs cannot pass the EtherCAT conformance tests.

Selecting Full or Evaluation License

There are individual setup files for full and evaluation license. The evaluation version can be easily upgraded to a full version just by running the EtherCAT IP Core setup for the full version.

For Linux, just install the full version over the evaluation license, the appropriate files will be overwritten.

A design using an evaluation EtherCAT IP Core does not have to be changed when upgrading to a full license (or vice-versa).

Four steps have to be performed to change the license type:

1. Acquire the intended license and set it up

2. Windows: Start the appropriate EtherCAT IP Core setup. Alternatively, uninstall the EtherCAT IP Core and install it again with the intended license version. The example designs are automatically updated and the decryption keys are also installed.

Linux:

Unzip the setup files over the existing installation (you might want to delete the installation folder <IPInst_dir> before). Copy the new decryption keys from the <IPInst_dir>/lib folder to your $HOME/RSA folder.

3. Update your own projects with the EtherCAT_IPCore.vhd from the lib-folder. For EDK projects, it is sufficient to generate the core again, because the IPCore_Config tool will integrate the current IP Core from the lib folder.

4. Synthesize your designs again to generate unlimited bitstreams with the full license, and timebombed bitstreams with the evaluation license.

A txt-file is placed in the lib folder which indicates the currently installed IP core version (evaluation or full).

Slave Controller – IP Core for Xilinx FPGAs III-11

Overview

1.10 Simulation

A behavioral simulation model of the EtherCAT IP core is not available because of its size and complexity. Thus, simulation of the entire EtherCAT IP Core is not supported. In most cases, simulation of the EtherCAT IP Core is not necessary, as the IP Core was thoroughly tested and the interfaces are standardized (Ethernet, PLB, AXI) or simple and well described. Problems at the interface level can often be solved with a scope shot of the interface signals.

Nevertheless, customer designs using the PLB or AXI on-chip bus can easily be simulated using a Bus Functional Model of the on-chip bus slave interface instead of a simulation model of the entire EtherCAT IP Core.

From the processor’s view, the EtherCAT IP Core is a memory (or a bunch of registers). For processor

bus verification, the EtherCAT IP Core can be substituted by another IP core with PLB/AXI slave interface which behaves like a memory as well. The EtherCAT IP Core can be replaced for simulation by e.g.:

 Xilinx XPS Block RAM (BRAM) Interface Controller with a Block RAM block  PLB Bus Functional models of the “IBM On-Chip Bus Model Toolkits”. This toolkit can be used for

complete verification of your PLB bus interfaces.

 AXI slave Bus Functional models

III-12 Slave Controller – IP Core for Xilinx FPGAs

Features and Registers

Feature

IP Core

Xilinx® V3.00k

IP Core

Xilinx®

V3.00c-

3.00j

EtherCAT Ports

1-3

Permanent ports

1-3

Optional Bridge port 3 (EBUS or

MII)

EBUS ports

MII ports

0-3

RMII ports

0-2

RGMII ports

0-3

Port 0

Ports 0, 1

x x Ports 0, 1, 2

Ports 0, 1, 3

Ports 0, 1, 2, 3

EtherCAT mode

Direct

Slave Category

Full Slave

Position addressing

x x Node addressing

Logical addressing

Broadcast addressing

Physical Layer General Features

FIFO Size configurable

(0x0100[18:16])

FIFO Size default from SII

EEPROM

Auto-Forwarder checks CRC and

SOF

Forwarded RX Error indication,

detection and Counter (0x0308:0x030B)

Lost Link Counter

(0x0310:0x0313)

Prevention of circulating frames

Fallback: Port 0 opens if all ports

are closed

VLAN Tag and IP/UDP support

Enhanced Link Detection per port

configurable

General Ethernet Features (MII/RMII/RGMII)

MII Management Interface

(0x0510:0x051F)

Supported PHY Address Offsets

any

Individual port PHY addresses

x x Port PHY addresses readable

x x Link Polarity configurable

User logic

Enhanced Link Detection

supported

FX PHY support (native)

PHY reset out signals

Link detection using PHY signal

(LED)

MI link status and configuration

MI controllable by PDI

(0x0516:0x0517)

MI read error (0x0510.13)

MI PHY configuration update

status (0x0518.5)

MI preamble suppression

x x Additional MCLK

Gigabit PHY configuration

Gigabit PHY register 9 relaxed

check

FX PHY configuration

x x Transparent Mode

Feature

IP Core

Xilinx® V3.00k

IP Core

Xilinx®

V3.00c-

3.00j

MII Features

CLK25OUT as PHY clock source

User logic

Bootstrap TX Shift settings

Automatic TX Shift setting (with

TX_CLK)

TX Shift not necessary (PHY

TX_CLK as clock source)

FIFO size reduction steps

PDI General Features

Increased PDI performance

Extended PDI Configuration

(0x0152:0x0153)

PDI Error Counter (0x030D)

PDI Error Code (0x030E)

CPU_CLK output (10, 20, 25

MHz)

User logic

SOF, EOF, WD_TRIG and

WD_STATE independent of PDI

Available PDIs and PDI features

depending on port configuration

PDI selection at run-time (SII

EEPROM)

PDI active immediately (SII

EEPROM settings ignored)

PDI function acknowledge by

write

PDI Information register

0x014E:0x014F

Digital I/O PDI

Digital I/O width [bits]

8/16/24/32

PDI Control register value

(0x0140:0x0141)

Control/Status signals:

7 7 LATCH_IN

x x SOF

x x OUTVALID

x x WD_TRIG

x x OE_CONF

- - OE_EXT

EEPROM_

Loaded

WD_STATE

EOF

Granularity of direction

configuration [bits]

8 8 Bidirectional mode

- (User logic)

Output high-Z if WD expired

User logic

Output 0 if WD expired

Output with EOF

Output with DC SyncSignals

Input with SOF

Input with DC SyncSignals

x x SPI Slave PDI

Max. SPI clock [MHz]

SPI modes configurable

(0x0150[1:0])

SPI_IRQ driver configurable

(0x0150[3:2])

SPI_SEL polarity configurable

(0x0150.4)

Data out sample mode

configurable (0x0150.5)

Busy signaling

2 Features and Registers

2.1 Features

Table 7: IP Core Feature Details

Slave Controller – IP Core for Xilinx FPGAs III-13

Features and Registers

Feature

IP Core

Xilinx® V3.00k

IP Core

Xilinx®

V3.00c-

3.00j

Wait State byte(s)

Number of address extension

byte(s)

any

2/4 Byte SPI master support

Extended error detection (read

busy violation)

SPI_IRQ delay

Status indication

EEPROM_

Loaded signal

Asynchronous µController PDI

8/16 bit

Extended µC configuration bits

0x0150[7:4], 0x0152:0x0153

ADR[15:13] available (000b if not

available)

EEPROM_Loaded signal

RD polarity configurable

(0x0150.7)

Read BUSY delay (0x0152.0)

Write after first edge (0x0152.2)

Synchronous µController PDI

On-Chip Bus PDI

Avalon®

OPB®

- - PLB v4.6®

AXI3TM

AXI4TM

x x AXI4 LITETM

Bus clock [MHz] (N=1,2,3,…)

any

Data bus width [bits]

8/16/32/64

Prefetch cycles

DC SyncSignals available directly

and as IRQ

Bus clock multiplier in register

0x0150[6:0]

EEPROM_

Loaded signal

EtherCAT Bridge (port 3, EBUS/MII)

General Purpose I/O

GPO bits

0/8/16/

32/64

0/8/16/

32/64

GPI bits

0/8/16/

32/64

0/8/16/

32/64

GPIO available independent of

PDI or port configuration

GPIO available without PDI

Concurrent access to GPO by

ECAT and PDI

ESC Information

Basic Information

(0x0000:0x0006)

Port Descriptor (0x0007)

ESC Features supported

(0x0008:0x0009)

Extended ESC Feature

Availability in User RAM (0x0F80 ff.)

Write Protection (0x0020:0x0031)

Data Link Layer Features

ECAT Reset (0x0040)

c c PDI Reset (0x0041)

ESC DL Control (0x0100:0x0103)

bytes

EtherCAT only mode (0x0100.0)

Temporary loop control

(0x0100.1)

FIFO Size configurable

(0x0100[18:16])

Configured Station Address

(0x0010:0x0011)

Configured Station Alias

(0x0100.24, 0x0012:0x0013)

Feature

IP Core

Xilinx® V3.00k

IP Core

Xilinx®

V3.00c-

3.00j

Physical Read/Write Offset

(0x0108:0x0109)

Application Layer Features

Extended AL Control/Status bits

(0x0120[15:5], 0x0130[15:5])

AL Status Emulation (0x0140.8)

AL Status Code (0x0134:0x0135)

c c Interrupts

ECAT Event Mask

(0x0200:0x0201)

AL Event Mask (0x0204:0x0207)

ECAT Event Request

(0x0210:0x0211)

AL Event Request

(0x0220:0x0223)

SyncManager activation changed

(0x0220.4)

SyncManager watchdog

expiration (0x0220.6)

Error Counters

RX Error Counter

(0x0300:0x0307)

Forwarded RX Error Counter

(0x0308:0x030B)

ECAT Processing Unit Error

Counter (0x030C)

PDI Error Counter (0x030D)

Lost Link Counter

(0x0310:0x0313)

Watchdog

Watchdog Divider configurable

(0x0400:0x0401)

Watchdog Process Data

x x Watchdog PDI

Watchdog Counter Process Data

(0x0442)

Watchdog Counter PDI (0x0443)

x x SII EEPROM Interface (0x0500:0x050F)

EEPROM sizes supported

1 Kbyte-

4 Mbyte

1 Kbyte-

4 Mbyte

EEPROM size reflected in

0x0502.7

EEPROM controllable by PDI

EEPROM Emulation by PDI

EEPROM Emulation CRC error

0x0502[11] PDI writable

Read data bytes (0x0502.6)

Internal Pull-Ups for

EEPROM_CLK and EEPROM_DATA

User logic

FMMUs

0-8

Bit-oriented operation

SyncManagers

0-8

Watchdog trigger generation for 1

Byte Mailbox configuration independent of reading access

SyncManager Event Times

(+0x8[7:6])

Buffer state (+0x5[7:6])

Distributed Clocks

Width

32/64

Sync/Latch signals

(0-2 Sync-

Signals,

0- 2 Latch-

Signals)

(0-2 Sync-

Signals,

0- 2

Latch-

Signals)

SyncManager Event Times

(0x09F0:0x09FF)

DC Receive Times

DC Time Loop Control

controllable by PDI

DC activation by EEPROM

(0x0140[11:10])

III-14 Slave Controller – IP Core for Xilinx FPGAs

Features and Registers

Feature

IP Core

Xilinx® V3.00k

IP Core

Xilinx®

V3.00c-

3.00j

Propagation delay measurement

with traffic (BWR/FPWR 0x900 detected at each port)

LatchSignal state in Latch Status

SyncSignal Auto-Activation

(0x0981.3)

SyncSignal 32 or 64 bit Start Time

(0x0981.4)

SyncSignal Late Activation

(0x0981[6:5])

SyncSignal debug pulse

(0x0981.7)

SyncSignal Activation State

0x0984)

Reset filters after writing filter

depth

ESC Specific Registers (0x0E00:0x0EFF)

Product and Vendor ID

POR Values

FPGA Update (online)

Process RAM and User RAM

Process RAM (0x1000 ff.) [Kbyte]

0-60

User RAM (0x0F80:0x0FFF)

Extended ESC Feature

Availability in User RAM

Additional EEPROMs

1-2

SII EEPROM (I²C)

(EEPROM

of µC used)

(EEPROM

of µC used)

FPGA configuration EEPROM

LED Signals

RUN LED

c c RUN LED override

c c Link/Activity(x) LED per port

x x PERR(x) LED per port

- - Device ERR LED

c c STATE_RUN LED

Optional LED states

RUN LED: Bootstrap

RUN LED: Booting

RUN LED: Device identification

RUN LED: loading SII EEPROM

Error LED: SII EEPROM loading

error

Error LED: Invalid hardware

configuration

Feature

IP Core

Xilinx® V3.00k

IP Core

Xilinx®

V3.00c-

3.00j

Error LED: Process data

watchdog timeout

Error LED: PDI watchdog timeout

Link/Activity: local auto-

negotiation error

Link/Activity: remote auto-

negotiation error

Link/Activity: unknown PHY auto-

negotiation error

LED test

Clock supply

Crystal

- - Crystal oscillator

TX_CLK from PHY

25ppm clock source accuracy

x x Internal PLL

User logic

Power Supply Voltages

FPGA dep.

FPGA

dep.

I/O Voltage

FPGA dep.

FPGA

dep.

Core Voltage

FPGA dep.

FPGA

dep.

Internal LDOs

Package

FPGA dep.

FPGA

dep.

Original Release date

1/2015

5/2013

Configuration and Pinout calculator (XLS)

individual

Complete IP Core evaluation

License device required

Example designs/ pre-synthesized time-limited evaluation

core included

3/3

4/3

LX150T Digital I/O

x/x

LX150T AXI

x/x

ZC702 AXI (PlanAhead)

x/x

ZC702 AXI (Vivado)

x/x

x/-

Symbol

Description

available

not available

configurable

User logic

Functionality can be added by user logic inside the FPGA

red

Feature changed in this version

Table 8: Legend

Slave Controller – IP Core for Xilinx FPGAs III-15

Features and Registers

Address

Length (Byte)

Description

IP Core V3.00c-

V3.00k

0x0000

Type x 0x0001

Revision

0x0002:0x0003

Build

0x0004

FMMUs supported

0x0005

SyncManagers supported

0x0006

RAM Size

0x0007

Port Descriptor

0x0008:0x0009

ESC Features supported

0x0010:0x0011

Configured Station Address

0x0012:0x0013

Configured Station Alias

0x0020

Write Register Enable

0x0021

Write Register Protection

0x0030

ESC Write Enable

0x0031

ESC Write Protection

0x0040

ESC Reset ECAT

0x0041

ESC Reset PDI

0x0100:0x0101

ESC DL Control

0x0102:0x0103

Extended ESC DL Control

0x0108:0x0109

Physical Read/Write Offset

0x0110:0x0111

ESC DL Status

0x0120

5 bits

[4:0]

AL Control

0x0120:0x0121

AL Control

0x0130

5 bits

[4:0]

AL Status

0x0130:0x0131

AL Status

0x0134:0x0135

AL Status Code

0x0138

RUN LED Override

0x0139

ERR LED Override

0x0140

PDI Control

0x0141

ESC Configuration

0x014E:0x014F

PDI Information

0x0150

PDI Configuration

0x0151

DC Sync/Latch Configuration

0x0152:0x0153

Extended PDI Configuration

0x0200:0x0201

ECAT Event Mask

0x0204:0x0207

PDI0 AL Event Mask

r/c

2.2 Registers

An EtherCAT Slave Controller (ESC) has an address space of 64KByte. The first block of 4KByte (0x0000:0x0FFF) is dedicated for registers. The process data RAM starts at address 0x1000, its size is configurable.

Some registers are implemented depending on the configuration. Table 9 gives an overview of the available registers.

Table 9: Register availability

III-16 Slave Controller – IP Core for Xilinx FPGAs

Features and Registers

Address

Length (Byte)

Description

IP Core V3.00c-

V3.00k

0x0210:0x0211

ECAT Event Request

0x0220:0x0223

AL Event Request

0x0300:0x0307

4x2

Rx Error Counter[3:0]

0x0308:0x030B

4x1

Forwarded Rx Error counter[3:0]

0x030C

ECAT Processing Unit Error Counter c 0x030D

PDI Error Counter

0x030E

PDI Error Code

0x0310:0x0313

4x1

Lost Link Counter[3:0]

0x0400:0x0401

Watchdog Divider

r/c

0x0410:0x0411

Watchdog Time PDI

0x0420:0x0421

Watchdog Time Process Data

0x0440:0x0441

Watchdog Status Process Data

0x0442

Watchdog Counter Process Data c 0x0443

Watchdog Counter PDI

0x0500:0x050F

SII EEPROM Interface

0x0510:0x0515

MII Management Interface

0x0516:0x0517

MII Management Access State

0x0518:0x051B

PHY Port Status[3:0]

0x0600:0x06FC

16x13

FMMU[15:0]

0-8

0x0800:0x087F

16x8

SyncManager[15:0]

0-8

0x0900:0x090F

4x4

DC – Receive Times[3:0]

0x0910:0x0917

DC – System Time

0x0918:0x091F

DC – Receive Time EPU

0x0920:0x0935

DC – Time Loop Control Unit

0x0936

DC – Receive Time Latch mode

0x0980

DC – Cyclic Unit Control

0x0981

DC – Activation

0x0982:0x0983

DC – Pulse length of SyncSignals

0x0984

DC – Activation Status

0x098E:0x09A7

DC – SYNC Out Unit

0x09A8

DC – Latch0 Control

0x09A9

DC – Latch1 Control

0x09AE

DC – Latch0 Status

0x09B0:0x09B7

DC – Latch0 Positive Edge

0x09B8:0x09BF

DC – Latch0 Negative Edge

0x09C0:0x09C7

DC – Latch1 Positive Edge

0x09C7:0x09CF

DC – Latch1 Negative Edge

0x09F0:0x09F3 0x09F8:0x09FF

DC – SyncManager Event Times

0x0E00:0x0E03

Power-On Values (Bits)

0x0E00:0x0E07

Product ID

Slave Controller – IP Core for Xilinx FPGAs III-17

Features and Registers

Address

Length (Byte)

Description

IP Core V3.00c-

V3.00k

0x0E08:0x0E0F

Vendor ID

0x0F00:0x0F03

Digital I/O Output Data

0x0F10:0x0F17

General Purpose Outputs [Byte]

0-8

0x0F18:0x0F1F

General Purpose Inputs [Byte]

0-8

0x0F80:0x0FFF

128

User RAM

0x1000:0x1003

Digital I/O Input Data

0x1000 ff.

Process Data RAM [Kbyte]

1-60

Symbol

Description

Available

Not available

Read only

Configurable

Available if Distributed Clocks with all Sync/Latch signals are enabled

Available if Receive Times or Distributed Clocks are enabled (always available for 3-4 ports)

Available if Digital I/O PDI is selected

red

Table 10: Legend

III-18 Slave Controller – IP Core for Xilinx FPGAs

+ 114 hidden pages

BECKHOFF EtherCAT IP Core for Xilinx FPGAs User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Section III – Hardware Description

DOCUMENT ORGANIZATION

DOCUMENT HISTORY

CONTENTS

TABLES

FIGURES

ABBREVIATIONS

1 Overview

1.1 Frame processing order

1.2 Scope of this document

1.3 Scope of Delivery

1.4 Target FPGAs

1.5 Designflow requirements

1.6 Tested FPGA/Designflow combinations

1.7 Release Notes

1.7.1 Major differences between V2.04x and V3.00x

1.7.2 Reading IP Core version from device

1.8 Design flow

1.9 IP Core Evaluation

1.10 Simulation

2 Features and Registers

2.1 Features

2.2 Registers