BECKHOFF ET1200 User Manual

Hardware Data Sheet ET1200

Slave Controller

Section I – Technology (Online at http://www.beckhoff.com)

Section II – Register Description (Online at http://www.beckhoff.com)

Section III – Hardware Description

Pinout, Interface description, electrical

and mechanical specification, ET1200 features and registers

Version 1.8 Date: 2014-07-07

DOCUMENT ORGANIZATION

Trademarks

Beckhoff®, TwinCAT®, EtherCAT®, Safety over EtherCAT®, TwinSAFE® and XFC® are registered trademarks of and licensed by Beckhoff Automation GmbH. Other designations used in this publication may be trademarks whose use by third parties for their own purposes could violate the rights of the owners.

Patent Pending

The EtherCAT Technology is covered, including but not limited to the following German patent applications and patents: DE10304637, DE102004044764, DE102005009224, DE102007017835 with corresponding applications or registrations in various other countries.

Disclaimer

The documentation has been prepared with care. The products described are, however, constantly under development. For that reason the documentation is not in every case checked for consistency with performance data, standards or other characteristics. In the event that it contains technical or editorial errors, we retain the right to make alterations at any time and without warning. No claims for the modification of products that have already been supplied may be made on the basis of the data, diagrams and descriptions in this documentation.

Copyright

© Beckhoff Automation GmbH 07/2014. The reproduction, distribution and utilization of this document as well as the communication of its contents to others without express authorization are prohibited. Offenders will be held liable for the payment of damages. All rights reserved in the event of the grant of a patent, utility model or design.

DOCUMENT ORGANIZATION

The Beckhoff EtherCAT Slave Controller (ESC) documentation covers the following Beckhoff ESCs:

 ET1200  ET1100  EtherCAT IP Core for Altera® FPGAs  EtherCAT IP Core for Xilinx® FPGAs  ESC20

The documentation is organized in three sections. Section I and section II are common for all Beckhoff ESCs, Section III is specific for each ESC variant.

The latest documentation is available at the Beckhoff homepage (http://www.beckhoff.com).

Section I – Technology (All ESCs)

Section I deals with the basic EtherCAT technology. Starting with the EtherCAT protocol itself, the frame processing inside EtherCAT slaves is described. The features and interfaces of the physical layer with its two alternatives Ethernet and EBUS are explained afterwards. Finally, the details of the functional units of an ESC like FMMU, SyncManager, Distributed Clocks, Slave Information Interface, Interrupts, Watchdogs, and so on, are described.

Since Section I is common for all Beckhoff ESCs, it might describe features which are not available in a specific ESC. Refer to the feature details overview in Section III of a specific ESC to find out which features are available.

Section II – Register Description (All ESCs)

Section II contains detailed information about all ESC registers. This section is also common for all Beckhoff ESCs, thus registers, register bits, or features are described which might not be available in a specific ESC. Refer to the register overview and to the feature details overview in Section III of a specific ESC to find out which registers and features are available.

Section III – Hardware Description (Specific ESC)

Section III is ESC specific and contains detailed information about the ESC features, implemented registers, configuration, interfaces, pinout, usage, electrical and mechanical specification, and so on. Especially the Process Data Interfaces (PDI) supported by the ESC are part of this section.

Additional Documentation

Application notes and utilities like pinout configuration tools for ET1200 can also be found at the Beckhoff homepage.

III-II Slave Controller – ET1200 Hardware Description

DOCUMENT HISTORY

Version

Comment

0.1

Initial release

0.2

Editorial changes

0.3

Register overview, PDI, Electrical and mechanical spec

0.4

Abbreviations, editorial changes

0.5

 Removed RJ45 description (will become part of Section I)  EEPROM_LOADED pull-down resistor recommendation added  Frame processing order example corrected  I2C EEPROM interface description added  MII management interface description added  Corrected Process RAM size in Register Overview  Revision/Build information added  Recommendations for unused input pins added (should not be left open)  EEPROM_SIZE description corrected from Kbyte to Kbit, possible EEPROM

sizes range from 16 Kbit to 4 Mbit

 RoHS compliance added  Autonegotiation is mandatory for ESCs  Description of power supply options added  Electrical characteristics added  SPI_IRQ delay added  TX Shift timing diagram and description added  Pin overview table corrected  Internal 27 kΩ PU/PD resistors at EBUS-RX pins added  LED polarity depending on configuration pin setting described  Recommendation for voltage stabilization capacitors added  Description of Digital I/O behavior on watchdog expiration enhanced  EBUS ports are open failsafe  Reset example schematic added  Ethernet PHY requirements and PHY connection schematic added  MI_DATA pull-up requirement added  Editorial changes

1.0

 RUN, LINKACT/x) and PERR(x) LED activity level corrected: active high if

pulled down, active low if pulled up

 TX Shift description: timing figures corrected, minor changes, moved to MII

Interface chapter

 Pin/Signal description overview added  PERR(x) LEDs are only for testing/debugging  Electrical characteristics enhanced  DC Characteristics enhanced: added V

Reset Core

, VID, VIC

 Digital I/O and SPI timing characteristics revised  DC SYNC/LATCH signal description and timing characteristics added  MII Interface chapter and MII timing characteristics added  EBUS Interface chapter added  PHY requirements, EEPROM Interface description and MII Management

Interface description moved to Section I

 Ambient temperature range instead of junction temperature range  Editorial changes

DOCUMENT HISTORY

Slave Controller – ET1200 Hardware Description III-III

DOCUMENT HISTORY

Version

Comment

1.1

 Clarified I/O voltage with respect to I/O power supply (only 3.3V I/O with

V

CCI/O

=3.3V, and no 5V input tolerance unless V

CCI/O

=5V)

 Update to ET1200 stepping 1  Added/revised OSC_IN, CLK25OUT, and MII TX signal timings  Added soldering profile  PHY address configuration changed  Added feature detail overview, removed redundant feature details  PDI and DC SYNC/LATCH signals are not driven until EEPROM is loaded  Editorial changes

1.2

 PHY address configuration chapter added, configuration revised  Enhanced link detection for MII available depending on PHY address

configuration

 Ethernet Management Interface: read and write times were interchanged  Editorial changes

1.3

 Added reset timing figure and power-on value sample time  Direction of Distributed Clocks SYNC/LATCH signals is configurable  Information on CLK25OUT/CPU_CLK clock output during reset added  Description of internal PU/PD resistors at EBUS_RX pins enhanced  Power supply example schematic clarified  Enhanced package information: MSL and plating material  Digital I/O PDI: added SOF/OUTVALID description  SPI PDI: Read busy signaling not recommended  Editorial changes

1.4

 OSC_IN/OSC_OUT pin capacitance added, crystal connection note extended  Release Notes added  Input threshold voltage for OSC_IN added  Renamed Err(x) LED to PERR(x)  Digital I/O PDI: OE_CONF functionality in bidirectional mode corrected  Digital I/O PDI: output event description corrected (EOF mode and WD_TRIG

mode)

 SPI PDI: access error if SPI_DI not 1 in the last read byte (not SPI_DO)  AC timing: forwarding delay figures added  Editorial changes

1.5

 AC timing: forwarding delay figures MII to MII added  Reset timing figure corrected  Maximum soldering profile added  SPI PDI updated  SII EEPROM interface is a point-to-point connection  Editorial changes

1.6

 Update to ET1200-0002  Editorial changes

1.7

 Enhanced Link Detection must not be activated if EBUS ports are used  Enhanced Link Detection for MII ports requires PHY address offset = 0  Digital Output principle schematic updated  Chip label updated  Editorial changes

1.8

 Update to ET1200-0003  Enhanced Link Detection for MII ports supports PHY address offset 0 and 16  Enhanced Link Detection for MII ports can be disabled at any time  Enhanced Link Detection for EBUS ports is always disabled  MII management interface issues additional MCLK cycle after write accesses  Remote link down signalling time configurable 0x0100[22]  Editorial changes

III-IV Slave Controller – ET1200 Hardware Description

CONTENTS

TABLES

Table 1: ET1200 Main Features .............................................................................................................. 1

Table 2: Frame Processing Order ........................................................................................................... 2

Table 3: Revision/Build History................................................................................................................ 3

Table 4: ET1200 Feature Details ............................................................................................................ 4

Table 5: Legend ....................................................................................................................................... 6

Table 6: Legend ....................................................................................................................................... 7

Table 7: Register Overview ..................................................................................................................... 7

Table 8: Pin Overview ........................................................................................................................... 10

Table 9: Signal Overview ....................................................................................................................... 11

Table 10: PDI signal overview ............................................................................................................... 12

Table 11: Chip Mode ............................................................................................................................. 13

Table 12: CPU_CLK Mode .................................................................................................................... 13

Table 13: TX Shift .................................................................................................................................. 13

Table 14: CLK_25OUT Enable .............................................................................................................. 14

Table 15: PHY Address Offset .............................................................................................................. 14

Table 16: SII EEPROM Size .................................................................................................................. 14

Table 17: General pins .......................................................................................................................... 15

Table 18: SII EEPROM pins .................................................................................................................. 15

Table 19: DC SYNC/LATCH and MII Management pins ....................................................................... 16

Table 20: LED pins ................................................................................................................................ 16

Table 21: Combinations of Chip modes and PDIs ................................................................................ 17

Table 22: Port 0/1 and PDI signals (Configuration and chip mode 00) ................................................. 19

Table 23: Port 0/1 and PDI signals (chip modes 10/11) ........................................................................ 19

Table 24: PDI pins ................................................................................................................................. 20

Table 25: Mapping of Digital I/O Interface ............................................................................................. 21

Table 26: Mapping of SPI Interface ....................................................................................................... 21

Table 27: Mapping of EBUS Bridge signals .......................................................................................... 22

Table 28: Mapping of MII Bridge signals ............................................................................................... 22

Table 29: Power supply options (all voltages nomal) ............................................................................ 23

Table 30: Power supply ......................................................................................................................... 23

Table 31: MII Interface signals .............................................................................................................. 25

Table 32: TX Shift Timing characteristics .............................................................................................. 26

Table 33: MII timing characteristics ....................................................................................................... 27

Table 34: EBUS Interface signals ......................................................................................................... 28

Table 35: Available PDIs for ET1200 .................................................................................................... 29

Table 36: ET1200 Digital I/O signals ..................................................................................................... 30

Table 37: Digital I/O timing characteristics ET1200 .............................................................................. 33

Table 38: SPI signals ............................................................................................................................. 35

Table 39: SPI commands CMD0 and CMD1 ......................................................................................... 36

Table 40: Address modes ...................................................................................................................... 36

Table 41: Interrupt request register transmission .................................................................................. 36

Table 42: SPI timing characteristics ET1200 ........................................................................................ 38

Table 43: Read/Write timing diagram symbols ...................................................................................... 39

Table 44: Distributed Clocks signals ..................................................................................................... 43

Table 45: DC SYNC/LATCH timing characteristics ET1200 ................................................................. 43

Table 46: I²C EEPROM signals ............................................................................................................. 44

Table 47: EEPROM timing characteristics ............................................................................................ 44

Table 48: Absolute Maximum Ratings ................................................................................................... 49

Table 49: Operating Conditions ............................................................................................................. 49

Table 50: DC Characteristics ................................................................................................................. 50

Table 51: DC Characteristics (Supply current) ...................................................................................... 51

Table 52: AC Characteristics ................................................................................................................. 52

Table 53: Forwarding Delays ................................................................................................................. 54

Table 54: Absolute Maximum Storage Conditions ................................................................................ 57

Table 55: Example Soldering Profile ..................................................................................................... 59

III-VIII Slave Controller – ET1200 Hardware Description

FIGURES

Figure 1: ET1200 Block Diagram ............................................................................................................ 1

Figure 2: Frame Processing .................................................................................................................... 2

Figure 3: MII Interface signals ............................................................................................................... 24

Figure 4: TX Shift Timing Diagram ........................................................................................................ 26

Figure 5: MII timing RX signals.............................................................................................................. 27

Figure 6: EBUS Interface Signals .......................................................................................................... 28

Figure 7: ET1200 Digital I/O Signals ..................................................................................................... 30

Figure 8: Digital Output Principle Schematic ......................................................................................... 31

Figure 9: Bidirectional mode: Input/Output connection (R=4.7 kΩ recommended) .............................. 32

Figure 10: Digital Input: Input data sampled at SOF, I/O can be read in the same frame .................... 34

Figure 11: Digital Input: Input data sampled with LATCH_IN ................................................................ 34

Figure 12: Digital Output timing ............................................................................................................. 34

Figure 13: Bidirectional Mode timing ..................................................................................................... 34

Figure 14: SPI master and slave interconnection.................................................................................. 35

Figure 15: Basic SPI_DI/SPI_DO timing (*refer to timing diagram for relevant edges of SPI_CLK) .... 39

Figure 16: SPI read access (2 byte addressing, 2 byte read data) with BUSY and separate status

reading ................................................................................................................................................... 40

Figure 17: SPI write access (2 byte addressing, 1 byte write data) ...................................................... 41

Figure 18: SPI write access (3 byte addressing, 1 byte write data) ...................................................... 42

Figure 19: Distributed Clocks signals .................................................................................................... 43

Figure 20: LatchSignal timing ................................................................................................................ 43

Figure 21: SyncSignal timing ................................................................................................................. 43

Figure 22: I²C EEPROM signals ............................................................................................................ 44

Figure 23: Quartz crystal connection ..................................................................................................... 45

Figure 24: Quartz crystal Clock source for ET1200 and Ethernet PHYs .............................................. 45

Figure 25: Oscillator clock source for ET1200 and Ethernet PHYs ...................................................... 46

Figure 26: ET1200 power supply........................................................................................................... 46

Figure 27: Dual purpose configuration input/LED output pins ............................................................... 47

Figure 28: PHY Connection ................................................................................................................... 47

Figure 29: LVDS termination ................................................................................................................. 48

Figure 30: RBIAS resistor ...................................................................................................................... 48

Figure 31: Reset Logic .......................................................................................................................... 48

Figure 32: Reset Timing ........................................................................................................................ 53

Figure 33: Package Outline ................................................................................................................... 55

Figure 34: Dimensions ........................................................................................................................... 56

Figure 35: Notes .................................................................................................................................... 56

Figure 36: Chip Label ............................................................................................................................ 56

Figure 37: Maximum Soldering Profile .................................................................................................. 58

Figure 38: Example Soldering Profiles .................................................................................................. 58

Slave Controller – ET1200 Hardware Description III-IX

ABBREVIATIONS

(x)

Logical Port x

[z]

Bit z

{y}

Physical Port y

µC

Microcontroller

ADR

Address

AL

Application Layer

BD

Bidirectional

BHE

Bus High Enable

CMD

Command

DC

Distributed Clock

Dir.

Pin direction

DL

Data Link Layer

ECAT

EtherCAT

EMC

Electromagnetic Compatibility

EMI

Electromagnetic Interference

EOF

End of Frame

EP

Exposed Pad

ESC

EtherCAT Slave Controller

ESI

EtherCAT Slave Information

FMMU

Fieldbus Memory Management Unit

GPI

General Purpose Input

GPO

General Purpose Output

I

Input

I/O

Input or Output

IRQ

Interrupt Request

LDO

Low Drop-Out regulator

LI-

LVDS RX-

LI+

LVDS RX+

LO-

LVDS TX-

LO+

LVDS TX+

MAC

Media Access Controller

MDIO

Management Data Input / Output

MI

(PHY) Management Interface

MII

Media Independent Interface

MISO

Master In – Slave Out

MOSI

Master Out – Slave In

n.a.

not available

n.c.

not connected

O

Output

PD

Pull-down

PDI

Process Data Interface

PLL

Phase Locked Loop

PU

Pull-up

QFN

Quad Flat package No leads

SII

Slave Information Interface

SM

SyncManager

SOF

Start of Frame

SPI

Serial Peripheral Interface

UI

Unused Input (PDI: PD, others: GND)

WD

Watchdog

WPD

Weak Pull-down, sufficient only for configuration signals

WPU

Weak Pull-up, sufficient only for configuration signals

ABBREVIATIONS

III-X Slave Controller – ET1200 Hardware Description

Overview

Feature

ET1200

Ports

2 permanent ports, optional one additional bridge port (each EBUS or MII, max. one MII port)

FMMUs

3

SyncManagers

4

RAM

1 Kbyte

Distributed Clocks

Yes, 64 bit

Process Data Interfaces

 16 Bit Digital I/O (unidirectional/bidirectional)  SPI Slave

Power supply

Two integrated voltage regulators (LDO) for I/O (5V to 3.3V) and logic core/PLL (5V/3.3V to 2.5V), optional external power supply for I/O and logic core/PLL.

I/O

3.3V compatible I/O

Package

QFN48 (7x7 mm2)

Other features

 Internal 1GHz PLL  Clock output for external devices (10, 20, 25 MHz)

ECAT Processing Unit

AutoForwarder +

Loopback

SyncManager

FMMU

ESC address space

User RAMRegisters Process RAM

EEPROM

Distributed

Clocks

Monitoring Status

Reset

PHY

Management

Reset

SYNC LEDsI²C EEPROM

PHY MI

SPI / Digital I/O0 1 3

EBUS/MII ports

LATCH

PDI

ECAT Interface PDI Interface

1 Overview

The ET1200 ASIC is an EtherCAT Slave Controller (ESC). It takes care of the EtherCAT communication as an interface between the EtherCAT fieldbus and the slave application. The ET1200 supports different applications, from simple digital I/O nodes without external logic up to designs with a µController and Distributed Clocks.

Table 1: ET1200 Main Features

The general functionality of the ET1200 EtherCAT Slave Controller (ESC) is shown in Figure 1:

Slave Controller – ET1200 Hardware Description III-1

Figure 1: ET1200 Block Diagram

Overview

Number of Ports

Frame processing order

2

0→EtherCAT Processing Unit→1 / 1→0

3

0→EtherCAT Processing Unit→3 / 3→1 / 1→0

1

Port 1

Auto-

Forwarder

1

Port 3

Auto-

Forwarder

Port 0

Auto-

Forwarder

Loopback function

EtherCAT

Processing Unit

Loopback function

ET1200

port 1 closed

port 1 open

port 3 open

port 3 closed

port 0 open

or all ports

closed

port 0 closed

1.1 Frame processing order

The ET1200 supports two ports (logical ports 0 and 1) or three ports (logical ports 0, 1, and 3). The frame processing order of the ET1200 depends on the number of ports (logical port numbers are used):

Table 2: Frame Processing Order

Figure 2 shows the frame processing in general:

Figure 2: Frame Processing

III-2 Slave Controller – ET1200 Hardware Description

Overview

Revision Register 0x0001

Build Register 0x0002:0x0003

Stepping

0x00

0x0000

ET1200-0000 or ET1200-0001

0x00

0x0002

ET1200-0002

0x00

0x0003

ET1200-0003

1.2 Scope of this document

This documentation refers to stepping ET1200-0003.

1.3 Revision/Build History

Table 3: Revision/Build History

The stepping code is printed on the devices, do not confuse the stepping code with the ordering codes.

Slave Controller – ET1200 Hardware Description III-3

Features and Registers

Feature

ET1200

-0003

EtherCAT Ports

2-3

Permanent ports

2

Optional Bridge port 3 (EBUS or MII)

c

EBUS ports

1-3

MII ports

0-1

RMII ports

-

RGMII ports

-

Port 0

-

Ports 0, 1

x

Ports 0, 1, 2

-

Ports 0, 1, 3

x

Ports 0, 1, 2, 3

-

Slave Category

Full Slave

Position addressing

x

Node addressing

x

Logical addressing

x

Broadcast addressing

x

Physical Layer General Features

FIFO Size configurable (0x0100[18:16])

x

FIFO Size default from SII EEPROM

-

Auto-Forwarder checks CRC and SOF

x

Forwarded RX Error indication, detection

and Counter (0x0308:0x030B)

x

Lost Link Counter (0x0310:0x0313)

x

Prevention of circulating frames

x

Fallback: Port 0 opens if all ports are

closed

x

VLAN Tag and IP/UDP support

x

Enhanced Link Detection per port

configurable

-

EBUS Features

Low Jitter

x

Enhanced Link Detection supported

-

Enhanced Link Detection compatible

X

EBUS signal validation

X

LVDS Transceiver internal

X

LVDS sample rate [MHz]

1,000

Remote link down signaling time

configurable 0x0100[22]

x

General Ethernet Features (MII/RMII/RGMII)

MII Management Interface

(0x0510:0x051F)

x

Supported PHY Address Offsets

0/16

Individual port PHY addresses

-

Port PHY addresses readable

-

Link Polarity configurable

-

Enhanced Link Detection supported

x

FX PHY support (native)

-

PHY reset out signals

-

Link detection using PHY signal (LED)

x

MI link status and configuration

-

MI controllable by PDI (0x0516:0x0517)

-

MI read error (0x0510.13)

-

MI PHY configuration update status

(0x0518.5)

-

MI preamble suppression

-

Additional MCLK

x

Gigabit PHY configuration

-

Gigabit PHY register 9 relaxed check

-

FX PHY configuration

-

Transparent Mode

-

Feature

ET1200

-0003

MII Features

CLK25OUT as PHY clock source

x

Bootstrap TX Shift settings

x

Automatic TX Shift setting (with TX_CLK)

-

TX Shift not necessary (PHY TX_CLK as

clock source)

-

FIFO size reduction steps

1

PDI General Features

Increased PDI performance

-

Extended PDI Configuration

(0x0152:0x0153)

x

PDI Error Counter (0x030D)

-

PDI Error Code (0x030E)

-

CPU_CLK output (10, 20, 25 MHz)

x

SOF, EOF, WD_TRIG and WD_STATE

independent of PDI

-

Available PDIs and PDI features

depending on port configuration

x

PDI selection at run-time (SII EEPROM)

x

PDI active immediately (SII EEPROM

settings ignored)

-

PDI function acknowledge by write

-

PDI Information register 0x014E:0x014F

-

Digital I/O PDI

x

Digital I/O width [bits]

8/16

PDI Control register value

(0x0140:0x0141)

4

Control/Status signals:

2/0

1,2

LATCH_IN

x2

SOF

x2

OUTVALID

x2

WD_TRIG

x2

OE_CONF

-

OE_EXT

-

EEPROM_

Loaded

-

WD_STATE

-

EOF

-

Granularity of direction configuration [bits]

2

Bidirectional mode

x

Output high-Z if WD expired

x

Output 0 if WD expired

-

Output with EOF

x

Output with DC SyncSignals

x

Input with SOF

x

Input with DC SyncSignals

x

1

2

2 Features and Registers

2.1 Features

Table 4: ET1200 Feature Details

III-4 Slave Controller – ET1200 Hardware Description

Shared control/status signals: LATCH_IN/SOF and

OUT_VALID/WD_TRIGGER

Availability depending on port configuration

Features and Registers

Feature

ET1200

-0003

SPI Slave PDI

x

Max. SPI clock [MHz]

6-20 (SPI

mode dep.)

SPI modes configurable (0x0150[1:0])

x

SPI_IRQ driver configurable (0x0150[3:2])

x

SPI_SEL polarity configurable (0x0150.4)

x

Data out sample mode configurable

(0x0150.5)

x

Busy signaling

x

Wait State byte(s)

-

Number of address extension byte(s)

1

2/4 Byte SPI master support

-

Extended error detection (read busy

violation)

-

SPI_IRQ delay

x

Status indication

x

EEPROM_

Loaded signal

x

Asynchronous µController PDI

-

Synchronous µController PDI

-

EtherCAT Bridge (port 3, EBUS/MII)

x

General Purpose I/O

x

GPO bits

0-12

GPI bits

-

GPIO available independent of PDI or port

configuration

-

GPIO available without PDI

-

Concurrent access to GPO by ECAT and

PDI

x

ESC Information

Basic Information (0x0000:0x0006)

x

Port Descriptor (0x0007)

x

ESC Features supported (0x0008:0x0009)

x

Extended ESC Feature Availability in User

RAM (0x0F80 ff.)

-

Write Protection (0x0020:0x0031)

x

Data Link Layer Features

ECAT Reset (0x0040)

x

PDI Reset (0x0041)

-

ESC DL Control (0x0100:0x0103) bytes

4

EtherCAT only mode (0x0100.0)

x

Temporary loop control (0x0100.1)

x

FIFO Size configurable (0x0100[18:16])

x

Configured Station Address

(0x0010:0x0011)

x

Configured Station Alias (0x0100.24,

0x0012:0x0013)

x

Physical Read/Write Offset

(0x0108:0x0109)

x

Application Layer Features

Extended AL Control/Status bits

(0x0120[15:5], 0x0130[15:5])

x

AL Status Emulation (0x0140.8)

x

AL Status Code (0x0134:0x0135)

x

Interrupts

ECAT Event Mask (0x0200:0x0201)

x

AL Event Mask (0x0204:0x0207)

x

ECAT Event Request (0x0210:0x0211)

x

AL Event Request (0x0220:0x0223)

x

SyncManager activation changed

(0x0220.4)

x

SyncManager watchdog expiration

(0x0220.6)

-

Error Counters

RX Error Counter (0x0300:0x0307)

x

Forwarded RX Error Counter

(0x0308:0x030B)

x

ECAT Processing Unit Error Counter

(0x030C)

-

PDI Error Counter (0x030D)

-

Lost Link Counter (0x0310:0x0313)

x

Feature

ET1200

-0003

Watchdog

Watchdog Divider configurable

(0x0400:0x0401)

x

Watchdog Process Data

x

Watchdog PDI

x

Watchdog Counter Process Data (0x0442)

x

Watchdog Counter PDI (0x0443)

x

SII EEPROM Interface (0x0500:0x050F)

EEPROM sizes supported

1 Kbyte-

4 Mbyte

EEPROM size reflected in 0x0502.7

x

EEPROM controllable by PDI

x

EEPROM Emulation by PDI

-

Read data bytes (0x0502.6)

8

Internal Pull-Ups for EEPROM_CLK and

EEPROM_DATA

x

FMMUs

3

Bit-oriented operation

x

SyncManagers

4

Watchdog trigger generation for 1 Byte

Mailbox configuration independent of reading access

x

SyncManager Event Times (+0x8[7:6])

-

Buffer state (+0x5[7:6])

-

Distributed Clocks

x

Width

64

Sync/Latch signals

1-23

SyncManager Event Times

(0x09F0:0x09FF)

-

DC Receive Times

x

DC Time Loop Control controllable by PDI

-

DC activation by EEPROM

(0x0140[11:10])

-

Propagation delay measurement with

traffic (BWR/FPWR 0x900 detected at each port)

-

LatchSignal state in Latch Status register

(0x09AE:0x09AF)

-

SyncSignal Auto-Activation (0x0981.3)

-

SyncSignal 32 or 64 bit Start Time

(0x0981.4)

-

SyncSignal Late Activation (0x0981[6:5])

-

SyncSignal debug pulse (0x0981.7)

-

SyncSignal Activation State 0x0984)

-

Reset filters after writing filter depth

-

ESC Specific Registers (0x0E00:0x0EFF)

Product and Vendor ID

-

POR Values

x

FPGA Update (online)

-

Process RAM and User RAM

Process RAM (0x1000 ff.) [Kbyte]

1

User RAM (0x0F80:0x0FFF)

x

Extended ESC Feature Availability in User

RAM

-

Additional EEPROMs

1

SII EEPROM (I²C)

x

FPGA configuration EEPROM

-

LED Signals

RUN LED

x

RUN LED override

-

Link/Activity(x) LED per port

x

PERR(x) LED per port

x

Device ERR LED

-

STATE_RUN LED

-

3

Slave Controller – ET1200 Hardware Description III-5

SYNC/LATCH[1] available if no MII port is used.

Features and Registers

Feature

ET1200

-0003

Optional LED states

RUN LED: Bootstrap

x

RUN LED: Booting

-

RUN LED: Device identification

-

RUN LED: loading SII EEPROM

-

Error LED: SII EEPROM loading error

-

Error LED: Invalid hardware configuration

-

Error LED: Process data watchdog timeout

-

Error LED: PDI watchdog timeout

-

Link/Activity: port closed

-

Link/Activity: local auto-negotiation error

-

Link/Activity: remote auto-negotiation error

-

Link/Activity: unknown PHY auto-

negotiation error

-

LED test

-

Clock supply

Crystal

x

Crystal oscillator

x

TX_CLK from PHY

x

25ppm clock source accuracy

x

Internal PLL

x

Feature

ET1200

-0003

Power Supply Voltages

1-3

I/O Voltage

3.3 V

x

3.3V / 5V tolerant

-

5 V

(x)

Core Voltage

2.5V

Internal LDOs

2

LDO supply voltage

3.3V/5V

Core Voltage

x

I/O Voltage

x

Package

QFN48

Size [mm²]

7x7

Original Release date

11/2006

Configuration and Pinout calculator (XLS)

x

Register Configuration

fixed

Symbol

Description

x

available

-

not available

c

configurable

Table 5: Legend

III-6 Slave Controller – ET1200 Hardware Description

Features and Registers

Symbol

Description

x

Available

-

Not available

Address

Length (Byte)

Description

ET1200

0x0000

1

Type x 0x0001

1

Revision

x

0x0002:0x0003

2

Build x 0x0004

1

FMMUs supported

x

0x0005

1

SyncManagers supported

x

0x0006

1

RAM Size

x

0x0007

1

Port Descriptor

x

0x0008:0x0009

2

ESC Features supported

x

0x0010:0x0011

2

Configured Station Address

x

0x0012:0x0013

2

Configured Station Alias

x

0x0020

1

Write Register Enable

x

0x0021

1

Write Register Protection

x

0x0030

1

ESC Write Enable

x

0x0031

1

ESC Write Protection

x

0x0040

1

ESC Reset ECAT

x

0x0041

1

ESC Reset PDI

-

0x0100:0x0101

2

ESC DL Control

x

0x0102:0x0103

2

Extended ESC DL Control

x

0x0108:0x0109

2

Physical Read/Write Offset

x

0x0110:0x0111

2

ESC DL Status

x

0x0120

5 bits

[4:0]

AL Control

x 0x0120:0x0121

2

AL Control

x

0x0130

5 bits

[4:0]

AL Status

x 0x0130:0x0131

2

AL Status

x

0x0134:0x0135

2

AL Status Code

x

0x0138

1

RUN LED Override

-

0x0139

1

ERR LED Override

-

0x0140

1

PDI Control

x

2.2 Register Overview

An EtherCAT Slave Controller (ESC) has an address space of 64 Kbyte. The first block of 4 Kbyte (0x0000:0x0FFF) is dedicated for registers. The process data RAM starts at address 0x1000, its size is 1 Kbyte (end address 0x13FF).

Table 7 gives an overview of the available registers.

Table 6: Legend

Table 7: Register Overview

Slave Controller – ET1200 Hardware Description III-7

Features and Registers

Address

Length (Byte)

Description

ET1200

0x0141

1

ESC Configuration

x

0x014E:0x014F

2

PDI Information

-

0x0150

1

PDI Configuration

x

0x0151

1

DC Sync/Latch Configuration

x

0x0152:0x0153

2

Extended PDI Configuration

x

0x0200:0x0201

2

ECAT Event Mask

x

0x0204:0x0207

4

PDI AL Event Mask

x

0x0210:0x0211

2

ECAT Event Request

x

0x0220:0x0223

4

AL Event Request

x

0x0300:0x0307

4x2

Rx Error Counter[3:0]

x

0x0308:0x030B

4x1

Forwarded Rx Error counter[3:0]

x

0x030C

1

ECAT Processing Unit Error Counter

0x030D

1

PDI Error Counter

-

0x030E

1

PDI Error Code

-

0x0310:0x0313

4x1

Lost Link Counter[3:0]

x

0x0400:0x0401

2

Watchdog Divider

x

0x0410:0x0411

2

Watchdog Time PDI

x

0x0420:0x0421

2

Watchdog Time Process Data

x

0x0440:0x0441

2

Watchdog Status Process Data

x

0x0442

1

Watchdog Counter Process Data

x

0x0443

1

Watchdog Counter PDI

x

0x0500:0x050F

16

SII EEPROM Interface

x

0x0510:0x0515

6

MII Management Interface

x

0x0516:0x0517

2

MII Management Access State

-

0x0518:0x051B

4

PHY Port Status[3:0]

-

0x0600:0x06FC

16x13

FMMU[15:0]

3

0x0800:0x087F

16x8

SyncManager[15:0]

4

0x0900:0x090F

4x4

DC – Receive Times[3:0]

x

0x0918:0x091F

8

DC – Receive Time EPU

x

0x0920:0x0935

24

DC – Time Loop Control Unit

x

0x0910:0x0917

8

DC – System Time

x

0x0936

1

DC – Receive Time Latch mode

x

0x0980

1

DC – Cyclic Unit Control

x

0x0981

1

DC – Activation

x

0x0982:0x0983

2

DC – Pulse length of SyncSignals

x

0x0984

1

DC – Activation Status

-

0x098E:0x09A7

26

DC – SYNC Out Unit

x

0x09A8

1

DC – Latch0 Control

x

0x09A9

1

DC – Latch1 Control

x

III-8 Slave Controller – ET1200 Hardware Description

Features and Registers

Address

Length (Byte)

Description

ET1200

0x09AE

1

DC – Latch0 Status

x

0x09B0:0x09B7

8

DC – Latch0 Positive Edge

x

0x09B8:0x09BF

8

DC – Latch0 Negative Edge

x

0x09C0:0x09C7

8

DC – Latch1 Positive Edge

x

0x09C7:0x09CF

8

DC – Latch1 Negative Edge

x

0x09F0:0x09F3 0x09F8:0x09FF

12

DC – SyncManager Event Times

-

0x0E00:0x0E03

4

Power-On Values (Bits)

8

0x0E00:0x0E07

8

Product ID

-

0x0E08:0x0E0F

8

Vendor ID

-

0x0E10

1

ESC Health Status

-

0x0F00:0x0F03

4

Digital I/O Output Data

x

0x0F10:0x0F17

8

General Purpose Outputs [Byte]

2

0x0F18:0x0F1F

8

General Purpose Inputs [Byte]

-

0x0F80:0x0FFF

128

User RAM

x

0x1000:0x1003

4

Digital I/O Input Data

io

0x1000 ff.

Process Data RAM [Kbyte]

1

Slave Controller – ET1200 Hardware Description III-9

Pin Description

Pin name

Dir.

Int.

PU/PD

Pin name

Dir.

Int.

PU/PD

EP

GND 25

RBIAS

1

TESTMODE

I

WPD

26

Reset

BD

WPU

2

EBUS{1}-RX-/LINK_MII

LI-/I

27 kΩ PU

27

PDI[17]/RX_D[3]

BD 3

EBUS{1}-RX+/RX_ERR

LI+/I

27 kΩ PD

28

PDI[16]/RX_D[2]

BD

4

EBUS{0}-TX-

LO-

29

PDI[15]/RX_D[1]

BD

5

EBUS{0}-TX+

LO+

30

PDI[14]/RX_D[0]

BD 6

V

CC I/O

I/O

31

PDI[13]/RX_DV

BD 7

GND

I/O

I/O*

32

PDI[12]/RX_CLK

BD 8

EBUS{0}-RX-

LI-

27 kΩ PU

33

PDI[11]/TX_D[3]/C25_SHI[1]

BD

9

EBUS{0}-RX+

LI+

27 kΩ PD

34

PDI[10]/TX_D[2]/C25_SHI[0]

BD 10

EBUS{1}-TX-/MI_CLK

LO-/O

35

PDI[9]/TX_D[1]/C25_ENA

BD

11

EBUS{1}-TX+/TX_ENA

LO+/O

36

PDI[8]/TX_D[0]/PHYAD_OFF

BD 12

PERR(0)/CLK_MODE[0]

BD

WPD

37

PDI[7]/CPU_CLK

BD 13

PERR(1)/CLK_MODE[1]

BD

WPD

38

PDI[6]/CLK25OUT

BD 14

VCC 39

PDI[5]

BD

15

GND 40

PDI[4]

BD 16

LINKACT(0)/MODE[0]

BD

WPD

41

V

CC Core

(2,5V)

17

LINKACT(1)/MODE[1]

BD

WPD

42

GND

Core

18

RUN/EEPROM_SIZE

BD

WPD

43

PDI[3]

BD/LI-

27 kΩ PU

19

EEPROM_CLK

BD

3.3 kΩ PU

44

PDI[2]

BD/LI+

27 kΩ PD

20

EEPROM_DATA

BD

3.3 kΩ PU

45

PDI[1]

BD/LO-

21

OSC_IN I 46

PDI[0]

BD/LO+

22

OSC_OUT

O

47

SYNC/LATCH[0]

BD

23

GND

PLL

48

SYNC/LATCH[1]/MI_DATA

BD

24

Vcc

PLL

(2,5V)

3 Pin Description

For pin configuration there is a table calculation file (ET1200 configuration and pinout V<version>.xls) available to make pin configuration easier. This file can be downloaded from the Beckhoff homepage (http://www.beckhoff.com). This documentation supersedes the table calculation file.

Input pins should not be left open/floating. Unused input pins (denoted with direction UI) without external or internal pull-up/pull-down resistor should not be left open. Unused configuration pins should be pulled down if the application allows this (take care of configuration signals in the PDI[17:0] area when bidirectional Digital I/O is used). Unused PDI[17:0] input pins should be pulled down, all other input pins can be connected to GND directly.

Pull-up resistors must connect to V be powered via the resistors and the internal clamping diodes as long as V

, not to a different power source. Otherwise the ET1200 could

CC I/O

is below the other

CC I/O

power source. Internal pull-up/pull-down resistor values shown in the pinout tables are nominal.

3.1 Overview

3.1.1 Pin Overview

Table 8: Pin Overview

NOTE: EP is the exposed center pad at the bottom of the ET1200.

III-10 Slave Controller – ET1200 Hardware Description

Pin Description

Signal

Type

Dir.

Description

C25_ENA

Configuration

I

CLK25OUT Enable: Enable CLK25OUT

C25_SHI[1:0]

Configuration

I

TX Shift: Shifting/phase compensation of MII TX signals

CLK_MODE[1:0]

Configuration

I

CPU_CLK configuration

CLK25OUT

MII O 25 MHz clock source for Ethernet PHY

CPU_CLK

PDI O Clock signal for µController

EBUS{1:0}-RX-

EBUS

LI-

EBUS LVDS receive signal -

EBUS{1:0}-RX+

EBUS

LI+

EBUS LVDS receive signal +

EBUS{1:0}-TX-

EBUS

LO-

EBUS LVDS transmit signal -

EBUS{1:0}-TX+

EBUS

LO+

EBUS LVDS transmit signal +

EEPROM_CLK

EEPROM

BD

EEPROM I2C Clock

EEPROM_DATA

EEPROM

BD

EEPROM I2C Data

EEPROM_SIZE

Configuration

I

EEPROM size configuration

PERR(1:0)

LED O Port receive error LED output (for testing)

GND

Power

Ground

GND

Core

Power

Core logic ground

GND

I/O

Power

I/O ground

GND

PLL

Power

PLL ground

LINK_MII(1:0)

MII I PHY signal indicating a link

LINKACT(1:0)

LED O Link/Activity LED output

MI_CLK

MII O PHY Management Interface clock

MI_DATA

MII

BD

PHY Management Interface data

MODE[1:0]

Configuration

I

Chip Mode, port configuration

OSC_IN

Clock

I

Clock source (crystal/oscillator)

OSC_OUT

Clock

O

Clock source (crystal)

PDI[17:0]

PDI

BD

PDI signal, depending on EEPROM content

PHYAD_OFF

Configuration

I

Ethernet PHY Address Offset

RBIAS

EBUS

BIAS resistor for LVDS TX current adjustment

RESET

General

BD

Open collector Reset output/Reset input

RUN

LED O Run LED controlled by AL Status register

RX_CLK

MII I MII receive clock

RX_D[3:0]

MII I MII receive data

RX_DV

MII I MII receive data valid

RX_ERR

MII I MII receive error

SYNC/LATCH[1:0]

DC

I/O

Distributed Clocks SyncSignal output or LatchSignal input

TESTMODE

General

I

Reserved for testing, connect to GND

TX_D[3:0]

MII O MII transmit data

TX_ENA

MII O MII transmit enable

V

CC

Power

Device power (LDO input)

V

CC Core

Power

Core logic power

V

CC I/O

Power

I/O power

V

CC PLL

Power

PLL power

3.1.2 Signal Overview

Table 9: Signal Overview

Slave Controller – ET1200 Hardware Description III-11

BECKHOFF ET1200 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Section III – Hardware Description

DOCUMENT ORGANIZATION

DOCUMENT HISTORY

CONTENTS

TABLES

FIGURES

ABBREVIATIONS

1 Overview

1.1 Frame processing order

1.2 Scope of this document

1.3 Revision/Build History

2 Features and Registers

2.1 Features

2.2 Register Overview

3 Pin Description

3.1 Overview

3.1.1 Pin Overview

3.1.2 Signal Overview