Features
•Compatible with MCS-51™ Products
•1K Byte of Reprogrammable Flash Memory
–Endurance: 1,000 Write/Erase Cycles
•2.7V to 6V Operating Range
•Fully Static Operation: 0 Hz to 24 MHz
•Two-Level Program Memory Lock
•64 bytes SRAM
•15 Programmable I/O Lines
•One 16-Bit Timer/Counter
•Three Interrupt Sources
•Direct LED Drive Outputs
•On-Chip Analog Comparator
•Low Power Idle and Power Down Modes
Description
The AT89C1051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 1K byte of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C1051 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
The AT89C1051 provides the following standard features: 1K Byte of Flash, 64 bytes of RAM, 15 I/O lines, one 16-bit timer/counter, a three vector two-level interrupt architecture, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C1051 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Configuration
PDIP/SOIC
8-Bit |
Microcontroller |
with 1K Byte |
Flash |
AT89C1051 |
0366D-A–12/97 |
4-3 |
Block Diagram |
|
|
|
|
|
VCC |
|
|
|
|
|
|
RAM ADDR. |
RAM |
FLASH |
|
|
GND |
REGISTER |
|
|||
|
|
||||
|
|
|
|
|
|
|
B |
|
|
STACK |
PROGRAM |
|
ACC |
|
ADDRESS |
||
|
REGISTER |
|
POINTER |
||
|
|
REGISTER |
|||
|
|
|
|
|
|
|
|
|
|
|
BUFFER |
|
|
TMP2 |
TMP1 |
|
|
|
|
|
|
|
PC |
|
|
|
ALU |
|
INCREMENTER |
|
|
|
|
INTERRUPT, |
|
|
|
|
|
AND TIMER BLOCKS |
|
|
|
|
|
|
PROGRAM |
|
|
|
PSW |
|
COUNTER |
|
|
|
|
|
|
|
TIMING |
INSTRUCTION |
|
|
|
RST |
AND |
|
|
DPTR |
|
REGISTER |
|
|
|||
|
CONTROL |
|
|
|
|
|
|
|
|
|
|
|
|
|
PORT 1 |
PORT 3 |
|
|
|
ANALOG |
LATCH |
LATCH |
|
|
|
COMPARATOR |
|
|
|
|
|
+ |
|
|
|
|
|
- |
|
|
|
|
OSC |
|
|
|
|
|
|
|
PORT 1 DRIVERS |
PORT 3 DRIVERS |
|
|
|
|
P1.0 - P1.7 |
P3.0 - P3.5 |
P3.7 |
4-4 |
AT89C1051 |
|
|
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 1
Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pullups.
Port 1 also receives code data during Flash programming and verification.
Port 3
Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features of the AT89C1051 as listed below:
Port Pin |
|
Alternate Functions |
|
|
|
|
|
P3.2 |
|
|
(external interrupt 0) |
INT0 |
|||
P3.3 |
|
|
(external interrupt 1) |
INT1 |
|||
P3.4 |
|
T0 (timer 0 external input) |
|
|
|
|
|
AT89C1051
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
Figure 1. Oscillator Connections
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
4-5
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the table below.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Restrictions on Certain Instructions
The AT89C1051 is an economical and cost-effective member of Atmel’s growing family of microcontrollers. It contains 1K byte of flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device.
All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 1K for the AT89C1051. This should be the responsibility of the software programmer. For example, LJMP 3FEH would be a valid instruction for the AT89C1051 (with 1K of memory), whereas LJMP 410H would not.
Table 1. AT89C1051 SFR Map and Reset Values
0F8H |
|
|
|
|
|
|
|
|
|
0FFH |
|
|
|
|
|
|
|
|
|
|
|
0F0H |
B |
|
|
|
|
|
|
|
0F7H |
|
|
|
00000000 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0E8H |
|
|
|
|
|
|
|
|
0EFH |
|
|
|
|
|
|
|
|
|
|
|
|
0E0H |
ACC |
|
|
|
|
|
|
|
0E7H |
|
|
|
00000000 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0D8H |
|
|
|
|
|
|
|
|
0DFH |
|
|
|
|
|
|
|
|
|
|
|
|
0D0H |
PSW |
|
|
|
|
|
|
|
0D7H |
|
|
|
00000000 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0C8H |
|
|
|
|
|
|
|
|
0CFH |
|
|
|
|
|
|
|
|
|
|
|
|
0C0H |
|
|
|
|
|
|
|
|
0C7H |
|
|
|
|
|
|
|
|
|
|
|
|
0B8H |
IP |
|
|
|
|
|
|
|
0BFH |
|
|
|
XXX00000 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0B0H |
P3 |
|
|
|
|
|
|
|
0B7H |
|
|
|
11111111 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0A8H |
IE |
|
|
|
|
|
|
|
0AFH |
|
|
|
0XX00000 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0A0H |
|
|
|
|
|
|
|
|
0A7H |
|
|
|
|
|
|
|
|
|
|
|
|
98H |
|
|
|
|
|
|
|
|
9FH |
|
|
|
|
|
|
|
|
|
|
|
|
90H |
P1 |
|
|
|
|
|
|
|
97H |
|
|
|
11111111 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
88H |
TCON |
TMOD |
TL0 |
|
TH0 |
|
|
|
8FH |
|
|
|
00000000 |
00000000 |
00000000 |
|
00000000 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
80H |
|
SP |
DPL |
DPH |
|
|
|
PCON |
87H |
|
|
|
|
00000111 |
00000000 |
00000000 |
|
|
|
0XXX0000 |
|
|
|
|
|
|
|
|
|
|
|
|
4-6 |
AT89C1051 |
|
|
||
|