ATMEL ATmega325P, ATmega325PV, ATmega3250P, ATmega3250PV User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 130 Powe rful Instructions – Most Single Clock Cy cle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-Chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 32K Bytes of In-System Self-programmable Flash program memory – 1K Bytes EEPROM – 2K Bytes Internal SRAM – Write/Erase cyles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C – Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode – Real Time Counter with Separate Oscillator –Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Pr ogrammab l e Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Pac kages

– 54/69 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

• Speed Grade:

– ATmega325PV/ATmega3250PV:

0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATmega325P/3250P:

0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode:

420 µA at 1 MHz, 1.8V

– Power-down Mode:

40 nA at 1.8V

– Power-save Mode:

750 nA at 1.8V

8-Bit Microcontroller

(1)

8-bit

Microcontroller with 32K Bytes In-System Programmable Flash

ATmega325P/V ATmega3250P/V

Preliminary

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ATmega325P/3250P

1. Pin Configurations

Figure 1-1. Pinout ATmega3250P

(RXD/PCINT0) PE0

DNC

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

GND

DNC

(PCINT24) PJ0

(PCINT25) PJ1

DNC

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

TQFP

AVCC

AGND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

DNC

PH7 (PCINT23)

PH6 (PCINT22)

PH5 (PCINT21)

PH4 (PCINT20)

DNC

GND

9998979695949392919089888786858483828180797877

100

26272829303132333435363738394041424344454647484950

(OC2A/PCINT15) PB7

DNC

INDEX CORNER

(T1) PG3

(T0) PG4

VCC

RESET/PG5

GND

(TOSC2) XTAL2

DNC

(TOSC1) XTAL1

ATmega3250

DNC

(PCINT26) PJ2

(PCINT27) PJ3

(PCINT28) PJ4

DNC

(PCINT29) PJ5

(PCINT30) PJ6

(INT0) PD1

(ICP1) PD0

PD2

VCC

PD3

DNC

PD4

PA0

PD5

PA1

PD6

PA2

PD7

PA3

PA4

PA5

PA6

PA7

PG2

PC7

PC6

DNC

PH3 (PCINT19)

PH2 (PCINT18)

PH1 (PCINT17)

PH0 (PCINT16)

DNC

PC5

PC4

PC3

PC2

PC1

PC0

PG1

PG0

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Figure 1-2. Pinout ATmega325P

GND

AVCC

DNC

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

PF0 (ADC0)

PF1 (ADC1)

AREF

6018592058

INDEX CORNER

ATmega325P/3250P

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

57225623552454255326522751

ATmega325

GND

PF7 (ADC7/TDI)

PF6 (ADC6/TDO)

VCC

PA 0

PA 1

PA 2

PA 3

PA 4

PA 5

PA 6

PA 7

PG2

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PG1

PG0

(T1) PG3

(T0) PG4

RESET/PG5

(OC2A/PCINT15) PB7

VCC

GND

(TOSC2) XTAL2

(TOSC1) XTAL1

(INT0) PD1

(ICP1) PD0

PD2

PD3

PD4

PD5

PD6

PD7

Note: The large center pad underneath the QFN/MLF packages is made of metal and inter nally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

1.1 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es will be available after the device is characterized.

2. Overview

The ATmega325P/3250P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega3 25P/32 50P achieves throughp uts ap proa ching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

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ATmega325P/3250P

2.1 Block Diagram

Figure 2-1. Block Diagram

AVCC

AGND

AREF

PH0 - PH7

PORTH DRIVERS

VCCGND

DATA DIR.

REG. PORTH

PORTH

DATA REGISTER

DATA DIR.

REG. PORTJ

DATA REGISTER

JTAG TAP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF

AVR CPU

PORTF DRIVERS

ADC

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

STACK

POINTER

SRAM

GENERAL

PURPOSE

REGISTERS

ALU

STATUS

PA0 - PA7PF0 - PF7

PORTA DRIVERS

DATA DIR.

REG. PORTA

8-BIT DATA BUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTERS

INTERRUPT

UNIT

EEPROM

PORTC DRIVERS

DATA REGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC0 - PC7

DATA DIR.

REG. PORTC

XTAL1

XTAL2

RESET

PJ0 - PJ6

PORTJ DRIVERS

PORTJ

DATA REGISTER

ANALOG

COMPARATOR

USART

DATA REGISTER

PORTE

UNIVERSAL

SERIAL INTERFACE

REG. PORTE

PORTE DRIVERS

DATA DIR.

DATA REGISTER

PORTB

PORTB DRIVERS

DATA DIR.

REG. PORTB

PB0 - PB7PE0 - PE7

SPI

DATAREGISTER

PORTD

PORTD DRIVERS

PD0 - PD7

DATA DIR.

REG. PORTD

DATAREG.

PORTG

PORTG DRIVERS

DATA DIR.

REG. PORTG

PG0 - PG4

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

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ATmega325P/3250P

The ATmega325P/3250P provides the following features: 32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counte rs , SPI po rt , an d inte rr upt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Powersave mode, the asynchronous timer, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consum ption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Bo ot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega325P/3250P is a powerful microcontroller that provides a highly flexible and cost effe ctive solut ion to man y emb edded co ntrol applications.

The ATmega325P/3250P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

2.2 Comparison between ATmega325P and ATmega3250P

The ATmega325P and ATmega3250P differs only in memory sizes, pin count and pinout. Table

2-1 on page 5 summarizes the different configurations for the four devices.

Table 2-1. Configuration Summary

Device Flash EEPROM RAM

ATmega325P 32K bytes 1K bytes 2K bytes 54 ATmega3250P 32K bytes 1K bytes 2K bytes 69

General Purpose I/O Pins

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ATmega325P/3250P

2.3 Pin Descriptions

The following section describes the I/O-pin special funct ion s.

2.3.1 V

2.3.2 GND

2.3.3 Port A (PA7..PA0)

2.3.4 Port B (PB7..PB0)

Digital supply voltage.

Ground.

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega325P/3250P as listed

on page 71.

2.3.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

2.3.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega325P/3250P as liste d on page 74.

2.3.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

8023E–AVR–06/08

resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega325P/3250P as listed on page 75.

2.3.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit) . The Por t F outpu t buffers ha ve symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a res et cond ition beco mes a ctive, ev en if th e clock is not ru nning. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

2.3.9 Port G (PG5..PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

ATmega325P/3250P

Port G also serves the functions of various special featur es of the ATmega325P/3250P as listed on page 75.

2.3.10 Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3250P as listed on

page 75.

2.3.11 Port J (PJ6..PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up re sistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3250P as listed on

page 75.

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ATmega325P/3250P

2.3.12 RESET

2.3.13 XTAL1

2.3.14 XTAL2

2.3.15 AVCC

2.3.16 AREF

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characterizations” on page 308. Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

through a low-pass filter.

This is the analog reference pin for the A/D Converter.

8023E–AVR–06/08

3. Resources

ATmega325P/3250P

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

8023E–AVR–06/08

ATmega325P/3250P

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5. About Code Examples

This documentation contains simple code examples t hat brief ly show h ow to us e various parts of the device. These code examples assume that the part specific header file is included b efore compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent . Please con firm wit h the C com piler d ocume ntation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

8023E–AVR–06/08

6. AVR CPU Core

6.1 Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

6.2 Architectural Overview

Figure 6-1. Block Diagram of the AVR Architecture

ATmega325P/3250P

Data Bus 8-bit

Flash

Program Memory

Instruction

Decoder

Program

Counter

Control Lines

Direct Addressing

Indirect Addressing

Status

and Control

32 x 8

General

Purpose

Registrers

ALU

Data

SRAM

EEPROM

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module1

I/O Module 2

I/O Module n

8023E–AVR–06/08

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ATmega325P/3250P

ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointe rs can also be used as an address pointe r for look up tables in Flash pr ogram memory. Thes e added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the AL U. After an arith metic operation, the Status Register is updated to reflect informat ion about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Prog ram Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega325P/3250P has Extended I/O space fr om 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

6.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are execut ed . The ALU ope ra tio ns are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

8023E–AVR–06/08

6.4 AVR Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Refe rence. This wil l in many cases remove the n eed for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be hand le d by so ftware.

6.4.1 SREG – AVR Status Register

Bit 76543210 0x3F (0x5F) ITHSVNZCSREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

ATmega325P/3250P

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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ATmega325P/3250P

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

6.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order t o achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10

Registers R17 0x11

7 0 Addr.

R0 0x00 R1 0x01 R2 0x02

…

R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 6-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

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6.5.1 The X-register, Y-register , and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure .

The X-, Y-, and Z-registers

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7070

R31 (0x1F) R30 (0x1E)

In the different addressing modes these addr ess regist er s have fun cti ons a s fi xed d isp lacement , automatic increment, and automatic decrement (see the instruction set reference for details).

6.6 Stack Pointer

ATmega325P/3250P

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area wh ere the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.

The Stack in the data SRAM must be defined by the program before any subroutine calls ar e executed or interrupts are enabled. Initial Stack Pointer value equa ls the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure

7-2 on page 21.

See Table 6-1 for Stack Pointer details.

Table 6-1. Stack Pointer instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack CALL

ICALL RCALL

POP Incremented by 1 Data is popped from the stack RET

RETI

Decremented by 2

Incremented by 2 Return address is popped from the stack with return from

Return address is pushed onto the stack with a subroutine call or interrupt

subroutine or return from interrupt

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The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

ATmega325P/3250P

6.6.1 SPH and SPL – Stack Pointe r High and Stack Pointer Low

T1 T2 T3 T4

Bit 151413121110 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

00000000

6.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 1 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 1. The Parallel Instruction Fetches and Instruction Executions

, directly generated from the selected clock source for the

CPU

clk

CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 2 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destination register.

Figure 2. Single Cycle ALU Operation

T1 T2 T3 T4

clk

CPU

Total Execution Time egister Operands Fetch ALU Operation Execute

Result Write Back

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6.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one toge ther with the Glo bal Interru pt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section ”Memory Program-

ming” on page 271 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 53. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to t he start of the Boot Flash section by setting t he IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 53 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see ”Boot Loader Support – Read-While-Write Self-Programming” on page

256.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

ATmega325P/3250P

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Int errupt Flags. If the interrup t condition disappears before t he interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt rou tine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

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ATmega325P/3250P

CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

6.8.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector addre ss fo r t he actua l interr up t ha nd ling rout ine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in ad dition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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7. AVR Memories

7.1 Overview

This section describes the different memories in the ATmega325 P/3250P. The AVR archit ecture has two main memory spaces, the Data Memory and the Pr ogram Memory spa ce. In addition, the ATmega325P/3250P features an EEPROM Memory for data storage. All three memory spaces are linear.

7.2 In-System Reprogrammable Flash Program Memory

The ATmega325P/3250P contains 32K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega325P/3250P Program Counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in ”Boot Lo ader Support – Rea d-While-Write Self-Pr o-

gramming” on page 256. ”Memory Programming” on page 271 contains a detailed description

on Flash data serial downloading using the SPI pins or the JTAG interface.

ATmega325P/3250P

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-

ing” on page 16.

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ATmega325P/3250P

Figure 7-1. Program Memory Map

Program Memory

Application Flash Section

Boot Flash Section

0x0000

0x3FFF

7.3 SRAM Data Memory

Figure 7-2 shows how the ATmega325P/3250P SRAM Memory is orga nized.

The ATmega325P/3250P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 2304 data memory locations address both the Reg ister File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 2048 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations f rom the base address given

by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and

the 2,048 bytes of internal data SRAM in the ATmega325P/3250P are all accessible through all

8023E–AVR–06/08

these addressing modes. The Register File is descr ibed in ”General Purp ose Register File” on

page 14.

Figure 7-2. Data Memory Map

7.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

Figure 7-3. On-chip Data SRAM Access Cycles

ATmega325P/3250P

Data Memory

32 Registers

64 I/O Registers

160 Ext I/O Reg.

Internal SRAM

(2048 x 8)

T1 T2 T3

0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF

0x0100

0x08FF

cycles as described in Figure 7-3.

CPU

clk

CPU

ddress

Compute Address

Address valid

Data

Write

Data

Memory Access Instruction

Next Instruction

Read

7.4 EEPROM Data Memory

The ATmega325P/3250P contains 1K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

page 285, page 291, and page 274 respectively.

7.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

8023E–AVR–06/08

ATmega325P/3250P

The write access time for the EEPROM is given in Table 7-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V

is likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specif ied as mi nimum for the clock fre quen cy used .

See Section “7.4.3” on page 22. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

7.4.2 EEPROM Write During Power-down Sleep Mode

When entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the clock continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down.

7.4.3 Preventing EEPROM Corruption

7.5 I/O Memory

During periods of low V

the EEPROM data can be corrupted because the supply voltage is

CC,

too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an exter nal low V

reset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

The I/O space definition of the ATmega325P/3250P is shown in ”Register Summary” on page

342.

All ATmega325P/3250P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instruction s, transferring data betwee n the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these re giste rs, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega325P/3250P is a complex microcontroller with more peripheral units than can be supported within the 64 location

8023E–AVR–06/08

reserved in Opcode for the IN and OUT instructions. For the Exten ded I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

7.6 Register Description

7.6.1 EEARH and EEARL – The EEPROM Address Register

Bit 151413121110 9 8 0x22 (0x42) –––––EEAR10EEAR9EEAR8EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/WriteRRRRRR/WR/WR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000XXX

XXXXXXXX

ATmega325P/3250P

• Bits 15:11 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bits 10:0 – EEAR10:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023. The initial value of EEAR is undefined. A proper value must be writte n bef ore th e EEPROM may be accessed.

Note: EEAR10 is only valid for ATmega645P and ATmega6450P.

7.6.2 EEDR – The EEPROM Data Register

Bit 76543210 0x20 (0x40) MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to b e written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

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ATmega325P/3250P

7.6.3 EECR – The EEPROM Control Register

Bit 76543210 0x1F (0x3F) – – – – EERIE EEMWE EEWE EERE EECR Read/Write R R R R R/W R/W R/W R/W Initial Value000000X0

• Bits 7:4 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value in to the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never bein g up da te d by th e CPU, step 2 can be omitted. See ”Boot Loader

Support – Read-While-Write Self-Programming” on page 256 for details about Boot

programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

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ATmega325P/3250P

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero bef ore wr iting th e next byte. Whe n EEWE has b een set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Registe r, the EERE b it must be writte n to a log ic one t o trigger t he EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 7-1 lists the typica l programming time for EEPROM access from the CPU.

Table 7-1. EEPROM Programming Time

Number of Calibrated

Symbol

EEPROM write (from CPU) 27,072 3.4 ms

RC Oscillator Cycles Typical Programming Time

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

8023E–AVR–06/08

ATmega325P/3250P

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

8023E–AVR–06/08

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

ATmega325P/3250P

7.6.4 General Purpose I/O Registers

The ATmega325P/3250P contains three General Purpose I/O Regi sters. These re gisters can be used for storing any inform ation, and th ey are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

7.6.5 GPIOR2 – General Purpose I/O Regist er 2

Bit 76543210 0x2B (0x4B) MSB LSB GPIOR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

7.6.6 GPIOR1 – General Purpose I/O Regist er 1

Bit 76543210 0x2A (0x4A) MSB LSB GPIOR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

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ATmega325P/3250P

7.6.7 GPIOR0 – General Purpose I/O Regist er 0

Bit 76543210 0x1E (0x3E) MSB LSB GPIOR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

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8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consump tion, th e cloc ks to modules not being used can be halted by using different sleep modes, as described in ”Power Manage-

ment and Sleep Modes” on page 38. The clock systems are detailed below.

Figure 8-1. Clock Distribution

Asynchronous

Timer/Counter

General I/O

Modules

ATmega325P/3250P

CPU Core RAM

Flash and EEPROM

8.1.1 CPU Clock – clk

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

8.1.2 I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that start condition detectio n in the USI module is carried ou t asynchronously when clk

8.1.3 Flash Clock – clk

CPU

FLASH

Timer/Counter

Oscillator

clk

I/O

clk

ASY

External Clock

is halted, enabling USI start condition detection in all sleep modes.

I/O

AVR Clock

Control Unit

Clock

Multiplexer

Source clock

Crystal

Oscillator

clk

CPU

clk

FLASH

Reset Logic

Watchdog Timer

Watchdog clock

Low-frequency

Crystal Oscillator

Watchdog

Oscillator

Calibrated RC

Oscillator

8023E–AVR–06/08

The Flash clock controls operation of the Flash inte rface. The Fla sh clock is usually active simultaneously with the CPU clock.

ATmega325P/3250P

8.1.4 Asynchronous Timer Clock – clk

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode.

ASY

8.1.5 ADC Clock – clk

8.2 Clock Sources

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion results.

The device has the following clock source options, selec table by Flash Fuse bits as shown below. The clock from the selected so ur ce is i npu t to th e AVR clo c k gene ra to r, and r ou te d to t he appropriate modules.

Table 8-1. Device Clocking Options Select

Device Clocking Option CKSEL3..0

External Crystal/Ceramic Resonator 1111 - 1000 External Low-frequency Crystal 0111 - 0110 Calibrated Internal RC Oscillator 0010 External Clock 0000 Reserved 0011, 0001, 0101, 0100

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

(1)

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the startup, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 8-

2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical Characteristics” on page 314.

Table 8-2. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

8.3 Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “ 10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel programmer.

4.1 ms 4.3 ms 4K (4,096) 65 ms 69 ms 64K (65,536)

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8.4 Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 8-2. Either a quartz crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 8-3. For ceramic resonators, the capacitor values given by the manufacturer should be used.

Figure 8-2. Crystal Oscillator Connections

ATmega325P/3250P

XTAL

GND

The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-3.

Table 8-3. Crystal Oscillator Operating Modes

Frequency Range

CKSEL3..1

(1)

100

101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22

Note: 1. This option should not be used with crystals, only with ceramic resonators.

(MHz)

0.4 - 0.9 –

Recommended Range for Capacitors C1 and

C2 for Use with Crystals (pF)

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

8-4.

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Table 8-4. Start-up Times for the Crystal Oscillator Clock Selection

CKSEL0 SUT1..0

000 258 CK

001 258 CK

010 1K CK

Start-up Time from

Power-down and

Power-save

(1)

(2)

Additional Delay from

Reset

(VCC = 5.0V) Recommended Usage

14CK + 4.1 ms

14CK + 65 ms

14CK

Ceramic resonator, fast

rising power

Ceramic resonator, slowly rising power

Ceramic resonator,

BOD enabled

ATmega325P/3250P

Table 8-4. Start-up Times for the Crystal Oscillator Clock Selection (Continued)

–=

CKSEL0 SUT1..0

011 1K CK

100 1K CK

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

2. These options are intended for use with cer amic resonators and will ensure frequency stability

01 16K CK 14CK Crystal Oscillator, BOD

10 16K CK 14CK + 4.1 ms Crystal Oscillator, fast

11 16K CK 14CK + 65 ms Crystal Oscillator, slowly

device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

8.5 Low-frequency Crystal Oscillator

The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega325P/3250P oscillator is optimized for very low power consumption, and thus when selecting crystals, see Table 8-5 on page 32 for maximum ESR recommendations on 6.5 pF,

9.0 pF and 12.5 pF crystals

Start-up Time from

Power-down and

Power-save

(2)

Additional Delay from

Reset

(VCC = 5.0V) Recommended Usage

14CK + 4.1 ms Ceramic resonator, fa st

rising power

14CK + 65 ms Ceramic resonator,

slowly rising power

enabled

rising power

Table 8-5. Maximum ESR Recommendation for 32.768 kHz Watch Crystal

Crystal CL (pF) Max ESR [kΩ]

6.5 75

9.0 65

12.5 30

Note: 1. Maximum ESR is typical value based on characterization

(1)

The Low-frequency Crystal Oscillator provides an internal load capacitance of typical 6 pF at each TOSC pin. The external capacitance (C) needed at each TOSC pin can be calculated by using:

CL⋅ C

where CL is the load capacitance for a 32.768 kHz crystal specified by the cryst al vendor and C is the total stray capacitance for one TOSC pin.

Crystals specifying load capacitance (CL) higher than 6 pF, require external capacitors applied as described in Figure 8-2 on page 31.

To find suitable load capacitance for a 32.768 kHz crystal, please consult the crystal datasheet.

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The Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or “0111” as shown in Table 8-7. Start-up times are determined by the SUT Fuses as shown in

Table 8-6.

Table 8-6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0 Additional Delay from Reset (VCC = 5.0V) Recomme nded Usage

00 4 CK Fast rising power or BOD enabled 01 4 CK + 4.1 ms Slowly rising power 10 4 CK + 65 ms Stable frequency at start-up 11 Reserved

Table 8-7. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

CKSEL3..0

(1)

0110

0111 32K CK Stable frequency at start-up

Note: 1. This option should only be used if frequency stability at start-up is not important for the

application

Power-down and Power-save Recommended Usage

8.6 Calibrated Internal RC Oscillator

ATmega325P/3250P

Start-up Time from

1K CK

By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibr ated by the user. See Ta ble 26-1

on page 307 for more details. The device is shipped with the CKDIV8 Fuse programmed. See ”System Clock Prescaler” on page 35 for more details.

This clock may be selected as the system cloc k by p rogr am m in g th e CKS E L Fus es a s sh own in

Table 8-8 on page 33. If selected, it will operate with no external components. During reset,

hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 26-1 on page 307.

By changing the OSCCAL register from SW, see ”OSCCAL – Oscillator Calibration Register” on

page 36, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of this calibration is shown as User calibration in Table 26-1 on page 307. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section ”Calibration Byte” on page 274.

Table 8-8. Internal Calibrated RC Oscillator Operating Modes

Frequency Range

7.3 - 8.1 0010

(2)

(MHz) CKSEL3..0

(1)(3)

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Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.

3. If 8 MHz frequency exceeds the specification of the device (depends on V Fuse can be programmed in order to divide the internal frequency by 8.

), the CKDIV8

ATmega325P/3250P

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-9 on page 34.

Table 8-9. Start-up times for the internal calibrated RC Oscillator clock selection

8.7 External Clock

Start-up Time from Power-

Power Conditions

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms

Note: 1. The device is shipped with this option selected.

down and Power-save

Reserved 11

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

(1)

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure

3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

Figure 3. External Clock Drive Configuration

EXTERNAL

CLOCK

SIGNAL

XTAL2

XTAL1

GND

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 2.

Table 1. Crystal Oscillator Clock Frequency

CKSEL3..0 Frequency Range

0000 0 - 16 MHz

Table 2. Start-up Times for the External Clock Selection

Start-up Time from Power-

SUT1..0

00 6 CK 14CK BOD enabled 01 6 CK 14CK + 4.1 ms Fast rising power 10 6 CK 14CK + 65 ms Slowly rising power 11 Reserved

down and Power-save

Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

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one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-ti me changes of the int ernal clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page

35 for details.

8.8 Clock Output Buffer

When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock will be output also during reset and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including internal RC Oscillator, can be selected when CLKO serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that is output when the CKOUT Fuse is programmed.

8.9 Timer/Counter Oscillator

ATmega325P/3250P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator. See ”Low-frequency Crystal Oscillator” on page 32 for details on the oscillator and crystal requirements.

ATmega325P/3250P

ATmega325P/3250P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be used when the Calibrated Internal RC Oscillator is selected as system clock source.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one. See ”Timer/Counter Timing Diagram, Clear Timer on Compare Match mode,

with Prescaler (fclk_I/O/8)” on page 146 for further description on selecting external clock as

input instead of a 32.768 kHz watch crystal.

8.10 System Clock Prescaler

The ATmega325P/3250P system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk are divided by a factor as shown in Table 8-10.

8.10.1 Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.

I/O

, clk

ADC

, clk

CPU

, and clk

FLASH

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The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

ATmega325P/3250P

8.11 Register Description

8.11.1 OSCCAL – Oscillator Calibration Register

Bit 76543210 (0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Device Specific Calibration Value

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in Table 26-1 on page 307. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 26-

1 on page 307. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that r ange, and a setting of 0x7F g ives the high est freq uency in the range.

8.11.2 CLKPR – Clock Prescale Register

Bit 76543210 (0x61) Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 See Bit Description

CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Selec t Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to t he MCU, the speed o f all synchronous peripherals is reduced when a division factor is used. The division factors are given in

Table 8-10.

8023E–AVR–06/08

ATmega325P/3250P

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure t he write procedur e is not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 8-10. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved

8023E–AVR–06/08

ATmega325P/3250P

9. Power Management and Sleep Modes

9.1 Overview

Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s require m en ts .

When enabled, the Brown-out Detector (BOD) actively monitors the power supply volta ge dur ing the sleep periods. To further save power, it is possib le to d isable the BOD in some sleep modes. See ”BOD Disable” on page 39 for more details.

9.2 Sleep Modes

Figure 8-1 on page 29 presents the different clock systems in the ATmega325P/3250P, and

their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 9-1 shows the different sleep modes, their wake up sources and BOD disable ability.

Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators Wake-up Sources

CPU

FLASH

Sleep Mode

Idle XXX X X ADCNRM X X X X Power-down X Power-save X X Standby

(1)

clk

clkIOclk

ADC

ASY

Software

clk

Main Clock

Source

Enabled

Timer Osc

Enabled

INT2:0 and

(2)

XXXXXXX

(2)X(3)

(3)

(2)X(3)

(3)

Pin Change

TWI Address

Match

Timer2

SPM/

EEPROM Ready

ADC

WDT Interrupt

(2)

XXX XXX XX X X XXX

Other I/O

BOD Disdable

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If Timer/Counter2 is running in asynchronous mode.

3. For INT0, only level interrupt.

To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode will be activated by the SLEEP instruction. See Table 9-2 on page 43 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from slee p. I f a r eset occurs d uri ng sle ep mode, the MCU wakes up and executes from the Reset Vector.

8023E–AVR–06/08

9.3 BOD Disable

9.4 Idle Mode

ATmega325P/3250P

When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 25-3 on page 272, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 9-1 on page

38. The sleep mode power consumption will then be at the same level as when BOD is globally

disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the V

When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60 µs to ensure that the BOD is working correctly before the MCU continues executing code.

BOD disable is controlled by bit 6, BODS (B OD Sleep) in the control register MCUCR, see

”MCUCR – MCU Control Register” on page 43. Writing this bit to one turns off the BOD in rele-

vant sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active, i.e. BODS set to zero.

Writing to the BODS bit is controlled by a timed sequence and an enable bit, see ”MCUCR –

MCU Control Register” on page 43.

level has dropped during the sleep period.

When the SM2:0 bits are written to 000, the SLEEP instru ctio n makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk

Idle mode enables the MCU to wake up from external triggered interrupts as well a s internal ones like the Timer Overflow and USART Transmit Complete interru pts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be po wered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

9.5 ADC Noise Reduction Mode

When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI start condition detection, Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is e ntered. Apart fo rm the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can wake up the M CU from ADC Noise Reduction mode.

CPU

and clk

, while allowing the other clocks to run.

FLASH

I/O

, clk

, and clk

CPU

, while allowing the other clocks to run.

FLASH

8023E–AVR–06/08

ATmega325P/3250P

9.6 Power-down Mode

When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition detection, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 58 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in ”Clock Sources” on page 30.

9.7 Power-save Mode

When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Powersave mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.

If Timer/Counter2 is running, Power-down mode is recommended instead of Power-save mode. The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save

mode. The clock source for the two modules can be selected independent of each other. If the Timer/Counter2 is using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If the Timer/Counter2 is using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the Timer/Counter2.

9.8 Standby Mode

When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.

9.9 Po wer Reduction Register

The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 44, pro- vides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers inaccessible. Resources used by the peripheral when stopping the clock will remain occupied so the peripheral should be disabled before stopping the clock. Waking up a module, which is done by clearing the b it in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in IDLE mode and active mode to reduce the overall power consumption. In all other sleep modes, the clock is already stopped.

8023E–AVR–06/08

9.10 Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

9.10.1 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to ”Analog to Digital Converter” on page 206 for details on ADC operation.

9.10.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independe nt of sleep mode. Refer to ”Analog Comparator” on page 203 for details on how to configure the Analog Comparator.

ATmega325P/3250P

9.10.3 Brown-out Detector

If the Brown-out Detector is not needed by the a pplication, this module sh ould be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to ”Brown-out Detection” on page 47 for details on how to configure the Brown-out Detector.

9.10.4 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to ”Internal Volt-

age Reference” on page 48 for details on the start-up time.

9.10.5 Watchdog Timer

If the Watchdog Timer is not needed in t he application, the m odule should be tu rned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to ”Watchdog Timer” on page 49 for details on how to configu re t he Wa tchd og Time r.

9.10.6 Port Pins

8023E–AVR–06/08

When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk be disabled. This ensures that no power is consumed by the input logic when not needed. In

) and the ADC clock (clk

I/O

) are stopped, the input buffers of the device will

ADC

ATmega325P/3250P

some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 67 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V

/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on page 205 and ”DIDR0 – Digital

Input Disable Register 0” on page 222 for details.

9.10.7 JTAG Interface and On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this:

• Disable OCDEN Fuse.

• Disable JTAGEN Fuse.

• Write one to the JTD bit in MCUCR. The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is

not shifting data. If the hardware connected to the TDO pin does not pull up the logic level, power consumption will increase. Note that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit in the MCUCR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface.

/2, the input buffer will use excessive power.

8023E–AVR–06/08

9.11 Register Description

9.11.1 SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

Bit 76543210 0x33 (0x53) Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 9-2.

Table 9-2. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle 0 0 1 ADC Noise Reduction 0 1 0 Power-down 0 1 1 Power-save

– – – – SM2 SM1 SM0 SE SMCR

ATmega325P/3250P

100Reserved 101Reserved 1 1 0 Standby 111Reserved

Note: 1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 1 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when th e SLEEP instruction is executed. To avoid the MCU enteri ng th e sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) b it to one just befor e the exe cution of the SLEEP instruction and to clear it immediately after waking up.

9.11.2 MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0 0x35 (0x55) Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

JTD BODS BODSE PUD – – IVSEL IVCE MCUCR

• Bit 6 – BODS: BOD Sleep

The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 9-1

on page 38. Writing to the BODS bit is controlled by a timed sequence and an enable bit,

BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to zero within four clock cycles.

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ATmega325P/3250P

The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode . The BODS bit is automatically cleared after three clock cycles.

• Bit 5 – BODSE: BOD Sleep Enable

BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disa b le is controlled by a timed sequence.

9.11.3 PRR – Power Reduction Register

Bit 76543210 (0x64) Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

– – – – PRTIM1 PRSPI PRUSART0 PRADC PRR

• Bits 7:4- Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing logic one to this bit shuts down the Timer/Counter1 module. When Timer/Counter1 is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re-initialized to ensure proper operation.

• Bit 1 - PRUSART: Power Reduction USART

Writing logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be re-initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

Note: The Analog Comparator is disabled using the ACD-bit in the ”ACSR – Analog Comparator Control

and Status Register” on page 204.

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10. System Control and Reset

10.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 10-1 on page 46 shows the reset logic. ”System and Reset Characterizations” on page 308 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in ”Clock Sources” on page 30.

ATmega325P/3250P

10.2 Reset Sources

The ATmega325P/3250P has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V

• External Reset. The MCU is reset when a low level is present on the RESET the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.

• Brown-out Re set. The MCU is reset when the supply v oltage V threshold (V

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section ”IEEE 1149.1 (JTAG) Boundary-

scan” on page 229 for details.

POT

) and the Brown-out Detector is enabled.

BOT

pin for longer than

is below the Brown-out Rese t

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ATmega325P/3250P

Figure 10-1. Reset Logic

RESET

Power-on Reset

Circuit

DATA BU S

MCU Status

JTRF

BORF

PORF

WDRF

EXTRF

10.2.1 Power-on Reset

BODLEVEL [1..0]

Pull-up Resistor

SPIKE

FILTER

JTAG Reset

Brown-out

Reset Circuit

Watchdog

Oscillator

Clock

Generator

CKSEL[3:0]

SUT[1:0]

Delay Counters

TIMEOUT

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characterizations” on page 308. The POR is activated when- ever V

is below the detection level. The POR circuit can be used to trigger the start-up Reset,

as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reac hing the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V

Figure 10-2. MCU Start-up, RESET

rise. The RESET signal is activated again, without any delay,

decreases below the detection level.

RESET

IME-OUT

NTERNAL

POT

RST

TOUT

Tied to V

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10.2.2 External Reset

RESET

Figure 10-3. MCU Start-up, RESET Extended Externally

RESET

IME-OUT

NTERNAL

POT

RST

TOUT

ATmega325P/3250P

An External Reset is generated by a low level on the RESET minimum pulse width (see ”System and Reset Characterizations” o n page 308) will g enerate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V delay counter starts the MCU after the Time-out period – t

Figure 10-4. External Reset During Operation

10.2.3 Brown-out Detection

ATmega325P/3250P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V V

BOT

value below the trigger level (V vated. When V starts the MCU after the Time-out period t

The BOD circuit will only detect a drop in V longer than t

+ V

HYST

pin. Reset pulses longer than the

RST

has expired.

TOUT –

/2 and V

increases above the trigger level (V

given in ”System and Reset Characterizations” on page 30 8.

BOD

BOT-

= V

BOT

- V

BOT-

/2.When the BOD is enabled, and VCC decreases to a

HYST

in Figure 10-5), the Brown-out Reset is immediately acti-

in Figure 10-5), the delay counter

BOT+

has expired.

TOUT

if the voltage stays below the trigger level for

– on its positive edge, the

BOT+

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ATmega325P/3250P

Figure 10-5. Brown-out Reset During Operation

10.2.4 Watchdog Reset

RESET

IME-OUT

NTERNAL

RESET

BOT-

BOT+

TOUT

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT

. Refer to

page 49 for details on operation of the Wat chdog Timer.

Figure 10-6. Watchdog Reset During Operation

10.3 Internal Voltage Reference

ATmega325P/3250P features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator or the ADC.

10.3.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. T he start-up time is given in ”System and Reset Characterizations” on page 308. To save power, the reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [1:0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or

ACBG bit i n ACSR).

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ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

10.4 Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at V controlling the Watchdog Timer prescaler, the Watchdog Reset inte rval can be adjusted as shown in Table 10-2 on page 51. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega325P/3250P resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 10-2 on page

51.

To prevent unintentional disabling of the Watchd og or unintentional chan ge of time-out period, two different safety levels are selected by the fuse WDTON as shown in Figure 10-1 Refer to

”Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 49 for

details.

Table 10-1. WDT Configuration as a Function of the Fuse Settings of WDTON

ATmega325P/3250P

= 5V. See characterization data for typical values at other VCC levels. By

Safety

WDTON

Unprogrammed 1 Disabled Timed sequence Timed sequence Programmed 2 Enabled Always enabled Timed sequence

Level

WDT Initial State

How to Disable the WDT

Figure 10-7. Watchdog Timer

WATCHDOG

OSCILLATOR

10.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level.

How to Change Timeout

10.4.2 Safety Level 1

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In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A t imed seq uen ce is need ed when cha ngi ng th e Watchd og Time -o ut period or disabling an enabled Watchdog Timer. To disab le an e nab led Watc hd og Timer , an d/or changing the Watchdog Time-out, the following procedure must be followed:

ATmega325P/3250P

1. In the same operation, write a logic one to WDCE and WDE. A logic one m ust be written

to WDE regardless of the previous value of the WDE bit.

2. Within the next f our clo c k cycles, in the same operation, write the WDE and WDP bits as

desired, but with the WDCE bit cleared.

10.4.3 Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence.

Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

10.5 Register Description

10.5.1 MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit 76543210 0x35 (0x55) Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description

– – – JTRF WDRF BORF EXTRF PORF MCUSR

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then

Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

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10.5.2 WDTCR – Watchdog Timer Control Register

Bit 76543210 (0x60) – – – WDCE WDE WDP2 WDP1 WDP0 WDTCR Read/Write R R R R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7:5 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See ”Timed Sequences for Changing the Configuration of the

Watchdog Timer” on page 49.

• Bit 3 – WDE: Watc hdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is di sabled. WDE can on ly be clear ed if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:

ATmega325P/3250P

1. In the same operation, write a logic one to WDCE and WDE. A logic one m ust be written

to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See Section “10.4.1” on page 49.

• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Time-out Periods are shown in Table 10-2 on page 51.

Table 10-2. Watchdog Timer Prescale Select

Number of WDT

WDP2 WDP1 WDP0

0 0 0 16K cycles 17.1 ms 16.3 ms 0 0 1 32K cycles 34.3 ms 32.5 ms 0 1 0 64K cycles 68.5 ms 65 ms 0 1 1 128K cycles 0.14 s 0.13 s 1 0 0 256K cycles 0.27 s 0.26 s 1 0 1 512K cycles 0.55 s 0.52 s 1 1 0 1,024K cycles 1.1 s 1.0 s 1 1 1 2,048K cycles 2.2 s 2.1 s

Oscillator Cycles

Typical Ti me-out at

VCC = 3.0V

Typical Time-out at

VCC = 5.0V

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ATmega325P/3250P

The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled ( e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

WDT_off:

; Reset WDT

wdr

; Write logical one to WDCE and WDE

in r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example

void WDT_off(void)

{

/* Reset WDT */

__watchdog_reset();

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

(1)

Note: 1. See Section “5.” on page 10.

8023E–AVR–06/08

11. Interrupts

11.1 Overview

This section describes the specifics of the interrupt handling as performed in ATmega325P/3250P. For a general explanation of the AVR interrupt handling, refer to ”Reset

and Interrupt Handling” on page 17.

11.2 Interrupt Vectors

Table 11-1. Reset and Interrupt Vectors

ATmega325P/3250P

Vector

No.

1 0x0000

2 0x0002 INT0 External Interrupt Request 0 3 0x0004 PCINT0 Pin Change Interrupt Request 0 4 0x0006 PCINT1 Pin Change Interrupt Request 1 5 0x0008 TIMER2 COMP Timer/Counter2 Compare Match 6 0x000A TIMER2 OVF Timer/Counter2 Overflow 7 0x000C TIMER1 CAPT Timer/Counter1 Capture Event 8 0x000E TIMER1 COMPA Timer/Counter1 Compare Match A

9 0x0010 TIMER1 COMPB Timer/Counter1 Compare Match B 10 0x0012 TIMER1 OVF Timer/Counter1 Overflow 11 0x0014 TIMER0 COMP Timer/Counter0 Compare Match 12 0x0016 TIMER0 OVF Timer/Counter0 Overflow 13 0x0018 SPI, STC SPI Serial Transfer Complete 14 0x001A USART, RX USART0, Rx Complete 15 0x001C USART, UDRE USART0 Data Register Empty 16 0x001E USART, TX USART0, Tx Complete

Program

Address

(2)

Source Interrupt Definition

(1)

RESET

External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset

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17 0x0020 USI START USI Start Condition 18 0x0022 USI OVERFLOW USI Overflow 19 0x0024 ANALOG COMP Analog Comparator 20 0x0026 ADC ADC Conversion Complete 21 0x0028 EE READY EEPROM Ready 22 0x002A SPM READY Store Program Memory Ready 23 0x002C NOT_USED RESERVED

(3)

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at

0x002E PCINT2 Pin Change Interrupt Request 2

0x0030 PCINT3 Pin Change Interrupt Request 3

reset, see ”Boot Loader Support – Read-While-Write Self-Programming” on page 256.

ATmega325P/3250P

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of th e Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

3. PCINT2 and PCINT3 are only present in ATmega3250P and ATmeg a6450P.

Table 11-2 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program co de can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.

Table 11-2. Reset and Interrupt Vectors Placement

(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x0000 0x0002 1 1 0x0000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x0002 0 1 Boot Reset Address Boot Reset Address + 0x0002

Note: 1. The Boot Reset Address is shown in Table 24-6 on page 268. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega325P/3250P is:

Address Labels Code Comments 0x0000 jmp RESET ; Reset Handler 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp PCINT0 ; PCINT0 Handler 0x0006 jmp PCINT1 ; PCINT1 Handler 0x0008 jmp TIM2_COMP ; Timer2 Compare Handler 0x000A jmp TIM2_OVF ; Timer2 Overflow Handler 0x000C jmp TIM1_CAPT ; Timer1 Capture Handler 0x000E jmp TIM1_COMPA ; Timer1 CompareA Handler 0x0010 jmp TIM1_COMPB ; Timer1 CompareB Handler 0x0012 jmp TIM1_OVF ; Timer1 Overflow Handler 0x0014 jmp TIM0_COMP ; Timer0 Compare Handler 0x0016 jmp TIM0_OVF ; Timer0 Overflow Handler 0X0018 jmp SPI_STC ; SPI Transfer Complete Handler 0x001A jmp USART_RXC ; USART0 RX Complete Handler 0x001C jmp USART_UDRE ; USART0,UDR0 Empty Handler 0x001E jmp USART_TXC ; USART0 TX Complete Handler 0x0020 jmp USI_STRT ; USI Start Condition Handler 0x0022 jmp USI_OVF ; USI Overflow Handler 0x0024 jmp ANA_COMP ; Analog Comparator Handler 0x0026 jmp ADC ; ADC Conversion Complete Handler 0x0028 jmp EE_RDY ; EEPROM Ready Handler 0x002A jmp SPM_RDY ; SPM Ready Handler 0x002C jmp NOT_USED ; RESERVED 0x002E jmp PCINT2 ; PCINT2 Handler 0x0030 jmp PCINT3 ; PCINT3 Handler ;

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ATmega325P/3250P

0x0032 RESET: ldi r16, high(RAMEND) ; Main program start 0x0033 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0034 ldi r16, low(RAMEND) 0x0035 out SPL,r16 0x0036 sei ; Enable interrupts 0x0037 <inst

... ... ...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

0x0000 RESET: ldi r16,high(RAMEND); Main program start

0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM

0x0002 ldi r16,low(RAMEND)

0x0003 out SPL,r16 0x0004 sei ; Enable interrupts

0x0005 <instr> xxx

;

.org 0x3802/0x7802

0x3804/0x7804 jmp EXT_INT0 ; IRQ0 Handler

0x3806/0x7806 jmp PCINT0 ; PCINT0 Handler

... ... ... ;

0x1C2C jmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 4K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:

xxx

Address Labels Code Comments

.org 0x0002

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp PCINT0 ; PCINT0 Handler

... ... ... ;

0x002C jmp SPM_RDY ; Store Program Memory Ready Handler

;

.org 0x3800/0x7800 0x3800/0x7801RESET:ldir16,high(RAMEND); Main program start

0x3801/0x7801 out SPH,r16 ; Set Stack Pointer to top of RAM

0x3802/0x7802 ldi r16,low(RAMEND)

0x3803/0x7803 out SPL,r16 0x3804/0x7804 sei ; Enable interrupts

0x3805/0x7805 <instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:

8023E–AVR–06/08

ATmega325P/3250P

Address Labels Code Comments

;

.org 0x3800/0x7800 0x3800/0x7800 jmp RESET ; Reset handler 0x3802/0x7802 jmp EXT_INT0 ; IRQ0 Handler

0x3804/0x7804 jmp PCINT0 ; PCINT0 Handler

... ... ... ;

0x382C/0x782C jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start

0x382F/0x782F out SPH,r16 ; Set Stack Pointer to top of RAM

0x3830/0x7830 ldi r16,low(RAMEND)

0x3831/0x7831 out SPL,r16 0x3832/0x7832 sei ; Enable interrupts

0x3833/0x7833 <instr> xxx

11.2.1 Moving Interrupts Between Application and Boot Space

The MCU Control Register controls the placement of the Interrupt Vector table.

11.3 Register Description

11.3.1 MCUCR – MCU Control Register

Bit 76543210 0x35 (0x55) Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

JTD BODS BODSE PUD – – IVSEL IVCE MCUCR

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section ”Boot Loader Support – Read-While-Write

Self-Programming” on page 256 for details. To avoid unintentional chan ges of Interrupt Vector

tables, a special write procedure must be followed to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,

interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section ”Boot Loader Support – Read-While-

Write Self-Programming” on page 256 for details on Boot Lock bits.

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ATmega325P/3250P

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above . See Code Example below.

Assembly Code Example

Move_interrupts:

;Get MCUCR

in r16, MCUCR

mov r17, r16

; Enable change of Interrupt Vectors

ori r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ori r17, (1<<IVSEL)

out MCUCR, r17

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of Interrupt Vectors */

MCUCR |= (1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR |= (1<<IVSEL);

}

8023E–AVR–06/08

ATmega325P/3250P

12. External Interrupts

12.1 Overview

The External Interrupts are triggered by the INT0 pin or any of the PCINT30:0 pins

(2)

. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30:0 pins are configured as outputs. This feature provides a way of gener ating a so ft ware int er rupt . Th e pin chang e int erru pt PCI1 will trigger if any enabled PCINT15:8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7:0 pin toggles. The PCMSK3

(1)

, PCMSK2

(1)

, PCMSK1, and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT30:0 are detected asynchronously. This implies that t hese inte rrupt s can be used for waking the part also from sleep modes other than Idle mode .

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the ”EICRA – External Interrupt Control Register A” on page 59. When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in ”Clock Systems and their Distribution” on

page 29. Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt

can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power -down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in ”System Clock and Clock Options” on page 29.

Notes: 1. PCMSK3 and PCMSK2 are only present in ATmega3250P.

2. PCINT30:16 are only present in ATmega3250P. Only PCINT15:0 are present in A Tmega325P. See ”Pin Configurations” on page 2 and ”Register Description” on page 59 for details.

8023E–AVR–06/08

12.2 Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 12-1.

Figure 12-1. Pin Change Interrupt

PCINT(0)

clk

PCINT(n)

pin_lat

pin_sync

ATmega325P/3250P

pin_lat

D Q

pin_sync

PCINT(0) in PCMSK(x)

pcint_in_(0)

clk

pcint_syn

pcint_setflag

pcint_in_(n)

pcint_syn

cint_setflag

PCIF

12.3 Register Description

12.3.1 EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit 76543210 (0x69) Read/Write RRRRRRR/WR/W Initial Value00000000

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 12-1. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not gu aranteed to generate an int errupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

– – – – – – ISC01 ISC00 EICRA

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ATmega325P/3250P

Table 12-1. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.

12.3.2 EIMSK – External Interrupt Mask Register

Bit 76543210 (0xD1) PCIE3 PCIE2 PCIE1 PCIE0 Read/Write R/W R/W R/W R/W R R R R/W Initial Value00000000

• Bit 7 – PCIE3: Pin Change Interrupt Enable 3

When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 3 is enabled. Any change on any enabled PCINT30:24 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT3 Interrupt Vector. PCINT30:24 pins are enabled individually by the PCMSK3 Register.

This bit is reserved bit in ATmega325P and should always be written to zero.

• Bit 6 – PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT2 Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register.

– – –INT0EIMSK

This bit is reserved bit in ATmega325P and should always be written to zero.

• Bit 5 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT1 Interrupt Vector. PCINT15:8 pins are enabled individually by the PCMSK1 Register.

• Bit 4 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt. The corresponding interrupt of Pin Change I nterrupt Request is e xecuted from the PCINT0 Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register.

• Bit 0 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an out put. The corre sponding interr upt of Ext ernal Interrupt Request 0 is executed from the INT0 Interrupt Vector.

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12.3.3 EIFR – External Interrupt Flag Register

Bit 76543210 0x1C (0x3C) PCIF3 PCIF2 PCIF1 PCIF0 Read/Write R/W R/W R/W R/W R R R R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – PCIF3: Pin Change Interrupt Flag 3

When a logic change on any PCINT30:24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

This bit is reserved bit in ATmega325P and will always be read as zero.

• Bit 6 – PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT24:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

ATmega325P/3250P

– – – INTF0 EIFR

This bit is reserved bit in ATmega325P and will always be read as zero.

• Bit 5 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 4 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrup t requ est, INTF0 be comes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.

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ATmega325P/3250P

12.3.4 PCMSK3 – Pin Change Mask Register 3

Bit 76543210 (0x73) Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

– PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 PCMSK3

• Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30:24

Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT30:24 is set and the PCIE3 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT30:24 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

12.3.5 PCMSK2 – Pin Change Mask Register 2

Bit 76543210 (0x6D) PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial

Value

00000000

• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16

Each PCINT23:16 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

(1)

Note: 1. PCMSK3 and PCMSK2 are only present in ATmega3250P.

12.3.6 PCMSK1 – Pin Change Mask Register 1

Bit 76543210 (0x6C) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1

• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8

Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interr upt is enabled o n the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

12.3.7 PCMSK0 – Pin Change Mask Register 0

Bit 76543210 (0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0

Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interru pt is en ab led on the cor responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

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13. I/O-Ports

13.1 Overview

ATmega325P/3250P

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/ disabling of p ull-up resist ors (if con figured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. Port B has a higher pin driver strength than the other ports, but all the pin drivers are strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V

and Ground as indicated in Figure 13-1. Refer to ”Electrical Characteristics” on page 304 for

a complete list of parameters. If exceeding the pin voltage “Absolute Maximum Ratings”, resulting currents can harm the device if not limited accordingly.

Figure 13-1. I/O Pin Equivalent Schematic

Pxn

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” rep resents the bit number. However, when using the register or bit defines in a program , the precise form must be used. For examp le, PORTB3 for bit no. 3 in Port B, here documented ge ner ally as PO RTxn . The physical I /O Registers and bit locations are listed in ”Register Description” on page 85.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in ”Ports as General Digital I/O” on page

64. Most port pins are multiplexed with alternate func tions for the peripheral featur es on the

device. How each alternate function interferes with the port pin is described in ”Alternate Port

See Figure

"General Digital I/O" for

Logic

Details

8023E–AVR–06/08

ATmega325P/3250P

Functions” on page 69. Refer to the individual module sections for a full description of the alter-

nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

13.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O-port pin, here generically called Pxn.

Figure 13-2. General Digital I/O

Pxn

PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL

: I/O CLOCK

clk

I/O

(1)

SLEEP

Q D

DDxn

CLR

RESET

PORTxn

CLR

RESET

RRx

SYNCHRONIZER

DLQ

WDx: WRITE DDRx RDx: READ DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER

PINxn

PUD

WDx

RDx

RPx

clk

DATA B U S

WPx

WRx

I/O

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

13.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register

Description” on page 85, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin h as to

SLEEP, and PUD are common to all ports.

I/O

8023E–AVR–06/08

be configured as an output pin. The port pi ns are tri-stated when re set condition b ecomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

13.2.2 Toggli ng the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

13.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-sta te ({DDxn, PORTxn} = 0b00) o r the o utput high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

ATmega325P/3250P

Table 13-1 summarizes the control signals for the pin value.

Table 13-1. Port Pin Configurations

DDxn PORTxn

0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source)

13.2.4 Reading the Pin Value

Independent of the setting of Data Direction b it DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 13-2, t he PINxn Regist er bit a nd th e prece ding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also intro duces a delay. Fi gure 13-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are deno te d t

PUD

(in MCUCR) I/O Pull-up Comment

pd,max

and t

respectively.

pd,min

8023E–AVR–06/08

ATmega325P/3250P

Figure 13-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

XXX in r17, PINx

r17

XXX

0x00 0xFF

pd, max

pd, min

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 13-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r16

out PORTx, r16 nop in r17, PINx

r17

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

8023E–AVR–06/08

ATmega325P/3250P

Assembly Code Example

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

(1)

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

13.2.5 Digital Input Enable and Sleep Modes

As shown in Figure 13-2, the digital input signal can be clamped to ground at the input of the Schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standb y mode to avoid high power co nsumption if some input signals are left floating, or have an analog signal level close to V

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in ”Alternate Port Functions” on page 69.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the extern al interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

/2.

8023E–AVR–06/08

ATmega325P/3250P

13.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensure t hat these pins have a defi ned level. Even though most of the digital inputs are disabled in th e deep sleep modes as de scribed above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output.

or GND is not recommended, since this may caus e excessiv e currents if t he pin is

8023E–AVR–06/08

13.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5 shows how the port pin control signals from th e simplified Figure 13-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

ATmega325P/3250P

Figure 13-5. Alternate Port Functions

Pxn

(1)

PUOExn

PUOVxn

DDOExn

DDOVxn

PVOExn

PVOVxn

DIEOExn

DIEOVxn

SLEEP

SYNCHRONIZER

SET

DLQ

PINxn

CLR

PUD

DDxn

CLR

RESET

PORTxn

CLR

RESET

CLR

WDx

RDx

RRx

clk

RPx

PTOExn

WRx

WPx

I/O

DATA BU S

8023E–AVR–06/08

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

PUD: PULLUP DISABLE WDx: WRITE DDRx RDx: READ DDRx RRx: READ PORTx REGISTER WRx: WRITE PORTx RPx: READ PORTx PIN WPx: WRITE PINx clk

: I/O CLOCK

I/O

DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

I/O

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

Table 13-2 summarizes the function of the o verridin g signals. Th e pin and por t indexes f rom Fig- ure 13-5 are not shown in the succeeding tables. The overriding signals ar e gen erat ed intern ally

in the modules having the alternate function.

ATmega325P/3250P

Table 13-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

If this signal is set, the pull-up enable is controlled by the PUO V signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.

PUOE

Pull-up Override Enable

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI Digital Input

AIO

Pull-up Override Value

Data Direction Override Enable

Data Direction Override Value

Port Value Override Enable

Port Value Override Value

Port Toggle Override Enable

Digital Input Enable Override Enable

Digital Input Enable Override Value

Analog Input/Output

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.

If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.

If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.

If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode).

If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.

This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bidirectionally.

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

Some pins are connected to different LCS segments on ATmega325P and ATmega3250P. See pinout on ”Pinout ATmega3250P” on page 2 and ”Pinout ATme ga325P” on page 3 for details.

8023E–AVR–06/08

13.3.1 Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 13-3.

Table 13-3. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7

PB6

OC2A/PCINT15 Change Interrupt15).

OC1B/PCINT Change Interrupt14).

(Output Compare and PWM Output A for Timer/Counter2 or Pin

14 (Output Compare and PWM Output B for Timer/Counter1 or Pin

ATmega325P/3250P

PB5

PB4

PB3 MISO/PCINT11 PB2 MOSI/PCINT10 PB1 SCK/PCINT9 PB0 SS/PCINT8

OC1A/PCINT13 Change Interrupt13).

OC0A/PCINT12 Change Interrupt12).

(Output Compare and PWM Output A for Timer/Counter1 or Pin

(Output Compare and PWM Output A for Timer/Counter0 or Pin

(SPI Bus Master Input/Slave Output or Pin Change Interrupt11). (SPI Bus Master Output/Slave Input or Pin Change Interrupt10).

(SPI Bus Serial Clock or Pin Change Interrupt9).

(SPI Slave Select input or Pin Change Interrupt8).

The alternate pin configuration is as follows:

• OC2A/PCINT15, Bit 7

OC2, Output Compare Match A output: The PB7 pin can serve a s an external output for the Timer/Counter2 Output Compare A. The pin has to be config ured as an out put (DDB7 se t ( one )) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function.

PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external interrupt source.

• OC1B/PCINT14, Bit 6

OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be config ured as an out put (DDB6 se t ( one )) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

8023E–AVR–06/08

PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt source.

• OC1A/PCINT13, Bit 5

OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be config ured as an out put (DDB5 se t ( one )) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external interrupt source.

• OC0A/PCINT12, Bit 4

OC0A, Output Compare Match A output: The PB4 pin can serve as an external output for the Timer/Counter0 Output Compare A. The pin has to be config ured as an out put (DDB4 se t ( one )) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

ATmega325P/3250P

PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external interrupt source.

• MISO/PCINT11 – Port B, Bit 3

MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.

PCINT11, Pin Change Interrupt Source 11: The PB3 pin can serve as an external interrupt source.

• MOSI/PCINT10 – Port B, Bit 2

MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is e nabled as a Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.

PCINT10, Pin Change Interrupt Source 10: The PB2 pin can serve as an external interrupt source.

• SCK/PCINT9 – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.

PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt source.

•SS

/PCINT8 – Port B, Bit 0

: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0. As a Slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit

PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source.

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ATmega325P/3250P

Table 13-4 and Table 13-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 13-5 on page 69. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

Table 13-4. Overriding Signals for Alternate Functions in PB7:PB4

PB7/OC2A/

Signal Name

PUOE0000 PUOV0000 DDOE0000 DDOV0000 PVOE OC2A ENABLE OC1B ENABLE OC1A ENABLE OC0A ENABLE PVOV OC2A OC1B OC1A OC0A PTOE–––– DIEOE PCINT15 • PCIE1 PCINT14 • PCIE1 PCINT13 • PCIE1 PCINT12 • PCIE1 DIEOV1111 DI PCINT15 INPUT PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT AIO––––

PCINT15

PB6/OC1B/ PCINT14

PB5/OC1A/ PCINT13

PB4/OC0A/ PCINT12

Table 13-5. Overriding Signals for Alternate Functions in PB3:PB0

PB3/MISO/

Signal Name

PUOE SPE • MSTR SPE • MSTR

PCINT11

PB2/MOSI/ PCINT10

PB1/SCK/ PCINT9

SPE • MSTR SPE • MSTR

PB0/SS/ PCINT8

PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR DDOV0000 PVOE SPE • MSTR

PVOV

PTOE–––– DIEOE PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT9 • PCIE1 PCINT8 • PCIE1 DIEOV1111

AIO––––

SPI SLAVE OUTPUT

PCINT11 INPUT SPI MSTR INPUT

SPE • MSTR SPE • MSTR 0 SPI MSTR

OUTPUT

PCINT10 INPUT SPI SLAVE INPUT

SCK OUTPUT 0

PCINT9 INPUT SCK INPUT

PCINT8 INPUT SPI SS

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ATmega325P/3250P

13.3.2 Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 13-6.

Table 13-6. Port D Pins Alternate Functions (SEG refers to 100-pin/64-pin pinout)

Port Pin Alternate Function

PD7 PD6 PD5 PD4 PD3 PD2 PD1 INT0 PD0 ICP1 (Timer/Counter1 Input Capture pin)

(External Interrupt0 Input)

The alternate pin configuration is as follows:

•INT0 – Port D, Bit 1

INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt source to the MCU.

• ICP1 – Port D, Bit 0

ICP1 – Input Capture pin1: The PD0 pin can act as an Input Capture pin for Timer/Counter1.

Table 13-7 relates the alternate functions of Port D to the overrid in g sig nal s sh own in F igu re 135 on page 69.

Table 13-7. Overriding Signals for Alternate Functions in PD3:PD0

Signal Name PD3 PD2 PD1/INT0 PD0/ICP1

PUOE 0 0 0) 0 PUOV0000 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE0000 PVOV0000 PTOE–––– DIEOE 0 0 INT0 ENABLE 0 DIEOV 0 0 INT0 ENABLE 0 DI – – INT0 INPUT ICP1 INPUT AIO – – – –

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13.3.3 Alternate Functions of Port E

The Port E pins with alternate functions are shown in Table 13-8.

Table 13-8. Port E Pins Alternate Functions

Port Pin Alternate Function

ATmega325P/3250P

PE7

PE6 DO/PCINT6 (USI Data Output or Pin Change Interrupt6) PE5 DI/SDA/PCINT5 (USI Data Input or TWI Serial DAta or Pin Change Interrupt5)

PE4

PE3 AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3)

PE2

PE1 TXD/PCINT1 (USART0 Transmit Pin or Pin Change Interrupt1) PE0 RXD/PCINT0 (USART0 Receive Pin or Pin Change Interrupt0)

PCINT7 (Pin Change Interrupt7) CLKO (Divided System Clock)

USCK/SCL/PCINT4 (USART0 External Clock Input/Output or TWI Serial Clock or Pin Change Interrupt4)

XCK/AIN0/ PCINT2 (USART0 External Clock or Analog Comparator Positive Input or Pin Change Interrupt2)

• PCINT7 – Port E, Bit 7

PCINT7, Pin Change Interrupt Source 7: The PE7 pin can serve as an external interrupt source. CLKO, Divided System Clock: The divided system clock can be output on the PE7 pin. The

divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTE7 and DDE7 settings. It will also be output during reset.

• DO/PCINT6 – Port E, Bit 6

DO, Universal Serial Interface Data output. PCINT6, Pin Change Interrupt Source 6: The PE6 pin can serve as an external interrupt source.

• DI/SDA/PCINT5 – Port E, Bit 5

DI, Universal Serial Interface Data input. SDA, Two-wire Serial Interface Data: PCINT5, Pin Change Interrupt Source 5: The PE5 pin can serve as an external interrupt source.

• USCK/SCL/PCINT4 – Port E, Bit 4

USCK, Universal Serial Interface Clock. SCL, Two-wire Serial Interface Clock. PCINT4, Pin Change Interrupt Source 4: The PE4 pin can serve as an external interrupt source.

• AIN1/PCINT3 – Port E, Bit 3

AIN1 – Analog Comparator Negative input . This pi n is dire ctly connect ed to t he ne gat ive inpu t of the Analog Comparator.

PCINT3, Pin Change Interrupt Source 3: The PE3 pin can serve as an external interrupt source.

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ATmega325P/3250P

• XCK/AIN0/PCINT2 – Port E, Bit 2

XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 operates in synchronous mode.

AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator.

PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.

• TXD/PCINT1 – Port E, Bit 1

TXD0, UART0 Transmit pin. PCINT1, Pin Change Interrupt Source 1: The PE1 pin can serve as an external interrupt source.

• RXD/PCINT0 – Port E, Bit 0

RXD, USART0 Receive pin. Receive Data (Data input pin for the USART0). When the USART0 Receiver is enabled this pin is configured as an input regardless of the value of DDE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.

PCINT0, Pin Change Interrupt Source 0: The PE0 pin can serve as an external interrupt source.

Table 13-9 and Table 13-10 relates the alternate functions of Port E to the overriding signals

shown in Figure 13-5 on page 69.

Table 13-9. Overriding Signals for Alternate Functions PE7:PE4

PE6/DO/

Signal Name PE7/PCINT7

PUOE 0 0 USI_TWO-WIRE USI_TWO-WIRE PUOV0000 DDOE CKOUT

DDOV 1 0

PVOE CKOUT

PVOV clk PTOE––0USITC

DIEOE PCINT7 • PCIE0 PCINT6 • PCIE0

DIEOV1111

DI PCINT7 INPUT PCINT6 INPUT

AIO––––

Note: 1. CKOUT is one if the CKOUT Fuse is programmed

(1)

I/O

PCINT6

0 USI_TWO-WIRE USI_TWO-WIRE

USI_THREEWIRE

DO 0 0

PE5/DI/SDA/ PCINT5

(SDA + POR TE5) • DDE5

USI_TWO-WIRE • DDE5

(PCINT5 • PCIE0) + USISIE

DI/SDA INPUT PCINT5 INPUT

PE4/USCK/SCL/ PCINT4

(USI_SCL_HOLD + PORTE4 DDE4

USI_TWO-WIRE • DDE4

(PCINT4 • PCIE0) + USISIE

USCKL/SCL INPUT

PCINT4 INPUT

) •

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ATmega325P/3250P

Table 13-10. Overriding Signals for Alternate Functions in PE3:PE0

Signal Name

PUOE 0

PUOV0XCK0PORTE0 • PUD DDOE 0 0 TXEN RXEN DDOV0010 PVOE 0 0 TXEN 0 PVOV 0 0 TXD 0 PTOE––––

DIEOE

DIEOV PCINT3 • PCIE0 PCINT2 • PCIE0 1 1

DI PCINT3 INPUT

AIO AIN1 INPUT AIN0 INPUT – –

Note: 1. AIN0D and AIN1D is described in ”DIDR1 – Digital Input Disable Register 1” on page 205.

13.3.4 Alternate Functions of Port F

The Port F has an alternate function as analog input for the ADC as shown in Table 13-11. If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs.

PE3/AIN1/ PCINT3

(PCINT3 • PCIE0) + AIN1D

(1)

PE2/XCK/AIN0/ PCINT2

XCK OUTPUT ENABLE

(PCINT2 • PCIE0) + AIN0D

XCK/PCINT2 INPUT

(1)

PE1/TXD/ PCINT1

TXEN RXEN

PCINT1 • PCIE0 PCINT0 • PCIE0

PCINT1 INPUT

PE0/RXD/ PCINT0

RXD/PCINT0 INPUT

8023E–AVR–06/08

Table 13-11. Port F Pins Alternate Functions

Port Pin Alternate Function

PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input) PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) PF5 ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) PF4 ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) PF3 ADC3 (ADC input channel 3) PF2 ADC2 (ADC input channel 2) PF1 ADC1 (ADC input channel 1) PF0 ADC0 (ADC input channel 0)

• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, Channel 7

TDI, JTAG Test Data In: Serial input dat a to be shif ted in t o the In struction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

ATmega325P/3250P

• TDO, ADC6 – Port F, Bit 6

ADC6, Analog to Digital Converter, Channel 6

TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high.

• TMS, ADC5 – Port F, Bit 5

ADC5, Analog to Digital Converter, Channel 5

TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TCK, ADC4 – Port F, Bit 4

ADC4, Analog to Digital Converter, Channel 4

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• ADC3 - ADC0 – Port F, Bit 3:0

Analog to Digital Converter, Channel 3-0.

Table 13-12. Overriding Signals for Alternate Functions in PF7:PF4

Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK

PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV1111 DDOEJTAGENJTAGENJTAGENJTAGEN

DDOV 0

PVOE 0 JTAGEN 0 0 PVOV0TDO00 PTOE–––– DIEOEJTAGENJTAGENJTAGENJTAGEN DIEOV 0 0 0 1 DI––––

AIO

TDI ADC7 INPUT

SHIFT_IR + SHIFT_DR

ADC6 INPUT

TMS ADC5 INPUT

TCK ADC4 INPUT

8023E–AVR–06/08

Table 13-13. Overriding Signals for Alternate Functions in PF3:PF0

Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0

PUOE0000 PUOV0000 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE0000 PVOV0000 PTOE–––– DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI–––– AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT

13.3.5 Alternate Functions of Port G

ATmega325P/3250P

The alternate pin configuration is as follows:

Table 13-14. Port G Pins Alternate Functions (SEG ref ers to 100-pin/64-pin pinout)

Port Pin Alternate Function

PG5 RESET PG4 T0(Timer/Counter0 Clock Input) PG3 T1(Timer/Counter1 Clock Input) PG2 – PG1 – PG0 –

Note: 1. Port G, PG5 is input only. Pull-up is always on.

See Table 25-3 on page 272 for RSTDISBL fuse.

(1)

The alternate pin configuration is as follows:

• RESET

RESET

– Port G, Bit 5

: External Reset input. When the RSTDISBL Fuse is programmed (‘0’), PG5 will function

as input with pull-up always on.

• T0 – Port G, Bit 4

T0, Timer/Counter0 Counter Source.

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• T1 – Port G, Bit 3

T1, Timer/Counter1 Counter Source.

Table 13-14 and Table 13-15 relates the alternate functions of Port G to the overriding signals

shown in Figure 13-5 on page 69.

ATmega325P/3250P

Table 13-15. Overriding Signals for Alternate Functions in PG4 and PG3

Signal Name PG4/T0 PG3/T1

PUOE 0 0 PUOV 0 0 DDOE 0 0 DDOV 0 0 PVOE 0 0 PVOV 0 0 PTOE – – DIEOE 0 0 DIEOV 0 0 DI T0 INPUT T1 INPUT AIO – –

13.3.6 Alternate Functions of Port H

Port H is only present in ATmega3250P. The alternate pin configuration is as follows:

Table 13-16. Port H Pins Alternate Functions

Port Pin Alternate Function

PH7 PCINT2 3(Pin Change Interrupt23) PH6 PCINT2 2 (Pin Change Interrupt22) PH5 PCINT2 1(Pin Change Interrupt21) PH4 PCINT2 0(Pin Change Interrupt20) PH3 PCINT1 9 (Pin Change Interrupt19) PH2 PCINT1 8(Pin Change Interrupt18) PH1 PCINT1 7(Pin Change Interrupt17) PH0 PCINT1 6(Pin Change Interrupt16)

The alternate pin configuration is as follows:

• PCINT23 – Port H, Bit 7

PCINT23, Pin Change Interrupt Source 23: The PH7 pin can serve as a n external interrupt source.

• PCINT22 – Port H, Bit 6

PCINT22, Pin Change Interrupt Source 22: The PH6 pin can serve as a n external interrupt source.

• PCINT21 – Port H, Bit 5

PCINT21, Pin Change Interrupt Source 21: The PH5 pin can serve as a n external interrupt source.

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ATmega325P/3250P

• PCINT20 – Port H, Bit 4

PCINT20, Pin Change Interrupt Source 20: The PH4 pin can serve as a n external interrupt source.

• PCINT19– Port H, Bit 3

PCINT19, Pin Change Interrupt Source 19: The PH3 pin can serve as a n external interrupt source.

• PCINT18 – Port H, Bit 2

PCINT18, Pin Change Interrupt Source 18: The PH2 pin can serve as a n external interrupt source.

• PCINT17/SEG – Port H, Bit 1

PCINT17, Pin Change Interrupt Source 17: The P1 pin can serve as an external interrupt source.

SEG, LCD front plane 9.

• PCINT16 – Port H, Bit 0

PCINT16, Pin Change Interrupt Source 16: The PH0 pin can serve as a n external interrupt source.

Table 13-17 and Table 13-18 relates the alternate functions of Port H to the overriding sign als

shown in Figure 13-5 on page 69.

Table 13-17. Overriding Signals for Alternate Functions in PH7:4

Signal Name PH7/PCINT23 PH6/PCINT22 PH5/PCINT21 PH4/PCINT20

PUOE0000 PUOV0000 DDOE0000 DDOV0000 PVOE0000 PVOV0000 PTOE–––– DIEOE PCINT23 • PCIE0 PCINT22 • PCIE0 PCINT21 • PCIE0 PCINT20 • PCIE0 DIEOV0000 DI PCINT23 INPUT PCINT22 INPUT PCINT21 INPUT PCINT20 INPUT AIO––––

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ATmega325P/3250P

Table 13-18. Overriding Signals for Alternate Functions in PH3:0

Signal Name PH3/PCINT19 PH2/PCINT18 PH1/PCINT17 PH0/PCINT16

PUOE0000 PUOV0000 DDOE0000 DDOV0000 PVOE0000 PVOV0000 PTOE–––– DIEOE PCINT19 • PCIE0 PCINT18 • PCIE0 PCINT17 • PCIE0 PCINT16 • PCIE0 DIEOV0000 DI PCINT19 INPUT PCINT18 INPUT PCINT17 INPUT PCINT16 INPUT AIO––––

13.3.7 Alternate Functions of Port J

Port J is only present in ATmega3250P. The alternate pin configuration is as follows:

Table 13-19. Port J Pins Alternate Functions

Port Pin Alternate Function

PJ6 PCINT30(Pin Change Interrupt30) PJ5 PCINT29(Pin Change Interrupt29) PJ4 PCINT28(Pin Change Interrupt28) PJ3 PCINT27(Pin Change Interrupt27) PJ2 PCINT26(Pin Change Interrupt26) PJ1 PCINT25(Pin Change Interrupt25) PJ0 PCINT24(Pin Change Interrupt26)

The alternate pin configuration is as follows:

• PCINT30 – Port J, Bit 6

PCINT30, Pin Change Interrupt Source 30: The PE30 pin can serve as an external interrupt source.

• PCINT29 – Port J, Bit 5

PCINT29, Pin Change Interrupt Source 29: The PE29 pin can serve as an external interrupt source.

• PCINT28 – Port J, Bit 4

PCINT28, Pin Change Interrupt Source 28: The PE28 pin can serve as an external interrupt source.

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ATmega325P/3250P

• PCINT27 – Port J, Bit 3

PCINT27, Pin Change Interrupt Source 27: The PE27 pin can serve as an external interrupt source.

• PCINT26 – Port J, Bit 2

PCINT26, Pin Change Interrupt Source 26: The PE26 pin can serve as an external interrupt source.

• PCINT25 – Port J, Bit 1

PCINT25, Pin Change Interrupt Source 25: The PE25 pin can serve as an external interrupt source.

• PCINT24 – Port J, Bit 0

PCINT24, Pin Change Interrupt Source 24: The PE24 pin can serve as an external interrupt source.

Table 13-20 and Table 13-21 relates the alternate functions of Port J to the overriding signals

shown in Figure 13-5 on page 69.

Table 13-20. Overriding Signals for Alternate Functions in PJ7:4

Signal Name PJ7 PJ6/PCINT30 PJ5/PCINT29 PJ4/PCINT28

PUOE0000 PUOV0000 DDOE0000 DDOV0000 PVOE0000 PVOV0000 PTOE–––– DIEOE 0 PCINT30 • PCIE0 PCINT2 9 • PCIE0 PCINT28 • PCIE0 DIEOV0000 DI–––– AIO––––

8023E–AVR–06/08

ATmega325P/3250P

Table 13-21. Overriding Signals for Alternate Functions in PH3:0

Signal Name PJ3/PCINT27 PJ2/PCINT26 PJ1/PCINT25 PJ0/PCINT24

PUOE0000 PUOV0000 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE0000 PVOV0000 PTOE–––– DIEOE PCINT27 • PCIE0 PCINT26 • PCIE0 PCINT25 • PCIE0 PCINT24 • PCIE0 DIEOV0000 DI–––– AIO––––

8023E–AVR–06/08

13.4 Register Description

13.4.1 MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0 0x35 (0x55) Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ”Con-

figuring the Pin” on page 64 for more details about this feature.

13.4.2 PORT A – Port A Data Register

Bit 76543210 0x02 (0x22) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

13.4.3 DDRA – Port A Data Direction Register

JTD BODS BODSE PUD – – IVSEL IVCE MCUCR

PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0

ATmega325P/3250P

PORTA

Bit 76543210 0x01 (0x21) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

13.4.4 PINA – Port A Input Pins Address

Bit 76543210 0x00 (0x20) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

13.4.5 PORTB – Port B Data Register

Bit 76543210 0x05 (0x25) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

13.4.6 DDRB – Port B Data Direction Register

Bit 76543210 0x04 (0x24) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

13.4.7 PINB – Port B Input Pins Address

8023E–AVR–06/08

Bit 76543210 0x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

ATmega325P/3250P

13.4.8 PORTC – Port C Data Register

Bit 76543210 0x08 (0x28) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

13.4.9 DDRC – Port C Data Direction Register

Bit 76543210 0x07 (0x27) DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

13.4.10 PINC – Port C Input Pins Address

Bit 76543210 0x06 (0x26) PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

13.4.11 PORTD – Port D Data Register

Bit 76543210 0x0B (0x2B) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

13.4.12 DDRD – Port D Data Direction Register

Bit 76543210 0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

13.4.13 PIND – Port D Input Pins Address

Bit 76543210 0x09 (0x29) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

13.4.14 PORTE – Port E Data Register

Bit 76543210 0x0E (0x2E) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE

13.4.15 DDRE – Port E Data Direction Register

Bit 76543210 0x0D (0x2D) DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

8023E–AVR–06/08

13.4.16 PINE – Port E Input Pins Address

Bit 76543210 0x0C (0x2C) PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

13.4.17 PORTF – Port F Data Register

Bit 76543210 0x11 (0x31) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 PORTF

13.4.18 DDRF – Port F Data Direction Register

Bit 76543210 0x10 (0x30) DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

13.4.19 PINF – Port F Input Pins Address

ATmega325P/3250P

Bit 76543210 0x0F (0x2F) PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

13.4.20 PORTG – Port G Data Register

Bit 76543210 0x14 (0x34) ––– Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

13.4.21 DDRG – Port G Data Direction Register

Bit 76543210 0x13 (0x33) – – – DDG4 DDG3 DDG2 DDG1 DDG0 DDRG Read/Write R R R R/W R/W R/W R/W R/W Initial Value00000000

13.4.22 PING – Port G Input Pins Address

Bit 76543210 0x12 (0x32) – – PING5 PING4 PING3 PING2 PING1 PING0 PING Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 N/A N/A N/A N/A N/A

13.4.23 PORTH – Port H Data Register

(1)

PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG

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Bit 76543210 (0xDA) PORTH7 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 PORTH

ATmega325P/3250P

13.4.24 DDRH – Port H Data Direction Register

Bit 76543210 (0xD9) DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 DDRH Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

13.4.25 PINH – Port H Input Pins Address

Bit 76543210 (0xD8) PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 PINH Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

13.4.26 PORTJ – Port J Data Register

Bit 76543210 (0xDD) – Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

(1)

PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 PORTJ

13.4.27 DDRJ – Port J Data Direction Register

Bit 76543210 (0xDC) – DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 DDRJ Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

13.4.28 PINJ – Port J Input Pins Address

(1)

Bit 76543210 (0xDB) – PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 PINJ Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 N/A N/A N/A N/A N/A N/A N/A

Note: 1. Register only available in ATmega3250P.

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14. 8-bit Timer/Counter0 with PWM

14.1 Features

• Single Compare Unit Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• External Event Counter

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)

14.2 Overview

Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual placement of I/O pins, refer to ”Pinout ATmega3250P” on page 2 and ”Pinout ATmega325P” on page 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The devicespecific I/O Register and bit locations are listed in the ”Register Description” on page 102.

Figure 14-1. 8-bit Timer/Counter Block Diagram

ATmega325P/3250P

14.2.1 Registers

TCCRn

count

clear

direction

BOTTOM

Timer/Counter

TCNTn

= 0

Control Logic

TOP

0xFF

clk

Clock Select

Edge

Detector

( From Prescaler )

DATA BU S

OCRn

Wavefo rm

Generation

TOVn

(Int.Req.)

OCn

(Int.Req.)

OCn

The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

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The Timer/Counter can be clocked internally, via th e prescaler, or b y an external clo ck source on the T0 pin. The Clock Select logic block controls which clock source a nd edge the Tim er/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk

ATmega325P/3250P

14.2.2 Definitions

TOVn

The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0A). See Sect ion “1 4. 5”

on page 92. for details. The compare match event will also set the Compare Flag (OCF0A)

which can be used to generate an Output Compare interrupt request.

Many register and bit references in this section are written in genera l form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare unit number, in this case unit A. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.

The definitions in Table 14-1 are also used extensively throughout the document. Table 14-1. Definitions of Timer/Counter values.

BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Re gister. The assignment is dependent on the mode of operation.

14.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0A) . For details o n clock sources and p rescaler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on page 100.

14.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

14-2 shows a block diagram of the counter and its surroundings.

Figure 14-2. Counter Unit Block Diagram

DATA BUS

TCNTn Control Logic

Signal description (internal signals):

count clear

direction

bottom

top

(Int.Req.)

clk

Clock Select

Edge

Detector

( From Prescaler )

count Increment or de cre m en t TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero).

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ATmega325P/3250P

clk

Timer/Counter clock, referred to as clkT0 in the following.

top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk

). clkT0 can be generated from an external or internal clock source,

selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk

is present or not. A CPU write overrides (has priority over) all counter clear or

count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0A). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see

”Modes of Operation” on page 94.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

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ATmega325P/3250P

14.5 Output Compare Unit

WGMn1:0

COMnX1:0

The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0A Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM0A1:0 ) bits. The max and bott om signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See Section “14.7” on page 94.).

Figure 14-3 shows a block diagram of the Output Compare unit.

Figure 14-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

= (8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer o n Compare ( CTC) modes of o peration , the doub le buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

Waveform Generator

OCnx

The OCR0A Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is disabled the CPU will access the OCR0A directly.

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14.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare match had occurred (the COM0A1:0 bits se ttings define whether the OC0A pin is set, cleared or toggled).

14.5.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initialized to the same value as TCNT0 without triggering an inte rrupt when the Timer/Counte r clock is enabled.

14.5.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is counting down.

ATmega325P/3250P

The setup of the OC0A should be performed before setting the Data Dire ction Register for the port pin to output. The easiest way of setting the OC0A value is to use the Force Output Compare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when changing between Waveform Generation modes.

Be aware that the COM0A1:0 bits are not double buffered together with the compare value. Changing the COM0A1:0 bits will take effect immediately.

14.6 Compare Match Output Unit

The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 14-4 shows a simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. If a System Reset occur, the OC0A Register is reset to “0”.

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ATmega325P/3250P

Figure 14-4. Compare Match Output Unit, Schematic

COMnx1

COMnx0 FOCn

clk

I/O

Waveform

Generator

OCnx

PORT

DATA BU S

DDR

OCn

The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is visible on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of operation. See ”Register Description” on page 102.

14.6.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on the OC0A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 1 4- 3 on pa ge 1 03. For fast PWM mode, refer to Table 14-

4 on page 103, and for phase correct PWM refer to Table 14-5 on page 103.

A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits.

14.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Gen eration mode (WGM01:0) and Comp are Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See Section “14.6” on page 93.).

For detailed timing information refer to Figure 4, Figure 5, Figure 6 and Figure 7 in

”Timer/Counter Timing Diagrams” on page 99.

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14.7.1 Normal Mode

O (

The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime.

The Output Compare unit can be used to ge nerat e int errup t s at so me given time . Usin g the Ou tput Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

14.7.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero wh en the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output fre quency. It also simplifies the operation of counting exte rn al ev en ts.

ATmega325P/3250P

The timing diagram for the CTC mode is shown in Figure 14-5. The counter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.

Figure 14-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

CNTn

Toggle)

eriod

1 4

2 3

(COMnx1:0 = 1)

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.

For generating a waveform output in CT C mod e, the O C0A outp ut can be set to t oggle it s logica l level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

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ATmega325P/3250P

14.7.3 Fast PWM Mode

--- -

the pin is set to output. The waveform generated will have a maximum frequency of f f

/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

clk_I/O

OC0

equation:

OCnx

----------------------------------------------

2 N 1 OCRnx+()⋅⋅

clk_I/O

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same tim er clock cycle tha t the

counter counts from MAX to 0x00.

The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation . The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slop es represent compare matches between OCR0A and TCNT0.

Figure 14-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Se

OCRnx Update and TOVn Interrupt Flag Set

CNTn

eriod

2 3

4 5 6 7

(COMnx1:0 = 2)

(COMnx1:0 = 3)

The Timer/Counter Overflow Flag (TOV0) is set each ti me the co unte r reache s MAX. If t he inte rrupt is enabled, the interrupt handler routine can be used for updating the compare value.

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ATmega325P/3250P

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 14-4 on page 103). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clear ing) t he OC0A Regist er at the compare match between OCR0A and TCNT0, and clearing (or setting) the OC0A Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

OC0

clk_I/O

----------------- -=

N 256⋅

= f

/2 when OCR0A is set to zero. This

clk_I/O

OCnxPWM

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Regis ter represe nts specia l cases when generat ing a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The wave form generated will have a maximum frequency of f feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.

14.7.4 Phase Correct PWM Mode

The phase correct PWM mode (WG M01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A while counting up, and set on the comp are match while counting down. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the p hase correct PWM mod e is shown on Figure 1 4-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent com p ar e ma tc he s be twe e n OCR0A and TCNT0.

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ATmega325P/3250P

Figure 14-7. Phase Correct PWM Mode, Timing Diagram

TCNTn

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

OCn

Period

1 2 3

(COMnx1:0 = 2)

(COMnx1:0 = 3)

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTT OM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0A1:0 to t hree ( See Table 14-5 on page 103). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is genera ted by clearing ( or setting) t he OC0A Register a t the compare match between OCR0A and TCNT0 when the counter increments, and setting (or clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:

clk_I/O

OCnxPCPWM

----------------- -=

N 510⋅

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If th e OCR0A is set equal to BOTTOM , the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 14-7 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value from MAX, like in Figure 14-7. When the OCR0A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

8023E–AVR–06/08

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason

misses the Compare Match and hence the OCn change that would ha v e ha ppened on the w a y up.

14.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. Th e figures include information on whe n Interrupt Flags are set. Figure 4 contains timing data for basic Timer/ Counte r operat ion. T he fig ure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 4. Timer/Counter Timing Diagram, no Prescaling

clk

I/O

clk

(clk

/1)

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

ATmega325P/3250P

TOVn

Figure 5 shows the same timing data, but with the pres caler enabled.

Figure 5. Timer/Counter Timing Diagram, with Prescaler (f

clk

I/O

clk

(clk

/8)

I/O

TCNTn

TOVn

MAX - 1 MAX BOTTOM BOTTOM + 1

clk_I/O

/8)

Figure 6 shows the setting of OCF0A in all modes except CTC mode.

Figure 6. Timer/Counter Timing Diagram, Setting of OC F0 A, with Prescaler (f

clk

I/O

clk

(clk

/8)

I/O

clk_I/O

/8)

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TCNTn

OCRnx

OCFnx

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

OCRnx Value

ATmega325P/3250P

Figure 7 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 7. Timer/Counter Timing Diagram, Clear Timer on Compar e Match mode, with Prescaler

/8)

clk_I/O

clk

I/O

clk

(clk

/8)

I/O

TCNTn

(CTC)

TOP - 1 TOP BOTTOM BOTTOM + 1

OCRnx

OCFnx

14.9 Timer/Counter0 and Timer/Counter1 Prescalers

Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0.

14.9.1 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by settin g the CSn2 :0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

14.9.2 Prescaler Reset

clock frequency (f clock source. The prescaled clock has a frequency of either f f

/1024.

CLK_I/O

The prescaler is free running, i.e., operates independently of t he Clock Select logic of the Timer/Counter, and it is shared by Timer/Counter1 and Timer/Cou nter0. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The numb er of syst em clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

). Alternatively, one of four taps from the prescaler can be used as a

CLK_I/O

TOP

CLK_I/O

/8, f

CLK_I/O

/64, f

CLK_I/O

/256, or

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to.

14.9.3 External Clock Source

An external clock source applied to the T1/T0 pin can be used a s Timer/Counter clock (clk logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 14-8 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the po sitive edge of the internal system clock ( is transparent in the high period of the internal system clock.

100

/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization

clk

). The latch

I/O

8023E–AVR–06/08

ATMEL ATmega325P, ATmega325PV, ATmega3250P, ATmega3250PV User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

1.1 Disclaimer

2. Overview

2.1 Block Diagram

2.2 Comparison between ATmega325P and ATmega3250P

2.3 Pin Descriptions

2.3.2 GND

2.3.3 Port A (PA7..PA0)

2.3.4 Port B (PB7..PB0)

2.3.5 Port C (PC7..PC0)

2.3.6 Port D (PD7..PD0)

2.3.7 Port E (PE7..PE0)

2.3.8 Port F (PF7..PF0)

2.3.9 Port G (PG5..PG0)

2.3.10 Port H (PH7..PH0)

2.3.11 Port J (PJ6..PJ0)

2.3.12 RESET

2.3.13 XTAL1

2.3.14 XTAL2

2.3.15 AVCC

2.3.16 AREF

3. Resources

4. Data Retention

5. About Code Examples

6. AVR CPU Core

6.1 Overview

6.2 Architectural Overview

6.4 AVR Status Register

6.5 General Purpose Register File

6.5.1 The X-register, Y-register , and Z-register

6.6 Stack Pointer

6.7 Instruction Execution Timing

6.8 Reset and Interrupt Handling

6.8.1 Interrupt Response Time

7. AVR Memories

7.1 Overview

7.2 In-System Reprogrammable Flash Program Memory

7.3 SRAM Data Memory

7.3.1 Data Memory Access Times

7.4 EEPROM Data Memory

7.4.1 EEPROM Read/Write Access

7.4.2 EEPROM Write During Power-down Sleep Mode

7.4.3 Preventing EEPROM Corruption

7.5 I/O Memory

7.6 Register Description

7.6.4 General Purpose I/O Registers

8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

8.2 Clock Sources

8.3 Default Clock Source

8.4 Crystal Oscillator

8.5 Low-frequency Crystal Oscillator

8.6 Calibrated Internal RC Oscillator

8.7 External Clock

8.8 Clock Output Buffer

8.9 Timer/Counter Oscillator

8.10 System Clock Prescaler

8.10.1 Switching Time

8.11 Register Description

9. Power Management and Sleep Modes

9.1 Overview

9.2 Sleep Modes

9.3 BOD Disable

9.4 Idle Mode

9.5 ADC Noise Reduction Mode

9.6 Power-down Mode

9.7 Power-save Mode

9.8 Standby Mode

9.9 Po wer Reduction Register

9.10 Minimizing Power Consumption

9.10.1 Analog to Digital Converter

9.10.2 Analog Comparator

9.10.3 Brown-out Detector

9.10.4 Internal Voltage Reference

9.10.5 Watchdog Timer