Atmel ATmega324PA User Manual

Features

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-chip 2-cycle Multiplier

• High Endurance Non-volat ile Memory segments

– 32K Bytes of In-System Self-programmable Flash program memory – 1K Bytes EEPROM – 2K Bytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/ 100 years at 25°C – Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits thr ough the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Six PWM Channels – 8-channel, 10-bit ADC

Differential mode with selectable gain at 1x, 10x or 200x – Byte-oriented Two-wire Serial Interface – Two Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power -save, Power-down, Standby and

Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF

– 44-pad DRQFN – 49-ball VFBGA

• Operating Voltages

– 1.8 - 5.5V

• Speed Grades

– 0 - 20MHz @ 1.8 - 5.5V

• Power Consumption at 1 MHz, 1.8V, 25°C

– Active: 0.4 mA – Power-down Mode: 0.1µA – Power-save Mode: 0.6µA (Including 32 kHz RTC)

8-bit Microcontroller

(1)

8-bit

Microcontroller with 32K Bytes In-System Programmable Flash

ATmega324PA

Summary

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1. Pin Configurations

(PCINT8/XCK0/T0) PB0

(PCINT9/CLKO/T1) PB1

(PCINT10/INT2/AIN0) PB2

(PCINT11/OC0A/AIN1) PB3

(PCINT12/OC0B/SS) PB4

(PCINT13/MOSI) PB5 (PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND XTAL2 XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVC C PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16) PD7 (OC2A/PCINT31)

PDIP

PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVC C PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20)

(PCINT13/MOSI) PB5 (PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND XTAL2 XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

(PCINT31/OC2A) PD7

VCC

GND

(PCINT16/SCL) PC0

(PCINT17/SDA) PC1

(PCINT18/TCK) PC2

(PCINT19/TMS) PC3

PB4 (SS/OC0B/PCINT12)

PB3 (AIN1/OC0A/PCINT11)

PB2 (AIN0/INT2/PCINT10)

PB1 (T1/CLKO/PCINT9)

PB0 (XCK0/T0/PCINT8)

GND

VCC

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

TQFP/VQFN/QFN/MLF

1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF

Figure 1-1. Pinout

Note: The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on

the board to ensure good mechanical stability.

ATmega324PA

8152AS–AVR–11/08

1.2 Pinout - DRQFN

Top view Bottom view

A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6

A18 B15 A17 B14 A16 B13 A15 B12 A14 B11 A13

A12

B10

A11

A10

B8A9 B7A8 B6

A24

B20

A23

B19

A22

B18

A21

B17

A20

B16

A19

A18 B15 A17 B14 A16 B13 A15 B12 A14 B11 A13

A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6

A19

B16

A20

B17

A21

B18

A22

B19

A23

B20

A24

Figure 1-2. DRQFN - Pinout

ATmega324PA

Table 1-1. DRQFN - Pinout

A1 PB5 A7 PD3 A13 PC4 A19 PA3 B1 PB6 B6 PD4 B11 PC5 B16 PA2 A2 PB7 A8 PD5 A14 PC6 A20 PA1 B2 RESET A3 VCC A9 PD7 A15 AVCC A21 VCC B3 GND B8 VCC B13 GND B18 GND A4 XTAL2 A10 GND A16 AREF A22 PB0 B4 XTAL1 B9 PC0 B14 PA7 B19 PB1 A5 PD0 A11 PC1 A17 PA6 A23 PB2 B5 PD1 B10 PC2 B15 PA5 B20 PB3

8152AS–AVR–11/08

A6 PD2 A12 PC3 A18 PA4 A24 PB4

B7 PD6 B12 PC7 B17 PA0

1.3 Pinout - VFBGA

B C D E F G

1 234567

B C D E F G

7654321

Top view Bottom view

Figure 1-3. VFBGA - Pinout

Table 1-2. BGA - Pinout

1234567

A GND PB4 PB2 GND VCC PA2 GND B PB6 PB5 PB3 PB0 PA0 PA3 PA5 C VCC RESET PB7 PB1 PA1 PA6 AREF D GND XTAL2 PD0 GND PA4 PA7 GND E XTAL1 PD1 PD5 PD7 PC5 PC7 AVCC F PD2 PD3 PD6 PC0 PC2 PC4 PC6 G GND PD4 VCC GND PC1 PC3 GND

ATmega324PA

8152AS–AVR–11/08

2. Overview

CPU

GND

VCC

RESET

Power

Supervision

POR / BOD &

RESET

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

XTAL1

XTAL2

PORT A (8)

PORT D (8)

PD7..0

PORT C (8)

PC5..0

TWI

SPI

EEPROM

JTAG/OCD

16bit T/C 1

8bit T/C 2

8bit T/C 0

SRAMFLASH

USART 0

Internal

Bandgap reference

Analog

Comparator

A/D

Converter

PA7..0

PORT B (8)

PB7..0

USART 1

TOSC1/PC6TOSC2/PC7

The ATmega324PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PA achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

ATmega324PA

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

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The ATmega324PA provides the following features: 32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscilla tor, an SPI serial port, IEEE std. 1149. 1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU wh ile allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modu les except Asynchr onous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega324PA is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega324PA AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

ATmega324PA

8152AS–AVR–11/08

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port A (P A7:PA0)

Port A serves as analog inputs to the Analog-to-digital Conver ter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-st ated when a reset co ndition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega324PA as listed on

page 81.

ATmega324PA

2.2.4 Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega324PA as listed on

page 83.

2.2.5 Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the ATmega324PA as listed on page 86.

2.2.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

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Port D also serves the functions of various special features of the ATmega324PA as listed on

page 88.

2.2.7 RESET

2.2.8 XTAL1

2.2.9 XTAL2

2.2.10 AVCC

2.2.11 AREF

3. Resources

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characteristics” on page 329. Shorter pulses are not guaranteed to generate a rese t.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It shou ld be exte rnally connected to V to V

through a low-pass filter.

This is the analog reference pin for the Analog-to-digital Converter.

, even if the ADC is not used. If the ADC is used, it should be connected

4. Data Retention

A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr.

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

ATmega324PA

8152AS–AVR–11/08

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