Atmel ATmega16U4, ATmega32U4 User Manual

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ATmega16U4/ATmega32U4

8-bit Microcontroller with 16/32K bytes of ISP Flash and

USB Controller

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Features

• High Performance, Low Power AVR

8-Bit Microcontroller

• Advanced RISC Architecture

– 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Worki ng Re gisters – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– 16/32KB of In-System Self-Programmable Flash – 1.25/2.5KB Internal SRAM – 512Bytes/1KB Internal EEPROM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85C/ 100 years at 25C – Optional Boot Code Section with Independent Lo ck Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation Parts using external XTAL clock are pre -prog rame d with a default USB bootloader

– Programming Lock for Software Security

• JTAG (IEEE

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

std. 1149.1 compliant) Interface

(1)

• USB 2.0 Full-speed/Low Speed Device Module with Interrupt on Transfer Completion

– Complies fully with Universal Serial Bus Specification Rev 2.0 – Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s – Endpoint 0 for Control Transfers: up to 64-bytes – Six Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or

Isochronous Transfers – Configurable Endpoints size up to 256 bytes in double bank mode – Fully independent 832 bytes USB DPRAM for endpoint memory allocation – Suspend/Resume Interrupts – CPU Reset possible on USB Bus Reset detection – 48MHz from PLL for Full-speed Bus Operation – USB Bus Connection/Disconnection on Microcontroller Request – Crystal-less operation for Low Speed mode

• Peripheral Features

– On-chip PLL for USB and High Speed Timer: 32 up to 96MHz operation – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

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– Two 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode – One 10-bit High-Speed Timer/Counter with PLL (64MHz) and Compare Mode – Four 8-bit PWM Channels – Four PWM Channels with Programmable Resolution from 2 to 16 Bits – Six PWM Channels for High Speed Operation, with Programmable Resolution from 2 to 11 Bits – Output Compare Modulator – 12-channels, 10-bit ADC (features Differential Channels with Programmable Gain) – Programmable Serial USART with Hardware Flow Control – Master/Slave SPI Serial Interface – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wa ke -u p on Pin Change – On-chip Temperature Sensor

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal 8MHz Calibrated Oscillator – Internal clock prescaler and On-the-fly Clock Switching (Int RC / Ext Osc) – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– All I/O combine CMOS outputs and LVTTL inputs – 26 Programmable I/O Lines – 44-lead TQFP Package, 10x10mm – 44-lead QFN Package, 7x7mm

• Operating Voltages

– 2.7 - 5.5V

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8MHz at 2.7V - Industrial range – 16MHz at 4.5V - Industrial range

Note: 1. See “Data Retention” on page 8 for details.

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1. Pin Configurations

(

)

Figure 1-1. Pinout

AVCC

D-

D+

1 2 3 4 5 6 7 8 9

(INT.6/AIN0) PE6

UVcc

UGnd UC ap

VBus

(SS/PCINT0) PB0

(PCINT1/SCLK) PB1

GND

VCC

PE2 (HWB)

PC7 (ICP3/CLK0/OC4A)

PC6 (OC3A/OC4A)

PB6 (PCINT6/OC1B/OC4B/AD

PB5 (PCINT5/OC1A/OC4B/AD

PB4 (PCINT4/ADC11)

PD7 (T0/OC4D/ADC10)

P F 4 (AD C 4/TCK

P F 5 (AD C 5/TMS)P F 6 (AD C 6/TDO)P F 7 (AD C 7/TD 38

GND

ARE F

P F 0 (AD C 0)

P F 1 (AD C 1)

INDEX CORNER

AT mega 32U4 AT mega 16U4

44-pin QFN/TQFP

PD6 (T1/OC4D/ADC9)

PD4 (ICP1/ADC8)

AVCC

(X C K1/CT S) P D5

24 23

GND

(PDI/PCINT2/MOSI) PB2

PDO/PCINT3/MISO) PB3

10 11

PCI NT7/OC0 A/OC1C/RT S) PB7

RESET

VCC

GND

XT AL2

XT AL1

(OC 0B /S C L/INT0) P D0

(S D A/INT1) P D1

(R X D1/INT 2) P D2

(T X D 1 /INT3) PD3

2. Overview

The ATmega16U4/ATmega32U4 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

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2.1 Block Diagram

PROGRAM COUNTER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

GENERAL PURPOSE

REGISTERS

INSTRUCTION

TIMERS/

COUNTERS

INSTRUCTION

DECODER

DATADIR.

REG. PORTB

DATADIR.

REG. PORTE

DATADIR.

REG. PORTD

DATAREGISTER

PORTB

DATAREGISTER

PORTE

DATAREGISTER

PORTD

INTERRUPT

UNIT

EEPROM

SPI

STATUS

SRAM

USART1

ALU

PORTB DRIVERS

PORTE DRIVERS

PORTF DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB7 - PB0

PE6

PF7 - PF4

RESET

VCC

GND

XTAL1

XTAL2

CONTROL

LINES

PC7

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

8-BIT DA TA BUS

USB 2.0

TIMING AND

CONTROL

OSCILLATOR

CALIB. OSC

DATADIR.

REG. PORTC

DATAREGISTER

PORTC

ON-CHIP DEBUG

JTAG TAP

PROGRAMMING

LOGIC

BOUNDARY-

SCAN

DATADIR.

REG. PORTF

DATAREGISTER

PORTF

POR - BOD

RESET

PD7 - PD0

TWO-WIRE SERIAL

INTERFACE

PLL

HIGH SPEED

TIMER/PWM

PE2

PC6PF1

PF0

ON-CHIP

USB PAD 3V

REGULATOR

UVcc

UCap

1uF

ANALOG

COMPARATOR

VBUS

ADC

AGND

AREF

AVCC

TEMPERATURE

SENSOR

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The device provides the following features: 16/32K bytes of In-System Programmable Flash with Read-WhileWrite capabilities, 512Bytes/1K bytes EEPROM, 1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS outputs and LVTTL inputs), 32 general purpose working registers, four flexible Timer/Counters with compare modes and PWM, one more high-speed Timer/Counter with compare modes and PLL adjustable source, one USART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12-channels 10-bit ADC with optional differential input stage with programmable gain, an on-chip calibrated temperature sensor, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable

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power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using the Atmel Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the device is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega16U4/ATmega32U4 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

high-density nonvolatile memory technology. The On-chip ISP

2.2.2 GND

Ground.

2.2.3 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the device as listed on page 74.

2.2.4 Port C (PC7,PC6)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running.

Only bits 6 and 7 are present on the product pinout.

Port C also serves the functions of special features of the device as listed on page 77.

2.2.5 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running.

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Port D also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 78.

2.2.6 Port E (PE6,PE2)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tristated when a reset condition becomes active, even if the clock is not running.

Only bits 2 and 6 are present on the product pinout.

Port E also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 81.

2.2.7 Port F (PF7..PF4, PF1,PF0)

Port F serves as analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter channels are not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Bits 2 and 3 are not present on the product pinout.

Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

2.2.8 D-

USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D- connector pin with a serial 22 resistor.

2.2.9 D+

USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+ connector pin with a serial 22 resistor.

2.2.10 UGND

USB Pads Ground.

2.2.11 UVCC

USB Pads Internal Regulator Input supply voltage.

2.2.12 UCAP

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF).

2.2.13 VBUS

USB VBUS monitor input.

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2.2.14 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-2 on page 53. Shorter pulses are not guaranteed to generate a reset.

2.2.15 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.16 XTAL2

Output from the inverting Oscillator amplifier.

2.2.17 AVCC

AVCC is the supply voltage pin (input) for all the A/D Converter channels. If the ADC is not used, it should be externally connected to V

2.2.18 AREF

This is the analog reference pin (input) for the A/D Converter.

. If the ADC is used, it should be connected to VCC through a low-pass filter.

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3. About

3.1 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min. and Max. values will be available after the device is characterized.

3.2 Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

3.3 Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details.

These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

3.4 Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1PPM over 20 years at 85°C or 100 years at 25°C.

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4. AVR CPU Core

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

4.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

4.2 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two

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operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Zregister, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega16U4/ATmega32U4 has Extended I/O space from 0x60 0x0FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

4.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See “Instruction Set Summary” on page 418 for a detailed description.

4.4 Stat u s Regi ster

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

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The AVR Status Register – SREG – is defined as:

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

I T H S V N Z C SREG

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See “Instruction Set Summary” on page 418 for detailed information.

• Bit 4 – S: Sign Bit, S = N

 V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See “Instruction Set Summary” on page 418 for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s arithmetic complements. See “Instruction Set

Summary” on page 418 for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See “Instruction Set

Summary” on page 418 for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See “Instruction Set Summary” on

page 418 for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See “Instruction Set Summary” on

page 418 for detailed information.

4.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

 One 8-bit output operand and one 8-bit result input  Two 8-bit output operands and one 8-bit result input

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 Two 8-bit output operands and one 16-bit result input  One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

70Addr.

R0 0x00 R1 0x01 R2 0x02 …

General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11

R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.

4.5.1 The X-register , Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3.

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Figure 4-3. The X-, Y-, and Z-registers

X-register 7 0 7 0

Y-register 7 0 7 0

Z-register 7 0 7 0

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (See “Instruction Set Summary” on page 418 for detailed information).

4.6 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by three when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by three when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

15 XH XL 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

R31 (0x1F) R30 (0x1E)

Bit 1514131211109 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 1 0 0 0 0 0

11111111

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4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Bit 7654321 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value0000000 0

RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 RAMPZ

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 4-4. Note that LPM is not affected by the RAMPZ setting.

Figure 4-4. The Z-pointer used by ELPM and SPM

Bit (Individually) 7 0 7 0 7 0

Bit (Z-pointer) 23 16 15 8 7 0

RAMPZ ZH ZL

The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero.

4.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk used.

Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture

and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

, directly generated from the selected clock source for the chip. No internal clock division is

CPU

Figure 4-5. The Parallel Instruction Fetches and Instruction Executions

Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using

two register operands is executed, and the result is stored back to the destination register.

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Figure 4-6. Single Cycle ALU Operation

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

4.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section

“Memory Programming” on page 353 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 63. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 63 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 353.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

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When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE out SREG, r16 ;

restore SREG value (I-bit)

C Code Example

char cSREG; cSREG = SREG; /*

store SREG value */

/* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending ; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */

4.8.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

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A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set.

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5. AVR Memories

This section describes the different memories in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the device features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

Table 5-1. Memory Mapping

Memory Mnemonic ATmega32U4 ATmega16U4

Flash

32 Registers

I/O Registers

Ext I/O Registers

Internal SRAM

Size

Start Address

End Address

Size

Start Address

End Address

Size

Start Address

End Address

Size

Start Address

End Address

Size

Start Address

Flash size 32KB 16KB

0x0000

(1)

(2)

0x3FFF

0x1FFF

Flash end

0x7FFF

0x3FFF

- 32 bytes 32 bytes

- 0x0000 0x0000

- 0x001F 0x001F

- 64 bytes 64 bytes

- 0x0020 0x0020

- 0x005F 0x005F

- 160 bytes 160 bytes

- 0x0060 0x0060

- 0x00FF 0x00FF

ISRAM size 2.5KB 1.25KB

ISRAM start 0x100 0x100

(1)

(2)

End Address

External Memory

Size

ISRAM end 0x0AFF 0x05FF

Not Present.

E2 size 1KB 512 bytes

EEPROM

End Address

E2 end 0x03FF 0x01FF

Notes: 1. Byte address.

2. Word (16-bit) address.

5.1 In-System Reprogrammable Flash Program Memory

The device contains 16/32K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 100,000 write/erase cycles. The device Program Counter (PC) is 16 bits wide, thus addressing the 32K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Memory Programming” on

page 353. “Memory Programming” on page 353 contains a detailed description on Flash data serial

downloading using the SPI pins or the JTAG interface.

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Constant tables can be allocated within the entire program memory address space (see the LPM – Load

0x00000

Program Memory

Application Flash Section

Boot Flash Section

0x7FFF (32KBytes)

Program Memory instruction description and ELPM - Extended Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 14.

Figure 5-1. Program Memory Map

5.2 SRAM Data Memory

Figure 5-2 on page 20 shows how the device SRAM Memory is organized.

The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The first 2,816 Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory and the next 2,560 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Zregister.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, and the 1.25/2.5Kbytes of internal data SRAM in the device are all accessible through all these addressing modes. The Register File is described in “General

Purpose Register File” on page 11.

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Figure 5-2. Data Memory Map

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

ata

emory

5.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

Figure 5-3. On-chip Data SRAM Access Cycles

160

32 R

I/O

egister

Ext I/O

Reg.

$0000 - $001 $0020 - $005 $0060 - $00

ISRAM start : $0100

nterna

SRA

ISRAM end : $05FF / $0AFF

FFFF

cycles as described in Figure 5-3.

CPU

5.3 EEPROM Data Memory

The device contains 512Bytes/1K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see page 367, page 371, and page 356 respectively.

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5.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 5-3 on page 23. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 25. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

5.3.2 The EEPROM Address Register – EEARH and EEARL

is likely to rise or fall slowly

Bit 1514131211 10 9 8

Read/WriteRRRRR/WR/WR/WR/W

Initial Value0000X XXX

––––EEAR11EEAR10EEAR9EEAR8EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543 2 10

R/W R/W R/W R/W R/W R/W R/W R/W

XXXXX X XX

• Bits 15..12 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bits 11..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512Bytes/1K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and E2_END. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

5.3.3 The EEPROM Data Register – EEDR

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

MSB LSB EEDR

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

5.3.4 The EEPROM Control Register – EECR

Bit 765432 10

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

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• Bits 7..6 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in the table below. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 5-2. EEPROM Mode Bits

EEPM1 EEPM0 Programming Time Operation

0 0 3.4ms Erase and Write in one operation (Atomic Operation)

0 1 1.8ms Erase Only

1 0 1.8ms Write Only

1 1 – Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Memory Programming” on page 353 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the

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EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. The following table lists the typical programming time for EEPROM access from the CPU.

Table 5-3. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write (from CPU)

26,368 3.3ms

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

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Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18 out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE ret

(1)

C Code Example

(1)

void EEPROM_write(unsigned int uiAddress, unsigned char ucData) {

/* Wait for completion of previous write */ while(EECR & (1<<EEPE))

; /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

Note: 1. See “Code Examples” on page 8.

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

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Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18 out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress) {

}

(1)

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

/* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

(1)

;

Note: 1. See “Code Examples” on page 8.

5.3.5 Preventing EEPROM Corruption

During periods of low V

the EEPROM data can be corrupted because the supply voltage is too low for the

CC,

CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

5.4 I/O Memory

The I/O space definition of the device is shown in “Register Summary” on page 414.

reset Protection circuit can be used. If a reset occurs while a write

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All I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

5.4.1 General Purpose I/O Registers

The device contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

5.4.2 General Purpose I/O Register 2 – GPIOR2

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

MSB LSB GPIOR2

5.4.3 General Purpose I/O Register 1 – GPIOR1

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

MSB LSB GPIOR1

5.4.4 General Purpose I/O Register 0 – GPIOR0

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

MSB LSB GPIOR0

ATmega16U4/32U4 [DATASHEET]

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6. System Clock and Clock Options

General I/O

Modules

CPU Core

RAM

clk

I/O

AVR Clock

Control Unit

clk

CPU

Flash and EEPROM

clk

FLASH

Source clock

Watchdog TimerReset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Crystal

Oscillator

External Clock

ADC

clk

ADC

System Clock

Prescaler

Watchdog

Oscillator

USB

clk

USB (48MHz)

PLL Clock

Prescaler

PLL

clk

PllPresc

High Speed

Timer

clk

PLL

PLL Postcaler

(1) (2)

clk

TMR

PLL Input

Multiplexer

Clock Switch

6.1 Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be

active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 43. The clock systems are detailed below.

Figure 6-1. Clock Distribution

6.1.1 CPU Clock – clk

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

6.1.2 I/O Clock – clk

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also, TWI address recognition is handled in all sleep modes.

6.1.3 Flash Clock – clk

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

I/O

CPU

FLASH

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6.1.4 ADC Clock – clk

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

ADC

6.1.5 PLL Prescaler Clock – clk

PllPresc

The PLL requires a 8MHz input. A prescaler allows user to use either a 8MHz or a 16MHz source (from a crystal or an external source), using a divider (by 2) if necessary. The output of the prescaler goes into the PLL Input multiplexer, that allows the user to select either the prescaler output of the System Clock Multiplexer, or the Internal 8MHz Calibrated Oscillator.

6.1.6 PLL Output Clock – clk

Pll

When enabled, the PLL outputs one frequency among numerous choices between 32MHz and 96MHz. The output frequency is determined by the PLL clock register. The frequency is independent of the power supply voltage. The PLL Output is connected to a postscaler that allows user to generate two different frequencies (clk

USB

and clk

) from the common PLL signal, each on them resulting of a selected division ratio (/1, /1.5, /2).

TMR

6.1.7 High-Speed Timer Clock– clk

When enabled, the PLL outputs one frequency among numerous choices between 32MHz and 96MHz, that goes into the PLL Postcaler. The High Speed Timer frequency input is generated from the PLL Postcaler, that proposes /1, /1.5 and /2 ratios. That can be determined from the PLL clock register. The High Speed Timer maximum frequency input depends on the power supply voltage and reaches its maximum of 64MHz at 5V.

6.1.8 USB Clock – clk

USB

The USB hardware module needs for a 48MHz clock. This clock is generated from the on-chip PLL. The output of the PLL passes through the PLL Postcaler where the frequency can be either divided by 2 or directly connected to the clk

USB

signal.

TMR

6.2 Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 6-1. Device Clocking Options Select

Device Clocking Option CKSEL[3:0] (or EXCKSEL[3:0])

Low Power Crystal Oscillator 1111 - 1 0 0 0

Reserved 0111 - 011 0

Low Frequency Crystal Oscillator 0101 - 0100

Reserved 0011

Calibrated Internal RC Oscillator 0010

External Clock 0000

Reserved 0001

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

(1)

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6.2.1 Default Clock Source ATmega16U4 and ATmega32U4

The device is shipped with Low Power Crystal Oscillator (8.0 - 16MHz) enabled and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock with an 8MHz crystal. See Table 28-5 on page 355 for an overview of the default Clock Selection Fuse setting.

6.2.2 Default Clock Source ATmega16U4RC and ATmega32U4RC

The device is shipped with Calibrated Internal RC oscillator (8.0MHz) enabled and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. See Table 28-5 on page 355 for an overview of the default Clock Selection Fuse setting.

6.2.3 Clock Startup Sequence

Any clock source needs a sufficient V

to start oscillating and a minimum number of oscillating cycles before it

can be considered stable.

To ensure sufficient V

, the device issues an internal reset with a time-out delay (t

) after the device reset is

TOUT

released by all other reset sources. “On-chip Debug System” on page 46 describes the start conditions for the internal reset. The delay (t

) is timed from the Watchdog Oscillator and the number of cycles in the delay is

TOUT

set by the SUTx and CKSELx fuse bits. The selectable delays are shown in the following table. The frequency of the Watchdog Oscillator is voltage dependent as shown in this table.

Table 6-2. Number of Watchdog Oscillator Cycles

Typ Time-o ut (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

0ms 0ms 0

4.1ms 4.3ms 512

65ms 69ms 8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V monitor the actual voltage and it will be required to select a delay longer than the V

. The delay will not

rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient V

before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without

utilizing a Brown-Out Detection circuit is not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from six cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Power-down mode, V

is assumed to be at a

sufficient level and only the start-up time is included.

6.3 Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-2. Either a quartz crystal or a ceramic resonator may be used.

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors

XTAL2

XTAL1

GND

depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in the below table. For ceramic resonators, the capacitor values given by the manufacturer should be used.

Figure 6-2. Crystal Oscillator Connections

The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL[3..1] as shown in this table.

Table 6-3. Low Power Crystal Oscillator Operating Modes

Frequency Range

0.4 - 0.9 100

(1)

[MHz] CKSEL3..1 Recommended Range for Capacitors C1 and C2 [pF]

(2)

–

0.9 - 3.0 101 12 - 22

3.0 - 8.0 11 0 12 - 22

8.0 - 16.0 111 12 - 22

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

2. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in this table.

Table 6-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection

Oscillator Source / Power Conditions

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Start-up Time from

Power-down and

Power-save

258CK 14CK + 4.1ms

258CK 14CK + 65ms

1K CK 14CK

1K CK 14CK + 4.1ms

1K CK 14CK + 65ms

Additional Delay from

Reset

= 5.0V) CKSEL0 SUT1..0

(1)

(2)

0 00

0 01

0 10

0 11

1 00

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Table 6-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection

Oscillator Source / Power Conditions

Crystal Oscillator, BOD enabled

Crystal Oscillator, fast rising power

Crystal Oscillator, slowly rising power

Start-up Time from

Power-down and

Power-save

16K CK 14CK 1 01

16K CK 14CK + 4.1ms 1 10

16K CK 14CK + 65ms 1 11

Additional Delay from

Reset

= 5.0V) CKSEL0 SUT1..0

Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and

only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

Table 6-5. Start-up times for the internal calibrated RC Oscillator clock selection

Power Conditions

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

BOD enabled 6CK 14CK 00

Fast rising power 6CK 14CK + 4.1ms 01

Slowly rising power 6CK 14CK + 65ms

(1)

Reserved 11

Note: 1.

The device is shipped with this option selected.

6.4 Low Frequency Crystal Oscillator

The device can utilize a 32.768kHz watch crystal as clock source by a dedicated Low Frequency Crystal Oscillator. The crystal should be connected as shown in Figure 6-2 on page 30. When this Oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in the table below.

Table 6-6. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power Conditions

BOD enabled 1K CK 14CK

Fast rising power 1K CK 14CK + 4.1ms

Slowly rising power 1K CK 14CK + 65ms

BOD enabled 32K CK 14CK 1 00

Fast rising power 32K CK 14CK + 4.1ms 1 01

Power-save

Reserved 0 11

Additional Delay from

Reset

(VCC = 5.0V) CKSEL0 SUT1..0

(1)

0 00

0 01

0 10

Slowly rising power 32K CK 14CK + 65ms 1 10

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Table 6-6. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power Conditions

Note: 1. These options should only be used if frequency stability at start-up is not important for the application.

Power-save

Reserved 1 11

6.5 Calibrated Internal RC Oscillator

The calibrated internal RC Oscillator by default provides a 8.0MHz clock. This frequency is nominal value at 3V and 25C. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on

page 35 for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as

shown in the table below. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 3V and 25C, this calibration gives a frequency of 8MHz ±1%. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1MHz within ±1% accuracy, by changing the OSCCAL register. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 356

Table 6-7. Internal Calibrated RC Oscillator Operating Modes

Frequency Range [MHz] CKSEL[3:0]

7.3 - 8.1 0010

Additional Delay from

Reset

= 5.0V) CKSEL0 SUT1..0

Notes: 1. The device is shipped with this option selected.

2. If 8 MHz frequency exceeds the specification of the device (depends on V programmed in order to divide the internal frequency by 8.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in the table.

Table 6-8. Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

Power Conditions

BOD enabled 6CK 14CK 00

Fast rising power 6CK 14CK + 4.1ms 01

Slowly rising power 6CK 14CK + 65ms 10

down and Power-save

Reserved 11

6.5.1 Oscillator Calibration Register – OSCCAL

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Device Specific Calibration Value

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Additional Delay from

Reset (V

= 5.0V) SUT1..0

), the CKDIV8 Fuse can be

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. The factory-calibrated value is automatically written to this register during chip reset, giving an oscillator frequency of 8.0MHz at 25°C. The application software can write this

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

EXTERNAL

CLOCK

SIGNAL

XTAL2

XTAL1

GND

With typical process at 25°C the code should be 127 for 8MHz. Input value of 0x00 gives the lowest frequency, and 0xFF the highest.

The temperature sensitivity is quite linear but as said previously depends on the process. To determine its slope, the frequency must be measured at two temperatures. The temperature sensor of the device allows such an operation, that is detailed on “Sensor Calibration” on page 304. It is then possible to calibrate the oscillator frequency in function of the temperature measured.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

6.5.2 Oscillator Control Register – RCCTRL

Bit 76543210

Read/WriteRRRRRRRR/W Initial Value00000000

- - - - - - - RCFREQ RCCTRL

Bits 7..1 – Reserved

Do not set these bits. Bits should be read as ‘0’.

Bit 0– RCFREQ: RC Oscillator Frequency Select

When this bit is cleared (default value), the RC Oscillator output frequency is set to 8MHz. When the bit is set, the RC output frequency is 1MHz. Note that the OSCCAL value has the same effect on both 8MHz and 1MHz output modes (~0.4% / step).

6.6 External Clock

The device can utilize a external clock source as shown in Figure 6-3. To run the device on an external clock, the CKSEL Fuses must be programmed as shown in Table 6-1 on page 28.

Figure 6-3. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in the table below.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Table 6-9. Start-up Times for the External Clock Selection

USB

CPU Clock

Ext ernal Oscillator

RC oscillator

Ext RC Ext

non-Idle Idle

(Suspend)

non-Idle

resume

Resume from Host

watchdog wake-up from power-down

Power Conditions

BOD enabled 6CK 14CK 00

Fast rising power 6CK 14CK + 4.1ms 01

Slowly rising power 6CK 14CK + 65ms 10

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page 35 for details.

6.7 Clock Switch

The device includes a Clock Switch controller, that allows user to switch from one clock source to another one by software, in order to control application power and execution time with more accuracy.

6.7.1 Example of use

The modification may be needed when the device enters in USB Suspend mode. It then switches from External Clock to Calibrated RC Oscillator in order to reduce consumption and wake-up delay. In such a configuration, the External Clock is disabled. The firmware can then use the watchdog timer to be woken-up from power-down in order to check if there is an event on the application. If an event occurs on the application or if the USB controller signals a non-idle state on the USB line (Resume for example), the firmware switches the Clock Multiplexer from the Calibrated RC Oscillator to the External Clock. in order to restart USB operation.

Start-up Time from Power-

down and Power-save

Reserved 11

Additional Delay from

Reset (V

= 5.0V) SUT1..0

Figure 6-4. Example of Clock Switching with Wake-up from USB Host

This feature can only be used to switch between Calibrated 8MHz RC Oscillator, External Clock and Low Power Crystal Oscillator. The Low Frequency Crystal Oscillator must not be used with this feature.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Figure 6-5. Example of Clock Switching with Wake-up from Device

USB

CPU Clock

Ext ernal Oscillator

RC oscillator

Ext RC Ext

non-Idle Idle

(Suspend)

non-Idle

upstream-resume

2 Upstream Resume from device

w atchdog wake-up from power-down

6.8 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO.

If the System Clock Prescaler is used, it is the divided system clock that is output.

6.8.1 System Clock Prescaler

The AVR USB has a system clock prescaler, and the system clock can be divided by setting the “CLKPR –

Clock Prescaler Register” on page 39. This feature can be used to decrease the system clock frequency and

the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk clk

CPU

, and clk

are divided by a factor as shown in Table 6-10 on page 40.

FLASH

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.

I/O

, clk

ADC

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

6.9 PLL

8 MHz

RC OSCILLATOR

XTAL1 XTAL2

XTAL

OSCILLATOR

PLL

PLLE

Lock

Detector

clk

TMR

To System Clock Prescaler

clk

8MHz

PLL clock Prescaler

PINDIV

PDIV3..0

clk

USB

/1.5

PLLTM1:0

PLLUSB

PINMUX

CKSEL3:0

PLOCK

The PLL is used to generate internal high frequency (up to 96MHz) clock for USB interface and/or High Speed Timer module, the PLL input is supplied from an external low-frequency clock (the crystal oscillator or external clock input pin from XTAL1).

6.9.1 Internal PLL

The internal PLL in the device generates a clock frequency between 32MHz and 96MHz from nominally 8MHz input.

The source of the 8MHz PLL input clock is the output of the internal PLL clock prescaler that generates the 8MHz from the clock source multiplexer output (See “PLL Control and Status Register – PLLCSR” on page 40. for PLL interface). The PLL prescaler allows a direct connection (8MHz oscillator) or a divide-by-2 stage for a 16MHz clock input.

The PLL output signal enters the PLL Postcaler stage before being distributed to the USB and High Speed Timer modules. Each of these modules can choose an independent division ratio.

Figure 6-6. PLL Clocking System

6.10 Clock switch Algorithm

6.10.1 Switch from External Clock to RC Clock

if (Usb_suspend_detected()) // if (UDINT.SUSPI == 1) {

Usb_ack_suspend(); // UDINT.SUSPI = 0; Usb_freeze_clock(); // USBCON.FRZCLK = 1; Disable_pll(); // PLLCSR.PLLE = 0; Enable_RC_clock(); // CLKSEL0.RCE = 1; while (!RC_clock_ready()); // while (CLKSTA.RCON != 1); Select_RC_clock(); // CLKSEL0.CLKS = 0; Disable_external_clock(); // CLKSEL0.EXTE = 0;

}

6.10.2 Switch from RC Clock to External Clock

if (Usb_wake_up_detected()) // if (UDINT.WAKEUPI == 1) {

Usb_ack_wake_up(); // UDINT.WAKEUPI = 0; Enable_external_clock(); // CKSEL0.EXTE = 1; while (!External_clock_ready()); // while (CLKSTA.EXTON != 1);

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Select_external_clock(); // CLKSEL0.CLKS = 1; Enable_pll(); // PLLCSR.PLLE = 1; Disable_RC_clock(); // CLKSEL0.RCE = 0; while (!Pll_ready()); // while (PLLCSR.PLOCK != 1); Usb_unfreeze_clock(); // USBCON.FRZCLK = 0;

}

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

6.11 Register Description

6.11.1 CLKSEL0 – Clock Selection Register 0

Bit 7 6 5 4 3210

Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 See Bit Description

RCSUT1 RCSUT0 EXSUT1 EXSUT0 RCE EXTE - CLKS CLKSEL0

• Bit 7-6 – RCSUT[1:0]: SUT for RC oscillator

These two bits are the SUT value for the RC Oscillator. If the RC oscillator is selected by fuse bits, the SUT fuse are copied into these bits. A firmware change will not have any effect because this additional start-up time is only used after a reset and not after a clock switch.

• Bit 5-4 – EXSUT[1:0]: SUT for External Clock/ Low Power Crystal Oscillator

These two bits are the SUT value for the External Clock / Low Power Crystal Oscillator. If the External Clock / Low Power Crystal Oscillator is selected by fuse bits, the SUT fuses are copied into these bits. The firmware can modify these bits by writing a new value. This value will be used at the next start of the External Clock / Low Power Crystal Oscillator.

• Bit 3 – RCE: Enable RC Oscillator

The RCE bit must be written to logic one to enable the RC Oscillator. The RCE bit must be written to logic zero to disable the RC Oscillator.

• Bit 2 – EXTE: Enable External Clock / Low Power Crystal Oscillator

The OSCE bit must be written to logic one to enable External Clock / Low Power Crystal Oscillator. The OSCE bit must be written to logic zero to disable the External Clock / Low Power Crystal Oscillator.

• Bit 0 – CLKS: Clock Selector

The CLKS bit must be written to logic one to select the External Clock / Low Power Crystal Oscillator as CPU clock. The CLKS bit must be written to logic zero to select the RC Oscillator as CPU clock. After a reset, the CLKS bit is set by hardware if the External Clock / Low Power Crystal Oscillator is selected by the fuse bits configuration. The firmware has to check if the clock is correctly started before selected it.

6.11.2 CLKSEL1 – Clock Selection Register 1

Bit7 6 5 4 3210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value0 0 1 0 0000

RCCKSEL3 RCCKSEL2 RCCKSEL1 RCCKSEL0 EXCKSEL3 EXCKSEL2 EXCKSEL1 EXCKSEL0 CLKSEL1

• Bit 7-4 – RCCKSEL[3:0]: CKSEL for RC oscillator

Clock configuration for the RC Oscillator. After a reset, this part of the register is loaded with the 0010b value that corresponds to the RC oscillator. Modifying this value by firmware before switching to RC oscillator is prohibited because the RC clock will not start.

• Bit 3-0 – EXCKSEL[3:0]: CKSEL for External Clock / Low Power Crystal Oscillator

Clock configuration for the External Clock / Low Power Crystal Oscillator. After a reset, if the External Clock / Low Power Crystal Oscillator is selected by fuse bits, this part of the register is loaded with the fuse configuration. Firmware can modify it to change the start-up time after the clock switch.

See Table 6-1 on page 28 for EXCKSEL[3:0] configuration. Only Low Power Crystal Oscillator, Calibrated Internal RC Oscillator, and External Clock modes are allowed.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

6.11.3 CLKSTA – Clock Status Register

Bit 7 6543210

Read/WriteRRRRRRRR Initial Value 0 0 0 0 0

- - - - - - RCON EXTON CLKSTA

• Bit 7-2 - Reserved bits

These bits are reserved and will always read as zero.

• Bit 1 – RCON: RC Oscillator On

This bit is set by hardware to one if the RC Oscillator is running. This bit is set by hardware to zero if the RC Oscillator is stopped.

• Bit 0 – EXTON: External Clock / Low Power Crystal Oscillator On

This bit is set by hardware to one if the External Clock / Low Power Crystal Oscillator is running. This bit is set by hardware to zero if the External Clock / Low Power Crystal Oscillator is stopped.

6.11.4 CLKPR – Clock Prescaler Register

Bit 7 6543210

Read/WriteR/WRRRR/WR/WR/WR/W Initial Value0 000See Bit Description

CLKPCE–––CLKPS3CLKPS2CLKPS1CLKPS0CLKPR

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 3..0 – CLKPS[3..0]: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in the table below.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Table 6-10. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0 0 0 0 1

0 0 0 1 2

0 0 1 0 4

0 0 1 1 8

0 1 0 0 16

0 1 0 1 32

0 1 1 0 64

0 1 1 1 128

1 0 0 0 256

1 0 0 1 Reserved

1 0 1 0 Reserved

1 0 1 1 Reserved

1 1 0 0 Reserved

1 1 0 1 Reserved

1 1 1 0 Reserved

1 1 1 1 Reserved

6.11.5 PLL Control and Status Register – PLLCSR

Bit 76543210 $29 ($29) Read/Write R R R R/W R R R/W R Initial Value 0 0 0 0 0 0 0 0

PINDIV PLLE PLOCK PLLCSR

• Bit 7:5 – Res: Reserved Bits

These bits are reserved and always read as zero.

• Bit 4 – PINDIV PLL Input Prescaler (1:1, 1:2)

These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the PLL from either a 8 or 16MHz input.

When using a 8MHz clock source, this bit must be set to 0 before enabling PLL (1:1).

When using a 16MHz clock source, this bit must be set to 1 before enabling PLL (1:2).

• Bit 3:2 – Res: Reserved Bits

These bits are reserved and always read as zero.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

• Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started. Note that the Calibrated 8MHz Internal RC oscillator is automatically enabled when the PLLE bit is set and with PINMUX (see PLLFRQ register) is set. The PLL must be disabled before entering Power down mode in order to stop Internal RC Oscillator and avoid extra-consumption.

• Bit 0 – PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock. After the PLL is enabled, it takes about several ms for the PLL to lock. To clear PLOCK, clear PLLE.

6.11.6 PLL Frequency Control Register – PLLFRQ

Bit 76543210 $32 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000100

PINMUX PLLUSB PLLTM1 PLLTM0 PDIV3 PDIV2 PDIV1 PDIV0 PLLFRQ

• Bit 7– PINMUX: PLL Input Multiplexer

This bit selects the clock input of the PLL:

 PINMUX = 0: the PLL input is connected to the PLL Prescaler, that has the Primary System Clock

as source

 PINMUX = 1: the PLL input is directly connected to the Internal Calibrated 8MHz RC Oscillator. This

mode allows to work in USB Low Speed mode with no crystal or using a crystal with a value different of 8/16MHz.

• Bit 6– PLLUSB: PLL Postcaler for USB Peripheral

This bit select the division factor between the PLL output frequency and the USB module input frequency:

 PLLUSB = 0: no division, direct connection (if PLL Output = 48MHz)  PLLUSB = 1: PLL Output frequency is divided by two and sent to USB module

(if PLL Output = 96MHz)

• Bit 5:4 – PLLTM1:0: PLL Postcaler for High Speed Timer

These bits codes for the division factor between the PLL Output Frequency and the High Speed Timer input frequency.

Note that the division factor 1.5 will introduce some jitter in the clock, but keeping the error null since the average duty cycle is 50%. See Figures 6-7 for more details.

PLLTM1 PLLTM0 PLL Postcaler Factor for High-Speed Timer

0 0 0 (Disconnected)

0 1 1

1 0 1.5

1 1 2

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Figure 6-7. PLL Postcaler operation with division factor = 1.5

Fi x ---

2 3

• Bit 3:0 – PDIV3:0 PLL Lock Frequency

These bits configure the PLL internal VCO clock reference according to the required output frequency value.

PDIV3 PDIV2 PDIV1 PDIV0 PLL Output Frequency

0 0 0 0 Not allowed

0 0 0 1 Not allowed

0 0 1 0 Not allowed

0 0 1 1 40MHz

0 1 0 0 48MHz

0 1 0 1 56MHz

0 1 1 0 Not allowed

0 1 1 1 72MHz

1 0 0 0 80MHz

1 0 0 1 88MHz

1 0 1 0 96MHz

1 0 1 1 Not allowed

1 1 0 0 Not allowed

1 1 0 1 Not allowed

1 1 1 0 Not allowed

1 1 1 1 Not allowed

The optimal PLL configuration at 5V is: PLL output frequency = 96MHz, divided by 1.5 to generate the 64MHz High Speed Timer clock, and divided by 2 to generate the 48MHz USB clock.

ATmega16U4/32U4 [DATASHEET]

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7. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be activated by the SLEEP instruction.

See Table 7-1 on page 44 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

Figure 6-1 on page 27 presents the different clock systems in the ATmega16U4/ATmega32U4, and their

distribution. The figure is helpful in selecting an appropriate sleep mode.

7.1 Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

CPU

and clk

FLASH

7.2 ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire Serial Interface address match and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run (including clkUSB).

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire serial interface interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT6, an external interrupt on INT3:0 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.

7.3 Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, 2wire Serial Interface address match, an external level interrupt on INT6, an external interrupt on INT3:0, a pin change interrupt or an asynchronous USB interrupt sources (VBUSTI, WAKEUPI), can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.

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Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 88 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in “Clock

Sources” on page 28.

7.4 Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. For compatibility reasons with AT90USB64/128 this mode is still present but since Timer 2 Asynchronous operation is not present here, this mode is identical to Power-down.

7.5 Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.

7.6 Extended Standby Mode

When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. For compatibility reasons with AT90USB64/128 this mode is still present but since Timer 2 Asynchronous operation is not present here, this mode is identical to Standbymode.

Table 7-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes

Active Clock

Oscillators Wake-up Sources

ADC

Main Clock

Source

Enabled

INT6, INT3:0 and

Pin Change

TWI Address

Match

SPM/

EEPROM Ready

ADC

WDT Interrupt

Other I/O

USB Synchronous

Interrupts

Sleep Mode

Domains

CPU

clk

FLASH

clk

clkIOclk

Idle X X X X X X X X X X X

ADCNRM X X X

Power-down X

Power-save X

Standby

Extended Standby

(1)

X X

(2)

X X X X X X

(2)

X X X

(2)

X X X

(2)

X X X

(2)

X X X

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. For INT6, only level interrupt.

3. Asynchronous USB interrupts are VBUSTI and WAKEUPI.

USB Asynchronous

(3)

Interrupts

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7.7 Power Reduction Register

The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped.

7.8 Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

7.8.1 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog to Digital Converter - ADC” on page 297 for details on ADC operation.

7.8.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 293 for details on how to configure the Analog Comparator.

7.8.3 Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to

“Brown-out Detection” on page 52 for details on how to configure the Brown-out Detector.

7.8.4 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on page 54 for details on the start-up time.

7.8.5 Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Interrupts” on page 63 for details on how to configure the Watchdog Timer.

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7.8.6 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk clock (clk

) are stopped, the input buffers of the device will be disabled. This ensures that no power is

ADC

consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 71 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to

/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by

writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to “Digital Input Disable Register 1 –

DIDR1” on page 296 and “Digital Input Disable Register 1 – DIDR1” on page 296 for details.

7.8.7 On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode, the main clock source is enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.

There are three alternative ways to disable the OCD system:

 Disable the OCDEN Fuse  Disable the JTAGEN Fuse  Write one to the JTD bit in MCUCR

/2, the input buffer will use excessive power.

) and the ADC

I/O

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7.9 Register Description

7.9.1 Sleep Mode Control Register – SMCR

The Sleep Mode Control Register contains control bits for power management.

Bit 76543210

Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

––––SM2SM1SM0SESMCR

• Bits 3, 2, 1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the six available sleep modes as shown in Table 7-2.

T able 7-2. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

0 0 0 Idle

0 0 1 ADC Noise Reduction

0 1 0 Power-down

0 1 1 Power-save

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Standby

1 1 1 Extended Standby

Note: 1. Standby modes are only recommended for use with external crystals or resonators.

(1)

• Bit 0 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.

7.9.2 Power Reduction Register 0 - PRR0

Bit 7654321 0

Read/Write R/W R R/W R R/W R/W R R/W Initial Val-ue0000000 0

PRTWI – PRTIM0 – PRTIM1 PRSPI – PRADC PRR0

• Bit 7 - PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.

• Bit 6 - Res: Reserved bit

This bits is reserved and will always read as zero.

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• Bit 5 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.

• Bit 4 - Res: Reserved bit

This bit is reserved and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.

• Bit 1 - Res: Reserved bit

These bits are reserved and will always read as zero.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

7.9.3 Power Reduction Register 1 - PRR1

Bit 7 654 3 210

Read/WriteR/W R R R R/W R R R/W

Initial Val-ue0 000 0 000

PRUSB – – PRTIM4 PRTIM3 – – PRUSART1 PRR 1

• Bit 7 - PRUSB: Power Reduction USB

Writing a logic one to this bit shuts down the USB by stopping the clock to the module. When waking up the USB again, the USB should be re initialized to ensure proper operation.

• Bit 6..5 - Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 4- PRTIM4: Power Reduction Timer/Counter4

Writing a logic one to this bit shuts down the Timer/Counter4 module. When the Timer/Counter4 is enabled, operation will continue like before the shutdown.

• Bit 3 - PRTIM3: Power Reduction Timer/Counter3

Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is enabled, operation will continue like before the shutdown.

• Bit 2..1 - Res: Reserved bits

These bits are reserved and will always read as zero.

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• Bit 0 - PRUSART1: Power Reduction USART1

Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be re initialized to ensure proper operation.

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8. System Control and Reset

8.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure

8-1 on page 51 shows the reset logic. Table 29-3 on page 386 defines the electrical parameters of the reset

circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 28.

8.2 Reset Sources

The ATmega16U4/ATmega32U4 has five sources of reset:

 Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold

POT

 External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the

minimum pulse length.

 Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is

enabled.

 Brown-out Reset. The MCU is reset when the supply voltage V

) and the Brown-out Detector is enabled.

BOT

 JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan

chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 325 for details.

 USB End of Reset. The MCU is reset (excluding the USB controller that remains enabled and attached)

on the detection of a USB End of Reset condition on the bus, if this feature is enabled by the user.

is below the Brown-out Reset threshold

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Figure 8-1. Reset Logic

MCU Status

Brown-out

Reset Circuit

BODLEVEL [2..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

WDRF

BORF

EXTRF

PORF

DATA BUS

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

JTRF

JTAG Reset

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

USB Reset

Detection

USBRF

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

POR

8.3 Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in

Table 8-1 on page 53. The POR is activated whenever V

is below the detection level. The POR circuit can be

used to trigger the start-up Reset, as well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V rise. The RESET signal is activated again, without any delay, when V

Figure 8-2. MCU Start-up, RESET Tied to V

decreases below the detection level.

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Figure 8-3. MCU Start-up, RESET Extended Externally

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

POR

8.4 External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 29-3 on page 386) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V positive edge, the delay counter starts the MCU after the Time-out period – t

Figure 8-4. External Reset During Operation

TOUT –

has expired.

– on its

RST

8.5 Brown-out Detection

ATmega16U4/ATmega32U4 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level

during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V

= V

BOT+

BOT

+ V

HYST

/2 and V

BOT-

= V

BOT

- V

HYST

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/2.

Table 8-1. BODLEVEL Fuse Coding

RESET

TIME-OUT

INTERNAL

RESET

BOT-

BOT+

TOUT

BODLEVEL 2..0 Fuses Min. V

BOT

Typ. V

BOT

Max. V

BOT

Units

111 BOD Disabled

110 1.8 2.0 2.2

101 2.0 2.2 2.4

100 2.2 2.4 2.6

011 2.4 2.6 2.8

010 3.2 3.4 3.6

001 3.3 3.5 3.7

000 4.0 4.3 4.5

Table 8-2. BOD characteristics

Symbol Parameter Min. Typ. Max. Units

HYST

BOD

When the BOD is enabled, and VCC decreases to a value below the trigger level (V Brown-out Reset is immediately activated. When V delay counter starts the MCU after the Time-out period t

The BOD circuit will only detect a drop in V

Brown-out Detector Hysteresis 50 mV

Min Pulse Width on Brown-out Reset ns

in Figure 8-5), the

BOT-

increases above the trigger level (V

has expired.

TOUT

if the voltage stays below the trigger level for longer than t

BOT+

given in Table 29-3 on page 386.

in Figure 8-5), the

BOD

Figure 8-5. Brown-out Reset During Operation

8.6 Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t Timer, see “Watchdog Timer” on page 55.

. For details on operation of the Watchdog

TOUT

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Figure 8-6. Watchdog Reset During Operation

USB Traffic

(USB Lines)

USBRSTMIN

End of Reset

8.7 USB Reset

When the USB controller is enabled and configured with the USB Reset CPU feature enabled and if a valid USB Reset signalling is detected on the bus, the CPU core is reset but the USB controller remains enabled and attached. This feature may be used to enhance device reliability.

Figure 8-7. USB Reset During Operation

8.8 Internal Voltage Reference

ATmega16U4/ATmega32U4 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC.

8.8.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 8-3 on page 55. To save power, the reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power

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consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

Table 8-3. Internal Voltage Referen ce Characteristics

Symbol Parameter Condition Min. Typ. Max. Units

Bandgap reference voltage

Bandgap reference start-up time

Bandgap reference current consumption

8.9 Watchdog Timer

ATmega16U4/ATmega32U4 has an Enhanced Watchdog Timer (WDT). The main features are:

•

Clocked from separate On-chip Oscillator

• Three Operating modes

– Interrupt – System Reset – Interrupt and System Reset

• Selectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

Figure 8-8. Watchdog Timer

128kHz

OSCILLATOR

VCC=2.7

=25°C

VCC=2.7

=25°C

VCC=2.7

=25°C

1.0 1.1 1.2 V

40 70 µs

10 µA

OSC/2K

OSC/4K

OSC/8K

OSC/16K

OSC/32K

OSC/64K

OSC/128K

OSC/256K

OSC/512K

OSC/1024K

WDP0

WATCHDOG RESET

WDE

WDIF

WDIE

WDP1 WDP2 WDP3

MCU RESET

INTERRUPT

The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.

In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in

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case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows:

1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with

the WDCE bit cleared. This must be done in one operation.

The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.

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Assembly Code Example

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in r16, MCUSR andi r16, (0xff & (0<<WDRF)) out MCUSR, r16

; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent

unintentional time-out

in r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) out WDTCSR, r16

; Turn off WDT

ldi r16, (0<<WDE) out WDTCSR, r16

; Turn on global interrupt

sei ret

(1)

C Code Example

(1)

void WDT_off(void) {

__disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent

unintentional time-out */

WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt();

}

Note: 1. The example code assumes that the part specific header file is included.

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is not in use.

The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.

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Assembly Code Example

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

in r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) out WDTCSR, r16

; -- Got four cycles to set the new values from

here -

; Set new prescaler(time-out) value = 64K cycles

(~0.5 s)

ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0) out WDTCSR, r16

; -- Finished setting new values, used 2 cycles ; Turn on global interrupt

sei ret

(1)

C Code Example

(1)

void WDT_Prescaler_Change(void) {

__disable_interrupt(); __watchdog_reset(); /* Start timed sequence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles

(~0.5 s) */

WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt();

}

Note: 1. The example code assumes that the part specific header file is included.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period.

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8.10 Register Description

8.11 MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit 76543210

Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description

– – USBRF JTRF WDRF BORF EXTRF P ORF MCUSR

• Bit 7..6 - Reserved

These bits are reserved and should be read as 0. Do not set these bits.

• Bit 5– USBRF: USB Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 4 – JTRF: JTAG Reset Flag

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

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8.11.1 Watchdog Timer Control Register - WDTCSR

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0

WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safetyfunction of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.

Table 8-4. Watchdog Timer Configuration

WDTON WDE WDIE Mode Action on Time-out

0 0 0 Stopped None

0 0 1 Interrupt Mode Interrupt

0 1 0 System Reset Mode Reset

0 1 1

1 x x System Reset Mode Reset

Interrupt and System Reset Mode

Interrupt, then go to System Reset Mode

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.

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• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in the following table.

Table 8-5. Watchdog Timer Prescale Select

Number of WDT Oscillator

WDP3 WDP2 WDP1 WDP0

0 0 0 0 2K (2048) cycles 16ms

0 0 0 1 4K (4096) cycles 32ms

0 0 1 0 8K (8192) cycles 64ms

0 0 1 1 16K (16384) cycles 0.125s

0 1 0 0 32K (32768) cycles 0.25s

0 1 0 1 64K (65536) cycles 0.5s

0 1 1 0 128K (131072) cycles 1.0s

0 1 1 1 256K (262144) cycles 2.0s

1 0 0 0 512K (524288) cycles 4.0s

1 0 0 1 1024K (1048576) cycles 8.0s

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

Cycles

Reserved

T ypical Time-out at

VCC = 5.0V

1 1 1 0

1 1 1 1

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9. Interrupts

This chapter describes the specifics of the interrupt handling as performed in ATmega16U4/ATmega32U4. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 15.

9.1 Interrupt Vectors in ATmega16U4/ATmega32U4

T able 9-1. Reset and Interrupt Vectors(cont’d)

Vector

No.

1 $0000

2 $0002 INT0 External Interrupt Request 0

3 $0004 INT1 External Interrupt Request 1

4 $0006 INT2 External Interrupt Request 2

5 $0008 INT3 External Interrupt Request 3

6 $000A Reserved Reserved

7 $000C Reserved Reserved

8 $000E INT6 External Interrupt Request 6

9 $0010 Reserved Reserved

10 $0012 PCINT0 Pin Change Interrupt Request 0

11 $0014 USB General USB General Interrupt request

12 $0016 USB Endpoint USB Endpoint Interrupt request

13 $0018 WDT Watchdog Time-out Interrupt

14 $001A Reserved Reserved

Program

Address

(2)

Source Interrupt Definition

(1)

RESET

External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset

15 $001C Reserved Reserved

16 $001E Reserved Reserved

17 $0020 TIMER1 CAPT Timer/Counter1 Capture Event

18 $0022 TIMER1 COMPA Timer/Counter1 Compare Match A

19 $0024 TIMER1 COMPB Timer/Counter1 Compare Match B

20 $0026 TIMER1 COMPC Timer/Counter1 Compare Match C

21 $0028 TIMER1 OVF Timer/Counter1 Overflow

22 $002A TIMER0 COMPA Timer/Counter0 Compare Match A

23 $002C TIMER0 COMPB Timer/Counter0 Compare match B

24 $002E TIMER0 OVF Timer/Counter0 Overflow

25 $0030 SPI (STC) SPI Serial Transfer Complete

26 $0032 USART1 RX USART1 Rx Complete

27 $0034 USART1 UDRE USART1 Data Register Empty

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T able 9-1. Reset and Interrupt Vectors(cont’d)

Vector

No.

28 $0036 USART1TX USART1 Tx Complete

29 $0038 ANALOG COMP Analog Comparator

30 $003A ADC ADC Conversion Complete

31 $003C EE READY EEPROM Ready

32 $003E TIMER3 CAPT Timer/Counter3 Capture Event

33 $0040 TIMER3 COMPA Timer/Counter3 Compare Match A

34 $0042 TIMER3 COMPB Timer/Counter3 Compare Match B

35 $0044 TIMER3 COMPC Timer/Counter3 Compare Match C

36 $0046 TIMER3 OVF Timer/Counter3 Overflow

37 $0048 TWI 2-wire Serial Interface

38 $004A SPM READY Store Program Memory Ready

39 $004C TIMER4 COMPA Timer/Counter4 Compare Match A

40 $004E TIMER4 COMPB Timer/Counter4 Compare Match B

41 $0050 TIMER4 COMPD Timer/Counter4 Compare Match D

Program

Address

(2)

Source Interrupt Definition

42 $0052 TIMER4 OVF Timer/Counter4 Overflow

43 $0054 TIMER4 FPF Timer/Counter4 Fault Protection Interrupt

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see

“Memory Programming” on page 353.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

The table shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.

Table 9-2. Reset and Interrupt Vectors Placement

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x0000 0x0002

1 1 0x0000 Boot Reset Address + 0x0002

0 0 Boot Reset Address 0x0002

0 1 Boot Reset Address Boot Reset Address + 0x0002

Note: 1. The Boot Reset Address is shown in Table 27-4 on page 340. For the BOOTRST Fuse “1” means

unprogrammed while “0” means programmed.

9.1.1 Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

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9.2 Register Description

9.2.1 MCU Control Register – MCUCR

Bit 76543210

Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

JTD – – PUD – – IVSEL IVCE MCUCR

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Memory Programming” on page 353 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are

disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Memory Programming” on page 353 for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.

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Assembly Code Example

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE) out MCUCR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL) out MCUCR, r16 ret

C Code Example

void Move_interrupts(void) {

/* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL);

}

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10. I/O-Ports

10.1 Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V

Characteristics” on page 383 for a complete list of parameters.

Figure 10-1. I/O Pin Equivalent Schematic

and Ground as indicated in Figure 10-1. Refer to “Electrical

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “” on page 83.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 67. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 72. Refer to the individual module sections for a full description of the alternate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.

10.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn.

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Figure 10-2. General Digital I/O

(1)

PUD

DDxn

CLR

RESET

WDx

RDx

Pxn

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

are common to all ports.

10.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “” on page 83, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

SLEEP

SYNCHRONIZER

PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk

: I/O CLOCK

I/O

DLQ

RPx

clk

DATA BUS

WRx

I/O

WPx

, SLEEP, and PUD

I/O

PORTxn

CLR

RESET

RRx

PINxn

WDx: WRITE DDRx RDx: READ DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN

WPx: WRITE PINx REGISTER

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

10.2.2 Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

10.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull-up enabled state is fully acceptable, as a high-impedance environment will not notice

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the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value

Table 10-1. Port Pin Configurations

DDxn PORTxn

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled low

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

(in MCUCR) I/O Pull-up Comment

10.2.4 Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2 on page 68, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3 on page 69 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t respectively.

PUD

pd,max

and t

pd,min

Figure 10-3. Synchronization when Reading an Externally Applied Pin Value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd max. and tpd min., a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

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When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd

through the synchronizer is one system clock period.

Figure 10-4. Synchronization when Reading a Software Assigned Pin Value

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a

nop instruction is included to be able to read back the value recently assigned to

some of the pins.

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Assembly Code Example

...

; Define pull-ups and set outputs high ; Define directions for port pins

ldi

r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi

r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16 out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB ...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ __no_operation(); /* Read port pins */ i = PINB;

...

(1)

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins

0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

10.2.5 Digital Input Enable and Sleep Modes

As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the Schmidt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to V

/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 72.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

10.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to

not enabled, the

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reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode, and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to V since this may cause excessive currents if the pin is accidentally configured as an output.

10.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5 shows how the port pin control signals from the simplified Figure 10-2 on page 68 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

or GND is not recommended,

Figure 10-5. Alternate Port Functions

Pxn

(1)

PUOExn

PUOVxn

DDOExn

DDOVxn

PVOExn

PVOVxn

DIEOExn

DIEOVxn

SLEEP

SYNCHRONIZER

SET

DLQ

CLR

PINxn

CLR

PORTxn

RESET

CLR

RESET

PUD

DDxn

CLR

WDx

RDx

RRx

RPx

clk

PTOExn

WRx

WPx

I/O

DATA BUS

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

PUD: PULLUP DISABLE WDx: WRITE DDRx RDx: READ DDRx RRx: READ PORTx REGISTER WRx: WRITE PORTx RPx: READ PORTx PIN WPx: WRITE PINx clk

: I/O CLOCK

I/O

DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

I/O

, SLEEP, and PUD

are common to all ports. All other signals are unique for each pin.

The table summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 on page

72 are not shown in the succeeding tables. The overriding signals are generated internally in the modules

having the alternate function.

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Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

Pull-up Override Enable

Pull-up Override Val ue

Data Direction Override Enable

Data Direction Override Value

Port Value Override Enable

Port Value Override Value

Port Toggle Override Enable

Digital Input Enable Override Enable

If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.

If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.

If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.

If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode).

Digital Input

DIEOV

DI Digital Input

AIO

Enable Override Val ue

Analog Input/Output

If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.

This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bidirectionally.

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

10.3.1 Alternate Functions of Port B

The Port B pins with alternate functions are shown below.

T able 10-3. Port B Pins Alternate Functions

Port Pin Alternate Functions

OC0A/OC1C/PCINT7/RTS (Output Compare and PWM Output A for Timer/Counter0,

PB7

PB6

PB5

PB4 PCINT4/ADC11 (Pin Change Interrupt 4 or Analog to Digital Converter channel 11)

Output Compare and PWM Output C for Timer/Counter1 or Pin Change Interrupt 7 or UART flow control RTS

OC1B/PCINT6/OC.4B/ADC13 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change Interrupt 6 or Timer 4 Output Compare B / PWM output or Analog to Digital Converter channel 13)

OC1A/PCINT5/OC.4B/ADC12 (Output Compare and PWM Output A for Timer/Counter1 or Pin Change Interrupt 5 or Timer 4 Complementary Output Compare B / PWM output or Analog to Digital Converter channel 12)

signal)

PB3

PB2

PB1 SCK/PCINT1 (SPI Bus Serial Clock or Pin Change Interrupt 1)

PB0 SS/PCINT0 (SPI Slave Select input or Pin Change Interrupt 0)

PDO/MISO/PCINT3 (Programming Data Output or SPI Bus Master Input/Slave Output or Pin Change Interrupt 3)

PDI/MOSI/PCINT2 (Programming Data Input or SPI Bus Master Output/Slave Input or Pin Change Interrupt 2)

The alternate pin configuration is as follows:

• OC0A/OC1C/PCINT7/RTS, Bit 7

OC0A, Output Compare Match A output: The PB7 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB7 set “one”) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set “one”) to serve this function. The OC1C pin is also the output pin for the PWM mode timer function.

PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source.

: RTS flow control signal used by enhanced UART.

RTS

• OC1B/PCINT6/OC.4B/ADC 12, Bit 6

OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set “one”) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

PCINT6, Pin Change Interrupt source 6: The PB7 pin can serve as an external interrupt source.

OC.4B: Timer 4 Output Compare B. This pin can be used to generate a high-speed PWM signal from Timer 4 module. The pin has to be configured as an output (DDB6 set “one”) to serve this function.

ADC13: Analog to Digital Converter, channel 13.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

• OC1A/PCINT5/OC.4B/ADC12, Bit 5

OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

PCINT5, Pin Change Interrupt source 5: The PB7 pin can serve as an external interrupt source.

: Timer 4 Output Compare B. This pin can be used to generate a high-speed PWM signal from Timer 4

OC.4B module, complementary to OC.4B (PB5) signal. The pin has to be configured as an output (DDB5 set (one)) to serve this function.

ADC12: Analog to Digital Converter, channel 12.

• PCINT4/ADC11, Bit 4

PCINT4, Pin Change Interrupt source 4: The PB7 pin can serve as an external interrupt source.

ADC11, Analog to Digital Converter channel 11.

• PDO/MISO/PCINT3 – Port B, Bit 3

PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega16U4/ATmega32U4.

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.

PCINT3, Pin Change Interrupt source 3: The PB7 pin can serve as an external interrupt source.

• PDI/MOSI/PCINT2 – Port B, Bit 2

PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega16U4/ATmega32U4.

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.

PCINT2, Pin Change Interrupt source 2: The PB7 pin can serve as an external interrupt source.

• SCK/PCINT1 – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.

PCINT1, Pin Change Interrupt source 1: The PB7 pin can serve as an external interrupt source.

•SS/PCINT0 – Port B, Bit 0

SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.

Table 10-4 and Table 10-5 on page 76 relate the alternate functions of Port B to the overriding signals shown in Figure 10-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is

divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

PCINT0, Pin Change Interrupt source 0: The PB7 pin can serve as an external interrupt source

Table 10-4. Overriding Signals for Alternate Functions in PB7..PB4

Signal Name

PB7/PCINT7/OC0A/O C1C/RTS

PB6/PCINT6/OC1B/ OC.4B/ADC13

PB5/PCINT5/OC1A/

/ADC12

OC.4B

PB4/PCINT4/ADC 11

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE OC0/OC1C ENABLE OC1B ENABLE OC1A ENABLE 0

PVOV OC0/OC1C OC1B OC1A 0

DIEOE PCINT7 • PCIE0 PCINT6 • PCIE0 PCINT5 • PCIE0 PCINT4 • PCIE0

DIEOV 1 1 1 1

DI PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT PCINT4 INPUT

AIO – – – –

Table 10-5. Overriding Signals for Alternate Functions in PB3..PB0

Signal Name

PB3/PD0/PCINT3/ MISO

PB2/PDI/PCINT2/ MOSI

PB1/PCINT1/ SCK

PB0/PCINT0/ SS

PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD

DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

DDOV 0 0 0 0

PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0

PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT 0

DIEOE PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT1 • PCIE0 PCINT0 • PCIE0

DIEOV 1 1 1 1

SPI MSTR INPUT

PCINT3 INPUT

SPI SLAVE INPUT

PCINT2 INPUT

SCK INPUT

PCINT1 INPUT

SPI SS

PCINT0 INPUT

AIO – – – –

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

10.3.2 Alternate Functions of Port C

The Port C pins with alternate functions are shown below.

T able 10-6. Port C Pins Alternate Functions

Port Pin Alternate Function

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

ICP3/CLKO/OC4A(Input Capture Timer 3 or CLK0 (Divided System Clock) or Output Compare and direct PWM output A for Timer 4)

OC.3A/OC4A (Output Compare and PWM output A for Timer/Counter3 or Output Compare and complementary PWM output A

Not present on pin-out.

for Timer 4)

• ICP3/CLKO/OC.4A – Port C, Bit 7

ICP3: If Timer 3 is correctly configured, this pin can serve as Input Capture feature.

CLKO: When the corresponding fuse is enabled, this pin outputs the internal microcontroller working frequency. If the clock prescaler is used, this will affect this output frequency.

OC.4A: Timer 4 Output Compare A. This pin can be used to generate a high-speed PWM signal from Timer 4 module. The pin has to be configured as an output (DDC7 set “one”) to serve this function.

• OC.3A/OC.4A – Port C, Bit 6

OC.3A: Timer 3 Output Compare A. This pin can be used to generate a PWM signal from Timer 3 module.

: Timer 4 Output Compare A. This pin can be used to generate a high-speed PWM signal from Timer 4

OC.4A module, complementary to OC.4A (PC7) signal. The pin has to be configured as an output (DDC6 set “one”) to serve this function.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

The following table shows the alternate functions of Port C to the overriding signals shown in Figure 10-5 on

page 72.

Table 10-7. Overriding Signals for Alternate Functions in PC7..PC6

Signal Name PC7/ICP3/CLKO/OC.4A PC6/OC.3A/OC.4A

PUOE SRE • (XMM<1) SRE • (XMM<2)|OC3A enable

PUOV 0 0

DDOE SRE • (XMM<1) SRE • (XMM<2)

DDOV 1 1

PVOE SRE • (XMM<1) SRE • (XMM<2)

PVOV A15 if (SRE.XMM<2) then A14 else OC3A

DIEOE 0 0

DIEOV 0 0

DI ICP3 input –

AIO – –

10.3.3 Alternate Functions of Port D

The Port D pins with alternate functions are shown below.

T able 10-8. Port D Pins Alternate Functions

Port Pin Alternate Function

PD7

PD6

PD5 XCK1/CTS (USART1 External Clock Input/Output or UART flow control CTS signal)

PD4

PD3 INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin)

PD2 INT2/RXD1 (External Interrupt2 Input or USART1 Receive Pin)

PD1 INT1/SDA (External Interrupt1 Input or TWI Serial DAta)

PD0

T0/OC.4D/ADC10 (Timer/Counter0 Clock Input or Timer 4 Output Compare D / PWM output or Analog to Digital Converter channel 10)

T1/OC.4D/ADC9 (Timer/Counter1 Clock Input or Timer 4 Output Complementary Compare D / PWM output or Analog to Digital Converter channel 9)

ICP1/ADC8 (Timer/Counter1 Input Capture Trigger or Analog to Digital Converter channel 8)

INT0/SCL/OC0B (External Interrupt0 Input or TWI Serial CLock or Output Compare for Timer/Counter0)

The alternate pin configuration is as follows:

• T0/OC.4D/ADC10 – Port D, Bit 7

T0, Timer/Counter0 counter source.

OC.4D: Timer 4 Output Compare D. This pin can be used to generate a high-speed PWM signal from Timer 4 module. The pin has to be configured as an output (DDD7 set “one”) to serve this function.

ADC10: Analog to Digital Converter, Channel 10.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

• T1/OC.4D/ADC9 – Port D, Bit 6

T1, Timer/Counter1 counter source.

OC.4D

: Timer 4 Output Compare D. This pin can be used to generate a high-speed PWM signal from Timer 4 module, complementary to OC.4D (PD7) signal. The pin has to be configured as an output (DDD6 set “one”) to serve this function.

ADC9: Analog to Digital Converter, Channel 9

• XCK1/CTS – Port D, Bit 5

XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1 operates in Synchronous mode.

CTS

: Clear-To-Send flow control signal used by enhanced UART module.

• ICP1/ADC8 – Port D, Bit 4

ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin for Timer/Counter1.

ADC8: Analog to Digital Converter, Channel 8

•INT3/TXD1 – Port D, Bit 3

INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU.

TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3.

•INT2/RXD1 – Port D, Bit 2

INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU.

RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

•INT1/SDA – Port D, Bit 1

INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the MCU.

SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.

•INT0/SCL/OC0B – Port D, Bit 0

INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the MCU.

SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.

OC.0B: Timer 0 Output Compare B. This pin can be used to generate a PWM signal from the Timer 0 module.

The two following tables relate the alternate functions of Port D to the overriding signals shown in Figure 10-5 on

page 72.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Table 10-9. Overriding Signals for Alternate Functions PD7..PD4

Signal Name PD7/T0/OC4D/ADC10 PD6/T1/OC4D/ADC9 PD5/XCK1/CTS PD4/ICP1/ADC8

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 0 XCK1 OUTPUT ENABLE 0

DDOV 0 0 1 0

PVOE 0 0 XCK1 OUTPUT ENABLE 0

PVOV 0 0 XCK1 OUTPUT 0

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI T0 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT

AIO – – – –

Table 10-10. Overriding Signals for Alternate Functions in PD3..PD0

(1)

Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1 PD1/INT1/SDA PD0/INT0/SCL/OC0B

PUOE TXEN1 RXEN1 TWEN TWEN

PUOV 0 PORTD2 • PUD PORTD1 • PUD PORTD0 • PUD

DDOE TXEN1 RXEN1 TWEN TWEN

DDOV 1 0 SDA_OUT SCL_OUT

PVOE TXEN1 0 TWEN ENABLE TWEN | OC0B ENABLE

PVOV TXD1 0 0 OC0B

DIEOE INT3 ENABLE INT2 ENABLE INT1 ENABLE INT0 ENABLE

DIEOV 1 1 1 1

DI INT3 INPUT INT2 INPUT/RXD1 INT1 INPUT INT0 INPUT

AIO – – SDA INPUT SCL INPUT

Note: 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not

shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

10.3.4 Alternate Functions of Port E

The Port E pins with alternate functions are shown below.

Table 10-11. Port E Pins Alternate Functions

Port Pin Alternate Function

PE7 Not present on pin-out.

PE6 INT6/AIN0 (External Interrupt 6 Input or Analog Comparator Positive Input)

PE5

Not present on pin-out.PE4

PE3

PE2 HWB (Hardware bootloader activation)

PE1

PE0

Not present on pin-out.

• INT6/AIN0 – Port E, Bit 6

INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source.

AIN0 – Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator.

•HWB – Port E, Bit 2

HWB allows to execute the bootloader section after reset when tied to ground during external reset pulse. The HWB mode of this pin is active only when the HWBE fuse is enable. During normal operation (excluded Reset), this pin acts as a general purpose I/O.

Table 10-12. Overriding Signals for Alternate Functions PE6, PE2

Signal Name PE6/INT6/AIN0 PE2/HWB

PUOE 0 0

PUOV 0 0

DDOE 0 0

DDOV 0 1

PVOE 0 0

PVOV 0 0

DIEOE INT6 ENABLE 0

DIEOV 1 0

DI INT6 INPUT HWB

AIO AIN0 INPUT -

10.3.5 Alternate Functions of Port F

The Port F has an alternate function as analog input for the ADC as shown in Table 10-13 on page 82. If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs.

Table 10-13. Port F Pins Alternate Functions

Port Pin Alternate Function

PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)

PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)

PF5 ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)

PF4 ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)

PF3

PF2

PF1 ADC1 (ADC input channel 1)

PF0 ADC0 (ADC input channel 0)

Not present on pin-out

• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, Channel 7.

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TDO, ADC6 – Port F, Bit 6

ADC6, Analog to Digital Converter, Channel 6.

TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

The TDO pin is tri-stated unless TAP states that shift out data are entered.

• TMS, ADC5 – Port F, Bit 5

ADC5, Analog to Digital Converter, Channel 5.

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TCK, ADC4 – Port F, Bit 4

ADC4, Analog to Digital Converter, Channel 4.

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• ADC3 – ADC0 – Port F, Bit 1..0

Analog to Digital Converter, Channel 1.0

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

Table 10-14. Overriding Signals for Alternate Functions in PF7..PF4

Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK

PUOE JTAGEN JTAGEN JTAGEN JTAGEN

PUOV 1 0 1 1

DDOE JTAGEN JTAGEN JTAGEN JTAGEN

DDOV 0

SHIFT_IR + SHIFT_DR

0 0

PVOE 0 JTAGEN 0 0

PVOV 0 TDO 0 0

DIEOE JTAGEN JTAGEN JTAGEN JTAGEN

DIEOV 0 0 0 0

DI – – – –

AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5 INPUT TCK/ADC4 INPUT

Table 10-15. Overriding Signals for Alternate Functions in PF1..PF0

Signal Name PF1/ADC1 PF0/ADC0

PUOE 0 0

PUOV 0 0

DDOE 0 0

DDOV 0 0

PVOE 0 0

PVOV 0 0

DIEOE 0 0

DIEOV 0 0

DI – –

AIO ADC1 INPUT ADC0 INPUT

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

10.4 Register Description for I/O-Ports

10.4.1 MCU Control Register – MCUCR

Bit7654 3210

Read/WriteR/W R R R/W R R R/W R/W

Initial Val-ue0000 0000

JTD – –PUD– – IVSEL IVCE MCUCR

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 68 for more details about this feature.

10.4.2 Port B Data Register – PORTB

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

10.4.3 Port B Data Direction Register – DDRB

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

10.4.4 Port B Input Pins Address – PINB

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

10.4.5 Port C Data Register – PORTC

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTC7PORTC6------PORTC

10.4.6 Port C Data Direction Register – DDRC

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

DDC7 DDC6 - - ----DDRC

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

10.4.7 Port C Input Pins Address – PINC

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

PINC7PINC6------PINC

10.4.8 Port D Data Register – PORTD

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORT D

10.4.9 Port D Data Direction Register – DDRD

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

10.4.10 Port D Input Pins Address – PIND

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

10.4.11 Port E Data Register – PORTE

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

-PORTE6---PORTE2--PORTE

10.4.12 Port E Data Direction Register – DDRE

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

- DDE6 - - - DDE2 - - DDRE

10.4.13 Port E Input Pins Address – PINE

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

-PINE6---PINE2--PINE

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

10.4.14 Port F Data Register – PORTF

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTF7 PORTF6 PORTF5 PORTF4 - - PORTF1 PORTF0 PORTF

10.4.15 Port F Data Direction Register – DDRF

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

DDF7 DDF6 DDF5 DDF4 - - DDF1 DDF0 DDRF

10.4.16 Port F Input Pins Address – PINF

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

PINF7 PINF6 PINF5 PINF4 - - PINF1 PINF0 PINF

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

11. External Interrupts

The External Interrupts are triggered by the INT6, INT3:0 pin or any of the PCINT7..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT[6;3:0] or PCINT7..0 pins are configured as outputs. This feature provides a way of generating a software interrupt.

The Pin change interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK0 Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT7 ..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT6). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT6 requires the presence of an I/O clock, described in “System Clock and Clock Options” on page 27. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 27.

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1 1.1 Register Description

11.1.1 External Interrupt Control Register A – EICRA

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA

• Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits

The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in the below table. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in the below table will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled.

ISCn1 ISCn0 Description

0 0 The low level of INTn generates an interrupt request.

0 1 Any edge of INTn generates asynchronously an interrupt request.

1 0 The falling edge of INTn generates asynchronously an interrupt request.

1 1 The rising edge of INTn generates asynchronously an interrupt request.

Note: 1. n = 3, 2, 1, or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

Symbol Parameter Condition Min. Typ. Max. Units

INT

Minimum pulse width for asynchronous external interrupt

11.1.2 External Interrupt Control Register B – EICRB

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

--ISC61ISC60----EICRB

• Bit 7..6 – Reserved Bits

These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.

• Bits 5, 4 – ISC61, ISC60: External Interrupt 6 Sense Control Bits

The External Interrupt 6 is activated by the external pin INT6 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pin that activate the interrupt are defined in the following table. The value on the INT6 pin are sampled before detecting edges. If edge or toggle interrupt is

50 ns

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selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.

ISC61 ISC60 Description

0 0 The low level of INT6 generates an interrupt request.

0 1 Any logical change on INT6 generates an interrupt request

1 0 The falling edge between two samples of INT6 generates an interrupt request.

1 1 The rising edge between two samples of INT6 generates an interrupt request.

Note: 1. When changing the ISC61/ISC60 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the

EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

• Bit 3..0 – Reserved Bits

These bits are reserved bits and always read as zero.

11.1.3 External Interrupt Mask Register – EIMSK

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

- INT6 - - INT3 INT2 INT1 IINT0 EIMSK

• Bits 7..0 – INT6, INT3 – INT0: External Interrupt Request 6, 3 - 0 Enable

When an INT[6;3:0] bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EICRB – defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt.

11.1.4 External Interrupt Flag Register – EIFR

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

- INTF6 - - INTF3 INTF2 INTF1 IINTF0 EIFR

• Bits 7..0 – INTF6, INTF3 - INTF0: External Interrupt Flags 6, 3 - 0

When an edge or logic change on the INT[6;3:0] pin triggers an interrupt request, INTF7:0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT[6;3:0] in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT[6;3:0] are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See

“Digital Input Enable and Sleep Modes” on page 71 for more information.

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11.1.5 Pin Change Interrupt Control Register - PCICR

Bit 76543210

Read/WriteRRRRRRRR/W Initial Value 0 0 0 0 0 0 0 0

– – – – –PCIE0PCICR

• Bit 0 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

11.1.6 Pin Change Interrupt Flag Register – PCIFR

Bit 76543210

Read/WriteRRRRRRRR/W Initial Value 0 0 0 0 0 0 0 0

– – – – –PCIF0PCIFR

• Bit 0 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

11.1.7 Pin Change Mask Register 0 – PCMSK0

Bit76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Val-ue00000000

PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

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12. Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers

Tn_sync

(To Clock Select Logic)

Edge DetectorSynchronization

DQDQ

clk

I/O

Timer/Counter0, 1, and 3 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1, or 3.

12.1 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either f

CLK_I/O

12.2 Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to.

/8, f

CLK_I/O

/64, f

CLK_I/O

/256, or f

CLK_I/O

/1024.

CLK_I/O

12.3 External Clock Source

An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 12-1 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock

clk

). The latch is transparent in the high period of the internal system clock.

(

I/O

The edge detector generates one clk detects.

Figure 12-1. Tn/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it

Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f

/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an

clk_I/O

ExtClk

external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and

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capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than

PSR10

Clear

clk

I/O

Synchronization

TIMER/COUNTERn CLOCK SOURCE

clk

TIMER/COUNTERn CLOCK SOURCE

clk

CSn0 CSn1 CSn2

/2.5.

clk_I/O

An external clock source can not be prescaled.

Figure 12-2. Prescaler for Synchronous Timer/Counters

Note: T3 input is not available on the

ATmega16U4/ATmega32U4 products. “Tn” only refers to either T0 or T1

inputs.

12.4 Register Description

12.4.1 General Timer/Counter Control Register – GTCCR

Bit 7 6 5 4 3 2 1 0

Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously.

• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters

When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0, Timer/Counter1 and Timer/Counter3 share the same prescaler and a reset of this prescaler will affect all timers.

TSM – – – – – PSRASY PSRSYNC GTCCR

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13. 8-bit Timer/Counter0 with PWM

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are:

Two Independent Output Compare Units

•

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0 B)

13.1 Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 13-1. For the actual placement of I/O pins, refer to “Pinout” on page 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register

Description” on page 104.

Figure 13-1. 8-bit Timer/Counter Block Diagram

Count

Clear

Direction

Timer/Counter

TCNTn

Control Logic

TOP BOTTOM

TOVn

(Int.Req.)

clk

Clock Select

Edge

Detector

( From Prescaler )

OCnA

(Int.Req.)

Wavefor m

Generation

OCnA

13.1.1 Registers

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk

OCRnA

DATA BUS

OCRnB

TCCRnA TCCRnB

Fixed TOP

Val ue

OCnB

(Int.Req.)

Wavefor m

Generation

OCnB

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The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See “Output Compare Unit” on

page 96. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can

be used to generate an Output Compare interrupt request.

13.1.2 Definitions

Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defined in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.

The definitions in the table are also used extensively throughout the document.

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

The counter reaches the TOP when it becomes equal to the highest value in the count

TOP

sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation.

13.2 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and prescaler, see “Timer/Counter0, Timer/Counter1, and

Timer/Counter3 Prescalers” on page 92.

13.3 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 13-2 shows a block diagram of the counter and its surroundings.

Figure 13-2. Counter Unit Block Diagram

Signal description (internal signals):

count: Increment or decrement TCNT0 by 1. direction: Select between increment and decrement. clear: Clear TCNT0 (set all bits to zero). clk

Timer/Counter clock, referred to as clkT0 in the following.

Tn:

top: Signalize that TCNT0 has reached maximum value.

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bottom: Signalize that TCNT0 has reached minimum value (zero).

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnX1:0

bottom

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk

). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits

(CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk all counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 98.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.

13.4 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max. and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 98).

Figure 13-3 on page 96 shows a block diagram of the Output Compare unit.

is present or not. A CPU write overrides (has priority over)

Figure 13-3. Output Compare Unit, Block Diagram

The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the

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counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly.

13.4.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled).

13.4.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled.

13.4.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting.

The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately.

13.5 Compare Match Output Unit

The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 13-4 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”.

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Figure 13-4. Compare Match Output Unit, Schematic

PORT

DDR

OCnx

Waveform Generator

COMnx1

COMnx0

DATA BU S

FOCn

clk

I/O

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter

13.5.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 13-1 on

page 104. For fast PWM mode, refer to Table 13-2 on page 104, and for phase correct PWM refer to Table 133 on page 105.

A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.

13.6 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or noninverted PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See “Compare Match Output Unit” on page 97.).

For detailed timing information see “Timer/Counter Timing Diagrams” on page 102.

13.6.1 Normal Mode

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its

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maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the

TCNTn

OCn (Toggle)

OCnx Interrupt Flag Set

1 4

Period

2 3

(COMnx1:0 = 1)

OCnx

clk_I/O

2 N 1 OCRnx+

------------------------------------------------- -=

Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

13.6.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 13-5 on page 99. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.

Figure 13-5. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f

OC0

= f

/2 when OCR0A is set to zero (0x00). The waveform frequency is

clk_I/O

defined by the following equation:

N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

The

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00.

ATmega16U4/32U4 [DATASHEET]

Atmel-7766J-USB-ATmega16U4/32U4-Datasheet_04/2016

13.6.3 Fast PWM Mode

TCNTn

OCRnx Update and TOVn Interrupt Flag Set

Period

2 3

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

4 5 6 7

OCnxPWM

clk_I/O

N 256

----------------- -=

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure

13-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation.

The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.

Figure 13-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 13-2 on page 104). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

The

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100

Atmel ATmega16U4, ATmega32U4 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

2. Overview

2.1 Block Diagram

2.2 Pin Descriptions

2.2.1 VCC

2.2.2 GND

2.2.3 Port B (PB7..PB0)

2.2.4 Port C (PC7,PC6)

2.2.5 Port D (PD7..PD0)

2.2.6 Port E (PE6,PE2)

2.2.7 Port F (PF7..PF4, PF1,PF0)

2.2.8 D-

2.2.9 D+

2.2.10 UGND

2.2.11 UVCC

2.2.12 UCAP

2.2.13 VBUS

2.2.14 RESET

2.2.15 XTAL1

2.2.16 XTAL2

2.2.17 AVCC

2.2.18 AREF

3. About

3.1 Disclaimer

3.2 Resources

3.3 Code Examples

3.4 Data Retention

4. AVR CPU Core

4.1 Introduction

4.2 Architectural Overview

4.3 ALU – Arithmetic Logic Unit

4.4 Stat u s Regi ster

4.5 General Purpose Register File

4.5.1 The X-register , Y-register, and Z-register

4.6 Stack Pointer

4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ

4.7 Instruction Execution Timing

4.8 Reset and Interrupt Handling

4.8.1 Interrupt Response Time

5. AVR Memories

5.1 In-System Reprogrammable Flash Program Memory

5.2 SRAM Data Memory

5.2.1 Data Memory Access Times

5.3 EEPROM Data Memory

5.3.1 EEPROM Read/Write Access

5.3.2 The EEPROM Address Register – EEARH and EEARL

5.3.3 The EEPROM Data Register – EEDR

5.3.4 The EEPROM Control Register – EECR

5.3.5 Preventing EEPROM Corruption

5.4 I/O Memory

5.4.1 General Purpose I/O Registers

5.4.2 General Purpose I/O Register 2 – GPIOR2

5.4.3 General Purpose I/O Register 1 – GPIOR1

5.4.4 General Purpose I/O Register 0 – GPIOR0

6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

6.2 Clock Sources

6.2.1 Default Clock Source ATmega16U4 and ATmega32U4

6.2.2 Default Clock Source ATmega16U4RC and ATmega32U4RC

6.2.3 Clock Startup Sequence

6.3 Low Power Crystal Oscillator

6.4 Low Frequency Crystal Oscillator

6.5 Calibrated Internal RC Oscillator

6.5.1 Oscillator Calibration Register – OSCCAL

6.5.2 Oscillator Control Register – RCCTRL

6.6 External Clock

6.7 Clock Switch

6.7.1 Example of use

6.8 Clock Output Buffer

6.8.1 System Clock Prescaler

6.9 PLL

6.9.1 Internal PLL

6.10 Clock switch Algorithm

6.10.1 Switch from External Clock to RC Clock

6.10.2 Switch from RC Clock to External Clock