• AVR – High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
• Data and Nonvolatile Program Memory
– 8K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 512 Bytes of SRAM
– 512 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler
Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Programmable Serial UART
– Master/Slave SPI Serial Interface
• Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power-down Mode: <1 µA
– 2.7 - 6.0V for AT90S8515-4
– 4.0 - 6.0V for AT90S8515-8
• Speed Grades
– 0 - 4 MHz for AT90S8515-4
– 0 - 8 MHz for AT90S8515-8
®
RISC Architecture
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90S8515
Summary
e:
ava ila bl e on ou r we b site at www.atmel.com .
s a summary docum ent. A complete document is
Rev. 0841GS–09/01
1
Pin Configurations
2
AT90S8515
0841GS–09/01
AT90S8515
DescriptionThe AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S8515
achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to
optimize power consumption versus processing speed.
Block DiagramFigure 1. The AT90S8515 Block Diagram
0841GS–09/01
The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
3
Pin Descriptions
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The AT90S8515 provides the following features: 8K bytes of In-System Programmable
Flash, 512 bytes EEPROM, 512 bytes SRAM, 32 general-purpose I/O lines, 32 generalpurpose working registers, flexible timer/counters with compare modes, internal and
external interrupts, a programmable serial UART, programmable Watchdog Timer with
internal oscillator, an SPI serial port and two software-selectable power-saving modes.
The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and
interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip In-System Programmable Flash allows the program memory to be reprogrammed In-System through an SPI serial interface or by a conventional nonvolatile
memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S8515 is a powerful
microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications.
The AT90S8515 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators and evaluation kits.
VCCSupply voltage.
GNDGround.
Port A (PA7..PA0)Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,
they will source current if the internal pull-up resistors are activated. The Port A pins are
tri-stated when a reset condition becomes active, even if the clock is not active.
Port A serves as multiplexed address/data input/output when using external SRAM.
Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not active.
Port B also serves the functions of various special features of the AT90S8515 as listed
on page 66.
Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output
buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not active.
Port C also serves as address output when using external SRAM.
Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output
buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source
4
AT90S8515
0841GS–09/01
AT90S8515
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not active.
Port D also serves the functions of various special features of the AT90S8515 as listed
on page 73.
RESET
XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2Output from the inverting oscillator amplifier.
ICPICP is the input pin for the Timer/Counter1 Input Capture function.
OC1BOC1B is the output pin for the Timer/Counter1 Output CompareB function.
ALEALE is the Address Latch Enable used when the External Memory is enabled. The ALE
Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the
clock is not running. Shorter pulses are not guaranteed to generate a reset.
strobe is used to latch the low-order address (8 bits) into an address latch during the first
access cycle, and the AD0 - 7 pins are used for data during the second access cycle.
Notes:1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all
bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work
with registers $00 to $1F only.
6
AT90S8515
0841GS–09/01
AT90S8515
Instruction Set Summary
MnemonicOperandsDescriptionOperationFlags# Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADDRd, RrAdd Two RegistersRd ← Rd + RrZ,C,N,V,H1
ADCRd, RrAdd with Carry Two RegistersRd ← Rd + Rr + CZ,C,N,V,H1
ADIWRdl, KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2
SUBRd, RrSubtract Two RegistersRd ← Rd - RrZ,C,N,V,H1
SUBIRd, KSubtract Constant from RegisterRd ← Rd - KZ,C,N,V,H1
SBCRd, RrSubtract with Carry Two RegistersRd ← Rd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1
SBIWRdl, KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S2
ANDRd, RrLogical AND RegistersRd ←=Rd • RrZ,N,V1
ANDIRd, KLogical AND Register and ConstantRd ← Rd •=KZ,N,V1
ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1
ORIRd, KLogical OR Register and ConstantRd ←=Rd v KZ,N,V1
EORRd, RrExclusive OR RegistersRd ← Rd ⊕ RrZ,N,V1
COMRdOne’s ComplementRd ← $FF - RdZ,C,N,V1
NEGRdTwo’s ComplementRd ← $00 - RdZ,C,N,V,H1
SBRRd, KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1
CBRRd, KClear Bit(s) in RegisterRd ← Rd • ($FF - K)Z,N,V1
INCRdIncrementRd ← Rd + 1Z,N,V1
DECRdDecrementRd ← Rd - 1Z,N,V1
TSTRdTest for Zero or MinusRd ← Rd • Rd Z,N,V1
CLRRdClear RegisterRd ← Rd ⊕ RdZ,N,V1
SERRdSet RegisterRd ← $FFNone1
BRANCH INSTRUCTIONS
RJMPkRelative JumpPC=← PC + k + 1None2
IJMPIndirect Jump to (Z)PC ← ZNone2
RCALLkRelative Subroutine CallPC ← PC + k + 1None3
ICALLIndirect Call to (Z)PC ← ZNone3
RETSubroutine ReturnPC ← STACKNone4
RETIInterrupt ReturnPC ← STACKI4
CPSERd, RrCompare, Skip if Equalif (Rd = Rr) PC=← PC + 2 or 3None1/2/3
CPRd, RrCompareRd - RrZ,N,V,C,H1
CPCRd, RrCompare with CarryRd - Rr - CZ,N,V,C,H1
CPIRd, KCompare Register with ImmediateRd - KZ,N,V,C,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b) = 0) PC ← PC + 2 or 3 None1/2/3
SBRSRr, bSkip if Bit in Register is Setif (Rr(b) = 1) PC ← PC + 2 or 3None1/2/3
SBICP, bSkip if Bit in I/O Register Clearedif (P(b) = 0) PC ← PC + 2 or 3 None1/2/3
SBISP, bSkip if Bit in I/O Register is Setif (P(b) = 1) PC ← PC + 2 or 3None1/2/3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC ←=PC + k + 1None1/2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC ←=PC + k + 1None1/2
BREQkBranch if Equalif (Z = 1) then PC ← PC + k + 1None1/2
BRNEkBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2
BRCSkBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2
BRCCkBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2
BRSHkBranch if Same or Higherif (C = 0) then PC ← PC + k + 1None1/2
BRLOkBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2
BRMIkBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2
BRPLkBranch if Plusif (N = 0) then PC ← PC + k + 1None1/2
BRGEkBranch if Greater or Equal, Signedif (N ⊕ V = 0) then PC ← PC + k + 1None1/2
BRLTkBranch if Less Than Zero, Signedif (N ⊕ V = 1) then PC ← PC + k + 1None1/2
BRHSkBranch if Half-carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2
BRHCkBranch if Half-carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2
BRTSkBranch if T-flag Setif (T = 1) then PC ← PC + k + 1None1/2
BRTCkBranch if T-flag Clearedif (T = 0) then PC ← PC + k + 1None1/2
BRVSkBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2
BRVCkBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/2
BRIEkBranch if Interrupt Enabledif (I = 1) then PC ← PC + k + 1None1/2
BRIDkBranch if Interrupt Disabledif (I = 0) then PC ← PC + k + 1None1/2
0841GS–09/01
7
Instruction Set Summary (Continued)
MnemonicOperandsDescriptionOperationFlags# Clocks
DATA TRANSFER INSTRUCTIONS
MOVRd, RrMove between RegistersRd ← RrNone1
LDIRd, KLoad ImmediateRd ← KNone1
LDRd, XLoad IndirectRd ← (X)None2
LDRd, X+Load Indirect and Post-inc.Rd ← (X), X ← X + 1None2
LDRd, -XLoad Indirect and Pre-dec.X ← X - 1, Rd ← (X)None2
LDRd, YLoad IndirectRd ← (Y)None2
LDRd, Y+Load Indirect and Post-inc.Rd ← (Y), Y ← Y + 1None2
LDRd, -YLoad Indirect and Pre-dec.Y ← Y - 1, Rd ← (Y)None2
LDDRd, Y+qLoad Indirect with DisplacementRd ← (Y + q)None2
LDRd, ZLoad Indirect Rd ← (Z)None2
LDRd, Z+Load Indirect and Post-inc.Rd ← (Z), Z ← Z + 1None2
LDRd, -ZLoad Indirect and Pre-dec.Z ← Z - 1, Rd ← (Z)None2
LDDRd, Z+qLoad Indirect with DisplacementRd ← (Z + q)None2
LDSRd, kLoad Direct from SRAMRd ← (k)None2
STX, RrStore Indirect(X)=← RrNone2
STX+, RrStore Indirect and Post-inc.(X)=← Rr, X ← X + 1None2
ST-X, RrStore Indirect and Pre-dec.X ← X - 1, (X) ← RrNone2
STY, RrStore Indirect(Y) ← RrNone2
STY+, RrStore Indirect and Post-inc.(Y) ← Rr, Y ← Y + 1None2
ST-Y, RrStore Indirect and Pre-dec.Y ← Y - 1, (Y) ← RrNone2
STDY+q, RrStore Indirect with Displacement(Y + q) ← RrNone2
STZ, RrStore Indirect(Z) ← RrNone2
STZ+, RrStore Indirect and Post-inc.(Z) ← Rr, Z ← Z + 1None2
ST-Z, RrStore Indirect and Pre-dec.Z ← Z - 1, (Z) ← RrNone2
STDZ+q, RrStore Indirect with Displacement(Z + q) ← RrNone2
STSk, RrStore Direct to SRAM(k) ← RrNone2
LPMLoad Program MemoryR0 ← (Z)None3
INRd, PIn PortRd ← PNone1
OUTP, RrOut PortP ← RrNone1
PUSHRrPush Register on StackSTACK ← RrNone2
POPRdPop Register from StackRd ← STACKNone2
BIT AND BIT-TEST INSTRUCTIONS
SBIP, bSet Bit in I/O RegisterI/O(P,b) ← 1None2
CBIP, bClear Bit in I/O RegisterI/O(P,b) ← 0None2
LSLRdLogical Shift LeftRd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V1
LSRRdLogical Shift RightRd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V1
ROLRdRotate Left through CarryRd(0) ←=C, Rd(n+1) ← Rd(n), C ←=Rd(7)Z,C,N,V1
RORRdRotate Right through CarryRd(7) ←=C, Rd(n) ← Rd(n+1), C ←=Rd(0)Z,C,N,V1
ASRRdArithmetic Shift RightRd(n) ← Rd(n+1), n = 0..6Z,C,N,V1
SWAPRdSwap NibblesRd(3..0) ←=Rd(7..4), Rd(7..4) ←=Rd(3..0)None1
BSETsFlag SetSREG(s) ← 1SREG(s)1
BCLRsFlag ClearSREG(s) ← 0SREG(s)1
BSTRr, bBit Store from Register to TT ← Rr(b)T1
BLDRd, bBit Load from T to RegisterRd(b) ← TNone1
SECSet CarryC ← 1C1
CLCClear CarryC ← 0C1
SENSet Negative FlagN ← 1N1
CLNClear Negative FlagN ← 0N1
SEZSet Zero FlagZ ← 1Z1
CLZClear Zero FlagZ ← 0Z1
SEIGlobal Interrupt EnableI ← 1I1
CLIGlobal Interrupt DisableI=← 0I1
SESSet Signed Test FlagS ← 1S1
CLSClear Signed Test FlagS ← 0S1
SEVSet Two’s Complement OverflowV ← 1V1
CLVClear Two’s Complement OverflowV ← 0V1
SETSet T in SREGT ← 1T1
CLTClear T in SREGT ← 0T1
SEHSet Half-carry Flag in SREGH ← 1H1
CLHClear Half-carry Flag in SREGH ← 0H1
NOPNo OperationNone1
SLEEPSleep(see specific descr. for Sleep function)None1
WDRWatchdog Reset(see specific descr. for WDR/timer)None1
8
AT90S8515
0841GS–09/01
AT90S8515
AT90S8515 Ordering Information
Speed (MHz)Power SupplyOrdering CodePackageOperation Range
42.7V - 6.0VAT90S8515-4AC
AT90S8515-4JC
AT90S8515-4PC
AT90S8515-4AI
AT90S8515-4JI
AT90S8515-4PI
84.0V - 6.0VAT90S8515-8AC
AT90S8515-8JC
AT90S8515-8PC
AT90S8515-8AI
AT90S8515-8JI
AT90S8515-8PI
Note:Order AT90S8515A-XXX for devices with the FSTRT Fuse programmed.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
AT ME L® and AVR® are the registered trademarks of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
0841GS–09/01/xM
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