Atmel AT90S8515-4 User Manual

Features

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This i

• Utilizes the AVR

• AVR – High-performance and Low-power RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz

• Data and Nonvolatile Program Memory

– 8K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles
– 512 Bytes of SRAM
– 512 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler

Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Programmable Serial UART
– Master/Slave SPI Serial Interface

• Special Microcontroller Features

– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources

• Specifications

– Low-power, High-speed CMOS Process Technology
– Fully Static Operation

• Power Consumption at 4 MHz, 3V, 25°C

– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power-down Mode: <1 µA

• I/O and Packages

– 32 Programmable I/O Lines
– 40-lead PDIP, 44-lead PLCC and TQFP

• Operating Voltages

– 2.7 - 6.0V for AT90S8515-4
– 4.0 - 6.0V for AT90S8515-8

• Speed Grades

– 0 - 4 MHz for AT90S8515-4
– 0 - 8 MHz for AT90S8515-8

®

RISC Architecture

8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash

AT90S8515

Summary

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Rev. 0841GS–09/01

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Pin Configurations

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AT90S8515

0841GS–09/01

AT90S8515

Description The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the AT90S8515
achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to
optimize power consumption versus processing speed.

Block Diagram Figure 1. The AT90S8515 Block Diagram

0841GS–09/01

The AVR core combines a rich instruction set with 32 general-purpose working regis­ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in

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Pin Descriptions

one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.

The AT90S8515 provides the following features: 8K bytes of In-System Programmable
Flash, 512 bytes EEPROM, 512 bytes SRAM, 32 general-purpose I/O lines, 32 general­purpose working registers, flexible timer/counters with compare modes, internal and
external interrupts, a programmable serial UART, programmable Watchdog Timer with
internal oscillator, an SPI serial port and two software-selectable power-saving modes.
The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and
interrupt system to continue functioning. The Power-down mode saves the register con­tents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip In-System Programmable Flash allows the program memory to be repro­grammed In-System through an SPI serial interface or by a conventional nonvolatile
memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro­grammable Flash on a monolithic chip, the Atmel AT90S8515 is a powerful
microcontroller that provides a highly flexible and cost-effective solution to many embed­ded control applications.

The AT90S8515 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators and evaluation kits.

VCC Supply voltage.

GND Ground.

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis­plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,
they will source current if the internal pull-up resistors are activated. The Port A pins are
tri-stated when a reset condition becomes active, even if the clock is not active.

Port A serves as multiplexed address/data input/output when using external SRAM.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not active.

Port B also serves the functions of various special features of the AT90S8515 as listed
on page 66.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output

buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not active.

Port C also serves as address output when using external SRAM.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source

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AT90S8515

0841GS–09/01