Apple MACKBOOK J113 Schematic

TABLE_TABLEOFCONTENTS_ITEM

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

10/03/14

J113 MLB SCHEMATIC

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE

Schematic / PCB #’s

PRODUCT SAFETY REQUIREMENTS:

ALIASES RESOLVED

1 OF 76

<PART_DESCRIPTION>

<SCH_NUM>

<ECO_DESCRIPTION>

1 OF 121

J41_MLB

60

02/06/2013

45 Fan

J41_MLB

58

02/06/2013

44

Thermal Sensors

J41_MLB

56

03/28/2013

43

Debug Sensors 1

J41_MLB

55

03/28/2013

42

Voltage & Load Side Current Sensing

J41_MLB

54

03/28/2013

41

High Side Current Sensing

J41_MLB

53

02/06/2013

40

SMBus Connections

J41_MLB

52

02/06/2013

39

SMC Project Support

J41_MLB

51

02/06/2013

38

SMC Shared Support

J41_MLB

50

02/06/2013

37 SMC

J41_MLB

48

02/12/2013

36

IPD Connector

J41_MLB

46

02/07/2013

35

External A USB3 Connector

MASTER

45

10/11/2010

34

SD CONTROLLER (GL3219)

MASTER

44

07/01/2011

33

SD READER CONNECTOR

J41_MLB

40

03/20/2013

32

Camera 2 of 2

J41_MLB

39

04/02/2013

31

Camera 1 of 2

J41_MLB

37

04/09/2013

30

SSD Connector

J41_MLB

35

02/06/2013

29

Wireless Connector

J41_MLB

32

02/07/2013

28

Thunderbolt Connector A

J41_MLB

30

02/06/2013

27

TBT Power Support

J41_MLB

29

02/06/2013

26

Thunderbolt Host (2 of 2)

J41_MLB

28

02/06/2013

25

Thunderbolt Host (1 of 2)

J41_MLB

27

02/06/2013

24

LPDDR3 DRAM Termination

J41_MLB

26

02/06/2013

23

LPDDR3 DRAM Channel B (32-63)

J41_MLB

25

02/06/2013

22

LPDDR3 DRAM Channel B (0-31)

J41_MLB

24

02/06/2013

21

LPDDR3 DRAM Channel A (32-63)

J41_MLB

23

02/06/2013

20

LPDDR3 DRAM Channel A (0-31)

J41_MLB

22

02/12/2013

19

DDR3 VREF MARGINING

J41_MLB

20

02/15/2013

18

Project Chipset Support

J41_MLB

19

02/06/2013

17

Chipset Support

J41_MLB

18

02/06/2013

16

CPU/PCH Merged XDP

J41_MLB

16

04/02/2013

15

PCH GPIO/MISC/LPIO

J41_MLB

15

02/06/2013

14

PCH PCIe/USB/LPC/SPI/SMBus

J41_MLB

14

02/06/2013

13

PCH PM/PCI/GFX

J41_MLB

13

02/06/2013

12

PCH Audio/JTAG/SATA/CLK

J41_MLB

12

02/07/2013

11

PCH Decoupling

WILL_J43

10

01/08/2013

10

CPU Decoupling

J41_MLB

9

02/06/2013

9

CPU/PCH GROUNDS

J41_MLB

8

04/09/2013

8

CPU/PCH POWER

J41_MLB

7

02/06/2013

7

CPU DDR3/LPDDR3 Interfaces

J41_MLB

6

04/02/2013

6

CPU Misc/JTAG/CFG/RSVD

J41_MLB

5

02/06/2013

5

CPU GFX/NCTF/RSVD

MASTER

4

MASTER

4

PD PARTS

K21_MLB

3

11/16/2010

3

BOM Variants

J41_MLB

2

04/09/2013

2

BOM Configuration

Reference

76

07/03/2012

J41_MLB

121

Project Specific Constraints

75

09/25/2012

CONSTRAINTS

119

Project Specific Constraints

74

12/07/2012

J41_MLB

118

SMC Constraints

73

09/25/2012

CONSTRAINTS

117

Camera Constraints

72

01/30/2013

J41_MLB

116

Thunderbolt Constraints

71

09/25/2012

CONSTRAINTS

115

Memory Constraints

70

09/25/2012

CONSTRAINTS

114

PCH Constraints 2

69

12/14/2012

J41_MLB

113

PCH Constraints 1

68

11/13/2012

CLEAN_J43

112

CPU Constraints

67

09/25/2012

CONSTRAINTS

111

PCB Rule Definitions

66

10/24/2012

CONSTRAINTS

110

Project FCT/NC/Aliases

65

09/13/2012

J41_MLB

105

Func Test / No Test

64

02/01/2013

J41_MLB

104

Signal Aliases

63

08/30/2012

J41_MLB

102

Power Aliases

62

01/30/2013

J41_MLB

100

Left I/O (LIO) Connector

61

11/13/2012

CLEAN_J43

95

Internal DisplayPort Connector

60

02/06/2013

J41_MLB

83

Power Control

59

02/06/2013

J41_MLB

81

Power FETs

58

02/06/2013

J41_MLB

80

Misc Power Supplies

57

02/06/2013

J41_MLB

78

LCD/KBD Backlight Driver

56

02/06/2013

J41_MLB

77

1.05V S0 Power Supply

55

05/21/2013

J41_MLB

76

5V S4RS3 / 3.3V S5 Power Supply

54

09/17/2012

J41_MLB

75

LPDDR3 Supply

53

05/21/2013

J41_MLB

74

CPU VR12.5 VCC Power Stage

52

05/21/2013

J41_MLB

73

CPU VR12.6 VCC Regulator IC

51

04/09/2013

J41_MLB

72

PBus Supply & Battery Charger

50

05/21/2013

J41_MLB

71

DC-In & G3H Supply

49

02/06/2013

J41_MLB

70

Battery Connector

48

MASTER

69

Audio: Speaker Amp

47

04/26/2013

J41_MLB

64

Date

Page Sync

Contents

(.csa)

LPC+SPI Debug Connector

46

04/02/2013

J41_MLB

61

820-00165

PCBF,MLB,J43

CRITICAL

PCB

1

051-00385

SCH

CRITICAL

1

SCHEM,MLB,J43A

LAST_MODIFIED=Fri Oct 3 11:36:00 2014

TITLE=MLB

ABBREV=DRAWING

(.csa)

Sync

Date

Contents

Page

MASTER

1

MASTER

1

Table of Contents

w w w . c h i n a f i x . c o m

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

Module Parts

DRAM Parts

CFG 0

00

1 0

0 1

CPU DRAM CFG Chart

CFG 1

HYNIX

VENDOR

SAMSUNG

MICRON

0

1

CFG 2

1

0

1

0

1

0

1

CFG 3

RSVD

16GB

8GB

4GB

SIZE

ELPIDA

Current Sensor Configuration

CPU DRAM SPD Straps

Programmable Parts

Alternate Parts

BOM Groups

ALT PWR DIST SW

353S00133

353S2741

ALL

311S0508

311S00013

ALT SNGL BUFFER

ALL

311S0515

311S00014

ALT DUAL BUFFER

ALL

ALT 2-INPT AND

311S0450

311S00015

ALL

311S00008

311S0271

ALT AND GATE

ALL

311S00007

311S0426

ALT SNGL BUFFER

353S3812353S3814

ALT TBT PORT MUX

ALL

341S00153

IC,EFI ROM(V0108)), PROTO 0,J110/J113

1

BOOTROM:PROG

CRITICAL

U6100

341S00159

T29,EEPROM,FALCON RIDGE(V27.1), PROtO 0,J110/J113

CRITICAL

1

TBTROM:PROG

U2890

335S00007

IC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1

BOOTROM_NUM:BLANK

CRITICAL

1

U6100

335S00006

IC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1

1

BOOTROM_MAC:BLANK

CRITICAL

U6100

IC,SMC12-B1,40MHZ/50DMIPS MCU,157BGA

338S1214

1

SMC:BLANK

U5000

CRITICAL

U2300,U2400,U2500,U2600

4

CRITICAL333S0791

IC,SDRAM,16GB,LPDDR3-1600,178P FBGA

DRAM_TYPE:MICRON_8GB

DRAM_TYPE:ELPIDA_16GB

333S0789

IC,SDRAM,25nm,32Gb,LPDDR3-1600,178P FBGA

CRITICAL

4

U2300,U2400,U2500,U2600

CRITICAL

4

DRAM_TYPE:MICRON_4GB

U2300,U2400,U2500,U2600

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

333S0793

333S0791

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

U2300,U2400,U2500,U2600

CRITICAL

4

DRAM_TYPE:ELPIDA_8GB

333S0793

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

CRITICAL

4

U2300,U2400,U2500,U2600

DRAM_TYPE:ELPIDA_4GB

MLB_DEBUG:PVT

BKLT:PROD,XDP,SAMCONN,ISNS:ENG,DBGLED,XDP_CONN

ALT STANDOFF W_O MYLAR

860-1328

ALL

860-3690

DRAM_TYPE:HYNIX_4GB

ALL

ALT STANDOFF W_O MYLAR

333S0787 333S0677

ALT STANDOFF W_O MYLAR

ALL

333S0785 333S0681

DRAM_TYPE:HYNIX_8GB

ALT STANDOFF W_O MYLAR

860-3428 860-1327

ALL

LABEL,TEXT,MLB,K21/K78

1

LABEL

825-7670

NEW_LABEL

LABEL,MLB,J41/J43

825-7987

1

870-5074 870-1938

ALT POGO PIN W_O CAP

ALL

107S0248107S0250

Cyntec alt to TFT

ALL

107S0255 107S0240

Cyntec alt to TFT

ALL

152S1804152S1876

TDK alt to Toko

ALL

376S0761

ALL

Renesas alt to Vishay

376S00014

SYNC_DATE=01/17/2013

SYNC_MASTER=J43_MLB

BOM Configuration

138S0638138S0841

ALL

Murata alt to Samsung

197S0544197S0542

NDK alt to TXC

ALL

377S0104377S0155

ALL

OnSemi alt to Infineon

Taiyo alt to Samsung

138S0638138S0681

ALL

197S0544197S0545

Epson alt to TXC

ALL

128S0220128S0398

Kemet alt to Sanyo

ALL

Kemet alt to Sanyo

128S0397 128S0325

128S0386

ALL

128S0284

Kemet alt to Sanyo

353S3452

Maxim alt to Microchip

ALL

353S1286

Diodes alt to Fairchild

376S0604376S1053

ALL

Diodes alt to ST Micro

ALL

371S0558371S0713

ALL

128S0376128S0371

Kemet alt to Sanyo

152S1757

Cyntec alt to NEC

ALL

152S1821

197S0343

ALL

NDK crystal alt to TXC

197S0480

107S0254 107S0241

ALL

Cyntec sense R alt to TFT

138S0648138S0703

Murata alt to Taiyo Yuden

ALL

152S1301152S0586

ALL

Dale/Vishay alt to Cyntec

372S0186

NXP alt to Diodes

372S0185

ALL

197S0478197S0479

200uW Epson alt to NDK

138S0660138S0684

Murata alt to Taiyo Yuden

ALL

376S1032 376S0855

Toshiba alt for Diodes dual

ALL

376S1089

ALL

NXP alt for Diodes single

376S1128

BKLT:PROD,SAMCONN,XDP,ISNS:PROD

MLB_DEBUG:PROD

XDP_CONN

MLB_DEVEL:PVT

MLB_DEVEL:ENG

ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENG

PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS,SSD_LPSR:S3

MLB_MISC

MLB_COMMON

ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:PVT,MLB_PROGPARTS

ALL

Epson crystal alt to TXC

197S0481 197S0343

376S0855

ALL

NXP alt for Diodes dual

376S1129

RAMCFG0:H,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:MICRON_8GB

DDR3:MICRON_8GB

DDR3:MICRON_16GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:MICRON_16GB

DDR3:HYNIX_16GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:HYNIX_16GB

DDR3:SAMSUNG_16GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:SAMSUNG_16GB

DDR3:ELPIDA_16GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:ELPIDA_16GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GB

DDR3:MICRON_4GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

DDR3:ELPIDA_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

DDR3:SAMSUNG_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

DDR3:ELPIDA_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

DDR3:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

DDR3:HYNIX_8GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

DDR3:HYNIX_4GB

ISNS:PROD

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NO

ISNS:ENG

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YES

4

CRITICAL

U2300,U2400,U2500,U2600

DRAM_TYPE:SAMSUNG_8GB

IC,SDRAM,23NM,16GB,LPDDR3-1600,178P FBGA

333S00003

U2300,U2400,U2500,U2600

CRITICAL

4

DRAM_TYPE:SAMSUNG_4GB

IC,SDRAM,23NM,8GB,LPDDR3-1600,178P FBGA

333S00001

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

U2300,U2400,U2500,U2600

CRITICAL

4

DRAM_TYPE:HYNIX_4GB

333S0677

376S1194 CRITICAL

Q7310,Q7320

2

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

VCORE_FET:VSHY

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

376S1193

Q7311,Q7321

CRITICAL

2

VCORE_FET:VSHY

900-0090

SOLDERPASTE

1

CRITICAL

2

CRITICAL

Q7311,Q7321

VCORE_FET:REN

376S00037

MOSFET,N-CH,30V,64A,3.5M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,52A,5.9M,8P 3.3X3.3 DFN

376S00036

CRITICAL

Q7310,Q7320

2

VCORE_FET:REN

946-5477 CRITICALGLUE

1

UV GLUE,MLB,J41_J43

U3900

CRITICAL

1

338S1264

IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA

607-6811

1

J6955

CRITICAL

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

J113_MLB

1

CRITICAL

U0500

CPU:1.6GHZ

BDW,QGHB,D0,1.6,15W,2+2,0.6,4M,B1168

337S00073

1

CRITICAL

U0500

337S00029

BDW,QGH9,D0,1.8,15W,2+2,0.7,4M,B1168

CPU:2.1GHZ

4

CRITICAL

DRAM_TYPE:HYNIX_8GB

U2300,U2400,U2500,U2600

333S0681

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

XDP,SAMCONN

MLB_DEBUG:ENG

EEPROM,4MBIT,SPI,50MHZ,1.8V,USON8

335S0915

U2890

1

CRITICAL

TBTROM:BLANK

338S00069

IC,TBT,FR-2C,288,12x12 ,FC-CSP,TRAY

CRITICAL

U2800

1

<SCH_NUM>

2 OF 121

2 OF 76

w w w . c h i n a f i x . c o m

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM Variants

Programmable Parts

BOM Groups

Alternate Parts

Sub-BOMs

Module Parts

338S1246

U4500

1

CRITICAL

IC,GL3219,USB3 SD CARD READER,46P,LQFN

685-00048

VCORE FET,VSHY,X433

VCORE_FET:VSHY

685-00047

VCORE FET,REN,X433

VCORE_FET:REN

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_4GB

639-00641

PCBA,MLB,BETTER,EL-4GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_16GB

PCBA,MLB,BETTER,MI-16GB,X433

639-00640

MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_8GB

639-00639

PCBA,MLB,BETTER,MI-8GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_4GB

PCBA,MLB,BETTER,MI-4GB,X433

639-00638

MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_8GB,ALTERNATE

639-00637

PCBA,MLB,BETTER,SM-8GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_4GB,ALTERNATE

PCBA,MLB,BETTER,SM-4GB,X433

639-00636

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_16GB

639-00635

PCBA,MLB,BETTER,HY-16GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_8GB,ALTERNATE

639-00634

PCBA,MLB,BETTER,HY-8GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_4GB,ALTERNATE

PCBA,MLB,BETTER,HY-4GB,X433

639-00633

639-00632

PCBA,MLB,BEST,EL-8GB,X433

MLB_CMNPTS,CPU:2.1GHZ,DDR3:ELPIDA_8GB

MLB_CMNPTS,CPU:2.1GHZ,DDR3:ELPIDA_4GB

PCBA,MLB,BEST,EL-4GB,X433

639-00631

639-00630

PCBA,MLB,BEST,MI-16GB,X433

MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_16GB

MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_8GB

PCBA,MLB,BEST,MI-8GB,X433

639-00629

639-00628

PCBA,MLB,BEST,MI-4GB,X433

MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_4GB

PCBA,MLB,BEST,SM-8GB,X433

639-00627

MLB_CMNPTS,CPU:2.1GHZ,DDR3:SAMSUNG_8GB,ALTERNATE

MLB_CMNPTS,CPU:2.1GHZ,DDR3:SAMSUNG_4GB,ALTERNATE

639-00626

PCBA,MLB,BEST,SM-4GB,X433

639-00624

MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_8GB,ALTERNATE

PCBA,MLB,BEST,HY-8GB,X433

PCBA,MLB,BEST,HY-4GB,X430

MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_4GB,ALTERNATE

639-00623

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

BOM Variants

333S0700333S0704

ALL

Elpida CAM DRAM alt to Hynix

685-00048685-00047

ALL

Renesas alt to Vishay

CMNPTS

1

MLB_CMNPTS

CRITICAL

685-00046

CMN PTS,PCBA,MLB,J113

VCOREFETS

VCORE_FETS

CRITICAL

1

685-00048

VCORE FET,VSHY,J113

MLB_PROGPARTS

BOOTROM:PROG,SMC:PROG,TBTROM:PROG

639-00625

PCBA,MLB,BEST,HY-16GB,X433

MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_16GB

SMC:PROG

1

CRITICAL

U5000

341S00148

IC,SMC-B1,EXT(Vxxxx),PROTO 0,J113

685-00046

CMN PTS,PCBA,MLB,X433

MLB_COMMON,J113_MLB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_8GB

639-00642

PCBA,MLB,BETTER,EL-8GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_16GB

PCBA,MLB,BETTER,EL-16GB,X433

639-00697

<SCH_NUM>

3 OF 121

3 OF 76

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PD Module Parts

EMI I/O Pogo Pins

USB/SD Card Pogo

Can Slots

2x TBT pin diodes

2x MDP Connector

2x USB Connector

2x TBT chip

DisplayPort Pogo

870-1938

860-1327

Fan Boss

860-1327

X21 Boss

870-1938

SSD Boss

860-1327

4x 860-1327

Plated Board Slot

CPU Heat Sink Mounting Bosses

1

ZS0406

SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

1

Z0414

STDOFF-4.5OD1.9H-SM

1

Z0405

STDOFF-4.5OD1.8H-SM

1

ZS0405

POGO-2.0OD-3.6H-K86-K87

CRITICAL

SM

1

SL0402

TH-NSP

SL-1.1X0.4-1.4X0.7

1

SL0406

TH-NSP

SL-1.1X0.4-1.4X0.7

1

SL0401

TH-NSP

SL-1.1X0.4-1.4X0.7

1

SL0403

SL-1.1X0.4-1.4X0.7

TH-NSP

1

SL0407

SL-1.1X0.45-1.4X0.75

TH-NSP

1

SL0408

SL-1.1X0.4-1.4X0.7

TH-NSP

1

SL0400

TH-NSP

SL-2.3X3.9-2.9X4.5

1

SL0405

TH-NSP

SL-1.1X0.45-1.4X0.75

1

SL0404

TH-NSP

SL-1.1X0.4-1.4X0.7

1

Z0410

STDOFF-4.5OD1.52H-SM

1

Z0412

STDOFF-4.5OD1.52H-SM

1

Z0413

STDOFF-4.5OD1.52H-SM

1

Z0411

STDOFF-4.5OD1.52H-SM

1

Z0415

STDOFF-4.5OD1.9H-SM

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PD PARTS

TBTTOPSIDE_2P_FENCE

CAN,TOPSIDE,ALT,J41/J43

806-5107 CRITICAL

1

806-5108

TBTTOPSIDE_2P_COVER

CAN,TOPSIDE,COVER,ALT,J41/J43

CRITICAL

1

806-3142

CAN,TBT,J11/J13

TBTFENCE CRITICAL

1

806-3215 TBTCOVER

CAN,COVER,TBT,J11/J13

CRITICAL

1

MDPCAN

CAN,MDP,J11/J13

806-3216 CRITICAL

1

USBCAN

SHLD,USB,MLB,J11/J13

806-3083 CRITICAL

1

<SCH_NUM>

4 OF 121

4 OF 76

w w w . c h i n a f i x . c o m

OUT

OUT OUT OUT OUT

BI BI

DDI

EDP

SYM 1 OF 19

EDP_TXN0

EDP_TXP1

EDP_TXN1

EDP_TXP0

DDI1_TXP2

DDI1_TXN2

DDI2_TXP3

DDI2_TXN3

DDI2_TXP2

DDI2_TXN2

DDI2_TXP1

DDI2_TXN1

DDI2_TXP0

DDI1_TXP1

DDI1_TXN1

DDI1_TXP0

DDI1_TXN0

DDI2_TXN0

DDI1_TXP3

DDI1_TXN3

EDP_RCOMP

EDP_DISP_UTIL

EDP_AUXN EDP_AUXP

EDP_TXP3

EDP_TXN3

EDP_TXP2

EDP_TXN2

SYM 17 OF 19

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

SPARE

SYM 18 OF 19

RSVD

RSVD RSVD

RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

TP

NC NC

NCNC NCNC NCNC

NCNC NCNC NCNC NC NC NC NC

OUT

OUT OUT OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Other corner test signals connected in

MCP Daisy-Chain Strategy:

Each corner of CPU has two testpoints.

NO_TESTNO_TEST

daisy-chain fashion. Continuity should exist between both TP’s on each corner.

eDP Port Assignment:

Internal panel

DDI Port Assignments:

TBT Sink 0

TBT Sink 1 (MUXed with HDMI if necessary)

18 25 67

60 67

64

60 67

B49

C46

B47

B46

A49

C47

A47

C45

D20 A43

B45

A45

B53

B50

B54

C50

A53

C49

C53

C51

B57

A55

C58

C55

A57

B55

B58

C54

U0500

BGA

OMIT_TABLE

CRITICAL

2C+GT2

BROADWELL-ULT

C2

C1

B63

B62

B61

B3

B2

AY62

AY61

AY60

AY3

AY2

AW63

AW62

AW61

AW3

AW2

AW1

AV1

A62

A61

A60

A4

A3

U0500

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

U10

T23

R23

N23

J21

H22

F22

D15

AY14

AW14

AV44

AU44

AU15

AU10

AT2

AP7

AM11

AL1

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

1

TP0531

TP-P6

1

TP0500

TP-P6

1

TP0510

TP-P6

1

TP0501

TP-P6

1

TP0511

TP-P6

1

TP0520

TP-P6

1

TP0521

TP-P6

1

TP0530

TP-P6

2

1

R0530

24.9

1%

MF 201

1/20W

25 67

18 25 67

CPU GFX/NCTF/RSVD

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

TRUE

MCP_DC_A3_B3

MCP_DC_A60

MCP_DC_A4

MCP_DC_A62

MCP_DC_A61_B61

TRUE

MCP_DC_AV1 MCP_DC_AW1 MCP_DC_AW2_AY2

TRUE

MCP_DC_AW61_AY61

TRUE

MCP_DC_AW3_AY3

MCP_DC_AW62_AY62

TRUE

MCP_DC_AW63

MCP_DC_B2

TRUE

MCP_DC_AW62_AY62

MCP_DC_A61_B61

TRUE

MCP_DC_A3_B3

TRUE

MCP_DC_B62_B63

TRUE

MCP_DC_C1_C2

TRUE

MCP_DC_AW61_AY61

MCP_DC_AY60

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW2_AY2

TRUE

DP_INT_ML_C_N<0>

NC_INT_ML_CP<1>

NC_INT_ML_CN<1>

DP_INT_ML_C_P<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

MCP_EDP_RCOMP TP_EDP_DISP_UTIL

DP_INT_AUXCH_C_N DP_INT_AUXCH_C_P

NC_INT_ML_CP<3>

NC_INT_ML_CN<3>

NC_INT_ML_CP<2>

NC_INT_ML_CN<2>

PPVCOMP_S0_CPU

5 OF 76

<SCH_NUM>

5 OF 121

5

8

w w w . c h i n a f i x . c o m

BI BI

BI

NC NC

NC

SYM 2 OF 19

MISC

THERMAL

JTAG

DDR3

PWR

SM_PG_CNTL1

SM_DRAMRST*

SM_RCOMP1 SM_RCOMP2

SM_RCOMP0

PROCHOT*

PROCPWRGD

PECI

CATERR*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

PROC_TDO

PROC_TDI

PROC_TRST*

PROC_TMS

PROC_TCK

PREQ*

PRDY*

PROC_DETECT*

RESERVED

SYM 19 OF 19

VSS VSS

RSVD

CFG_RCOMP

RSVD

RSVD RSVD

TD_IREF

CFG0 CFG1

CFG5

CFG4

CFG3

CFG2

CFG6

CFG10

CFG9

CFG8

CFG7

CFG11

CFG15

CFG14

CFG13

CFG12

CFG18

CFG16

CFG17 CFG19

RSVD RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

PROC_OPI_COMP

RSVD RSVD

RSVD_B43

BI

OUT

NC

BI

OUT

IN

OUT

NC NC

NC NC NC

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

(IPU)

(IPD)

(IPU)

These can be placed close to J1800 and are only for debug access

issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid

CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID

2

1

R0640

NOSTUFF

1K

5%

201

1/20W

MF

2

1

R0639

HSW_PRE_ES2

1K

5%

201

1/20W MF

2

1

R0638

MF

1/20W

201

5%

1K

NOSTUFF

2

1

R0631

MF

1/20W

201

5%

1K

NOSTUFF

2

1

R0630

NOSTUFF

1K

5%

201

1/20W MF

6

16 67

6

16 67

16 64 67

16 67

6

16 67

6

16 67

6

16 67

6

16 67

16

AU61

AV60

AU60

AV61

AV15

C61

K63

E59

E61

F62

F63

E60

D61

K62

J62

N62

K61

J61

K60

H63

K59

H62

H61

H60

J60

U0500

BROADWELL-ULT

2C+GT2

BGA

OMIT_TABLE

CRITICAL

P22 N21

B12

Y22

W23

L60

C63 C62

B51

AV63 AU63

A51

R20

P20

N60

J20 H18

E1

D58

D1

B43

AV62

A5

AY15

V63

V61

V62

Y60

Y61

Y62

AA60

AA63

AC63

U62

U63

AA61

AA62

T60

T61

T62

T63

U60

V60

AC62

AC60

U0500

CRITICAL

OMIT_TABLE

BROADWELL-ULT

2C+GT2

BGA

37 38 51 67

2

1

R0610

5%

1/20W

MF

201

62

2 1

R0611

201

5%

MF

56

1/20W

38 67

37 67

2

1

R0620

PLACE_NEAR=U0500.C61:12.7mm

201

MF

1/20W

5%

10K

16 67

16 64 67

12 16 64 67

16 64 67

2

1

R0652

MF

1/20W

201

100

1%

PLACE_NEAR=U0500.AU61:12.7mm

2

1

R0651

MF

1/20W

201

1%

PLACE_NEAR=U0500.AV60:12.7mm

121

2

1

R0650

1%

200

201

1/20W

MF

PLACE_NEAR=U0500.AU60:12.7mm

18

17

2

1

R0680

1%

1/20W

201

MF

49.9

2

1

R0690

201

MF

1/20W

1%

49.9

2

1

R0685

1/20W MF 201

1%

8.25K

2

1

R0634

1K

5%

201

1/20W MF

EDP

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

CPU Misc/JTAG/CFG/RSVD

CPU_CFG_RCOMP

PCH_TD_IREF

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<5>

CPU_CFG<4>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<6>

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<11>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<12>

CPU_CFG<18>

CPU_CFG<16>

CPU_CFG<17> CPU_CFG<19>

TP_MCP_RSVD_AV63 TP_MCP_RSVD_AU63

TP_MCP_RSVD_C63 TP_MCP_RSVD_C62

TP_MCP_RSVD_A51 TP_MCP_RSVD_B51

TP_MCP_RSVD_L60

CPU_OPI_RCOMP

CPU_MEMVTT_PWR_EN_LSVDDQ

TP_CPU_MEM_RESET_L

CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>

CPU_SM_RCOMP<0>

CPU_PROCHOT_R_L

CPU_PWRGD

CPU_PECI

CPU_CATERR_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPUPCH_TRST_L

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_PREQ_L

XDP_CPU_PRDY_L

CPU_CFG<1>

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

CPU_CFG<0>

CPU_PROCHOT_L

CPU_CFG<4>

PP1V05_S0

6 OF 76

6 OF 121

<SCH_NUM>

67

6

16 67

6

16 67

6

16 67

6

16 67

6

16 67

6

16 67

8

11 15 16 17 38 42 51 55 58

59 62 64

w w w . c h i n a f i x . c o m

BI BI

BI

BI BI BI

BI BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI BI

BI

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI

SYM 3 OF 19

MEMORY CHANNEL A

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ55 SA_DQ56

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ45 SA_DQ46

SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ40 SA_DQ41

SA_DQ39

SA_DQ37 SA_DQ38

SA_DQ34

SA_DQ36

SA_DQ32 SA_DQ33

SA_DQ29 SA_DQ30 SA_DQ31

SA_DQ27 SA_DQ28

SA_DQ24 SA_DQ25

SA_DQ22 SA_DQ23

SA_DQ21

SA_DQ19 SA_DQ20

SA_DQ17 SA_DQ18

SA_DQ16

SA_DQ14 SA_DQ15

SA_DQ11

SA_DQ13

SA_DQ10

SA_DQ9

SA_DQ7 SA_DQ8

SA_DQ6

SA_DQ4 SA_DQ5

SA_DQ3

SA_DQ1

SA_DQ0

SA_CLK1*

SA_CLK0

SA_CLK0*

SA_DQ12

SM_VREF_DQ1

SM_VREF_CA

SM_VREF_DQ0

SA_DQ35

SA_DQ26

SA_DQ2

SA_CLK1

SA_CS0* SA_CS1*

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0

SA_MA2

SA_MA1

SA_MA3 SA_MA4 SA_MA5

SA_MA7

SA_MA6

SA_MA8

SA_MA10

SA_MA9

SA_MA12

SA_MA11

SA_MA13 SA_MA14 SA_MA15

SA_BA2

SA_BA0 SA_BA1

SA_DQSP0

SA_DQSP2

SA_DQSP1

SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SA_DQSN1

SA_DQSN0

SA_DQSN2

SA_DQSN4

SA_DQSN3

SA_DQSN5 SA_DQSN6 SA_DQSN7

SYM 4 OF 19

MEMORY CHANNEL B

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5

SB_CKE0

SB_DQ6

SB_CKE1

SB_DQ7

SB_CKE2

SB_DQ8

SB_CKE3 SB_DQ9 SB_DQ10 SB_CS0* SB_DQ11 SB_CS1* SB_DQ12 SB_DQ13 SB_ODT0 SB_DQ14 SB_DQ15 SB_RAS* SB_DQ16

SB_WE* SB_DQ17 SB_CAS* SB_DQ18 SB_DQ19

SB_BA0 SB_DQ20

SB_BA1 SB_DQ21

SB_BA2 SB_DQ22 SB_DQ23

SB_MA0 SB_DQ24

SB_MA1 SB_DQ25

SB_MA2 SB_DQ26

SB_MA3 SB_DQ27

SB_MA4 SB_DQ28

SB_MA5 SB_DQ29

SB_MA6 SB_DQ30

SB_MA7 SB_DQ31

SB_MA8 SB_DQ32

SB_MA9 SB_DQ33 SB_MA10 SB_DQ34 SB_MA11 SB_DQ35 SB_MA12

SB_MA13 SB_DQ37 SB_MA14 SB_DQ38 SB_MA15 SB_DQ39 SB_DQ40

SB_DQSN0

SB_DQ41

SB_DQSN1

SB_DQ42

SB_DQSN2

SB_DQ43

SB_DQSN3

SB_DQ44

SB_DQSN4

SB_DQ45

SB_DQSN5

SB_DQ46

SB_DQSN6

SB_DQ47

SB_DQSN7 SB_DQ48 SB_DQ49

SB_DQSP0 SB_DQ50

SB_DQSP1 SB_DQ51

SB_DQSP2 SB_DQ52

SB_DQSP3 SB_DQ53

SB_DQSP4 SB_DQ54

SB_DQSP5 SB_DQ55

SB_DQSP6 SB_DQ56

SB_DQSP7 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_DQ36

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE

12

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CAA3

CAA1

CAB7 CAA7

CAA6 CAB0

CAA9

CAA8

CAA5

CAB9

CAB8 CAB5

RSVD1

RSVD2

CAA0

CAA2

CAA4

CAB3

CAB2 CAB1

CAB4 CAB6

LPDDR3

CAA5

CAB9

CAB8 CAB5

CAB3

CAB2 CAB1

CAB4 CAB6

LPDDR3

CAA3

CAA1

CAB7 CAA7

CAA6 CAB0

CAA9

CAA8

CAA0

CAA2

CAA4

RSVD3

RSVD4

63 70

21 63 70

63 70

21 63 70

63 70

63

20 21 24 63 70

20 21 24 70

20 24 70

21 24 70

20 24 70

63

21 24 63 70

63

20 24 63 70

63

63 70

21 63 70

63 70

21 24 70

19

22 24 70

23 24 70

22 24 70

23 24 70

22 23 24 70

22 23 24 63 70

63

23 24 63 70

63

22 24 63 70

63

63 70

23 63 70

63 70

23 63 70

63 70

23 63 70

63 70

AP51

AR51

AP49

AW34

AY34

AP32

AU40

AY39

AW39

AV40

AR36

AU39

AP36

AR38

AU42

AV42

AR35

AU41

AW41

AP35

AY37

AU36

AL49

AL42

AW53

AW57

AN55

AN58

AN61

AJ62

AL48

AL43

AV53

AV57

AM55

AM58

AN62

AJ61

AM62

AM63

AK60

AK51

AM51

AK48

AM48

AK61

AK49

AM49

AK46

AM46

AM42

AM40

AK43

AK45

AM45

AM43

AH60

AK42

AK40

AU52

AV52

AU54

AV54

AW52

AY52

AW54

AY54

AH61

AU56

AV56

AU58

AV58

AW56

AY56

AW58

AY58

AN54

AR54

AK62

AK55

AL55

AK54

AM54

AR55

AP55

AN57

AR57

AK58

AL58

AK63

AK57

AM57

AR58

AP58

AP60

AP61

AM60

AM61

AP62

AP63

AH62

AH63

AR32

AP33

AW36 AY36

AU37 AV37

AY43

AY42

AW43

AU43

AU34

AY41

AV35

AU35

U0500

BGA

2C+GT2

BROADWELL-ULT

OMIT_TABLE

CRITICAL

AK35

AM35

AL32

AU46

AY47

AY46

AW46

AP45

AR45

AR42

AP42

AP46

AR46

AK33

AU47

AV47

AK36

AR40

AP40

AM18

AM21

AW18

AV22

AM25

AM28

AW26

AV30

AN18

AN21

AV18

AW22

AN25

AN28

AV26

AW30

AW27

AY27

AU29

AP18

AR18

AM20

AK20

AV29

AL18

AK18

AR20

AN20

AK22

AK21

AP21

AN22

AM22

AL21

AU31

AR22

AR21

AU17

AV17

AU19

AV19

AW17

AY17

AW19

AY19

AV31

AU21

AV21

AU23

AV23

AW21

AY21

AW23

AY23

AL25

AK25

AW29

AM26

AK26

AP25

AR25

AR26

AN26

AP28

AR28

AN29

AR29

AY29

AK28

AL28

AK29

AM29

AU25

AV25

AU27

AV27

AW25

AY25

AW31

AY31

AK32

AM32

AV50

AW49

AU50

AY49

AK38 AL38

AM38 AN38

AM33

AU49

AM36

AL35

U0500

BGA

OMIT_TABLE

CRITICAL

BROADWELL-ULT

2C+GT2

CPU DDR3/LPDDR3 Interfaces

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<55> MEM_A_DQ<56>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<45> MEM_A_DQ<46>

MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<40> MEM_A_DQ<41>

MEM_A_DQ<39>

MEM_A_DQ<37> MEM_A_DQ<38>

MEM_A_DQ<34>

MEM_A_DQ<36>

MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31>

MEM_A_DQ<27> MEM_A_DQ<28>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<22> MEM_A_DQ<23>

MEM_A_DQ<21>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<17> MEM_A_DQ<18>

MEM_A_DQ<16>

MEM_A_DQ<14> MEM_A_DQ<15>

MEM_A_DQ<11>

MEM_A_DQ<13>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<7> MEM_A_DQ<8>

MEM_A_DQ<6>

MEM_A_DQ<4> MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_DQ<12>

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

CPU_DIMMA_VREFDQ

MEM_A_DQ<35>

MEM_A_DQ<26>

MEM_A_DQ<2>

MEM_A_CLK_P<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_CKE<0> MEM_A_CKE<1> MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_ODT<0>

=MEM_A_RAS_L =MEM_A_WE_L =MEM_A_CAS_L

=MEM_A_A<0>

=MEM_A_A<2>

=MEM_A_A<1>

TP_LPDDR3_RSVD1 TP_LPDDR3_RSVD2 =MEM_A_A<5>

=MEM_A_A<7>

=MEM_A_A<6>

=MEM_A_A<8>

=MEM_A_A<10>

=MEM_A_A<9>

MEM_A_CAA<6>

=MEM_A_A<11>

=MEM_A_A<13> =MEM_A_A<14> =MEM_A_A<15>

=MEM_A_BA<2>

=MEM_A_BA<0> MEM_A_CAB<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_DQ<36>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQS_P<7>

MEM_B_DQ<56>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQS_P<5>

MEM_B_DQ<54>

MEM_B_DQS_P<4>

MEM_B_DQ<53>

MEM_B_DQS_P<3>

MEM_B_DQ<52>

MEM_B_DQS_P<2>

MEM_B_DQ<51>

MEM_B_DQS_P<1>

MEM_B_DQ<50>

MEM_B_DQS_P<0>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQS_N<7>

MEM_B_DQ<47>

MEM_B_DQS_N<6>

MEM_B_DQ<46>

MEM_B_DQS_N<5>

MEM_B_DQ<45>

MEM_B_DQS_N<4>

MEM_B_DQ<44>

MEM_B_DQS_N<3>

MEM_B_DQ<43>

MEM_B_DQS_N<2>

MEM_B_DQ<42>

MEM_B_DQS_N<1>

MEM_B_DQ<41>

MEM_B_DQS_N<0>

MEM_B_DQ<40>

MEM_B_DQ<39>

=MEM_B_A<15>MEM_B_DQ<38>

=MEM_B_A<14>MEM_B_DQ<37>

=MEM_B_A<13>

MEM_B_CAA<6>MEM_B_DQ<35>

=MEM_B_A<11>MEM_B_DQ<34>

=MEM_B_A<10>MEM_B_DQ<33>

=MEM_B_A<9>

MEM_B_DQ<32>

=MEM_B_A<8>

MEM_B_DQ<31>

=MEM_B_A<7>

MEM_B_DQ<30>

=MEM_B_A<6>

MEM_B_DQ<29>

=MEM_B_A<5>

MEM_B_DQ<28>

TP_LPDDR3_RSVD4

MEM_B_DQ<27>

TP_LPDDR3_RSVD3

MEM_B_DQ<26>

=MEM_B_A<2>

MEM_B_DQ<25>

=MEM_B_A<1>

MEM_B_DQ<24>

=MEM_B_A<0>

MEM_B_DQ<23>

MEM_B_DQ<22>

=MEM_B_BA<2>MEM_B_DQ<21>

MEM_B_CAB<6>MEM_B_DQ<20>

=MEM_B_BA<0>MEM_B_DQ<19>

MEM_B_DQ<18>

=MEM_B_CAS_LMEM_B_DQ<17>

=MEM_B_WE_L

MEM_B_DQ<16>

=MEM_B_RAS_LMEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_ODT<0>MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_CS_L<1>

MEM_B_DQ<11>

MEM_B_CS_L<0>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_CKE<3>

MEM_B_DQ<8>

MEM_B_CKE<2>

MEM_B_DQ<7>

MEM_B_CKE<1>

MEM_B_DQ<6>

MEM_B_CKE<0>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

7 OF 76

7 OF 121

<SCH_NUM>

w w w . c h i n a f i x . c o m

OUT

IN

NC NC

NC

BI

NC NC

IN OUT IN

NC NC NC

NC

OUT

NC

NC NC

NC

NC NC NC

IN

NC

SUS OSCILLATOR

SERIAL IO

THERMAL SENSOR

SYM 13 OF 19

USB2

LPT LP POWER

CORE

SPI RTC

HSIO

OPI

USB3

AZALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

ICC

VCCHSIO VCCHSIO VCCHSIO

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCDSW3_3

VCCCLK

VCCACLKPLL

DCPSUS4

VCCRTC

DCPRTC

VCCSPI

VCCASW

VCC1P05 VCC1P05

VCC1P05

DCPSUSBYP DCPSUSBYP

VCCASW VCCASW VCCASW

DCPSUS1

VCCTS1_5

VCCSDIO

RSVD

RSVD RSVD RSVD

VCCAPLL

VCC1_05 VCC1_05

VCC3_3

VCCCLK VCCCLK

VCCSUS3_3

VCCSUS3_3 VCCSUS3_3

VCCSUS3_3

HSW ULT POWER

SYM 12 OF 19

VCC

VCCST

RSVD

RSVD RSVD

RSVD

RSVD_TP

VSS

PWR_DEBUG*

VSS

VCC_SENSE

RSVD

VCC RSVD

VDDQ VDDQ

VDDQ

RSVD

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VDDQ

VCCIOA_OUT RSVD RSVD

VIDALERT*

RSVD

VIDSOUT

VIDSCLK

VR_EN

VCCST_PWRGD

VR_READY

VCCIO_OUT

RSVD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE

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SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

114mA Max

Max load: 300mA

42mA Max

17mA Max

3mA Max

31mA Max

Powered in DeepSx

11mA Max

18mA Max

???mA Max

32A Max

1.4A Max (DDR3: 1.5-1.35V)

1.1A Max (LPDDR3: 1.2V)

213mA Max[1]3.3mA Max[1]

1mA Max[1]

40mA Max[1]

473mA Max[1]

185mA Max[1]

29mA Max[1]

0.3mA Max[1]

59mA Max[1]

41mA Max

WF: RSVD on Sawtooth Peak rev 1.0

1838mA Max

57mA Max

VCCCLK: 200mA Max

1499mA Max[1]

VCCCLK: 200mA Max

Max load: 300mA

R0802.2:

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

R0800.2:

R0810.2:

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0. Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.

2

1

R0802

PLACE_NEAR=U0500.L63:2.54mm

1/20W

1%

130

MF 201

51 67

16

2

1

R0860

1/20W

100

PLACE_NEAR=U0500.C50:50.8mm

MF

201

5%

51 67

16 17

17 51

51 67

2

1

C0899

BYPASS=R0899:U0500:2.54mm

402

CERM

1UF

10%

6.3V

21

R0899

1%

MF-LF

5.11

PLACE_NEAR=U0500.AG19:2.54mm

1/20W

201

51 67

2

1

C0895

0.1UF

CERM 402

10V

20%

BYPASS=U0500.AE7:6.35mm

2

1

C0892

402

CERM

10V

20%

0.1UF

BYPASS=U0500.AG10:6.35mm

2

1

C0891

BYPASS=U0500.AG10:6.35mm

0.1UF

402

CERM

10V

20%

2

1

C0890

BYPASS=U0500.AG10:6.35mm

1UF

402

CERM

6.3V

10%

B18

J15

AH11

AE21

AE20

AC9 AA9

Y8

U8 T9

B11

AG10

M9

L10

K9

AH14

AH10

T21

R21

K19

J18

J17

AG8

AG14 AG13

AF9

AE9

W21

AA21

A20

W9

V8

K16

K14

P9

N8

J11

H15

H11

AG17

AG16

AF22

AE8

Y20

V21

M20

K18

AC20

AG20

AG19

AB8

J13

AH13

AD8

AD10

AE7

U0500

BGA

CRITICAL

OMIT_TABLE

BROADWELL-ULT

2C+GT2

P62

D63

C59

F60

L63

N63

L62

AY50

AY44

AY40

AY35

AR48

AP43

AN33

AJ37

AJ33

AJ31

AH26

B59

AE23

AE22

AC22

E20

A59

W57

U57

E63

P57

M57

M23

L22

K57

K23

J23

H23

G57

G55

G53

G51

G49

G47

G45

G43

G41

G39

G37

G35

G33

G31

G29

G27

G25

G23

F56

F52

F48

F44

F40

F36

F32

F28

F24

E57

E55

E53

E51

E49

E47

E45

E43

E41

E39

E37

E35

E33

E31

E29

E27

E25

E23

C56

C52

C48

C44

C40

C36

C32

C28

C24

AG57

AD57

AB57

F59

V59

U59

P61

P60

N61

N59

T59

N58

L59 J58

AG58

AE60

AE59

AD60 AD59

AD23

AC59

AC58

AB23

AA59

AA23

H59

U0500

BGA

CRITICAL

OMIT_TABLE

2C+GT2

BROADWELL-ULT

21

R0811

MF

1/20W

0201

0

5%

21

R0812

MF

1/20W

0201

0

5%

21

R0810

201

1/20W

PLACE_NEAR=U0500.L62:38.1mm

43

5%

MF

2

1

R0800

PLACE_NEAR=R0810.1:2.54mm

75

1/20W

MF

1%

201

SYNC_MASTER=J43_MLB

SYNC_DATE=10/02/2012

CPU/PCH POWER

PPVCC_S0_CPU

PP1V05_S0

TP_CPU_RSVDN61

TP_CPU_RSVD_N59

TP_CPU_RSVDP61

TP_CPU_RSVD_P60

CPU_PWR_DEBUG

CPU_VCCSENSE_P

PPVCC_S0_CPU

PPVMEMIO_S0_CPU

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PPVCOMP_S0_CPU

CPU_VIDALERT_R_L

CPU_VIDSOUT_R

CPU_VIDSCLK_R

CPU_VR_EN

CPU_VCCST_PWRGD

CPU_VR_READY

TP_PPVCCIO_S0_CPU

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V05_S0SW_PCH_HSIO

PP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_S0SW_PCH_VCCSATA3PLL

PP1V05_S0_PCH_VCCAPLL_OPI

PP1V5_S0SW_AUDIO_HDA

PP3V3_S5

PP1V05_S0

PP1V05_S0_PCH_VCCACLKPLL

PPVRTC_G3H

PPVOUT_S0_PCH_DCPRTC

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP3V3_SUS

PP1V05_S0

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP_R

PP1V05_S0

PP1V5_S0

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP1V05_S0_PCH_VCC_ICC

PP3V3_SUS

PP1V05_S0

CPU_VIDSCLK

CPU_VIDALERT_L

CPU_VIDSOUT

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP

<SCH_NUM>

8 OF 121

8 OF 76

8

10 42 52 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

18

8

10 42 52 62 64

10 42

5

11 58 62

11 14

11 12

11

11 17 58

11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

6 8

11 15 16 17 38 42 51

55 58 59 62 64

11 12

12 13 17 62 64

8

11 14 18 46 57 58 59

62 64

6 8

11 15 16 17 38 42 51

55 58 59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

57 58 59 62 64

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51

55 58 59 62 64

8

11 12 13 15 17 18 26 30

36 38 39 40 41 42 43 44 45

56 59 61 62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

11

8

11 14 18 46 57 58 59 62

64

8

11 14 18 46 57 58 59 62

64

8

11 14 18 46 57 58 59 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

w w w . c h i n a f i x . c o m

OUT

SYM 14 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

SYM 15 OF 19

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS

SYM 16 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS_SENSE

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

2

1

R0960

201

MF

1/20W

100

5%

PLACE_NEAR=U0500.E62:50.8mm

51 67

AP20

AP17

AP10

AN7

AN63

AN60

AN52

AN51

AN49

AN48

AN46

AN45

AN43

AN42

AN40

AN39

AN36

AN35

AN32

AN31

AN23

AN17

AM52

AM31

AM23

AM17

AM1

AL61

AL60

AL57

AL54

AL52

AL51

AL46

AL45

AL40

AL39

AL36

AL33

AL31

AL29

AL26

AL23

AL22

AL20

AL17

AL13

AL10

AK52

AK3

AK23

AJ63

AJ60

AJ58

AJ56

AJ54

AJ52

AJ50

AJ47

AJ45

AJ43

AJ41

AJ39

AJ35

AJ29

AJ27

AJ25

AJ23

AJ14

AJ13

AH57

AH55

AH53

AH51

AH49

AH44

AH42

AH40

AH38

AH36

AH34

AH32

AH30

AH28

AH24

AH22

AH20

AH19

AH17

AG63

AG62

AG61

AG60

AG23

AG21

AG11

AG1

AF18

AF17

AF15

AF14

AF12

AF11

AE58

AE5

AE10

AD63

AD3

AD21

AC61

AB7

AB22

AB20

AB10

AA58

AA1

A56

A52

A48

A44

A40

A36

A32

A28

A24

A18

A14

A11

U0500

OMIT_TABLE

CRITICAL

BGA

2C+GT2

BROADWELL-ULT

D31

D30

D29

D27

D26

D25

D23

D21

D2

D18

D14

D12

C57

C39

C38

C27

C25

C20

C18

C14

C11

B60

B56

B52

B48

B44

B40

B4

B36

B32

B28

B26

B24

B20

AY6

AY59

AY57

AY53

AY51

AY4

AY33

AY30

AY26

AY24

AY22

AY18

AY16

AY11

AW60

AW59

AW51

AW50

AW47

AW44

AW42

AW40

AW4

AW37

AW35

AW33

AW24

AW16

AV8

AV59

AV55

AV51

AV49

AV46

AV43

AV41

AV39

AV36

AV34

AV33

AV28

AV24

AV20

AV16

AV14

AU59

AU57

AU55

AU53

AU51

AU33

AU30

AU28

AU26

AU24

AU22

AU20

AU18

AU16

AU1

AT63

AT62

AT61

AT49

AT46

AT43

AT42

AT40

AT37

AT35

AT13

AR52

AR5

AR49

AR43

AR39

AR33

AR31

AR23

AR17

AR15

AR11

AP57

AP54

AP52

AP48

AP39

AP38

AP31

AP3

AP29

AP26

AP23

AP22

U0500

BROADWELL-ULT

2C+GT2

CRITICAL

OMIT_TABLE

BGA

Y63

Y59

Y10

W22

W20

V7

V58

V3

V23

V10

U9

U61

U22

U20

T58

T1

E62

R8

R22

R10

P63

P59

N3

N10

M22

L7

L61

L58

L20

L18

L17

L15

L13

K12

K1

J63

J59

J22

J10

H57

H17

H13

G8

G6

G5

G3

G22

G18

F61

F58

F54

F50

F46

F42

F38

F34

F30

F26

F20

E17

E11

D8

D62

D59

D57

D55

D54

D53

D51

D50

D5

D49

D47

D46

D45

D43

D42

D41

D39

D38

D37

D35

D34

D33

AH46

AH16

U0500

BGA

CRITICAL

OMIT_TABLE

2C+GT2

BROADWELL-ULT

CPU/PCH GROUNDS

SYNC_MASTER=J43_MLB

SYNC_DATE=10/02/2012

CPU_VCCSENSE_N

9 OF 76

9 OF 121

<SCH_NUM>

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise

CPU VCC Decoupling

CPU VDDQ DECOUPLING

Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603

2x Bulk nostuff per Harris Beach v1.0 schematic

Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff

Apple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff

2

1

C1000

CRITICAL

4V X6S 0402

20%

10UF

2

1

C1050

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1051

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1052

CERM-X5R 0402-1

10UF

6.3V

20%

2

1

C1053

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1054

CERM-X5R

20%

0402-1

10UF

6.3V 2

1

C1055

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1040

6.3V CERM 402-LF

2.2UF

20%

2

1

C1041

402-LF

6.3V CERM

2.2UF

20%

2

1

C1042

6.3V CERM 402-LF

20%

2.2UF

2

1

C1043

6.3V

20%

2.2UF

402-LF

CERM

2

1

C1060

TANT

2V

20%

270UF

CASE-B2-SM

2

1

C1061

NO STUFF

CASE-B2-SM

TANT

2V

20%

270UF

2

1

C1001

CRITICAL

20% 4V X6S 0402

10UF

2

1

C1002

CRITICAL

4V X6S

10UF

20%

0402

2

1

C1003

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1004

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1005

NO STUFF

10UF

0402

4V X6S

20%

2

1

C1006

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1007

CRITICAL

10UF

0402

4V X6S

20%

2

1

C1008

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1009

NO STUFF

20%

0402

4V X6S

10UF

2

1

C1010

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1011

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1012

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1013

10UF

0402

4V X6S

20%

NO STUFF

2

1

C1014

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1015

4V X6S

20%

10UF

0402

NO STUFF

2

1

C1016

CRITICAL

4V

20%

0402

X6S

10UF

2

1

C1017

CRITICAL

20%

10UF

X6S

4V

0402

2

1

C1018

CRITICAL

4V

20%

0402

X6S

10UF

2

1

C1019

20% 4V X6S

10UF

0402

NO STUFF

2

1

C1020

20%

X6S

4V

10UF

0402

NO STUFF

2

1

C1021

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1084

CRITICAL

4V X6S

20%

10UF

0402

2

1

C1083

CRITICAL

4V X6S

20%

10UF

0402

2

1

C1082

4V X6S

20%

10UF

0402

NO STUFF

2

1

C1081

20%

0402

X6S

4V

10UF

NO STUFF

2

1

C1080

NO STUFF

4V X6S

10UF

20%

0402

2

1

C1079

4V X6S

20%

10UF

0402

NO STUFF

2

1

C1078

NO STUFF

10UF

20%

X6S

4V

0402

2

1

C1077

CRITICAL

20%

X6S

4V

10UF

0402

2

1

C1076

CRITICAL

4V X6S

10UF

20%

0402

2

1

C1075

NO STUFF

4V X6S

10UF

20%

0402

2

1

C1074

10UF

20% 4V X6S 0402

NO STUFF

2

1

C1073

NO STUFF

X6S

4V

20%

0402

10UF

2

1

C1072

10UF

X6S

4V

20%

0402

NO STUFF

2

1

C1071

NO STUFF

4V X6S

10UF

20%

0402

2

1

C1070

NO STUFF

20%

0402

10UF

X6S

4V

2

1

C1097

NO STUFF

0402

20%

10UF

X6S

4V

2

1

C1096

0402

4V X6S

20%

10UF

NO STUFF

2

1

C1095

0402

20%

10UF

X6S

4V

NO STUFF

2

1

C1094

0402

20%

10UF

X6S

4V

NO STUFF

2

1

C1093

10UF

0402

20%

X6S

4V

NO STUFF

2

1

C1092

NO STUFF

0402

10UF

20%

X6S

4V

2

1

C1091

NO STUFF

0402

4V

20%

X6S

10UF

2

1

C1090

NO STUFF

0402

20%

10UF

X6S

4V

2

1

C1089

CRITICAL

0402

20%

10UF

X6S

4V

2

1

C1088

CRITICAL

0402

20%

10UF

X6S

4V

2

1

C1087

NO STUFF

0402

20%

10UF

X6S

4V

2

1

C1086

NO STUFF

10UF

0402

20% 4V X6S

2

1

C1085

NO STUFF

10UF

0402

20%

X6S

4V

2

1

C1038

NO STUFF

0402

10UF

20% 4V X6S

2

1

C1037

NO STUFF

0402

4V X6S

10UF

20%

2

1

C1036

NO STUFF

4V

0402

X6S

20%

10UF

2

1

C1035

NO STUFF

0402

20%

10UF

4V X6S

2

1

C1034

NO STUFF

X6S 0402

20% 4V

10UF

2

1

C1033

NO STUFF

0402

20% 4V X6S

10UF

2

1

C1032

0402

10UF

20%

X6S

4V

NO STUFF

2

1

C1029

0402

20% 4V X6S

NO STUFF

10UF

2

1

C109A

0402

10UF

20% 4V X6S

NO STUFF

2

1

C1099

NO STUFF

0402

X6S

20%

10UF

4V

2

1

C1098

NO STUFF

0402

4V X6S

20%

10UF

2

1

C107B

NO STUFF

20%

X6S

4V

10UF

0402

2

1

C107A

4V

20%

10UF

X6S 0402

NO STUFF

2

1

C1069

NO STUFF

10UF

X6S

4V

20%

0402

2

1

C1068

NO STUFF

0402

X6S

4V

10UF

20%

2

1

C108F

NO STUFF

20% 4V X6S 0402

10UF

2

1

C1067

NO STUFF

0402

4V X6S

20%

10UF

2

1

C108E

NO STUFF

20% 4V X6S

10UF

0402

2

1

C1066

NO STUFF

0402

10UF

20% 4V X6S

2

1

C108D

NO STUFF

X6S

4V

20%

0402

10UF

2

1

C108C

NO STUFF

X6S

4V

20%

10UF

0402

2

1

C1065

NO STUFF

0402

10UF

4V

20%

X6S

2

1

C1028

NO STUFF

10UF

0402

4V X6S

20%

2

1

C1027

10UF

0402

4V X6S

20%

NO STUFF

2

1

C1049

0402

NO STUFF

4V

20%

X6S

10UF

2

1

C1048

0402

4V

20%

X6S

10UF

NO STUFF

2

1

C1026

10UF

4V X6S 0402

20%

NO STUFF

2

1

C1047

0402

X6S

10UF

4V

20%

NO STUFF

2

1

C1025

NO STUFF

10UF

20% 4V X6S 0402

2

1

C1024

NO STUFF

10UF

0402

4V X6S

20%

2

1

C1046

NO STUFF

0402

X6S

10UF

4V

20%

2

1

C1045

NO STUFF

0402

10UF

4V

20%

X6S

2

1

C1023

NO STUFF

0402

4V X6S

10UF

20%

2

1

C1022

NO STUFF

10UF

0402

20% 4V X6S

2

1

C1044

NO STUFF

0402

20%

X6S

4V

10UF

2

1

C1039

NO STUFF

0402

10UF

X6S

4V

20%

2

1

C1064

NO STUFF

X6S 0402

10UF

20% 4V

2

1

C108B

X6S

20% 4V

0402

10UF

NO STUFF

2

1

C1063

0402

X6S

4V

10UF

20%

NO STUFF

2

1

C108A

NO STUFF

20%

X6S

4V

10UF

0402

2

1

C1062

10UF

20% 4V X6S

NO STUFF

0402

2

1

C109F

NO STUFF

X6S

10UF

4V

20%

0402

2

1

C109E

NO STUFF

X6S

4V

20%

10UF

0402

2

1

C1059

NO STUFF

10UF

0402

20% 4V X6S

2

1

C1058

NO STUFF

0402

10UF

4V X6S

20%

2

1

C109D

NO STUFF

10UF

20% 4V X6S 0402

2

1

C1057

0402

20%

NO STUFF

4V X6S

10UF

2

1

C109C

NO STUFF

X6S

10UF

20% 4V

0402

2

1

C1056

NO STUFF

0402

10UF

4V X6S

20%

2

1

C109B

NO STUFF

X6S

4V

0402

10UF

20%

3 2

1

C1031

CRITICAL

470UF-0.0045OHM

SM

2.5V POLY-TANT

20%

2

1

C1030

0402

4V X6S

10UF

20%

NO STUFF

2

1

C104C

NO STUFF

10UF

0402

4V X6S

20%

2

1

C104D

4V

NO STUFF

20%

X6S

10UF

0402

2

1

C104E

20%

10UF

X6S

4V

0402

NO STUFF

2

1

C104F

NO STUFF

20%

10UF

X6S

4V

0402

2

1

C106A

NO STUFF

20%

10UF

X6S

4V

0402

2

1

C106B

20%

10UF

X6S

4V

0402

NO STUFF

2

1

C106C

20%

10UF

X6S

4V

0402

NO STUFF

2

1

C106D

0402

4V X6S

10UF

20%

NO STUFF

2

1

C106E

0402

4V X6S

10UF

20%

NO STUFF

2

1

C105A

NO STUFF

20%

10UF

X6S

4V

0402

2

1

C105B

NO STUFF

20%

10UF

X6S

4V

0402

2

1

C105C

NO STUFF

4V

20%

10UF

X6S 0402

2

1

C105D

20%

10UF

X6S

4V

0402

NO STUFF

2

1

C105E

0402

4V X6S

10UF

20%

NO STUFF

2

1

C105F

NO STUFF

0402

4V X6S

10UF

20%

2

1

C104A

NO STUFF

10UF

0402

4V X6S

20%

2

1

C104B

NO STUFF

0402

4V X6S

10UF

20%

SYNC_DATE=01/08/2013SYNC_MASTER=WILL_J43

CPU Decoupling

PPVCC_S0_CPU

PPVMEMIO_S0_CPU

10 OF 121

<SCH_NUM>

10 OF 76

8

42 52 62 64

8

42

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

??mA Max

PCH OPI VCCAPLL FILTER/BYPASS

57mA Max

31mA Max

??mA Max

42mA Max83mA Max

41mA Max

PCH VCCDSW3_3 BYPASS

PCH VCCSUS3_3 BYPASS

(PCH 1.05V PCIe/SATA/USB3 PWR)

PCH VCCHSIO BYPASS

PCH VCCASW BYPASS (PCH 1.05V ME CORE PWR)

(PCH 1.05V OPI PLL PWR)

(PCH 1.05V CLK PWR)

PCH VCCCLK BYPASS

PCH VCC3_3 BYPASS (PCH 3.3V GPIO/LPC PWR)

PCH VCC3_3 BYPASS (PCH 3.3V THERMAL PWR)

(PCH 1.05V USB2 PWR)

PCH VCCIO BYPASS

(PCH 1.05V VCCCLK PWR)

PCH VCCCLK FILTER/BYPASS

PCH VCCACLKPLL FILTER/BYPASS (PCH 1.05V ACLK PLL PWR)

(PCH 3.3V DSW PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

PCH VCCSPI BYPASS (PCH 3.3V SPI PWR)

(PCH 3.3V SUSPEND RTC PWR)

(PCH 3.3V/1.5V HDA PWR)

PCH VCCSDIO BYPASS (PCH 3.3V/1.8V SDIO PWR)

PCH VCCSUSHDA BYPASS

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0 as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

PCH VCCSATA3PLL FILTER/BYPASS

(PCH 1.05V USB3 PLL PWR)

PCH VCCUSB3PLL FILTER/BYPASS

(PCH 1.05V SATA3 PLL PWR)

PCH VCC BYPASS (PCH 1.05V CORE PWR)

2

1

C1202

BYPASS=U0500.Y8:6.35mm

CERM

402

0.1UF

20% 10V

NO STUFF

21

L1280

0603

2.2UH-240MA-0.221OHM

CRITICAL NO STUFF

21

R1280

0

MF-LF

402

5%

1/16W

2

1

C1295

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.B18:12.7mm

2

1

C1296

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.B18:12.7mm

NO STUFF

2

1

C1290

BYPASS=U0500.B11:12.7mm

CERM-X5R

4V

20%

47UF

0805-1

2

1

C1291

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.B11:12.7mm

NO STUFF

2

1

C1280

BYPASS=U0500.AA21:12.7mm

0805-1

47UF

20%

4V

CERM-X5R

NO STUFF

2

1

C1281

CERM-X5R

4V

20%

47UF

BYPASS=U0500.AA21:12.7mm

0805-1

NO STUFF

2

1

C1275

BYPASS=U0500.J18:12.7mm

4V

20%

47UF

0805-1

CERM-X5R

2

1

C1276

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.J18:12.7mm

2

1

C1270

CERM-X5R

BYPASS=U0500.A20:12.7mm

0805-1

47UF

20%

4V

2

1

C1271

CERM-X5R

4V

20%

47UF

0805-1

BYPASS=U0500.A20:12.7mm

2

1

C1200

6.3V

10%

402

CERM

1UF

BYPASS=U0500.AH10:6.35mm

NO STUFF

2

1

C1210

BYPASS=U0500.AH14:6.35mm

6.3V

10%

1UF

CERM

402

2

1

C1214

BYPASS=U0500.K14:6.35mm

CERM

402

10V

20%

0.1UF

2

1

C1206

BYPASS=U0500.AH11:6.35mm

402

CERM

6.3V

1UF

10%

2

1

C1264

402

CERM

BYPASS=U0500.AG16:6.35mm

1UF

10%

6.3V

2

1

C1261

1UF

CERM

402

10%

6.3V

BYPASS=U0500.L10:6.35mm

2

1

C1262

0402-1

20%

10UF

CERM-X5R

BYPASS=U0500.M9:6.35mm

6.3V

2

1

C1266

6.3V CERM

402

1UF

10%

BYPASS=U0500.J17:6.35mm

2

1

C1255

BYPASS=U0500.J11:12.7mm

6.3V

20%

603

X5R

10UF

2

1

C1250

BYPASS=U0500.AE9:12.7mm

X5R-CERM-1

6.3V

20%

22UF

603

NO STUFF

2

1

C1256

BYPASS=U0500.J11:6.35mm

6.3V 402

10%

1UF

CERM

2

1

C1257

1UF

BYPASS=U0500.AE8:6.35mm

6.3V

10%

402

CERM

2

1

C1251

BYPASS=U0500.AE9:6.35mm

6.3V

10%

402

CERM

1UF

2

1

C1267

6.3V CERM

402

1UF

10%

BYPASS=U0500.R21:6.35mm

2

1

C1204

X5R-CERM-1

6.3V

20%

22UF

603

BYPASS=U0500.AC9:12.7mm

2

1

C1212

22UF

20%

6.3V

X5R-CERM-1

BYPASS=U0500.V8:12.7mm

603

2

1

C1208

BYPASS=U0500.U8:6.35mm

402

CERM

6.3V

1UF

10%

2

1

C1260

BYPASS=U0500.K9:6.35mm

1UF

402

10%

6.3V CERM

2

1

C1277

10V

10%

402

X5R

1UF

BYPASS=U0500.J18:6.35mm

21

L1275

2.2UH-240MA-0.221OHM

0603

CRITICAL

2

1

C1297

10V

10%

402

X5R

1UF

BYPASS=U0500.B18:6.35mm

21

L1295

CRITICAL

0603

2.2UH-240MA-0.221OHM

2

1

C1292

10V

10%

402

X5R

1UF

BYPASS=U0500.B11:6.35mm

21

L1290

2.2UH-240MA-0.221OHM

CRITICAL

0603

21

R1275

0

1/16W

5%

402

MF-LF

2

1

C1272

1UF

X5R 402

10% 10V

BYPASS=U0500.A20:6.35mm

21

L1270

0603

CRITICAL

2.2UH-240MA-0.221OHM

21

R1270

5%

402

MF-LF

1/16W

0

2

1

C1282

1UF

X5R 402

10% 10V

BYPASS=U0500.AA21:6.35mm

SYNC_DATE=02/07/2013

SYNC_MASTER=J41_MLB

PCH Decoupling

PP1V05_S0

PP3V3_SUS

PP3V3_S0

PP1V5_S0SW_AUDIO_HDA

PP3V3_S5

PP3V3_SUS

PP1V05_S0

PP3V3_S0

PP1V05_S0

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCACLKPLL_R

PP1V05_S0

PP1V05_S0SW_PCH_HSIO

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_S0

PP1V05_S0SW_PCH_HSIO

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0SW_PCH_VCCSATA3PLL

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC_R

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCACLKPLL

MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCAPLL_OPI

<SCH_NUM>

12 OF 121

11 OF 76

6 8

11 15 16 17 38 42 51 55

58 59 62 64

8

11 14 18 46 57 58 59 62 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8

17 58

8

13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

6 8

11 15 16 17 38 42 51 55

58 59 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

8

11 58 62

8

14

6 8

11 15 16 17 38 42 51 55

58 59 62 64

8

11 58 62

8

12

8

12

8

w w w . c h i n a f i x . c o m

IN IN

IN

OUT

BI

AUDIO

SYM 5 OF 19

SATA

JTAG

RTC

RSVD

HDA_DOCK_EN*/I2S1_TXD

HDA_BCLK/I2S0_SCLK

RTCX1 RTCX2

RTCRST*

INTVRMEN

INTRUDER*

SRTCRST*

HDA_RST*/I2S_MCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

PCH_TRST*

PCH_TDI

PCH_TCK

PCH_TDO

RSVD

PCH_TMS

JTAGX

RSVD

RSVD SATALED*

SATA_RCOMP

SYM 6 OF 19

CLOCK SIGNALS

CLKOUT_LPC_1

CLKOUT_LPC_0

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

PCIECLKRQ5*/GPIO23

PCIECLKRQ4*/GPIO22

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

PCIECLKRQ3*/GPIO21

CLKOUT_PCIE_P4

CLKOUT_PCIE_N4

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

CLKOUT_PCIE_N0

XTAL24_OUT

XTAL24_IN

CLKOUT_PCIE_P0

TESTLOW

TESTLOW TESTLOW

DIFFCLK_BIASREF

RSVD

OUT

IN

OUT

IN

OUT

OUT OUT

IN

OUT OUT

IN

OUT

IN

NC NC

NC

IN

OUT

IN

OUT

IN

NC NC

OUT OUT

IN IN

OUT

NC NC

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD-PLTRST#)

SSD Lane 1

SATA Port assignments:

Reserved: ODD

Primary HDD/SSD

Unused

Secondary HDD/SSD

(IPD)

(IPU)

(IPD-PLTRST#)

(IPD-PWROK)

SSD Lane 3

PCIe Port assignments:

SSD Lane 2

SSD Lane 0

(IPD)

16 64 69

21

R1345

MF

201

5%

1/20W

100K

21

R1375

201

1/20W

5% MF

100K

16

12 16

15 16

21

R1343

1/20W

MF

201

5%

100K

16 64 69

16

AV6

U3

D17

C15

B17

A15

C17

B14

A17

B15

E5

H6

H8

H5

F5

J6

J8

J5

C12

A12

AC1

V6

U1

V1

AY5

AW5

AU7

L11

K10

AV2

AL11

AC4

AU62

AD62

AE61

AD61

AE62

AE63

AV7

AU6

AY8

AV11

AU11

AU12

AY10

AU8

AV10

AW10

AW8

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

B25

A25

C35 C34

AL8

AK8

M21

K21

T2

U5

N1

AD1

Y5

U2

C26

A37

B39

C37

B42

A41

C42

B37

A39

B38

C41

B41

C43

AP15

AN15

A35

B35

U0500

2C+GT2

BROADWELL-ULT

BGA

OMIT_TABLE

CRITICAL

25 69

12 25

29 64 69

12 29

29 64 69

32 69

12 31

30 64 67

12 30

21

R1376

100K

MF5%

1/20W

201

61 65 69

21

R1377

201

1/20W

5% MF

100K

61 65 69

21

R1312

PLACE_NEAR=U0500.AU8:1.27mm

1/20W

5% MF33201

21

R1311

201

PLACE_NEAR=U0500.AV11:1.27mm

MF5%

1/20W

33

61 65 69

21

R1310

PLACE_NEAR=U0500.AW8:1.27mm

1/20W

5%

201

MF

33

17

2

1

R1302

MF

201

5%

1/20W

330K

2

1

R1301

1M

MF 201

5% 1/20W

2

1

C1300

10V

10%

402

X5R

1UF

2

1

R1300

1/20W

5%

201

MF

20K

2

1

C1303

10V

10%

1UF

402

X5R

2

1

R1303

5%

201

20K

1/20W MF

6

16 64 67

2

1

R1370

PLACE_NEAR=U0500.C12:2.54mm

1% 1/20W

3.01K

MF 201

30 67

30 64 67

30 67

30 64 67

30 67

30 64 67

61 65 69

2

1

R1380

1/20W

PLACE_NEAR=U0500.C26:2.54mm

1%

201

MF

3.01K

17 69

21

R1390

10K

MF

1/20W

5%

201

21

R1391

MF

201

1/20W

10K

5%

21

R1392

201

MF

1/20W

10K

5%

21

R1393

5%

10K

1/20W

MF

201

17

21

R1313

201

PLACE_NEAR=U0500.AU11:1.27mm

33

1/20W

5% MF

21

R1341

1/20W

5%

201

MF

100K

21

R1344

100K

MF

201

5%

1/20W

21

R1340

1/20W

5%

201

MF

100K

21

R1342

5% MF

201

1/20W

100K

PCH Audio/JTAG/SATA/CLK

SYNC_DATE=12/17/2012SYNC_MASTER=WILL_J43

SSD_CLKREQ_L

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

NC_PCIE_CLK100M_FWN NC_PCIE_CLK100M_FWP

FW_CLKREQ_L

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

AP_CLKREQ_L

PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_P

CAMERA_CLKREQ_L

TP_PCIE_CLK100M_ENETSDP

TP_PCIE_CLK100M_ENETSDN

ENETSD_CLKREQ_L

TP_LPC_CLK24M_LPCPLUS_R

LPC_CLK24M_SMC_R

TP_ITPXDP_CLK100MN TP_ITPXDP_CLK100MP

PCH_CLK24M_XTALOUT

PCH_CLK24M_XTALIN

PCH_TESTLOW_C34

PCH_TESTLOW_C35

PCH_TESTLOW_AK8 PCH_TESTLOW_AL8

PCH_DIFFCLK_BIASREF

TP_PCH_I2S1_TXD

HDA_BIT_CLK_R

PCH_CLK32K_RTCX1 NC_RTC_CLK32K_RTCX2

RTC_RESET_L

PCH_INTVRMEN

PCH_INTRUDER_L

PCH_SRTCRST_L

HDA_RST_R_L

HDA_SYNC_R

HDA_SDIN0 NC_HDA_SDIN1

HDA_SDOUT_R

TP_PCH_I2S1_SFRM

TP_PCH_I2S1_SCLK

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_C_P<0>

XDP_SSD_PCIE0_SEL_L

PP1V05_S0SW_PCH_VCCSATA3PLL

XDP_CPUPCH_TRST_L

XDP_PCH_TDI

XDP_PCH_TCK

XDP_PCH_TDO

XDP_PCH_TMS

PCH_JTAGX

PCH_SATALED_L

PCH_SATA_RCOMP

HDA_RST_L

HDA_SDOUT

HDA_BIT_CLK

HDA_SYNC

PPVRTC_G3H

PP1V05_S0_PCH_VCCACLKPLL

ENETSD_CLKREQ_L CAMERA_CLKREQ_L

FW_CLKREQ_L

AP_CLKREQ_L

TBT_CLKREQ_L SSD_CLKREQ_L

XDP_FW_PME_L XDP_PCH_GPIO35

PCH_SATALED_L

PP3V3_S0

XDP_PCH_UART_SSD_L_BT_H

XDP_PCH_GPIO35

XDP_PCH_UART_SSD_L_BT_H

13 OF 121

<SCH_NUM>

12 OF 76

64

12

69

64

17 69

8

11

12

8

13 17 62 64

8

11

12

12 31

12

12 29

12 25

12 30

12

8

11 13 15 17 18 26 30 36 38 39

40 41 42 43 44 45 56 59 61 62

64 65 74

12 16

w w w . c h i n a f i x . c o m

IN

OUT

IN

OUT

SYSTEM POWER MANAGEMENT

SYM 8 OF 19

SLP_WLAN*/GPIO29

SLP_S0*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

PCH_PWROK

APWROK

SYS_RESET*

SUSACK*

PLTRST*

SYS_PWROK

DPWROK

DSWVRMEN

CLKRUN*/GPIO32

WAKE*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

SIDEBAND

eDP

DISPLAY

PCI

SYM 9 OF 19

GPIO53

GPIO51

GPIO54

GPIO52

GPIO55

PME*

PIRQC*/GPIO79 PIRQD*/GPIO80

PIRQA*/GPIO77 PIRQB*/GPIO78

EDP_BKLEN

EDP_BKLCTL

EDP_HPD

DDPC_HPD

DDPC_AUXP

DDPB_AUXP

DDPB_HPD

DDPB_AUXN DDPC_AUXN

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

EDP_VDDEN

OUT

IN

OUT

BI

IN

OUT

BI BI

BI

OUT

IN

IN IN IN

OUT OUT OUT

OUT

IN

OUT

IN

NC

08

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R1400 kept for debug purposes.

(IPU)

(IPD-PLTRST#)

(IPD-DeepSx)

(IPU)

(IPD-PLTRST#)

U1420 ensures signal will only be high in S0.

SLP_S0# can be driven high outside of S0

SLP_S0# Isolation

59 64

13 18 37

39

AJ5

AC3

AG2

AV4

AE6

AK2

AG4

AM5

AP4

AP5

AJ6

AT4

AF3 AJ7

AL5

AW6

AL7

AG7

AY7

AW7

AV5

V5

AN4

AB5

AJ8

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

AD4

N2

N4

P4

U6

U7

L3

L4

L1

R5

C6

D6

A9

B8

A8

D11

D9

A6

B6

C8

C9

B9

B5

C5

U0500

BGA

CRITICAL

OMIT_TABLE

BROADWELL-ULT

2C+GT2

13 30

15 16 18

21

R1441

100K

MF

1/20W

201

5%

13 17

16 17 37

17 37 64

13 42 59

13 17 18 37 59

13 18 29 36 37 59

13 37 59

38 69

37 64

13 37 64

13 29 31 64

2

1

R1451

5%

201

1/20W MF

100K

37

2

1

R1450

5%

201

1/20W MF

330K

13 56

56

13 60

25 67

18 25 67

25 67

18 28

18

18 28

25

18 25

60

21

R1446

5%

201

1/20W

MF

100K

21

R1445

5%

201

1/20W

MF

100K

21

R1442

5%

201

1/20W

MF

100K

21

R1443

5%

201

1/20W

MF

100K

2

1

R1400

5%

0

0201

1/20W

MF

NO STUFF

21

R1440

100K

MF

1/20W

201

5%

13 26

13 37

13 64

13 27 37

21

R1455

5%

201

1/20W

MF

10K

21

R1410

5%

201

1/20W

MF

10K

21

R1447

5%

201

1/20W

MF

100K

21

R1448

5%

201

1/20W

MF

100K

21

R1449

5%

201

1/20W

MF

100K

21

R1431

5%

201

1/20W

MF

100K

21

R1430

5%

201

1/20W

MF

100K

37 38

13 59 61 65

21

R1405

5%

201

1/20W

MF

1K

21

R1452

5%

201

1/20W

MF

10K

21

R1460

5%

201

1/20W

MF

100K

21

R1461

5%

201

1/20W

MF

100K

21

R1462

5%

201

1/20W

MF

100K

21

R1464

5%

201

1/20W

MF

100K

21

R1463

5%

201

1/20W

MF

100K

13 16 37

4

6

53

1

2

U1420

CRITICAL

74LVC1G08

SOT891

2

1

C1420

0201

X5R-CERM

10% 10V

0.1UF

PCH PM/PCI/GFX

SYNC_DATE=02/20/2013

SYNC_MASTER=J43_MLB

PP3V3_S0

SMC_RUNTIME_SCI_L

AP_PCIE_DEV_WAKE

SSD_BOOT

AUD_PWR_EN

ENET_LOW_PWR

HDMITBTMUX_LATCH

ODD_PWR_EN_L

NC_PCI_PME_L

TBT_PWR_REQ_L SMC_RUNTIME_SCI_L

EDP_BKLT_EN

EDP_BKLT_PWM

DP_INT_HPD

DP_TBTSNK1_HPD

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_HPD

DP_TBTSNK0_AUXCH_C_N DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

EDP_PANEL_PWR

TP_PCH_SLP_WLAN_L

PCH_PM_SLP_S0_L

PM_BATLOW_L

SMC_ADAPTER_EN

PM_PWRBTN_L

PCH_SUSWARN_L

PM_RSMRST_L

PM_PCH_PWROK

PM_SYSRST_L

PCH_SUSACK_L

PLT_RESET_L

PM_PCH_SYS_PWROK

PM_DSW_PWRGD

PCH_DSWVRMEN

PM_CLKRUN_L

PCIE_WAKE_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PM_SLP_S4_L

PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

TP_PCH_SLP_LAN_L

PM_SLP_SUS_L

EDP_BKLT_EN EDP_PANEL_PWR

HDMITBTMUX_FLAG

PM_SLP_S0_L

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S0_L

PP3V3_S0

PM_BATLOW_L

PM_PWRBTN_L

PP3V3_S5

AUD_PWR_EN AP_PCIE_DEV_WAKE

ENET_LOW_PWR

HDMITBTMUX_LATCH

ODD_PWR_EN_L

SSD_BOOT

TBT_PWR_REQ_L

PM_SLP_S5_L

PM_CLKRUN_L

PCIE_WAKE_L

PPVRTC_G3H

HDMITBTMUX_FLAG

14 OF 121

<SCH_NUM>

13 OF 76

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

13 37

64

13 42 59

13 56

13 60

13 64

13 18 37

13 17 18 37 59

13 18 29 36 37 59

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

13 27 37

13 16 37

8

11 15 16 17 18 28 29 34 42 57

58 59 60 62 64 74

13 59 61 65

13 64

13 30

13 26

13 37 59

13 37 64

13 29 31 64

8

12 17 62 64

w w w . c h i n a f i x . c o m

OUT

IN IN IN

OUT

IN

OUT

USB

PCI-E

SYM 11 OF 19

PCIE_RCOMP PCIE_IREF

RSVD

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP5_L3

PETN5_L3

PETP5_L2

PETN5_L2

PERP5_L2

PERN5_L2

PETP5_L1

PETN5_L1

PERP5_L1

PERN5_L1

USB2P7

USB2N7

PERP5_L3

PERN5_L3

PETP5_L0

PETN5_L0

PERP5_L0

PERN5_L0

OC1*/GPIO41

OC0*/GPIO40

OC2*/GPIO42 OC3*/GPIO43

RSVD RSVD

USBRBIAS*

USBRBIAS

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

PERN1/USB3RN3

PERN2/USB3RN4

PERP1/USB3RP3

PERP2/USB3RP4

PETN1/USB3TN3

PETN2/USB3TN4

PETP1/USB3TP3

PETP2/USB3TP4

USB3RN1

USB3RN2

USB3RP1

USB3RP2

USB3TN1

USB3TN2

USB3TP1

USB3TP2

SYM 7 OF 19

LPC

SMBUS

SPI

C-LINK

SPI_IO3

SPI_MISO

SPI_IO2

SPI_CS2*

SPI_MOSI

SPI_CS0*

SPI_CS1*

LFRAME*

LAD2 LAD3

LAD1

SPI_CLK

LAD0

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1ALERT*/PCHHOT*/GPIO73

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST*

IN IN

OUT OUT

IN IN

OUT OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

NC NC

BI

IN

BI

OUT

BI

OUT

BI BI

BI

OUT

IN

BI

OUT

BI

OUT

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

Otherwise, 100k pull-up to 3.3V SUS required.

Ext A (SS)

SD Card Reader

(IPD)

Reserved: Camera

Trackpad

(IPU)

(IPU/IPD)

(IPU)

(IPU/IPD)

Reserved: SD (HS)

IR

BT

Ext B (LS/FS/HS)

Ext A (LS/FS/HS)

USB Port Assignments:

Ext B (SS)

Camera

AirPort

Reserved: FireWire

Thunderbolt lane 0

USB3 Port Assignments:

PCIe Port Assignments:

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

(& Ethernet if combo)

Unused

SML1ALERT# pull-up not provided on this page, may be wire-ORed into other signals.

25 69

21

R1580

201

1/20W

MF5%

100K

21

R1581

201

MF

1/20W

5%

100K

14 16 35

14 16 61 65

14 16

18 39

14 16

25 69

14 64

AJ10 AJ11

A33

B34

B33

C33

F18

H20

E18

G20

AP13

AN11

AN13

AL15

AT10

AP8

AT7

AM8

AR13

AP11

AM13

AM15

AR10

AR8

AR7

AN8

E15 E13

AN10 AM10

A21

C21

A23

C22

A29

B30

A31

C31

B22

B21

B23

C23

B29

C29

B31

C30

F6

G10

E8

E10

G13

F11

G15

F17

E6

H10

F8

F10

F13

G11

F15

G17

A27 B27 AV3

AH2

AT1

AL3

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

AA2

AA4

AF1

Y6

AC2

Y4

Y7

AA3

AH3

AU3

AU4

AK1

AN1

AL2

AH1

AP2

AN2

AV12

AW11

AY12

AW12

AU14

AF4

AD2

AF2

U0500

2C+GT2

BROADWELL-ULT

BGA

OMIT_TABLE

CRITICAL

25 69

34 65 68

32 69

29 69

29 64 69

2

1

R1500

1/20W

PLACE_NEAR=U0500.A27:2.54mm

1%

MF

201

3.01K

61 65 68

35 68

25 69

35 68

2

1

R1570

PLACE_NEAR=U0500.AJ10:2.54mm

MF

1/20W

1%

201

22.6

36 64 68

64

25 69

64

29 68

61 65 68

25 69

35 68

37 64 69

21

R1543

33

MF

201

5%

1/20W

21

R1542

33

5% MF

1/20W

201

25 69

21

R1544

1/20W

5%

201

MF

33

21

R1540

33

MF

201

1/20W

5%

21

R1541

33

MF

201

5%

1/20W

46 69

32 37 40 43 44 64 69 73

25 69

32 37 40 43 44 64 69 73

40 69

16 19 40 56 69

46 69

25 69

14 46 69

21

R1591

100K

5% MF

1/20W

201

21

R1549

201

1/20W

MF5%

1K

21

R1590

201

MF

1/20W

5%

100K

21

R1548

201

1/20W

MF5%

1K

21

R1582

201

MF

1/20W

5%

100K

21

R1583

1/20W

5% MF

201

100K

PCH PCIe/USB/LPC/SPI/SMBus

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

LPC_FRAME_L

LPC_AD<3>

LPC_AD<1>

LPC_AD<0>

LPC_AD<2>

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L

WOL_EN

SPI_IO<3>

PCH_SMBALERT_L

SPI_IO<2>

XDP_USB_EXTD_OC_L

PP3V3_SUS PP3V3_SUS

USB3_EXTB_R2D_C_P

USB3_EXTA_R2D_C_P

USB3_EXTB_R2D_C_N

USB3_EXTA_R2D_C_N

USB3_EXTB_D2R_P

USB3_EXTA_D2R_P

USB3_EXTB_D2R_N

USB3_EXTA_D2R_N

PCIE_CAMERA_R2D_C_P

USB3_SD_R2D_C_P

PCIE_CAMERA_R2D_C_N

USB3_SD_R2D_C_N

PCIE_CAMERA_D2R_P

USB3_SD_D2R_P

PCIE_CAMERA_D2R_N

USB3_SD_D2R_N

NC_USB_CAMERAP

NC_USB_CAMERAN

TP_USB_5P

TP_USB_5N

USB_TPAD_P

USB_TPAD_N

NC_USB_IRP

NC_USB_IRN

USB_BT_P

USB_BT_N

USB_EXTB_P

USB_EXTB_N

USB_EXTA_P

USB_EXTA_N

PCH_USB_RBIAS

XDP_USB_EXTD_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L

PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<3> PCIE_TBT_D2R_P<3>

NC_USB_SDN NC_USB_SDP

PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1> PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_P<2>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<3> PCIE_TBT_R2D_C_P<3>

PCIE_AP_D2R_N PCIE_AP_D2R_P

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

NC_PCIE_FW_D2RN NC_PCIE_FW_D2RP

NC_PCIE_FW_R2D_CN NC_PCIE_FW_R2D_CP

PP1V05_S0SW_PCH_VCCUSB3PLL

PCH_PCIE_RCOMP

NC_CLINK_RESET_L

NC_CLINK_DATA

NC_CLINK_CLK

SMBUS_SMC_1_S0_SDA

PCH_SML1ALERT_L

SMBUS_SMC_1_S0_SCL

SML_PCH_0_DATA

SML_PCH_0_CLK

WOL_EN

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PCH_SMBALERT_L

LPC_AD_R<0>

SPI_CLK_R

LPC_AD_R<1>

LPC_AD_R<3>

LPC_AD_R<2>

LPC_FRAME_R_L

TP_SPI_CS1_L

SPI_CS0_R_L

SPI_MOSI_R

TP_SPI_CS2_L

SPI_IO<2>

SPI_MISO

SPI_IO<3>

<SCH_NUM>

15 OF 121

14 OF 76

14 16 35

14 16 61 65

14 16

14 64

14 46 69

14

14 46 69

14 16

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

64

68

64

8

11

64

14

w w w . c h i n a f i x . c o m

IN

OUT

BI

LPIO

GPIO

CPU/MISC

SYM 10 OF 19

SPKR/GPIO81

GPIO10

GPIO9

GPIO46

GPIO45

GPIO14

GPIO25

GPIO13

HSIOPC/GPIO71

GPIO50

GPIO49

GPIO48

GPIO44

GPIO47

GPIO59

GPIO58

GPIO57

GPIO56

GPIO26

GPIO27

GPIO28

GPIO24

GPIO16

GPIO17

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

BMBUSY*/GPIO76

SDIO_D3/GPIO69

SDIO_D2/GPIO68

SDIO_D1/GPIO67

I2C0_SDA/GPIO4

UART1_TXD/GPIO1

UART1_CTS*/GPIO3

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

GSPI0_MOSI/GPIO86

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85

GSPI0_CS*/GPIO83

RSVD RSVD

PCH_OPI_COMP

RCIN*/GPIO82

SERIRQ

GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART1_RST*/GPIO2

I2C1_SDA/GPIO6

I2C0_SCL/GPIO5

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66

SDIO_POWER_EN/GPIO70

DEVSLP0/GPIO33

DEVSLP1/GPIO38

DEVSLP2/GPIO39

THERMTRIP*

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

NC

OUT

NC

OUT

BI

OUT

IN

OUT

IN

OUT

IN

BI

IN

OUT

BI

OUT

IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SSD_LPSR:S0 BOM option is on R1620

Stuffed R1632

Pull-up on TBT page

TBTLC for CR, S0 for RR

(IPD)

(IPD-RSMRST#)

(IPD-DeepSx)

Requires connection to SMC via 1K series R

(IPD-PLTRST#)

Pull-up/down on chipset support page (depends on TBT controller) Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down. Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

GPIO12:

(IPD-PLTRST#)

platform does not use SD card

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

R1616 should also be stuffed if

No-Stuffed R1634

21

R1652

1/20W

5%

201

MF

10K

21

R1674

MF

201

5%

1/20W

100K

21

R1676

MF

201

5%

1/20W

100K

2

1

R1639

100K

201

MF

1/20W

5%

21

R1641

5% MF1K201

1/20W

21

R1629

5%

1/20W

MF

100K

201

2

1

R1621

201

MF

5%

100K

1/20W

13 15 16 18

18 25

15 37 64

G2

K4

J3

J4

K3

J1

J2

G1

D60

V2

T4

C4

E2

C3

E4

D3

F4

E3

AF20 AB21

V4

AW15

AM7

G4

F1

F2

F3

Y2

K2

N7

R7

L5

L8

N6

R6

L6

AM3

AU2

AT5

AL4

AP1

AG6

P3

Y3

U4

AB6

AG3

AG5

AK4

AD7

AN5

AN3

AM4

AD5

T3

Y1

AD6

AH4

AT3

AM2

N5

L2

P2

P1

U0500

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2

1

R1631

RAMCFG3:H

1/20W

5%

201

MF

100K

15 29

29

2

1

R1671

MF

1/20W

100K

5%

201

13 15 16 18

2

1

R1680

100K

201

MF

1/20W

5%

18 31

2

1

R1681

0201

MF

1/20W

5%

0

2

1

R1682

0

5% 1/20W MF 0201

15 36

21

R1668

MF

201

5%

1/20W

47K

2

1

R1636

1/20W

5%

201

MF

100K

RAMCFG2:H

21

R1669

47K

1/20W

5%

201

MF

21

R1670

MF

201

5%

1/20W

47K

21

R1677

47K

1/20W

5%

201

MF

21

R1672

MF

201

5%

1/20W

47K

21

R1673

47K

1/20W

5%

201

MF

21

R1675

MF

201

5%

1/20W

47K

15 18

15

21

R1678

201

1/20W

5%

2.2K

MF

21

R1679

MF

2.2K

5%

1/20W

201

2

1

R1635

100K

1/20W

MF

201

5%

RAMCFG1:H

15 18 19 33 36 40 41 58 62 64

2

1

R1696

201

MF

5%

100K

1/20W

SSD_LPSR:S3

2

1

R1611

5%

201

MF

1/20W

100K

RAMCFG0:H

26

15 64

39

15 16

15 16 18

15 16 64

15 36

18

15 30 58 59 64

15 64

15 34

15 25

15 16 18 25

15 18

15 58

15 46 64

15 18

15 30 64

15 29

30

15 37

15 34

15

38 67

15 16

15 16 18

18 25

15 36

15 16 33

15 36

15 36 68

2

1

R1650

201

MF

1/20W

1K

5%

15 36 68

21

R1610

100K

1/20W

5% MF

201

21

R1614

100K

5%

201

1/20W

MF

21

R1615

100K

1/20W

201

MF5%

21

R1616

SD_ON_MLB

1/20W

MF

201

5%

100K

21

R1617

201

MF5%

1/20W

100K

21

R1618

MF

201

5%

1/20W

100K

21

R1619

5% MF

1/20W

100K

201

21

R1620

SSD_LPSR:S0

MF5%

100K

201

1/20W

21

R1622

MF

201

1/20W

5%

100K

21

R1623

MF

100K

1/20W

5%

201

21

R1624

100K

5%

1/20W

201

MF

21

R1625

201

100K

1/20W

5% MF

21

R1626

1/20W

5%

100K

201

MF

21

R1627

MF

201

100K

1/20W

5%

21

R1628

100K

5% MF

201

1/20W

21

R1630

100K

1/20W

5%

201

MF

21

R1632

MF

201

5%

1/20W

100K

21

R1633

1/20W

5%

201

MF

100K

21

R1634

NOSTUFF

MF

201

5%

1/20W

100K

21

R1640

MF

201

5%

1/20W

100K

21

R1637

100K

5%

201

MF

1/20W

21

R1638

MF

201

5%

1/20W

100K

21

R1691

100K

MF

201

5%

1/20W

21

R1694

100K

1/20W

5%

201

MF

21

R1693

100K

1/20W

5%

201

MF

2

1

R1655

PLACE_NEAR=U0500.AW15:2.54mm

49.9

201

1% 1/20W MF

21

R1695

100K

1/20W

5%

201

MF

21

R1660

MF

201

5%

1/20W

100K

21

R1661

100K

MF

201

5%

1/20W

21

R1662

100K

1/20W

5%

201

MF

21

R1663

MF

201

5%

1/20W

100K

21

R1664

MF

201

5%

1/20W

47K

21

R1665

MF

201

5%

1/20W

47K

21

R1666

1/20W

5%

201

MF

47K

21

R1667

MF

201

5%

1/20W

47K

PCH GPIO/MISC/LPIO

SYNC_MASTER=WILL_J43 SYNC_DATE=01/14/2013

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

TPAD_SPI_INT_GPIO46_L

JTAG_ISP_TDO

PCH_UART1_CTS_L

PCH_UART1_RXD PCH_UART1_TXD

PCH_BT_UART_CTS_L

PCH_BT_UART_RTS_L

PCH_BT_UART_CTS_L

PCH_BT_UART_RTS_L

PCH_BT_UART_R2D

PCH_BT_UART_D2R

TPAD_SPI_INT_GPIO46_L

TPAD_SPI_INT_L

PP3V3_S5

SPIROM_USE_MLB

XDP_MLB_RAMCFG0

XDP_MLB_RAMCFG3

PP3V3_S0

PP3V3_S3

PP3V3_S0

BT_PWRRST_L

LPC_SERIRQ

XDP_FW_PME_L

PCH_HSIO_PWR_EN TPAD_SPI_IF_EN

CAMERA_PWR_EN_PCH

LCD_IRQ_L

ENET_MEDIA_SENSE

PP1V05_S0

XDP_MLB_RAMCFG2

XDP_MLB_RAMCFG1

LCD_PSR_EN

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

XDP_PCH_GPIO76

PP3V3_S0SW_SD

PP3V3_S3RS0_CAMERA

PP3V3_S3

JTAG_ISP_TDO

AP_S0IX_WAKE_L

AUD_SPI_CS_L AUD_SPI_CLK AUD_SPI_MISO AUD_SPI_MOSI

TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI

XDP_LPCPLUS_GPIO

SD_RESET_L

JTAG_TBT_TMS_PCH

TPAD_USB_IF_EN

XDP_SDCONN_STATE_CHANGE_L

PP3V3_S0

TBT_PWR_EN

SD_PWR_EN

SSD_PWR_EN

HDD_PWR_EN

SMC_WAKE_SCI_L

XDP_PCH_GPIO17

PM_THRMTRIP_L

SSD_SR_EN_L

AP_S0IX_WAKE_SEL

PCH_STRP_TOPBLK_SWP_L

BT_PWRRST_L

TBT_POC_RESET_L

PCH_BT_UART_R2D

TPAD_SPI_MOSI

TPAD_SPI_MISO

LPC_SERIRQ

TBT_CIO_PLUG_EVENT_L

PCH_OPI_COMP

AUD_SPI_CS_L

AUD_SPI_MISO

AUD_SPI_CLK

TPAD_SPI_CLK

TPAD_SPI_CS_L

AUD_SPI_MOSI

PCH_UART1_RXD

PCH_UART1_CTS_L

PCH_UART1_TXD

ENET_MEDIA_SENSE

LCD_IRQ_L

LCD_PSR_EN

XDP_PCH_GPIO76

XDP_MLB_RAMCFG0

HDMITBTMUX_SEL_TBT

TP_MEM_VDD_SEL_1V5_L

XDP_PCH_GPIO17

XDP_LPCPLUS_GPIO

SD_RESET_L

TPAD_SPI_INT_GPIO28_L

SMC_WAKE_SCI_L

TPAD_USB_IF_EN

PCH_TBT_PCIE_RESET_L

HDD_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

TBT_PWR_EN

SD_PWR_EN

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

JTAG_TBT_TMS_PCH

PCH_HSIO_PWR_EN

TPAD_SPI_IF_EN

SPIROM_USE_MLB

XDP_MLB_RAMCFG3

CAMERA_PWR_EN_PCH

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG2

PCH_TCO_TIMER_DISABLE

PCH_BT_UART_D2R

PCH_I2C1_SCL

PCH_I2C1_SDA

AP_S0IX_WAKE_L

PLT_RESET_L

AP_RESET_L

PLT_RESET_L

SSD_RESET_L

CAM_PCIE_RESET_L

PCH_I2C1_SDA

PP3V3_S0

PCH_I2C1_SCL

TPAD_SPI_INT_GPIO28_L

SSD_PWR_EN

PP3V3_S3

AP_S0IX_WAKE_SEL

PP3V3_S0

SSD_SR_EN_L

15 OF 76

<SCH_NUM>

16 OF 121

15

15 64

15

15 36

8

11 13 16 17 18 28 29 34 42 57

58 59 60 62 64 74

15 46 64

15 16 18

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

15 18 19 33 36 40 41 58 62 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

15 64

15 37 64

12 16

15 58

15 36

15 18

15 64

6 8

11 16 17 38 42 51 55 58

59 62 64

15 16 18

15 64

15 16 18 25

15 16

34 37 39 65

31 41

15 18 19 33 36 40 41 58 62 64

15 18

15 29

15 64

15 36

15 36 68

15 16 64

15 34

15 18

15 36

15 16 33

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

15 25

15 34

15 30 58 59 64

15 64

15 37

15 16

15 64

15

15 64

15

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

15

15 29

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44

45 56 59 61 62 64 65 74

15 30 64

w w w . c h i n a f i x . c o m

IN

IN IN

IN

OUT

IN

OUT

IN

OUT OUT

IN

NC NC

IN IN

IN

TP

OUT

IN

OUT

IN

OUT

IN

TP

OUT

IN

BI

OUT

TP

BI

TP

BI

TP

BI

IN

OUT

BI

IN

OUT

IN

OUT

BI

TP

IN

OUT

Y

NC NC

VCC

GND

A

NC

IN

NC

IN

TP

IN

TP

IN

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

OUT

TP

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

OBSFN_A0 OBSFN_A1

VCC_OBS_CD

Extra BPM Testpoints

support chipset debug.

OBSFN_C0

OBSDATA_C0

OBSFN_C1

OBSDATA_C1

OBSDATA_C3

OBSDATA_C2

OBSDATA_D0

OBSFN_D1

ITPCLK#/HOOK5

OBSDATA_D3

DBR#/HOOK7

XDP_PRESENT#

ITPCLK/HOOK4

TMS

TDI

OBSDATA_A0

OBSFN_B1

OBSDATA_A3

OBSDATA_A2

OBSFN_B0

OBSDATA_B0 OBSDATA_B1

HOOK3

HOOK1

SDA

TCK1

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to

OBSDATA_A1

OBSDATA_D2

SCL

OBSFN_D0

Merged (CPU/PCH) Micro2-XDP

TRSTn

TDO

HOOK2

TDI and TMS are terminated in CPU.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

Unused & MLB_RAMCFGx GPIOs have TPs.

SSD_PCIEx_SEL_L straps are connected via 1K to common net.

PCH/XDP Signals

RESET#/HOOK6

PCH XDP Signals

Non-XDP Signals

These signals do not connect to XDP connector in this architecture, only accessible via Top-Side Probe. Nets are listed here to show XDP associations and to make clear what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

NOTE: Must not short XDP pins together!

OBSDATA_B3

OBSDATA_D1

TCK0

CPU JTAG Isolation

518S0847

OBSDATA_B2

PWRGD/HOOK0

VCC_OBS_AB

6

13 15 18

6

67

6

64 67

6

67

6

67

6

67

6

67

13 37

13 17 37

12 16 64 69

17 67

6

12 16 64 69

21

R1805

5%

201

1/20W

MF

PLACE_NEAR=U0500.AG7:2.54mm

1K

XDP

12

R1813

5%

201

1/20W

MF

PLACE_NEAR=U0500.E60:28mm

51

XDP

21

R1804

5%

0

XDP

402

MF-LF1/16W

21

R1802

5%

0

0201

1/20W

MF

PLACE_NEAR=U5000.J3:2.54mm

XDP

21

R1800

5%

201

1/20W

MF

PLACE_NEAR=U0500.C61:2.54mm

XDP

1K

6

67

9

8 7

64 63

62

61

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1800

XDP_CONN

DF40RC-60DP-0.4V

CRITICAL

M-ST-SM1

6

67

6

67

6

67

6

67

6

67

6

67

6

67

6

67

6

67

6

67

1

TP1806

TP-P6

1

TP1807

TP-P6

1

TP1805

TP-P6

1

TP1804

TP-P6

1

TP1803

TP-P6

1

TP1802

TP-P6

8

2

1

R1830

5% 1/16W MF-LF 402

150

21

R1810

5%

201

1/20W

MF

PLACE_NEAR=U0500.F62:28mm

XDP

51

12 16 64 69

2

1

R1831

5%

XDP

MF-LF 402

1/16W

1K

12

R1896

5%

201

1/20W

MF

NO STUFF

PLACE_NEAR=U0500.AE62:28mm

51

12

R1892

5%

201

1/20W

MF

PLACE_NEAR=U0500.AD62:28mm

XDP

51

12

R1891

5%

201

1/20W

MF

PLACE_NEAR=U0500.AD61:28mm

XDP

51

12

R1890

5%

201

1/20W

MF

PLACE_NEAR=U0500.AE61:28mm

51

XDP

12

R1899

5%

201

1/20W

MF

NO STUFF

PLACE_NEAR=U0500.AE63:28mm

1K

21

R1835

5%

0

0201

1/20W

MF

PLACE_NEAR=J1800.58:28mm

XDP

12 16

6

12 16 64 67

6

64 67

6

64 67

6

16 64 67

2

1

C1801

XDP

6.3V CERM-X5R 0201

0.1UF

10%

15 16 33

14

14 16 61 65

6

67

14 16 61 65

1

TP1870

TP-P6

14 16 35 14 16 35

15 18

14

1

TP1874

TP-P6

2

1

C1800

XDP

6.3V

CERM-X5R

0201

0.1UF

10%

1

TP1876

TP-P6

15 18

1

TP1877

TP-P6

15 18

1

TP1878

TP-P6

15 18

15

15 16 18 25 15 16 18 25

12

6

64 67

21

R1884

5%

201

1/20W

MF

1K

15 16 64

6

64 67

15

15 16 18 25 15 16 18 25

15 16 64

1

TP1887

TP-P6

2

1

C1804

XDP

6.3V

CERM-X5R

0201

0.1UF

10%

2

1

C1806

XDP

6.3V CERM-X5R 0201

0.1UF

10%

6

67

6

12 16 64 67

12

R1897

5%

201

1/20W

MF

51

NO STUFF

PLACE_NEAR=U0500.AU62:28mm

4

6

5

1

3

2

U1845

SOT891

74LVC1G07GF

2

1

C1845

X5R-CERM

0201

16V

0.1UF

10%

6

67

2

1

R1845

5%

201

1/20W MF

330K

17 37 59

1

TP1873

TP-P6

15 16 33

1

TP1886

TP-P6

6

67

4

5

3

Q1842

PLACE_NEAR=J1800.55:28mm

DMN5L06VK-7

CRITICAL

XDP

SOT563

1

2

6

Q1842

SOT563

DMN5L06VK-7

CRITICAL

XDP

1

2

6

Q1840

DMN5L06VK-7

XDP

CRITICAL

SOT563

4

5

3

Q1840

PLACE_NEAR=J1800.51:28MM

SOT563

DMN5L06VK-7

XDP

CRITICAL

12 15

1

TP1879

TP-P6

1

TP1880

TP-P6

1

TP1881

TP-P6

6

67

14 19 40 56 69

6

16 64 67

6

8

17

6

67

6

67

SYNC_DATE=12/17/2012

CPU/PCH Merged XDP

SYNC_MASTER=WILL_J43

XDP_PCH_UART_SSD_L_BT_H

XDP_PCH_GPIO35

XDP_FW_PME_L

XDP_CPU_TDO

XDP_JTAG_CPU_ISOL_L

XDP_PCH_TDO

XDP_TRST_L

XDP_CPU_PRESENT_L

CPU_CFG<6> CPU_CFG<7>

CPU_PWR_DEBUG

PP1V05_S0

XDP_CPU_PWRBTN_L

XDP_BPM_L<0>

CPU_CFG<3>

XDP_CPU_PRDY_L

XDP_CPU_VCCST_PWRGD

XDP_CPURST_L XDP_DBRESET_L

XDP_JTAG_ISP_TCK

XDP_USB_EXTA_OC_L

XDP_SDCONN_STATE_CHANGE_L

XDP_MLB_RAMCFG3

PCH_JTAGX

PP3V3_S5

XDP_SYS_PWROK

XDP_CPU_PREQ_L

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<19> CPU_CFG<18>

CPU_CFG<13>

XDP_MLB_RAMCFG2

XDP_PCH_GPIO17

XDP_SSD_PCIE0_SEL_L

SMBUS_PCH_DATA

XDP_PCH_GPIO76

XDP_MLB_RAMCFG1

XDP_USB_EXTD_OC_L

XDP_USB_EXTC_OC_L

XDP_MLB_RAMCFG0

XDP_USB_EXTB_OC_L

XDP_CPU_TCK

XDP_PCH_TCK

CPU_CFG<11>

CPU_CFG<10>

XDP_CPUPCH_TRST_L

PLT_RESET_L

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<9>

CPU_CFG<8>

PM_PCH_SYS_PWROK

PM_PWRBTN_L

CPU_VCCST_PWRGD

XDP_PCH_TCK

SMBUS_PCH_CLK

CPU_CFG<5>

CPU_CFG<4>

XDP_BPM_L<1>

CPU_CFG<2>

CPU_CFG<0>

PP1V05_S0

XDP_PCH_TDO

XDP_CPU_TDO

XDP_PCH_TDI

PCH_JTAGX

PP1V05_SUS

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_CPU_TCK

CPU_CFG<1>

XDP_CPUPCH_TRST_L

XDP_PCH_TMS

PP5V_S0

ALL_SYS_PWRGD

XDP_JTAG_ISP_TDI

XDP_LPCPLUS_GPIO

XDP_PCH_TMS

XDP_CPU_TMS

XDP_PCH_TDI

XDP_CPU_TDI

XDP_LPCPLUS_GPIO

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_JTAG_ISP_TCK

XDP_SDCONN_STATE_CHANGE_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTA_OC_L

XDP_CPUPCH_TRST_L

MAKE_BASE=TRUE

16 OF 76

<SCH_NUM>

18 OF 121

6 8

11 15 16 17 38 42 51 55

58 59 62 64

64

67

8

11 13 15 17 18 28 29 34 42

57 58 59 60 62 64 74

64

12 16 64 69

6 8

11 15 16 17 38 42 51 55

58 59 62 64

12 16 64 69

6

16 64 67

12 16 64 69

12 16

57 62

6

16 64 67

6

12 16 64 67

12 16 64 69

17 32 45 51 52 56 58 59 61 62 64

6

12 16 64 67

w w w . c h i n a f i x . c o m

OUT

NC NC

OUT

IN

BIIN

OUT

IN

OUT

NC

NC NC

OUT

IN

NC

OUT

IN

NC

A Y

NC NC

VCC

GND

NC

IN

OUT

IN

OUT

IN

OUT

IN

YA

B

NC

GND

VCC

32.768K

GND

THRM

VOUT

X2 X1

25M_A 25M_B 25M_C

VIOE_25M_A VIOE_25M_B VIOE_25M_C

VG3HOT

NC

VDD

PAD

NC NC

VER 3

D

S G

VER 3

D

SG

Y

A

B

08

Y

A

B

08

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Must be powered if any VDDIO is powered.

available ~3.3V power

WF: Do we need this?

TPS51916 I(leak) = +/- 1uA, Vih(min) = 1.8V 33uW when driven-low

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

Memory VTT Enable Level-Shifter

SMC controls strap enable to allow in-field control of strap setting.

VCCST (1.05V S0) PWRGD

IPD = 9-50k

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

PCH Reset Button

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

CAM XTAL Power

PCH PWROK Generation

PCH 24MHz Outputs

No bypass necessary

No Coin-Cell: 3.3V S5

Coin-Cell & No G3Hot: 3.3V S5

TBT XTAL Power

GreenCLK 25MHz Power

PCH 24MHz Crystal

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell: VBAT (300-ohm & 10uF RC)

System RTC Power Source & 32kHz / 25MHz Clock Generator

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

VBAT and +V3.3A are internally ORed to create VDD_RTC_OUT.

+V3.3A should be first

to reduce VBAT draw.

For SB RTC Power

PCH ME Disable Strap

NOTE: 30 PPM or better required for RTC accuracy

pin 5 must receive S5 power (Stuff R2042)

new and old parts. With GreenCLK Rev C

This looks a little ugly to support

12

25 69

2

1

C1902

X5R

1UF

0201

20%

6.3V

2

1

C1910

0201

6.3V

20%

1UF

X5R

31

42

Y1905

SM-3.2X2.5MM

CRITICAL

25.000MHZ-12PF-20PPM

17 37 69

21

R1927

PLACE_NEAR=U0500.AN15:5.1mm

22

MF

1/20W

201

5%

12 69

13 37 64 16 67

2

1

C1924

0201

X5R-CERM

16V

10%

0.1UF

21

R1905

MF

1/20W

0201

0

5%

2

1

R1906

NO STUFF

1M

MF

1/20W

201

5%

21

R1996

XDP

MF

1/20W

0201

0

5%

2

1

R1997

402

1/16W MF-LF

SILK_PART=SYS RESET

NO STUFF

0

5%

2

1

R1995

10K

MF

1/20W

201

5%

2

1

R1920

100K

MF

1/20W 201

5%

2

1

R1921

1K

MF

1/20W 201

5%

12 69

37

2

1

C1922

0.1UF

10% 16V

0201

X5R-CERM

32 69

2

1

R1916

1M

MF

1/20W

201

5%

21

R1915

MF

1/20W

0201

0

5%

21

C1915

C0G

6.8PF

0201

+/-0.1PF

25V

21

C1916

6.8PF

0201

C0G

25V

+/-0.1PF

12

12 17

8

16

2

1

R1931

10K

MF

1/20W

201

5%

2

1

C1930

0201

16V

X5R-CERM

10%

0.1UF

13 18 37 59

2

1

R1970

330K

MF

1/20W

201

5%

4

6

5

1

3

2

U1970

SOT891

74AUP1G07GF

2

1

C1970

0.1UF

10% 16V

0201

X5R-CERM

6

17 53

26 27 37 38

16 17 37 59

2

1

C1950

X5R-CERM

10%

0201

16V

0.1UF

BYPASS=U1950:5MM

1

2

R1963

MF

1/20W

0201

0

5%

1

2

R1960

NO STUFF

MF

1/20W

0201

0

5%

21

R1962

1K

MF

1/20W

201

5%

13 16 37

13 17

21

R1951

NO STUFF

MF

1/20W

0201

0

5%

2

1

R1950

10K

MF

1/20W

201

5%

2

1

R1955

10K

MF

1/20W

201

5%

8

51

8

17 51

8

17 51

2

1

R1961

NO STUFF

100K

MF

1/20W

201

5%

4

6

5

3

1

2

U1930

74AUP1G09

SOT891

CRITICAL

3 4

1

14

6

11

13

5

17216107

12

15

8

9

U1900

SLG3NB148CV

CRITICAL

TQFN

CKPLUS_WAIVE=PwrTerm2Gnd

3 1

4 2

Y1915

CRITICAL

3.20X2.50MM-SM1

24.000MHZ-20PPM-6PF

4

5

3

Q1920

DMN5L06VK-7

SOT563

1

2

6

Q1920

SOT563

DMN5L06VK-7

2 1

C1905

0201

5%

25V

CERM

12PF

7

8

4

2

1

U1950

74LVC2G08GT/S505

SOT833

3

8

4

6

5

U1950

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

21

C1906

0201

5%

25V

CERM

12PF

Chipset Support

SYNC_DATE=01/09/2013SYNC_MASTER=J43_MLB1

SYSCLK_CLK25M_X1

LPC_CLK24M_SMC

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_RTC_CLK32K_RTCX2

MEMVTT_PWR_EN

MAKE_BASE=TRUE

CPU_VR_READY

PM_PCH_PWROK

MAKE_BASE=TRUE

SYS_PWROK_R

SMC_DELAYED_PWRGD

PM_S0_PGOOD

CPUVR_PGOOD_R

ALL_SYS_PWRGD

PP3V42_G3H

SPI_DESCRIPTOR_OVERRIDE_L

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE

PP1V5_S0SW_AUDIO_HDA

PP3V3_S5

PP3V3_S5RS3RS0_SYSCLKGEN

NC_RTC_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PP3V3_TBTLC

PP3V42_G3H

PP1V2_CAM_XTALPCIEVDD

PCH_CLK24M_XTALOUT_R

PCH_CLK24M_XTALIN

PM_SLP_S3_L

ALL_SYS_PWRGD

PP3V3_S5

CPU_VCCST_PWRGD

PP1V05_S0

CPU_VR_EN

CPU_VR_READY

XDP_DBRESET_L

PM_SYSRST_L

PP3V3_S0

HDA_SDOUT_R

PCH_CLK24M_XTALOUT

LPC_CLK24M_SMC_R

PP5V_S0

CPU_MEMVTT_PWR_EN_LSVDDQ

PP1V2_S3

PP3V3_S0

MEMVTT_PWR_EN

PM_PCH_SYS_PWROK

PM_PCH_PWROK

PP3V3_S0

LPC_CLK24M_SMC

PPVRTC_G3H

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_CAMERA SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_X2

<SCH_NUM>

19 OF 121

17 OF 76

69

17 37 69

12 17

17 53

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

8

11 58

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

18

18 25 26 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

31

16 17 37 59

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

6 8

11 15 16 38 42 51 55 58 59

62 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

16 32 45 51 52 56 58 59 61 62 64

19 20 21 22 23 42 53 62 70

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8

12 13 62 64

69 69

w w w . c h i n a f i x . c o m

OUT

IN

IN IN IN IN

IN OUT OUT

BI

OUT

BI

OUT IN IN

IN

OUT

IN

OUT

IN

IN BI

BIBI

NC

08

NC

OUT

IN

OUT OUT

IN IN

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

OUT

VCC

1A 1Y

2A 2Y

GND

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

No MAKE_BASE on TCK/TDI as these are provided on XDP page.

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC (on TBT page)

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

Falcon Ridge PLUG_EVENT is active-low, always driven (pull-up)

NOTE: Only DDC_DATA is sensed by PCH, so

Unbuffered

to indicate active display interface.

DDC_CLK pull-ups are unstuffed.

LPDDR3 Alias Support

MAKE_BASE

DDC Pull-Ups

GreenCLK 25MHz Power

R2041/2 should be stuffed for

DP++ spec violation, should remove!

TBTSNK1_DDC is pulled-up just to indicate that DP port is used. No DDC on this port, AUX-only.

2.2k pull-ups are required by PCH

Required for unused second TBT port

R2042 should be stuffed for GreenCLK C

GreekCLK A or B depending on S2 rail

Buffered

TBT Aliases

MAKE_BASE

Scrub for Layout Optimization

Platform Reset Connections

Pull-downs for chip-down RAM systems

RAM Configuration Straps

Single-port TBT implementation does not require DDC Crossbar

MAKE_BASE

Thunderbolt Pull-up/downs

(For development only)

Power State Debug LEDs

To RR

To PCH

S0 pull-up on PCH page

Redwood Ridge JTAG Isolation

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

S0 pull-up on PCH page

From PCH

From RR

and TDI as well for PCH glitch-prevention.

different isolation techniques will likely be necessary.

Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK

Pin N61 needs a TP for Power to perform iFDIM test

Renaming the pins N61 and P61 to remove automatic diffpari property

2

1

R2022

5%

201

1/20W

MF

NO STUFF

2.2K

2

1

R2023

5%

201

1/20W MF

2.2K

2

1

R2020

5%

201

1/20W

MF

2.2K

NO STUFF

2

1

R2021

5%

201

1/20W MF

2.2K

2

1

R2050

5%

201

1/20W

MF

RAMCFG3:L

10K

2

1

R2051

5%

201

1/20W

MF

RAMCFG2:L

10K

2

1

R2052

5%

201

1/20W

MF

RAMCFG1:L

10K

2

1

R2053

5%

201

1/20W

MF

RAMCFG0:L

10K

2

1

R2016

5%

201

1/20W

MF

10K

2

1

R2017

5%

201

1/20W MF

10K

2

1

R2018

5%

201

1/20W

MF

10K

2

1

R2019

5%

201

1/20W MF

10K

2

1

R2014

5%

201

1/20W MF

10K

K

A

D2090

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S5_ON

K

A

D2091

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=STBY_ON

2

1

R2090

5%

201

1/20W

MF

DBGLED

20K

2 1

R2094

5%

0

402

MF-LF

1/16W

PLACE_SIDE=BOTTOM

DBGLED

2

1

R2091

5%

201

1/20W

MF

DBGLED

20K

K

A

D2092

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S3_ON

GREEN-56MCD-2MA-2.65V LTQH9G-SM

2

1

R2092

5%

201

1/20W

MF

DBGLED

20K

K

A

D2093

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON

DBGLED

2

1

R2093

5%

201

1/20W

MF

DBGLED

20K

15 16

25

6

18

15 18

28 58 59

13 18 29 36 37 59

13 17 37 59

2

1

R2095

5%

201

1/20W

MF

20K

DBGLED

K

A

D2095

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S0_ON

13 37

13 18 25

5

25 67

5

25 67

13 18 28

13 18 25 67

13 18 28

13 18

13 18 25 67

13 18 25

13 18

2

1

C2071

10% 16V

0.1UF

X5R-CERM 0201

5

4

1

2

3

U2071

SC70-HF

CRITICAL MC74VHC1G08

2

1

R2070

5%

201

1/20W MF

100K

21

R2088

5%

0

0201

1/20W

MF

21

R2072

5%

0

0201

1/20W

MF

13 15 16

21

R2071

5%

0

0201

1/20W

MF

56

37

19

15 18 25 15 18 25

21

R2089

5%

0

0201

1/20W

MF

NOSTUFF

15 31

15 18 25 15 18 25

21

R2040

5%

0

0201

1/20W

MF

NO STUFF

21

R2041

5%

0

0201

1/20W

MF

NO STUFF

13 18 28

15 18 25 15 18 25

4

6

5 3

1

2

U2030

CRITICAL

74LVC1G08

SOT891

NOSTUFF

2

1

C2030

NOSTUFF

0.1UF

BYPASS=U2030:3mm

0201

X5R-CERM

10% 10V

21

R2030

5%

0

0201

1/20W

MF

31

15

13 18 29 36 37 59

21

R2042

5%

0

0201

1/20W

MF

15 16 18 25

1

2

6

Q2090

DBGLED

DMN5L06VK-7

SOT563

4

5

3

Q2090

DBGLED

DMN5L06VK-7

SOT563

1

2

6

Q2091

SOT563

DMN5L06VK-7

DBGLED

4

5

3

Q2091

SOT563

DMN5L06VK-7

DBGLED

2

1

R2015

100K

MF

1/20W

201

5%

15

25

2

1

R2062

100K

1/20W 201

5%

MF

52

4

3

6

1

U2060

SOT891

74LVC2G07

2

1

C2060

10V

20%

402

CERM

0.1UF

2

1

R2061

1/20W

100K

5%

201

MF

25

15

2

1

R2010

100K

1/20W 201

5%

MF

14 39

SYNC_MASTER=J43_MLB

Project Chipset Support

SYNC_DATE=01/17/2013

PCH_SML1ALERT_L

PP3V3_SUS

TP_CPU_RSVDN61

MAKE_BASE=TRUE

TP_CPU_RSVDN61

MAKE_BASE=TRUE

TP_CPU_RSVDP61TP_CPU_RSVDP61

JTAG_TBT_TMS_PCH

PP3V3_TBTLC

JTAG_TBT_TDO JTAG_ISP_TDO

JTAG_TBT_TMS

PM_SLP_S4_L

CAMERA_PWR_EN_PCH

CAMERA_PWR_EN

PP3V3_S5

PM_SLP_S0_L

DBGLED_S0_D

PM_SLP_S3_L

DBGLED_S0I3_D

PM_SLP_S4_L

DBGLED_S3_D

S4_PWR_EN

DBGLED_S4_D

PP3V3_S5

TRUE

DP_TBTSNK1_HPD DP_TBTSNK1_ML_C_P<3..0>

TRUE

=DP_TBTSNK1_ML_C_P<3..0> =DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_DATA

PP3V3_S5_DBGLED

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=3.3V

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5RS3RS0_SYSCLKGEN

BKLT_PLT_RST_L

TRUE

DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK1_HPD

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

TRUE

PCH_TBT_PCIE_RESET_L

CAM_PCIE_RESET_L

SMC_LRESET_L

PCH_TBT_PCIE_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

PP3V3_S0

PLT_RESET_L

PCA9557D_RESET_L

DP_TBTSNK0_DDC_DATA

PP3V3_S3

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK

PP3V3_S0

PP3V3_S5RS3RS0_SYSCLKGEN

HDMITBTMUX_SEL_TBT

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1

TBT_CIO_PLUG_EVENT_L

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_DDC_DATA

TRUE

DP_TBTSNK1_DDC_DATA

TRUE

DP_TBTSNK1_DDC_CLK

TRUE

DP_TBTSNK1_AUXCH_C_P

TRUE

DP_TBTSNK0_DDC_CLK

TBT_B_CONFIG1_BUF

TBT_B_CONFIG2_RC

DP_TBTPB_HPD

TBT_B_CIO_SEL

PP0V6_S3_MEM_VREFCA_B PP0V6_S3_MEM_VREFCA_B

VOLTAGE=0.6V

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_B PP0V6_S3_MEM_VREFDQ_B

VOLTAGE=0.6V

MAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5_L

TP_CPU_MEM_RESET_L

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_A

VOLTAGE=0.6V

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_A

VOLTAGE=0.6V

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5_L

MAKE_BASE=TRUE

TP_CPU_MEM_RESET_L

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG2

DP_TBTSNK1_DDC_CLK

DBGLED_S0

DBGLED_S0I3

DBGLED_S5

DP_TBTSNK0_DDC_CLK

TRUE

DP_TBTSNK1_DDC_CLK

XDP_JTAG_ISP_TCKXDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI XDP_JTAG_ISP_TDI

PP3V3_S5

DBGLED_S3DBGLED_S4

TBT_CIO_PLUG_EVENT_L

TRUE

PP3V3_S0

TBT_B_LSRX

HDMITBTMUX_SEL_TBT

TRUE

<SCH_NUM>

20 OF 121

18 OF 76

8

11 14 46 57 58 59 62 64

8

18

8

18

8

18

8

18

17 25 26 62 64

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

17 18

8

11 12 13 15

17 18 26 30 36

38 39 40 41 42

43 44 45 56 59

61 62 64 65 74

13 18 28

15 19 33 36 40 41 58 62 64

13 18

13 18 28

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

17 18

13 18

18 19 22 23 70 18 19 22 23 70

18 19 20 21 70 18 19 20 21 70

15 18

6

18

13 18

8

11 13

15 16 17

18 28 29

34 42 57

58 59 60

62 64 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

25

w w w . c h i n a f i x . c o m

OUT

V-

V+

V-

V+

IN

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VRef Dividers

of margining option.

+21uA - -21uA (- = sourced)

0.000V - 2.397V (0x00 - 0xBA)

0.800V - 1.600V (+/- 400mV)

NOTE: Margining will be disabled across all

Always used, regardless

Addr=0x98(WR)/0x99(RD)

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step

FETs for CPU isolation during DAC margining

R22x6 pin 2:

Q2265 pin 6:

to remove short due to CPU.

and disables margining after platform reset.

DAC sets voltage level, PCA9557 & FETs enable outputs

Addr=0x30(WR)/0x31(RD)

soft-resets and sleep/wake cycles.

watchdog will disable margining.

RST* on ’platform reset’ so that system

3.53mV / step @ output

+25uA - -25uA (- = sourced)

1.343V (DAC: 0x68)

0.972V - 1.714V (+/- 371mV)

DDR3L (1.35V)

DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider

1.200V (DAC: 0x5D)

5

D

MEM VREG

LPDDR3 (1.2V)

DAC Channel:

PCA9557D Pin:

MEM A VREF DQ

1

A B

2

MEM A VREF CA

C

3

MEM B VREF CA

DDR3L (1.35V)

C

4

6.36mV / step @ output

+82uA - -82uA (- = sourced)

DAC output, cannot enable

NOTE: MEMVREG and SPARE share a

(All 4 R’s)

+73uA - -73uA (- = sourced)

0.600V (DAC: 0x2E.5)

0.675V (DAC: 0x34)

Margined target:

0.300V - 0.900V (+/- 300mV)

0.000V - 1.199V (0x00 - 0x5D)

CPU-Based Margining

margining support. When

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

Pins B1 & B4:

both at the same time!

(OD)

Q2225 pin 6:

DDR3L (1.35V) 6.99mV per step

VREFMRGN_CPU_EN is low

VREFCA. Split into two

- =I2C_VREFDACS_SCL

DAC range:

Nominal value

VRef current:

DAC step size:

- =PP3V3_S3_VREFMRGN

- =PPDDR_S3_MEMVREF

- =I2C_VREFDACS_SDA

0.000V - 2.694V (0x00 - 0xD1)0.000V - 1.354V (0x00 - 0x69)

BOM options provided by this page:

- DDRVREF_DAC - Stuffs DAC margining circuit.

EN RC’s to avoid drain glitches May not be necessary due to C22x0

LPDDR3 (1.2V) ?.??mV per step

DAC margining VREFCA ensure

LPDDR3 (1.2V)

4.28mV / step @ output

DAC-Based Margining

signals for independent DAC

NOTE: CPU has single output for

MEM B VREF DQ

0.337V - 1.013V (+/- 337.5mV)

6.36mV / step @ output

53

2

1

C2202

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

21

R2214

201

PLACE_NEAR=R7415.2:1mm

1%

DDRVREF_DAC

1/20W

MF

38.3K

2

1

R2213

201

5%

100K

1/20W

MF

DDRVREF_DAC

2

1

R2212

201

5%

100K

1/20W

MF

DDRVREF_DAC

B4

B1

A4

A1

A2

A3

U2204

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

MAX4253

UCSP

CRITICAL DDRVREF_DAC

B4

B1

C4

C1

C2

C3

U2204

UCSP

DDRVREF_DAC

MAX4253

CRITICAL

21

R2218

SHORT

NONE NONE

NONE

OMIT

402

18

7

2

1

R2202

201

1/20W

5%

MF

DDRVREF_DAC

100K

7

2

1

R2201

201

100K

DDRVREF_DAC

5%

1/20W

MF

21

R2225

201

1/20W

5%

MF

DDRVREF_DAC

100K

2

1

C2225

10%

6.3V

DDRVREF_DAC

0.1UF

0201

CERM-X5R

2

1

C2245

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

21

R2245

201

MF

1/20W

DDRVREF_DAC

5%

100K

21

R2265

201

MF

1/20W

5%

DDRVREF_DAC

100K

2

1

C2265

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

2

1

C2285

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

2

1

R2215

201

100K

5%

1/20W

MF

DDRVREF_DAC

21

R2285

201

DDRVREF_DAC

MF

1/20W

5%

100K

2

1

R2207

201

DDRVREF_DAC

100K

5%

1/20W

MF

21

R2226

201

1%

1/20W

MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2225.1:2.54mm

21

R2246

201

1%

1/20W

MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2265.1:2.54mm

21

R2266

201

1%

1/20W

MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2225.4:2.54mm

21

R2286

201

1%

1/20W

MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2265.4:2.54mm

2

1

R2217

201

MF

1/20W

5%

DDRVREF_DAC

1M

2

1

R2200

201

100K

5%

1/20W

MF

2

1

R2221

201

PLACE_NEAR=Q2220.6:3mm

MF

1%

8.2K

1/20W

21

R2280

201

MF

1/20W

1%

24.9

2

1

C2280

10%

0.022UF

0201

X5R-CERM

6.3V

PLACE_NEAR=Q2260.3:2mm

21

R2283

201

MF

1/20W

10

1%

2

1

R2281

201

PLACE_NEAR=Q2260.3:3mm

1%

8.2K

1/20W MF

2

1

R2282

201

1%

8.2K

1/20W

MF

PLACE_NEAR=R2281.2:1mm

2

1

R2262

201

PLACE_NEAR=R2261.2:1mm

1%

8.2K

1/20W

MF

21

R2260

201

MF

1/20W

1%

24.9

21

R2263

201

MF

1/20W

10

1%

2

1

C2260

10%

0.022UF

0201

X5R-CERM

6.3V

PLACE_NEAR=Q2220.3:2mm

2

1

R2261

201

PLACE_NEAR=Q2220.3:3mm

1%

8.2K

1/20W MF

2

1

R2242

201

PLACE_NEAR=R2241.2:1mm

1%

8.2K

1/20W

MF

21

R2240

201

MF

1/20W

1%

24.9

21

R2243

201

10

MF

1/20W

1%

2

1

C2240

6.3V X5R-CERM 0201

0.022UF

10%

PLACE_NEAR=Q2260.6:2mm

2

1

R2241

201

8.2K

PLACE_NEAR=Q2260.6:3mm

1% 1/20W MF

21

R2223

201

1/20W

MF

10

1%

2

1

R2222

201

PLACE_NEAR=R2221.2:1mm

1%

8.2K

MF

1/20W

21

R2220

201

MF

1/20W

1%

24.9

2

1

C2220

10%

0.022UF

0201

X5R-CERM

6.3V

PLACE_NEAR=Q2220.6:2mm

4

5

3

Q2265

SOT563

DMN5L06VK-7

DDRVREF_DAC

CRITICAL

1

2

6

Q2265

PLACE_NEAR=Q2260.6:2.54mm

SOT563

CRITICAL

DDRVREF_DAC

DMN5L06VK-7

4

5

3

Q2225

SOT563

DMN5L06VK-7

DDRVREF_DAC

CRITICAL

1

2

6

Q2225

CRITICAL

DDRVREF_DAC

DMN5L06VK-7

SOT563

PLACE_NEAR=Q2220.6:2.54mm

1

2

6

Q2220

CRITICAL

DMN5L06VK-7

SOT563

1

2

6

Q2260

SOT563

CRITICAL

DMN5L06VK-7

4

5

3

Q2220

SOT563

CRITICAL

DMN5L06VK-7

4

5

3

Q2260

SOT563

CRITICAL

DMN5L06VK-7

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2201

DDRVREF_DAC

CRITICAL

QFN

PCA9557

14 16 19 40 56 69

5

4

2

1

8

7

6

3

10

9

U2200

MSOP

DDRVREF_DAC

CRITICAL

DAC5574

14 16 19 40 56 69

2

1

C2201

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

2

1

C2200

6.3V

20%

CERM

2.2UF

DDRVREF_DAC

402-LF

2

1

C2205

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

SYNC_DATE=02/12/2013

DDR3 VREF MARGINING

SYNC_MASTER=J41_MLB

PP3V3_S3

VREFMRGN_SPARE_BUF

VREFMRGN_MEMVREG_BUF

MEM_VREFCA_A_RC

MEM_VREFDQ_B_RC

SMBUS_PCH_CLK

SMBUS_PCH_DATA

DDRREG_FB

MEM_VREFCA_B_RC

VREFMRGN_DQ_A

VREFMRGN_CA_AB

PP1V2_S3

VREFMRGN_DQ_B

VREFMRGN_MEMVREG

MEM_VREFDQ_A_RC

PCA9557D_RESET_L

SMBUS_PCH_CLK SMBUS_PCH_DATA

VREFMRGN_DQ_A_EN VREFMRGN_DQ_B_EN

VREFMRGN_MEMVREG_EN

VREFMRGN_CA_A_EN VREFMRGN_CA_B_EN

VREFMRGN_SPARE_EN

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP0V6_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V6_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V6_S3_MEM_VREFDQ_A

VREFMRGN_CA_B_EN_RC

VREFMRGN_CA_B_RDIV

VREFMRGN_DQ_B_EN_RC

VREFMRGN_DQ_B_RDIV

VREFMRGN_CA_A_EN_RC

VREFMRGN_CA_A_RDIV

VREFMRGN_DQ_A_EN_RC

VREFMRGN_DQ_A_RDIV

CPU_MEM_VREFDQ_A_ISOL

CPU_DIMMA_VREFDQ

CPU_MEM_VREFDQ_B_ISOL

CPU_DIMMB_VREFDQ

CPU_MEM_VREFCA_B_ISOL

CPU_MEM_VREFCA_A_ISOL

VREFMRGN_CPU_EN

CPU_DIMM_VREFCA

<SCH_NUM>

22 OF 121

19 OF 76

15 18 19 33 36 40 41 58 62 64

17 20 21 22 23 42 53 62 70

18 22 23 70

18 20 21 70

w w w . c h i n a f i x . c o m

BI BI BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10uF caps are shared between DRAM.

PLACEMENT_NOTE:

LPDDR3 CHANNEL A (0-31)

Distribute evenly.

63

2

1

C2306

10UF

20% 25V X5R-CERM 0603

2

1

C2307

25V

0603

10UF

20%

X5R-CERM

2

1

C2302

402

10V X5R

1UF

10%

63

2

1

C2300

10%

0.1UF

X5R-CERM

16V

0201

2

1

C2303

402

10V X5R

1UF

10%

2

1

C2304

10V X5R 402

1UF

10%

2

1

C2301

10%

0.1UF

0201

X5R-CERM

16V

2

1

C2305

10V X5R 402

1UF

10%

63

2

1

C2310

10V X5R 402

1UF

10%

2

1

C2311

10V X5R 402

1UF

10%

2

1

C2312

25V

0603

10UF

20%

X5R-CERM

2

1

C2320

10%

1UF

402

X5R

10V

2

1

C2321

10%

1UF

402

X5R

10V

2

1

C2322

10%

1UF

402

X5R

10V

63

2

1

C2324

X5R-CERM

20%

10UF

0603

25V

2

1

C2323

X5R-CERM

20%

10UF

0603

25V

2

1

C2333

10UF

20%

0603

25V X5R-CERM

2

1

C2332

25V

0603

10UF

20%

X5R-CERM

2

1

C2331

10%

1UF

402

X5R

10V

2

1

C2330

10%

1UF

X5R

10V

402

63

2

1

C2341

0.047UF

201

10%

X5R

6.3V

2

1

C2340

201

0.047UF

X5R

6.3V

10%

63

24 63 70

7

24 63 70

63

24 63 70

7

24 70

7

24 70

7

24 70

7

24 70

7

21 24 70

7

21 24 70

7

21 24 63 70

63

2

1

R2300

201

MF

1/20W

1%

243

2

1

R2301

1%

243

1/20W

MF

201

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2300

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2300

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

63

LPDDR3 DRAM Channel A (0-31)

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

PP1V2_S3

MEM_A_CAA<1>

MEM_A_CAA<3>

MEM_A_CKE<0>

PP1V8_S3

MEM_A_ODT<0>

MEM_A_CS_L<1>

=MEM_A_DQ<0> =MEM_A_DQ<1> =MEM_A_DQ<2>

=MEM_A_DQ<5> =MEM_A_DQ<6> =MEM_A_DQ<7> =MEM_A_DQ<8> =MEM_A_DQ<9>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<12>

=MEM_A_DQ<21>

=MEM_A_DQ<26>

=MEM_A_DQ<28>

=MEM_A_DQ<27>

=MEM_A_DQ<29> =MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<2> =MEM_A_DQS_N<3>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<1>

=MEM_A_DQS_P<3>

=MEM_A_DQ<19>

=MEM_A_DQS_N<1>

=MEM_A_DQ<3>

PP1V2_S3

=MEM_A_DQS_P<0>

=MEM_A_DQ<25>

PP1V2_S3

=MEM_A_DQ<17>

=MEM_A_DQ<24>

MEM_A_CAA<0>

MEM_A_CAA<2>

=MEM_A_DQ<20>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<18>

=MEM_A_DQ<16>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

PP1V2_S3

=MEM_A_DQ<4>

MEM_A_CAA<6>

MEM_A_CAA<9>

PP1V8_S3

MEM_A_CAA<4>

MEM_A_CAA<8>

MEM_A_CKE<1>

MEM_A_CLK_P<0>

MEM_A_CAA<7>

MEM_A_CAA<5>

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_ZQ<1>

PP0V6_S3_MEM_VREFDQ_A

PP0V6_S3_MEM_VREFCA_A

MEM_A_ZQ<0>

PP1V2_S3

23 OF 121

<SCH_NUM>

20 OF 76

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

18 19 21 70

17 19 20 21 22 23 42 53 62 70

w w w . c h i n a f i x . c o m

BI BI

IN

BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Distribute evenly.

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

LPDDR3 CHANNEL A (32-63)

63

2

1

C2423

25V

0603

10UF

20%

X5R-CERM

2

1

C2403

10%

1UF

402

X5R

10V

2

1

C2404

10%

1UF

402

X5R

10V

2

1

C2405

10%

1UF

402

X5R

10V

2

1

C2406

0603

X5R-CERM

25V

20%

10UF

63

7

20 24 63 70

2

1

R2400

243

1%

1/20W

MF

201

2

1

R2401

201

MF

1/20W

243

1%

2

1

C2440

6.3V X5R

0.047UF

201

10%

63

2

1

C2441

6.3V X5R

10%

0.047UF

201

63

7

63 70

63

7

63 70

7

63 70

63

24 63 70

7

24 63 70

63

24 63 70

7

24 70

7

24 70

7

24 70

7

24 70

7

20 24 70

7

20 24 70

63

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2400

OMIT_TABLE

FBGA

EDFA232A1MA-GD-F

CRITICAL

LPDDR3-16GB

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2400

FBGA

EDFA232A1MA-GD-F

LPDDR3-16GB

CRITICAL

OMIT_TABLE

2

1

C2430

10V X5R 402

1UF

10%

2

1

C2431

10V X5R 402

1UF

10%

2

1

C2410

10%

1UF

402

X5R

10V

2

1

C2411

10%

1UF

402

X5R

10V

63

2

1

C2432

X5R-CERM

20%

10UF

0603

25V

2

1

C2412

10UF

X5R-CERM

20%

0603

25V

2

1

C2420

10V X5R 402

1UF

10%

2

1

C2400

10%

0.1UF

X5R-CERM

16V

0201

2

1

C2421

10V X5R 402

1UF

10%

2

1

C2401

0.1UF

16V X5R-CERM

10%

0201

2

1

C2422

10V X5R 402

1UF

10%

2

1

C2402

10V

10%

1UF

402

X5R

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

LPDDR3 DRAM Channel A (32-63)

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

MEM_A_ZQ<3>

MEM_A_ZQ<2>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CKE<3>

MEM_A_CKE<2>

MEM_A_CAB<5>

MEM_A_CAB<3>

MEM_A_CAB<2>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_CAB<4>

PP1V2_S3

PP1V8_S3

PP1V2_S3

PP1V8_S3

PP1V2_S3

MEM_A_CS_L<1>

=MEM_A_DQ<32> =MEM_A_DQ<33>

=MEM_A_DQ<35>

=MEM_A_DQ<34>

=MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<38> =MEM_A_DQ<39> =MEM_A_DQ<40> =MEM_A_DQ<41>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

MEM_A_DQ<33> =MEM_A_DQ<46> =MEM_A_DQ<47> =MEM_A_DQ<48> =MEM_A_DQ<49> =MEM_A_DQ<50> =MEM_A_DQ<51> =MEM_A_DQ<52> =MEM_A_DQ<53> =MEM_A_DQ<54> =MEM_A_DQ<55> =MEM_A_DQ<56> =MEM_A_DQ<57> =MEM_A_DQ<58>

=MEM_A_DQ<60>

=MEM_A_DQ<59>

=MEM_A_DQ<61> =MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<4>

MEM_A_DQS_N<6> =MEM_A_DQS_N<7>

=MEM_A_DQS_P<4>

MEM_A_DQS_P<6>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<7>

MEM_A_CLK_N<1>

=MEM_A_DQ<44>

MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9>

MEM_A_CLK_P<1>

<SCH_NUM>

21 OF 76

24 OF 121

18 19 20 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

w w w . c h i n a f i x . c o m

BI BI

IN

BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

LPDDR3 CHANNEL B (0-31)

63

2

1

C2523

25V

0603

10UF

20%

X5R-CERM

2

1

C2503

10%

1UF

402

X5R

10V

2

1

C2504

10%

1UF

402

X5R

10V

2

1

C2505

10%

1UF

402

X5R

10V

2

1

C2506

0603

X5R-CERM

25V

20%

10UF

63

7

23 24 63 70

2

1

R2500

201

MF

1/20W

1%

243

2

1

R2501

1%

243

1/20W

MF

201

2

1

C2540

201

0.047UF

X5R

6.3V

10%

2

1

C2541

201

0.047UF

10%

X5R

6.3V

63

24 63 70

7

24 63 70

63

24 63 70

7

24 70

7

24 70

7

24 70

7

24 70

7

23 24 70

7

23 24 70

63

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2500

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2500

EDFA232A1MA-GD-F

LPDDR3-16GB

FBGA

CRITICAL

OMIT_TABLE

2

1

C2530

10V X5R 402

1UF

10%

2

1

C2531

10V X5R 402

1UF

10%

2

1

C2510

10%

1UF

402

X5R

10V

2

1

C2511

10%

1UF

402

X5R

10V

63

2

1

C2532

X5R-CERM

20%

10UF

0603

25V

2

1

C2512

X5R-CERM

20%

10UF

0603

25V

2

1

C2520

10V X5R 402

1UF

10%

2

1

C2500

10%

0.1UF

X5R-CERM

16V

0201

2

1

C2521

10V X5R 402

1UF

10%

2

1

C2501

16V X5R-CERM

0.1UF

10%

0201

2

1

C2522

10V X5R 402

1UF

10%

2

1

C2502

10%

1UF

402

X5R

10V

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

LPDDR3 DRAM Channel B (0-31)

PP1V8_S3

PP1V2_S3

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

MEM_B_CKE<0> MEM_B_CKE<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<0>

PP1V8_S3

PP1V2_S3

MEM_B_CS_L<1>

=MEM_B_DQ<0> =MEM_B_DQ<1>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<4> =MEM_B_DQ<5> =MEM_B_DQ<6> =MEM_B_DQ<7> =MEM_B_DQ<8> =MEM_B_DQ<9>

=MEM_B_DQ<11>

=MEM_B_DQ<10>

=MEM_B_DQ<12> =MEM_B_DQ<13> =MEM_B_DQ<14> =MEM_B_DQ<15> =MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQ<18> =MEM_B_DQ<19> =MEM_B_DQ<20> =MEM_B_DQ<21> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<24> =MEM_B_DQ<25> =MEM_B_DQ<26>

=MEM_B_DQ<28>

=MEM_B_DQ<27>

=MEM_B_DQ<29> =MEM_B_DQ<30> =MEM_B_DQ<31>

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<2> =MEM_B_DQS_N<3>

=MEM_B_DQS_P<0>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<3>

MEM_B_ODT<0>

MEM_B_ZQ<0> MEM_B_ZQ<1>

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_B

22 OF 76

25 OF 121

<SCH_NUM>

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

18 19 23 70

w w w . c h i n a f i x . c o m

BI

IN

BI BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LPDDR3 CHANNEL B (32-63)

PLACEMENT_NOTE:

Distribute evenly.

10uF caps are shared between DRAM.

63

2

1

C2623

X5R-CERM

20%

10UF

0603

25V

2

1

C2603

10V X5R 402

1UF

10%

2

1

C2604

10V X5R 402

1UF

10%

2

1

C2605

10V X5R 402

1UF

10%

2

1

C2606

10UF

20% 25V X5R-CERM 0603

7

22 24 63 70

63

2

1

R2600

201

MF

1/20W

1%

243

2

1

R2601

1%

243

1/20W

MF

201

2

1

C2640

201

0.047UF

X5R

6.3V

10%

2

1

C2641

201

0.047UF

10%

X5R

6.3V

63

7

63 70

63

7

63 70

63

7

63 70

24 63 70

7

24 63 70

63

24 63 70

7

24 70

7

24 70

7

24 70

7

24 70

7

22 24 70

7

22 24 70

63

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2600

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2600

OMIT_TABLE

CRITICAL

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

2

1

C2630

10%

1UF

402

X5R

10V

2

1

C2631

10%

1UF

402

X5R

10V

2

1

C2610

10V X5R 402

1UF

10%

2

1

C2611

X5R

10V

402

1UF

10%

63

2

1

C2632

25V

0603

10UF

20%

X5R-CERM

2

1

C2620

10%

1UF

402

X5R

10V

2

1

C2600

0201

16V X5R-CERM

0.1UF

10%

2

1

C2621

10%

1UF

402

X5R

10V

2

1

C2601

0201

10%

0.1UF

X5R-CERM

16V

2

1

C2622

10%

1UF

402

X5R

10V

2

1

C2602

10V X5R 402

1UF

10%

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

LPDDR3 DRAM Channel B (32-63)

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_B

MEM_B_ZQ<2> MEM_B_ZQ<3>

MEM_B_DQS_P<6>

=MEM_B_DQS_P<5> =MEM_B_DQS_P<6>

=MEM_B_DQS_P<4>

MEM_B_DQS_N<6>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<4> =MEM_B_DQS_N<5>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=MEM_B_DQ<61>

=MEM_B_DQ<59> =MEM_B_DQ<60>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DQ<53>

=MEM_B_DQ<52>

=MEM_B_DQ<51>

=MEM_B_DQ<50>

=MEM_B_DQ<49>

=MEM_B_DQ<48>

=MEM_B_DQ<47>

=MEM_B_DQ<46>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQ<42> =MEM_B_DQ<43>

=MEM_B_DQ<41>

MEM_B_DQ<32>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQ<34> =MEM_B_DQ<35>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

PP1V2_S3

PP1V8_S3

PP1V2_S3

MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9>

MEM_B_CKE<2> MEM_B_CKE<3>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CS_L<1>

PP1V2_S3

PP1V8_S3

MEM_B_CS_L<0>

MEM_B_ODT<0>

23 OF 76

<SCH_NUM>

26 OF 121

18 19 22 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

w w w . c h i n a f i x . c o m

IN IN IN

IN

IN IN IN IN

IN

IN IN IN

IN

IN IN IN

IN

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN IN IN

IN

IN IN IN

NC NC NCNC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Spare Spare

Intel reccomends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

2

1

C2702

201

CERM-X5R-1

20% 4V

0.47UF

2

1

C2704

4V

20% CERM-X5R-1

0.47UF

201

2

1

C2700

CERM-X5R-1

0.47UF

20% 4V

201

2

1

C2701

20% 4V

201

0.47UF

CERM-X5R-1

2

1

C2703

0.47UF

201

20% 4V CERM-X5R-1

2

1

C2706

0.47UF

20% 4V CERM-X5R-1 201

2

1

C2705

201

20% 4V

0.47UF

CERM-X5R-1

2

1

C2707

20% CERM-X5R-1

0.47UF

201

4V

2

1

C2709

0.47UF

4V

201

CERM-X5R-1

20%

20 63 70

7

20 63 70

7

20 70

7

20 70

7

20 70

7

21 70

21 63 70

20 63 70

7

20 70

20 63 70

21 63 70

20 63 70

7

21 63 70

63

RP2701

56

5%

1/32W

4X0201-HF

20 63 70

21 63 70

2

1

C2708

0.47UF

4V

20%

201

CERM-X5R-1

54

RP2701

1/32W

56

5%

4X0201-HF

72

RP2701

56

5%

1/32W

4X0201-HF

81

RP2701

56

5%

1/32W

4X0201-HF

22 63 70

2

1

C2712

0.47UF

CERM-X5R-1

4V

20%

201

2

1

C2714

CERM-X5R-1

0.47UF

201

20% 4V

2

1

C2716

CERM-X5R-1

0.47UF

201

20% 4V

2

1

C2718

CERM-X5R-1

0.47UF

20%

201

4V

2

1

C2719

0.47UF

20% 4V

201

CERM-X5R-1

2

1

C2717

CERM-X5R-1

4V

20%

201

0.47UF

2

1

C2715

CERM-X5R-1

0.47UF

201

20% 4V

2

1

C2713

CERM-X5R-1

0.47UF

201

20% 4V

2

1

C2711

CERM-X5R-1

0.47UF

4V

20%

201

2

1

C2710

0.47UF

20% CERM-X5R-1

4V 201

54

RP2712

1/32W

56

5%

4X0201-HF

22 63 70

7

22 63 70

7

22 70

7

22 70

7

22 70

7

22 70

22 63 70

23 63 70

7

23 63 70

7

23 70

7

23 70

7

23 70

7

23 70

23 63 70

7

21 70

7

21 70

7

21 70

23 63 70

7

22 23 70

7

22 23 70

7

22 23 63 70

20 63 70

7

20 21 70

7

20 21 70

7

20 21 63 70

21

R2700

MF

1/20W5%201

56

21

R2701

39

MF

201

5%

1/20W

21

R2702

39

MF

1/20W

201

5%

21

R2703

MF

1/20W

201

5%

82

21

R2704

82

201

1/20W

MF5%

21

R2705

201

1/20W

MF

56

5%

21

R2706

201

MF

1/20W

56

5%

54

RP2703

1/32W

56

5%

4X0201-HF

63

RP2703

1/32W

56

5%

4X0201-HF

72

RP2703

1/32W

5%

56

4X0201-HF

54

RP2707

1/32W

56

5%

4X0201-HF

63

RP2707

1/32W

56

5%

4X0201-HF

72

RP2707

1/32W

56

5%

4X0201-HF

81

RP2707

1/32W

56

5%

4X0201-HF

21

R2707

201

1/20W

MF

39

5%

21

R2708

201

MF

1/20W

39

5%

21

R2709

201

1/20W

MF

82

5%

21

R2720

201

MF

82

1/20W

5%

21

R2721

1/20WMF201

56

5%

54

RP2704

1/32W

56

5%

4X0201-HF

63

RP2704

1/32W

56

5%

4X0201-HF

72

RP2704

1/32W

56

5%

4X0201-HF

81

RP2704

1/32W

56

5%

4X0201-HF

21

R2722

201

1/20W

MF

82

5%

21

R2723

MF

201

1/20W

82

5%

21

R2724

1/20WMF201

82

5%

63

RP2712

1/32W

56

5%

4X0201-HF

72

RP2712

1/32W

56

5%

4X0201-HF

81

RP2712

1/32W

56

5%

4X0201-HF

21

R2710

201

1/20W

MF

56

5%

21

R2711

201

1/20W

MF

39

5%

21

R2712

20139MF

1/20W

5%

21

R2713

201

1/20W

MF

82

5%

21

R2714

201

1/20W

MF

82

5%

21

R2715

201

1/20W

MF

56

5%

21

R2716

201

MF

1/20W

56

5%

54

RP2713

1/32W

56

5%

4X0201-HF

63

RP2713

1/32W

56

5%

4X0201-HF

72

RP2713

1/32W

56

5%

4X0201-HF

54

RP2717

1/32W

56

5%

4X0201-HF

63

RP2717

1/32W

56

5%

4X0201-HF

72

RP2717

1/32W

56

5%

4X0201-HF

81

RP2717

1/32W

56

5%

4X0201-HF

21

R2717

201

1/20W

MF

39

5%

21

R2718

20139MF

1/20W

5%

21

R2719

201

1/20W

MF

82

5%

21

R2730

201

1/20W

MF

82

5%

21

R2731

1/20WMF201

56

5%

54

RP2714

1/32W

56

5%

4X0201-HF

63

RP2714

1/32W

56

5%

4X0201-HF

72

RP2714

1/32W

56

5%

4X0201-HF

81

RP2714

1/32W

56

5%

4X0201-HF

21

R2732

201

1/20W

MF

82

5%

21

R2733

201

1/20W

MF

82

5%

21

R2734

20182MF

1/20W

5%

21

R2725

201

MF

1/20W

56

5%

21

R2735

MF

1/20W

201

56

5%

2

1

C2720

PLACE_NEAR=RP2701.5:4mm

6.3V

20%

603

X5R-CERM-1

22UF

CRITICAL

2

1

C2740

PLACE_NEAR=RP2714.8:4mm

CRITICAL

20%

603

22UF

X5R-CERM-1

6.3V

81

RP2703

5%

56

4X0201-HF

1/32W

81

RP2713

5%

56

4X0201-HF

1/32W

LPDDR3 DRAM Termination

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

MEM_B_ODT<0>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CAB<0>

MEM_B_CAB<3> MEM_B_CAB<1>

MEM_B_CAB<2>

MEM_B_CAB<4>

MEM_B_CKE<3>

MEM_B_CKE<2>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CAB<5>

MEM_B_CAB<6>

MEM_B_CAB<7>

MEM_B_CAB<8>

MEM_B_CAB<9>

MEM_B_CAA<0>

MEM_B_CAA<1>

MEM_B_CAA<3>

MEM_B_CAA<2>

MEM_B_CAA<4>

PP0V6_S0_DDRVTT

MEM_B_CKE<1> MEM_B_CKE<0>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CAA<5>

MEM_B_CAA<6>

MEM_B_CAA<7>

MEM_B_CAA<8>

MEM_B_CAA<9>

MEM_A_ODT<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CAB<0>

MEM_A_CAB<1>

MEM_A_CAB<3>

MEM_A_CAB<2>

MEM_A_CAB<4>

MEM_A_CKE<3>

MEM_A_CKE<2>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_CAB<5>

MEM_A_CAB<7>

MEM_A_CAB<8> MEM_A_CAB<6>

MEM_A_CAB<9>

MEM_A_CAA<0>

MEM_A_CAA<1>

MEM_A_CAA<2>

MEM_A_CAA<3>

MEM_A_CAA<4>

PP0V6_S0_DDRVTT

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CAA<5>

MEM_A_CAA<7>

MEM_A_CAA<6>

MEM_A_CAA<9> MEM_A_CAA<8>

<SCH_NUM>

27 OF 121

24 OF 76

24 53 62 24 53 62

w w w . c h i n a f i x . c o m

OUT

IN

OUT

IN

OUT

IN

OUT OUT

IN

OUT

IN IN

OUT

BI

IN

BI

OUT IN

OUT

IN

OUT OUT

BI BI

IN

IN IN IN OUT

OUT OUT

BI BI

IN

OUT OUT OUT

OUT

IN

IN IN

IN

OUT

VCC

DO/IO1

GND

THRM_PAD

CS*

CLK

WP*

HOLD*

DI/IO0

IN

OUT

IN

MISC

PCIE GEN2

SYM 1 OF 2

PORTS

DISPLAY PORT

DPSNK1_1_P DPSNK1_1_N

DPSRC_AUX_N

DPSRC_AUX_P

XTAL_25_OUT

REFCLK_100_IN_N

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_CIO3_TX_N/DPSRC_2_N

PB_CIO3_RX_N

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO2_RX_N

PB_AUX_N

PA_DPSRC_3_N

PA_DPSRC_1_N

PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_RX_N

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_RX_N

PA_AUX_N

GPIO_8/EN_CIO_PWR_N_OD

DPSRC_3_N

DPSRC_2_N

DPSRC_1_N

DPSRC_0_N

DPSNK1_AUX_N

DPSNK1_3_N

DPSNK1_2_N

DPSNK1_0_N

DPSNK0_AUX_N

DPSNK0_3_N

DPSNK0_2_N

DPSNK0_1_N

DPSNK0_0_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

PETN_0

PETP_0

PETP_1 PETN_1

PETP_2

RSENSE

PETN_2

PETP_3 PETN_3

RBIAS

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P

GPIO_16/DEVICE_PCIE_RST_N

RSVD_GND

GPIO_19

GPIO_18

GPIO_17

XTAL_25_IN

TMU_CLK_OUT

GPIO_2/TMU_CLK_IN/AC_PRESENT

DPSRC_HPD_OD

DPSRC_2_P

DPSRC_3_P

DPSRC_1_P

DPSRC_0_P

GPIO_3/FORCE_PWR GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO3_TX_P/DPSRC_2_P

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

GPIO_15

GPIO_14

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PB_CIO3_RX_P

PB_DPSRC_1_P

PB_DPSRC_3_P

PB_DPSRC_HPD

PB_LSTX/CIO_3_LSEO PB_LSRX/CIO_3_LSOE

PB_AUX_P

PERP_0

PERP_1 PERN_1

PERP_2 PERN_2

PERN_3

PWR_ON_POC_RSTN

MONDC1

MONDC0

EE_DI

THERMDA

MONOBSN

MONOBSP

EE_DO

EE_CLK

TCK TDO TEST_EN TEST_PWR_GOOD

EE_CS_N

DPSNK0_3_P

DPSNK0_2_P

DPSNK0_1_P

DPSNK0_0_P

DPSNK0_HPD

DPSNK0_AUX_P

DPSNK1_3_P

DPSNK1_2_P

DPSNK1_HPD

DPSNK1_AUX_P

DPSNK1_0_P

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_P/DPSRC_2_P

PA_CIO0_TX_P/DPSRC_0_P

PA_DPSRC_3_P

PA_DPSRC_1_P

PA_CIO1_RX_P

PA_DPSRC_HPD

PA_AUX_P

PA_LSTX/CIO_1_LSEO PA_LSRX/CIO_1_LSOE

GPIO_12/PA_DP_PWRDN/BYP2

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

PERST_OD_N

TDI TMS

PERN_0

PERP_3

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

6 - PCIE_RST_2_N 7 - PCIE_RST_3_N

1 - GPIO_1

4 - GPIO_5

2 - GPIO_2 3 - GPIO_3

0 - GPIO_13

5 - PCIE_RST_1_N

11 - GPIO_0

10 - GPIO_14

12 - GPIO_12 13 - GPIO_10 14 - PB_LSTX 15 - PB_LSRX

9 - GPIO_11

8 - GPIO_15

NOTE: The following pins require testpoints:

Divides 3.3V to 1.8V

DEBUG: For monitoring clock

Use AA8 GND ball for THERM_DN

(TBT_SPI_CS_L)

If strap != bit then security is enabled?

Security strap setting is XORed with bit in the flash, so the active-level depends on the code in the flash.

Used for straps in host mode

(TBT_SPI_CLK)

(TBT_SPI_MOSI) (TBT_SPI_MISO)

SNK1 AC Coupling

SNK0 AC Coupling

DEBUG: For monitoring current/voltage

2

1

R2890

MF

1/20W

201

3.3K

5%

13

13 18

2

1

R2825

100

5%

MF

1/20W 201

28

28 71

28

28 71

18

64

18

64

2

1

R2830

MF

1/20W

201

100K

5%

2

1

R2831

MF

1/20W

201

100K

5%

28 71

2

1

R2893

MF

1/20W 201

3.3K

5%

21

C2829

0201

0.1UF

X5R-CERM

16V10%

13 67

5

67

5

67

5

67

5

67

5

67

5

67

5

67

5

67

21

C2828

0201

0.1UF

X5R-CERM

10% 16V

21

C2827

0201

0.1UF

X5R-CERM

16V10%

21

C2826

0201

0.1UF

X5R-CERM

10% 16V

21

C2825

0201

0.1UF

X5R-CERM

16V10%

21

C2824

0201

X5R-CERM

0.1UF

10% 16V

21

C2823

0201

0.1UF

X5R-CERM

16V10%

21

C2822

0201

0.1UF

X5R-CERM

10% 16V

2

1

R2855

1%

1K

201

1/20W MF

21

C2821

0201

0.1UF

X5R-CERM

16V10%

21

C2820

0201

0.1UF

X5R-CERM

16V10%

21

C2830

0201

0.1UF

X5R-CERM

16V10%

21

C2831

0201

0.1UF

X5R-CERM

16V10%

21

C2832

0201

0.1UF

X5R-CERM

16V10%

21

C2833

0201

0.1UF

X5R-CERM

16V10%

21

C2834

0201

X5R-CERM

0.1UF

16V10%

21

C2835

0201

0.1UF

X5R-CERM

16V10%

21

C2836

0201

0.1UF

X5R-CERM

16V10%

21

C2837

0201

0.1UF

X5R-CERM

16V10%

21

C2838

0201

0.1UF

X5R-CERM

16V10%

21

C2839

0201

X5R-CERM

0.1UF

16V10%

5

18 67

5

18 67

5

18 67

5

18 67

5

18 67

5

18 67

5

18 67

5

18 67

2

1

C2890

BYPASS=U2890::2mm

1UF

10%

6.3V CERM

402

13 18 67

28

64

18

15 18

64 71

18

15 16 18

18

15 16 18

18

28 71

28

25 27 28

28

25 28

25

18

25

25 26

33 37 38

12

17 69

21

R2895

201

MF

1/20W

1%

806

2

1

R2896

1/20W MF 201

1K

5%

2

1

R2899

MF

5%

1/20W

NO STUFF

10K

201

12 69

26

2

1

R2815

NONE

NOSTUFF

NONE NONE

OMIT

0201

2

1

R2888

5%

10K

201

1/20W

MF

2

1

R2887

10K

201

MF

1/20W

5%

2

1

R2886

NO STUFF

5%

201

1/20W MF

10K

2

1

R2885

NO STUFF

5%

10K

201

1/20W

MF

2

1

R2880

100K

MF

1/20W

201

5%

15

25

15 18

2

1

R2883

5%

201

1/20W MF

100K

3

8

9

7

4

25

1

6

U2890

4MBIT

USON

W25X40CLXIG

OMIT_TABLE

CRITICAL

25 27

25 28

2

1

R2861

5%

10K

201

1/20W MF

2

1

R2863

MF

1/20W

201

10K

5%

2

1

R2867

MF

1/20W

201

10K

5%

NO STUFF

2

1

R2862

MF

1/20W

201

10K

5%

2

1

R2881

MF

1/20W

201

5%

100K

2

1

R2829

10K

201

1/20W

MF

5%

2

1

R2884

100K

MF

1/20W

201

5%

2

1

R2882

MF

1/20W

201

5%

100K

15 18 25

2

1

R2878

100K

MF

1/20W

201

5%

2

1

R2879

5%

201

1/20W MF

100K

2

1

R2832

5%

201

1/20W

MF

100K

AB23

AA24

AA4

AB1

AB7

W8

R6

U6

W2

AA6

L8

AD1

U20

AB21 AD21

W20

R4

AD17

AD13

AD9

AD5

AD19

AD15

AD11

AD7

P5

AA18

AB15

AA12

AB9

AB19

AA16

AB13

AA10

V3

M5 P7

N6

A22 B23

A20 B21

M1

D3

W24 U24

W22 U22

R24 N24

R22 N22

K3 K1

N8 J6

M3

A18 B19

A16 B17

K5

P1

L24 J24

L22 J22

G24 E24

G22 E22

L4 L2

W18 W16

AC24

AD23

M7

V7

T7

Y1

Y7

H5

L6

U2

F1

V1

AD3

AB3

W6

T3

T1

F3P3

R2N2

R8

Y3

AA2

T5 U8

AC2

J4 J2

A14 B15

A12 B13

A10 B11

A8 B9

U4

H3 H1

E6 D5

E8 D7

E10

D9

E12 D11

AB5

G4 G2

E14 D13

E16 D15

E18 D17

E20 D19

U2800

CRITICAL

OMIT_TABLE

FALCON-RIDGE-FR2C

FCBGA

21

C2801

0.1UF

0201

10%

16V X5R-CERM

21

C2800

0201

10%

0.1UF

16V X5R-CERM

21

C2802

0201

10%

0.1UF

16V X5R-CERM

21

C2803

0201

10%

16V X5R-CERM

0.1UF

2

1

R2892

MF

1/20W

201

3.3K

5%

21

C2804

0.1UF

10%

X5R-CERM

0201

16V

21

C2805

0201

0.1UF

10%

16V X5R-CERM

21

C2806

0201

10%

0.1UF

16V X5R-CERM

21

C2807

0201

10%

0.1UF

16V X5R-CERM

21

C2840

16V10%

X5R-CERM

0.1UF

0201

21

C2841

16V10%

X5R-CERM

0.1UF

0201

21

C2842

16V10%

X5R-CERM

0.1UF

0201

2

1

R2891

MF

1/20W

201

3.3K

5%

21

C2843

16V10%

X5R-CERM

0.1UF

0201

21

C2845

16V10%

X5R-CERM

0.1UF

0201

21

C2844

16V10%

0.1UF

X5R-CERM

0201

21

C2846

10% 16V

0.1UF

X5R-CERM

0201

21

C2847

10% 16V

0.1UF

X5R-CERM

0201

14 69

SYNC_DATE=01/19/2013

SYNC_MASTER=T29_RR

Thunderbolt Host (1 of 2)

DP_TBTSNK1_ML_P<1> DP_TBTSNK1_ML_N<1>

NC_DP_TBTSRC_AUXCH_CN

NC_DP_TBTSRC_AUXCH_CP

TP_TBT_XTAL25OUT

PCIE_CLK100M_TBT_N

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_N<1>

NC_TBT_B_R2D_CN<1>

NC_TBT_B_D2RN<1>

NC_TBT_B_R2D_CN<0>

NC_TBT_B_D2RN<0>

NC_DP_TBTPB_AUXCH_CN

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_N<1>

TBT_A_R2D_C_N<1>

TBT_A_D2R_N<1>

TBT_A_R2D_C_N<0>

TBT_A_D2R_N<0>

DP_TBTPA_AUXCH_C_N

TBT_EN_CIO_PWR_L

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CN<2>

NC_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<0>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<0>

TBT_CIO_PLUG_EVENT_L

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_P<1> PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<2>

TBT_RSENSE

PCIE_TBT_D2R_C_N<2>

PCIE_TBT_D2R_C_P<3> PCIE_TBT_D2R_C_N<3>

TBT_RBIAS

TBT_CLKREQ_L

PCIE_CLK100M_TBT_P

TP_TBT_PCIE_RESET0_L

TBT_DFT_STRAP_3

TBT_ROM_SECURITY_XOR

TBT_DFT_STRAP_1

SYSCLK_CLK25M_TBT_R

TBT_TMU_CLK_OUT

TBT_GPIO2

DP_TBTSRC_HPD

TP_DP_TBTSRC_ML_CP<2>

TP_DP_TBTSRC_ML_CP<3>

NC_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CP<0>

TBT_PWR_EN SMC_PME_S4_DARK_L

HDMITBTMUX_SEL_TBT TBT_GPIO7

TBT_BATLOW_L

NC_TBT_B_D2RP<0>

NC_TBT_B_R2D_CP<0>

NC_TBT_B_R2D_CP<1>

TBT_B_CONFIG1_BUF TBT_B_CONFIG2_RC

TBT_DDC_XBAR_EN_L

TBTDP_AUXIO_EN

TBT_B_HV_EN TBT_B_CIO_SEL TBT_B_DP_PWRDN

NC_TBT_B_D2RP<1>

DP_TBTPB_ML_C_P<1>

DP_TBTPB_ML_C_P<3>

DP_TBTPB_HPD

NC_TBT_B_LSTX TBT_B_LSRX

NC_DP_TBTPB_AUXCH_CP

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_P<1> PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<2> PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_N<3>

TBT_PWR_ON_POC_RST_L

TP_TBT_MONDC1

TP_TBT_MONDC0

TBT_SPI_MOSI

TP_TBT_THERM_DP

TBT_MONOBSN

TBT_MONOBSP

TBT_SPI_MISO

TBT_SPI_CLK

XDP_JTAG_ISP_TCK JTAG_TBT_TDO TBT_TEST_EN TBT_TEST_PWR_GOOD

TBT_SPI_CS_L

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_HPD

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_HPD

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_P<0>

TBT_A_D2R_P<0>

TBT_A_CONFIG2_RC

TBT_A_CONFIG1_BUF

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_P<0>

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_P<1>

TBT_A_D2R_P<1>

DP_TBTPA_HPD

DP_TBTPA_AUXCH_C_P

TBT_A_LSTX TBT_A_LSRX

TBT_A_DP_PWRDN

TBT_A_CIO_SEL

TBT_A_HV_EN

PCH_TBT_PCIE_RESET_L

XDP_JTAG_ISP_TDI JTAG_TBT_TMS

PCIE_TBT_R2D_N<0>

PCIE_TBT_R2D_P<3>

PP3V3_TBTLC

TBT_B_DP_PWRDN TBT_A_HV_EN

PCIE_TBT_R2D_C_N<0>

SYSCLK_CLK25M_TBT

PP3V3_TBTLC

DP_TBTSNK0_ML_C_P<0>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_R2D_C_P<3>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK1_ML_P<0>

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_N<1>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<1>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<2>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_P<3>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_AUXCH_C_P

PCIE_TBT_D2R_P<2>

TBTROM_HOLD_L

TBTROM_WP_L

TBT_A_DP_PWRDN

TBT_B_HV_EN

TBT_BATLOW_L

PP3V3_S4

TBTDP_AUXIO_EN

TBT_DDC_XBAR_EN_L HDMITBTMUX_SEL_TBT

TBT_EN_CIO_PWR_L

PP3V3_S4

DP_TBTSRC_HPD

PP3V3_TBTLC

25 OF 76

28 OF 121

<SCH_NUM>

25 67

64

25 67

69

25

64

69

71

25 67

69

17 18 25 26 62 64

25

25 27 28

17 18 25 26 62 64

25 67

25 28

25

25 27

25 26 27 29 33 36 38 39 58 62 64

25 28

25

15 18 25

25 26

25 26 27 29 33 36 38 39 58 62 64

25

17 18 25 26 62 64

w w w . c h i n a f i x . c o m

NC

VER 3

D

S G

VOUT

GND

ON

VIN

IN

OUT

IN

D

SYM_VER_3

S G

G

VER 5

S D

OUT

GND

SENSE

ENABLE SENSE_OUT

CT

VCC

VCC1P0_CIO

VSS

VCC3P3_RDV_DECAP

VCC3P3_LC

VCC3P3

VCC1P0_RDV_DECAP

SVR_VCC1P0

VSS

SVR_AMON

SVR_IND

GND

VCC

SYM 2 OF 2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U2940

Pull-up (S0) on PCH page

3.1 W (Dual-Port)

TPS22920

Push-pull output

Isolated to reduce noise from SVR

Part

Type

R(on)

@ 1.05V

Max Current = 4A (85C)

8 mOhm Typ

11.5 mOhm Max

Load Switch

1.05V TBT "CIO" Switch

EDP: 1.25 A

25 mA EDP

1200 mA EDP

700 mA EDP

1900 mA EDP

SVR input to RR - 1100 mA EDP

2.4 W (Single-Port)

100 mA EDP

Internal switch not functional on RR.

Delay = 4.04ms nominal

TBT "POC" Power-up Reset

Vth = 2.508V nominal

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

POC input to RR - 150 mA EDP

2

1

C2906

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2911

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2910

0201-1

X5R

6.3V

1.0UF

20%

2

1

C2922

6.3V

CERM-X5R

0402-1

10UF

20%

2

1

C2923

6.3V

CERM-X5R

0402-1

10UF

20%

K

A

D2920

NSR1020MW2T1G

SOD-323

CRITICAL

1

2

6

Q2945

DMN5L06VK-7

SOT563

2

1

R2945

100K

201

MF

1/20W

5%

C1

B1

A1

C2

B2

A2

D2

D1

U2940

CSP

TPS22920

CRITICAL

2

1

C2940

X5R

6.3V

0201-1

1.0UF

20%

2

1

C2981

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2980

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2970

0201-1

6.3V X5R

20%

1.0UF

25

2

1

C2960

0201-1

6.3V X5R

1.0UF

20%

2

1

C2961

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2953

20%

10UF

0402-1

CERM-X5R

6.3V

2

1

C2952

6.3V

CERM-X5R

0402-1

10UF

20%

2

1

C2951

6.3V

CERM-X5R

0402-1

10UF

20%

2

1

C2950

6.3V

CERM-X5R

0402-1

10UF

20%

2

1

XW2960

PLACE_NEAR=C2953.1:1mm

SM

25

2

1

R2991

1/20W MF 201

24.9K

1%

2

1

C2990

X5R

10%

0.1UF

25V

402

15

2

1

R2995

MF

201

100K

1/20W

5%

17 27 37 38

2

1

R2990

100K

1/20W MF 201

5%

2

1

3

Q2995

DFN1006H4-3

DMN32D2LFB4

2

1

C2991

X7R-CERM

10% 50V

0.001UF

0402

4

5

3

Q2945

DMN5L06VK-7

SOT563

13

6

4

3

2

1

5

U2990

TPS3895ADRY

USON

CRITICAL

2

1

R2992

1/20W

100K

201

MF

5%

Y9

AC12

Y23

Y21

Y19

Y17

Y15

Y13

Y11

V9

V23

V21

AC10

V13

U16

U12

T9

T23

T21

T17

T13

R20

R16

AB17

R12

P9

P23

P21

P13

N20

N16

N12

M9

M23

AB11

M21

M13

L20

L12

K23

K21

K13

J20

J16

J14AA8

H23

H21

G8

G6

G20

F9

F7

F5

F23

F21

AA22

F19

F17

F15

F13

F11

E4

D23

D21

C8

C6

AA20

C4

C24

C22

C20

C2

C18

C16

C14

C12

C10

AA14

B7

B1

AC8

AC6

AC4

AC22

AC20

AC18

AC16

AC14

A24

A2

W10

R18

N18

L18

H7

H17

H15

H13

Y5

W4

V5

N4

H11

E2

D1

K17

K15

J18

H9

H19

G18

G16

W14

G14

W12

V17

V15

U18

T19

P19

M19

L16

K7

K19

G12

G10

R10

P15

P11

N14

N10

M11

L10

K11

V11

U14

U10

T15

T11

R14

J12

J10

V19

P17

M17

M15

L14

K9

J8

B3

A6

A4

B5

U2800

CRITICAL

OMIT_TABLE

FALCON-RIDGE-FR2C

FCBGA

21

L2920

CRITICAL

0.68UH-20%-4.2A-0.032OHM

PIMB041B-SM

2

1

C2995

0201

16V X7R

10%

330PF

2

1

C2903

0201-1

6.3V X5R

1.0UF

20%

2

1

C2920

20%

10UF

0402-1

CERM-X5R

6.3V

2

1

C2921

6.3V

CERM-X5R

0402-1

10UF

20%

2

1

C2904

20%

6.3V X5R

0201-1

1.0UF

2

1

C2905

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2900

0201-1

6.3V X5R

1.0UF

20%

2

1

C2901

1.0UF

X5R

6.3V

20%

0201-1

2

1

C2902

0201-1

6.3V X5R

1.0UF

20%

2

1

C2932

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2931

20%

1.0UF

X5R

6.3V

0201-1

2

1

C2930

20%

1.0UF

X5R

6.3V

0201-1

Thunderbolt Host (2 of 2)

SYNC_MASTER=T29_RR

SYNC_DATE=12/17/2012

TBTPOCRST_MR_L

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V05_TBTCIO

PP3V3_S4_TBT_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MMMIN_LINE_WIDTH=0.38 MM

MIN_NECK_WIDTH=0.20 MM

PP3V3_TBTRDV

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_TBTLC

PP1V05_TBTRDV

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.20 MM

PP1V05_TBT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.50 MM

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.20 MM

P1V05TBT_SW

TBT_POC_RESET_L

SMC_DELAYED_PWRGD

PP3V3_S0

PP3V3_S4

TBTPOCRST_SENSE

PP1V05_TBT

TBTPOCRST_CT

TBT_PWR_ON_POC_RST_L

PP3V3_TBTLC

TBT_EN_CIO_PWR

TBT_EN_CIO_PWR_L

PP3V3_S0

TBT_PWR_REQ_L

PP3V3_S4

<SCH_NUM>

29 OF 121

26 OF 76

62 64

17 18 25 26 62 64

26 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

25 26 27 29 33 36 38 39 58 62 64

26 64

17 18 25 26 62 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

25 26 27 29 33 36 38 39 58 62 64

w w w . c h i n a f i x . c o m

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

SYM_VER_2

G S

D

VER 3

D

S G

VER 3

D

S G

OUT

D

SYM_VER_3

S G

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

- =PPVIN_SW_TBTBST (8-13V Boost Input)

(NONE)

- =PP15V_TBT_REG (15V Boost Output)

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

for 2S.

UVLO(falling) = 1.22 * (R1 + R2) / R2

TBT 15V Boost Regulator

Max Vgs: 10V

add property on another page.

Voltage not specified here,

Rds(on): 46mOhm @ 4.5V Vgs

Vds(max): -30V

SI8409DB:

Vgs(max): +/-12V

Id(max): 3.7A @ 70C

Vgs(th): -1.4V

<R1>

UVLO = 4.55V (falling), 4.95 (rising)

UVLO(rising) = UVLO(falling) + (2uA * R1)

<R2>

Vout = 15.1V Max Current = 1.0A Freq = 300KHz

<Ra>

<Rb>

Vout = 1.6V * (1 + Ra / Rb)

GND inside package, no XW necessary.

SGND shorted to

8-13V Input Changes required

Pull-up on RR page

BATLOW# Isolation

25 28

2

1

R3080

470K

MF

1/20W

201

5%

2

1

C3080

10% 25V X5R 402

0.1UF

2

1

R3092

1%

73.2K

MF

1/20W

201

2

1

R3087

330K

MF

1/20W

201

5%

2

1

R3094

1%

41.2K

MF

1/20W

201

2

1

C3094

10%

6.3V CERM-X5R 402

0.33UF

2

1

R3088

330K

MF

1/20W

201

5%

17 26 37 38

2

1

C3089

50V CERM 402

100PF

NO STUFF

5%

2

1

R3096

402

MF-LF

1/16W

1%

15.8K

2

1

C3095

X5R-CERM 0603

20% 25V

10UF

2

1

C3092

X5R-CERM

20% 10V

402

2.2UF

4

1

32

Q3080

SI8409DB

BGA

CRITICAL

2

1

R3091

1%

200K

MF

1/20W

201

2

1

C3090

X5R-CERM

20% 25V

0603

10UF

2

1

C3091

X5R-CERM

20% 25V

0603

10UF

27

30

34

382120

9

8

32

372423

4

3

6

33

36

35

10

2

1

28

1716151413

12

31

25

U3090

QFN

LT3957

CRITICAL

2 1

XW3095

PLACE_NEAR=C3095.1:2 mm

SM

21

R3089

MF

1/20W

0201

0

5%

KA

D3095

CRITICAL

DFLS230L

POWERDI-123

2

1

C3099

10% 50V X7R-CERM 0402

0.001UF

2

1

C3093

10%

0201

3300PF

10V X7R-CERM

2

1

R3081

150K

MF

1/20W

201

5%

2

1

R3093

1%

10K

MF

1/20W

201

2

1

R3095

402

MF-LF

1/16W

1%

133K

21

L3095

CRITICAL

6.8UH-4.0A

PIMB062D-SM

1

2

R3090

402

49.9K

1% 1/16W MF-LF

2

1

C3082

X5R-CERM

20% 10V

402

2.2UF

2

1

C3081

X5R-CERM

2.2UF

402

10V

20%

2

1

C3096

X5R-CERM

20% 25V

0603

10UF

2

1

C3097

X5R-CERM

20% 25V

0603

10UF

2

1

C3098

X5R-CERM

20% 25V

0603

10UF

2

1

C3084

X5R-CERM

20% 25V

0603

10UF

2

1

C3085

X5R-CERM

10UF

0603

25V

20%

2

1

C309B

X5R-CERM

20% 25V

0603

10UF

2

1

C309A

X5R-CERM

10UF

0603

25V

20%

2

1

3

Q3005

DMN32D2LFB4

DFN1006H4-3

1

2

6

Q3088

DMN5L06VK-7

SOT563

4

5

3

Q3088

DMN5L06VK-7

SOT563

25 27

2

1

3

Q3000

DMN32D2LFB4

DFN1006H4-3

13 37

2

1

C3087

C0G

25V

5%

47PF

0201

2

1

C3088

22PF

5% 50V CER-C0G 0402

TBT Power Support

SYNC_DATE=12/17/2012SYNC_MASTER=WILL_J43

TBTBST_FBX

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

TBTBST_VSNS_RC

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

GND_TBTBST_SGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

TBTBST_VC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

TBTBST_INTVCC

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_S4SW_TBTBST_FET

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

TBTBST_SNS1

TBTBST_VSNS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

TBTBST_BOOST

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

TBTBST_SNS2

TBT_BATLOW_L

MAKE_BASE=TRUE

PM_BATLOW_L

TBT_BATLOW_L

PP3V3_S4

SMC_DELAYED_PWRGD

TBTBST_SHDN_DIV

TBTBST_EN_UVLO

PP15V_TBT

TBTBST_VC_RC

TBTBST_SS

TBTBST_RT

TBT_A_HV_EN

TBTBST_PWREN_DIV_L

PPBUS_G3H

TBTBST_PWREN_L

<SCH_NUM>

30 OF 121

27 OF 76

25 27

25 26 29 33 36 38 39 58 62 64

28 62 64

41 42 49 50 56 62 64

w w w . c h i n a f i x . c o m

IN IN

OUT

IN IN

IN

OUT

BI IN

IN

OUT

OUT OUT

OUT

IN IN

BI BI

IN IN

OUT

TB+

LSRX

AUX+

CA_DET

DPMLO+ DPMLO-

HPD

THMPAD

GND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENA

TB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN IN

IN

V3P3

ISET_V3P3

OUT

THRM

GND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

ML_LANE2N

ML_LANE2P

ML_LANE1N

ML_LANE1P

GND

HOT_PLUG_DETECT

CONFIG2

ML_LANE0P ML_LANE0N

GND

RETURN

AUX_CHN

CONFIG1

ML_LANE3N

ML_LANE3P

AUX_CHP

DP_PWR

SHIELD PINS

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

3.3V/HV Power MUX

wake from Thunderbolt devices.

Sink HPD range:

15.75V Max

ISET_Sx with CD3210.

TBT: RX_1

TBT: RX_0

TBT: TX_1

For 12V systems:

12V: See

Single R on ISET_V3P3 OK.

requires two R’s per HV

below

Single-fault protection

Nominal Min Max

<RV3P3>

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

(IPU)

(IPD)

(IPU)

TBT: RX_1

TBT: LSX_A_R2P/P2R (P/N)

High: 2.0 - 5.0V

Low: 0 - 0.8V

DP Source must pull

down HPD input with greater than or equal

to 100K (DPv1.1a).

TBT: LSX_R2P/P2R (P/N)

(Both C’s)

DP Dir

(0-18.9V)

TBT: TX_0

TBT Dir

(Both C’s)

on AC-coupled signals.

(Both C’s)

TBT Dir

DP Dir

(Both C’s)

ILIM = 40000 / RISET

Nominal Min Max IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

V3P3 must be S4 to support

IV3P3 1100mA 1030mA 1200mA

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

(0-18.9V)

470k R’s for ESD protection

Thunderbolt Connector A

TBT: Unused

514-0818

2

1

C3200

0.01UF

X7R-CERM

0402

10% 50V

25 71

2

1

C3202

0.01UF

X5R-CERM

10% 16V

0201

21

R3201

MF

1/20W

201

5%

12

2

1

C3201

0.01UF

X7R-CERM 0402

10% 50V

2

1

R3294

5%

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

1/20W

MF

201

1K

2

1

R3295

5%

1K

MF 201

1/20W

GND_VOID=TRUE

NO_XNET_CONNECTION=TRUE

2

1

R3241

5%

100K

MF 201

1/20W

2

1

C3286

10UF

CERM-X5R 0402

20%

6.3V

2

1

C3285

0.1UF

0201

10% 16V

X5R-CERM

2

1

C3281

0.1UF

16V

10%

0201

X5R-CERM

2

1

C3280

X5R-CERM-1

603

6.3V

20%

22UF

2

1

C3287

CRITICAL

POLY-TANT

CASE-B2-SM

20%

6.3V

100UF

2

1

R3252

5%

1M

MF

201

1/20W

2

1

R3251

5%

1M

MF 201

1/20W

21

L3200

FERR-120-OHM-3A

0603

CRITICAL

25

2

1

C3210

402

25V X5R

10%

0.1UF

2

1

R3270

5%

GND_VOID=TRUE

1/20W

201

MF

470K

2

1

R3271

5%

GND_VOID=TRUE

1/20W

201

MF

470K

21

C3271

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

21

C3270

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

25 71

21

C3272

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

21

C3273

GND_VOID=TRUE

6.3V

20%

0201

X5R

0.22UF

2

1

R3273

5%

GND_VOID=TRUE

1/20W

201

MF

470K

2

1

R3272

5%

GND_VOID=TRUE

1/20W

201

MF

470K

25 27

18 58 59

57 59

2

1

R3212

36.5K

MF 201

1% 1/20W

2

1

C3211

402

25V X5R

10%

0.1UF

2

1

C3220

X5R-CERM

16V

10%

0201

0.1UF

25

13 18

25

25 71

21

C3232

X5R

0201

20%

6.3V

0.22UF

21

C3233

X5R

0201

20%

6.3V

0.22UF

25 71

21

C3230

0201

X5R-CERM

16V10%

0.1UF

21

C3231

16V10%

X5R-CERM

0.1UF

0201

25 71

21

C3278

X5R

0201

20%

6.3V

0.22UF

21

C3279

X5R

0201

20%

6.3V

0.22UF

25 71

2

1

R3211

TBTHV:P15V

22.6K

MF 201

1% 1/20W

2

1

R3210

TBTHV:P15V

22.6K

MF

201

1%

1/20W

2

1

R3214

1/20W

1%

201

MF

22.6K

TBTHV:P15V

2

1

R3213

1/20W

1%

201

MF

22.6K

TBTHV:P15V

2

1

C3215

25V

4.7UF

X5R-CERM

0603

10%

2

1

C3205

25V

GND_VOID=TRUE

10%

0201

X5R-CERM

0.01UF

2

1

C3206

25V

0.01UF

X5R-CERM

0201

10%

GND_VOID=TRUE

25

21

C3274

20%

0.47UF

CERM-X5R-1

201

GND_VOID=TRUE

4V

21

C3275

20%

0.47UF

CERM-X5R-1

GND_VOID=TRUE

4V

201

3

25

8

7 15

14

13

12 17

21

9

19

20

6

11

10

4

5

16 18

22

23

24

2

1

U3220

CRITICAL

CBTL05024

SIGNAL_MODEL=TBT_MUX

HVQFN24-COMBO

25

2

1

R3279

5%

470K

MF

201

1/20W

2

1

R3278

5%

470K

MF 201

1/20W

21

C3277

CERM-X5R-1

GND_VOID=TRUE

20%

0.47UF

4V

201

21

C3276

CERM-X5R-1

GND_VOID=TRUE

20%

0.47UF

4V

201

7

6

18

20

19

21

17

14

12

8

9

1011

15

13

321

4

16

5

U3210

CRITICAL

QFN

CD3211A1RGP

19

10 12

15 17

9 11

3 5

28272625242322

21

2

14 8

13 7

1

20

6

4

16 18

J3200

MDP-J11

CRITICAL

F-RT-TH

2

1

C3294

0201

16V X7R

10%

330PF

2

1

C3295

0201

16V X7R

10%

330PF

R3211,R3214

118S0145

TBTHV:P12V

2

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

2

R3210,R3213

TBTHV:P12V

118S0145

RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

Thunderbolt Connector A

SYNC_MASTER=T29_RR

SYNC_DATE=10/26/2012

TBT_A_CONFIG2_RC

TBT_A_CONFIG1_RC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_S4_TBTAPWR

VOLTAGE=15V

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3_S4_TBTAPWR

VOLTAGE=18V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_S4_TBTAPWR_F

MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBTACONN_7_C

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MM

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM

TBT_A_R2D_N<1>

TBT_A_R2D_P<1>

DP_A_LSX_ML_N<1>

DP_A_LSX_ML_P<1>

TBT_A_HPD

TBT_A_D2R_C_N<0>

TBT_A_R2D_P<0> TBT_A_R2D_N<0>

TBT_A_D2R1_AUXDDC_N

TBT_A_D2R_C_P<0>

DP_TBTPA_ML_N<3>

DP_TBTPA_ML_P<3>

TBT_A_D2R1_AUXDDC_P

TBT_A_CIO_SEL

TBTDP_AUXIO_EN

TBT_A_DP_PWRDN

TBT_A_D2R1_AUXDDC_P

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_N<1>

DP_TBTPA_AUXCH_C_P

TBT_A_D2R_P<0>

TBT_A_D2R_N<0>

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_N<3>

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

TBT_A_R2D_C_N<0>

PP3V3_S4_TBTAPWR

TBT_A_CONFIG1_RC

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

TBT_A_HPD

DP_TBTPA_ML_P<1>

DP_TBTPA_ML_N<1>

DP_TBTPA_AUXCH_N

TBT_A_D2R1_AUXDDC_N

TBT_A_CONFIG1_BUF

DP_TBTSNK0_DDC_CLK

DP_TBTSNK0_DDC_DATA

TBT_A_LSTX

TBT_A_LSRX

DP_TBTPA_HPD

TBTAPWRSW_ISET_S0_R

TBTAPWRSW_ISET_S3_R

DP_TBTPA_AUXCH_P

DP_TBTPA_AUXCH_C_N

TBT_A_D2R_C_N<1>

TBT_A_D2R_N<1>

TBT_A_D2R_C_P<1>

TBT_A_D2R_P<1>

PP15V_TBT

TBTAPWRSW_ISET_S3

TBTAPWRSW_ISET_S0

S4_PWR_EN

TBT_A_HV_EN

TBTAPWRSW_ISET_V3P3

PP3V3_S5

PM_SLP_S3_BUF_L

<SCH_NUM>

32 OF 121

28 OF 76

28

28 62

71

28 71

28

71

28 71

71

28 71

28 62

28

28 71

28

71

28 71

71

27 62 64

8

11 13 15 16 17 18 29 34

42 57 58 59 60 62 64 74

w w w . c h i n a f i x . c o m

IN

OUT OUT

OUT

NC

BI

IN

GND

VOUTONVIN

IN

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

RESET*

+

-

PAD

(OD)

DLY

VREF

IN

DP_2

DM_2

DM_1

DP_1

S

DP

GND

VDD

OE*

DM

OUT

SYM_VER_2

G S

D

IN

GND

VCC

A

B0 B1

S

VER-3

OUT OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Supervisor & CLKREQ# Isolation

Delay = 130 ms +/- 20%

AIRPORT

Sense resistor on

sensor page

Type

R(on) @ 2.5V

Part

18.5 mOhm Typ

Load Switch

25.8 mOhm Max

TPS22924C

3.3V WLAN Switch

514S0335

Max Current = 2A (85C)

SEL OUTPUT

H USB_BT (2)

L BT_WAKE (1)

BLUETOOTH

H AP_S0IX_WAKE_L (B1)

L PCIE_WAKE_L (B0)

SEL OUTPUT

PCIe Wake Muxing

14 69

12 64 69

2

1

C3521

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=J3501:5mm

14 64 69

2

1

C3532

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=J3501:1.5mm

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

21

20

19

J3501

SSD-K99

F-RT-SM1

CRITICAL

37 38 64

2

1

C3510

10%

0.1UF

0201

CERM-X5R

6.3V

14 68

12

29 37 39

2

1

R3553

5%

201

1/20W

MF

100K

APCLKRQ:ISOL

2

1

R3554

201

1/20W MF

1%

232K

2

1

R3555

201

1/20W MF

1%

100K

2

1

C3540

10%

0.1UF

0201

CERM-X5R

6.3V

21

C3531

10%

0.1UF

X5R-CERM

16V 0201

21

C3530

10%

0.1UF

X5R-CERM

0201

16V

B1

A1

B2

A2

C2

C1

U3550

CRITICAL

CSP

TPS22924

29 37 39

2

1

C3550

X5R

6.3V

1.0UF

20%

0201-1

2

1

R3556

5%

0

0201

1/20W MF

APCLKRQ:ISOL

2 1

R3557

5%

0

0201

1/20W

MF

APCLKRQ:BIDIR

1

9

2

4

8

3

7

5

6

U3540

SLG4AP041V

TDFN

CRITICAL

21

R3558

5%

0

0201

1/20W

MF

2 1

R3559

5%

0

0201

1/20W

MF

NOSTUFF

15

5

4

3

8

6

2

10

7

1

9

U3510

SIGNAL_MODEL=BT_MUX

DFN

USB3740

CRITICAL

36 37 39

2

1

R3512

201

1/20W MF

1%

15K

2

1

3

Q3510

DMN32D2LFB4

NO_XNET_CONNECTION=TRUE

DFN1006H4-3

13 18 36 37 59

5

6

2

1

3

4

U3560

CRITICAL

SC70

NC7SB3157P6XG

13 31 64

2

1

C3560

10%

0.1UF

0201

CERM-X5R

6.3V

15

21

R3560

5%

0

0201

1/20W

MF

NOSTUFF

2

1

R3561

5%

201

1/20W MF

100K

SYNC_DATE=02/06/2013

Wireless Connector

SYNC_MASTER=J41_MLB

AP_S0IX_WAKE_SEL

AP_S0IX_WAKE_L

PCIE_WAKE_L

PP3V3_S5

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_WLAN

MIN_LINE_WIDTH=0.5 mm

AP_RESET_L

AP_CLKREQ_L

PCIE_AP_R2D_C_P

WIFI_EVENT_L

AP_CLKREQ_R_L

PCIE_AP_R2D_N

PCIE_AP_R2D_P

PP3V3_WLAN_R

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

SMC_WIFI_PWR_EN

PP3V3_S5

SMC_WIFI_PWR_EN

PCIE_AP_R2D_C_N

P3V3WLAN_VMON

AP_RESET_CONN_R_L

PM_SLP_S4_L

USB_BT_N

USB_BT_P

SMC_PME_S4_WAKE_L

BT_WAKE

PP3V3_S4

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

PP3V3_S4

PCIE_AP_D2R_N

PCIE_AP_D2R_P

AP_RESET_CONN_L

AP_CLKREQ_Q_L

PP3V3_S5

AP_PCIE_WAKE_L

USB_BT_CONN_N

USB_BT_CONN_P

<SCH_NUM>

35 OF 121

29 OF 76

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

37 38 39 41 64

64 69

41

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

25 26 27 29 33 36 38 39 58 62 64

64

8

11 13

15 16 17

18 28 29

34 42 57

58 59 60

62 64 74

64 68

w w w . c h i n a f i x . c o m

OUT

IN

NC

08

NC

IN

IN IN

OUT

IN

OUT

NC

08

IN

NC

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Supervisor & CLKREQ# Isolation

are only permitted on the device side, provided the device PHY supports it.

PCIe polarity inversion and lane reversal

Gumstick3 Connector

GND_VOID

OOB Isolation

514S0449

GND_VOID

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

Delay = ~55ms

SMC_PWRFAIL_WARN_L Signal no connect on X31

37

2

1

C3702

10%

0.1UF

10V X5R-CERM 0201

PLACE_NEAR=L3700.1:1mm

21

L3700

0603

PLACE_NEAR=J3700.1:3mm

FERR-26-OHM-6A

CRITICAL

2

1

C3701

10%

0.1UF

PLACE_NEAR=L3700.1:1mm

10V X5R-CERM 0201

2

1

R3742

201

MF

1%

100K

1/20W

2

1

R3740

201

100K

1/20W

MF

5%

2

1

R3741

201

1%

MF

1/20W

232K

12

2

1

C3740

10%

0201

6.3V CERM-X5R

0.1UF

15

15 30 58 59 64

4

6

5 3

1

2

U3711

74LVC1G08

CRITICAL

BYPASS=U3711:5 mm

SOT891

2

1

C3719

10%

0.1UF

0201

X5R-CERM

10V

12 67

21

C3716

10%

0.1UF

GND_VOID=TRUE

16V

0201

X5R-CERM

21

C3717

10%

0.1UF

16V

0201

X5R-CERM

GND_VOID=TRUE

21

C3713

10%

0.1UF

GND_VOID=TRUE

X5R-CERM

16V

0201

21

C3712

10%

0.1UF

GND_VOID=TRUE

X5R-CERM

16V

0201

21

C3715

10%

0.1UF

GND_VOID=TRUE

16V

0201

X5R-CERM

21

C3714

10%

0.1UF

GND_VOID=TRUE

X5R-CERM

16V

0201

21

C3711

10%

0.1UF

X5R-CERM

16V

0201

GND_VOID=TRUE

21

C3710

10%

0.1UF

0201

16V

X5R-CERM

GND_VOID=TRUE

12 64 67

15 30 58 59 64

37 64

30 64

9

8

7

63

62

61

60

6

59

58

57

56

55

54

53 52

51

50

5

49

48 47

46 45

44 43

42

41 40

4

39

38 37

36 35

34

33

32

31 30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3700

SSD-GS3

TRUE

TRUE TRUE

TRUE

CRITICAL

TRUE

F-RT-SM

TRUE

2

1

R3700

NOSTUFF

201

100K

1/20W

MF

1%

4

6

53

1

2

U3710

74LVC1G08

CRITICAL

SOT891

37

2

1

C3718

10%

0.1UF

10V

0201

X5R-CERM

BYPASS=U3710:5 mm

2

1

R3710

NOSTUFF

201

100K

1/20W

MF

5%

1

9

2

4

8

3

7

5

6

U3740

SLG4AP016V

TDFN

CRITICAL

15 64

21

R3701

NOSTUFF

0

MF

02015%1/20W

13

2

1

R3703

1%

MF

1/20W

100K

201

21

R3702

0201

0

1/20W

MF

5%

SYNC_DATE=02/20/2013

SYNC_MASTER=J43_MLB

SSD Connector

PCIE_SSD_D2R_N<3>

SSD_BOOT

SSD_BOOT_R

SSD_SR_EN_L

PP3V3_S0SW_SSD

MIN_NECK_WIDTH=0.15mm

MIN_LINE_WIDTH=0.6mm

PP3V3_S0SW_SSD_FLT

VOLTAGE=3.3V

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_N<0>

PP3V3_S0

PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_P<1>

PCIE_SSD_R2D_N<2>

PCIE_SSD_R2D_P<3>

PCIE_SSD_R2D_N<3>

PCIE_SSD_R2D_P<2>

PCIE_SSD_R2D_P<0>

SMC_OOB1_D2R_L

PP3V3_S0

PP3V3_S0SW_SSD

SMC_OOB1_R2D_L

SMC_OOB1_R2D_CONN_L

SSD_PWR_EN

TP_SSD_DEVSLP SMC_PWRFAIL_WARN_L

PCIE_SSD_D2R_P<3>

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_N<2>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_P<0>

P3V3SSD_VMON

PP3V42_G3H

SSD_CLKREQ_CONN_L

SSD_RESET_L

SSD_PWR_EN SSD_CLKREQ_L

SSD_RESET_CONN_L

PP3V3_S0SW_SSD

PCIE_SSD_R2D_C_P<1>

SMC_OOB1_D2R_CONN_L

SSD_PCIE_SEL_L

<SCH_NUM>

37 OF 121

30 OF 76

30 41 62 64

64

64 67

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

64 67

8

11 12 13 15 17 18

26 30 36 38 39 40 41

42 43 44 45 56 59 61

62 64 65 74

30 41 62 64

64

17 35 36 37 38 40 46 49 50 59 61 62 64 65

64

30 41 62 64

64

30 64

w w w . c h i n a f i x . c o m

NC NC

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

SYM 1 OF 3

DEBUG_15

DEBUG_14

PWR_MODE

SENSOR_WAKE*

PCIE_WAKE*

PCIE_CLKREQ*

JTAG_SRST*

JTAG_TRST*

JTAG_TMS

JTAG_TDO

PCIE_REFCLKN

DEBUG_03 DEBUG_04 DEBUG_05

DEBUG_09

PCIE_RDP0

DEBUG_06

DEBUG_00 DEBUG_01 DEBUG_02

DEBUG_07 DEBUG_08

DEBUG_10 DEBUG_11 DEBUG_12 DEBUG_13

DEBUG_16

GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07

I2C_CLK_DBG I2C_CLK_SENSOR I2C_DATA_DBG I2C_DATA_SENSOR

JTAG_TCK JTAG_TDI

MIPI_CP_CLK

PCIE_RDN0

PCIE_REFCLKP

PCIE_RST*

PCIE_TDN0

RESET*

SHUTDOWN*

UARTCTS UARTRTS

UARTRXD UARTTXD

XTAL_N

XTAL_P

MIPI_DM0

MIPI_DP0

MIPI_CM_CLK

PCIE_TDP0

PCIE_TESTN

MIPI_DP1 MIPI_DM1

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

TEST_OUT

TEST_MODE

PCIE_TESTP

SYM 2 OF 3

DDR_CK_N0

DDR_CK_P0

DDR_CAS*

DDR_RAS*

DDR_CKE

DDR_AD00 DDR_AD01 DDR_AD02 DDR_AD03 DDR_AD04 DDR_AD05 DDR_AD06 DDR_AD07 DDR_AD08 DDR_AD09 DDR_AD10 DDR_AD11 DDR_AD12 DDR_AD13 DDR_AD14

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CS*

DDR_DM0 DDR_DM1

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15

DDR_DQS_N0

DDR_DQS_N1

DDR_DQS_P0

DDR_DQS_P1

DDR_RESET*

DDR_WE*

DDR_ZQ

SYM 3 OF 3

SR_VLXD_O

VDD_1P35A

PCIE_GND

XTAL_AVDD1P2

VDDC

VDD1P8_O

SR_VLXC_O

SR_VDD_3P3D

SR_VDD_3P3C

SR_PVSSD

SR_PVSSC

PMU_AVSS

OTP_VDD3P3

DDR_VDDIO_CK

MIPI_AGND

VDD_3P3A

DDR_VREF

VSSC

XTAL_AVSS

DDR_VDDIO

PCIE_VDD1P2

VSENSE_D

VSENSE_C

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

VDD1P2_O

VDDO18

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

BI BI BI

BI BI

OUT OUT OUT

IN

OUT

IN

OUT

NC

OUT

NC NC NC

NC

NC NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(=PP3V3_S3RS0_CAMERA)

L3901:1 L3902:1

A1 SILICON BUG

PU = 25MHz

PD = 1.35V

PU on PCH page

12

32

32 64

2

1

R3930

MF

1/20W

5%

NOSTUFF

100K

201

2

1

R3932

NOSTUFF

1/20W

5%

201

MF

100K

18

15 18

2

1

C3900

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C3924

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C3923

X5R

6.3V

20%

0201-1

1.0UF

2

1

C3922

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C3921

X5R

6.3V

1.0UF

0201-1

20%

2

1

C3910

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U3900.D6:2.54MM

2

1

C3951

BYPASS=U3900.D6:2.54MM

6.3V CERM-X5R 0201

0.1UF

10%

2

1

R3901

5%

201

1/20W MF

100K

32 69

2

1

R3906

5%

201

1/20W MF

CAM_XTAL:YES

100K

2

1

R3907

5%

201

1/20W MF

CAM_XTAL:NO

100K

2

1

R3904

5%

201

1/20W MF

100K

21

L3901

1008

PLACE_NEAR=U3900.M13:4MM

1.0UH-1.6A-55MOHM

21

L3902

PLACE_NEAR=U3900.K13:4MM

1008

1.0UH-1.6A-55MOHM

21

L3906

22NH

0402

2

1

C3916

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U3900.L7:2.54MM

2

1

C3919

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U3900.J1:2.54MM

2

1

C3937

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U3900:5mm

2

1

C3935

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U3900:5mm

2

1

C3940

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U3900:5mm

2

1

C3941

6.3V

BYPASS=U3900.F15:2.54MM

2.2UF

20%

402-LF

CERM

2

1

C3939

10% X5R

BYPASS=U3900.G15:2.54MM

1UF

10V

402

2

1

C3960

10%

0.1UF

0201

CERM-X5R

6.3V

A13

A12

E14

E13

D14

D13

J12

M10

C12

C13

H12

R13

E15

G12

N12

B9

C9

A8 B8

R14

B10 A10

B7 A7

P13

P6

P8

R6

R8

P7

R7

D11

D12

F12

E12

F13

C11

R9

C15

R10

D15

N9

N10

N11

P9

P10

P11

P12

R12

L10

L11

K10

K11

J10

H10

H11

G10

G11

F10

F11

E10

E11

A15

B14

C14

B11

U3900

CRITICAL

BCM15700

FBGA

OMIT_TABLE

G3

J2

R3

H3

A2

E2

A3

D2

B3

B2

C5

A5

B4

B1

C3

B5

F2

F4

F1

F3

D3

E4

E3

C2

C4

C1

L4

J3

H2 G2

H4

K2

L2

K3

R4

P1

L1

R2

J4

P2

P3

N2

P4

M2

M1

M3

N3

M4

L3

U3900

BCM15700

CRITICAL

FBGA

OMIT_TABLE

B12

B13

G8

G7

G6

G1

E5

D5

E9

R5

R1

P5

D1

N1

M9

A14

K9

K8

K7

K6

K5

K1

J9

B6

J8

J7

J6

J5

H9

H8

H7

H6

H5

G9

A6

A1

K12

M11

R11

B15

L9

L8

L5

L6

F9

F8

F7

F6

J11

F14

G15

F15

K14

K13

N14

M13

J15

J14

J13

H15

H14

N15

M15

M14

L15

L14

L13

L12

K15

R15

P15

P14

N13

M12

G14

D6

C8

D9

C7

C10

D7

L7

N6

N8

N7

N5

G5

N4

K4

G4

D4

A4

J1

U3900

CRITICAL

BCM15700

FBGA

OMIT_TABLE

32 72

32

2

1

R3910

5%

201

1/20W MF

NO STUFF

100K

2

1

R3911

5%

201

1/20W MF

100K

21

R3912

201

1/20W

MF

1%

240

2

1

R3913

5%

201

1/20W

MF

1K

2

1

R3914

5%

201

1/20W

MF

1K

32 72

21

XW3900

SM

21

XW3901

SM

2

1

R3990

5%

201

1/20W MF

100K

2

1

C3990

10%

0.1UF

0201

CERM-X5R

6.3V

NOSTUFF

2

1

C3927

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C3930

X5R

6.3V

1.0UF

20%

0201-1

32 72

2

1

C3932

X5R

6.3V

0201-1

1.0UF

20%

2

1

C3931

20%

10UF

6.3V CERM-X5R 0402-1

2

1

C3933

20%

10UF

6.3V CERM-X5R 0402-1

2

1

R3915

5%

201

1/20W MF

CAM_A1

100K

21

L3903

0603

220-OHM-1.4A

21

L3904

220-OHM-1.4A

0603

21

R3991

NOSTUFF

5%

0

0201

1/20W

MF

13 29 64

2

1

C3975

BYPASS=U3900.L9:2.54MM

CERM-X5R 0201

0.1UF

10%

6.3V

2

1

C3974

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U3900.L9:2.54MM

2

1

C3972

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U3900.F9:2.54MM

2

1

C3970

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U3900.F6:2.54MM

2

1

R3975

5%

201

1/20W MF

51K

2

1

R3976

5%

201

1/20W MF

51K

2

1

R3920

5%

201

1/20W MF

100K

2

1

R3921

5%

201

1/20W MF

100K

2

1

R3934

NOSTUFF

1/20W

5%

201

MF

100K

2

1

R3931

MF

1/20W

5%

330K

201

2

1

R3933

MF

1/20W

5%

330K

201

2

1

R3935

MF

5%

330K

201

1/20W

2

1

R3936

5%

201

1/20W

MF

100K

NOSTUFF

2

1

R3937

5%

201

1/20W

MF

100K

NOSTUFF

2

1

C3912

X5R

6.3V

BYPASS=U3900.K13:2.54MM

402

20%

4.7UF

2

1

C3913

X5R

6.3V

402

20%

4.7UF

2

1

C3914

X5R

6.3V

20%

4.7UF

402

2

1

C3915

X5R

6.3V

4.7UF

402

20%

PLACE_NEAR=U3900.M13:2.54MM

2

1

C3926

X5R

6.3V

PLACE_NEAR=U3900.M14:2.54MM

402

20%

4.7UF

2

1

C3928

X5R

6.3V

402

20%

4.7UF

2

1

C3942

X5R

6.3V

402

BYPASS=U3900:7mm

20%

4.7UF

32 72

2

1

C3918

BYPASS=U3900.J1:2.54MM

1000PF

10% 16V X7R-1 0201

2

1

C3934

BYPASS=U3900:3mm

0201

X7R-1

16V

10%

1000PF

2

1

C3917

BYPASS=U3900.L7:2.54MM

1000PF

10% 16V X7R-1 0201

2

1

C3936

BYPASS=U3900:3mm

0201

X7R-1

16V

10%

1000PF

2

1

C3938

BYPASS=U3900.D7:2.54MM

0201

X7R-1

16V

10%

1000PF

2

1

C3973

BYPASS=U3900.F9:2.54MM

0201

X7R-1

16V

10%

1000PF

2

1

C3971

BYPASS=U3900.F6:2.54MM

1000PF

10% 16V X7R-1 0201

SYNC_MASTER=J43_MLB1

Camera 1 of 2

SYNC_DATE=01/09/2013

PP1V2_CAM

PP3V3_S3RS0_CAMERA

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V8_CAM

PP1V2_CAM_PCIE_VDD_FLT

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V2_CAM_SRVLXC_PHASE

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

GND_CAM_PVSSD

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V35_CAM_SRVLXD_PHASE

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

GND_CAM_PVSSC

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PP1V2_CAM_PCIE_PVDD_FLT

PP1V35_DDR_CLK

VOLTAGE=1.35V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP0V675_CAM_VREF

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

PP1V2_CAM_XTALPCIEVDD

MIN_NECK_WIDTH=0.2MM

PP1V2_CAM

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.35V

PP1V35_CAM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

PCIE_CLK100M_CAMERA_C_N

CLK25M_CAM_CLKN

PCIE_CAMERA_D2R_C_N

MIPI_DATA_N

MIPI_CLK_N

MIPI_CLK_P

GND_CAM_PVSSD

PP1V2_CAM_XTALPCIEVDD

PCIE_CAMERA_R2D_N

MEM_CAM_DQ<6>

PP1V8_CAM

P1V2_CAM_SRVLXC_PHASE

PP1V8_CAM

I2C_CAM_SMBDBG_DAT

I2C_CAM_SMBDBG_CLK

GND_CAM_PVSSC

PP1V35_CAM

PP1V2_CAM

MEM_CAM_ZQ_S2

MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2>

MEM_CAM_A<6>

MEM_CAM_A<8> MEM_CAM_A<9>

MEM_CAM_A<11> MEM_CAM_A<12>

MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2>

MEM_CAM_CLK_P MEM_CAM_CLK_N

MEM_CAM_DM<0> MEM_CAM_DM<1>

MEM_CAM_CKE MEM_CAM_CS_L

MEM_CAM_DQ<15>

MEM_CAM_DQ<14>

MEM_CAM_DQ<13>

MEM_CAM_DQ<12>

MEM_CAM_DQ<11>

MEM_CAM_DQ<10>

MEM_CAM_DQ<9>

MEM_CAM_DQ<8>

MEM_CAM_DQ<7>

MEM_CAM_DQ<5>

MEM_CAM_DQ<4>

MEM_CAM_DQ<3>

MEM_CAM_DQ<2>

MEM_CAM_DQ<1>

MEM_CAM_DQ<0>

CAM_JTAG_SRST_L

CAMERA_PWR_EN

CAM_SENSOR_WAKE_L

TP_CAM_JTAG_TMS

TP_CAM_JTAG_TDI TP_CAM_JTAG_TDO

TP_CAM_JTAG_TRST_L CAM_JTAG_SRST_L

TP_CAM_JTAG_TCK

I2C_CAM_SMBDBG_DAT

I2C_CAM_SMBDBG_CLK

MIPI_DATA_P

PCIE_CAMERA_R2D_P

PP1V8_CAM

CAM_DEBUG_RESET_L

CAM_PWR_SEL

CAM_XTAL_SEL

PP1V8_CAM

CAM_XTAL_FREQ

CAM_UARTCTS

CAM_UARTRXD

CLK25M_CAM_CLKP

P1V35_CAM_SRVLXD_PHASE

CAMERA_CLKREQ_L

PP1V2_CAM_XTALPCIEVDD

MEM_CAM_DQS_P<0> MEM_CAM_DQS_N<0>

MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1>

MEM_CAM_RAS_L MEM_CAM_WE_L MEM_CAM_CAS_L MEM_CAM_RESET_L

CAM_TEST_MODE

PP1V8_CAM

PCIE_WAKE_L

CAM_TEST_OUT

CAM_PCIE_RESET_L CAM_PCIE_WAKE_L

I2C_CAM_SCK

I2C_CAM_SDA

PCIE_CLK100M_CAMERA_C_P

GND_CAM_PVSSC

PP1V2_CAM_XTALPCIEVDD

TP_CAM_LV_JTAG_TMS

TP_CAM_LV_JTAG_TDO

TP_CAM_LV_JTAG_TDI

TP_CAM_LV_JTAG_TCK

TP_CAM_TEST_MODE2

TP_CAM_TEST_MODE1

TP_CAM_TEST_MODE0

TP_CAM_LV_JTAG_TRSTN

CAM_XTAL_SEL

CAM_TEST_OUT CAM_TEST_MODE

CAM_XTAL_FREQ

TP_CAM_UARTRTS

CAM_RAMCFG0

CAM_RAMCFG2

CAM_RAMCFG1

TP_CAM_UARTTXD

CAM_UARTRXD

CAM_UARTCTS

CAM_GPIO3 TP_CAM_PLL_BYPASS

PCIE_CAMERA_D2R_C_P

MEM_CAM_A<10>

MEM_CAM_A<7>

MEM_CAM_A<5>

MEM_CAM_A<4>

MEM_CAM_A<3>

PP1V8_CAM

MEM_CAM_A<13> MEM_CAM_A<14>

GND_CAM_PVSSD

CAM_RAMCFG2 CAM_RAMCFG1 CAM_RAMCFG0

PP1V8_CAM

<SCH_NUM>

39 OF 121

31 OF 76

31

15 41

31

32 72

17 31

31

31 32 72

31

17 31

31 32

31

31 32

31

31 32 72

31

31 32

31

31 32

31

17 31

31

31 32

31

31 32

w w w . c h i n a f i x . c o m

OUT

IN

BI

IN

BI

BI IN

A4

A14

DQSL*

DQL1

VDD

A2 A3

A1

A0

NC

A6

ODT

RESET*

VSSQ

VSS

CAS*

RAS*

BA2

BA0 BA1

DQL7

DQL4

DQL3

DQL2

DQL0

ZQ

DQU3

DQU2

DQU4

CS*

CKE

DQU7

DQU6

DQSU*

DQU0

DQSL

A13

A11

A10/AP

A8

A5

A7

A9

CK

DML DMU

DQL5 DQL6

DQSU

DQU1

DQU5

VREFCA

VREFDQ

CK*

WE*

VDDQ

A12/BC*

NC NC NC NC NC

BI BI BI BI BI BI BI BI

BI BI

IN IN

BI BI BI BI BI BI BI BI

IN

IN IN IN

IN

IN IN IN IN IN IN IN IN IN IN IN IN IN IN

IN IN IN

IN

SYM_VER-1

NC NC

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

96.2 mA peak

77.2 mA nominal max

ALS

NOTE: TBD PPM crystal required

518S0892

CAMERA SENSOR

31 69

14 69

21

C4033

X5R-CERM

0201

16V

0.1UF

10%

21

C4032

X5R-CERM

0201

16V

0.1UF

10%

21

C4031

16V

0201

X5R-CERM

0.1UF

10%

21

C4030

16V

0201

X5R-CERM

0.1UF

10%

14 69

31 69

21

R4009

CAM_XTAL:YES

MF

1/20W

0201

0

5%

21

R4010

CAM_XTAL:YES

MF

1/20W

0201

0

5%

21

R4008

CAM_XTAL:NO

MF

1/20W

020105%

21

R4007

CAM_XTAL:YES

MF

1/20W

020105%

21

R4000

1/20W

MF020105%

2

1

C4004

20% 4V CERM-X5R-1

0.47UF

BYPASS=U4000.H9:4mm

201

2

1

C4008

BYPASS=U4000.K2:4mm

X5R-CERM

20%

2.2UF

10V

402

2

1

C4006

BYPASS=U4000.D2:4mm

2.2UF

X5R-CERM

10V

20%

402

2

1

R4012

NOSTUFF

1M

1%

MF

1/20W

201

2

1

C4009

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C4007

BYPASS=U4000.R9:4mm

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C4013

20%

CERM

10V

0.1uF

402

31 64

2

1

C4005

6.3V CERM-X5R 0201

0.1UF

10%

31 72

2 1

L4010

FERR-120-OHM-1.5A

0402-LF

2

1

C4003

0402-1

CERM-X5R

6.3V

10UF

20%

BYPASS=U4000.B2:4mm

2

1

C4002

0402-1

CERM-X5R

6.3V

10UF

20%

BYPASS=U4000.A1:4mm

14 37 40 43 44 64 69 73

2

1

R4022

1K

1% MF

1/20W

201

2

1

R4023

1K

1%

MF

1/20W

201

L8

L3

G9G1F9E8E2D8D1B9B1

P9P1M9M1J8J2G8

E1

T9

T1

B3

A9

H1

M8

H9H2F1E9D2C9C1A8A1

R9R1N9N1K8K2G7D9B2

T2

J3

K1

M7

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

T7

T3

N7

R7

L7

P7

N3

U4000

4GB-DDR3-256MX16

H5TC4G63AFR

FBGA

CRITICAL

31 72

2

1

C4011

CERM-X5R

6.3V

0201

0.1UF

10%

31 72

2

1

C4010

6.3V

CERM-X5R

0201

0.1UF

10%

31 72

31

31 72

2

1

R4020

1%

84.5

MF

1/20W

201

31 72

2

1

R4021

NO STUFF

1%

82

MF

1/20W

201

31 72

2

1

R4002

1K

MF

1/20W

201

5%

2

1

R4003

NOSTUFF

1K

MF

1/20W

201

5%

2

1

R4004

1%

240

MF

1/20W

201

21

R4030

CAM_WAKE:YES

MF

1/20W

020105%

2

1

R4031

CAM_WAKE:NO

MF

1/20W

0201

0

5%

9

8

7

6

5

4

3

2

12

11

10

1

13

14

J4002

F-RT-SM

CRITICAL

CCR20-AK7100-1

21

C4061

X5R-CERM

0201

16V

0.1UF

10%

21

C4062

X5R-CERM

0201

16V

0.1UF

10%

2 1

L4011

NOSTUFF

0402-LF

FERR-120-OHM-1.5A

31 72

2

1

C4016

100PF

CAM_XTAL:NO

C0G

25V

5%

0201

2

1

R4006

NO STUFF

0201

5% 25V C0G

100PF

21

C4015

12PF

CERM

25V

5%

0201

CAM_XTAL:YES

21

C4014

0201

5%

25V

CERM

12PF

CAM_XTAL:YES

4

32

1

L4009

TAM0605

CRITICAL

PLACE_NEAR=J4002.2:2.54MM

90-OHM-0.1A-0.7-2GHZ

4

32

1

L4007

90-OHM-0.1A-0.7-2GHZ

PLACE_NEAR=J4002.2:2.54MM

CRITICAL

TAM0605

3 1

4 2

Y4000

CAM_XTAL:YES

SM-3.2X2.5MM

25.000MHZ-12PF-20PPM

CRITICAL

31 69

12 69

2

1

R4005

100K

MF

1/20W 201

5%

17 69

SYNC_DATE=09/14/2012

SYNC_MASTER=J43_MLB

Camera 2 of 2

MIPI_DATA_N

MIPI_DATA_P

MIPI_DATA_CONN_P

MIPI_DATA_CONN_N

MIPI_CLK_N

MIPI_CLK_P

MIPI_CLK_CONN_P

MIPI_CLK_CONN_N

PP5V_S3RS0_ALSCAM_F

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP0V675_MEM_CAM_VREFCA

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.675V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.675V

PP0V675_MEM_CAM_VREFDQ

MEM_CAM_CKE_R

CLK25M_CAM_CLKN

CAM_SENSOR_WAKE_L_CONN

MEM_CAM_DM<1>

MEM_CAM_A<14>

I2C_CAM_SCK

MEM_CAM_CLK_N

MEM_CAM_CLK_P

PP5V_S4RS3

MEM_CAM_BA<0> MEM_CAM_BA<1> MEM_CAM_BA<2>

MEM_CAM_A<11>

MEM_CAM_WE_L

MEM_CAM_DM<0>

MEM_CAM_CKE

PCIE_CLK100M_CAMERA_C_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAMERA_N

PCIE_CAMERA_D2R_C_N

MEM_CAM_CS_L

MEM_CAM_CAS_L

MEM_CAM_RAS_L

MEM_CAM_A<9>

MEM_CAM_A<8>

MEM_CAM_A<7>

MEM_CAM_A<1> MEM_CAM_A<2>

MEM_CAM_DQ<13>

MEM_CAM_DQ<9>

MEM_CAM_DQS_P<1>

MEM_CAM_DQ<6>

MEM_CAM_DQ<5>

MEM_CAM_DQS_P<0>

MEM_CAM_DQ<14> MEM_CAM_DQ<15>

MEM_CAM_DQ<12>

MEM_CAM_DQ<10> MEM_CAM_DQ<11>

MEM_CAM_DQ<0>

MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4>

MEM_CAM_DQ<7>

MEM_CAM_DQ<1>

MEM_CAM_DQS_N<0>

CLK25M_CAM_CLKP

PCIE_CAMERA_R2D_C_N

PCIE_CAMERA_D2R_C_P

PCIE_CAMERA_R2D_N

PCIE_CAMERA_D2R_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_R2D_P

SYSCLK_CLK25M_CAMERA

PCIE_CAMERA_R2D_C_P

CLK25M_CAM_XTALP_R

MEM_CAM_A<6>

MEM_CAM_A<0>

PP1V8_CAM

MEM_CAM_RESET_L

MEM_CAM_ZQ_DDR

PCIE_CLK100M_CAMERA_P

CAM_SENSOR_WAKE_L

MEM_CAM_DQ<8>

PP5V_S0

SMBUS_SMC_1_S0_SDA SMBUS_SMC_1_S0_SCL

I2C_CAM_SDA

MEM_CAM_A<5>

PP0V675_CAM_VREF

CAM_SENSOR_WAKE_L_CONN

MEM_CAM_DQS_N<1>

MEM_CAM_A<13>

MEM_CAM_A<12>

MEM_CAM_A<10>

MEM_CAM_A<3>

MEM_CAM_ODT

MEM_CAM_A<4>

PP1V35_CAM

CLK25M_CAM_XTALP

CLK25M_CAM_XTALN

<SCH_NUM>

40 OF 121

32 OF 76

64 72

64

72

32 64

35 47 49 54 55 58 62 64

69

31

16 17 45 51 52 56 58 59 61 62 64

31 72

32 64

72

31 72

69

w w w . c h i n a f i x . c o m

OUT

BI

OUT

BI BI

IN

BI

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW CARD_DETECT_GND

DAT6 DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

CLK CMD

DAT0

SHLD_PIN

SHLD_PIN SHLD_PIN

SHLD_PIN

NC NC NC NC

NC

DET_OUT

DET_IN

RST_IN*

DET_CHNGD*

LOW_PWR

RST_OUT*

VDD

THRM

GND PAD

(IPU)

(OD)

DLY

XOR

LOGIC

RST

OUT

Y A

B

NC

GND

VCC

NC

VER 3

D

S G

VER 3

D

S G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

To SMC

To PCH

DLY block is 20ms nominal

FROM SD CONN ->

(IPU)

SDCONN_STATE_CHANGE Isolation

(CARD INSERTED = GROUND)

516-0253

SD CARD CONNECTOR

34 75

21

R4479

5%

201

1/20W

MF

33

21

L4400

0402

47NH-1.3OHM

CRITICAL

2

1

C4470

5%

15PF

50V

402

CERM

NOSTUFF

2

1

C4471

5% CERM

22PF

NOSTUFF

50V 402

21

R4471

5%

0

0201

1/20W

MF

21

R4472

5%

0

0201

1/20W

MF

21

R4473

5%

0

0201

1/20W

MF

21

R4474

5%

0

0201

1/20W

MF

21

R4461

5%

0

0201

1/20W

MF

2

1

C4430

BYPASS=U4430.1:5mm

0201

10% 16V

0.1UF

X5R-CERM

16

6

3

4

20

19

18

17

13

12

11

10

9

8

7

2

5

1

14

15

J4400

F-RT-TH-1

SD-CARD-K16

CRITICAL

1

9

4

3

2

5

7

6

8

U4430

TDFN

SLG4AP014V

CRITICAL

34 75

2

1

R4410

5%

201

1/20W MF

470K

2

1

R4411

5%

201

1/20W

MF

470K

2

1

C4410

BYPASS=U4410.5:5mm

6.3V

CERM-X5R

0.1UF

10%

0201

15 16

2

1

C4472

5%

NOSTUFF

402

10PF

50V CERM

2

1

C4473

5%

10PF

50V

NOSTUFF

402

CERM

2

1

C4474

5%

NOSTUFF

402

10PF

50V CERM

2

1

C4475

5%

NOSTUFF

402

CERM

10PF

50V

2

1

C4476

5%

NOSTUFF

CERM

10PF

50V 402

21

R4480

5%

0

402

1/16WMF-LF

21

R4481

5%

0

1/16W

402

MF-LF

2

1

R4482

5%

0

402

NOSTUFF

MF-LF

1/16W

4

6

5

3

1

2

U4410

74AUP1G09

SOT891

CRITICAL

4

5

3

Q4410

SOT563

DMN5L06VK-7

1

2

6

Q4410

SOT563

DMN5L06VK-7

SD CARD

SYNC_MASTER=MASTER

SD READER CONNECTOR

SYNC_DATE=07/01/2011

SD_CD_L

SDCONN_CLK_L

SDCONN_R_DATA<3>

SDCONN_CMD

SDCONN_DATA<3>

SDCONN_DATA<1> SDCONN_DATA<2>

SDCONN_CLK_R1

SDCONN_DETECT_L

PP3V3_S4

SDCONN_CLK

PP3V3_S0_SD_CONN

SD_CONN_CLK

SDCONN_DATA<0>

SDCONN_R_DATA<2>

SDCONN_CLK_R2

SDCONN_CMD_R

SDCONN_R_DATA<1>

SDCONN_WP

SDCONN_R_DATA<0>

SMC_PME_S4_DARK_L

XDP_SDCONN_STATE_CHANGE_L

PP3V3_S4

PP3V3_S3

SMC_PME_S4_DARK_L

SMC_PME_SDCONN

SDCONN_STATE_CHANGE_SAK_L

<SCH_NUM>

44 OF 121

33 OF 76

25 26 27 29 33 36 38 39 58 62 64

34

25 33 37 38

25 26 27 29 33 36 38 39 58 62 64

15 18 19 36 40 41 58 62 64

25 33 37 38

w w w . c h i n a f i x . c o m

VCC

GND

THRM

CS*

HOLD*

DIO(IO0)

DO(IO1)

CLK

WP*

PAD

NC

GND

VDD

D

SON

CAP

IN

OUT

IN

BI

IN

BI BI BI BI

NC

PAD

PMOS33

AVDD12

AVDD33

DVDD12

DVDD33

V33IN

DVDD33

VUHSI

NC

NC NC

NC

RTERM

RSTZ*

RXP

X1 X2

RXN

DP

DM

THRM

GND

LED

SD_WP

TXP

TXN

SD_D3

SD_D2

SD_D1 SD_D0

SPI_CS

SD_CLK

SD_CMD SD_CDZ

SPI_SO

SPI_SI

SPI_CK

NC NC NC NC NC NC NC NC NC

OUT

NC

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

900mA max

USING ON CHIP CLOCK SOURCE MODE (CRYSTAL AS BACK-UP)

15 mOhm Typ

(IPU)

U4550

Load Switch

EDP: 1.05A

SLG5AP1438V

17 mOhm Max

2.5A

R(on)

Type

Part

NO USB 2.0 INTERFACE

Current

3.3V S3 SD Card Switch

21

C4513

PLACE_NEAR=U4500.2:5mm

0.1UF

GND_VOID=TRUE

0201

16V10%

X5R-CERM

2

1

R4580

5%

0

0201

1/20W

MF

3

8

9

7

4

2

5

1

6

U4590

NOSTUFF

W25X05CL

USON

512KB

2

1

R4582

5%

201

1/20W MF

1M

21

R4581

5%

0

0201

1/20W

MF

31

42

Y4580

CRITICAL

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

2 1

C4580

5%

25V

12PF

NP0-C0G-CERM

0201

21

C4512

PLACE_NEAR=U4500.1:5mm

0201

0.1UF

GND_VOID=TRUE

16V10%

X5R-CERM

21

C4581

5%

NP0-C0G-CERM

25V

0201

12PF

1

52

8

37

U4550

TDFN

SLG5AP1443V

CRITICAL

2

1

C4561

201

4700PF

10V

10% X7R

2

1

C4570

201

6.3V

0.047UF

X5R

10%

2

1

C4521

BYPASS=U4500.38:5mm

402

6.3V

20%

X5R

4.7UF

2

1

C4550

BYPASS=U4500.39:5mm

4.7UF

20%

6.3V

402

X5R

21

R4570

5%

201

1/20W

MF

3.3K

14 65 68

21

C4511

X5R-CERM

10%

0201

16V

GND_VOID=TRUE

0.1UF

PLACE_NEAR=U4500.5:5mm

21

C4510

PLACE_NEAR=U4500.4:5mm

0.1UF

16V10%

0201

X5R-CERM

GND_VOID=TRUE

33 75

2

1

R4500

201

1/20W

MF

1%

680

2

1

C4520

BYPASS=U4500.21:5mm

X5R-CERM

4V

0201

20%

2.2UF

2

1

C4522

0201-1

X5R-CERM

10%

6.3V

BYPASS=U4500.22:5mm

1.0UF

2

1

C4526

X5R-CERM

BYPASS=U4500.9:5mm

10%

0.1UF

0201

16V

2

1

C4528

402-LF

CERM

2.2UF

6.3V

20%

BYPASS=U4500.43:5mm

2

1

C4527

0201

16V

10%

BYPASS=U4500.43:5mm

X5R-CERM

0.1UF

2

1

C4524

X5R-CERM

0201

BYPASS=U4500.3:5mm

10% 16V

0.1UF

2

1

C4523

BYPASS=U4500.46:5mm

X5R-CERM

0201

0.1UF

10% 16V

2

1

C4525

0201-1

1.0UF

10%

6.3V

X5R-CERM

BYPASS=U4500.3:5mm

2

1

C4531

0201-1

BYPASS=U4500.30:5mm

10%

1.0UF

6.3V

X5R-CERM

2

1

C4530

5%

100PF

NP0-CERM

25V

0201

BYPASS=U4500.30:5mm

2

1

C4529

5%

0201

NP0-C0G-CERM

47PF

25V

BYPASS=U4500.30:5mm

21

L4500

FERR-1000-OHM-450MA

CRITICAL

0402

21

L4501

FERR-1000-OHM-450MA

0402

CRITICAL

8

7

30

22

2

1

47

37

36

34

35

23

28

29

24

25

27

26

20

5

4

10

41

39

32

19

18

17

16

15

14

13

12

11

33

6

403831

42

21

44

45

43

9463

U4500

GL3219

LQFN

CRITICAL

OMIT_TABLE

14 65 68

2

1

C4590

0201-1

BYPASS=U4590.8:5mm

X5R-CERM

6.3V

10%

1.0UF

2

1

R4590

5%

201

1/20W

MF

3.3K

2

1

R4591

5%

201

1/20W MF

3.3K

15

14 65 68

2

1

C4560

0201-1

1.0UF

X5R

6.3V

20%

BYPASS=U4550.A2:5mm

2

1

R4595

5%

201

1/20W

MF

10K

NOSTUFF

15

2

1

C4519

X5R-CERM

BYPASS=U4500.42:5mm

0201

16V

10%

0.1UF

2

1

C4518

X5R-CERM

0201

10%

0.1UF

BYPASS=U4500.31:5mm

16V

SD CONTROLLER (GL3219)

SYNC_MASTER=MASTER

SYNC_DATE=10/11/2010

PP3V3_S5

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V2_S3_SD_DVDD12

VOLTAGE=1.2V

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V2_S0_SD_VUHS1

VOLTAGE=3.3V

PP3V3_S0_SD_AVDD33

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

SDCONN_CLK

SDCONN_CMD

SDCLK_CLK25M_X2_R

SD_RTERM

PP1V2_S0_SD_AVDD12

MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 MM

SD_SPI_MOSI

SD_PWR_EN

USB3_SD_D2R_N

USB3_SD_D2R_P

PP3V3_S0_SD_CONN

USB_SD_DM

MAKE_BASE=TRUE

VOLTAGE=3.3VMIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.20MM

PP3V3_S0_SD_CONN

USB_SD_DP

SD_RESET_L

SDCONN_DATA<3>

SDCONN_DATA<0>

P3V3_SD_FET_RAMP

PP3V3_S0SW_SD

SDCLK_CLK25M_X2

SDCONN_DATA<1>

SDCONN_DATA<2>

SDCONN_WP

SD_SPI_CS_L

USB3_SD_D2R_C_P

SDCONN_DETECT_L

USB3_SD_R2D_N USB3_SD_R2D_P

SDSCLK_CLK25M_X1

SD_RESET_R_L

USB3_SD_R2D_C_P

USB3_SD_R2D_C_N

SD_SPI_CLK

SD_SPI_HOLD_L

SD_SPI_WP_L

PP3V3_S0SW_SD

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

SD_SPI_MISO

USB3_SD_D2R_C_N

<SCH_NUM>

34 OF 76

45 OF 121

8

11 13 15 16 17 18 28 29 42

57 58 59 60 62 64 74

69 75

75

33 34

15 34 37 39 65

69

75

68

69

75

15 34 37 39 65

75

68

w w w . c h i n a f i x . c o m

SYM_VER-1

OUT

IN

GND

SSRX-

SXRX+

GND

D+

GND

SSTX+ SSTX-

D-

VBUS

FAULT*

IN_1

IN_0

ILIM

OUT1 OUT2

EN

GND

THRM

PAD

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

BI BI

IN OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Current limit per port (R4600+R4601): 2.19A min / 2.76A max

H USB (D)

Mojo SMC Debug Mux

SEL OUTPUT

APN: 514-0819

USB Port Power Switch

Right USB Port A

L SMC (M)

2

1

C4605

0.01UF

16V

0201

X5R-CERM

10%

4 3

21

L4600

DLP0NS

90-OHM

CRITICAL

14 68

21

C4620

GND_VOID=TRUE

6.3V

CERM-X5R 0201

0.1UF

10%

21

C4621

GND_VOID=TRUE

6.3V

CERM-X5R 0201

0.1UF

10%

1

8

2

3

9

18

17

16

15

14

13

12

11

10

7

4

6

5

J4600

CRITICAL

F-RT-TH

USB3.0-J11-J13

2

1

R4601

1%

22.1K

1/20W MF 201

9

7

6

3

2

5

1

8

4

U4600

TPS2557DRB

CRITICAL

SON

1 2

9

10

8

5 4

3

7 6

U4650

CRITICAL

TQFN

PI3USB102EZLE

SIGNAL_MODEL=MOJO_MUX_SMSC

2

1

C4650

BYPASS=U4650.9:3:5mm

0201

X5R-CERM

10V

0.1UF

10%

2

1

R4650

201

100K

MF

1/20W

5%

14 68

37 38 68

37

2

1

D4601

0201-THICKSTNCL

CRITICAL

ESD112-B1-02ELS

2

1

D4600

ESD112-B1-02ELS

CRITICAL

0201-THICKSTNCL

2

1

D4620

GND_VOID=TRUE

ESD112-B1-02ELS

CRITICAL

0201-THICKSTNCL

2

1

D4621

GND_VOID=TRUE

0201-THICKSTNCL

CRITICAL

ESD112-B1-02ELS

2

1

D4611

CRITICAL

GND_VOID=TRUE

ESD112-B1-02ELS

0201-THICKSTNCL

2

1

D4610

GND_VOID=TRUE

CRITICAL

0201-THICKSTNCL

ESD112-B1-02ELS

2

1

C4695

0402-1

6.3V

10UF

CERM-X5R

20%

2

1

C4691

16V X5R-CERM 0201

0.1UF

10%

14 16

2

1

C4690

0402-1

6.3V

CERM-X5R

20%

10UF

2

1

R4600

MF

1/20W

22.1K

1%

201

2

1

C4696

CRITICAL

POLY-TANT

20%

CASE-B2-SM1

220UF-35MOHM

6.3V

21

L4605

CRITICAL

FERR-120-OHM-3A

0603

SYNC_DATE=02/20/2013

SYNC_MASTER=J43_MLB

External A USB3 Connector

XDP_USB_EXTA_OC_L

USB_PWR_EN

USB_ILIM_R

USB3_EXTA_R2D_C_N

USB3_EXTA_R2D_C_P

PP5V_S3_RTUSB_A_ILIM

VOLTAGE=5V

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.5 mm

USB_ILIM

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L

USB_EXTA_P

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

PP5V_S3_RTUSB_A_F

USB2_EXTA_MUXED_P

PP5V_S4RS3

USB_EXTA_N

PP3V42_G3H

USB2_EXTA_MUXED_N

SMC_DEBUGPRT_EN_L

USB2_EXTA_MUXED_F_P

USB2_EXTA_MUXED_F_N

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_N

USB3_EXTA_R2D_P

<SCH_NUM>

46 OF 121

35 OF 76

59 61 65

68

32 47 49 54 55 58 62 64

17 30 36 37 38 40 46 49 50 59 61 62 64 65

68

w w w . c h i n a f i x . c o m

IN

OUT

D

SYM_VER_3

S G

OUT

IN

OUT

BI

OUT

IN

D

SYM_VER_3

S G

IN

Y

A

B

08

Y

A

B

08

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518S0884

(TPAD_SPI_INT_S4_WAKE_L_CONN)

(TPAD_WAKE_L)

(TPAD_USB_IF_EN_CONN)

(=PP3V42_G3H_IPD)

IPD Flex Connector

From PCH

(TPAD_SPI_IF_EN_CONN)

To SMC

To PCH

2

1

C4810

0201

X5R-CERM

16V

PLACE_NEAR=J4800.14:1.5MM

0.1UF

10%

13 18 29 36 37 59

15

2

1

3

Q4800

TPAD_INTWAKE:SHARED

DMN32D2LFB4

DFN1006H4-3

PLACE_NEAR=R4842.2:5MM

2

1

C4841

BYPASS=U4810:3mm

6.3V

CERM-X5R

0201

0.1UF

10%

29 37 39

21

R4842

5%

0

0201

1/20W

MF

TPAD_INTWAKE:SPLIT

PLACE_NEAR=R4843.2:1.5MM

21

R4843

5%

0

0201

1/20W

MF

TPAD_INTWAKE:SHARED

PLACE_NEAR=R4841.1:1.5MM

21

R4841

5%

0

0201

1/20W

MF

TPAD_INTWAKE:SPLIT

PLACE_NEAR=R4844.1:1.5MM

2

1

R4844

5%

0

0201

1/20W

MF

PLACE_NEAR=J4800.8:1.5MM

TPAD_INTWAKE:SHARED

36 37 38 61 64 65

36 38 64

36 37 38 64

36 37 40 44 64 73

14 64 68

9

8

7

6

5

4

3

20

2

19

18

17

16

15

14

13

12

11

10

1

21

22

J4800

F-RT-SM-1

CRITICAL

TF13BS-20S-0.4SH

2

1

R4810

5%

201

1/20W MF

100K

NOSTUFF

21

R4850

5%

201

1/20W

MF

PLACE_NEAR=J4800.2:2.54mm

33

15 68

21

R4852

5%

201

1/20W

MF

PLACE_NEAR=J4800.9:2.54mm

33

15 68

21

R4851

5%

201

1/20W

MF

PLACE_NEAR=J4800.7:2.54mm

33

15 68

21

R4853

5%

201

1/20W

MF

33

PLACE_NEAR=J4800.12:2.54mm

15

13 18 29 36 37 59

2

1

3

Q4860

DFN1006H4-3

DMN32D2LFB4

15

2

1

R4860

5%

201

1/20W MF

100K

2

1

C4832

0201

5% 25V C0G

100PF

NOSTUFF

BYPASS=J4800.6:1.5MM

2

1

C4833

0201

5% 25V C0G

100PF

NOSTUFF

BYPASS=J4800.5:1.5mm

2

1

C4820

BYPASS=J4800.19:1.5MM

6.3V

CERM-X5R

0201

0.1UF

10%

2

1

C4834

0201

5% 25V C0G

100PF

BYPASS=J4800.4:1.5MM

2

1

C4835

0201

5% 25V C0G

100PF

BYPASS=J4800.3:8.5MM

2

1

C4836

100PF

C0G

25V

5%

0201

BYPASS=J4800.1:1.5MM

7

8

4

2

1

U4810

CRITICAL

74LVC2G08GT/S505

SOT833

3

8

4

6

5

U4810

74LVC2G08GT/S505

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

2

1

C4800

BYPASS=J4800.10:1.5MM

6.3V

CERM-X5R

0201

0.1UF

10%

21

L4820

FERR-120-OHM-1.5A

PLACE_NEAR=J4800.14:1.5MM

0402-LF

21

R4830

5%

0

0201

1/20W

MF

PLACE_NEAR=J4800.10:1.5MM

IPD Connector

SYNC_MASTER=J43_MLB

SYNC_DATE=01/17/2013

TPAD_SPI_IF_EN_CONN

TPAD_SPI_IF_EN

PM_SLP_S4_L

TPAD_USB_IF_EN_CONN

TPAD_USB_IF_EN

PM_SLP_S4_L

PP3V3_S4

TPAD_SPI_MISO

PP3V3_S4

TPAD_SPI_INT_L

PP5V_S5

SMC_PME_S4_WAKE_L

TPAD_SPI_MOSI

TPAD_SPI_CLK

SMC_ONOFF_L

TPAD_SPI_INT_S4_WAKE_L_CONN

TPAD_SPI_MOSI_R

TPAD_WAKE_L

TPAD_SPI_CLK_R

USB_TPAD_N

USB_TPAD_P

SMC_LID

TPAD_SPI_MISO_R

TPAD_SPI_CS_R_L

SMC_LSOC_RST_L

PP3V3_S3

TPAD_SPI_CS_CONN_L

PP3V3_S3

PP3V3_S0

TPAD_SPI_CS_L

PP3V42_G3H

SMBUS_SMC_3_SDA SMBUS_SMC_3_SCL

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

PP5V_S4_IPD

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm

PP3V3_S4_IPD

SMBUS_SMC_3_SDA SMBUS_SMC_3_SCL SMC_ONOFF_L SMC_LID SMC_LSOC_RST_L

48 OF 121

<SCH_NUM>

36 OF 76

64

25 26 27 29 33 36 38 39 58 62 64

53 54 62

64

15 18 19 33 36 40 41 58 62 64

8

11 12 13 15 17 18 26 30 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

17 30 35 37 38 40 46 49 50 59 61 62 64 65

64

36 37 40 44 64 73

36 37 38 64

36 37 38 61 64 65

36 38 64

w w w . c h i n a f i x . c o m

LPC0AD3 LPC0CLK LPC0FRAME*

LPC0AD1 LPC0AD2

AIN08

AIN07 LPC0CLKRUN* LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119 PP4/IRQ120

C0-

WT2CCP0/PH0 WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2 SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127 PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4 PF5

T1CCP0/PJ0

T2CCP0/PJ2 T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

BI BI BI BI

IN IN IN

BI

OUT IN OUT

BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT OUT OUT OUT

OUT

IN

OUT

OUT OUT OUT

IN

OUT

IN

OUT

OUT OUT

OUT

NC

OUT

NC

BI

OUT

IN OUT

OUT IN OUT

OUT

IN

OUT

IN IN

IN

IN IN IN IN IN IN IN

IN OUT

OUT

BI

OUT OUT

IN

OUT

IN

OUT

IN

IN IN

OUT

BI

OUT

BI

IN

OUT

IN IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMS Interrupt can be active high or low, rename net accordingly.

(OD)

those designated as inputs require pull-ups.

pins designed as outputs can be left floating,

(OD)

NOTE:

If SMS interrupt is not used, pull up to SMC rail.

(OD)

(OD) (OD)

(OD)

(OD) (OD)

(OD)

NOTE:

Unused pins have "SMC_Pxx" names. Unused

(OD)

(PL7)

(PL6)

H10

G4

H3

H4

J3

K4

K3

L7

K7

E12

E13

E11

F11

M1

L3

C5

D5

C8

A9

B9

C9

F3

F4

N9

M9

K10

L10

N1

L4

M3

M2

L6

M6

K5

N6

N5

F5

E4

D4

K6

D8

L5

J13

J12

M5

L12

M13

M11

N11

N12

L11

D10

G3

L13

H11

A12

C11

B12

J2

J4

K9

L9

C6

C4

L1

H13

F12

C13

F13

D12

G11

H12

D11

C12

A13

B13

N3

N4

M7

N7

K8

L8

M8

N8

N2

M4

D13

E10

L2

K1

K2

A8

B8

A7

B7

H2

H1

G1

G2

B2

B1

C2

C1

A6

B6

A5

B5

A4

B4

A3

B3

F1

F2

E1

E2

U5000

BGA

LM4FSXAH5BB

OMIT_TABLE

N10

M10

N13

D2

D1

D6

K13

J6

J1

D3

J10

J9

J7

F10

E9

E8

E6

D7

K12

B10

A11

A10

C10G10

B11

G13

G12

A2

M12

E3

C3

J11

J8

J5

H9

H5

F9

E5

D9

K11

C7

A1

U5000

BGA

LM4FSXAH5BB

OMIT_TABLE

2 1

XW5000

SM

PLACE_NEAR=U5000.A1:4MM

38 46 50 64

38 69

2

1

R5002

1M

MF

5% 1/20W

201

2

1

C5006

0.1UF

X5R-CERM 0201

10V

10%

2

1

C5005

0.1UF

0201

X5R-CERM

10V

10%

2

1

C5009

0201

10V

0.1UF

X5R-CERM

10%

2

1

C5008

0.1UF

0201

X5R-CERM

10V

10%

2

1

C5004

0.1UF

0201

X5R-CERM

10V

10%

2

1

C5003

0.1UF

X5R-CERM 0201

10V

10%

2

1

C5007

0.1UF

0201

X5R-CERM

10V

10%

14 64 69

17 69

14 64 69

18

15 64

13 64

13

40 60 73

14 32 40 43 44 64 69 73

40 61 65 73

36 40 44 64 73

64

40 48 50 64 73

39 41

39 42

39 41

39 42

39 41

39 43

39 41

39 42

39 43

39 41

39 42

39 41

15 34 39 65

39 41

39 42

39 43

29 38 39 41 64

38 54 59

13

17 26 27 38

38

35 38 68

64

46 69

35

64

16 17 59

38

13 16

13 17 64

13 38

15

38

38 64

64

39

56

45

64

29 36 39

36 38 61 64 65

38

38 50 61 65

13 18

13 17 18 59

13 18 29 36 59

13 59

36 38 64

25 33 38

38 59

13 27

29 38 64

64

39

38

39

54 59

17

21

L5001

0402

30-OHM-1.7A

6

38 51 67

30

64

30

61 65

13 16 17

6

67

38

39 42 58

2

1

C5016

PLACE_NEAR=U5000.K13:5MM

10V

0201

X5R-CERM

0.1UF

10%

2

1

C5015

PLACE_NEAR=U5000.K13:5MM

10V

10%

0.1UF

0201

X5R-CERM

2

1

C5013

PLACE_NEAR=U5000.J1:5MM

10%

0.1UF

0201

10V X5R-CERM

2

1

C5010

0201-1

X5R

6.3V

20%

1.0UF

PLACE_NEAR=U5000.D6:5MM

2

1

C5001

X5R-CERM

0.1UF

0201

10V

10%

2

1

C5002

0201

6.3V

1UF

20% X5R

38

43

64

2

1

C5021

20%

1UF

0201

X5R

6.3V

BYPASS=U5000.D2:D1:1MM

2

1

C5020

10V X5R-CERM 0201

0.01UF

10%

BYPASS=U5000.D2:D1:1MM

64

2

1

C5011

PLACE_NEAR=U5000.J1:5MM

0.1UF

10%

0201

10V X5R-CERM

2

1

C5012

X5R-CERM

10V

0201

0.1UF

10%

PLACE_NEAR=U5000.J6:5MM

2

1

C5014

0201-1

X5R

6.3V

20%

1.0UF

PLACE_NEAR=U5000.J6:5MM

2

1

C5017

0201-1

X5R

6.3V

1.0UF

20%

PLACE_NEAR=U5000.D6:5MM

38 39

29 39

38

30 64

39

SMC

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

SMC_BIL_BUTTON_L

LPC_PWRDWN_L

SMBUS_SMC_0_S0_SCL

SMC_SENSOR_ALERT_L

S5_PWRGD

PM_PWRBTN_L

PM_DSW_PWRGD

SYS_ONEWIRE

SMC_S5_PWRGD_VIN

SMC_VCCIO_CPU_DIV2

SMC_DEBUGPRT_TX_L

SMC_DEBUGPRT_RX_L

SMC_PROCHOT

SMC_DELAYED_PWRGD

SMC_PM_G2_EN

SMC_CPU_DBGPWR_RD_L

SMC_OOB1_D2R_L

SMC_ADAPTER_EN

NC_SMC_T25_EN_L

SMC_SYS_KBDLED

NC_SMC_FAN_1_CTL

SMC_FAN_0_TACH

SMC_FAN_0_CTL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

NC_SMBUS_SMC_4_ASF_SDA

PM_SLP_S4_L

PM_SLP_S3_L

SMC_CPU_VSENSE

NC_SMC_FAN_5_CTL

SMC_S4_WAKESRC_EN

SMC_PME_S4_DARK_L

SMC_OOB1_R2D_L

SMC_PCH_SUSACK_L

SPI_SMC_MOSI

SMC_CPUVR_ADJUST_ISENSE

PP3V3_WLAN

SMC_SENSOR_PWR_EN

ALL_SYS_PWRGD SMC_THRMTRIP

SMC_OTHER_HI_ISENSE

SMC_DCIN_VSENSE

LPC_AD<3>

NC_SMC_GFX_OVERTEMP

MEM_EVENT_L

PM_SYSRST_L

NC_BDV_BKL_PWM

PM_BATLOW_L

CPU_THRMTRIP_3V3

NC_SMC_GFX_THROTTLE_L

CPU_CATERR_L

NC_SMC_SYS_LED

SPI_SMC_MISO

SPI_SMC_CLK

SPI_DESCRIPTOR_OVERRIDE_L

PM_SLP_S5_L

SMBUS_SMC_1_S0_SCL

PM_CLKRUN_L

LPC_AD<1>

LPC_CLK24M_SMC LPC_FRAME_L

SMBUS_SMC_0_S0_SDA

SMC_CPU_ISENSE

PP3V42_G3H

PP1V2_S5_SMC_VDDC

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.1MM VOLTAGE=1.2V

SMC_LCDBKLT_ISENSE

SMC_P1V05S0_VSENSE

SMC_P3V3S0_ISENSE

SMC_SSD_ISENSE

SMC_WLAN_ISENSE

SMC_1V2S3_ISENSE

SMC_PANEL_ISENSE

SMC_DCIN_ISENSE

SMC_BMON_ISENSE

SMC_TMS

SMC_TCK

SMC_DEBUGPRT_EN_L

SMC_RUNTIME_SCI_L

NC_SMC_XOSC1

SMBUS_SMC_3_SCL

SMBUS_SMC_1_S0_SDA

SMC_CPUDDR_ISENSE

SMC_PBUS_VSENSE

SMC_CPU_IMON_ISENSE

SMC_P3V3S5_ISENSE

SMC_XTAL

WIFI_EVENT_L SMC_WAKE_L

LPC_AD<2>

SMC_BMON_DISCRETE_ISENSE

NC_SMC_HIB_L

SMC_RESET_L

SMC_TDI

SMC_TDO

SPI_SMC_CS_L

CPU_PROCHOT_L

LPC_AD<0>

LPC_SERIRQ

SMC_HS_COMPUTING_ISENSE

SMC_WAKE_SCI_L

SMC_CLK32K

SMC_P1V05S0_ISENSE

SMC_EXTAL

SMC_LRESET_L

GND_SMC_AVSS

PP3V3_S5_AVREF_SMC

PP3V3_S5_SMC_VDDA

MIN_LINE_WIDTH=0.25MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1MM

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_2_S3_SCL

SMC_CAMERA_ISENSE PP3V3_S0SW_SD

NC_SMC_FAN_1_TACH SMC_TOPBLK_SWP_L

SMBUS_SMC_3_SDA NC_SMBUS_SMC_4_ASF_SCL

SMC_BC_ACOK

SMC_LID

CPU_PECI_R SMC_PECI_L

SMC_PME_S4_WAKE_L

SMS_INT_L

SMC_TX_L

SMC_PWRFAIL_WARN_L

TP_SMC_5VSW_PWR_EN

NC_SMC_DP_HPD_L

PM_SLP_S0_L

SMC_ONOFF_L

SMC_RX_L

SMC_WIFI_PWR_EN

PM_PCH_SYS_PWROK

SMC_PCH_SUSWARN_L

<SCH_NUM>

50 OF 121

37 OF 76

17 30 35 36 38 40 46 49 50 59 61 62 64 65

38 46 64

38

38 64

38

41

42 43

38

w w w . c h i n a f i x . c o m

IN

OUT

BI

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

SYM_VER_2

G S

D

NCNC

IN

SN0903049

PAD

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

VER 3

D

S G

VER 3

D

S G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: Internal pull-ups are to VIN, not V+.

SMC USB Clock require these crystal

From/To CPU/PCH

From SMC

SMC12 PECI Support

To SMC

values:5,6,8,10,12,16,18,20,24,25 MHz

MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard.

Debug Power "Buttons"

SMC Crystal Circuit

(IPU)

Module has 3.3K PU

Desktops: 5V Mobiles: 3.42V

SMC Reset "Button", Supervisor & AVREF Supply

21

R5170

10K

MF

1/20W

201

5%

21

R5171

100K

MF

1/20W

201

5%

21

R5173

10K

MF

1/20W

201

5%

21

R5174

100K

MF

1/20W

201

5%

21

R5177

10K

MF

1/20W

201

5%

21

R5178

10K

MF

1/20W

201

5%

21

R5179

10K

MF

1/20W

201

5%

21

R5180

10K

MF

1/20W

201

5%

37 38

15 38 67

2

1

R5115

MF-LF

1/10W

PLACE_SIDE=TOP

603

OMIT

SILK_PART=PWR_BTN

0

5%

6

37 51 67

37

21

R5189

NO STUFF

10K

MF

1/20W

201

5%

21

R5181

10K

MF

1/20W

201

5%

21

R5110

2.49K

1%

MF

1/20W

201

21

R5187

100K

MF

1/20W

201

5%

21

R5192

100K

MF

1/20W

201

5%

2

1

R5116

SILK_PART=PWR_BTN

1/10W

603

MF-LF

OMIT

PLACE_SIDE=BOTTOM

0

5%

2

1

R5101

OMIT

MF-LF 603

PLACE_SIDE=BOTTOM

1/10W

SILK_PART=SMC_RST

0

5%

36 37 38 64

36 64

2

1

C5101

X5R-CERM

0.01UF

10V

10%

0201

2

1

C5120

0.47UF

402

10%

6.3V

CERM-X5R

2

1

C5126

10%

0.01UF

X5R-CERM

10V 0201

2

1

R5100

100K

MF

1/20W

201

5%

37 46 50 64

13 69

21

R5112

22

PLACE_NEAR=U0500.AE6:5.1mm

MF

1/20W

201

5%

37 69

21

R5190

100K

MF

1/20W

201

5%

21

R5175

20K

MF

1/20W

201

5%

21

R5176

20K

MF

1/20W

201

5%

21

R5186

10K

MF

1/20W

201

5%

2

1

R5197

1%

100K

MF

1/20W

201

2

1

R5196

100K

1% MF

1/20W

201

21

R5193

10K

MF

1/20W

201

5%

36 37 38 64

37

2

1

R5153

1.6K

NOSTUFF

MF

1/20W

201

5%

21

R5152

MF

1/20W

0201

0

5%

2

1

R5151

330

MF

1/20W

201

5%

21

R5114

NO STUFF

10K

MF

1/20W

201

5%

21

R5117

100K

MF

1/20W

201

5%

21

R5167

100K

MF

1/20W

201

5%

6 67

37

21

R5134

43

MF

1/20W

201

5%

15 38 67

2

3

1

Q5158

MMBT3904LP-7

CRITICAL

DFN1006-3

37 38

2

1

C5125

0402-1

10V

20%

X5R-CERM

10UF

21

R5158

3.3K

MF

1/20W

201

5%

21

R5191

100K

MF

1/20W

201

5%

31

42

Y5110

3.2X2.5MM-SM

12.000MHZ-30PPM-10PF-85C

CRITICAL

2

1

3

Q5150

CRITICAL

DFN1006H4-3

DMN32D2LFB4

2

1

C5127

X5R

20%

402

6.3V

4.7UF

NOSTUFF

21

R5127

402

1/16W MF-LF

0

5%

21

R5172

10K

MF

1/20W

201

5%

25 33 37 38

3

1

9

5

8

7

6

2

4

U5110

CRITICAL

DFN

VREF-3.3V-VDET-3.0V

21

R5198

5%

201

1/20W

MF

100K

1

2

6

Q5159

DMN5L06VK-7

SOT563

4

5

3

Q5159

SOT563

DMN5L06VK-7

21

R5185

100K

MF

1/20W

201

5%

2

1

C5110

0201

CERM

25V

5%

12PF

2

1

C5111

0201

CERM

25V

5%

12PF

2

1

C5134

PLACE_NEAR=Q5150.2:5MM

NOSTUFF

0201

47PF

5% 25V C0G

2

1

C5131

PLACE_NEAR=Q5159.6:5MM

C0G

25V

5%

47PF

0201

SYNC_MASTER=WILL_J43

SMC Shared Support

SYNC_DATE=12/17/2012

CPU_PROCHOT_L

MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

PP3V3_S5_AVREF_SMC

VOLTAGE=0V

MIN_NECK_WIDTH=0.1 mm

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm

PP3V42_G3H_SMC_SPVSR

VOLTAGE=3.42V

SMC_BC_ACOK

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

CPU_PECI_R

SMC_XTAL_R

SMC_EXTAL

SMC_ADAPTER_EN SMC_THRMTRIP

PP3V3_S0

PP3V42_G3H

SMC_DEBUGPRT_RX_L

SMC_TDI

SMC_PM_G2_EN

SMC_DELAYED_PWRGD

SMC_S4_WAKESRC_EN

SMC_TMS

SMC_VCCIO_CPU_DIV2

SMC_TDO

SMC_BIL_BUTTON_L

SMC_S5_PWRGD_VIN

SMC_TCK

SMS_INT_L

SMC_BC_ACOK

PP3V3_WLAN

PP3V3_S4

MEM_EVENT_L CPU_THRMTRIP_3V3

SMC_DEBUGPRT_TX_L

SMC_RX_L

SMC_TX_L

SMC_LID

SMC_SENSOR_ALERT_L

SMC_ONOFF_L

SMC_PME_S4_DARK_L

PP3V42_G3H

WIFI_EVENT_L

SMC_LSOC_RST_L

SMC_RESET_L

SMC_MANUAL_RST_L

SMC_ONOFF_L

PP3V42_G3H

GND_SMC_AVSS

PM_CLK32K_SUSCLK_R

SMC_XTAL

PM_THRMTRIP_R_L

CPU_PECI

CPU_THRMTRIP_3V3

SMC_CLK32K

SMC_PECI_L_R

PP1V05_S0

SMC_ONOFF_L

SMC_PME_S4_DARK_L

PP1V05_S0

SMC_PECI_L

PM_THRMTRIP_L

SMC_BC_ACOK

PM_THRMTRIP_L

SMC_THRMTRIP

SMC_PROCHOT

<SCH_NUM>

51 OF 121

38 OF 76

37

37 38 41 42 43

37 38 50 61 65

25 33 37 38

37

13 37

37 38

8

11 12 13 15 17 18 26 30 36

39 40 41 42 43 44 45 56 59 61

62 64 65 74

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

35 37 68

37 64

37 54 59

17 26 27 37

37 59

37 46 64

37

37 64

37

37 46 64

37

37 38 50 61 65

29 37 39 41 64

25 26 27 29 33 36 39 58 62 64

37

37 38

35 37 68

37 64

36 37 61 64 65

37 39

36 37 38 64

25 33 37 38

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

29 37 64

17 30 35 36 37 38

40 46 49

50 59 61

62 64 65

37 38 41 42 43

37

6 8

11 15 16

17 38 42 51 55

58 59 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

37 38 50 61 65

w w w . c h i n a f i x . c o m

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SD alias on page 103

Top-Block Swap

29 36 37 39

2

1

R5282

5%

201

1/20W MF

100K

29 36 37 39

37 38

44

21

R5212

5%

201

1/20W

MF

100

21

R5211

5%

201

1/20W

MF

100

NOSTUFF

21

R5210

5%

201

1/20W

MF

100

61 65

21

R5283

5%

201

1/20W

MF

1K

15 37

21

R5294

5%

201

1/20W

MF

NOSTUFF

10K

21

R5213

5%

201

1/20W

MF

100

43

21

R5214

5%

201

1/20W

MF

100

44

21

R5215

5%

201

1/20W

MF

100

NOSTUFF

14 18

2

1

R5296

5%

201

1/20W

MF

1K

21

R5295

5%

201

1/20W

MF

10K

NOSTUFF

21

R5216

5%

201

1/20W

MF

100

43

15 34 37 65

37 13

13 37

21

R5230

5%

0

0201

1/20W

MF

21

R5231

5%

0

0201

1/20W

MF

SMC Project Support

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

TBTMLBSNS_ALERT_L

SMC_SENSOR_ALERT_L

CPUTHMSNS_ALERT_L

SMC_HS_COMP_ALERT_L

PCH_SML1ALERT_L

MAKE_BASE=TRUE

SMC_CPUVR_ADJUST_ISENSE

SMC_CPU_IMON_ISENSE

MAKE_BASE=TRUE

PP3V3_WLAN

MAKE_BASE=TRUE

SMC_P3V3S5_ISENSE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_P1V05S0_VSENSE

MAKE_BASE=TRUE

SMC_CAMERA_ISENSE

MAKE_BASE=TRUE

SMC_1V2S3_ISENSE

SMC_PANEL_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_WLAN_ISENSE

MAKE_BASE=TRUE

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

SMC_BMON_DISCRETE_ISENSE

SMC_WIFI_PWR_EN

PP3V3_S4

SMC_SENSOR_PWR_EN

TP_SMC_5VSW_PWR_EN

MAKE_BASE=TRUE

TP_SMC_5VSW_PWR_EN

SMC_P1V05S0_ISENSE

SMC_P1V05S0_VSENSE

PP3V3_S0

SMC_TOPBLK_SWP_L

SMC_PBUS_VSENSE

SMC_BMON_ISENSE

SMC_CPU_ISENSE

SMC_P3V3S0_ISENSE

SMC_1V2S3_ISENSE

MAKE_BASE=TRUE

SMC_CPUDDR_ISENSE

MAKE_BASE=TRUE

SMC_BMON_DISCRETE_ISENSE

SMC_OTHER_HI_ISENSE

SMC_P1V05S0_ISENSE

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

CPUBMONSNS_ALERT_L

PP3V3_WLAN

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

SMC_HS_COMPUTING_ISENSE

SMC_CPUVR_ADJUST_ISENSE

SMC_CPU_IMON_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

SMC_HS_COMPUTING_ISENSE

MAKE_BASE=TRUE

PP3V3_S4

SMC_PME_S4_WAKE_L

PCH_STRP_TOPBLK_SWP_L

SMC_SENSOR_PWR_EN

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_PANEL_ISENSE

SMC_WLAN_ISENSE

FINSTACKSNS_ALERT_L

MAKE_BASE=TRUE

SMC_SENSOR_PWR_EN

SMC_BMON_COMP_ALERT_L

MAKE_BASE=TRUE

SMC_P3V3S0_ISENSE

SMC_CAMERA_ISENSE

PP3V3_S0SW_SD

MAKE_BASE=TRUE

SMC_WIFI_PWR_EN SMC_WIFI_PWR_EN

SMC_CPUDDR_ISENSE

SMC_SSD_ISENSE

SMC_P3V3S5_ISENSE

SMC_LCDBKLT_ISENSE

SMC_CPU_VSENSE

SMC_SENSOR_PWR_EN

MAKE_BASE=TRUE

SMC_PCH_SUSWARN_L

SMC_PCH_SUSACK_L

MAKE_BASE=TRUE

PCH_SUSWARN_L

PCH_SUSACK_L

<SCH_NUM>

52 OF 121

39 OF 76

37 39 43

29 37 38 39 41 64

37 39 42

37 39 41

37 39 43

37 39 41

37 39 42

37 39 43

29 37 39

25 26 27 29 33 36 38 39 58 62 64

37 39 42 58

37 39 37 39

37 39 42

8

11 12 13 15 17 18 26 30 36 38

40 41 42 43 44 45 56 59 61 62

64 65 74

37 39 42

37 39 41

37 39 42

37 39 41

37 39 42

37 39 43

37 39 41

37 39 42

37 39 41

29 37 38 39 41 64

37 39 41

37 39 43

37 39 41

37 39 42

37 39 41

37 39 42

37 39 41

25 26 27 29 33 36 38 39 58 62 64

37 39 42 58

37 39 42

37 39 43

37 39 41

37 39 42 58

37 39 41

29 37 39 29 37 39

37 39 42

37 39 41

37 39 42

37 39 41

37 39 42

37 39 42 58

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC S0 "1" SMBus Connections

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

Internal DP

Chipset current

(* = Multiple options)

Samsung LGD Samsung LGD AUO

Internal DP

Battery

LYNX POINT LP S0 SMBus "0" Connections

LCD BACKLIGHT

(Write: 0x58 Read: 0X59)

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *

(Write: 0x92 Read 0x93)

U7701

SMLink 1 is slave port to

access PCH

(Write: 0x88 Read: 0x89)

(MASTER)

SMC

(Write: 0x98 Read: 0x99)

LIO Finstack Temp

(Write: 0xFE Read: 0XFF)

(MASTER)

Margin Control

(MASTER)

SMC

TBT

J8300

Trackpad

U2200

U2201

SMC

U5000

(MASTER)

U5000

(MASTER)

U5000

U2800

J9500

Battery

(Write: 0x12 Read: 0x13)

U5000

(Write: 0x30 Read: 0x31)

Battery Manager - (Write: 0x16 Read: 0x17)

(Write: 0x98 Read: 0x99)

(MASTER)

LYNX POINT LP

U0500

J1800

LYNX POINT LP

U0500

LYNX POINT LP S0 "SMLink 1" Connections

LYNX POINT LP S0 "SMLink 0" Connections

EMC1414: U5810

TBT & MLBBOT, TBD Temp

(See Table)

J6950

Pullups are on eDP

(See Table)

J43 J41

gated by EDP_PANEL_PWR

connector page and

VRef DACs

SMC "0" SMBus S0 Connections

(Write: 0x90 Read: 0x91)

J4800

CPU Temp, Inlet, DDR, BMON THR

EMC1704-02: U5800

PAC1921: U5620

(Write: 0x98 Read: 0x99)

SMC

(MASTER)

U5000

ALS

J4002

(Write: 0x72 Read 0x73)

XDP Connectors

SMC

SMC "2" SMBus S3 Connections

Battery Charger

SMC "3" SMBus S0 Connections

SMC "5" SMBus G3H Connections

ISL6259 - U7100

(Write: 0x30 Read: 0x31)

2

1

R5361

1/20W MF

5%

2.0K

201

2

1

R5360

1/20W

5%

MF

2.0K

201

2

1

R5380

2.0K

1/20W

MF

201

5%

2

1

R5381

201

2.0K

5% 1/20W MF

2

1

R5370

5%

201

MF

1/20W

1K

2

1

R5371

MF

1/20W

201

5%

1K

2

1

R5310

201

MF

1/20W

5%

8.2K

2

1

R5311

201

MF

8.2K

1/20W

5%

2

1

R5301

1K

MF 201

1/20W

5%

2

1

R5300

201

1/20W

MF

1K

5%

2

1

R5391

201

MF

5%

2.0K

1/20W

2

1

R5390

5%

MF

201

1/20W

2.0K

SYNC_DATE=02/06/2013

SMBus Connections

SYNC_MASTER=J41_MLB

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

MAKE_BASE=TRUE

PP3V42_G3H

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

PP3V3_S0

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_3_SCL

PP3V3_S0

MAKE_BASE=TRUE

SMBUS_PCH_CLK

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

PP3V3_S3

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_2_S3_SDA

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_SMC_3_SCL

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

SML_PCH_0_DATA

MAKE_BASE=TRUE

SML_PCH_0_CLK

MAKE_BASE=TRUE

PP3V3_S0

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PP3V3_S0

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SCL

40 OF 76

53 OF 121

<SCH_NUM>

14 32 37 40 43 44 64 69

73

14 32 37 40 43 44

64 69 73

14 32 37 40 43 44 64 69

73

37 40 48 50 64 73

17 30 35 36 37 38 46 49 50 59 61 62 64 65

14 32 37 40 43 44 64 69

73

14 32 37 40 43 44 64 69 73

14 32 37 40 43 44

64 69 73

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

14 32 37 40 43 44 64 69 73

36 37 40 44 64 73

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

14 16 19 40 56 69

37 40 60 73

15 18 19 33 36 41 58 62 64

37 40 48 50 64 73

37 40 61 65 73

14 16 19 40 56 69

36 37 40 44 64 73

37 40 61 65 73

37 40 48 50 64 73

14 69

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

14 16 19 40 56 69

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

14 16 19 40 56 69

36 37 40 44 64 73

14 16 19 40 56 69

37 40 60 73

14 32 37 40 43 44

64 69 73

14 32 37 40 43 44

64 69 73

37 40 61 65 73

37 40 61 65

73

w w w . c h i n a f i x . c o m

OUT OUT

IN

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

OUT

V+

REFIN+

IN-

OUT

GND

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN-

IN+ REF

V+

GND

OUT

IN-

IN+ REF

V+

GND

V+

REFIN+

IN-

OUT

GND

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SENSE R : R7450 0.002R

EDP Current: 310A

Max VOut: 3.3V at 9.167A

Scale: 2.78A / V

ISL6259 Gain: 36x

ISL6259 Gain: 20x

Sense R is R7120, 20mOhm

EDP Current: 3.5A

GAIN : 200X

GAIN : 500X

EDP Current : 0.67A

MAX Vdiff : 15 mV

GAIN : 200X

EDP Current : 3.00A

GAIN : 100X

MAX Vdiff : 25 mV

EDP Current : 1.00A

ISDC : SSD Current Sense

MAX Vdiff : 15.14 mV

EDP Current : 7.57A

IM3C :DDR 1V2 Current Sense (LPDDR + CPUDDR)

EDP Current :10.75A

MAX Vdiff : 24 mV

IAPC :AirPort Current Sense

APN: 104S0024

(100V/V)

(For R and C)

PLACEMENT_NOTEs:

(200V/V)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

Replacing caps with 100K PD on ISENSE SMC inputs

CHARGER BMON High Side Current Sense

Scale: 2.5A / V

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(200V/V)

PLACEMENT_NOTEs:

(1000V/V)

(50V/V)

APN: 107S0137

(100V/V)

(200V/V)

(500V/V)

MAX Vdiff : 53.75 mV

GAIN : 50X

IO0R : OTHER High Side Current Sense

EDP Current : 0.82A

MAX Vdiff : 3.06 mV

EDP Current :1.02A

GAIN : 1000X

Max VOut: 1.4V at 8.25A

DC-IN (AMON) Current Sense

IR0C : 3.3V S0 FET Current Sense

IS2C : 3.3V Camera Current Sense

GAIN : 200X

MAX Vdiff : 16.36 mV

(For R and C)

IBLC : LCD Backlight Driver Input Current Sense

MAX Vdiff : 0.06 mV

IC0R : COMPUTING High Side Current Sense

GAIN : 100X

EDP Current :12A

37 39 37 39

2

1

C5431

10%

PLACE_NEAR=U5000.B3:11MM

2.2NF

10V

0201

X5R-CERM

21

R5431

201

PLACE_NEAR=U5000.B3:11MM

45.3K

1%

MF

1/20W

50

37 39

2

1

C5465

Place close to SMC

X5R

6.3V

PLACE_NEAR=U5000.A5:11mm

DRAM_ISNS:YES

20%

0.22UF

0201

21

R5465

DRAM_ISNS:YES

PLACE_NEAR=U5000.A5:11mm

Place close to SMC

201

4.53K

1%

MF

1/20W

2

1

C5460

DRAM_ISNS:YES

10%

0.1UF

0201

CERM-X5R

6.3V

53 74

2

1

C5475

PLACE_NEAR=U5000.C1:11mm

AIRPORT_ISNS:YES

Place close to SMC

X5R

6.3V

0.22UF

20%

0201

21

R5475

PLACE_NEAR=U5000.C1:11mm

AIRPORT_ISNS:YES

Place close to SMC

201

4.53K

1%

1/20W

MF

2

1

C5485

SSD_ISNS:YES

Place close to SMC

0201

0.22UF

20%

PLACE_NEAR=U5000.C2:11mm

6.3V X5R

21

R5485

PLACE_NEAR=U5000.C2:11mm

SSD_ISNS:YES

Place close to SMC

201

1/20W

1%

4.53K

MF

2

1

C5470

10%

0.1UF

0201

CERM-X5R

6.3V

AIRPORT_ISNS:YES

2

1

C5495

PLACE_NEAR=U5000.B6:11mm

LCDBKLT_ISNS:YES

Place close to SMC

0.22UF

20%

0201

6.3V X5R

21

R5495

PLACE_NEAR=U5000.B6:11mm

LCDBKLT_ISNS:YES

Place close to SMC

1%

4.53K

1/20W

MF

201

2

1

C5490

LCDBKLT_ISNS:YES

6.3V CERM-X5R 0201

0.1UF

10%

21

R5422

201

PLACE_NEAR=U5000.A4:11MM

1/20W

MF

1%

300K

2

1

C5422

10%

0201

10V X7R-CERM

3300PF

PLACE_NEAR=U5000.A4:11MM

37 39

2

1

C5455

Place close to SMC

X5R

6.3V

PLACE_NEAR=U5000.E2:11mm

0201

CPU_HS_ISNS:YES

0.22UF

20%

21

R5455

201

PLACE_NEAR=U5000.E2:11mm

1%

MF

4.53K

CPU_HS_ISNS:YES

1/20W

2

1

C5450

10%

0.1UF

0201

CERM-X5R

6.3V

CPU_HS_ISNS:YES

2

1

C5480

SSD_ISNS:YES

6.3V CERM-X5R 0201

0.1UF

10%

37 39

2

1

C5433

OTHER_HS_ISNS:YES

0201

20%

0.22UF

PLACE_NEAR=U5000.A4:11mm

6.3V X5R

Place close to SMC

21

R5433

201

PLACE_NEAR=U5000.A4:11mm

4.53K

MF

1%

1/20W

Place close to SMC

OTHER_HS_ISNS:YES

2

1

C5430

CERM-X5R

10%

0.1UF

0201

6.3V

OTHER_HS_ISNS:YES

3

1

6

4

5

2

U5430

OTHER_HS_ISNS:YES

PLACE_NEAR=R5430:5mm

INA213

CRITICAL

SC70

27 41 42 49

50 56

62 64

54 62 64

50

3

1

6

4

5

2

U5460

PLACE_NEAR=R7450:5mm

DRAM_ISNS:YES

CRITICAL

SC70

INA210

432

1

R5450

0612

1%

0.002

MF

1W

CRITICAL

432

1

R5480

0612

MF

1W

1%

0.003

CRITICAL

OMIT_TABLE

3

1

6

4

5

2

U5480

SSD_ISNS:YES

PLACE_NEAR=R5480:5mm

SC70

INA210

CRITICAL

37 39

2

1

C5445

Place close to SMC

X5R

6.3V

PLACE_NEAR=U5000.B1:11mm

0.22UF

20%

0201

3V3S0_ISNS:YES

21

R5445

Place close to SMC

201

1/20W

MF

1%

4.53K

3V3S0_ISNS:YES

PLACE_NEAR=U5000.B1:11mm

2

1

C5440

10%

0201

CERM-X5R

6.3V

0.1UF

3V3S0_ISNS:YES

3

1

6

4

5

2

U5440

SC70

INA212

CRITICAL

PLACE_NEAR=R5440:5mm

3V3S0_ISNS:YES

37 39

21

R5425

Place close to SMC

201

CAM_ISNS:YES

PLACE_NEAR=U5000.B2:11mm

1/20W

4.53K

MF

1%

2

1

C5425

Place close to SMC

CAM_ISNS:YES

20%

0201

0.22UF

PLACE_NEAR=U5000.B2:11mm

6.3V X5R

2

1

C5420

6.3V CERM-X5R 0201

10%

CAM_ISNS:YES

0.1UF

3

1

6

4

5

2

U5490

PLACE_NEAR=R5490:5mm

LCDBKLT_ISNS:YES

SC70

INA211

CRITICAL

21

R5421

402

5%

MF-LF

0

1/16W

21

R5423

NOSTUFF

402

5%

MF-LF

1/16W

0

432

1

R5470

CRITICAL

0612

0.025

1W

MTL

1%

3

1

6

4

5

2

U5450

SC70

INA214

CPU_HS_ISNS:YES

CRITICAL

3

1

6

4

5

2

U5470

PLACE_NEAR=R5470:5mm

AIRPORT_ISNS:YES

CRITICAL

SC70

INA214

3

1

6

4

5

2

U5420

CRITICAL

SC70

INA210

PLACE_NEAR=R8061:5mm

CAM_ISNS:YES

2

1

R5451

20K

201

MF

1/20W

5%

2

1

R5432

201

5%

1/20W

MF

20K

2

1

R5461

201

5%

1/20W

MF

20K

2

1

R5471

201

5%

1/20W

MF

20K

2

1

R5481

20K

MF

1/20W

5%

201

2

1

R5491

20K

5%

1/20W

MF

201

2

1

R5441

201

5%

1/20W

MF

20K

2

1

R5424

20K

5%

1/20W

MF

201

432

1

R5430

0612-SHORT

0.003

1% 1w

CYN

OMIT

432

1

R5440

0612-SHORT

CYN

1w 1%

0.003

OMIT

432

1

R5420

0612-SHORT

0.020

0.5%

1w

MF

OMIT

432

1

R5490

0612-SHORT

OMIT

MF 1w

0.5%

0.020

SYNC_MASTER=J41_MLB

SYNC_DATE=03/28/2013

High Side Current Sensing

CPU_HS_ISNS:NO

RES,MF,1/20W,100K OHM,5,0201,SMD

117S0008

1

C5455

117S0008

DRAM_ISNS:NO

RES,MF,1/20W,100K OHM,5,0201,SMD

1

C5465

107S0248 CRITICAL

RES,SENSE,0.003OHM,1W,4-TERM,1%,0612,TFT

R5480

1

C5433

1

117S0008

OTHER_HS_ISNS:NO

RES,MF,1/20W,100K OHM,5,0201,SMD

C5425

1

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

CAM_ISNS:NO

3V3S0_ISNS:NO

117S0008

1

C5445

RES,MF,1/20W,100K OHM,5,0201,SMD

1

117S0008

C5495

LCDBKLT_ISNS:NO

RES,MF,1/20W,100K OHM,5,0201,SMD

117S0008

1

C5485

SSD_ISNS:NO

RES,MF,1/20W,100K OHM,5,0201,SMD

1

C5475

AIRPORT_ISNS:NO

RES,MF,1/20W,100K OHM,5,0201,SMD

117S0008

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

PPVIN_S0SW_LCDBKLT

PPVIN_S0SW_LCDBKLT_FET

PP3V3_S4SW_SNS

PP3V3_S0_FET_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_S3RS0_CAMERA_R

PP3V3_S3RS0_CAMERA

ISNS_CAMERA_P

ISNS_CAMERA_N

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S3RS0_CAMERA

MIN_NECK_WIDTH=0.2 MM

PP3V3_S4SW_SNS

ISNS_P3V3_S0_P

PP3V3_S0

ISNS_P3V3_S0_N

PPBUS_S5_HS_OTHER_ISNS

GND_SMC_AVSS

PPBUS_G3H

PP3V3_S4SW_SNS

ISNS_P3V3_S0_IOUT

HS_OTHER_IOUT

PP3V3_S4SW_SNS

PPBUS_G3H

ISNS_HS_OTHER_P

ISNS_HS_OTHER_N

MIN_LINE_WIDTH=0.4 MM

PPVIN_S0SW_LCDBKLT

VOLTAGE=8.6V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

ISNS_SSD_N

MAKE_BASE=TRUE

VOLTAGE=8.6V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.25 MM

PPVIN_S0SW_LCDBKLT_FET

SMC_LCDBKLT_ISENSE

GND_SMC_AVSS

ISNS_SSD_P

GND_SMC_AVSS

PPBUS_S5_HS_COMPUTING_ISNS

SMC_HS_COMPUTING_ISENSE

ISNS_HS_COMPUTING_IOUT

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

PP3V3_S0

SMC_P3V3S0_ISENSE

GND_SMC_AVSS

PP3V3_S3RS0_CAMERA

PP3V3_S0

PP3V3_S3

SMC_OTHER_HI_ISENSE

GND_SMC_AVSS

ISNS_CAMERA_IOUT

SMC_CAMERA_ISENSE

GND_SMC_AVSS

SMC_DCIN_ISENSE

CHGR_AMON

SMC_BMON_ISENSECHGR_BMON

PP3V3_S0SW_SSD_FET_R

PP3V3_S0SW_SSD

ISNS_P5VSSD_IOUT

SMC_SSD_ISENSE

ISNS_LCDBKLT_IOUT

PP3V3_S4SW_SNS

GND_SMC_AVSS

PP3V3_S4SW_SNS

SMC_1V2S3_ISENSE

ISNS_1V2_IOUTISNS_1V2_S3_N

ISNS_1V2_S3_P

GND_SMC_AVSS

PP3V3_WLAN_R

PP3V3_WLAN

PP3V3_S4SW_SNS

SMC_WLAN_ISENSE

ISNS_P5VWLAN_IOUT

ISNS_AIRPORT_P

ISNS_AIRPORT_N

<SCH_NUM>

54 OF 121

41 OF 76

74

41 56

41 42 43 58 62

58

15 31

41

74

15 31

41

41 42 43 58 62

74

8

11 12 13 15 17

18 26 30 36 38 39

40 41 42 43 44 45

56 59 61 62 64 65

74

37 38 41 42 43

41 42 43 58 62

27 41 42 49

50 56

62 64

74

41 56

74

41 56

37 38 41 42 43

74

37 38 41 42 43

51 52 53 55

62 64

43

43 74

43

74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

37 38 41 42 43

15 31

41

15 18 19 33

36 40

58 62

64

37 38 41 42 43

58

30 62 64

41 42 43 58 62

37 38 41 42 43

41 42 43 58 62

37 38 41 42 43

29

29 37 38 39 64

41 42 43 58 62

74

w w w . c h i n a f i x . c o m

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

IN

V-

V+

+

-

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

IN-

IN+ REF

V+

GND

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

MAX Vdiff : 12.60 mV

EDP Current : 3.00A

IM0C : CPU DDR Current Sense

VP0R: PBUS Voltage Sense Enable & Filter

GAIN : 200X

ICS0 : CPU VCore Load Side Current Sense

(500V/V)

GAIN : 500X

MAX Vdiff : 5.65 mV

EDP Current : 1A

Gain:274.72x

Sense R is R7310, R7320

EDP: 32A TDP :28.05A

Sense R is 0.75mOhm each, combined 0.375mOhm

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

(200V/V)

RTHEVENIN = 4573 Ohms

IC1C: 1.05V S0 CURRENT SENSE / FILTER

Max VOut: 3.3V at 19.77V Input

VD0R: DC-In Voltage Sense Enable & Filter

divider when SUS present.

Enables DC-In VSense

Max VOut: 3.3V at 19.77V Input

RTHEVENIN = 4573 Ohms

CPU Vcore Voltage Sense / Filter

1.05V Voltage Sense / Filter

GAIN : 100X

EDP Current : 3.00A

MAX Vdiff : 30.00 mV

(100V/V)

Replacing caps with 100K PD on ISENSE SMC inputs

IR5C :3.3 S5 REG Current Sense

37 39

58

2

1

R5502

MF

1%

100K

1/20W

201

2

1

R5501

1/20W

100K

1%

MF

201

37 39

2

1

C5504

20%

0.22UF

0201

6.3V X5R

PLACE_NEAR=U5000.E1:11MM

2

1

R5503

1%

MF

1/20W

27.4K

201

PLACE_NEAR=U5000.E1:11MM

2

1

R5504

5.49K

1/20W

1%

MF

201

PLACE_NEAR=U5000.A3:11MM

4

1

5

2

3

6

Q5500

SOT-963

NTUD3169CZ

37 39

21

R5561

PLACE_NEAR=U5000.H2:11MM

P1V05_ISNS:YES

201

1/20W

MF

1%

4.53K

2

1

C5561

P1V05_ISNS:YES

X5R

6.3V

20%

0.22UF

0201

PLACE_NEAR=U5000.H2:11MM

2

1

C5560

P1V05_ISNS:YES

10%

0.1UF

0201

CERM-X5R

6.3V

55 74

3

1

6

4

5

2

U5560

SC70

PLACE_NEAR=R7640:5mm

P1V05_ISNS:YES

PLACE_NEAR=R7640.3:5MM

PLACE_NEAR=R7640.4:5MM

CRITICAL

INA211

21

R5548

201

1/20W

4.53K

MF

1%

CPUVR_ISNS:YES

PLACE_NEAR=U5000.B4:11MM

37 39

2

1

C5541

X5R

6.3V

CPUVR_ISNS:YES

0.22UF

20%

0201

PLACE_NEAR=U5000.B4:11MM

2

1

C5540

10%

0.1UF

0201

CERM-X5R

6.3V

CPUVR_ISNS:YES

PLACE_NEAR=U5540.5:3MM

52 74

37 39

2

1

R5513

27.4K

1/20W

MF

1%

PLACE_NEAR=U5000.B3:11MM

201

2

1

C5514

0.22UF

0201

PLACE_NEAR=U5000.B3:11MM

6.3V

X5R

20%

2

1

R5514

1/20W

5.49K

MF

1%

201

PLACE_NEAR=U5000.F1:11MM

2

1

R5512

MF

100K

1%

201

1/20W

4

1

5

2

3

6

Q5510

NTUD3169CZ

SOT-963

2

1

R5511

100K

1/20W

1%

MF

201

13 59

5

2

4

3

1

U5540

SC70-5

OPA333DCKG4

CRITICAL

CPUVR_ISNS:YES

37 39

2

1

C5595

0201

0.22UF

20%

Place close to SMC

6.3V X5R

PLACE_NEAR=U5000.A6:11mm

P3V3S5_ISNS:YES

21

R5595

Place close to SMC

1/20W

MF

1%

4.53K

201

P3V3S5_ISNS:YES

PLACE_NEAR=U5000.A6:11mm

2

1

C5590

P3V3S5_ISNS:YES

6.3V CERM-X5R 0201

0.1UF

10%

52 74

21

R5540

402

1%

4.42K

MF-LF

CPUVR_ISNS:YES

1/16W

PLACE_NEAR=R7310.3:5MM

21

R5541

402

1%

4.42K

MF-LF

CPUVR_ISNS:YES

1/16W

PLACE_NEAR=R7320.3:5MM

21

R5542

CPUVR_ISNS:YES

402

MF-LF

1/16W

4.42K

1%

PLACE_NEAR=R7310.3:5MM

21

R5543

CPUVR_ISNS:YES

402

1/16W

4.42K

1%

MF-LF

PLACE_NEAR=R7320.3:5MM

21

R5545

MF-LF

402

1.43K

1%

CPUVR_ISNS:YES

1/16W

21

R5544

402

1.43K

MF-LF

1%

1/16W

CPUVR_ISNS:YES

21

R5547

402

1M

CPUVR_ISNS:YES

MF-LF

1/16W

1%

NO_XNET_CONNECTION=TRUE

2

1

R5546

CPUVR_ISNS:YES

MF-LF

1% 1/16W

1M

402

37 39

2

1

C5575

Place close to SMC

CPUDDR_ISNS:YES

0.22UF

20%

0201

6.3V X5R

PLACE_NEAR=U5000.H1:11mm

21

R5575

1/20W

Place close to SMC

MF

1%

4.53K

201

CPUDDR_ISNS:YES

PLACE_NEAR=U5000.H1:11mm

2

1

C5570

CPUDDR_ISNS:YES

6.3V CERM-X5R 0201

0.1UF

10%

3

1

6

4

5

2

U5570

INA210

CPUDDR_ISNS:YES

SC70

PLACE_NEAR=R5570:5mm

37 39

2

1

C5530

0.22UF

20%

0201

6.3V X5R

PLACE_NEAR=U5000.G1:11MM

21

R5530

1%

4.53K

MF

1/20W

201

PLACE_NEAR=U5000.G1:11MM

21

XW5530

SM

PLACE_NEAR=R7640.2:5 MM

52 74

3

1

6

4

5

2

U5590

INA214

SC70

CRITICAL

PLACE_NEAR=R5590:5mm

P3V3S5_ISNS:YES

2

1

R5571

MF

1/20W

5%

20K

201

2

1

R5591

MF

5%

20K

201

1/20W

2

1

R5562

201

20K

MF

1/20W

5%

432

1

R5570

OMIT

0612-SHORT

CYN

1w 1%

0.003

432

1

R5590

0612-SHORT

OMIT

CYN

1w

1%

0.003

37 39

21

R5520

1/20W

1%

MF

4.53K

201

PLACE_NEAR=U5000.B7:11MM

2

1

C5520

0201

0.22UF

20%

6.3V X5R

PLACE_NEAR=U5000.B7:11MM

21

XW5520

PLACE_NEAR=R7310.2:5 MM

SM

C5575

RES,MF,1/20W,100K OHM,5,0201,SMD

CPUDDR_ISNS:NO

1

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

P1V05_ISNS:NO

117S0008

1

C5561

SYNC_DATE=03/28/2013

SYNC_MASTER=J41_MLB

Voltage & Load Side Current Sensing

1

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

C5595

P3V3S5_ISNS:NO

RES,MF,1/20W,100K OHM,5,0201,SMD

CPUVR_ISNS:NO

117S0008

1

C5541

PP3V3_S5_REG_R

PP3V3_S5

PP1V2_S3

ISNS_CPUDDR_P

ISNS_CPUDDR_N

PP3V3_S4SW_SNS

DCINVSENS_EN_L

GND_SMC_AVSS

CPUVR_ISUM_IOUT

GND_SMC_AVSS

SMC_CPU_ISENSE

PP3V3_S0

GND_SMC_AVSS

SMC_CPU_VSENSE

SMC_P1V05S0_VSENSE

PPVCC_S0_CPU CPUVSENSE_IN

PP1V05_S0

P1V05VSENSE_IN

SMC_DCIN_VSENSE

PDCINVSENS_EN_L_DIV

DCIN_S5_VSENSE

PM_SLP_SUS_L

SMC_PBUS_VSENSE

PPBUS_G3H

PBUSVSENS_EN_L_DIV

GND_SMC_AVSS

SMC_SENSOR_PWR_EN

PPDCIN_G3H_ISOL

CPUVR_ISNS1_P

CPUVR_ISNS2_P

CPUVR_ISNS1_N

CPUVR_ISNS2_N

CPUVR_ISNS1_P_R

CPUVR_ISUM_R_P

CPUVR_ISNS1_N_R

CPUVR_ISUM_R_N

GND_SMC_AVSS

SMC_CPUDDR_ISENSE

SMC_P3V3S5_ISENSE

ISNS_CPUDDR_IOUT

ISNS_P3V3S5_IOUT

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP3V3_S5_REG_R

MIN_LINE_WIDTH=0.5 MM

PP3V3_S4SW_SNS

GND_SMC_AVSS

SMC_P1V05S0_ISENSE

P1V05S0_IOUT

ISNS_1V05_S0_P

ISNS_1V05_S0_N

PP3V3_S4SW_SNS

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.1 MM

PPVMEMIO_S0_CPU

VOLTAGE=1.2V

PBUSVSENS_EN_L

PBUS_S0_VSENSE

ISNS_P3V3S5_P

ISNS_P3V3S5_N

PPVMEMIO_S0_CPU

<SCH_NUM>

55 OF 121

42 OF 76

42 54

8

11 13 15 16 17 18 28 29 34

57 58 59 60 62 64 74

17 19 20 21 22 23 53 62 70

74

41 42 43 58 62

37 38 41 42 43

8

11 12 13 15 17 18 26 30 36

38 39 40 41 43 44 45 56 59 61

62 64 65 74

37 38 41 42 43

8

10

52 62

64

6 8

11

15 16 17

38 51 55

58 59 62

64

27 41 49 50 56 62 64

37 38 41 42 43

49 50

62

64

43 74

74

43 74

74

37 38 41 42 43

37 38 41 42 43 42 54

41 42 43 58 62

37 38 41 42 43

41 42 43 58 62

8

10 42

74

8

10 42

w w w . c h i n a f i x . c o m

SYM_VER_2

G S

D

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

SYM_VER_2

G S

D

IN

BI

IN

BI

IN

OUT

VDD

SENSE-

ADDR_SEL/GAIN_SEL

SENSE+

EPAD

GND

SM_DATA/OUT_SEL

SM_CLK/INT_SEL

COMM_SEL

OUT

READ*/INT

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Discrete High side Current threshold

ILDC :LCD Panel Current Sense / Filter

(200V/V)

Gain: 200x

Max Vdiff: 15 mV

EDP Current: 0.750 A

MAX VOUT: 3V AT 0.825A

Scale: 2A / V

BMON : Discrete BMON Current Sense / Filter

present on IN+/- pins with INA output voltage decreasing

R5821: ADDR - 0x56/0x57 (r/w)

Hysteresis TBD based on RC value changes

(For R and C)

PLACEMENT_NOTEs:

to measure power into the system

VR IMON Current Sense Filter

(50V/V)

Vtl = 0.290mv = 0.687A from battery

Vref = 0.406mV Vth = 0.442 = 1A from Battery

Scale: 0.25A / V

Gain: 50x

Max VOut: 3.3V at 6.6A

CHGR_CSO_R_P/N are swapped on purpose

Replacing caps with 100K PD on ISENSE SMC inputs

from 3.3V with increasing discharge current.

This will set the minumum current threshold at 0.100mA

going into sense pins of U5800.

With 100mA battery current, Will have 10.2mV difference

Sense Pins gain stage for U5800 (EMC1704)

In battery discharge scenario negative voltage will be

GAIN: 500X

(500V/V)

PU: SMBus mode

ICS3 : Adjustable Gain CPU VR Current

2

5

1

4

3

U5601

MCP6541T SC70-5

2

1

3

U5602

DMN32D2LFB4

DFN1006H4-3

42 74

39

21

R5609

402

1% 1/16W MF-LF

200K

21

R5606

402

MF-LF

1/16W

1%

10.2K

2

1

R5604

402

100K

1% 1/16W MF-LF

2

1

R5605

402

100K

1% 1/16W MF-LF

21

C5601

X5R

6.3V

NO STUFF

0.22UF

0201

20%

42 74

2

1

C5603

6.3V CERM-X5R 0201

10%

0.1UF

BYPASS=U5601:3MM

2

1

R5621

5%

201

1/20W

MF

4.3K

3

1

6

4

5

2

U5600

CRITICAL

CKPLUS_WAIVE=NdifPr_badTerm

INA213

SC70

CKPLUS_WAIVE=NdifPr_badTerm

2

1

R5600

5%

0

0201

1/20W MF

2

1

C5600

402

25V

10%

0.1UF

X5R

NOSTUFF

2

1

R5607

5%

0

0201

1/20W MF

NOSTUFF

3

1

6

4

5

2

U5660

CRITICAL

SC70

INA211

CKPLUS_WAIVE=NdifPr_badTerm

PLACE_NEAR=R7150:5MM

50 73

2

1

C5670

10%

0.1UF

0201

CERM-X5R

6.3V

PANEL_ISNS:YES

21

R5675

MF

PLACE_NEAR=U5000.C1:11mm

1%

PANEL_ISNS:YES

4.53K

Place close to SMC

1/20W

201

2

1

C5675

6.3V

PANEL_ISNS:YES

0.22UF

20%

Place close to SMC

0201

PLACE_NEAR=U5000.C1:11mm

X5R

37 39

3

1

6

4

5

2

U5670

SC70

INA210

PANEL_ISNS:YES

PLACE_NEAR=R5470:5mm

CRITICAL

39

2

1

3

U5612

DFN1006H4-3

DMN32D2LFB4

21

C5611

X5R

6.3V

NO STUFF

0.22UF

0201

20%

21

R5619

402

255K

1% 1/16W MF-LF

2

5

1

4

3

U5611

SC70-5

MCP6541T

21

R5616

402

10.2K

1% 1/16W MF-LF

2

1

C5610

NOSTUFF

402

25V

10%

0.1UF

X5R

2

1

C5613

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U5601:3MM

2

1

R5610

5%

0

0201

1/20W MF

2

1

R5617

5%

0

0201

1/20W MF

NOSTUFF

2

1

R5614

402

294K

1/16W

1%

MF-LF

2

1

R5615

402

1/16W

49.9K

MF-LF

1%

41

21

R5668

5%

0

0201

1/20W

MF

21

R5669

5%

0

0201

1/20W

MF

NO STUFF

21

R5667

5%

0

0201

1/20W

MF

NO STUFF

21

R5666

5%

0

0201

1/20W

MF

14 32 37 40 44 64 69 73

41 43

74

41 43

74

2

1

R5671

5%

1/20W

MF

20K

201

2

1

R5601

5%

201

1/20W

MF

20K

2

1

R5663

5%

201

1/20W

MF

20K

432

1

R5670

0612-SHORT

0.020

0.5% 1w MF

OMIT

K

A

D5617

NOSTUFF

0201

RB521ES-30

K

A

D5607

NOSTUFF

0201

RB521ES-30

14 32 37 40 44 64 69 73

2

1

C5665

0.22UF

NO STUFF

X5R

6.3V

0201

20%

2

1

C5660

0201

CERM-X5R

10%

0.1UF

6.3V

PLACE_NEAR=U5660.3:5MM

37

41 43 74

21

R5665

5%

0

0201

1/20W

MF

2

1

R5662

201

1/20W

MF

1K

1%

2

1

R5661

201

1/20W

MF

27K

1%

44 74

21

R5660

5%

0

0201

1/20W

MF

37 39

2

1

C5606

0201

CERM-X5R

10%

0.1UF

6.3V

BYPASS=U5600:3MM

2

1

C5602

X5R

6.3V

20%

PLACE_NEAR=U5000.A3:5MM

0.22UF

0201

21

R5608

201

1/20W

MF

PLACE_NEAR=U5000.A3:5MM

1%

4.53K

1

11

9

10

2

3

8

4

5

7

6

U5620

PLACE_NEAR=U5540.1:5MM

PAC1921-1-AIA

DFN

37 39

21

R5625

5%

0

0201

1/20W

MF

PLACE_NEAR=U5000.A7:5MM

2

1

C5625

X5R

6.3V

PLACE_NEAR=U5000.A7:5MM

0.22UF

20%

0201

NO STUFF

2

1

C5620

0201-1

X5R

6.3V

20%

1.0UF

BYPASS=U5620.1:5:3MM

21

R5620

402

1%

100

1/16W MF-LF

37 39

2

1

C5641

10%

NO STUFF

PLACE_NEAR=U5000.B8:5MM

10V X5R-CERM 0201

2.2NF

51

21

R5641

5%

0

0201

1/20W

MF

PLACE_NEAR=U5000.B8:5MM

RES,MF,1/20W,100K OHM,5,0201,SMD

117S0008

1

PANEL_ISNS:NO

C5675

SYNC_DATE=03/28/2013

SYNC_MASTER=J41_MLB

Debug Sensors 1

BMON_IOUT_D

BMON_IOUT

HS_IOUT_D

ISNS_HS_COMPUTING_IOUT

ISNS_HS_GAIN_P_R

ISNS_HS_COMPUTING_N

ISNS_HS_COMPUTING_P

ISNS_HS_GAIN_OUT_R

ISNS_HS_COMPUTING_N

SMC_HS_COMP_ALERT_L

ISNS_HS_GAIN_N

CPUVR_ISNS1_N_R

PP3V3_S0

BMON_COMP_FB

BMON_IOUT_R

BMON_COMP_VREF

ISNS_HS_GAIN_OUT

ISNS_PANEL_IOUT

ISNS_HS_GAIN_N_R

CPUVR_ISNS1_P_R

SMC_CPUVR_ADJUST_ISENSE

SMBUS_SMC_1_S0_SDA

SMC_CPU_DBGPWR_RD_L

GND_SMC_AVSS

SMC_CPU_IMON_ISENSE

CHGR_CSO_R_P

CHGR_CSO_R_N

GND_SMC_AVSS

SMC_PANEL_ISENSE

GND_SMC_AVSS

SMC_BMON_DISCRETE_ISENSE

SMC_BMON_COMP_ALERT_L

HS_COMP_VREF

HS_COMP_FB

HS_COMP_OUT

CPUVR_IMON

SMBUS_SMC_1_S0_SCL

GND_SMC_AVSS

ISNS_HS_COMPUTING_P

ISNS_HS_GAIN_P

PP3V3_S0

SMC_CPUVR_ADJUST_ISENSE_R

PP3V3_S4SW_SNS

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=3.3V

PP3V3_SNS_CPUVR_ADJUST_ISNS

CPUVRSNS_ADDR_SEL

HS_IOUT_R

BMON_COMP_OUT

ISNS_PANEL_N

PP3V3_S0SW_LCD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S4SW_SNS

PP3V3_S0

ISNS_PANEL_P

PP3V3_S0SW_LCD_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S0SW_LCD_R

<SCH_NUM>

56 OF 121

43 OF 76

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

37 38 41 42 43

37 38

41

42

43

37 38 41 42 43

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

41 42 43 58 62

74

43 60

41 42 43 58 62

8

11

12 13

15 17

18 26

30 36

38 39

40 41

42 43

44 45

56 59

61 62

64 65

74

43 60

w w w . c h i n a f i x . c o m

DUR_SEL

DP1

VDD

THERM*

ALERT*

SMDATA

SMCLK

ADDR_SEL

GPIO

THRM_PAD

GND

TH_SEL

SENSE-

SENSE+

DN2/DP3

DP2/DN3

DN1

BI

OUT

BI

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

BI

OUT

BI

NC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU Proximity, Inlet ,DDR and BMON THR Sensor

Placement note:

Place U5800 under CPU

Write Address: 0x98

TBT, MLBBOT and TBD Temp Sensor

Placement note:

TBT,MLB Bottom Proximity Sensors

Read Address: 0x38

Write Address: 0x39

TBD

Placement note:

Place Q5820 close to TBT on TOP side

Place Q5840 on MLB bottom side opposite U5810

Placement note:

Read Address: 0x99

Place Q5810 next to DDR/5V/3.3V supply on TOP side

Place Q5830 between near rear vent on bottom side

Placement note:

Detect DDR/5V/3.3V Proximity Temperature

21

R5840

MF

1/20W

0201

0

5%

21

R5841

MF

1/20W

0201

0

5%

2

3

1

Q5810

BC846BLP

DFN1006H4-3

2

3

1

Q5820

DFN1006H4-3

BC846BLP

2

3

1

Q5830

BC846BLP

DFN1006H4-3

2

3

1

Q5840

DFN1006H4-3

BC846BLP

1

17

9

14

11

12

16

15

7

8

13

4

2

5

3

10

6

U5800

EMC1704-2

QFN

CRITICAL

2

1

C5800

0.1UF

10%

6.3V CERM-X5R 0201

21

R5800

47

MF

1/20W

201

5%

14 32 37 40 43 64 69 73

2

1

C5801

10%

PLACE_NEAR=U5800.2:5mm

PLACE_NEAR=U5800.3:5mm

10V

X7R-CERM

0201

2200PF

NO_XNET_CONNECTION=TRUE

2

1

C5802

10%

X7R-CERM

PLACE_NEAR=U5800.5:5mm

0201

10V

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5800.4:5mm

2200PF

2

1

R5805

MF

1/20W

0201

0

5%

39

43 74

36 37 40 64 73

2

1

C5810

10%

0.1UF

0201

CERM-X5R

6.3V

1

7

9

10

6

4

2

5

3 8

U5810

CRITICAL

EMC1414-1-AIZL

MSOP

21

R5810

47

MF

1/20W

201

5%

2

1

C5812

10%

PLACE_NEAR=U5810.4:5mm

PLACE_NEAR=U5810.5:5mm

0201

X7R-CERM

10V

NO_XNET_CONNECTION=TRUE

2200PF

44 74

39

2

1

R5803

NOSTUFF

10K

MF

1/20W

201

5%

2

1

R5804

NOSTUFF

10K

MF

1/20W

201

5%

2

3

1

Q5850

BC846BLP

DFN1006H4-3

2

1

C5813

10% 10V

2200PF

NO_XNET_CONNECTION=TRUE

X7R-CERM

0201

44 74

2

1

R5802

100K

NOSTUFF

MF

1/20W

201

5%

2

1

R5811

22K

MF

1/20W

201

5%

2

3

1

Q5860

BC846BLP

DFN1006H4-3

2

1

R5806

100K

MF

1/20W

201

5%

39

2

1

C5830

25V

PLACE_NEAR=Q5830:3MM

NP0-C0G-CERM

47PF

0201

5%

2

1

C5811

25V

PLACE_NEAR=Q5810:3MM

NP0-C0G-CERM

47PF

0201

5%

2

1

C5860

25V

PLACE_NEAR=Q5860:3MM

NP0-C0G-CERM

47PF

0201

5%

2

1

C5820

25V

PLACE_NEAR=Q5820:3MM

NP0-C0G-CERM

47PF

0201

5%

2

1

C5840

25V

PLACE_NEAR=Q5840:3MM

NP0-C0G-CERM

47PF

0201

5%

2

1

C5850

25V

PLACE_NEAR=Q5850:3MM

NP0-C0G-CERM

47PF

0201

5%

SYNC_DATE=02/06/2013

Thermal Sensors

SYNC_MASTER=J41_MLB

TBDTHMSNS_D2_P

CPUTHMSNS_D2_P

INLET_THMSNS_D1_N

TBDTHMSNS_D2_P

TBDTHMSNS_D2_N

TBT_MLBBOT_THMSNS_N

TBT_MLBBOT_THMSNS_P

TBTTHMSNS_D2_R_N

TBTTHMSNS_D2_R_P

ISNS_HS_GAIN_P

TBT_MLBBOT_THMSNS_N

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

MAKE_BASE=TRUE

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

MAKE_BASE=TRUE

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

TBT_MLBBOT_THMSNS_P

PP3V3_S0_TBTMLB_ISNS_R

MIN_NECK_WIDTH=0.20 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm

TBT_MLBBOT_THMSNS_P

TBT_MLBBOT_THMSNS_N

TBT_INLET_THM_L

TBTMLBSNS_ALERT_L

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

PP3V3_S0

CPUTHMSNS_TH_SEL

CPUTHMSNS_D2_N

TBDTHMSNS_D2_N

ISNS_HS_GAIN_N

CPUTHMSNS_DUR_SEL

INLET_THMSNS_D1_P

CPUTHMSNS_ADDR_SEL

PP3V3_S0_CPUTHMSNS_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

CPUTHMSNS_ALERT_L

CPUBMONSNS_ALERT_L

<SCH_NUM>

58 OF 121

44 OF 76

74

44 74

74

44 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

74

w w w . c h i n a f i x . c o m

D

SYM_VER_3

S G

NC

OUT

IN

NC

08

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518S0793

GND

5V DC TACH

FAN CONNECTOR

MOTOR CONTROL

21

R6065

47K

MF

1/20W

201

5%

2

1

R6060

47K

MF

1/20W

201

5%

2

1

R6061

100K

MF

1/20W

201

5%

4

3

2

1

6

5

J6000

F-RT-SM

FF14A-4C-R11DL-B-3H

CRITICAL

2

1

3

Q6060

DMN32D2LFB4

DFN1006H4-3

37

4

6

53

1

2

U6010

74LVC1G08

SOT891

CRITICAL

NOSTUFF

2

1

C6010

BYPASS=U6010:3mm

NOSTUFF

6.3V CERM-X5R 0201

0.1UF

10%

21

R6010

MF

1/20W

0201

0

5%

Fan

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=3.3V

PP3V3_S0_FAN

FAN_RT_TACH

SMC_FAN_0_CTL

SMC_FAN_0_TACH

FAN_RT_PWM

PP5V_S0

PP3V3_S0

<SCH_NUM>

60 OF 121

45 OF 76

64

16 17 32 51 52 56 58 59 61 62 64

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 56 59 61 62

64 65 74

w w w . c h i n a f i x . c o m

BI

OUTOUT

VCC

D

B

A Y

OE*

C

GND

CS*

DI(IO0)

THRM_PAD

CLK

WP*(IO2) HOLD*(IO3)

DO(IO1)

VCC

GND

OUT

BI

OUT

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SAM Card ROM Slave

SPI Bus Series Termination

CPU Master

SMC12 Master

MLB ROM Slave

(SWDIO) (SWCLK)

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)

SPI ROM

Quad-IO Mode (Mode 0 & 3) supported.

in normal and Dual-IO modes.

IO2

IO3

SPI+SWD SAM Connector

SPI Frequency: 50MHz for CPU, 20MHz for SMC.

IO1

IO0

ROM will ignore SPI cycles

NOTE: If HOLD* is asserted

in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

37 38 64

15 46 64

37 38 64

9

8 7

6 5

4 3

2

16

15

14 13

12 11

10

1

J6100

SAMCONN

CRITICAL

DF40PC-12DP-0.4V-51

M-ST-SM

37 38 50 64

2

1

C6100

0201

BYPASS=U6100::3mm

10% 16V

X5R-CERM

0.1UF

2

1

C6101

0201

16V

10%

BYPASS=U6101::3mm

0.1UF

X5R-CERM

7

8

1

4

6

5

3

2

U6101

74LVC1G99

CRITICAL

SOT833

PLACE_NEAR=U6100.1:12MM

3

8

9

7

4

2

5

1

6

U6100

CRITICAL

W25Q64FVZPIG

64MBIT

WSON

OMIT_TABLE

46 69

21

R6120

PLACE_NEAR=R6125.2:5mm

1/20W

201

MF

43

5%

2

1

R6125

PLACE_NEAR=J6100.14:5mm

201

MF

43

1/20W

5%

SAMCONN

2

1

R6126

PLACE_NEAR=J6100.12:5mm

1/20W

5%

201

MF

43

SAMCONN

2

1

R6127

43

5% 1/20W MF 201

PLACE_NEAR=J6100.15:5mm

SAMCONN

2

1

R6128

201

MF

1/20W

1%

24.9

PLACE_NEAR=J6100.2:5mm

SAMCONN

21

R6110

5%

15

MF

201

1/20W

PLACE_NEAR=U0500.Y7:5mm

21

R6121

PLACE_NEAR=R6126.2:5mm

1/20W

5%

MF

43

201

21

R6116

1/20W

5%

MF

15

201

PLACE_NEAR=U6100.6:1mm

21

R6122

1/20W

5%

PLACE_NEAR=R6127.2:5mm

201

43

MF

21

R6123

24.9

1%

PLACE_NEAR=U6100.2:5mm

MF

201

1/20W

21

R6115

1/20W

15

MF

5%

201

PLACE_NEAR=U6100.5:1mm

21

R6114

1/20W

201

24.9

1%

MF

PLACE_NEAR=U6100.2:1mm

21

R6117

PLACE_NEAR=U6100.1:1mm

1/20W

15

5% MF

201

21

R6112

15

MF

201

5%

1/20W

PLACE_NEAR=U0500.AA2:5mm

21

R6111

201

15

MF

5%

1/20W

PLACE_NEAR=U0500.AA3:5mm

21

R6113

15

MF

5%

1/20W

PLACE_NEAR=U0500.AA2:5mm

201

37 69

14 69

21

R6118

PLACE_NEAR=U0500.Y6:5mm

15

MF

201

5%

1/20W

21

R6119

PLACE_NEAR=U0500.AF1:5mm

15

MF

5%

1/20W

201

14 69

21

R6130

1/20W

5%

201

43

MF

PLACE_NEAR=R6132.2:5mm

46 69

2

1

R6132

PLACE_NEAR=J6100.8:5mm

SAMCONN

201

MF

1/20W

5%

43

21

R6131

MF

43

201

5%

1/20W

PLACE_NEAR=R6133.2:5mm

2

1

R6133

PLACE_NEAR=J6100.10:5mm

43

5% 1/20W MF 201

SAMCONN

BOM_COST_GROUP=CPU SUPPORT

SPI Debug Connector

SYNC_DATE=01/09/2013

SYNC_MASTER=YHARTANTO_J44

SPI_MLB_CS_L

PP3V3_SUS

SPI_MLB_CLK

SPI_MLBROM_CS_L

SPI_MLB_IO2_WP_L SPI_MLB_IO3_HOLD_L

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISO

SPIROM_USE_MLB

SPI_MLB_CS_L

SPI_ALT_IO3_HOLD_L

SPI_ALT_IO1_MISO

SPI_ALT_IO0_MOSI

SPIROM_USE_MLB

SPI_ALT_CS_L

SPI_ALT_CLK

PP3V42_G3H

SMC_RESET_L

SPI_ALT_IO2_WP_L

SMC_TMS SMC_TCK

SPI_ALT_CS_L

SPI_ALT_IO0_MOSI

SPI_ALT_CLK

SPI_ALT_IO1_MISO

SPI_MLB_CLK

SPI_SMC_MISO

SPI_SMC_MOSI

SPI_SMC_CLK

SPI_SMC_CS_L

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISO

SPI_MLB_IO2_WP_L

SPI_CS0_L

SPI_CLK

SPI_CS0_R_L

SPI_CLK_R

SPI_MOSI_R

SPI_MISO

SPI_IO<2>

SPI_IO<3>

SPI_MOSI

SPI_MISO_R

SPI_IO2_R

SPI_ALT_IO2_WP_L

SPI_MLB_IO3_HOLD_L

SPI_ALT_IO3_HOLD_L

SPI_IO3_R

<SCH_NUM>

61 OF 121

46 OF 76

8

11 14 18 57 58 59 62 64

46 69

15 46 64

46 69

46 64

17 30 35 36 37 38 40 49 50 59 61 62 64 65

46 64

69

46 64

69

w w w . c h i n a f i x . c o m

IN

IN-

IN+

OUT+ OUT-

GAIN

SHDN*

PVDD

NC

PGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

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NOTICE OF PROPRIETARY PROPERTY:

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A

C

PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

ALIAS OF PP5VRT_S0, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.20MM

518S0519

SPEAKER AMPLIFIERS

80 HZ < FC < 132 HZ

APN:353S2888

GAIN

6DB

Right Speaker Connector

SPEAKER LOWPASS

21

C6410

0201

10% 16V

0.1UF

OMIT_TABLE

CRITICAL

X5R-CERM

61 65 74

61 65

61 65 74

C2

A1

A2

B1

C1

B2

A3

B3

C3

U6410

CRITICAL

MAX98300

WLP

2

1

R6412

201

100K

1/20W

5%

MF

21

C6411

0201

X5R-CERM

10% 16V

CRITICAL

OMIT_TABLE

0.1UF

2

1

R6411

1/20W

201

5%

MF

100K

2

1

R6413

5%

100K

NOSTUFF

MF

201

1/20W

21

R6414

603

1/10W

0

MF-LF

5%

2

1

C6407

X5R-CERM

16V

0201

10%

0.1UF

2

1

C6401

CRITICAL

POLY-TANT

20%

47UF

6.3V

0805-LLP

2

1

4

3

J6404

CRITICAL

M-RT-SM

78171-0002

132S0460

2

C6410,C6411

CRITICAL

CAP,CER,X5R,0.1UF,10%,16V,0201,MURATA

Audio: Speaker Amp

SYNC_MASTER=J41_MLB

SYNC_DATE=04/26/2013

PP5V_S3_U6210

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

SPKRAMP_INR_N

R_AMP_GAIN

MAX98300_R_P

MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.30 mm

SPKRAMP_ROUT_P

SPKRAMP_ROUT_N

MIN_LINE_WIDTH=0.30 mm

MIN_NECK_WIDTH=0.20 mm

SPKRAMP_SHDN_L

MAX98300_R_N

PP5V_S4RS3

SPKRAMP_INR_P

<SCH_NUM>

64 OF 121

47 OF 76

74 64 74

64 74 74

32 35 49 54 55 58 62 64

w w w . c h i n a f i x . c o m

IN BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518S0540

Battery Connector

13" SPECIFIC

37 40 50 64 73

2

1

3

D6950

RCLAMP2402B

NO STUFF

SC-75

CRITICAL

2

1

R6950

10K

5%

1/20W

MF

201

2

1

C6950

10%

402

25V X5R

0.1UF

2

1

C6951

X5R

1UF

16V

402

10%

9

8

7

6

5

4

3

2

1

J6950

WTB-PWR-M82

CRITICAL

M-RT-SM

Battery Connector

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

PPVBAT_G3H_CONN

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SYS_DETECT_L

<SCH_NUM>

69 OF 121

48 OF 76

50 64

64

w w w . c h i n a f i x . c o m

NC

G

D

S

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MLB to LIO Power Cable Connector

Vout = 3.425V

<Ra>

<Rb>

Vout = 1.25V * (1 + Ra / Rb)

518S0508

(Switcher limit)

sparkitecture requirements

Input impedance of 68K meets

for detection of B121 (16.5V)

300mA Max Output

6.8V Zener

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

6

5

4

3

2

1

J7000

CRITICAL

WTB-PWR-M82

M-RT-SM

21

L7095

CRITICAL

10UH-20%-0.85A-0.46OHM

2520

2

1

C7094

10%

CERM

0.22UF

10V

402

3

2

1

D7005

CRITICAL

BAT30CWFILM

SOT-323

21

R7006

4.7

805

MF-LF

1/8W

5%

21

R7005

1/8W

805

10

MF-LF

5%

2

1

R7095

1%

348K

MF

1/20W

201

2

1

R7096

200K

1%

MF

1/20W

201

2

1

R7010

100K

MF

1/20W

201

5%

5A

5

4

1

Q7010

SI5419DU

POWERPAK

CRITICAL

2

1

C7005

NO STUFF

0.1UF

603-1

X7R

50V

10%

2

1

C7006

0.1UF

0201

X5R-CERM

16V

10%

2

1

C7091

X5R

1UF

CRITICAL

10% 25V

402

2

1

C7090

CRITICAL

X5R

1UF

10% 25V

402

2

1

C7092

CRITICAL

20%

5.6UF

POLY-TANT CASE-B2-SM

25V

2

1

C7099

10V

0402-1

X5R-CERM

20%

10UF

CRITICAL

2

1

C7098

10V

0402-1

X5R-CERM

20%

10UF

CRITICAL

2

1

C7008

NO STUFF CRITICAL

1UF

603

X5R

35V

10%

2

1

C7007

CRITICAL

NO STUFF

1UF

603

X5R

35V

10%

21

R7011

1%

10K

MF

1/20W

201

6

9

48

7

5

1

3

2

U7090

CRITICAL

DFN

LT3470AED

2

1

R7012

68K

1%

MF

1/20W

201

2

1

R7080

MF

1/20W 0201

0

5%

2

1

R7081

1%

NO STUFF

49.9K

MF

1/20W 201

2

1

C7080

NO STUFF

1000PF

0402

CERM

25V

5%

2

1

C7012

CRITICAL

10% 25V X7R

0402

0.047UF

K

A

D7012

SDZT15R6.8

0201

CRITICAL

2

1

C7095

22PF

5% 50V C0G 0201

DC-In & G3H Supply

SYNC_DATE=09/13/2012

SYNC_MASTER=J43_MLB

DCIN_ISOL_GATE

DCIN_ISOL_GATE_R

PPDCIN_G3H

PPBUS_G3H

PPDCIN_G3H_ISOL

PP5V_S4RS3

P3V42G3H_SHDN_L

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PPVIN_G3H_P3V42G3H

P3V42G3H_BOOST

DIDT=TRUE MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

P3V42G3H_SW

SWITCH_NODE=TRUE DIDT=TRUE

VOLTAGE=8.6V

MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H_R

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=18.5V

PP18V5_DCIN_ISOL_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

P3V42G3H_FB

<SCH_NUM>

70 OF 121

49 OF 76

50 62 64

27 41 42 50 56 62 64

42 50 62 64

32 35 47 54 55 58

62 64

17 30 35 36 37 38 40 46 50 59 61 62 64 65

w w w . c h i n a f i x . c o m

OUT

IN BI

OUT

IN

S

G

D

IN

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

G

S

D

S

D

NCNCNCNC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(CHGR_CSO_P)

(GND)

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

Max Current = 8A

ACIN pin threshold is 3.2V, +/- 50mV

DIVIDER SETS ACIN THRESHOLD AT 13.55V

Float CELL for 1S

Reverse-Current Protection

(CHGR_AGATE)

Inrush Limiter

FROM ADAPTER

(AGND)

(OD)

36V/V

20V/V

Vout = 1.25V * (1 + Ra / Rb)

(Switcher limit)

.

(PPVBAT_G3H_CHGR_R)

<Ra>

<Rb>

Vout = 5.50V 200MA MAX OUTPUT

For Erp Lot6 spec

5.5v "G3Hot" Supply

(CHGR_DCIN)

TO/FROM BATTERY

Need to stuff R7192 if either PP5V5_DCIN:YES or PP5V5_VDDP are used!

TO SYSTEM

(CHGR_BGATE)

(CHGR_SGATE)

* R7151 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

f = 400 kHz

30mA max load

2

1

R7111

46.4K

1%

MF

1/20W

201

2

1

C7142

6.3V CERM-X5R 0201

0.1UF

10%

2

1

C7116

470PF

16V

0201

X5R-X7R-CERM

10%

2

1

C7115

470PF

X5R-X7R-CERM

16V

0201

10%

2

1

C7102

1UF

10V X5R

10%

402

2

1

C7100

1UF

402-1

10V X5R

10%

21

R7101

MF-LF

4.7

1/16W

402

5%

2

1

R7110

130K

1%

MF

1/20W

201

21

XW7100

PLACE_NEAR=U7100.22:1mm

SM

2

1

C7101

1UF

10V X5R

10%

402

2

1

C7121

X5R

0.1UF

10% 25V

402

2

1

C7122

X5R

0.1UF

10% 25V

402

2

1

C7120

0.047UF

16V X7R-CERM 0402

10%

2

1

C7125

PLACE_NEAR=U7100.25:2mm

CERM

10V

0.22UF

10%

402

21

R7122

10

MF

1/20W

201

5%

21

R7121

10

MF

1/20W

201

5%

2

1

C7130

CASE-D3L

POLY-TANT

CRITICAL

25V

20%

33UF-0.06OHM

2

1

C7131

33UF-0.06OHM

POLY-TANT

CRITICAL

CASE-D3L

25V

20%

21

F7140

8AMP-24V

1206

CRITICAL

2

1

R7186

332K

1%

MF

1/20W

201

2

1

R7181

62K

MF

1/20W

201

5%

2

1

C7105

0.22UF

X5R-CERM

50V

10%

0603-1

41

37 40 48 64 73

2

1

C7111

10V

X5R-CERM

0201

0.01UF

10%

2

1

C7150

0.47UF

10V

0402

X5R

10%

37 38 61 65

2

1

C7137

BYPASS=Q7130:1.5mm

0.001UF

X7R-CERM 0402

50V

10%

2

1

R7102

100K

NO STUFF

MF

1/20W

201

5%

59

321

4

5

Q7155

SI7137DP

SO-8

CRITICAL

2

1

R7113

100

MF

1/20W

201

5%

3

2

1

D7105

SOT-323

CRITICAL

BAT30CWFILM

2

1

C7185

0.1UF

10% 25V

402

X5R

2

1

R7180

100K

MF

1/20W

201

5%

2

1

R7185

470K

1%

MF

1/20W

201

2

1

C7135

1UF

603-1

X5R

10% 25V

2

1

C7136

1UF

603-1

X5R

10% 25V

21

R7100

MF

1/20W

0201

0

5%

37 38 46 64

2

1

C7114

603-1

1UF

X5R

10% 25V

2

1

C7113

X5R

0.1UF

10% 25V

402

2

1

C7112

0.01UF

X7R

10% 25V

402

2

1

C7117

805

10UF

X5R

10% 25V

21

R7151

2.2

MF

1/20W

201

5%

21

R7152

MF

1/20W

0201

0

5%

2

1

R7115

1%

255K

MF

1/20W

201

2

1

R7116

1%

10K

MF

1/20W

201

2

1

C7140

CASE-B2S

20%

TANT-POLY

11V

62UF-0.023OHM

2

1

C7143

62UF-0.023OHM

11V

20%

CASE-B2S

TANT-POLY

2

1

C7141

11V

TANT-POLY

20%

62UF-0.023OHM

CASE-B2S

21

L7130

CRITICAL

4.7UH-17A

PIMC104T4R7MN-SM

21

R7105

PP5V5_DCIN:NO

MF-LF

603

20

5%

1/10W

2

1

C7199

603

10UF

CRITICAL

10V

NO STUFF

X5R

20%

2

1

C7198

X5R

NO STUFF

603

10V

10UF

CRITICAL

20%

2

1

R7195

NO STUFF

1%

681K

MF

1/20W

201

2

1

R7196

1%

200K

NO STUFF

MF

1/20W

201

2

1

C7194

0.22UF

CERM

10V

10%

402

NO STUFF

6

9

48

7

5

1

3

2

U7190

CRITICAL

NO STUFF

DFN

LT3470A

21

R7190

PP5V5_DCIN:YES

MF-LF

1/16W

40205%

21

R7191

PP5V5_VDDP

1/16W

402

MF-LF05%

21

R7192

1/16W

MF-LF

NO STUFF

40205%

2

1

C7190

X5R-CERM

4.7UF

0603

NO STUFF

10% 25V

21

L7195

NO STUFF

CRITICAL

10UH-20%-0.85A-0.46OHM

2520

2

1

C7184

X5R-CERM

4.7UF

0603

10% 25V

8

12

4

20

19

7

24

29

13

26

10

11

23

22

21

5

2

18 17

28

27

6

25

15

16

9

1

14

3

U7100

TQFN

CRITICAL

ISL6259

251

4

3

6

1097

8

Q7180

CRITICAL

DIRECTFET-MC

IRF9395TRPBF

4

321

R7120

0.020

MF-LF 0612

CRITICAL

1W

0.5%

2

1

R7142

1K

MF

1/20W

201

5%

43

21

R7150

0612-4

0.5%

0.01

1W MF

765

10

8

1

9432

Q7130

CRITICAL

DFN

NTMFD4902NF

2

1

C7195

NO STUFF

0201

C0G

50V

5%

22PF

2

1

C7126

0201

X7R-1

16V

10%

1000PF

2

1

C7145

10% 16V X7R-1 0201

1000PF

BYPASS=L7130:Q7130:1.5mm

SYNC_MASTER=J43_MLB

PBus Supply & Battery Charger

SYNC_DATE=09/14/2012

CHGR_CSI_N

PPDCIN_G3H_ISOL

PP3V42_G3H

CHGR_CELL

CHGR_ICOMP_R

CHGR_ACIN

PPDCIN_G3H

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

CHGR_VFRQ

CHGR_VCOMP_R

CHGR_CSO_R_N

CHGR_CSO_R_P

CHGR_DCIN

PPBUS_G3H

PP5V1_CHGR_VDDP

SMC_BC_ACOK

CHGR_BMON

CHGR_AMON

CHGR_CSI_R_N

CHGR_AGATE_DIV

CHGR_RST_L

SMC_RESET_L

CHGR_VNEG_R

P5V1_FB

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

CHGR_BGATE

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=5.5V

PP5V5_CHGR_VDDP

SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_PHASE

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm VOLTAGE=8.6V

PPDCIN_G3H_CHGR

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

CHGR_LGATE

DIDT=TRUE

CHGR_UGATE

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

P5V1_SW

DIDT=TRUE

CHGR_CSO_P

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

PPCHGR_DCIN_D_R

MIN_LINE_WIDTH=0.5 mm

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=8.6V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

CHGR_CSI_P

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

CHGR_AGATE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

CHGR_SGATE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

CHGR_DCIN

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.2 mm

CHGR_CSI_R_P

MIN_NECK_WIDTH=0.2 mm

CHGR_BOOT

DIDT=TRUE

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

CHGR_ICOMP

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5.1V

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.5 mm

PPCHGR_DCIN_D_R

MIN_NECK_WIDTH=0.2 mm

CHGR_DCIN_D

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=8.6V

MIN_NECK_WIDTH=0.15 mm

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P5V1_BOOST

MIN_NECK_WIDTH=0.2 mm

CHGR_VNEG

MIN_LINE_WIDTH=0.2 mm

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

CHGR_VCOMP

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

CHGR_CSO_N

PP5V1_CHGR_VDD

VOLTAGE=5.1V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.6V

PPVBAT_G3H_CHGR_REG

<SCH_NUM>

71 OF 121

50 OF 76

73

42 49 62 64

17 30 35 36 37 38 40 46 49 59 61 62 64 65

49 62 64

43 73

50

27 41 42 49 56 62 64

50

73

50

73

50

73

50

48 64

73

w w w . c h i n a f i x . c o m

BI

IN

OUT

IN

OUT

ISEN3

ISEN2

ISEN1

IMON

ISUMN

ISUMP

FB2

FB

RTN

COMP

SCLK

ALERT*

SDA

NTC

VINVDD

FCCM

PWM1

PWM2

PWM3

DRSEL

PGOOD

THRM

VR_ON

PROG3

NC

NC NC

PROG2

SLOPE

VR_HOT*

PROG1

PAD

OUT

NC NC

OUT OUT

IN IN

IN

OUT

IN

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(CPUVR_ISUMP)

FCCM = 0: DCM FCCM = FLOATING: PS4

(GND)

FCCM = 1: Forced CCM

8

67

8

67

8

67

8

17

6

37 38 67

2

1

R7279

1%

54.9

PLACE_NEAR=U7200.32:2mm

MF

1/20W

201

2

1

R7280

PLACE_NEAR=U7200.30:2mm

1%

130

MF

1/20W

201

1

4

17

16

33

29

30

32

13

23

22 2026

27

28

2

5

24

21

19

9

15 14

10

11

12

3

18

8

7

25

6

31

U7200

LLP

CRITICAL

ISL95826HRZ-_R6200

8

17

52

21

R7224

MF

1/20W

0201

0

5%

21

R7202

402

1/16W MF-LF

10

5%

2

1

C7202

25V

10%

0402

PLACE_NEAR=U7200.17:2mm

0.22UF

X7R

21

R7201

402

1/16W MF-LF

1

5%

2

1

C7201

10%

X5R 402-1

1UF

10V

PLACE_NEAR=U7200.16:2mm

52

2

1

C7210

10%

0.01UF

10V

0201

X7R-CERM

2

1

C7211

10% 10V

0201

0.01UF

X7R-CERM

52

2

1

C7213

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

R7220

6.04K

1%

MF

1/20W

201

2

1

R7221

21K

1%

MF

1/20W

201

43

2

1

R7230

95.3K

1%

MF

1/20W

201

2

1

C7230

10% 10V

1800PF

X5R-CERM

201

52

2

1

C7214

25V

10%

X7R-CERM

NO_XNET_CONNECTION=TRUE

220PF

201

21

R7215

1%

845

MF

1/20W

201

21

C7215

25V

10%

X7R-CERM

820PF

0201

8

67

9

67

2

1

C7240

0201-1

+/-10%

1.2NF

CERM

10V

2

1

R7240

75K

NO_XNET_CONNECTION=TRUE

1%

MF

1/20W

201

2 1

R7242

1%

1K

MF

1/20W

201

21

R7243

NO_XNET_CONNECTION=TRUE

MF

1/20W

0201

0

5%

21

R7235

9.31K

1%

MF

1/20W

201

2

1

R7236

95.3K

1%

MF

1/20W

201

2

1

R7237

0201

100KOHM

21

R7250

NOSTUFF

NO_XNET_CONNECTION=TRUE

2K

1%

MF

1/20W

201

21

R7241

1.37K

1%

MF

1/20W

201

21

R7210

1%

255

MF

1/20W

201

2

1

R7223

1%

16.9K

MF

1/20W

201

2

1

R7222

9.31K

1%

MF

1/20W

201

21

XW7261

NO_XNET_CONNECTION=TRUE

SM

2

1

R7225

NOSTUFF

MF

1/20W

0201

0

5%

2

1

C7278

10%

0.1UF

0201

CERM-X5R

6.3V

PLACE_NEAR=R7279.32:2mm

2 1

C7242

100PF

5% 25V C0G

0201

NO_XNET_CONNECTION=TRUE

21

C7216

47PF

5%

25V C0G

0201

2

1

C7241

NO_XNET_CONNECTION=TRUE

0201

NP0-C0G

25V

5%

56PF

2

1

C7261

330PF

10%

X7R

16V

0201

2

1

C7260

330PF

10%

X7R

16V

0201

2

1

C7250

0201

16V X7R

10%

330PF

NOSTUFF

SYNC_DATE=10/09/2012

SYNC_MASTER=J43_MLB

CPU VR12.6 VCC Regulator IC

CPUVR_FB_RC

CPU_VCCSENSE_N

CPU_VCCSENSE_P

VOLTAGE=12.9V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVIN_S0_CPUVR_VIN

PP5V_S0_CPUVR_VDD

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

CPU_VCCSENSE_P_RC

CPU_VCCSENSE_P_R

CPUVR_PROG2

CPU_RTN

CPU_VIDALERT_L

CPUVR_PROG1

CPU_VR_READY

CPU_VR_EN

CPUVR_SLOPE

CPUVR_DRSEL

CPUVR_ISUMN

CPU_VIDSOUT

CPUVR_ISEN1

CPUVR_ISUMP

CPU_VIDSCLK

CPU_PROCHOT_L

CPUVR_FCCM

CPUVR_NTC

PP1V05_S0

CPUVR_NTC_R

CPUVR_ISUMN_RC

CPUVR_COMP_RC

PP5V_S0

PPBUS_S5_HS_COMPUTING_ISNS

CPUVR_PWM2

CPUVR_IMON

CPUVR_PWM1

CPUVR_PROG3

CPUVR_ISUMN_R

CPUVR_FB2

CPUVR_COMP

CPUVR_FB

CPUVR_ISEN2

<SCH_NUM>

72 OF 121

51 OF 76

6 8

11 15 16 17 38 42 55 58

59 62 64

16 17 32 45 52 56 58 59 61 62 64

41 52 53 55 62 64

w w w . c h i n a f i x . c o m

IN

OUT

IN

OUT

IN

D

S

G

D

S

G

D

S

G

D

S

G

OUTOUT

THRM

PAD

PHASE

VCC

LGATE

BOOT

UGATE

FCCM

GND

PWM

THRM

PAD

PHASE

VCC

LGATE

BOOT

UGATE

FCCM

GND

PWM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Additonal Input Bulk Caps

PHASE 1

PHASE 2

353S3942

152S1757

.

THESE TWO CAPS ARE FOR EMC

Vout = 1.85V max f = 700kHz

353S3942

32A max output

2

1

C7372

CRITICAL

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

2

1

C7371

CRITICAL

62UF-0.023OHM

CASE-B2S

11V TANT-POLY

20%

2

1

C7370

CASE-B2S

11V TANT-POLY

CRITICAL

20%

62UF-0.023OHM

2

1

C7319

X7R-CERM 0402

0.001UF

10% 50V

2

1

C7318

0.001UF

10% 50V X7R-CERM 0402

2

1

C7317

16V

0402

1UF

X6S-CERM

10%

2

1

C7316

10UF

CRITICAL

20% 16V

NOSTUFF

0603

X6S-CERM

2

1

C7315

0603

10UF

CRITICAL

NOSTUFF

X6S-CERM

16V

20%

2

1

R7314

0201

MF-LF

1/20W

1%

1.00

2

1

C7314

62UF-0.023OHM

20% 11V TANT-POLY CASE-B2S

CRITICAL

2

1

C7313

CASE-B2S

CRITICAL

11V TANT-POLY

20%

62UF-0.023OHM

21

L7310

0.40UH-20%-16A

MPCG0730-SM

CRITICAL

2

1

R7312

2.2

603

5% 1/10W MF-LF

NOSTUFF

2

1

C7312

10%

X7R-CERM 0402

50V

0.001UF

NOSTUFF

51

51 52

2

1

C7373

CASE-B2S

CRITICAL

11V TANT-POLY

20%

62UF-0.023OHM

2

1

R7316

NO_XNET_CONNECTION=TRUE

201

200K

1%

MF

1/20W

2

1

R7315

201

MF

1%

1K

1/20W

51

51 52

21

R7317

NONE 0201

NO_XNET_CONNECTION=TRUE

NONE

OMIT

NOSTUFF

2

1

C7329

0.001UF

0402

50V

10%

X7R-CERM

51 52

2

1

C7328

0402

X7R-CERM

50V

10%

0.001UF

2

1

C7327

X6S-CERM

16V

0402

10%

1UF

2

1

R7324

0201

1/20W MF-LF

1.00

1%

2

1

C7326

20% 16V X6S-CERM 0603

10UF

CRITICAL

NOSTUFF

2

1

C7325

CRITICAL

20% 16V

10UF

X6S-CERM 0603

NOSTUFF

2

1

C7324

CASE-B2S

20% 11V

CRITICAL

62UF-0.023OHM

TANT-POLY

2

1

C7323

CASE-B2S

20%

TANT-POLY

CRITICAL

11V

62UF-0.023OHM

21

L7320

CRITICAL

MPCG0730-SM

0.40UH-20%-16A

2

1

C7322

50V

0.001UF

NOSTUFF

0402

X7R-CERM

10%

2

1

R7326

NO_XNET_CONNECTION=TRUE

1%

201

200K

MF

1/20W

2

1

R7325

1%

MF

1/20W

1K

201

2

1

R7322

NOSTUFF

603

2.2

5% 1/10W MF-LF

51

21

R7327

NO_XNET_CONNECTION=TRUE

NONE

OMIT

NOSTUFF

NONE NONE

0201

51

51 52

2 1

R7311

MF-LF

402

5%

1/16W

2.2

21

C7311

402

CERM

10% 16V

0.22UF

2

1

C7310

X6S-CERM

1UF

10% 16V

0402

2

1

C7320

0402

X6S-CERM

10%

1UF

16V

51 52

2

1

C7376

CASE-B2S

20%

TANT-POLY

CRITICAL

62UF-0.023OHM

11V

2

1

C7375

CASE-B2S

TANT-POLY

11V

20%

62UF-0.023OHM

CRITICAL

2

1

C7377

CRITICAL

CASE-B2S

TANT-POLY

11V

20%

62UF-0.023OHM

2

1

C7374

CASE-B2S

CRITICAL

11V TANT-POLY

20%

62UF-0.023OHM

2 1

R7321

402

2.2

5% 1/16W MF-LF

21

C7321

0.22UF

CERM

10% 16V

402

321

4

5

Q7310

SISA18DN

PWRPAK-SM

CRITICAL

OMIT_TABLE

321

4

5

Q7320

CRITICAL

SISA18DN

PWRPAK-SM

OMIT_TABLE

4 3

2 1

R7310

0.00075

1% 1W MF

0612

CRITICAL

43

21

R7320

CRITICAL

0.00075

1W

1%

MF

0612

321

4

5

Q7311

SISA12DN

PWRPAK-SM

CRITICAL

OMIT_TABLE

321

4

5

Q7321

SISA12DN

PWRPAK-SM

CRITICAL

OMIT_TABLE

42 52 74 42 74

6

1

9

3

8

5

4

7

2

U7310

CRITICAL

DFN

ISL6208D

6

1

9

3

8

5

4

7

2

U7320

CRITICAL

DFN

ISL6208D

SYNC_DATE=05/21/2013

CPU VR12.5 VCC Power Stage

SYNC_MASTER=J41_MLB

PPBUS_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

CPUVR_BOOT2

DIDT=TRUE

PP5V_S0

CPUVR_ISNS2_P

CPUVR_ISEN1

PPVCC_S0_CPU_PH1

MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUVR_PHASE1

CPUVR_FCCM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

CPUVR_BOOT1

DIDT=TRUE

CPUVR_PH1_SNUB

CPUVR_BOOT2_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

CPUVR_LGATE2

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUVR_PHASE2

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

CPUVR_BOOT1_RC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

CPUVR_LGATE1

CPUVR_ISEN2

CPUVR_ISUMP

CPUVR_ISNS2_N

CPUVR_ISUMN

CPUVR_ISNS1_N

CPUVR_ISNS2_N

CPUVR_ISUMP

MIN_NECK_WIDTH=0.25 MM

PPVCC_S0_CPU_PH2

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

CPUVR_ISNS1_N

DIDT=TRUE

CPUVR_PH2_SNUB

CPUVR_PWM1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

CPUVR_UGATE1

DIDT=TRUE

CPUVR_FCCM

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

CPUVR_UGATE2

MIN_NECK_WIDTH=0.2 MM

CPUVR_PWM2

PP5V_S0

CPUVR_ISNS1_P

PPVCC_S0_CPU

<SCH_NUM>

73 OF 121

52 OF 76

41 51 53 55 62 64

16 17 32 45 51 52 56 58 59 61

62 64

42 52 74

16 17 32 45 51 52 56 58 59 61 62 64

8

10 42 62 64

w w w . c h i n a f i x . c o m

BG

TGR

TG

PGND

VIN

VSW

IN

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(DDRREG_DRVH)

Vout = 1.35V

14.1A max output

(Q7435 limit)

f = 400 kHz

10mA max load

(VDDQ/VTTREF Enable)

(VTT Enable)

(DDRREG_LL)

(DDRREG_DRVL)

(DDRREG_VDDQSNS)

2

1

C7462

20%

603

X5R

6.3V

10UF

CRITICAL

BYPASS=U7400.3:3mm

8

7

6

1

4

3

9

5

Q7430

Q3D

CSD58873Q3D

CRITICAL

2

1

R7435

2.2

5%

NOSTUFF

1/10W MF-LF 603

2

1

C7435

NOSTUFF

X7R-CERM

0402

50V

0.001UF

10%

21

R7460

201

5%

10

1/20W

MF

2

1

C7400

20%

603

BYPASS=U7400.12:1mm

10UF

X5R

10V

2

1

C7432

10%

603-1

25V X5R

1UF

21

C7425

0.1UF

402

X5R

10% 25V

2

1

C7433

10% X7R-CERM

0402

50V

0.001UF

2

1

C7445

20%

6.3V

10UF

603

X5R

2

1

C7446

X7R-CERM

0402

50V

10%

0.001UF

2

1

XW7401

PLACE_NEAR=C7440.1:1mm

SM

59

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14

U7400

CRITICAL

QFN

TPS51916

59

21

XW7460

PLACE_NEAR=C2720.1:3mm

SM

2

1

XW7400

PLACE_NEAR=U7400.21:1mm

SM

2

1

C7450

10%

CERM

402

10V

0.22UF

17

2

1

C7415

0.1UF

0402

X7R-CERM

10% 16V

BYPASS=U7400.6:1mm

2

1

R7417

PLACE_NEAR=U7400.19:3mm

1% 1/20W

201

200K

MF

2

1

R7415

201

MF

1% 1/20W

PLACE_NEAR=U7400.8:5mm

28.7K

2

1

R7416

1/20W

57.6K

MF 201

1%

PLACE_NEAR=U7400.8:5mm

2

1

C7416

16V

10%

0402

X7R-CERM

0.01UF

BYPASS=U7400.8:1mm

2

1

C7401

20%

BYPASS=U7400.2:1mm

603

10UF

X5R

10V

21

R7425

402

1/16W

MF-LF

0

5%

21

L7430

1.0UH-20%-11A-0.011OHM

FDSD0630-SM

CRITICAL

43

21

R7450

1206

0.002

1/4W

MF-LF

1%

CRITICAL

41 74

2

1

R7418

1/20W

1%

MF

PLACE_NEAR=U7400.18:3mm

49.9K

201

2

1

C7440

20%

CRITICAL

2.0V CASE-B2-SM1

330UF

POLY-TANT

2

1

C7441

20%

CRITICAL

2.0V

CASE-B2-SM1

POLY-TANT

330UF

2

1

C7430

CASE-B2S

20% TANT-POLY

11V

62UF-0.023OHM

2

1

C7431

TANT-POLY

20% 11V

CASE-B2S

62UF-0.023OHM

2

1

C7434

20% TANT-POLY

11V

62UF-0.023OHM

CASE-B2S

SYNC_DATE=05/21/2013

SYNC_MASTER=J41_MLB

LPDDR3 Supply

PPBUS_S5_HS_COMPUTING_ISNS

DDRREG_DRVH

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST

MIN_LINE_WIDTH=0.2 mm

DDRREG_FB

MIN_NECK_WIDTH=0.1 mm

ISNS_1V2_S3_N

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

PPVTT_S3_DDR_BUF

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVL

DIDT=TRUE

GATE_NODE=TRUE

PP0V6_S0_DDRVTT

PP1V2_S3

DIDT=TRUE

PDDR_S3_REG_SNUB

MIN_NECK_WIDTH=0.1 MM

DIDT=TRUE

PDDR_S3_REG_L

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

DDRREG_VBST_RC

PP5V_S5

ISNS_1V2_S3_P

DDRREG_MODE DDRREG_TRIP

MIN_NECK_WIDTH=0.1 mm

DDRREG_VTTSNS

MIN_LINE_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM

PPDDR_S3_REG_R

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2 mm

DDRREG_VDDQSNS_R

MIN_NECK_WIDTH=0.17 mm

PP1V2_S3

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_1V8_VREF

DDRREG_EN

MEMVTT_PWR_EN

GND_DDRREG_SGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.15 mm

DDRREG_PGOOD DDRREG_VDDQSNS

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

SWITCH_NODE=TRUE

DDRREG_LL

<SCH_NUM>

74 OF 121

53 OF 76

41 51 52 55 62 64

19

24

62

17 19 20 21 22 23 42 53 62 70

36 54 62

17 19 20 21 22 23 42 53

62 70

w w w . c h i n a f i x . c o m

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1 SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2 CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

BG

TGR

TG

PGND

VIN

VSW

BG

TGR

TG

PGND

VIN

VSW

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

152S1798

Vout = 3.3V

152S1798

6.5A MAX OUTPUT7.2A MAX OUTPUT

F=400KHZ

SKIPSEL Strap

F=400KHZ

Vout = 5.0V

353S3905

VREG3

VREF2

OOA Auto Skip (Lower Efficiency)

Auto Skip (Higher Efficiency)

2

1

C7500

1UF

402

X5R

16V

10%

21

L7560

2.2UH-20%-9A-0.012OHM

PIME063T2R2MS-SM

CRITICAL

2

1

C7541

X5R

16V

402

10%

1UF

2

1

C7564

X5R

0.1UF

402

10% 25V

2

1

C7524

25V X5R

0.1UF

10%

402

2

1

C7552

CRITICAL

150UF-0.035OHM

20%

CASE-B2-SM

POLY-TANT

6.3V

2

1

C7581

1UF

10%

X5R 402

16V

2

1

R7506

1%

249K

MF

1/20W

201

59

2

1

XW7561

SM

PLACE_NEAR=L7560.2:3mm

2

1

C7501

0.22UF

402

CERM

10V

10%

2

1

R7560

23.2K

1%

MF

1/20W

201

2

1

R7561

1%

10K

MF

1/20W

201

2

1

R7520

1%

41.2K

MF

1/20W

201

2

1

R7521

10K

1%

MF

1/20W

201

21

XW7500

SM

PLACE_NEAR=U7501.28:1mm

2

1

R7516

6.65K

1%

MF

1/20W

201

21

R7546

1.54K

1%

MF

1/20W

201

2

1

XW7560

PLACE_NEAR=L7560.1:3mm

SM

21

C7518

0402

16V

10%

X7R-CERM

0.1UF

21

R7547

1/20W

1.33K

1%

MF

201

2

1

R7556

4.22K

1%

MF

1/20W

201

2

1

XW7520

SM

PLACE_NEAR=L7520.1:3mm

2

1

XW7521

SM

PLACE_NEAR=L7520.2:3mm

2

1

R7536

7.5K

1%

MF

1/20W

201

2

1

R7537

1%

20K

NO STUFF

MF

1/20W

201

2

1

XW7562

SM

PLACE_NEAR=L7560.2:3mm

2

1

XW7522

SM

PLACE_NEAR=L7520.1:3mm

2

1

C7592

20%

CASE-B2-SM

CRITICAL

TANT

6.3V

150UF-0.018OHM-1.8A

2

1

R7539

1%

20K

MF

1/20W

201

2

1

C7539

0201

5%

6.3V

22PF

NP0-C0G

2

1

R7538

1%

7.5K

MF

1/20W

201

2

1

C7538

10V X7R

10%

4700PF

201

59 59

21

R7548

NO STUFF

MF

1/20W

0201

0

5%

2

1

R7549

MF

1/20W

0201

0

5%

29

22

13

23

16

9

26

31

2

33

25

32

19

6

3

20

5

14

11

28

21

4

12

27

30

24

1

18

7

17

8

15

10

U7501

TPS51980A

QFN

CRITICAL

2

1

R7545

MF-LF

1/16W

402

0

5%

2

1

R7551

PLACE_NEAR=U7501.4:2mm

MF

1/20W

0201

0

5%

2

1

R7552

PLACE_NEAR=U7501.21:2mm

MF

1/20W

0201

0

5%

37 59

37 38 59

2

1

C7536

10V X7R

10%

4700PF

201

2

1

C7537

0201-1

10%

270PF

X7R-CERM

16V

21

C7588

0.1UF

0402

10% 16V

X7R-CERM

1

2

R7564

1/16W

402

MF-LF

0

5%

2

1

C7554

CRITICAL

ELEC

6.3V

CASE-B2S

62UF

20%

2

1

C7590

10V

10UF

X5R 603

20%

2

1

C7550

10V X5R

10UF

603

20%

21

L7520

PIME063T2R2MS-SM

2.2UH-20%-9A-0.012OHM

CRITICAL

2

1

C7505

10UF

10V

603

X5R

20%

2

1

C7542

11V

TANT-POLY

20%

62UF-0.023OHM

CASE-B2S

2

1

C7540

11V

20%

62UF-0.023OHM

TANT-POLY

CASE-B2S

2

1

C7584

20%

TANT-POLY

11V

62UF-0.023OHM

CASE-B2S

2

1

C7582

62UF-0.023OHM

TANT-POLY

11V

20%

CASE-B2S

2

1

R7500

MF

1/20W

0201

0

5%

2

1

R7501

NOSTUFF

MF

1/20W

0201

0

5%

2

1

C7503

X5R-CERM

2.2UF

10V

402

20%

8

7

6

1

4

3

9

5

Q7560

CSD58873Q3D

CRITICAL

Q3D

8

7

6

1

4

3

9

5

Q7520

CSD58873Q3D

CRITICAL

Q3D

2

1

C7562

10%

0.001UF

X7R-CERM

50V

0402

NOSTUFF

2

1

R7562

2.2

1/10W MF-LF

603

NOSTUFF

5%

2

1

R7522

1/10W

NOSTUFF

2.2

MF-LF 603

5%

2

1

C7522

0402

50V

X7R-CERM

10%

NOSTUFF

0.001UF

2

1

R7523

10

MF

1/20W

201

5%

2

1

R7563

10

MF

1/20W

201

5%

2

1

C7553

150UF-0.035OHM

CRITICAL

CASE-B2-SM

20%

6.3V

POLY-TANT

2

1

C7593

150UF-0.018OHM-1.8A

CASE-B2-SM

CRITICAL

TANT

6.3V

20%

2

1

C7594

20%

6.3V TANT

CRITICAL

CASE-B2-SM

150UF-0.018OHM-1.8A

2

1

C7570

BYPASS=Q7520.1:1.5mm

1000PF

10% 16V X7R-1 0201

2

1

C7571

PLACE_NEAR=L7520.1:1.5mm

0201

X7R-1

16V

10%

1000PF

2

1

C7572

PLACE_NEAR=L7560.2:1.5mm

1000PF

10% 16V X7R-1 0201

2

1

C7583

BYPASS=Q7560.1:1.5mm

0201

X7R-1

16V

10%

1000PF

5V S4RS3 / 3.3V S5 Power Supply

SYNC_MASTER=J41_MLB

SYNC_DATE=09/17/2012

Power

PPBUS_S5_HS_OTHER_ISNS

PP3V3_S5_REG_R

PP5V_S4RS3

PP5V_S5

P5VP3V3_VREG3

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP5V_S4RS3

P3V3_S5_COMP2

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P3V3_S5_VFB2

P3V3_S5_CSN2

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P5V_S4RS3_CSP1

P5VP3V3_VREG3

P5VS4RS3_EN_R

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

GND_P5VP3V3_SGND MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P3V3_S5_REG_L

DIDT=TRUEMIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.1 mm

P3V3_S5_CSP2_R

P3V3_S5_REG_SNUB

DIDT=TRUE

P3V3S5_EN_R

S5_PWRGD

SMC_PM_G2_EN

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P3V3_S5_DRVH

GATE_NODE=TRUE

DIDT=TRUE

P5VP3V3_VREF2

P5V_S4RS3_CSN1

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

P5VS4RS3_PGOOD

P5VP3V3_VREF2

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P5V_S4RS3_VFB1

P3V3_S5_RF

P5VP3V3_SKIPSEL

P5VP3V3_VREF2

P5V_S4RS3_DRVH

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUEMIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

P3V3_S5_CSP2

S5_PWR_EN

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3_S5_DRVL

GATE_NODE=TRUE

P3V3_S5_VFB2_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P3V3_S5_VFB2_XW

MIN_NECK_WIDTH=0.1 mm

P5V_S4RS3_VFB1_XW

MIN_LINE_WIDTH=0.2 mm

P5V_S4RS3_VFB1_R

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P5V_S4RS3_DRVL

GATE_NODE=TRUE

DIDT=TRUEMIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

DIDT=TRUEMIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

P5V_S4RS3_LL

P5V_S4RS3_FUNC

DIDT=TRUE

P5V_S4RS3_REG_SNUB

P5V_S4RS3_VBST

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3_S5_VBST_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P5V_S4RS3_COMP1

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P5V_S4RS3_COMP1_R

P3V3_S5_COMP2_R

P5VS4RS3_EN

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P3V3_S5_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3_S5_VBST

DIDT=TRUE

P5V_S4RS3_VBST_R

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P5V_S4RS3_REG_L

DIDT=TRUE

P5V_S4RS3_CSP1_R MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

54 OF 76

<SCH_NUM>

75 OF 121

41 62 64

42 32 35 47 49 54 55 58

62 64

36 53 62

54

32 35 47 49 54 55 58 62 64

54

54 54

54

w w w . c h i n a f i x . c o m

GND

HSG

V+

LSG

SW

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Scrub S3 & S5 pins connections!

Vout = 1.05V

21A Max Output

f = 300 kHz

1.05V S0 Regulator

2

1

C7630

0402

10% 16V X7R-CERM

0.1UF

2

1

C7623

PLACE_NEAR=L7630.2:1.5mm

5%

1000PF

0402

CERM

25V

2

1

C7622

PLACE_NEAR=Q7630.8:1.5mm

CERM

5%

1000PF

25V

0402

2

1

R7630

5%

603

2.2

MF-LF

1/10W

21

R7631

5%

1/16W

MF-LF

402

0

2

1

C7648

CASE-B2-SM1

POLY-TANT

CRITICAL

330UF

2.0V

20%

2

1

C7649

POLY-TANT

CASE-B2-SM1

CRITICAL

330UF

2.0V

20%

21

L7630

1.0UH-20%-11A-0.011OHM

CRITICAL

FDSD0630-SM

2

1

C7619

CASE-B2S

11V TANT-POLY

20%

62UF-0.023OHM

2

1

C7620

CASE-B2S

62UF-0.023OHM

11V

TANT-POLY

20%

2

1

C7621

CASE-B2S

TANT-POLY

11V

20%

62UF-0.023OHM

9

8

4

3

2

7

1

10

6

5

Q7630

FDPC1012S

LLP

CRITICAL

2

1

C7624

X5R

1UF

16V

10%

402

2

1

C7632

NOSTUFF

0.001UF

X7R-CERM

0402

10% 50V

2

1

R7632

603

5%

2.2

1/10W MF-LF

NOSTUFF

2

1

C7650

402

CERM

0.22UF

10V

10%

2

1

XW7600

SM

PLACE_NEAR=U7600.21:1mm

2

1

C7601

BYPASS=U7600.2:1mm

603

10V X5R

10UF

20%

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14

U7600

TPS51916

QFN

CRITICAL

2

1

R7614

201

17.4K

1/20W MF

1%

PLACE_NEAR=U7600.18:3mm

2

1

C7600

10UF

BYPASS=U7600.12:1mm

X5R 603

10V

20%

2

1

R7613

PLACE_NEAR=U7600.19:3mm

201

1% MF

1/20W

47.5K

2

1

C7616

BYPASS=U7600.8:1mm

0402

0.01UF

X7R-CERM

10% 16V

2

1

R7611

PLACE_NEAR=U7600.8:5mm

35.7K

1/20W

1%

201

MF

2

1

R7612

PLACE_NEAR=U7600.8:5mm

1/20W

201

49.9K

1%

MF

2

1

C7615

BYPASS=U7600.6:1mm

10%

0.1UF

X7R-CERM

16V

0402

2

1

R7610

MF

1% 1/20W

1K

201

2

1

XW7610

SM

PLACE_NEAR=C7648.1:1mm

21

R7641

5%

MF

1/20W

10

201

42 74

59

43

21

R7640

CYN

0612-SHORT

0.003

1% 1w

OMIT

1.05V S0 Power Supply

SYNC_DATE=05/21/2013

SYNC_MASTER=J41_MLB

PPBUS_S5_HS_COMPUTING_ISNS

P1V05S0_PGOOD

P1V05S0_BOOT_RC

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

P1V05S0_DRVL

PP1V05_S0

P1V05S0_VTT

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

P1V05S0_VDDQSNS

P1V05S0_EN

P1V05S0_LL_SNUB

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

P1V05S0_DRVH

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P1V05S0_FB

PP5V_S4RS3

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V05S0_AGND

P1V05S0_VTTREF

MIN_NECK_WIDTH=0.2 mm

P1V05S0_LL

SWITCH_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

P1V05S0_VDDQSNS_R

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0_REG_R

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0

ISNS_1V05_S0_P

ISNS_1V05_S0_N

P1V05S0_TRIP

P1V05S0_MODE

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm

P1V05_S0_VREF

P1V05S3_EN

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

P1V05S0_VBST

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P1V05S0_DRVH_R

<SCH_NUM>

76 OF 121

55 OF 76

41 51 52 53 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

59

32 35 47 49 54 58 62 64

6 8

11 15

16 17 38

42 51 55

58 59 62

64

w w w . c h i n a f i x . c o m

VDDIO

VIN

VLDO

SW_0 SW_1

FB

OUT3

OUT2

OUT1

OUT4 OUT5 OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

OUT

TP

BI

NC

VIN

SW

OUT

FB

EN

NC

THRM

GND

PAD

NC

VER 3

D

SG

VER 3

D

SG

IN

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

*C7797 AND C7799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS *PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

(EEPROM should set EN_I_RES=1)

I_LED=17.1mA

(GND_BKL_SGND)

Addr: 0x58(Wr)/0x59(Rd)

Keyboard Backlight Connector

518S0793

43 mOhm @4.5V

0.65 A (EDP)

P-TYPE

FDC638APZ

ON THE SENSOR PAGE

CHANNEL

MOSFET

PPBUS S0 LCDBkLT FET

THERE IS A SENSE RESISTOR BETWEEN

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

I_LED=369/Riset

RDS(ON)

LOADING

AND PPBUS_SW_BKL

PPBUS_SW_LCDBKLT_PWR

see spec for others

Fpwm=9.62kHz

measurement on LED strings.

10.2 ohm resistors for current

Keyboard Backlight Driver & Detection

2

1

C7799

10% X5R

1210-1

50V

10UF

CRITICAL

PLACE_NEAR=D7701.2:5mm

2

1

C7797

10% X5R

1210-1

50V

10UF

CRITICAL

PLACE_NEAR=D7701.2:3mm

21

L7701

PIMB053T-SM

15UH-2.8A

CRITICAL

D2

D1

C1

C4

B2

B1

D4

D3

A4

E1

E2

E3

C5

D5

E5

B3

A2

A1B5E4

B4

C2

A5

C3

A3

U7701

CRITICAL

LP8550

25-BUMP-MICRO

18

13

2

1

R7789

201

1/20W MF

1%

147K

21

F7700

3AMP-32V-467

603-HF

PLACE_SIDE=BOTTOM

2

1

R7788

201

1/20W MF

1%

301K

2

1

C7782

10%

0.1UF

16V

0402

X7R-CERM

4

3

6521

Q7706

FDC638APZ_SBMS001

CRITICAL

SSOT6-HF

21

XW7720

SM

PLACE_NEAR=C7797.1:5mm

2

1

R7714

201

1/20W

MF

21.5K

1%

21

R7731

201

1/20W

MF

1%

200K

2

1

R7715

201

1/20W MF

1%

100K

21

R7741

5%

201

1/20W

MF

10K

21

R7753

5%

0

0201

1/20W

MF

21

R7757

5%

0

0201

1/20W

MF

21

R7704

5%

201

1/20W

MF

33

2

1

R7716

201

1/20W MF

1%

90.9K

2

1

R7755

5%

201

1/20W MF

10K

2

1

C7711

10%

0.1UF

0201

CERM-X5R

6.3V

BYPASS=U7701.C4:4mm

2

1

C7714

10%

BYPASS=U7701.D1:3mm

0.01UF

X5R-CERM 0201

10V

21

R7717

5%

0

402

1/16W MF-LF

BKLT:PROD

PLACE_NEAR=U7701.E5:10mm

60 64

21

R7718

5%

0

402

BKLT:PROD

MF-LF1/16W

PLACE_NEAR=U7701.D5:10mm

60 64

21

R7719

5%

0

402

1/16W MF-LF

BKLT:PROD

PLACE_NEAR=U7701.C5:10mm

21

R7720

5%

0

402

BKLT:PROD

MF-LF1/16W

PLACE_NEAR=U7701.E3:10mm

60 64

21

R7721

5%

0

402

1/16W MF-LF

BKLT:PROD

PLACE_NEAR=U7701.E2:10mm

21

R7722

5%

0

402

BKLT:PROD

MF-LF1/16W

PLACE_NEAR=U7701.E1:10mm

1

TP7701

PLACE_SIDE=BOTTOM

TP-P6

37

2

1

R7700

5%

402

4.7

1/16W MF-LF

2

1

C7750

10%

X5R

10V

402-1

1UF

BYPASS=U7750.1:2:2 MM

21

L7750

CRITICAL

1098AS-SM

10UH-0.58A-0.35OHM

2

1

C7755

10% 50V X5R-CERM 0603-1

0.22UF

2

1

C7756

10%

0.22UF

0603-1

X5R-CERM

50V

2

9

7

1

5

8

4

6

3

U7750

SPN035007G

MLF

CRITICAL

4

3

2

1

6

5

J7715

CRITICAL

F-RT-SM

FF14A-4C-R11DL-B-3H

4

5

3

Q7707

SOT563

DMN5L06VK-7

1

2

6

Q7707

DMN5L06VK-7

SOT563

2

1

C7704

33PF

5% 25V NP0-C0G 0201

2

1

C7712

25V

10% X5R

10UF

805

CRITICAL

PLACE_NEAR=L7701.1:3mm

2

1

C7713

402

25V

10%

0.1UF

X5R

PLACE_NEAR=L7701.1:3mm

2

1

C7796

10% X7R-CERM

50V 0402

220PF

PLACE_NEAR=U7701.A5:3mm

KA

D7701

SOD-123

RB160M-60G

CRITICAL

PLACE_NEAR=L7701.2:3mm

2

1

C7710

25V

10% X5R

BYPASS=U7701.D1:5mm

1UF

603-1

21

XW7710

SM

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

13

14 16 19 40 69

LCD/KBD Backlight Driver

SYNC_MASTER=J43_MLB

SYNC_DATE=09/13/2012

BKLT:ENG

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

R7717,R7718,R7719

103S0198

3

R7720,R7721,R7722

3

BKLT:ENG

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

103S0198

BKL_PWM

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

GND_BKL_SGND

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN3 BKL_ISEN4

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN5

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

LED_RETURN_5

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN2

PPVIN_S0SW_LCDBKLTFET

MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

MIN_LINE_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM

VOLTAGE=50V

PPVOUT_SW_LCDBKLT_FB

LED_RETURN_6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=50V SWITCH_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.150 MM

LCDBKLT_BOOST

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=40V

KBDLED_ANODE

MIN_LINE_WIDTH=0.3 MM

DIDT=TRUE

KBDLED_SW

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.225 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

KBDLED_FB

VOLTAGE=40V

BKL_EN

BKL_SDA

BKL_VSYNC_R

BKL_SCL

PP5V_S0

BKL_ISET

PPVIN_S0SW_LCDBKLT

PPHV_S0SW_LCDBKLT

SMC_SYS_KBDLED

PPVIN_S0SW_LCDBKLT

PP3V3_S0

PP5V_S0

EDP_BKLT_PWM

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PPVIN_S0SW_LCDBKLT_FET

PPBUS_G3H

BKL_FAULT

BKL_FSET

BKL_FLTR

LCDBKLT_EN_DIV_L

BKLT_PLT_RST_L

LCDBKLT_EN_L

EDP_BKLT_EN

LCDBKLT_DISABLE

<SCH_NUM>

77 OF 121

56 OF 76

64 64

16 17 32 45 51 52 56 58 59 61 62 64

41 56

60 62 64

41 56

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 59 61

62 64 65 74

16 17 32 45 51 52 56 58 59 61 62 64

41

27 41 42 49 50 62 64

w w w . c h i n a f i x . c o m

IN

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

NC NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

152S1870

1.8V S3 REGULATOR

Freq = 1 MHz

Max Current = 1.8A

Vout = 1.794V

<Rb>

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

1.5V S0 LDO

Max Current = 0.02A

<Ra>

Vout = 0.8V * (1 + Ra / Rb)

Vout = 1.5V

70mA is required to support pull-ups. Alternative is strong voltage

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

1.05V SUS LDO

Vout = 1.05V

Max Current = 0.35A

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.

2

1

C7821

22UF

CRITICAL

20%

6.3V X5R-CERM-1 603

2

1

C7822

CRITICAL

22UF

6.3V

20%

X5R-CERM-1

603

2

1

R7820

113K

1%

201

1/20W

MF

21

L7820

CRITICAL

2.2UH-20%-2.0A-0.108OHM

2520-SM

2

1

C7820

CRITICAL

22UF

20%

603

X5R-CERM-1

6.3V

59

2

1

R7821

90.9K

201

1/20W

MF

1%

2

1

C7872

10%

2.2UF

6.3V X5R 402

7

1

2

6

5

3

4

U7870

SON

TPS72015

CRITICAL

2

1

C7871

BYPASS=U7870.6:1mm

10%

1UF

CERM

6.3V

402

2

1

C7870

BYPASS=U7870.4:1mm

10%

6.3V CERM

1UF

402

20 21 22 23 57 62

28 59

1

6

9

4 5

3

8

7

2

U7820

CRITICAL

DFN

ISL8009B

43

21

R7829

1%

0.002

1W MF

OMIT

0612-SHORT

2

1

C7840

XDP

10%

1UF

402

CERM

6.3V

7

1

2

6

5

3

4

U7840

XDP

SON

CRITICAL

TPS720105

2

1

C7841

XDP

10%

X5R 402

2.2UF

6.3V

2

1

C7825

CRITICAL

22UF

6.3V

20%

X5R-CERM-1

603

2

1

C7823

5% 25V C0G 0201

47PF

2

1

C7824

1000PF

0201

X7R-1

16V

10%

SYNC_MASTER=J43_MLB

SYNC_DATE=10/04/2012

Misc Power Supplies

PP3V3_S5

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V

PP1V8_S3_REG_R

P1V8S3_SW

DIDT=TRUE

SWITCH_NODE=TRUE

PP1V05_SUS

PP3V3_SUS

PM_SLP_S3_BUF_L

P1V8S3_PGOOD

P1V8S3_EN

PP3V3_S5

PP1V8_S3

PP1V5_S0

PP1V8_S3

P1V8S3_FB

<SCH_NUM>

78 OF 121

57 OF 76

8

11 13 15 16

17 18 28 29 34

42 57 58 59

60 62 64 74

16 62

8

11 14 18 46 58 59 62 64

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

8

58 59 62 64

20 21 22 23 57 62

w w w . c h i n a f i x . c o m

IN

GND

VOUT

ON

VIN

NC NC

GND

VOUT

ON

VIN

IN

NCNC

GND

VOUT

ON

VIN

IN

NC NC

IN

GND

VOUT

ON

VIN

IN

GND

VOUT

ON

VIN

IN

GND

VDD

D

SON

CAP

NC NC

GND

VOUT

ON

VIN

S

D

N-CHANNEL

G

D

G

P-CHANNEL

G

D

S

IN

GND

VDD

D

SON

CAP

S

D

ON S

D

VDD

GND

IN

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

@ 2.5V

R(on)

1.5V S0 Audio Switch

5V S0 Switch

Loading specs per J41/43_PowerBudget_Riviera_rev0.99e

EDP: 35mA

R(on)

3.3V SUS Switch

Current

25.8 mOhm Max

18.5 mOhm Typ

TPS22924C

Type

Load Switch

18.5 mOhm Typ

U8040

TPS22924C

19.6 mOhm Typ

21.8 mOhm Max

2A Max

@ 2.5V

Current

@ 1.8V

R(on)

Part

Current

3.3V Sensor Switch

Sense R on sensor page

2A Max

25.8 mOhm Max

Type

Current

2A Max

Current

Type

R(on) @ 2.5V

EDP: 1A

2.5A

17 mOhm Max

15 mOhm Typ

25.8 mOhm Max

Load Switch

@ 2.5V

R(on)

Type

Part

Load Switch

Current

R(on)

Part

@ 2.5V

2A Max

EDP: 1.02A

U8010

TPS22924C

Current

EDP: 50mA

18.5 mOhm Typ

Part

Current

2A Max

EDP: 112mA

8.5 mOhm Max

Type

Load Switch

Type

Part

U8050

Part

R(on)

Load Switch

U8020

TPS22924C

U8030

Part

3.3V S0 Switch

Type

SLG5AP1438V

Load Switch

18.5 mOhm Typ

TPS22924C

Load Switch

3.3V S3 Switch

EDP: 300mA?

U8080

Part

U8005

Load Switch

Current

Type

R(on)

(HSIOFET_EN_L)

U8070

25.8 mOhm Max

3.3V SSD Switch

Type

18.5 mOhm Typ

25.8 mOhm Max

EDP: 5A

Sense R on sensor page

6A Max

@ 4V Vgs

9.8 mOhm Typ

EDP: 1.84A

1.05V PCH HSIO Switch

3.3V S4 Switch

R(on) @ 25C

5.3A Max

SLG5AP1453V

Part

7.8 mOhm Typ

2A Max

EDP: 1.84A

U8000

TPS22924C

SLG5AP1417V

TBD mOhm Max

EDP: 119mA

HSIO has turn-on requirement of

<65uS from EN to 95% (1.05V)

<0.1V/uS ramp rate and

58 59

2

1

C8030

20%

0201-1

1.0UF

6.3V X5R

B1

A1

B2

A2

C2

C1

U8030

CRITICAL

CSP

TPS22924

B1

A1

B2

A2

C2

C1

U8000

TPS22924

CSP

CRITICAL

18 28 59

2

1

C8000

0201-1

20%

1.0UF

6.3V X5R

B1

A1

B2

A2

C2

C1

U8020

CSP

TPS22924

CRITICAL

2

1

C8020

0201-1

20%

1.0UF

6.3V X5R

59

2

1

C8071

4700PF

10V X7R

10%

201

2

1

C8070

6.3V CERM-X5R 0201

0.1UF

10%

15 30 59 64

59

2

1

C8010

0201-1

20%

1.0UF

6.3V X5R

B1

A1

B2

A2

C2

C1

U8010

CSP

TPS22924

CRITICAL

43

21

R8011

0612-SHORT

0.002

OMIT

1W

1% MF

43

21

R8000

0612-SHORT

OMIT

1W

1%

0.002

MF

43

21

R8020

0612-SHORT

OMIT

1W

1%

0.002

MF

2

1

C8040

0201-1

20%

1.0UF

6.3V X5R

59

2

1

R8040

NOSTUFF

10K

MF

1/20W

201

5%

21

R8070

NOSTUFF

MF

1/20W

0201

0

5%

58 59

21

R8041

MF

1/20W

0201

0

5%

21

R8042

NOSTUFF

MF

1/20W

0201

0

5%

37 39 42

B1

A1

B2

A2

C2

C1

U8050

CSP

TPS22924

CRITICAL

2

1

C8050

0201-1

20%

1.0UF

6.3V X5R

21

R8050

MF-LF

402

1/16W

0

5%

2

1

C8080

16V X5R-CERM 0201

0.1UF

10%

59

1

52

8

37

U8080

CRITICAL

TDFN

SLG5AP1443V

43

21

R8081

0612-SHORT

OMIT

1W

1%

0.002

MF

2

1

C8081

4700PF

10V X7R

10%

201

B1

A1

B2

A2

C2

C1

U8040

TPS22924

CRITICAL

CSP

4

1

5

2

3

6

Q8061

NTUD3169CZ

SOT-963

NOSTUFF

2

1

R8061

330

NOSTUFF

MF

1/20W

201

5%

2

1

R8062

330

NOSTUFF

MF

1/20W

201

5%

2

1

C8060

0201

0.01UF

X5R-CERM

10V

NOSTUFF

10%

321

4

5

Q8060

IRFHM830DPBF

PQFN3.3X3.3

NOSTUFF

CRITICAL

2

1

R8060

300

402

1/16W MF-LF

NOSTUFF

5%

2

1

R8063

10K

NOSTUFF

MF

1/20W

201

5%

15 58

1

52

8

37

U8070

SLG5AP1453V

TDFN

CRITICAL

1

7

59

8

3

2

U8005

TDFN

SLG5AP1471V

CRITICAL

15 58

2

1

C8005

10V

1UF

402

X5R

10%

1

2

6

Q8062

DMN5L06VK-7

SOT563

NOSTUFF

4

5

3

Q8062

NOSTUFF

DMN5L06VK-7

SOT563

SYNC_MASTER=J41_MLB

Power FETs

SYNC_DATE=02/06/2013

SSD_PWR_EN

PP1V05_S0SW_PCH_HSIO

PP1V05_S0

PP1V05_S0SW_PCH_HSIO

P3V3S0SW_SSD_FET_RAMP

PCH_HSIO_PWR_EN

PP5V_S0

PP3V3_S5

HSIOFET_DRV_H

HSIOFET_DRV_L

PP1V05_S0

HSIOFET_EN

PP5V_S0

P1V5S0SW_AUDIO_EN

PP1V5_S0

S4_PWR_EN

SMC_SENSOR_PWR_EN

PP3V3_S4SW_SNS

P3V3SUS_EN

PP3V3_SUS

PP3V3_S5

P3V3S3_EN

PP3V3_S3

PP3V3_S5

P3V3S0_EN

PP3V3_S5

P5VS0_FET_RAMP

PP3V3_S4

PP1V5_S0SW_AUDIO

PP5V_S4RS3

PP1V5_S0SW_AUDIO_HDA

P5VS0_EN

PP3V3_S5

P3V3S0_EN

MIN_NECK_WIDTH=0.17 mm

PP1V5_S0SW_AUDIO

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=1.5V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.3 mm

PP1V5_S0SW_AUDIO_HDA

VOLTAGE=1.5V

PP5V_S0_FET_R

VOLTAGE=5V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

VOLTAGE=3.3V

PP3V3_S3_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_S0_FET_R

PP3V3_S4_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_SUS_FET_R

VOLTAGE=3.3V

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

PP3V3_S4SW_SNS_FET_R

MIN_NECK_WIDTH=0.20MM

PP3V3_S0SW_SSD_FET_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.50MM

PCH_HSIO_PWR_EN

HSIOFET_DISCHARGE

HSIOFET_EN_L

<SCH_NUM>

80 OF 121

58 OF 76

8

11 58 62

6 8

11 15 16 17 38 42 51 55

58 59 62 64

8

11 58 62

16 17 32 45 51 52 56 58 59 61 62 64

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

6 8

11 15 16 17 38 42 51 55

58 59 62 64

16 17 32 45 51 52 56 58 59 61 62 64

8

57 59

62 64

41 42 43 62

8

11 14 18 46 57 59 62 64

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

15 18 19 33 36 40 41 62 64

8

11

13 15

16

17 18

28

29 34

42

57 58

59

60 62

64

74

8

11 13

15 16 17

18 28 29

34 42 57

58 59 60

62 64 74

25 26 27 29 33 36 38 39 62 64

58 61 65

32 35 47 49 54 55 62 64

8

11 17 58

8

11 13 15

16 17 18 28

29 34 42 57

58 59 60 62

64 74

8

11 13 15

16 17 18 28

29 34 42 57

58 59 60 62

64 74

58 61 65

8

11 17 58

41

w w w . c h i n a f i x . c o m

OUT

IN

NC

Q3

Q2

Q4

Q1

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

IN

OUT

NC

IN

OUT

IN

SYM_VER_2

G S

D

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

1.5V Codec Enable

so 1.05V can fall after 1.5V

Vce(sat) 0.1V max @ 1mA

V4MON: 0.572V-0.630V

Vbe 0.7V max @ 2mA

(IPU)

V3MON: 0.572V-0.630V

Thresholds:

S5_PWRGD-->SMC

5V needs to be held up

U8130 Sense input

SSD Enable

VFRQ High: Variable Frequency

5V Divider:

1.5V Divider:

1.05V Divider:

3.19V @ 4.5Vmin

0.718V @ 1.45Vmin

0.723V @ 1.02Vmin

353S2310

S3 Enables

S5 Power Good

SMC-->PM_DSW_PWRGD

S5 Enables

Min delay time

No stuff C8131, 12ms

threhold is 3.07V

Standby Enables

VFRQ Low: Fix Frequency

SUS Enables

3.3V Divider: 1.07V

VDD: 2.734V-3.010V

5.0V Divider: 1.07V

V2MON: 2.815V-3.099V

Q1 Vth 0.7~1V @Id 250uA

CHGR VFRQ Generation

(ISL version used for development)

S0 Rail PGOOD Circuitry

9ms RC delay

3.3V SUS Detect

S0 Rail PGOOD (BJT Version)

376S0854

PM_SLP_S3_LPM_SLP_S4_LPM_SLP_S5_L

PM_SUS_EN

1

0

1

0

1

0

1

0

1

11

0

1

0

1

Mobile System Power State Table

SMC_S4_WAKESRC_EN

SMC_PM_G2_ENABLE

SMC_ADAPTER_EN

State

1

0

1

0

1

0

1

0

1

0

toggle 3Hz

1

X

Battery Off (G3HotAC)

Battery Off (G3Hot)

Sleep (S3AC)

Deep Sleep (S4)

Run (S0)

Deep Sleep (S5AC)

Deep Sleep (S4AC)

Sleep (S3)

Deep Sleep (S5)

S0 Enables

2

1

R8131

5%

201

1/20W

MF

330K

50

2

1

R8167

5%

201

1/20W MF

10K

16 17 37 59

2

1

R8157

5%

201

1/20W

MF

100

21

R8166

5%

201

1/20W

MF

100

21

R8164

5%

201

1/20W

MF

100

21

R8162

5%

201

1/20W

MF

S0PGOOD_ISL

330

55

2

1

R8156

201

1/20W

MF

1%

150K

2

1

C8160

S0PGOOD_ISL

6.3V

CERM-X5R

0201

0.1UF

10%

2

1

R8151

201

1/20W MF

54.9K

1%

2

1

R8152

201

1/20W MF

15K

1%

3

2

8

4

6

1

7

5

Q8150

DFN2015H4-8

CRITICAL

ASMCC0179

21

R8154

5%

201

1/20W

MF

1K

21

R8155

5%

201

1/20W

MF

1K

2

1

R8133

5%

201

1/20W MF

100K

2

1

C8130

BYPASS=U8130.6:2.3mm

6.3V

CERM-X5R

0201

0.1UF

10%

13 64

7

2

6

5

3

9

8

1

4

U8160

ISL88042IRTEZ

TDFN

CRITICAL

S0PGOOD_ISL

2

1

R8173

201

1/20W MF

15K

1%

S0PGOOD_ISL

2

1

R8171

201

1/20W MF

15K

1%

S0PGOOD_ISL

2

1

R8161

201

1/20W MF

1%

15K

S0PGOOD_ISL

2

1

R8170

201

1/20W MF

15K

1%

S0PGOOD_ISL

2

1

R8172

201

1/20W MF

6.04K

1%

S0PGOOD_ISL

2

1

R8160

201

1/20W MF

6.04K

1%

S0PGOOD_ISL

13 42 59

58 59

21

R8153

5%

201

1/20W

MF

1K

21

R8115

5%

0

0201

1/20W

MF

4

6

5 3

1

2

U8170

SOT891

74LVC1G32

NOSTUFF

13 37

2

1

C8170

BYPASS=U8170.6:2.3mm

NOSTUFF

6.3V

CERM-X5R

0201

0.1UF

10%

37 38

18 28 58 59

53

2

1

3

Q8131

DFN1006H4-3

DMN32D2LFB4

21

R8168

5%

201

1/20W

MF

100

37 54 59

2

1

R8141

5%

201

1/20W

MF

PLACE_NEAR=U7501.20:7mm

100K

37 38 54 59

21

R8140

5%

201

1/20W

MF

100

PLACE_NEAR=U7501.21:7mm

54 59

13 18 29 36 37 59

2

1

C8111

10V CERM

20%

PLACE_NEAR=U7400.16:6mm

0.1UF

402

2

1

C8112

CERM-X5R

0.47UF

PLACE_NEAR=U8010.D2:6mm

NO STUFF

6.3V

10%

402

2

1

R8111

5%

201

1/20W MF

20K

PLACE_NEAR=U7400.16:6mm

2

1

R8112

5%

0

0201

1/20W MF

PLACE_NEAR=U8010.D2:6mm

2

1

C8114

NO STUFF

0.47UF

PLACE_NEAR=U4600.4:6mm

CERM-X5R

6.3V

10%

402

2

1

R8114

5%

201

1/20W MF

100

PLACE_NEAR=U4600.4:6mm

USB_PWR:STBY

53 59

58 59

35 59 61 65

13 42 59

2

1

R8158

201

1/20W MF

15K

1%

2

1

R8159

201

1/20W MF

7.15K

1%

13 17 18 37

21

R8178

5%

201

1/20W

MF

100

28 57 59

5

4

1

2

3

U8180

SC70-HF

MC74VHC1G08

2

1

R8180

5%

201

1/20W MF

330K

NOSTUFF

2

1

C8185

PLACE_NEAR=U7600.16:6mm

NO STUFF

10V

0.22UF

CERM

10%

402

21

R8138

5%

201

1/20W

MF

820

NO STUFF

PLACE_NEAR=U7600.16:6mm

2

1

R8185

5%

0

0201

1/20W MF

PLACE_NEAR=U7600.16:6mm

2

1

C8186

CERM

10V

20%

PLACE_NEAR=U8030.2:6mm

0.1UF

402

2

1

R8186

5%

201

1/20W MF

20K

PLACE_NEAR=U8030.2:6mm

2

1

C8187

0.68UF

CERM

PLACE_NEAR=U8080.2:6mm

NO STUFF

6.3V

10%

402

2

1

R8187

5%

0

0201

1/20W MF

PLACE_NEAR=U8080.2:6mm

55 59

28 57 59

58 59

57 59

2

1

R8116

5%

0

0201

1/20W MF

PLACE_NEAR=U7820.2:6mm

2

1

C8116

NO STUFF

PLACE_NEAR=U7820.2:6mm

0.47UF

CERM-X5R

6.3V

10%

402

15 30 58 59 64 15 30 58 59 64

58

2

1

C8146

PLACE_NEAR=U8040.C2:7mm

X5R

0.1UF

10% 25V

402

21

R8146

5%

201

1/20W

MF

1K

21

R8145

5%

201

1/20W

MF

100K

PLACE_NEAR=U8040.2:C7mm

13 61 65

2

1

C8180

BYPASS=U8180.6:3mm

6.3V CERM-X5R 0201

0.1UF

10%

1

7

2 6

4

5

3

U8130

CRITICAL

TPS3808G33

QFN

21

R8176

5%

201

1/20W

MF

PLACE_NEAR=U7501.4:15mm

NO STUFF

240

2

1

R8175

5%

0

0201

1/20W MF

PLACE_NEAR=U7501.4:15mm

2

1

C8175

PLACE_NEAR=U7501.4:15mm

NO STUFF

2.2UF

6.3V X5R

10%

402

2

1

C8142

0.47UF

CERM-X5R

PLACE_NEAR=U7501.21:7mm

NOSTUFF

6.3V

10%

402

58 59

2

1

R8190

5%

0

0201

1/20W MF

2

1

C8190

NO STUFF

X5R

0.1UF

10% 25V

402

2

1

R8117

5%

201

1/20W MF

100

PLACE_NEAR=U4600.4:6mm

USB_PWR:S3

37 38 54 59

54

21

R8179

5%

0

0201

1/20W

MF

USB_PWR:S3

21

R8177

5%

0

0201

1/20W

MF

USB_PWR:STBY

21

R8165

5%

201

1/20W

MF

100

54

2

1

C8159

10V

1UF

X5R

10%

402

2

1

R8184

5%

201

1/20W MF

330

PLACE_NEAR=U8030.2:6mm

K A

D8184

RB521ES-30

0201

PLACE_NEAR=U8030.2:6mm

K A

D8146

PLACE_NEAR=U8040.2:C7mm

0201

RB521ES-30

K

A

D8185

RB521ES-30

PLACE_NEAR=U7600.16:6mm

NO STUFF

0201

K

A

D8175

PLACE_NEAR=U7501.4:15mm

RB521ES-30

NO STUFF

0201

2

1

C8131

1000PF

0201

X7R-1

16V

10%

NO STUFF

SYNC_MASTER=J43_MLB

SYNC_DATE=09/16/2012

Power Control

SUS_PGOOD_CT

MAKE_BASE=TRUE

PM_SLP_S3_BUF_L

P3V3S0_EN

MAKE_BASE=TRUE

USB_PWR_EN

MAKE_BASE=TRUE

P1V8S3_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

P3V3S3_EN

P3V3SUS_EN

MAKE_BASE=TRUE

SSD_PWR_EN

MAKE_BASE=TRUE

S5_PWRGD

S5_PWR_EN

MAKE_BASE=TRUE

SMC_PM_G2_EN

MAKE_BASE=TRUE

S4_PWR_EN

MAKE_BASE=TRUE

PM_SLP_SUS_L

P5VS0_EN

MAKE_BASE=TRUE

P1V05S0_EN

MAKE_BASE=TRUE

P5VS4RS3_EN_RC

P5VS4RS3_EN_D

P1V05_EN_D

P1V5CODEC_EN_D

AUD_PWR_EN

P3V3S0_EN_D

P1V05S0_EN

P3V3S0_EN

P5VS0_EN

PM_SLP_S3_BUF_L

PM_SLP_S3_L

PM_SLP_S3_R_L

PP3V3_S5

PM_SLP_S5_L

VMON_Q4_BASE

USB_PWR_EN

PP1V5_S0

PM_SLP_S3_BUF_L

ALL_SYS_PWRGD

VMON_Q2_BASE

S0PGD_BJT_GND_R

P1V8S3_PGOOD

PP3V3_S5

VMON_5V_DIV

VMON_3V3_DIV

VMON_Q3_BASE

PP3V3_S0

TP_SUS_PGOOD_MR_L

PP5V_S0

PP3V3_S5

PM_SLP_S3_R_L

PP3V3_SUS

PM_SLP_SUS_L

PM_RSMRST_L

S4_PWR_EN

SMC_PM_G2_EN

S5_PWR_EN

DDRREG_PGOOD

ALL_SYS_PWRGD

S0PGD_C

P1V05_DIV_VMON

P5V_DIV_VMON P1V5_DIV_VMON

PP5V_S0

CHGR_VFRQ

PP3V42_G3H

ALL_SYS_PWRGD_R

PP1V05_S0

PP1V5_S0

PP3V42_G3H

S5_PWRGD

PP3V3_SUS

S4_PWR_EN

PM_SLP_S4_L

P5VS4RS3_PGOOD

SMC_S4_WAKESRC_EN

P3V3SUS_EN

P5VS4RS3_EN

P3V3S3_EN

P1V8S3_EN

SSD_PWR_EN

PP3V3_S0

P1V05S0_PGOOD

PP3V3_S5

DDRREG_EN

PM_SLP_S4_L

P1V5S0SW_AUDIO_EN

59 OF 76

<SCH_NUM>

81 OF 121

28 57 59

58 59

35 59 61 65

57 59

53 59

58 59

54 59

58 59

55 59

59

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

8

57 58 59 62 64

28 57 59

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

8

11 12 13 15

17 18 26 30 36

38 39 40 41 42

43 44 45 56 59 61 62

64 65 74

16 17 32 45 51 52 56 58 59 61 62 64

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

59

8

11 14 18 46 57 58 59 62 64

18 28 58 59

16 17 37 59

16 17 32 45

51 52

56 58

59 61

62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

6 8

11 15 16 17 38 42 51 55

58 62 64

8

57 58 59 62 64

17 30 35 36 37 38 40 46

49 50 59 61

62 64 65

37 54 59

8

11 14 18 46 57 58 59 62 64

13 18 29 36 37 59

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8

11 13 15 16 17 18 28

29 34 42 57 58 59 60 62 64 74

w w w . c h i n a f i x . c o m

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

OUT

OUT OUT OUT OUT OUT OUT

IN

BI

IN

NC

NC NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

sensor page

Sense resistor on

(DP_INT_AUX_CH_C_P)

(DP_INT_AUX_CH_C_N)

Pull-ups on panel side,

DisplayPort I/F

LED Backlight I/F

LCD Connector

Internal DP Connector: 518S0829

4.7 kOhm to 3.3V

2

1

C8312

X5R

6.3V

10UF

603

20%

2

1

C8311

10%

0.1UF

0201

CERM-X5R

6.3V

2

1

C8309

10%

0.1UF

0201

CERM-X5R

6.3V

5

4

3

2

7

1

6

U8300

MFET-2X2-8IN

CRITICAL

FPF1009

2

1

C8317

5%

50V

C0G-CERM

603

1000PF

PLACE_NEAR=J8300.3:2mm

21

C8324

10%

0.1UF

0201

X5R-CERM

16V

21

C8325

10%

0.1UF

X5R-CERM

0201

16V

21

C8320

10%

0.1UF

X5R-CERM

0201

16V

21

C8321

10%

0.1UF

X5R-CERM

0201

16V

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J8300

CRITICAL

20525-130E-01

F-RT-SM

2

1

R8350

5%

201

1/20W

MF

100K

PLACE_NEAR=J8300.14:2mm

21

R8360

5%

0

0201

1/20W

MF

2

1

R8380

5%

201

1/20W MF

1M

2

1

R8370

5%

201

1/20W MF

1M

13

56 64

5

67

5

67

13

5

67

5

67

37 40 73

21

R8361

5%

0

0201

1/20W

MF

21

R8362

5%

0

0201

1/20W

MF

2

1

R8318

5%

201

1/20W

MF

1M

PLACE_NEAR=J8300.24:1mm

2

1

R8317

5%

201

1/20W

MF

1M

PLACE_NEAR=J8300.25:1mm

2

1

R8363

5%

201

1/20W MF

4.7K

2

1

R8364

5%

201

1/20W MF

4.7K

2

1

C8315

1000PF

0201

X7R-1

16V

10%

21

L8304

0402-LF

FERR-120-OHM-1.5A

Internal DisplayPort Connector

SYNC_MASTER=J43_MLB

SYNC_DATE=09/11/2012

PP3V3_S0SW_LCD_UF

MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

PP3V3_S0SW_LCD

PP3V3_S0SW_LCD_R

I2C_TCON_SCL_R

PPHV_S0SW_LCDBKLT

EDP_PANEL_PWR

PP3V3_S5

I2C_TCON_SDA_R

LED_RETURN_2 LED_RETURN_1

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

DP_INT_ML_C_N<0>

DP_INT_HPD_CONN

DP_INT_ML_C_P<0>

DP_INT_AUXCH_C_N

DP_INT_AUXCH_C_P

SMBUS_SMC_0_S0_SDA

DP_INT_ML_N<0>

DP_INT_ML_P<0>

DP_INT_AUX_CH_C_P

DP_INT_AUX_CH_C_N

DP_INT_HPD

SMBUS_SMC_0_S0_SCL

<SCH_NUM>

83 OF 121

60 OF 76

64

43 43

64

56 62 64

8

11 13 15 16 17 18 28 29 34

42 57 58 59 62 64 74

64

64 67

w w w . c h i n a f i x . c o m

IN

BI

IN

OUT

IN IN OUT

BI

OUT

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ON MLB SIDE AS LIO CAN’T FIT CAPS

516S1036

(Right Speaker Enable)

2

1

C9510

PLACE_NEAR=J9500.21:1.5mm

16V

0201

X5R-CERM

10%

0.1UF

36 37 38 64 65

12 65 69

2

1

C9520

PLACE_NEAR=J9500.7:1.5mm

0.1UF

10% 16V

0201

X5R-CERM

14 65 68

47 65 74

37 38 50 65

35 59 65

39 65

37 65

37 40 65 73

14 16 65

12 65 69

47 65

12 65 69

21

C9522

GND_VOID=TRUE

X5R-CERM 10% 16V

0201

0.1UF

21

C9521

GND_VOID=TRUE

X5R-CERM

0.1UF

16V

10%

0201

14 65 68

21

R9510

5%00201

1/20W

MF

GND_VOID=TRUE

21

C9532

5%

GND_VOID=TRUE

NP0-CERM

0201

15PF

25V

NOSTUFF

21

R9520

5%00201

1/20W

MF

GND_VOID=TRUE

21

C9531

5%

25V

NP0-CERM

0201

GND_VOID=TRUE

15PF

NOSTUFF

9

87

6

5251

50

5

49

4847

4645

4443

4241

40

4

39

3837

3635

3231

30

3

29

2827

2625

2423

2221

20

2

19

1615

1413

1211

10

1

J9500

GND_VOID=TRUE

F-ST-SM

CRITICAL

GND_VOID=TRUE

DF40CG3.0-48DS-0.4V

13 59 65

2 1

R9501

5%

0

0201

1/20W

MF

NOSTUFF

2

1

C9550

10PF

5%

50V

CERM

NOSTUFF

0402

2

1

D9510

ESD112-B1-02ELS

0201-THICKSTNCL

GND_VOID=TRUE

CRITICAL

2

1

D9511

0201-THICKSTNCL

ESD112-B1-02ELS

CRITICAL

GND_VOID=TRUE

2

1

D9520

GND_VOID=TRUE

CRITICAL

0201-THICKSTNCL

ESD112-B1-02ELS

2

1

D9521

GND_VOID=TRUE

CRITICAL

ESD112-B1-02ELS

0201-THICKSTNCL

2

1

C9500

PLACE_NEAR=J9500.9:1.5mm

16V X5R-CERM

0.1UF

10%

0201

SYNC_DATE=11/13/2012

SYNC_MASTER=CLEAN_J43

Left I/O (LIO) Connector

IO Ports

USB3_EXTB_D2R_RC_P

USB3_EXTB_D2R_RC_N

SMBUS_SMC_2_S3_SDA SMBUS_SMC_2_S3_SCL

PP3V42_G3H

PP3V3_S0

SPKRAMP_INR_N SPKRAMP_INR_P

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.1 mm

PP5V_S0_ALT_AUD_LDO_EN

VOLTAGE=5V

HDA_SDOUT

SMC_LID

HDA_SYNC

HDA_SDIN0

SPKRAMP_SHDN_L

PP1V5_S0SW_AUDIO

HDA_RST_L

XDP_USB_EXTB_OC_L

SYS_ONEWIRE

SMC_BC_ACOK USB_PWR_EN

FINSTACKSNS_ALERT_L

USB_EXTB_P

PP5V_S0

USB_EXTB_N

USB3_EXTB_D2R_P

USB3_EXTB_R2D_C_P

USB3_EXTB_R2D_C_N

AUD_PWR_EN

USB3_EXTB_D2R_N

HDA_BIT_CLK

USB3_EXTB_R2D_N

USB3_EXTB_R2D_P

<SCH_NUM>

95 OF 121

61 OF 76

65 68

17 30 35 36 37 38 40 46 49 50 59 62 64 65

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

62 64 65 74

65

58 65

16 17 32 45 51 52 56 58 59 62 64

65 68

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

? mA

5V Rails

3.3V Rails

2A max supply

"G3Hot" (Always-Present) Rails

TBT Rails (off when no cable)

1.8V/1.5V/1.2V/1.05V Rails

CPU "VCORE" RAILS

Digital Ground

1.84A

LCDBKLT Rail

SYNC_DATE=12/17/2012

Power Aliases

SYNC_MASTER=WILL_J43

PP5V_S0

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_TBTCIO

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.175 MM

PP1V05_S0

PP1V05_S0 PP1V05_S0

PP1V05_S0

PP0V6_S0_DDRVTT

MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V

MIN_LINE_WIDTH=0.6 mm

PP0V6_S0_DDRVTT

MAKE_BASE=TRUE

PP1V2_S3

PP3V3_S0

MAKE_BASE=TRUE

PP3V3_S4SW_SNS

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_SUS

PP3V3_S3

PPDCIN_G3H_ISOL

PP3V42_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H_ISOL

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H_ISOL

PP3V3_S0

PP3V42_G3H

PP3V3_S3

PP3V3_SUS

PP3V3_S5

PP3V3_S3

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S4

PPDCIN_G3H

PP1V8_S3

PP15V_TBT

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=17.8V MAKE_BASE=TRUE

PP15V_TBT

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S4SW_SNS

PP3V3_S4

PP3V3_S5

PP1V05_S0

PP5V_S0

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0SW_PCH_HSIO

MIN_LINE_WIDTH=0.6 MM

PP3V3_S4SW_SNS

PP1V5_S0

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PPVRTC_G3H

PP3V42_G3H

PP3V3_S4SW_SNS

PP5V_S4RS3

PP5V_S0

PP3V3_S4SW_SNS

PP5V_S0

PPVRTC_G3H

PP5V_S4RS3

PP1V05_S0SW_PCH_HSIO

PPDCIN_G3H_ISOL

PP3V3_S0SW_SSD

PPHV_S0SW_LCDBKLT

PP1V8_S3

PP3V3_TBTLC

PP1V2_S3

PP1V5_S0

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_TBTLC

PP15V_TBT

PP1V2_S3

MIN_NECK_WIDTH=0.25 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

PPVCC_S0_CPU

MAKE_BASE=TRUE

PPHV_S0SW_LCDBKLT

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=50V

MIN_NECK_WIDTH=0.375 MM

PPHV_S0SW_LCDBKLT

PP1V2_S3

PP3V3_S0SW_SSD

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

MAKE_BASE=TRUE

PPDCIN_G3H

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 MM

PP3V42_G3H

PPBUS_S5_HS_COMPUTING_ISNS

PPDCIN_G3H

PP3V42_G3H

PPBUS_G3H

PP1V8_S3

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

PP1V05_S0SW_PCH_HSIO

VOLTAGE=8.6V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

PPBUS_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

PP1V05_S0

PPBUS_S5_HS_OTHER_ISNS

PP1V05_S0

PP3V3_S4SW_SNS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.6V

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

PP1V2_S3

PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=8.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PPBUS_S5_HS_OTHER_ISNS

PP1V05_S0

PP3V42_G3H

PP5V_S5

PP5V_S0

MIN_LINE_WIDTH=0.6MM

PP1V8_S3

MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V MAKE_BASE=TRUE

PPBUS_S5_HS_COMPUTING_ISNS

PP3V3_SUS PP3V3_SUS

PP3V3_SUS

PP3V3_S3

PP3V3_SUS

MIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP1V2_S3

VOLTAGE=1.2V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5

PP3V3_S4_TBTAPWR

PP5V_S4RS3 PP5V_S4RS3

PP5V_S4RS3

PP5V_S0

PP5V_S5

PP1V5_S0

PP0V6_S0_DDRVTT

PP1V05_SUS

PP0V6_S0_DDRVTT

PP1V05_SUS

PP1V5_S0

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S0

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.3 mm

PP1V2_S3

MIN_NECK_WIDTH=0.2 MM

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V MAKE_BASE=TRUE

PPBUS_S5_HS_OTHER_ISNS

PPBUS_S5_HS_COMPUTING_ISNS

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM

PP3V42_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 MM

PPVRTC_G3H

PP3V42_G3H

PP5V_S5

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

PP5V_S4RS3

MIN_NECK_WIDTH=0.175 MM

PP5V_S4RS3

PP3V3_S4SW_SNS

PP1V05_S0SW_PCH_HSIO

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5

PP3V3_S5

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

PP3V3_S5

MAKE_BASE=TRUE

VOLTAGE=12.8V

PPVIN_SW_TBTBST

PP3V3_S0

MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

PP3V3_S4

MIN_LINE_WIDTH=0.60MM VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

PP3V3_S4_TBTAPWR

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.075MM

<SCH_NUM>

100 OF 121

62 OF 76

16 17 32 45 51 52 56 58 59 61 62 64

26 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

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59 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64 6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

24 53 62

17 19 20 21 22 23 42 53 62 70

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44

45 56 59 61 62 64 65 74

41 42 43 58 62

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62

64 65 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8

11 14 18 46 57 58 59 62 64

15 18 19 33 36 40 41 58 62 64

42 49 50 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

42 49 50 62 64

8

11 12 13 15 17 18 26 30 36 38

39 40

41 42 43 44 45 56 59 61 62 64

65

74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56

59 61 62 64 65 74

8 11

12 13 15 17 18 26 30 36 38 39

40

41 42 43 44 45 56 59 61 62 64

65 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56

59 61 62 64 65 74

8 11

12

13

15 17 18 26 30 36 38 39 40 41

42 43 44

45 56 59 61 62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44

45 56 59 61 62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40

41 42 43 44 45 56 59 61 62 64

65

74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56

59 61 62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44

45 56 59 61 62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40

41 42 43 44 45 56 59 61 62 64

65

74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56

59 61 62 64 65 74

8 11

12 13 15 17 18 26 30 36 38

39

40 41 42 43 44 45 56 59 61 62

64 65 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56

59 61 62 64 65 74

8 11

12

13

15 17 18 26 30 36 38 39 40 41

42 43 44

45 56 59 61 62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44

45 56 59 61 62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40

41 42 43 44 45 56 59 61 62 64

65

74

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

15 18 19 33 36 40 41 58 62 64

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

15 18 19 33 36 40 41 58 62 64

25 26 27 29 33 36 38 39 58 62 64

49 50 62 64

20 21 22 23 57 62

27 28 62 64

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

41 42 43 58 62

25 26 27 29 33 36 38 39 58 62 64

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

16 17 32 45 51 52 56 58 59 61 62 64

8

11 58 62

41 42 43 58 62

8

57 58 59 62 64

8

12 13 17 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

41 42 43 58 62

32 35 47 49 54 55 58 62 64

16 17 32 45 51 52 56 58 59 61 62 64

41 42 43 58 62

16 17 32 45 51 52 56 58 59 61 62 64

8

12 13

17 62 64

32 35 47 49 54 55 58 62 64

8

11 58 62

42 49 50 62 64

30 41 62 64

56 60 62 64

20 21 22 23 57 62

17 18 25 26 62 64

17 19 20 21 22 23 42 53 62 70

8

57 58 59 62 64

17 18 25 26 62 64

27 28 62 64

17 19 20 21 22 23 42 53 62 70

8

10 42 52

62 64

8

10 42 52

62 64

8

10 42 52 62 64

8

10 42 52

62 64

56 60 62 64 56 60 62 64

17 19 20 21 22 23 42 53 62 70

30 41 62 64

49 50 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

41 51 52 53 55 62 64

49 50 62 64

17 30 35 36 37 38 40 46 49 50

59 61 62 64 65

27 41 42 49 50 56

62 64

27 41 42 49 50 56 62 64

20 21 22 23 57 62

27 41 42 49 50 56 62 64

8

11 58 62

41 51 52 53 55 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

41 54 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

41 42 43 58 62

27 41 42 49 50 56 62 64

17 19 20 21 22 23 42 53 62 70

27 41 42 49 50 56 62 64

41 54 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

36 53 54 62

16 17 32 45 51 52 56 58 59 61 62 64

20 21 22 23 57 62

41 51 52 53 55 62 64

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

15 18 19 33 36 40 41 58 62 64

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

17 19 20 21 22 23 42 53 62 70

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

28 62

32 35 47 49 54 55 58 62 64

16 17 32 45 51 52 56 58 59 61 62 64

36 53 54 62

24 53 62

16 57 62

8

57 58 59 62 64

8

57 58 59 62 64

17 19 20 21 22 23 42 53 62 70

16 57 62

41 54 62 64

41 51 52 53 55 62

64

17 30 35 36 37 38

40 46 49

50 59 61

62 64 65

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

8

12 13 17 62 64

17 30 35 36 37 38 40 46 49 50

59 61 62 64 65

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

36 53 54 62

32 35 47 49 54 55 58 62 64

41 42 43 58 62

8

11 58 62

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28

29 34 42 57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74 8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62

64 65 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56

59 61 62 64 65 74

8 11

12 13 15 17 18 26 30 36 38 39

40

41 42 43 44 45 56 59 61 62 64

65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

25 26 27 29 33 36 38 39 58 62 64

28 62

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LPDDR3 Command/Address

MAKE_BASE MAKE_BASE

Memory Bit/Byte Swizzle

MAKE_BASE

Signal Aliases

SYNC_MASTER=J41_MLB

SYNC_DATE=08/30/2012

=MEM_B_DQ<28>

TRUE

MEM_B_DQ<41>

TRUE

MEM_B_DQ<43>

TRUE

MEM_B_DQ<45>

TRUE

MEM_B_DQ<40>

=MEM_B_DQ<36>

=MEM_B_DQ<35>

=MEM_B_DQ<38> =MEM_B_DQ<39> MEM_B_DQ<32>

=MEM_B_DQ<37>

TRUE

MEM_A_DQ<29>

=MEM_B_DQ<6>

=MEM_B_DQ<12>

TRUE

MEM_B_DQ<21>

TRUE

MEM_B_DQ<19>

=MEM_B_DQ<33>

TRUE

MEM_A_DQ<46>

TRUE

MEM_A_DQ<47>

=MEM_A_DQ<43>

=MEM_A_DQ<31>

TRUE

MEM_A_CAA<2>

TRUE

MEM_A_CAA<5>

=MEM_A_DQ<25>

MEM_A_DQ<33>

TRUE

MEM_A_DQ<35>

MEM_A_DQ<44>

TRUE

=MEM_A_DQ<2>

=MEM_A_DQ<6>

=MEM_A_DQ<8> =MEM_A_DQ<9>

TRUE

MEM_A_DQ<7>

TRUE

MEM_A_DQ<26>

=MEM_A_DQS_N<7>

TRUE

MEM_A_DQS_N<7>

=MEM_A_DQS_P<7>

TRUE

MEM_A_DQS_P<7>

=MEM_A_DQS_N<5>

TRUE

MEM_A_DQS_N<4>

MEM_A_DQS_P<6>

TRUE

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

TRUE

MEM_A_DQS_N<6>

=MEM_A_DQS_P<5>

TRUE

MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>

TRUE

MEM_A_DQS_N<5>

=MEM_A_DQS_P<2>

TRUE

MEM_A_DQS_P<3>

=MEM_A_DQS_N<2>

TRUE

MEM_A_DQS_N<3>

=MEM_A_DQS_P<4>

TRUE

MEM_A_DQS_P<5>

=MEM_A_DQS_P<3>

TRUE

MEM_A_DQS_P<2>

=MEM_A_DQS_N<3>

TRUE

MEM_A_DQS_N<2>

=MEM_A_DQS_P<0>

TRUE

MEM_A_DQS_P<1>

=MEM_A_DQS_N<0>

TRUE

MEM_A_DQS_N<1>

=MEM_A_DQS_N<1>

TRUE

MEM_A_DQS_N<0>

=MEM_A_DQS_P<1>

TRUE

MEM_A_DQS_P<0>

=MEM_A_DQ<63>

TRUE

MEM_A_DQ<56>

=MEM_A_DQ<59>

TRUE

MEM_A_DQ<61>

=MEM_A_DQ<62>

TRUE

MEM_A_DQ<57>

=MEM_A_DQ<58>

TRUE

MEM_A_DQ<60>

=MEM_A_DQ<61>

TRUE

MEM_A_DQ<63>

=MEM_A_DQ<60>

TRUE

MEM_A_DQ<59>

=MEM_A_DQ<56>

TRUE

MEM_A_DQ<58>

=MEM_A_DQ<55>

TRUE

MEM_A_DQ<55>

=MEM_A_DQ<57>

TRUE

MEM_A_DQ<62>

=MEM_A_DQ<54>

TRUE

MEM_A_DQ<54>

=MEM_A_DQ<53>

TRUE

MEM_A_DQ<50>

MEM_B_DQS_N<6>

TRUE

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

TRUE

MEM_B_DQS_P<6>

=MEM_B_DQS_N<5>

TRUE

MEM_B_DQS_N<4>

=MEM_B_DQS_P<6>

TRUE

MEM_B_DQS_P<7>

=MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

TRUE

=MEM_B_DQS_P<5>

TRUE

MEM_B_DQS_P<4>

=MEM_B_DQS_N<4>

TRUE

MEM_B_DQS_N<5>

=MEM_B_DQS_P<4>

TRUE

MEM_B_DQS_P<5>

=MEM_B_DQS_N<3>

TRUE

MEM_B_DQS_N<2>

=MEM_B_DQS_P<3>

TRUE

MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

TRUE

MEM_B_DQS_N<3>

=MEM_B_DQS_P<2>

TRUE

MEM_B_DQS_P<3>

=MEM_B_DQS_N<0>

TRUE

MEM_B_DQS_N<1>

=MEM_B_DQS_P<1>

TRUE

MEM_B_DQS_P<0>

=MEM_B_DQS_N<1>

TRUE

MEM_B_DQS_N<0>

=MEM_B_DQS_P<0>

TRUE

MEM_B_DQS_P<1>

=MEM_B_DQ<63>

TRUE

MEM_B_DQ<54>

=MEM_B_DQ<60>

TRUE

MEM_B_DQ<52>

=MEM_B_DQ<62>

TRUE

MEM_B_DQ<50>

=MEM_B_DQ<59>

TRUE

MEM_B_DQ<53>

=MEM_B_DQ<58>

TRUE

MEM_B_DQ<48>

=MEM_B_DQ<61>

TRUE

MEM_B_DQ<55>

=MEM_B_DQ<54>

TRUE

MEM_B_DQ<58>

=MEM_B_DQ<56>

TRUE

MEM_B_DQ<49>

=MEM_B_DQ<57>

TRUE

MEM_B_DQ<51>

=MEM_B_DQ<55>

TRUE

MEM_B_DQ<61>

=MEM_B_DQ<53>

TRUE

MEM_B_DQ<62>

=MEM_A_DQ<49>

TRUE

MEM_A_DQ<51>

=MEM_A_DQ<52>

TRUE

MEM_A_DQ<53>

=MEM_A_DQ<48>

TRUE

MEM_A_DQ<52>

=MEM_A_DQ<50>

TRUE

MEM_A_DQ<48>

=MEM_A_DQ<51>

TRUE

MEM_A_DQ<49>

=MEM_A_DQ<44>

TRUE

MEM_A_DQ<32>

TRUE

MEM_A_DQ<39>

=MEM_A_DQ<47>

TRUE

MEM_A_DQ<38>

=MEM_A_DQ<46>

TRUE

MEM_A_DQ<33>

=MEM_A_DQ<41>

TRUE

MEM_A_DQ<37>

=MEM_A_DQ<42>

TRUE

MEM_A_DQ<34>

=MEM_A_DQ<39>

TRUE

MEM_A_DQ<43>

=MEM_A_DQ<38>

TRUE

MEM_A_DQ<42>

=MEM_A_DQ<40>

TRUE

MEM_A_DQ<36>

=MEM_A_DQ<37>

MEM_A_DQ<45>

TRUE

=MEM_A_DQ<35> =MEM_A_DQ<36>

TRUE

MEM_A_DQ<40>

=MEM_A_DQ<34>

=MEM_A_DQ<33>

=MEM_A_DQ<32>

TRUE

MEM_A_DQ<41>

=MEM_A_DQ<27>

TRUE

MEM_A_DQ<23>

TRUE

MEM_A_DQ<17>

=MEM_A_DQ<28>

TRUE

MEM_A_DQ<20>

=MEM_A_DQ<30>

TRUE

MEM_A_DQ<22>

MEM_A_DQ<19>

TRUE

MEM_A_DQ<21>

=MEM_A_DQ<26>

TRUE

MEM_A_DQ<16>

=MEM_A_DQ<24>

MEM_A_DQ<18>

TRUE

=MEM_A_DQ<23>

TRUE

MEM_A_DQ<30>

=MEM_A_DQ<22>

=MEM_A_DQ<17>

TRUE

MEM_A_DQ<28>

=MEM_A_DQ<21>

TRUE

MEM_A_DQ<25>

=MEM_A_DQ<18>

MEM_A_DQ<27>

TRUE

=MEM_A_DQ<20>

TRUE

MEM_A_DQ<24>

=MEM_A_DQ<19>

TRUE

MEM_A_DQ<31>

=MEM_A_DQ<14>

MEM_A_DQ<3>

TRUE

=MEM_A_DQ<15>

MEM_A_DQ<6>

TRUE

=MEM_A_DQ<16>

=MEM_A_DQ<13>

MEM_A_DQ<5>

TRUE

=MEM_A_DQ<12>

TRUE

MEM_A_DQ<4>

=MEM_B_DQ<52>

TRUE

MEM_B_DQ<63>

=MEM_B_DQ<51>

TRUE

MEM_B_DQ<59>

=MEM_B_DQ<49>

TRUE

MEM_B_DQ<56>

=MEM_B_DQ<50>

TRUE

MEM_B_DQ<60>

=MEM_B_DQ<48>

TRUE

MEM_B_DQ<57>

=MEM_B_DQ<44>

TRUE

MEM_B_DQ<36>

=MEM_B_DQ<46>

TRUE

MEM_B_DQ<38>

=MEM_B_DQ<47>

TRUE

MEM_B_DQ<35>

=MEM_B_DQ<45>

TRUE

MEM_B_DQ<37>

=MEM_B_DQ<43>

TRUE

MEM_B_DQ<39>

TRUE

MEM_B_DQ<46>

=MEM_B_DQ<41>

TRUE

MEM_B_DQ<33>

=MEM_B_DQ<42>

TRUE

MEM_B_DQ<34>

TRUE

MEM_B_DQ<47>

=MEM_B_DQ<34>

TRUE

MEM_B_DQ<42>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

TRUE

MEM_B_DQ<18>

=MEM_B_DQ<27>

TRUE

MEM_B_DQ<22>

=MEM_B_DQ<29>

TRUE

MEM_B_DQ<17>

=MEM_B_DQ<23>

TRUE

MEM_B_DQ<26>

=MEM_B_DQ<22>

TRUE

MEM_B_DQ<31>

=MEM_B_DQ<26>

TRUE

MEM_B_DQ<23>

=MEM_B_DQ<24>

TRUE

MEM_B_DQ<20>

=MEM_B_DQ<25>

TRUE

MEM_B_DQ<16>

=MEM_B_DQ<20>

TRUE

MEM_B_DQ<24>

=MEM_B_DQ<21>

TRUE

MEM_B_DQ<25>

=MEM_B_DQ<19>

TRUE

MEM_B_DQ<27>

=MEM_B_DQ<18>

TRUE

MEM_B_DQ<30>

=MEM_B_DQ<17>

TRUE

MEM_B_DQ<29>

=MEM_B_DQ<14>

TRUE

MEM_B_DQ<6>

=MEM_B_DQ<15>

TRUE

MEM_B_DQ<3>

=MEM_B_DQ<16>

TRUE

MEM_B_DQ<28>

=MEM_B_DQ<13>

TRUE

MEM_B_DQ<5>

TRUE

MEM_B_DQ<4>

TRUE

MEM_A_DQ<0>

=MEM_A_DQ<11>

=MEM_A_DQ<7>

TRUE

MEM_A_DQ<15>

=MEM_A_DQ<10>

TRUE

MEM_A_DQ<2>

TRUE

MEM_A_DQ<1>

=MEM_A_DQ<3>

TRUE

MEM_A_DQ<11>

TRUE

MEM_A_DQ<10>

TRUE

MEM_A_DQ<14>

=MEM_A_DQ<4>

TRUE

MEM_A_DQ<8>

=MEM_A_DQ<5> MEM_A_DQ<13>

TRUE

=MEM_A_DQ<0>

TRUE

MEM_A_DQ<9>

=MEM_A_DQ<1>

TRUE

MEM_A_DQ<12>

=MEM_B_DQ<11>

MEM_B_DQ<7>

TRUE

=MEM_B_DQ<10>

TRUE

MEM_B_DQ<2>

=MEM_B_DQ<9>

TRUE

MEM_B_DQ<1>

=MEM_B_DQ<8>

TRUE

MEM_B_DQ<0>

=MEM_B_DQ<7>

TRUE

MEM_B_DQ<15>

=MEM_B_DQ<2>

TRUE

MEM_B_DQ<10>

=MEM_B_DQ<5>

TRUE

MEM_B_DQ<8>

TRUE

MEM_B_DQ<14>

=MEM_B_DQ<3>

TRUE

MEM_B_DQ<11>

=MEM_B_DQ<4>

TRUE

MEM_B_DQ<13>

=MEM_B_DQ<1>

TRUE

MEM_B_DQ<9>

=MEM_B_DQ<0>

TRUE

MEM_B_DQ<12>

MEM_B_ODT<0>

MEM_A_CAB<6>

MEM_B_CAA<6>

=MEM_A_WE_L

=MEM_A_A<14>

=MEM_A_BA<2>

=MEM_A_A<10>

MEM_A_CAA<6>

=MEM_A_A<7>

=MEM_A_A<8>

=MEM_A_A<5>

=MEM_A_A<6>

=MEM_A_A<9>

=MEM_A_BA<0>

=MEM_A_RAS_L

=MEM_A_CAS_L

=MEM_A_A<13>

=MEM_A_A<11>

=MEM_A_A<0>

=MEM_A_A<1>

=MEM_A_A<15>

TP_LPDDR3_RSVD2

=MEM_B_A<0>

=MEM_B_A<1>

=MEM_B_A<10>

MEM_B_CAB<6>

=MEM_B_A<2>

=MEM_B_BA<0>

=MEM_B_RAS_L

=MEM_B_WE_L

=MEM_B_CAS_L

=MEM_B_A<13>

=MEM_B_A<14>

=MEM_B_A<7> =MEM_B_BA<2>

=MEM_B_A<8>

=MEM_B_A<6>

=MEM_B_A<9>

=MEM_B_A<5>

MEM_A_ODT<0>

TP_LPDDR3_RSVD4

TP_LPDDR3_RSVD3

MEM_B_CAB<5>

TRUE

MEM_B_CAB<7>

MEM_A_CAB<6>

TRUE

MEM_A_CAA<6>

TRUE

MEM_A_CAA<4>

MEM_A_CAA<3>

TRUE

MEM_A_CAA<0>

TRUE

MEM_A_CAA<1>

MEM_A_CAB<4>

TRUE

MEM_A_CAB<0>

TRUE

MEM_A_CAA<8>

TRUE

MEM_A_CAA<9>

TRUE

MEM_A_CAA<7>

MEM_A_CAB<7>

TRUE

MEM_A_CAB<9>

TRUE

MEM_A_CAB<8>

TRUE

MEM_A_CAB<3>

TRUE

MEM_A_CAB<1>

TRUE

TP_LPDDR3_RSVD2

TRUE

MEM_B_CAB<9>

TRUE

MEM_B_CAB<8>

TRUE

MEM_B_CAB<6>

TRUE

MEM_B_CAB<3>

TRUE

MEM_B_CAB<2>

TRUE

MEM_B_CAB<1>

TRUE

MEM_B_CAB<0>

TRUE

MEM_B_CAA<9>

TRUE

MEM_B_CAA<8>

TRUE

MEM_B_CAA<7>

TRUE

MEM_B_CAA<6>

TRUE

MEM_B_CAA<4>

TRUE

MEM_B_CAA<5>

MEM_B_CAA<3>

TRUE

MEM_B_CAA<2>

TRUE

MEM_B_CAA<1>

TRUE

MEM_B_CAA<0>

MEM_B_ODT<0>

TRUE

TP_LPDDR3_RSVD4

TRUE

TP_LPDDR3_RSVD3

TRUE

TP_LPDDR3_RSVD1

MEM_A_ODT<0>

TRUE

MEM_A_CAB<5>

TRUE

MEM_A_CAB<2>

TRUE

=MEM_A_A<2>

=MEM_B_A<11> =MEM_B_A<15>

TRUE

MEM_B_CAB<4>

TP_LPDDR3_RSVD1

=MEM_A_DQ<29>

=MEM_B_DQ<32>

TRUE

MEM_B_DQ<44>

TRUE

MEM_B_DQ<32>

<SCH_NUM>

102 OF 121

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w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(Nets with offpages not used on this project)

Unused nets with offpage

(Need 4 TPs)

(Need to add 5 GND TPs)

J7000: DC-In Connector

(Need to add 5 GND TPs)

J6404: Speaker Connector

(Need 2 TPs)

FUNC_TEST

J7050 and 1 for shield)

(Need to add 6 GND TPs)

(Need to add 2 GND TPs)

(Only a subset are needed

for FCT HVM test fixture)

J1800: XDP Connector

FUNC_TEST

J7715: KB BKLT Connector

(Need to add 2 GND TPs)

FUNC_TEST

TBT

(Need to add 27 GND TPs)

FUNC_TEST

(Need TBD TPs)

(Need 6 TPs)

(Need 2 TPs)

(Need to add TBD GND TPs)

J4002: Camera Connector

FUNC_TEST

J3700: SSD Connector

FUNC_TEST

(Need to add 6 GND TPs)

FUNC_TEST

J6100: LPC+SPI Connector

SMC

NO_TEST Nets

MAKE_BASE

NO_TEST

CPU/PCH

J6950: Battery Connector

(Need to add 5 GND TPs)

J8300: Internal DP Connector

(Need to add 4 GND TPs near

(Need to add 3 GND TPs)

FUNC_TEST

J6000: Fan Connector

Functional Test Points

FUNC_TEST FUNC_TEST

Misc Voltages & Control Signals

(Need 3 TPs)

(Need 4 TPs)

(Need 5 TPs)

(Need to add 1 GND TP)

FUNC_TEST

J4800: IPD Flex Connector

J3501: AirPort / BT Connector

(Need to add 8 GND TPs)

I776

I777

I778

I779

I780

I781

I782

I783

I784

I785

I786

I787

I788

I789

I790

I791

I792

I793

SYNC_DATE=12/17/2012SYNC_MASTER=WILL_J43

Func Test / No Test

PP1V05_TBTCIO

TRUE

PPDCIN_G3H

TRUE

USB_BT_CONN_P

TRUE

USB_BT_CONN_N

TRUE

PP3V3_S4

TRUE

PCIE_AP_R2D_N

TRUE

USB_TPAD_N

TRUE

TPAD_SPI_CS_R_L

TRUE

PP3V3_S4_IPD

TRUE

TPAD_SPI_MOSI_R

TRUE

TPAD_WAKE_L

TRUE

TPAD_SPI_CLK_R

TRUE

USB_TPAD_P

TRUE

TPAD_SPI_MISO_R

TRUE

SMC_LID

TPAD_SPI_IF_EN_CONN

TRUE

PCIE_WAKE_L

TRUE

AP_CLKREQ_Q_L

TRUE

SMC_LSOC_RST_L

TRUE

PP5V_S0

PCIE_SSD_R2D_P<3..0>

TRUE

PP3V3_S0

TRUE

SMC_OOB1_R2D_CONN_L

PPVBAT_G3H_CONN

TRUE

LCD_IRQ_L

LCD_PSR_EN

AP_PCIE_DEV_WAKE

TRUE

PPVIN_SW_TBTBST

NC_DP_TBTPB_AUXCH_CN

TRUETRUE

NC_DP_TBTPB_AUXCH_CN

NC_DP_TBTPB_ML_CN<3..1:2> NC_DP_TBTPB_ML_CN<3..1:2>

TRUETRUE

NC_DP_TBTPB_AUXCH_CP NC_DP_TBTPB_AUXCH_CP

TRUETRUE

NC_DP_TBTPB_ML_CP<3..1:2> NC_DP_TBTPB_ML_CP<3..1:2>

TRUETRUE

NC_TBT_B_LSTX NC_TBT_B_LSTX

TRUETRUE

TBT_B_D2R_N<1..0>

NC_TBT_B_D2RN<1..0>

TRUETRUE

TBT_B_R2D_C_P<1..0>

NC_TBT_B_R2D_CP<1..0>

TRUETRUE

TBT_B_D2R_P<1..0>

NC_TBT_B_D2RP<1..0>

TRUETRUE

TBT_B_R2D_C_N<1..0>

NC_TBT_B_R2D_CN<1..0>

TRUETRUE

NC_SMC_T25_EN_L

NC_PCI_PME_L

NC_CLINK_DATA NC_CLINK_RESET_L

NC_SMC_FAN_1_CTL

NC_ENET_ASF_GPIO

NC_SMBUS_SMC_4_ASF_SDA

TRUE TRUE

PP3V3_S0SW_SSD

TRUE

PP3V3_SUS

TRUE

PP1V5_S0

TRUE

PP3V3_S0

TRUE

PPBUS_G3H

TRUE

PPBUS_S5_HS_COMPUTING_ISNS

TRUE

PP3V42_G3H

PP5V_S4_IPD

TRUE

TPAD_SPI_INT_S4_WAKE_L_CONN

TRUE

TPAD_USB_IF_EN_CONN

TRUE

FAN_RT_TACH

TRUE

FAN_RT_PWM

TRUE

SMBUS_SMC_5_G3_SCL

PP5V_S4RS3

TRUE

SPKRAMP_ROUT_P SPKRAMP_ROUT_N

TRUE

PP3V42_G3H

TRUE TRUE

SMC_ONOFF_L

PP3V3_S0SW_LCD_UF

TRUE

DP_INT_HPD_CONN

TRUE

LED_RETURN_2

PPHV_S0SW_LCDBKLT

TRUE

DP_INT_ML_N<0>

TRUE

DP_INT_ML_P<0>

TRUE

NC_PCIE_CLK100M_SDP

TRUETRUE

NC_PCIE_CLK100M_SDP

NC_PCIE_CLK100M_SDN

TRUETRUE

NC_PCIE_CLK100M_SDN

NC_PCIE_CLK100M_FWP

TRUETRUE

NC_PCIE_CLK100M_FWP

NC_PCIE_CLK100M_FWN

TRUETRUE

NC_PCIE_CLK100M_FWN

TRUE TRUE

NC_PCIE_FW_D2RNNC_PCIE_FW_D2RN

TRUETRUE

NC_PCIE_FW_D2RPNC_PCIE_FW_D2RP

NC_PCIE_FW_R2D_CP

TRUETRUE

NC_PCIE_FW_R2D_CP

TRUETRUE

NC_PCIE_FW_R2D_CNNC_PCIE_FW_R2D_CN

NC_USB_IRN

TRUETRUE

NC_USB_IRN

NC_USB_IRP

TRUETRUE

NC_USB_IRP

TRUE

NC_USB_CAMERAP

TRUE

NC_USB_CAMERAP

NC_USB_CAMERAN

TRUETRUE

NC_USB_CAMERAN

NC_USB_SDP

TRUETRUE

NC_USB_SDP

TRUE TRUE

NC_INT_ML_CP<3..1>

DP_INT_ML_C_P<3..1>

NC_USB_SDN

TRUETRUE

NC_USB_SDN

TRUETRUE

NC_INT_ML_CN<3..1>

DP_INT_ML_C_N<3..1>

NC_HDA_SDIN1

TRUETRUE

NC_HDA_SDIN1

NC_PCI_PME_L

TRUETRUE

NC_CLINK_CLK

TRUETRUE

NC_CLINK_CLK

TRUETRUE

NC_CLINK_DATA NC_CLINK_RESET_L

TRUE

NC_SMC_SYS_LED

TRUETRUE

NC_SMC_SYS_LED

NC_IR_RX_OUT_RC

TRUETRUE

NC_IR_RX_OUT_RC

TRUETRUE

NC_USB_SMCPNC_USB_SMCP

TRUETRUE

NC_USB_SMCNNC_USB_SMCN

TRUETRUE

NC_SMC_GFX_OVERTEMPNC_SMC_GFX_OVERTEMP

TRUE TRUE

NC_SMC_GFX_THROTTLE_LNC_SMC_GFX_THROTTLE_L

TRUETRUE

NC_SMC_FAN_1_CTL

TRUE TRUE

NC_SMC_FAN_5_CTLNC_SMC_FAN_5_CTL

TRUE TRUE

NC_SMC_FAN_1_TACHNC_SMC_FAN_1_TACH

NC_ENET_ASF_GPIO

TRUE TRUE

TRUE

NC_SMC_MPM5_LED_PWR

TRUE

NC_SMC_MPM5_LED_PWR

NC_SMC_MPM5_LED_CHG

TRUE TRUE

NC_SMC_MPM5_LED_CHG

TRUE

NC_SMC_DP_HPD_L

TRUE

NC_SMC_DP_HPD_L

NC_SMC_T25_EN_L

TRUE TRUE

NC_SMBUS_SMC_4_ASF_SCL

TRUE TRUE

NC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SDA

NC_BDV_BKL_PWM

TRUE TRUE

NC_BDV_BKL_PWM

DP_INT_AUX_CH_C_N

TRUE

I2C_TCON_SCL_R

PCIE_SSD_R2D_N<3..0>

TRUE

PCIE_AP_D2R_N

PCIE_AP_D2R_P

TRUE

PP3V3_S0SW_SSD_FLT

TRUE

PP3V3_WLAN

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_AP_R2D_P

TRUE

WIFI_EVENT_L

TRUE

MIPI_CLK_CONN_P

TRUE

MIPI_CLK_CONN_N

TRUE

CAM_SENSOR_WAKE_L_CONN

TRUE

PCIE_SSD_D2R_P<3..0>

TRUE

SMC_PWRFAIL_WARN_L

TRUE

SSD_SR_EN_L

SSD_PCIE_SEL_L

TRUE

SMC_OOB1_D2R_CONN_L

TRUE

SSD_RESET_CONN_L

TRUE

SSD_CLKREQ_CONN_L

PCIE_CLK100M_SSD_N

TRUE

PCIE_CLK100M_SSD_P

TRUE

MIPI_DATA_CONN_N MIPI_DATA_CONN_P

TRUE

SMBUS_SMC_1_S0_SCL

TRUE

SMBUS_SMC_1_S0_SDA

TRUE

I2C_CAM_SCK

TRUE

I2C_CAM_SDA

TRUE

PP5V_S3RS0_ALSCAM_F

TRUE

TP_SMC_MD1 SMC_TX_L

TRUE

LPC_FRAME_L

TRUE

SPI_ALT_IO1_MISO

TRUE

PM_CLKRUN_L

TRUE

SPIROM_USE_MLB

TRUE

SPI_ALT_CLK

TRUE

LPC_SERIRQ

TRUE

SPI_ALT_CS_L

TRUE

LPC_PWRDWN_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

SMC_RESET_L

TRUE

SMC_ROMBOOT

TRUE TRUE

SMC_RX_L

PP3V3_S5

TRUE

PP3V3_S3

TRUE

PP15V_TBT

TRUE

PP3V3_TBTLC

TRUE TRUE

PP1V05_TBT

LED_RETURN_3

TRUE

LED_RETURN_5

TRUE

LED_RETURN_6

TRUE

PPBUS_S5_HS_OTHER_ISNS

TRUE

PPDCIN_G3H

TRUE

PPVRTC_G3H

AUD_I2C_INT_L

AUD_IP_PERIPHERAL_DET

ENET_LOW_PWR

TRUE

SMBUS_SMC_5_G3_SDA

ODD_PWR_EN_L

TRUE

PP1V05_S0

PPVCC_S0_CPU

TRUE

PPDCIN_G3H_ISOL

TRUE

PP3V3_S4

TRUE

TP_DP_TBTSRC_ML_CP<3> TP_DP_TBTSRC_ML_CN<3> TP_DP_TBTSRC_ML_CP<2> TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CP<0> TP_DP_TBTSRC_ML_CN<0>

NC_DP_TBTSRC_ML_CP<1> NC_DP_TBTSRC_ML_CN<1>

NC_DP_TBTSRC_AUXCH_CP NC_DP_TBTSRC_AUXCH_CN

TRUETRUE

NC_DP_TBTSRC_AUXCH_CN

TRUETRUE

NC_DP_TBTSRC_AUXCH_CP

TRUETRUE

NC_DP_TBTSRC_ML_CN<1>

TRUETRUE

NC_DP_TBTSRC_ML_CP<1>

TRUE

NC_DP_TBTSRC_ML_CN<0>

TRUE

NC_DP_TBTSRC_ML_CP<0>

TRUE

TRUETRUE

NC_DP_TBTSRC_ML_CN<2>

TRUETRUE

NC_DP_TBTSRC_ML_CP<2>

TRUETRUE

NC_DP_TBTSRC_ML_CN<3>

TRUETRUE

NC_DP_TBTSRC_ML_CP<3>

TRUE

KBDLED_ANODE KBDLED_FB

TRUE

XDP_CPU_TDO

TRUE

XDP_CPU_TDI

TRUE

XDP_CPU_TMS

TRUE

XDP_CPUPCH_TRST_L

TRUE

XDP_PCH_TDI

TRUE

XDP_PCH_TMS

TRUE

XDP_CPU_PREQ_L

TRUE

XDP_PCH_TDO

TRUE

XDP_CPU_VCCST_PWRGD

TRUE

XDP_CPU_PRDY_L

TRUE

XDP_SYS_PWROK

TRUE

PM_RSMRST_L

TRUE

CPU_CFG<3>

TRUE

PM_SYSRST_L

TRUE

XDP_CPU_TCK

TRUE

XDP_PCH_TCK

TRUE

PP1V05_S0

TRUE

SMC_TMS

TRUE

GND

TRUE

LPCPLUS_RESET_L

TRUE

SMC_TDO

TRUE

TP_SMC_TRST_L

XDP_LPCPLUS_GPIO

TRUE

DP_INT_AUX_CH_C_P

TRUE

I2C_TCON_SDA_R

TRUE

SYS_DETECT_L

TRUE

LED_RETURN_1

LED_RETURN_4

TRUE

LPC_AD<3..0>

PCIE_SSD_D2R_N<3..0>

TRUE

SSD_PWR_EN

TRUE

SMBUS_SMC_3_SCL

AP_RESET_CONN_L

TRUE

SMBUS_SMC_3_SDA

TRUE

PCIE_CLK100M_AP_P

TRUE

HDMITBTMUX_FLAG FW_PWR_EN

ENET_MEDIA_SENSE

WOL_EN BT_PWRRST_L

FW_PME_L

HDD_PWR_EN

HDMITBTMUX_LATCH

AUD_SPI_MISO AUD_SPI_MOSI

AUD_SPI_CS_L AUD_SPI_CLK

PCH_BT_UART_RTS_L PCH_BT_UART_CTS_L

PCH_BT_UART_D2R PCH_BT_UART_R2D

TRUE

SPI_ALT_IO0_MOSI

TRUE

SPI_ALT_IO3_HOLD_L

TRUE

SPI_ALT_IO2_WP_L

<SCH_NUM>

104 OF 121

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26 62

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29 68

25 26 27 29 33 36 38 39 58 62 64

29 69

14 36 68

36

14 36 68

36

36 37 38 61 65

36

13 29 31

29

36 38

16 17 32 45 51 52 56 58 59 61 62

30 67

8

11 12 13 15 17 18

26 30 36 38 39 40 41

42 43 44 45 56 59 61

62 64 65 74

30

48 50

15

13

62

25 64 71 25 64 71

64 71 64 71

25 64 71 25 64 71

64 71 64 71

25 64 25 64

71 25

37 64

13 64

14 64

37 64

64

37 64

30 41 62

8

11 14 18 46 57 58 59 62

8

57 58 59 62

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

27 41 42 49 50 56 62

41 51 52 53 55 62

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

36

45

37 40 48 50 73

32 35 47 49 54 55 58 62

47 74

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

36 37 38

60

56 60

56 60 62

60 67

64 64

12 64 12 64

14 64 14 64

5

67

14 64 14 64

5

67

12 64 12 64

13 64

14 64 14 64

14 64

37 64 37 64

64 64

37 64 37 64

37 64

37 64 37 64

64

64 64

37 64 37 64

37 64

37 64 37 64

37 64

37 64 37 64

60 67

60

30 67

14 29 69

30

29 37 38 39 41

12 29 69

29 69

29 37 38

32 72

32

12 30 67

30 37

15 30

30

12 30 67

32 72

14 32 37 40 43 44 69 73

31 32

32

37 38

14 37 69

46

13 37

15 46

46

15 37

46

13 37

37 38

37 38 46

37 38 46 50

37 38

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 74

15 18 19 33 36 40 41 58 62

27 28 62

17 18 25 26 62

26

56 60

41 54 62

49 50 62 64

8

12 13 17 62

13

37 40 48 50 73

13

6 8

11 15 16 17 38 42 51 55 58

59 62 64

8

10 42 52 62

42 49 50 62

25 26 27 29 33 36 38 39 58 62 64

25

25 64

25 64 25 64

25 64

56

6

16 67

6

16 67

6

16 67

6

12 16 67

12 16 69

6

16 67

12 16 69

16

6

16 67

16

13 59

6

16 67

13 17 37

6

16 67

12 16 69

6 8

11 15 16 17 38 42 51 55 58

59 62 64

37 38 46

69

37 38

15 16

60 67

60

48

56 60

14 37 69

12 30 67

15 30 58 59

36 37 40 44 73

29

36 37 40 44 73

12 29 69

13

15

14

15

13

15

46

w w w . c h i n a f i x . c o m

TP

TP TP

TP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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NOTICE OF PROPRIETARY PROPERTY:

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REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Functional Test Points

(MAKE_BASE=TRUE on page 45)

SD Card Aliases

MAKE_BASE

J9500: LIO Connector

Bead Probes

FUNC_TEST

(Need to add 5 GND TPs)

1

BPA522

BEAD-PROBE

1

BPA523

BEAD-PROBE

1

BPA512

BEAD-PROBE

1

BPA521

BEAD-PROBE

1

BPA513

BEAD-PROBE

1

BPA520

BEAD-PROBE

1

BPA510

BEAD-PROBE

1

BPA511

BEAD-PROBE

Project FCT/NC/Aliases

SYNC_DATE=09/13/2012

SYNC_MASTER=J41_MLB

TRUE

AUD_PWR_EN

TRUE

USB3_EXTB_R2D_P

USB3_EXTB_D2R_RC_P

TRUE

USB3_EXTB_D2R_RC_N

TRUE

HDA_SYNC

TRUE

XDP_USB_EXTB_OC_L

TRUE

HDA_RST_L

TRUE

HDA_BIT_CLK HDA_SDIN0

TRUE

HDA_SDOUT

TRUE

PP5V_S0_ALT_AUD_LDO_EN

USB_EXTB_P

TRUE

SPKRAMP_INR_P

TRUE

FINSTACKSNS_ALERT_L

TRUE TRUE

SPKRAMP_INR_N

SMC_BC_ACOK

TRUE

USB_PWR_EN

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

SMBUS_SMC_2_S3_SCL

TRUE TRUE

SPKRAMP_SHDN_L

PP3V3_S0

TRUE TRUE

PP1V5_S0SW_AUDIO

USB3_EXTB_R2D_N

USB3_EXTB_R2D_C_P

USB3_EXTB_R2D_P

USB3_EXTB_R2D_C_N

USB3_EXTB_D2R_RC_P

USB3_EXTB_D2R_RC_N

USB3_EXTB_D2R_P

USB3_EXTB_D2R_N

PP3V42_G3H

TRUE

USB3_EXTB_R2D_N

USB3_SD_R2D_C_P

USB3_SD_D2R_N

USB3_SD_D2R_P

USB3_SD_R2D_C_N

PP3V3_S0SW_SD

TRUE

USB3_SD_D2R_P

TRUE

USB3_SD_D2R_N USB3_SD_R2D_C_P

TRUE

USB3_SD_R2D_C_N

TRUE

PP3V3_S0SW_SD

TRUE

USB_EXTB_N

TRUE

SMC_lID

SYS_ONEWIRE

TRUE

<SCH_NUM>

105 OF 121

65 OF 76

13 59 61

61 65 68

12 61 69

14 16 61

12 61 69

61

14 61 68

47 61 74

39 61

47 61 74

37 38 50 61

35 59 61

37 40 61 73

47 61

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 74

58 61

61 65 68

14 61 68

61 65 68

14 61 68

61 65 68

14 61 68

17 30 35 36 37 38 40 46 49 50

59 61 62 64

61 65 68

14 34 65 68

15 34 37 39 65

14 34 65 68

15 34 37 39 65

14 61 68

36 37 38 61 64

37 61

w w w . c h i n a f i x . c o m

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

B

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

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PAGE TITLE

SHEET

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

J41/J43 Board-Specific Spacing & Physical Constraints

Differential Pair Physical Constraints

Single-ended Physical Constraints

Spacing Constraints

ISL2,ISL11

80_OHM_DIFF

0.081 MM 0.081 MM 0.115 MM 0.115 MM

Y

80_OHM_DIFF

ISL3,ISL10

Y

0.081 MM 0.081 MM 0.115 MM 0.115 MM

80_OHM_DIFF

ISL4,ISL9

Y

0.088 MM 0.088 MM 0.110 MM 0.110 MM

=STANDARD

100 MM

80_OHM_DIFF

=STANDARD=STANDARD

* N

100 MM

PCB Rule Definitions

SYNC_DATE=10/24/2012

SYNC_MASTER=CONSTRAINTS

100 MM100 MM

N*

=STANDARD45_OHM_SE =STANDARD=STANDARD

0.080 MM

Y

ISL4,ISL945_OHM_SE

0.080 MM

0.096 MM 0.096 MM

Y

40_OHM_SE

ISL3,ISL10

100 MM

N*

35_OHM_SE

100 MM

=STANDARD =STANDARD=STANDARD

Y

ISL4,ISL935_OHM_SE

0.125 MM0.125 MM

Y

ISL3,ISL10

0.125 MM 0.125 MM

35_OHM_SE

P070MM_BGA

5 MM

0.075 MM0.070 MM

*

100 MM

N*

=STANDARD =STANDARD40_OHM_SE =STANDARD

100 MM

0.170 MM

TOP,BOTTOM

Y

40_OHM_SE

0.170 MM

0.090 MM

TOP,BOTTOM

Y

0.090 MM

55_OHM_SE

0.106 MM0.106 MM

73_OHM_DIFF

0.150 MM0.150 MM

ISL3,ISL10

Y

TOP,BOTTOM

Y

90_OHM_DIFF

0.200 MM 0.200 MM0.115 MM 0.115 MM

Y

ISL2,ISL11

90_OHM_DIFF

0.070 MM0.070 MM 0.180 MM 0.180 MM

0.096 MM

ISL2,ISL11

Y

40_OHM_SE

0.096 MM

N*

=STANDARD =STANDARD =STANDARD

85_OHM_DIFF

100 MM 100 MM

Y

ISL4,ISL9

85_OHM_DIFF

0.082 MM 0.082 MM 0.140 MM 0.140 MM

ISL3,ISL10

Y

85_OHM_DIFF

0.078 MM 0.078 MM 0.160 MM 0.160 MM

Y

ISL2,ISL11

85_OHM_DIFF

0.078 MM 0.078 MM 0.160 MM 0.160 MM

0.150 MM0.150 MM

Y

TOP,BOTTOM

85_OHM_DIFF

0.120 MM 0.120 MM

0.165 MM0.165 MM

73_OHM_DIFF

Y

TOP,BOTTOM

0.150 MM 0.150 MM

73_OHM_DIFF

=STANDARD=STANDARD=STANDARD

* N

100 MM100 MM

0.110 MM0.110 MM

73_OHM_DIFF

0.150 MM0.150 MM

ISL4,ISL9

Y

0.106 MM0.106 MM

73_OHM_DIFF

0.150 MM0.150 MM

ISL2,ISL11

Y

ISL2,ISL11

Y

45_OHM_SE

0.075 MM0.075 MM

ISL4,ISL9

Y

=45_OHM_SE =45_OHM_SE

DEFAULT

P070MM_BGA

BGA

*

0.071 MM

1x_DIELECTRIC

TOP,BOTTOM

?

0.053 MM

ISL3,ISL10

?

1x_DIELECTRIC

ISL4,ISL9

0.050 MM

?

DEFAULT

*

0.1 MM

?

*

0.090 MM

?

1x_DIELECTRIC

0.100 MM

1:1_SPACING

* ?

=DEFAULT =DEFAULTSTANDARD

*

=DEFAULT =DEFAULT =DEFAULT=DEFAULT

0.099 MM

40_OHM_SE

Y

ISL4,ISL9

0.099 MM

STANDARD

*

=DEFAULT

?

Y

27P4_OHM_SE

0.310 MM0.310 MM

TOP,BOTTOM

0.075 MM

BGA_P075MM

* ?

BGA

BGA_P075MM

**

0 MM

10 MM

100 MM 100 MM

N*

DEFAULT

0 MM

0.135 MM

TOP,BOTTOM

Y

45_OHM_SE

0.135 MM

16.2

MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA,MEM_TERM

TOP,BOTTOM =50_OHM_SE

DEFAULT

=50_OHM_SE

Y

ISL2,ISL11

DEFAULT

Y

=45_OHM_SE =45_OHM_SE

DEFAULT

ISL3,ISL10

Y

=45_OHM_SE =45_OHM_SE

0.182 MM 0.182 MM

Y

27P4_OHM_SE

ISL2,ISL11

0.182 MM0.182 MM

Y

ISL3,ISL10

27P4_OHM_SE

N

27P4_OHM_SE

*

100 MM 100 MM

=STANDARD=STANDARD=STANDARD

35_OHM_SE

TOP,BOTTOM

Y

0.195 MM0.195 MM

0.182 MM 0.182 MM

ISL4,ISL9

Y

27P4_OHM_SE

0.125 MM

35_OHM_SE

Y

0.125 MM

ISL2,ISL11

Y

ISL3,ISL10

45_OHM_SE

0.075 MM0.075 MM

0.110 MM

50_OHM_SE

Y

TOP,BOTTOM

0.110 MM

Y

70_OHM_DIFF

TOP,BOTTOM

0.165 MM 0.165 MM 0.110 MM 0.110 MM

Y

ISL4,ISL9

90_OHM_DIFF

0.180 MM0.180 MM0.076 MM 0.076 MM

N

=STANDARD =STANDARD =STANDARD

100 MM

*

90_OHM_DIFF

100 MM

Y

ISL3,ISL10

90_OHM_DIFF

0.070 MM 0.070 MM 0.180 MM 0.180 MM

80_OHM_DIFF

Y

0.132 MM 0.130 MM 0.130 MM

TOP,BOTTOM

0.132 MM

=STANDARD=STANDARD

* N

70_OHM_DIFF

=STANDARD

100 MM100 MM

ISL4,ISL9

Y

70_OHM_DIFF

0.110MM

0.095 MM 0.095 MM0.110 MM

Y

70_OHM_DIFF

ISL2,ISL11

0.105 MM 0.105 MM 0.100 MM 0.100 MM

70_OHM_DIFF

ISL3,ISL10

Y

0.105 MM 0.100 MM 0.100 MM0.105 MM

=STANDARD55_OHM_SE =STANDARD

* N

100 MM 100 MM

=STANDARD

100 MM100 MM

N*

=STANDARD =STANDARD=STANDARD50_OHM_SE

<SCH_NUM>

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TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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SHEET

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DRAWING NUMBER

REVISION

BRANCH

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THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(FSB_CPURST_L)

CPU PCIE Spacing

CPU Signal Constraints

PCIE Clock Spacing

PCH PCIE Spacing

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

Note: CPU_8MIL and CPU_ITP can be converted

back to TABLE_SPACING_RULE

once rdar://10308147 is resolved

Note: DisplayPort tables are on Page 113

DP

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

PCIe SSD

PCI-Express Interface Constraints

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I214

I215

SYNC_MASTER=CONSTRAINTS

CPU Constraints

SYNC_DATE=09/25/2012

PCIE_RX2OTHERRX

?

TOP,BOTTOM

=5x_DIELECTRIC

PCIE_CPU_TX

**

PCIE_2OTHER

*

PCIE_CPU_TX

*_RX

PCIE_2OTHERHS

CPU_8MIL

CPU_8MIL_2ANY

**

?

=2x_DIELECTRIC

CPU_AGTL

TOP,BOTTOM

=45_OHM_SE

*

=STANDARD

CPU_45S

=45_OHM_SE=45_OHM_SE =45_OHM_SE

=STANDARD

=80_OHM_DIFF =80_OHM_DIFF

=80_OHM_DIFF

CLK_PCIE_80D

*

=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF

CLK_PCIE_2SELF

* ?

=4x_DIELECTRIC

CPU_8MIL_2ANY

?

8 MIL

*

=4x_DIELECTRIC

* ?

CPU_ITP_2ANY

?*

=4x_DIELECTRIC

PCIE_2OTHERHS

PCIE_RX2OTHERRX

=4x_DIELECTRIC

* ?

PCIE_TX2RX

?

=7x_DIELECTRIC

TOP,BOTTOM

*

CLK_PCIE CLK_PCIE

CLK_PCIE_2SELF

CLK_PCIE_2OTHER =10x_DIELECTRIC

?

TOP,BOTTOM

?*

PCIE_TX2RX

=6x_DIELECTRIC

=4x_DIELECTRIC

PCIE_TX2OTHERTX

* ?

=2.5x_DIELECTRIC

PCIE_RX2RX

?*

?

PCIE_TX2TX

=2.5x_DIELECTRIC

*

TOP,BOTTOM

PCIE_2OTHER

=5x_DIELECTRIC

?

PCIE_2OTHERHS

TOP,BOTTOM

?

=6x_DIELECTRIC

PCIE_RX2TX TOP,BOTTOM

?

=7x_DIELECTRIC

PCIE_TX2OTHERTX

?

TOP,BOTTOM

=5x_DIELECTRIC

PCIE_TX2TX TOP,BOTTOM

=5x_DIELECTRIC

?

PCIE_PCH_TXPCIE_PCH_TX

*

PCIE_TX2TX

PCIE_RX2RX

*

PCIE_PCH_RX PCIE_PCH_RX

*

PCIE_PCH_TX

*_PCH_TX

PCIE_TX2OTHERTX

PCIE_PCH_RX

*

PCIE_RX2OTHERRX

*_PCH_RX

PCIE_2OTHERHS

*_RX

*

PCIE_PCH_TX

PCIE_PCH_RX

*

PCIE_2OTHERHS

*_TX

PCIE_PCH_TX

PCIE_2OTHERHS

*

*_TX

*_PCH_RX

*

PCIE_TX2RX

PCIE_PCH_TX

*_PCH_TX

*

PCIE_RX2TX

PCIE_PCH_RX

*_RX

*

PCIE_2OTHERHS

PCIE_PCH_RX

PCIE_PCH_TX

*

PCIE_2OTHER

*

PCIE_PCH_RX

* *

PCIE_2OTHER

PCIE_CPU_RX

*

PCIE_2OTHER

*

PCIE_CPU_RX

*

PCIE_2OTHERHS

*_RX

PCIE_2OTHERHS

PCIE_CPU_RX

*_TX

*

*_CPU_TX

PCIE_CPU_TX

*

PCIE_TX2OTHERTX

*_CPU_RX

PCIE_RX2OTHERRX

*

PCIE_CPU_RX

*

PCIE_RX2RX

PCIE_CPU_RX

PCIE_CPU_TX

*

PCIE_TX2TX

PCIE_CPU_TX

=3x_DIELECTRIC

*

?

PCIE_2OTHER

*

PCIE_RX2TX

?

=6x_DIELECTRIC

*

CLK_PCIE

*

CLK_PCIE_2OTHER

=27P4_OHM_SE

0.100 MM

*

CPU_27P4S

=27P4_OHM_SE =27P4_OHM_SE

0.100 MM

=27P4_OHM_SE

CPU_VCCSENSE

CPU_VCCSENSE_2SELF

*

CPU_VCCSENSE

PCIE_CPU_TX

*_TX

*

PCIE_2OTHERHS

*

PCIE_RX2TX

PCIE_CPU_RX

*_CPU_TX

PCIE_TX2RX

*

*_CPU_RX

PCIE_CPU_TX

CPU_VCCSENSE_2OTHER

* *

CPU_VCCSENSE

=6x_DIELECTRIC

* ?

CLK_PCIE_2OTHER

?

TOP,BOTTOM

=6x_DIELECTRIC

CPU_VCCSENSE_2SELF

=6x_DIELECTRIC

* ?

CPU_COMP_2OTHER

=4x_DIELECTRIC

* ?

CPU_COMP_2SELF

?*

CPU_AGTL

=STANDARD

CLK_PCIE_2SELF =6x_DIELECTRIC

?

TOP,BOTTOM

CPU_VCCSENSE_2OTHER

=6x_DIELECTRIC

* ?

CPU_VCCSENSE_2SELF

=4x_DIELECTRIC

* ?

CPU_COMP_2SELF

?

TOP,BOTTOM

=6x_DIELECTRIC

TOP,BOTTOM

CPU_COMP_2OTHER

?

=10x_DIELECTRIC

PCIE_RX2RX

=5x_DIELECTRIC

?

TOP,BOTTOM

CPU_VCCSENSE_2OTHER

?

TOP,BOTTOM

=10x_DIELECTRIC

* *

CPU_ITP_2ANY

CPU_ITP

CPU_COMP_2SELF

*

CPU_COMPCPU_COMP

* *

CPU_COMP_2OTHER

CPU_COMP

=80_OHM_DIFF=80_OHM_DIFF

=80_OHM_DIFF

*

PCIE_80D

=80_OHM_DIFF=80_OHM_DIFF

DP_INT_AUX_CH_C_P

DP_AUXDP_80DDP_INT_AUXCH

DP_INT_AUXCH DP_80D DP_AUX

DP_INT_AUXCH_C_N

DP_80D DP_AUX

DP_INT_AUXCH_P

DP_INT_AUXCH

DP_INT_AUXCH_C_P

DP_AUXDP_80D

DP_INT_AUX_CH_C_N

DP_AUXDP_80DDP_INT_AUXCH

DP_INT_ML_C_N<3..0>

DP_TX

DP_80D

DP_INT_ML_C_P<3..0>

DP_TX

DP_80D

DP_INT_ML_N<3..0>

DP_TX

DP_80D

DP_INT_ML

DP_INT_ML_P<3..0>

DP_TX

DP_80D

DP_INT_ML

DP_80D

DP_TBTSNK1_AUXCH_C_N

DP_AUX

DP_TBT_AUXCH DP_80D

DP_TBTSNK1_AUXCH_N

DP_AUX

DP_80D

DP_TBTSNK1_AUXCH_C_P

DP_AUX

DP_TBTSNK1_ML_C_N<3..0>

DP_80D

DP_TX

DP_TBTSNK1_ML_C_P<3..0>

DP_80D

DP_TX

DP_80D

DP_TBTSNK1_AUXCH_P

DP_TBT_AUXCH DP_AUX

DP_TBTSNK1_ML_P<3..0>

DP_80D

DP_TBT_ML

DP_TX

DP_TBTSNK1_ML_N<3..0>

DP_80D

DP_TBT_ML

DP_TX

DP_80D

DP_TBTSNK0_AUXCH_C_N

DP_AUX

DP_80D

DP_TBTSNK0_AUXCH_C_P

DP_AUX

DP_80D

DP_TBTSNK0_AUXCH_P

DP_TBT_AUXCH DP_AUX

DP_80D

DP_TBTSNK0_AUXCH_N

DP_TBT_AUXCH DP_AUX

DP_80D

DP_TBTSNK0_ML_C_P<3..0>

DP_TX

DP_80D

DP_TBT_ML

DP_TBTSNK0_ML_N<3..0>

DP_TX

DP_80D

DP_TBTSNK0_ML_C_N<3..0>

DP_TX

DP_80D

DP_TBT_ML

DP_TBTSNK0_ML_P<3..0>

DP_TX

CPU_AXG_VALSENSE_P

CPU_VCCSENSECPU_VALSENSE

CPU_27P4S

CPU_COMP

CPU_SVIDALERT_L

CPU_45S

CPU_VIDALERT_L

DP_80D DP_AUX

DP_INT_AUXCH_N

PCIE_SSD_D2R_C_P<3..0>

PCIE_80D

PCIE_CPU_RX

PCIE_SSD_D2R_C_N<3..0>

PCIE_80D

PCIE_CPU_RX

PCIE_SSD_D2R_P<3..0>

PCIE_CPU_SSD_D2R

PCIE_CPU_RX

PCIE_80D

PCIE_SSD_D2R_N<3..0>

PCIE_CPU_SSD_D2R

PCIE_CPU_RX

PCIE_80D

PCIE_CLK100M_SSD

PCIE_CLK100M_SSD_P

CLK_PCIE_80D

CLK_PCIE

PCIE_CLK100M_SSD_N

PCIE_CLK100M_SSD

CLK_PCIE_80D

CLK_PCIE

DPLL_REF_CLKP

CLK_PCIEDPLL_REF_CLK120M

CLK_PCIE_80D

XDP_CPU_CLK100M_P

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_80D

XDP_CPU_TDO

CPU_ITPXDP_TDO CPU_45S

XDP_CPU_TCK

XDP_TCK CPU_45S CPU_ITP

XDP_CPU_TMS

CPU_45S CPU_ITPXDP_TMS

PCIE_CPU_TX

PCIE_80D

PCIE_SSD_R2D_P<3..0> PCIE_SSD_R2D_N<3..0>

PCIE_80D

PCIE_CPU_TX

CPU_PECI

CPU_45S

CPU_COMPCPU_PECI

PM_MEM_PWRGD

CPU_AGTL

PM_MEM_PWRGD

CPU_45S

PM_SYNC

CPU_AGTL

PM_SYNC CPU_45S

XDP_DBRESET_L

CPU_ITPCPU_45S

XDP_CPU_PRDY_L

CPU_45S CPU_ITP

XDP_CPU_PREQ_L

CPU_45S CPU_ITP

EDP_COMP

CPU_27P4S

CPU_COMP

CPU_PEG_COMP

CPU_27P4S

CPU_COMP

CPU_SM_RCOMP<0>

CPU_COMP

CPU_SM_RCOMP

CPU_27P4S

CPU_COMP

CPU_SM_RCOMP<1>

CPU_27P4S

CPU_SM_RCOMP

CPU_SM_RCOMP<2>

CPU_COMP

CPU_SM_RCOMP

CPU_27P4S

CPU_CFG<11..0>

CPU_ITPCPU_45S

CPU_CATERR_L

CPU_AGTL

CPU_CATERR_L

CPU_45S

CPU_VCCIO_SEL

CPU_AGTL

CPU_45S

CPU_PROCHOT_L

CPU_AGTL

CPU_PROCHOT_L

CPU_45S

CPU_PWRGD

CPU_AGTL

CPU_PWRGD

CPU_45S

PM_THRMTRIP_L

CPU_8MIL

PM_THRMTRIP_L

CPU_45S CLK_PCIE_80D

DMI_CLK100M_CPU_P

CLK_PCIE

DMI_CLK100M

CLK_PCIE

ITPXDP_CLK100M_N

ITPCPU_CLK100M

CLK_PCIE_80D

CPU_VCCSENSE_P

SENSE_1TO1_P2MM

CPU_VCCSENSECPU_VCCSENSE

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_80D

ITPCPU_CLK100M_N

XDP_CPUPCH_TRST_L

XDP_TRST_L

CPU_45S CPU_ITP

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE

CPU_VCCSENSE

SENSE_1TO1_P2MM

CPU_COMP

CPU_45S

CPU_SVIDSCLK

CPU_VIDSCLK

PCIE_CPU_SSD_R2D

PCIE_CPU_TX

PCIE_80D

PCIE_SSD_R2D_C_N<3..0>

CPU_VDDQ_SENSE_P

CPU_27P4S

CPU_VALSENSE CPU_VCCSENSE

CPU_VCCIOSENSE_N

CPU_VCCSENSE

CPU_VCCIOSENSE

SENSE_1TO1_P2MM

XDP_OBSDATA_B<3..0>

CPU_ITPCPU_45S

CPU_ITP

XDP_BPM_L

XDP_BPM_L<1..0>

CPU_45S

CPU_ITPCPU_45S

XDP_BPM_L<7..2>

CPU_27P4S

CPU_VCCSENSECPU_VALSENSE

CPU_VDDQ_SENSE_N

XDP_CPURST_L

CPU_ITPCPU_45S

CPU_VALSENSE CPU_VCCSENSE

CPU_27P4S

CPU_VCC_VALSENSE_P

CPU_27P4S

CPU_VALSENSE CPU_VCCSENSE

CPU_VCC_VALSENSE_N

CPU_COMP

CPU_45S

CPU_SVIDSOUT

CPU_VIDSOUT

PCIE_CPU_SSD_R2D PCIE_80D

PCIE_CPU_TX

PCIE_SSD_R2D_C_P<3..0>

CPU_27P4S

CPU_VALSENSE CPU_VCCSENSE

CPU_AXG_VALSENSE_N

CPU_AXG_SENSE_N

CPU_AXG_SENSE

CPU_VCCSENSE

SENSE_1TO1_P2MM

CPU_AXG_SENSE_P

CPU_VCCSENSE

CPU_AXG_SENSE

SENSE_1TO1_P2MM

CPU_VCCSENSE_N

SENSE_1TO1_P2MM

CPU_VCCSENSE CPU_VCCSENSE

XDP_CPU_TDI

CPU_45S CPU_ITPXDP_TDI

XDP_CPU_CLK100M_N

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_80D

CPU_CFG<15..12>

CPU_ITPCPU_45S

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_80D

ITPXDP_CLK100M_P

ITPCPU_CLK100M_P

ITPCPU_CLK100M

CLK_PCIE_80D

CLK_PCIE

DPLL_REF_CLKN

CLK_PCIEDPLL_REF_CLK120M

CLK_PCIE_80D

DMI_CLK100M_CPU_N

CLK_PCIE

CLK_PCIE_80D

DMI_CLK100M

<SCH_NUM>

111 OF 121

67 OF 76

60 64

5

60

5

60

60 64

5

60 64

5

60 64

13 18 25

25

13 18 25

5

18 25

5

18 25

25

13 25

25

5

25

5

25

8

51

12 30 64

6

16 64

6

16 64

6

16 64

30 64

6

38

16 17

6

16 64

6

16 64

6

16 64

6

37

6

37 38 51

6

15 38

8

51

6

12 16 64

8

51

12 30

6

16

6

16

8

51

12 30

9

51

6

16 64

6

16

w w w . c h i n a f i x . c o m

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

USB EXTB nets (Left USB port)

SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

SATA Interface Constraints

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

PCH Net Properties

USB 3.0 Interface Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB 2.0 Interface Constraints

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

USB EXTA nets (Right USB port)

USB Hucopyb nets

UART Interface Constraints

TP SPI nets

=STANDARD

*

=STANDARD

8 MIL

=STANDARD

8 MIL

PCH_USB_RBIAS

=STANDARD

=80_OHM_DIFF =80_OHM_DIFF

*

=80_OHM_DIFF

USB_80D

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

UART

?*

=2x_DIELECTRIC

?

USB

*

=2x_DIELECTRIC

USB3_RX2RX

USB3_PCH_RXUSB3_PCH_RX

*

=80_OHM_DIFF

SATA_80D

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

*

=80_OHM_DIFF =80_OHM_DIFF

=4x_DIELECTRIC

SATA_ICOMP

* ?

?

USB

=4x_DIELECTRIC

TOP,BOTTOM

USB3_TX2TX

?

=5x_DIELECTRIC

TOP,BOTTOM

=5x_DIELECTRIC

USB3_RX2RX

?

TOP,BOTTOM

USB3_TX2OTHERTX

?

=5x_DIELECTRIC

USB3_RX2OTHERRX

?

=5x_DIELECTRIC

TOP,BOTTOM

USB3_TX2RX TOP,BOTTOM

?

=7x_DIELECTRIC

USB3_RX2TX

?

TOP,BOTTOM

USB3_2OTHERHS

=6x_DIELECTRIC

?

TOP,BOTTOM

USB3_2OTHER

?

=5x_DIELECTRIC

*

=2.5x_DIELECTRIC

?

USB3_RX2RX

*

=6x_DIELECTRIC

?

USB3_TX2RX

*

=4x_DIELECTRIC

?

USB3_TX2OTHERTX

*

=4x_DIELECTRIC

?

USB3_RX2OTHERRX

*

=6x_DIELECTRIC

?

USB3_RX2TX

*

=3x_DIELECTRIC

USB3_2OTHER

?

* ?

USB3_2OTHERHS

=4x_DIELECTRIC

USB3_TX2TX

USB3_PCH_TXUSB3_PCH_TX

*

USB3_RX2TX

USB3_PCH_RX

*

*_PCH_TX

USB3_PCH_TX

USB3_TX2OTHERTX

*

*_PCH_TX

USB3_RX2OTHERRX

USB3_PCH_RX

*

*_PCH_RX

USB3_TX2RX

USB3_PCH_TX

*

*_PCH_RX

USB3_PCH_RX

*

*_TX

USB3_2OTHERHS

USB3_PCH_TX

*

*_TX

USB3_2OTHERHS

USB3_PCH_TX

*

*_RX

USB3_2OTHERHS

USB3_2OTHERUSB3_PCH_RX

**

USB3_PCH_RX

*

*_RX

USB3_2OTHERHS

USB3_2OTHERUSB3_PCH_TX

**

* ?

USB3_TX2TX

=2.5x_DIELECTRIC

SYNC_DATE=11/13/2012

SYNC_MASTER=CLEAN_J43

PCH Constraints 1

=45_OHM_SE=45_OHM_SE=45_OHM_SE

UART_45S

*

=45_OHM_SE =45_OHM_SE=45_OHM_SE

USB

USB_80D

USB_BT_WAKE_P

USB_SDCARD

USB_80D

USB

USB_SDCARD_N

TPAD_SPI_MOSI

SPI_45S

SPI SPI

SPI_45S

TPAD_SPI_MISO

USB_80D

USB

USB_TPAD_CONN_N

UART_45S

UART

SMC_DEBUGPRT_RX_L

USB

USB_TPAD

USB_TPAD_P

USB_80D

USB

USB_BT_WAKE_N

USB_80D

USB

USB_80D

USB_BT_CONN_N

USB_HUB_UP_N

USB_80D

USB

USB_HUB1_UP

USB3_SD_RX

USB3_SD_D2R_P

USB3_PCH_RX

USB_80D

USB3_SD_TX

USB3_SD_R2D_C_P

USB3_PCH_TX

USB_80D

USB3_PCH_RX

USB3_SD_D2R_C_P

USB3_SD_R2D_P

USB3_PCH_TX

USB_80D

PCIE_CLK100M_PCH_P

CLK_PCIE

CLK_PCIE_80D

PCH_DIFFCLK_UNUSED_

USB3_SD_TX

USB3_SD_R2D_C_N

USB3_PCH_TX

USB_80D

USB3_SD_RX

USB3_SD_D2R_N

USB3_PCH_RX

USB_80D

USB3_EXTB_R2D_C_N

USB3_PCH_TX

USB_80D

USB3_EXTB_TX

USB3_EXTB_R2D_N

USB3_PCH_TX

USB_80D

USB3_PCH_RX

USB_80D

USB3_EXTB_RX

USB3_EXTB_D2R_N USB3_EXTB_D2R_RC_P

USB3_PCH_RX

USB_80D

USB3_EXTB_R2D_C_P

USB_80D

USB3_PCH_TX

USB_80D

USB3_SD_D2R_C_N

USB3_PCH_RX

USB3_PCH_TX

USB3_SD_R2D_N

USB_80D

PCH_CLK96M_DOT_P

CLK_PCIE_80D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

PCH_CLK96M_DOT_N

PCH_DIFFCLK_UNUSED_

CLK_PCIE_80D

CLK_PCIE

PCH_CLK100M_SATA_P

CLK_PCIE_80D

PCH_DIFFCLK_UNUSED_

CLK_PCIE

PCH_CLK100M_SATA_N

PCH_DIFFCLK_UNUSED_

CLK_PCIE

CLK_PCIE_80D

PCH_CLK14P3M_REFCLK

CPU_45S

CLK_PCIE

USB_EXTB_N

USB_80D

USB_EXTB

USB

USB_EXTB_P

USB

USB_80D

USB_EXTB

USB3_EXTB_D2R_P

USB_80D

USB3_PCH_RX

USB3_EXTB_RX

USB3_EXTB_D2R_RC_N

USB3_PCH_RX

USB_80D

USB3_EXTA_R2D_C_N

USB_80D

USB3_PCH_TX

USB3_EXTA_TX

USB3_PCH_TX

USB_80D

USB3_EXTA_R2D_N

USB3_EXTA_R2D_F_P

USB_80D

USB3_PCH_TX

USB_80D

USB3_PCH_TX

USB3_EXTA_R2D_C_P

USB3_EXTB_R2D_P

USB3_EXTB_TX

USB_80D

USB3_PCH_TX

USB3_EXTA_R2D_F_N

USB_80D

USB3_PCH_TX

USB

USB_BT_P

USB_80D

USB_BT

USB

USB_TPAD

USB_80D

USB_TPAD_N

USB

USB_80D

USB_BT_CONN_P

USB

USB_HUB_UP_P

USB_80D

USB_HUB1_UP

PCIE_CLK100M_PCH_N

PCH_DIFFCLK_UNUSED_

CLK_PCIE

CLK_PCIE_80D

USB3_EXTA_D2R_F_N

USB_80D

USB3_PCH_RX

USB_80D

USB3_EXTA_D2R_F_P

USB3_EXTA_TX

USB_80D

USB3_PCH_TX

USB3_EXTA_R2D_P

USB_80D

USB_BT

USB

USB_BT_N

SATA_ICOMP

PCH_SATA_ICOMP

PCH_SATAICOMP

USB2_EXTA

USB

USB_80D

USB2_EXTA_MUXED_P

USB_80D

USB

USB_TPAD_CONN_P

PCH_USB_RBIAS

PCH_USB_RBIAS PCH_USB_RBIAS

USB

USB_80D

TPAD_SPI_MISO_USB_N

USB

USB_80D

TPAD_SPI_MOSI_USB_P

USB3_EXTA_RX

USB_80D

USB3_EXTA_D2R_N

USB3_PCH_RX

USB3_EXTA_RX

USB_80D

USB3_PCH_RX

USB3_EXTA_D2R_P

USB2_EXTA

USB

USB_80D

USB2_EXTA_MUXED_F_N

USB2_EXTA

USB_80D

USB

USB2_EXTA_MUXED_F_P

USB2_EXTA

USB

USB_80D

USB2_EXTA_MUXED_N

UART_45S

SMC_DEBUGPRT_TX_L

UART

USB_EXTA

USB_80D

USB

USB_EXTA_N

USB

USB_EXTA

USB_80D

USB_EXTA_P

SPI

SPI_45S

TPAD_SPI_CLK

USB_80D

USB

USB_SDCARD_P

USB_SDCARD

USB

USB_TPAD_M_N

USB_80D

USB_TPAD_M

USB

USB_TPAD_M_P

USB_80D

USB_TPAD_M

<SCH_NUM>

112 OF 121

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29 64

14 34 65

34

14 34 65

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61 65

14 61 65

61 65

14 61 65

34

14 61 65

61 65

14 35

35

14 35

61 65

14 29

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29 64

35

14 29

35

14

14 35

35

35 37 38

14 35

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w w w . c h i n a f i x . c o m

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET

SIO Signal Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SMBus Interface Constraints

SPI Interface Constraints

XDP Constraints

LPC Bus Constraints

NOTE: 25MHz system clocks very sensitive to noise.

HD Audio Interface Constraints

PHYSICAL

NET_TYPE

System Clock Signal Constraints

DisplayPort

NET_TYPE

PCH Net Properties

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

Clock Net Properties

?

TOP,BOTTOM

DP_2OTHER

=4x_DIELECTRIC

?*

=3x_DIELECTRIC

DP_2DP

=45_OHM_SE

CLK_SLOW_45S

=STANDARD=STANDARD

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE

CLK_25M_45S

=STANDARD=STANDARD

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

*

DP_TX

*_TX

DP_2OTHERHS

=3x_DIELECTRIC

*

?

DP_2OTHER

DP_AUX

* ?

=3x_DIELECTRIC

*

?

DP_2OTHERHS

=4x_DIELECTRIC

CLK_SLOW_45S

=STANDARD

=45_OHM_SE

=STANDARD

*

=45_OHM_SE =45_OHM_SE =45_OHM_SE

CLK_LPC_45S

=45_OHM_SE =45_OHM_SE

=STANDARD=STANDARD

*

=45_OHM_SE=45_OHM_SE

LPC

=3x_DIELECTRIC

?*

=4x_DIELECTRIC

*

CLK_LPC

?

CLK_25M

?

=5x_DIELECTRIC

*

=STANDARD=STANDARD

*

=45_OHM_SE=45_OHM_SE=45_OHM_SE =45_OHM_SE

LPC_45S

=50_OHM_SE =50_OHM_SE=50_OHM_SE=50_OHM_SETOP,BOTTOM

SMB_45S_R_50S

?

=2x_DIELECTRIC

*

SMB

HDA

?

=2x_DIELECTRIC

*

=2x_DIELECTRIC

CLK_SLOW

?*

CLK_SLOW

=4x_DIELECTRIC

?*

=2:1_SPACING

?

PCH_ITP

*

=4x_DIELECTRIC

?

SPI

*

=STANDARD

=45_OHM_SE

PCH_45S

=45_OHM_SE

*

=STANDARD

=45_OHM_SE=45_OHM_SE

=45_OHM_SE

=STANDARD =STANDARD

*

=45_OHM_SE=45_OHM_SE=45_OHM_SE

SMB_45S_R_50S

=45_OHM_SE =45_OHM_SE=45_OHM_SE

=STANDARD =STANDARD

*

SPI_45S

=45_OHM_SE

=80_OHM_DIFF =80_OHM_DIFF

*

=80_OHM_DIFF

=80_OHM_DIFFDP_80D =80_OHM_DIFF =80_OHM_DIFF

DP_2DP

DP_TXDP_TX

*

*_RX

*

DP_TX

DP_2OTHERHS

*

DP_TX

*

DP_2OTHER

?

TOP,BOTTOM

DP_AUX

=4x_DIELECTRIC

DP_2DP

?

TOP,BOTTOM

=4x_DIELECTRIC

?

TOP,BOTTOM

DP_2OTHERHS

=6x_DIELECTRIC

SYNC_MASTER=J41_MLB

PCH Constraints 2

SYNC_DATE=12/14/2012

=STANDARD

=45_OHM_SE

*

HDA_45S

=45_OHM_SE =45_OHM_SE =45_OHM_SE

=STANDARD

SPI_MLB_IO3_HOLD_L

SPI

SPI_45S

SPI_IO3_R

SPI_45S

SPI

SPI_IO<3>

SPI_45S

SPI

SPI_MLB_IO2_WP_L

SPI_45S

SPI

SPI_IO2_R

SPI_45S

SPI

SPI_IO<2>

SPI_45S

SPI

SPI_MLB_CS_L

SPI

SPI_45S

SPI_MLB_IO0_MOSI

SPI

SPI_45S

SPI_MLB_IO1_MISO

SPI

SPI_45S

CLK_PCIE_80D

PCIE_CLK100M_CAMERA_C_N

CLK_PCIE

CLK_PCIE_80D

PCIE_CLK100M_CAMERA_C_P

CLK_PCIE

PCIE_CLK100M_CAM

CLK_PCIE_80D

PCIE_CLK100M_CAMERA_N

CLK_PCIE

PCIE_CLK100M_CAM

PCIE_CLK100M_CAMERA_P

CLK_PCIE_80D

CLK_PCIE

PCIE_80D

PCIE_PCH_RX

PCIE_CAMERA_D2R_C_N

PCIE_CAMERA_D2R_C_P

PCIE_80D

PCIE_PCH_RX

PCIE_CAM

PCIE_CAMERA_D2R_N

PCIE_80D

PCIE_PCH_RX

PCIE_CAM PCIE_80D

PCIE_PCH_RX

PCIE_CAMERA_D2R_P

PCIE_80D

PCIE_PCH_TX

PCIE_CAMERA_R2D_C_P

PCIE_80D

PCIE_PCH_TX

PCIE_CAMERA_R2D_C_N

PCIE_CAM PCIE_80D

PCIE_PCH_TX

PCIE_CAMERA_R2D_P

PCIE_CAM PCIE_80D

PCIE_PCH_TX

PCIE_CAMERA_R2D_N

XDP_PCH_TCK

PCH_45S PCH_ITPXDP_TCK

PCH_45S PCH_ITPXDP_TMS

XDP_PCH_TMS

XDP_TDO PCH_ITPPCH_45S

XDP_PCH_TDO

XDP_TDI PCH_45S PCH_ITP

XDP_PCH_TDI

CLK_PCIE_80D

CLK_PCIE

PEG_CLK100M_N

CLK_PCIE_80D

PEG_CLK100M_P

CLK_PCIE

PCIE_CLK100M_TBT CLK_PCIE

CLK_PCIE_80D

PCIE_CLK100M_TBT_N

PCIE_80D

PCIE_PCH_RX

PCIE_TBT_D2R_C_N<3..0>

PCIE_CLK100M_TBT

CLK_PCIE_80D

CLK_PCIE

PCIE_CLK100M_TBT_P

PCIE_PCH_RX

PCIE_80D

PCIE_TBT_D2R_C_P<3..0>

PCIE_80D

PCIE_TBT_D2R

PCIE_PCH_RX

PCIE_TBT_D2R_N<3..0>

PCIE_PCH_RX

PCIE_80D

PCIE_TBT_D2R_P<3..0>

PCIE_TBT_D2R

PCIE_80D

PCIE_PCH_TX

PCIE_TBT_R2D_C_N<3..0>

PCIE_PCH_TX

PCIE_TBT_R2D_C_P<3..0>

PCIE_80D

PCIE_PCH_TX

PCIE_TBT_R2D_N<3..0>

PCIE_TBT_R2D

PCIE_PCH_TX

PCIE_80D

PCIE_TBT_R2D

PCIE_TBT_R2D_P<3..0>

CLK_PCIE_80D

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP

CLK_PCIE

CLK_PCIE_80D

PCIE_CLK100M_AP_P

CLK_PCIE

PCIE_CLK100M_AP

PCIE_AP_D2R_N

PCIE_80D

PCIE_AP_D2R PCIE_PCH_RX

PCIE_80D

PCIE_AP_D2R PCIE_PCH_RX

PCIE_AP_D2R_P

PCIE_80D

PCIE_PCH_TX

PCIE_AP_R2D_C_N

PCIE_80D

PCIE_AP_R2D_C_P

PCIE_PCH_TX

PCIE_AP_R2D_N

PCIE_PCH_TX

PCIE_80D

PCIE_AP_R2D

PCIE_PCH_TX

PCIE_80D

PCIE_AP_R2D

PCIE_AP_R2D_P

CLK_25M_45S

CLK_25M

CLK25M_CAM_CLKP

CLK25M_CAM_CLKN

CLK_25M_45S

CLK_25M

SDCLK_CLK25M_X2_R

CLK_25M

CLK_25M_45S

SDSCLK_CLK25M_X1

CLK_25M

CLK_25M_45S

SYSCLK_CLK32K_RTC

CLK_SLOW_45S

CLK_SLOW

SYSCLK_CLK32K_RTCX1

SYSCLK_CLK25M_SB

CLK_25M_45S

SYSCLK_CLK25M_CAMERA

CLK_25M

SDCLK_CLK25M_X2

CLK_25M

CLK_25M_45S

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_X2_R

CLK_25M_45S

CLK_25M

CLK25M_CAM_XTALP_R

CLK_25M

CLK25M_CAM_XTALP

CLK_25M_45S

CLK_25M

CLK25M_CAM_XTALN

SYSCLK_CLK25M_TBT

CLK_25M

CLK_25M_45S

SYSCLK_CLK25M_TBT

CLK_25M_45S

SYSCLK_CLK25M_TBT_R

CLK_25M

SYSCLK_CLK25M_X1

SYSCLK_CLK25M_XTAL

CLK_25M

CLK_25M_45S

CLK_25M

SYSCLK_CLK25M_X2

CLK_25M_45S

CLK_SLOW

CLK_SLOW_45S

PM_SUS_CLK

PM_CLK32K_SUSCLK_R

CLK_SLOW_45S

CLK_SLOW

SMC_CLK32K

SPI_CLK

SPI

SPI_45S

SPI_CLK_R SPI_CLK

SPI_45S

SPI

SPI_MOSI_R

SPI_MOSI

SPI_45S

SPI

SPI_MOSI

SPI_45S

SPI

SMBUS_PCH_0_DATA

SML_PCH_0_DATA

SMB

SMB_45S_R_50S

SMBUS_PCH_DATA

SMB

SMB_45S_R_50S

SMBUS_SMC_1_S0_SCL

SMB_45S_R_50S

SMB

CLK_LPC_45S

CLK_LPC

LPC_CLK33M

LPC_CLK24M_SMC

HDA_SDIN0

HDA

HDA_45S

HDA_SYNC

HDA_45S

HDA

HDA_SYNC

HDA_45S

HDA

HDA_RST_L

HDA

HDA_RST_L

HDA_RST_R_L

HDA_45S

HDA

HDA_SDOUT_R

HDA_45S

HDA_SDOUT

HDA_45S

HDA

HDA_SYNC_R

HDA_45S

HDA

SMBUS_SMC_1_S0_SDA

SMB_45S_R_50S

SMB

SMBUS_SMC_1_S0_SDA

SMBUS_PCH_0_CLK

SMB_45S_R_50S

SML_PCH_0_CLK

SMB

HDA_BIT_CLK_R

HDA_45S

HDA

SMBUS_PCH_CLK

SMB

SMB_45S_R_50S

LPC_CLK24M_SMC_R

CLK_LPC

CLK_LPC_45S

LPC

LPC_45S

LPCPLUS_RESET_L

LPC

LPC_FRAME_L

LPC_45S

LPC_FRAME_L

LPC_AD<3..0>

LPC

LPC_45S

LPC_AD

LPC_CLK24M_LPCPLUS_R

CLK_LPC_45S

CLK_LPC

LPC_CLK24M_LPCPLUS

CLK_LPC_45S

LPC_CLK33M

CLK_LPC

HDA_BIT_CLK

HDA

HDA_BIT_CLK

HDA_45S

SPI_SMC_CS_L

SPI

SPI_45S

SPI_MLB_CLK

SPI

SPI_45S

SPI

SPI_45S

SPI_SMC_MISO

SPI_SMC_MOSI

SPI

SPI_45S

SPI

SPI_45S

SPI_SMC_CLK

SPI_45S

SPI_CS0_R_L

SPI

SPI_CS0

SPI

SPI_CS0_L

SPI_45S

SPI_MISO

SPI_45S

SPI

SPI_MISO SPI_MISO_R

SPI

SPI_45S

<SCH_NUM>

113 OF 121

69 OF 76

46

14 46

46

14 46

46

31 32

12 32

31 32

14 32

31 32

12 16 64

12 25

25

12 25

25

14 25

25

12 29 64

14 29 64

14 29

29 64

31 32

34 75

34

17 32

34

17

32

17 25

25

17

13 38

37 38

14 46

46

14 46

46

14 40

14 16 19 40 56

14 32 37 40 43 44 64 73

17 37

12 61 65

12

12 17

12 61 65

12

14 32 37 40 43 44 64 73

14 40

12

14 16 19 40 56

12 17

64

14 37 64

12 61 65

37 46

46

37 46

14 46

46

14 46

46

w w w . c h i n a f i x . c o m

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

Memory Net Properties

SPACING

Memory Bus Spacing Group Assignments

Memory to Power Spacing

Memory to GND Spacing

Memory Bus Constraints

Spacing Rule Sets

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_7

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_6

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_5

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_4

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_2

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_3

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_1

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_B_DATA_0

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_6

*

MEM_2OTHERMEM

MEM_*_DATA_*

*

MEM_A_DATA_7

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_5

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_4

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_3

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_2

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_0

*

MEM_2OTHERMEM

MEM_*_DATA_*MEM_A_DATA_1

*

SYNC_MASTER=CONSTRAINTS

Memory Constraints

SYNC_DATE=09/25/2012

*

MEM_*MEM_*

MEM_2OTHERMEM

MEM_CMD2CMD

MEM_CMD MEM_CMD

*

MEM_B_DQS_5

MEM_B_DATA_5

*

MEM_DQS2OWNDATA

MEM_B_DQS_3

*

MEM_DQS2OWNDATA

MEM_B_DATA_3

MEM_B_DQS_1

*

MEM_B_DATA_1

MEM_DQS2OWNDATA

*

MEM_B_DQS_0

MEM_B_DATA_0

MEM_DQS2OWNDATA

MEM_B_DQS_4

*

MEM_DQS2OWNDATA

MEM_B_DATA_4

MEM_B_DQS_2

*

MEM_B_DATA_2

MEM_DQS2OWNDATA

**

MEM_2OTHER

MEM_A_DQS_5

**

MEM_2OTHER

MEM_A_DQS_6

**

MEM_2OTHER

MEM_A_DQS_7

**

MEM_2OTHER

MEM_B_DQS_0

**

MEM_2OTHER

MEM_B_DQS_1

* *

MEM_2OTHER

MEM_B_DQS_2

MEM_B_DQS_3

*

MEM_2OTHER

*

**

MEM_2OTHER

MEM_A_DQS_1

**

MEM_2OTHER

MEM_B_DQS_5

MEM_2OTHER

* *

MEM_A_DATA_0

*

MEM_*_DATA_*

MEM_DATA2SELF

=SAME

**

MEM_2OTHER

MEM_A_DQS_2

**

MEM_2OTHER

MEM_A_DQS_0MEM_A_DQS_0

*

MEM_A_DATA_0

MEM_DQS2OWNDATA

MEM_A_DQS_1

*

MEM_DQS2OWNDATA

MEM_A_DATA_1

*

MEM_A_DQS_3

MEM_DQS2OWNDATA

MEM_A_DATA_3

*

10000

MEM_2PWR

=2x_DIELECTRIC

=4x_DIELECTRIC

* ?

MEM_2OTHERMEM

?*

=6x_DIELECTRIC

MEM_CLK2CLK

=3x_DIELECTRIC

* ?

MEM_CTRL2CTRL

* ?

=3x_DIELECTRIC

MEM_CMD2CTRL

?

=3x_DIELECTRIC

*

MEM_CMD2CMD

=3x_DIELECTRIC

* ?

MEM_DQS2OWNDATA

=8x_DIELECTRIC

?

*

MEM_DATA2OTHERMEM

MEM_2OTHER

* *

MEM_CLK

* ?

MEM_DATA2SELF

=2x_DIELECTRIC

*

=2x_DIELECTRIC

10000

MEM_2GND

=40_OHM_SE

MEM_40S

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE

=40_OHM_SE

*

=50_OHM_SE =50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

=50_OHM_SE

MEM_50S

*

=73_OHM_DIFF=73_OHM_DIFF=73_OHM_DIFF=73_OHM_DIFF=73_OHM_DIFF

MEM_73D

*

=73_OHM_DIFF

=70_OHM_DIFF

*

MEM_70D

=70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFF

MEM_2OTHER

*

MEM_CMD

*

MEM_CTRL

*

MEM_2OTHER

MEM_CMD2CTRL

MEM_CMD

*

MEM_CTRL

*

MEM_DQS2OWNDATA

MEM_A_DQS_2

MEM_A_DATA_2

*GND

MEM_*

MEM_2GND

*

MEM_*

MEM_PWR

MEM_2PWR

*

DEFAULTMEM_PWR

*

* ?

MEM_2OTHER

=6x_DIELECTRIC

MEM_A_DATA_4

MEM_A_DQS_4

*

MEM_DQS2OWNDATA

MEM_A_DATA_5

MEM_A_DQS_5

*

MEM_DQS2OWNDATA

MEM_A_DQS_6

*

MEM_A_DATA_6

MEM_DQS2OWNDATA

MEM_A_DQS_7

*

MEM_A_DATA_7

MEM_DQS2OWNDATA

*

MEM_B_DQS_7

MEM_2OTHER

*

MEM_73D

MEM_TERM

MEM_70D

MEM_50S

MEM_TERM

MEM_40S

**

MEM_2OTHER

MEM_B_DQS_6

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_*_DATA_*

*

MEM_*

MEM_DATA2OTHERMEM

MEM_B_DQS_6

*

MEM_DQS2OWNDATA

MEM_B_DATA_6

*

MEM_B_DQS_7

MEM_DQS2OWNDATA

MEM_B_DATA_7

MEM_CLK

*

MEM_CLK2CLK

MEM_CLK

**

MEM_2OTHER

MEM_A_DQS_3

MEM_2OTHER

**

MEM_A_DQS_4

*

MEM_2OTHER

MEM_B_DQS_4

*

MEM_2OTHER

*

MEM_B_DATA_6

*

MEM_B_DATA_7

*

MEM_2OTHER

*

MEM_B_DATA_5

MEM_2OTHER

* *

MEM_B_DATA_4

MEM_2OTHER

* *

MEM_2OTHER

MEM_B_DATA_3

* *

MEM_B_DATA_2

MEM_2OTHER

* *

MEM_B_DATA_1

MEM_2OTHER

* *

MEM_B_DATA_0

MEM_2OTHER

* *

MEM_2OTHER

**

MEM_A_DATA_7

MEM_2OTHER

MEM_A_DATA_6

* *

MEM_A_DATA_5

MEM_2OTHER

* *

MEM_A_DATA_4

MEM_2OTHER

* *

MEM_2OTHER

MEM_A_DATA_3

* *

MEM_A_DATA_2

MEM_2OTHER

* *

MEM_A_DATA_1

MEM_2OTHER

* *

MEM_A_CLK0

MEM_A_CLK_N<0>

MEM_CLKMEM_70D

MEM_A_CLK0

MEM_A_CLK_P<0>

MEM_70D MEM_CLK

MEM_A_CLK_P<1>

MEM_A_CLK1

MEM_CLKMEM_70D

MEM_A_CLK_N<1>

MEM_70D MEM_CLK

MEM_A_CLK1

MEM_A_CS_L<1..0>

MEM_A_CTRL

MEM_CTRL

MEM_40S

MEM_A_ODT<0>

MEM_40S

MEM_CTRL

MEM_A_CTRL MEM_A_CKE0

MEM_A_CKE<1..0>

MEM_40S MEM_CMD

MEM_CMDMEM_40S

MEM_A_CKE<3..2>

MEM_A_CKE1

MEM_40S

MEM_A_CAB<9..0>

MEM_CMD

MEM_A_CMD1

MEM_40S

MEM_A_CAA<9..0>

MEM_CMD

MEM_A_CMD0

MEM_40SMEM_A_DQ_BYTE0

MEM_A_DATA_0

MEM_A_DQ<7..0>

MEM_40SMEM_A_DQ_BYTE2

MEM_A_DATA_2

MEM_A_DQ<23..16>

MEM_40SMEM_A_DQ_BYTE1

MEM_A_DATA_1

MEM_A_DQ<15..8>

MEM_40SMEM_A_DQ_BYTE4

MEM_A_DATA_4

MEM_A_DQ<39..32>

MEM_40SMEM_A_DQ_BYTE3

MEM_A_DATA_3

MEM_A_DQ<31..24>

MEM_40SMEM_A_DQ_BYTE5

MEM_A_DATA_5

MEM_A_DQ<47..40>

MEM_A_DQ<63..56>

MEM_40SMEM_A_DQ_BYTE7

MEM_A_DATA_7

MEM_A_DQ<55..48>

MEM_40SMEM_A_DQ_BYTE6

MEM_A_DATA_6

MEM_A_DQS_P<0>

MEM_70D

MEM_A_DQS0

MEM_A_DQS_0

MEM_A_DQS_N<0>

MEM_70D

MEM_A_DQS0

MEM_A_DQS_0

MEM_A_DQS_P<1>

MEM_70D

MEM_A_DQS1

MEM_A_DQS_1

MEM_A_DQS_P<2>

MEM_70D

MEM_A_DQS2

MEM_A_DQS_2

MEM_A_DQS_N<1>

MEM_70D

MEM_A_DQS1

MEM_A_DQS_1

MEM_70D

MEM_A_DQS3

MEM_A_DQS_3

MEM_A_DQS_P<3>

MEM_A_DQS_N<2>

MEM_70D

MEM_A_DQS2

MEM_A_DQS_2

MEM_70D

MEM_A_DQS3

MEM_A_DQS_3

MEM_A_DQS_N<3>

MEM_A_DQS_4

MEM_70D

MEM_A_DQS4

MEM_A_DQS_N<4>

MEM_A_DQS_4

MEM_70D

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_A_DQS_5

MEM_70D

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_A_DQS_6

MEM_A_DQS6

MEM_70D

MEM_A_DQS_P<6>

MEM_A_DQS5

MEM_A_DQS_5

MEM_70D

MEM_A_DQS_N<5>

MEM_A_DQS6

MEM_A_DQS_6

MEM_70D

MEM_A_DQS_N<6>

MEM_A_DQS_7

MEM_70D

MEM_A_DQS_P<7>

MEM_A_DQS7

MEM_A_DQS_7

MEM_70D

MEM_A_DQS_N<7>

MEM_A_DQS7

MEM_B_CLK_P<0>

MEM_CLKMEM_70D

MEM_B_CLK0

MEM_B_CLK_N<0>

MEM_CLKMEM_70D

MEM_B_CLK0

MEM_B_CLK_P<1>

MEM_CLKMEM_70D

MEM_B_CLK1 MEM_B_CLK1

MEM_B_CLK_N<1>

MEM_CLKMEM_70D

MEM_B_CTRL

MEM_B_CS_L<1..0>

MEM_CTRL

MEM_40S

MEM_B_CTRL

MEM_B_ODT<0>

MEM_CTRL

MEM_40S

MEM_B_CKE<1..0>

MEM_B_CKE0

MEM_CMDMEM_40S

MEM_B_CKE1

MEM_B_CKE<3..2>

MEM_CMDMEM_40S

MEM_B_CMD0

MEM_B_CAA<9..0>

MEM_CMDMEM_40S

MEM_B_CMD1

MEM_B_CAB<9..0>

MEM_CMDMEM_40S MEM_B_DATA_0

MEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_40S

MEM_B_DQ_BYTE2

MEM_B_DATA_2

MEM_B_DQ<23..16>

MEM_40S

MEM_B_DATA_1

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_40S

MEM_B_DATA_3

MEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_40S

MEM_B_DQ_BYTE4 MEM_40S

MEM_B_DATA_4

MEM_B_DQ<39..32>

MEM_B_DATA_5

MEM_B_DQ<47..40>

MEM_40SMEM_B_DQ_BYTE5

MEM_B_DQ<55..48>

MEM_B_DATA_6

MEM_40SMEM_B_DQ_BYTE6

MEM_B_DATA_7

MEM_B_DQ<63..56>

MEM_40SMEM_B_DQ_BYTE7

MEM_B_DQS_0

MEM_B_DQS_P<0>

MEM_70D

MEM_B_DQS0

MEM_B_DQS_0

MEM_B_DQS0

MEM_B_DQS_N<0>

MEM_70D

MEM_B_DQS_1

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_70D

MEM_B_DQS_1

MEM_B_DQS1

MEM_B_DQS_N<1>

MEM_70D

MEM_B_DQS_2

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_70D

MEM_B_DQS_2

MEM_B_DQS2

MEM_B_DQS_N<2>

MEM_70D

MEM_B_DQS_3

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_70D

MEM_B_DQS_3

MEM_B_DQS3

MEM_B_DQS_N<3>

MEM_70D

MEM_B_DQS4

MEM_B_DQS_4

MEM_B_DQS_P<4>

MEM_70D

MEM_B_DQS_4

MEM_B_DQS4

MEM_B_DQS_N<4>

MEM_70D MEM_70D

MEM_B_DQS_P<5>

MEM_B_DQS_5

MEM_B_DQS5

MEM_B_DQS_6

MEM_B_DQS_P<6>

MEM_B_DQS6

MEM_70D

MEM_B_DQS_5

MEM_B_DQS5

MEM_B_DQS_N<5>

MEM_70D

MEM_B_DQS_N<6>

MEM_B_DQS_6

MEM_B_DQS6

MEM_70D

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_B_DQS_7

MEM_70D

MEM_B_DQS_7

MEM_B_DQS7

MEM_B_DQS_N<7>

MEM_70D

PP1V2_S3

MEM_PWR MEM_PWR

PP0V6_S3_MEM_VREFCA_A

MEM_PWR

PP0V6_S3_MEM_VREFDQ_A PP0V6_S3_MEM_VREFCA_B

MEM_PWR

PP0V6_S3_MEM_VREFDQ_B

MEM_PWR

<SCH_NUM>

114 OF 121

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17 19 20 21 22 23 42 53 62

18 19 20 21

18 19 22 23

w w w . c h i n a f i x . c o m

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Only used on dual-port hosts.

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

Thunderbolt IC Net Properties

SPACING

Only used on hosts supporting Thunderbolt video-in

Thunderbolt/DP Net Properties

DisplayPort Signal Constraints

Thunderbolt SPI Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

Thunderbolt/DP Connector Signal Constraints

*

TBTDP_TXTBTDP_TX

TBTDP_TX2TX

SYNC_MASTER=CONSTRAINTS

SYNC_DATE=09/25/2012

Thunderbolt Constraints

TOP,BOTTOM

?

TBTDP_TX2RX

=10x_DIELECTRIC

?

TOP,BOTTOM

=10x_DIELECTRIC

TBTDP_2OTHERHS

TOP,BOTTOM

?

TBTDP_RX2RX

=6x_DIELECTRIC

*

TBTDP_2OTHERHS

*_TX

TBTDP_TX

* *

TBTDP_RX

TBTDP_2OTHER

*

TBTDP_TX

*

TBTDP_2OTHER

TBTDP_RX

*

TBTDP_2OTHERHS

*_RX

TOP,BOTTOM

?

=6x_DIELECTRIC

TBTDP_2OTHER

*

TBTDP_RXTBTDP_TX

TBTDP_TX2RX

=4x_DIELECTRIC

*

TBTDP_TX2TX

?

=6x_DIELECTRIC

*

?

TBTDP_TX2RX

=4x_DIELECTRIC

*

?

TBTDP_RX2RX

*

?

TBTDP_2OTHER

=4x_DIELECTRIC

?

*

TBTDP_2OTHERHS =6x_DIELECTRIC

TBTDP_RX

*

TBTDP_2OTHERHS

*_TX

TBTDP_TX

*

*_RX

TBTDP_2OTHERHS

?

=2x_DIELECTRIC

*

TBT_SPI

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF

*

TBTDP_80D

=80_OHM_DIFF

TBTDP_RX2RX

*

TBTDP_RXTBTDP_RX

*

TBTDP_RX

TBTDP_TX2RX

TBTDP_TX

TOP,BOTTOM

?

TBTDP_TX2TX

=6x_DIELECTRIC

=STANDARD=STANDARD

=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE

*

TBT_SPI_45S

TBT_A_D2R_C_P<1..0>

TBTDP_80D

TBTDP_RX

TBT_A_D2R_P<1>

TBT_A_D2R1

TBTDP_80D

TBTDP_RX

TBTDP_80D

TBT_A_D2R_N<1>

TBT_A_D2R1

TBTDP_RX

TBTDP_80D

TBT_A_D2R_P<0>

TBT_A_D2R0

TBTDP_RX

TBTDP_80D

TBT_A_D2R_N<0>

TBT_A_D2R0

TBTDP_RX

DP_TBTPA_AUXCH_C_P

DP_80D

TBT_A_AUXCH

DP_AUX

DP_TBTPA_AUXCH_C_N

TBT_A_AUXCH

DP_80D DP_AUX

DP_80D

DP_TBTPA_AUXCH_P

DP_AUX

DP_80D

DP_TBTPA_AUXCH_N

DP_AUX

DP_A_AUXCH_DDC_P

DP_80D DP_AUX

TBT_A_D2R_C_N<1..0>

TBTDP_80D

TBTDP_RX

TBT_A_D2R1_AUXDDC_P

TBTDP_80D

TBTDP_RX

TBT_A_D2R1_AUXDDC_N

TBTDP_80D

TBTDP_RX

TBTDP_80DTBT_B_R2D

TBT_B_R2D_C_N<1..0>

TBTDP_TX

TBTDP_80D

TBT_B_R2D_N<1..0>

TBTDP_TX

TBTDP_80DTBT_A_R2D

TBT_A_R2D_C_P<1..0>

TBTDP_TX

TBTDP_80DTBT_A_R2D

TBT_A_R2D_C_N<1..0>

TBTDP_TX

TBTDP_80D

TBT_A_R2D_N<1..0>

TBTDP_TX

TBTDP_80D

TBT_A_R2D_P<1..0>

TBTDP_TX

DP_TX

DP_80D

DP_TBTSRC_ML_C_P<3..0>

DP_TX

DP_80D

DP_TBTSRC_ML_C_N<3..0>

DP_AUXDP_80D

DP_TBTSRC_AUXCH_C_P

DP_AUXDP_80D

DP_TBTSRC_AUXCH_C_N

TBT_SPI

TBT_SPI_45STBT_SPI_CLK

TBT_SPI_CLK

TBT_SPI

TBT_SPI_45S

TBT_SPI_MOSI

TBT_SPI

TBT_SPI_45S

TBT_SPI_MISO

TBT_SPI_CS_L

TBT_SPI

TBT_SPI_45S

TBT_SPI_CS_L

TBTDP_80D

TBT_B_R2D_C_P<1..0>

TBT_B_R2D

TBTDP_TX

TBTDP_80D

TBT_B_R2D_P<1..0>

TBTDP_TX

DP_TX

DP_80D

NC_DP_TBTPB_ML_CP<3..1:2>

DP_TBTPB_ML

DP_TX

DP_80D

DP_TBTPB_ML_P<3..1:2>

DP_TX

DP_80D

DP_TBTPB_ML

NC_DP_TBTPB_ML_CN<3..1:2>

DP_TX

DP_80D

DP_TBTPB_ML_N<3..1:2>

DP_B_LSX_ML_N<1>

DP_TX

DP_80D

DP_B_LSX_ML_P<1>

DP_TX

DP_80D

TBT_B_D2R_C_P<1..0>

TBTDP_80D

TBTDP_RX

TBTDP_80D

TBT_B_D2R_C_N<1..0>

TBTDP_RX

TBT_B_D2R TBTDP_80D

TBT_B_D2R_P<1..0>

TBTDP_RX

TBTDP_80DTBT_B_D2R

TBT_B_D2R_N<1..0>

TBTDP_RX

DP_80D

TBT_B_AUXCH

NC_DP_TBTPB_AUXCH_CP

DP_AUX

DP_80D

TBT_B_AUXCH

NC_DP_TBTPB_AUXCH_CN

DP_AUX

DP_80D

DP_B_AUXCH_DDC_P

DP_AUX

DP_80D

DP_TBTPB_AUXCH_P

DP_AUX

DP_80D

DP_TBTPB_AUXCH_N

DP_AUX

DP_80D

DP_B_AUXCH_DDC_N

DP_AUX

TBTDP_80D

TBT_B_D2R1_AUXDDC_P

TBTDP_RX

TBTDP_80D

TBT_B_D2R1_AUXDDC_N

TBTDP_RX

DP_A_AUXCH_DDC_N

DP_80D DP_AUX

DP_A_LSX_ML_P<1>

DP_80D

DP_TX

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML1 DP_80D

DP_TX

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML1 DP_80D

DP_TX

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML3

DP_TX

DP_80D

DP_TX

DP_A_LSX_ML_N<1>

DP_80D

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML3

DP_TX

DP_80D

DP_TBTPA_ML_N<3..1:2>

DP_TX

DP_80D

DP_TBTPA_ML_P<3..1:2>

DP_TX

<SCH_NUM>

115 OF 121

71 OF 76

28

25 28

28

64

25 28

28

25

64

25 64

28

25 28

28

25 28

28

w w w . c h i n a f i x . c o m

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_RULE_ITEM

Memory Bus Constraints

NET_TYPE

PHYSICAL

SPACING

Memory to GND Spacing

Memory to Power Spacing

Spacing Rule Sets

MIPI Interface Constraints

Memory Bus Spacing Group Assignments

Camera Net Properties

ELECTRICAL_CONSTRAINT_SET

I101

I102

I103

I104

I106

I107

I108

I109

I110

I127

I128

I129

I130

I131

I132

I133

I134

I145

I146

I147

I148

I149

=2x_DIELECTRIC

S2_CMD2CTRL

?*

S2_CMD2CMD

* ?

=2x_DIELECTRIC

SYNC_DATE=01/30/2013

SYNC_MASTER=J41_MLB

Camera Constraints

*

S2_MEM_DATA1

S2_DQS2OWNDATA

S2_MEM_DQS1

?*

S2MEM_2OTHER

=6x_DIELECTRIC

=2x_DIELECTRIC

S2MEM_2GND

* ?

=4X_DIELECTRIC

*

?

MIPI_2OTHER

?

=6X_DIELECTRIC

*

MIPI_2CLK

?

=7X_DIELECTRIC

*

MIPICLK_2OTHER

MIPI_DATA

MIPI_2OTHER

**

MIPI_DATA

CLK_MIPI

MIPI_2CLK

*

MIPICLK_2OTHER

*

CLK_MIPI

*

=45_OHM_SES2_MEM_45S

*

=45_OHM_SE

=STANDARD

=45_OHM_SE

=STANDARD

=45_OHM_SE

S2_MEM_85D

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

*

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

MIPI_85D

*

S2_MEM_*

S2MEM_2GND

GND

S2_MEM_* S2_MEM_*

*

S2_2OTHERMEM

*

S2_CTRL2CTRL

S2_MEM_CTRLS2_MEM_CTRL

*

S2_MEM_CMD

S2_CMD2CMD

S2_MEM_CMD

*

S2MEM_2OTHER

*

S2_MEM_CLK

**

S2_MEM_CTRL

S2MEM_2OTHER

S2_MEM_CMD

* *

S2MEM_2OTHER

*

S2_MEM_DATA0

S2_DQS2OWNDATA

S2_MEM_DQS0

DEFAULT

* *

S2_MEM_PWR

*

S2_MEM_PWR

S2_MEM_*

S2MEM_2PWR

S2_MEM_DATA*

S2_DATA2SELF

*

=SAME

**

S2_MEM_DATA* S2MEM_2OTHER

S2MEM_2OTHER

* *

S2_MEM_DQS*

*

S2_CMD2CTRL

S2_MEM_CTRL

S2_MEM_CMD

* ?

S2_DATA2SELF

=2x_DIELECTRIC

S2MEM_2PWR

=2x_DIELECTRIC

* ?

S2_DQS2OWNDATA

* ?

=2x_DIELECTRIC

?*

=4x_DIELECTRIC

S2_2OTHERMEM

=2x_DIELECTRIC

S2_CTRL2CTRL

* ?

S2_CTRL2CTRL

?

TOP,BOTTOM

=4x_DIELECTRIC

?

=4x_DIELECTRIC

TOP,BOTTOMS2MEM_2GND

TOP,BOTTOM

=6x_DIELECTRIC

?

S2_2OTHERMEM

S2_CMD2CMD

?

TOP,BOTTOM

=4x_DIELECTRIC

=4x_DIELECTRICS2_DQS2OWNDATA

?

TOP,BOTTOM

S2_DATA2SELF

?

=4x_DIELECTRIC

TOP,BOTTOM

=6X_DIELECTRIC

?

TOP,BOTTOM

MIPI_2OTHER

MIPI_2CLK

=8X_DIELECTRIC

?

TOP,BOTTOM

MIPICLK_2OTHER

=10X_DIELECTRIC

TOP,BOTTOM

?

=4x_DIELECTRIC

S2_CMD2CTRL

?

TOP,BOTTOM

?

S2MEM_2PWR

=4x_DIELECTRIC

TOP,BOTTOM

=10x_DIELECTRIC

?

S2MEM_2OTHER

MEM_CAM_CLK_P

S2_MEM_85D S2_MEM_CLKS2_MEM_CLK

MIPI_85D

MIPI_DATA_P

MIPI_DATA

MIPI_DATA_S2

MIPI_85D

MIPI_DATA_S2

MIPI_DATA

MIPI_DATA_N

MIPI_85D

MIPI_DATA

MIPI_DATA_CONN_P

MIPI_85D

MIPI_DATA

MIPI_DATA_CONN_N

MEM_CAM_DQS_P<1>

S2_MEM_DQS1

S2_MEM_85D

S2_MEM_DQS1

PP1V35_CAM

S2_MEM_PWR

S2_MEM_DATA_1

S2_MEM_45S

MEM_CAM_DQ<15..8>

S2_MEM_DATA1

S2_MEM_DQS1

MEM_CAM_DQS_N<1>

S2_MEM_DQS1

S2_MEM_85D

S2_MEM_PWR

PP0V675_MEM_CAM_VREFCA

MIPI_85D

MIPI_CLK_S2

MIPI_CLK_N

CLK_MIPI

S2_MEM_CMD S2_MEM_45S S2_MEM_CMD

MEM_CAM_BA<2>

MEM_CAM_BA<0>

S2_MEM_45SS2_MEM_CMD S2_MEM_CMD

MEM_CAM_CS_L

S2_MEM_CNTL S2_MEM_CTRL

S2_MEM_45S

MEM_CAM_CLK_N

S2_MEM_CLKS2_MEM_85DS2_MEM_CLK

S2_MEM_DATA_0

MEM_CAM_DQ<7..0>

S2_MEM_45S

S2_MEM_DATA0

MIPI_85D

MIPI_CLK_S2

CLK_MIPI

MIPI_CLK_P

MEM_CAM_WE_L

S2_MEM_CMD S2_MEM_45S S2_MEM_CMD

MEM_CAM_RAS_L

S2_MEM_CMD S2_MEM_45S

S2_MEM_CTRL

S2_MEM_45S

MEM_CAM_CKE

S2_MEM_CTRLS2_MEM_CNTL

MEM_CAM_CAS_L

S2_MEM_CTRL

S2_MEM_45SS2_MEM_CMD

MEM_CAM_ODT

S2_MEM_45S

S2_MEM_CTRL

MIPI_85D

MIPI_CLK_CONN_N

CLK_MIPI

S2_MEM_45SS2_MEM_CMD

MEM_CAM_BA<1>

S2_MEM_CMD

S2_MEM_PWR

PP0V675_CAM_VREF

S2_MEM_DATA1

MEM_CAM_DM<1>

S2_MEM_DATA_1

S2_MEM_45S

S2_MEM_A

S2_MEM_CMD

MEM_CAM_A<14..0>

S2_MEM_45S

S2_MEM_DATA_0

MEM_CAM_DM<0>

S2_MEM_DATA0

S2_MEM_85D

S2_MEM_DQS0

MEM_CAM_DQS_P<0>

S2_MEM_DQS0

MEM_CAM_DQS_N<0>

S2_MEM_85D

S2_MEM_DQS0

S2_MEM_PWR

PP0V675_MEM_CAM_VREFDQ

MIPI_85D

MIPI_CLK_CONN_P

CLK_MIPI

<SCH_NUM>

116 OF 121

72 OF 76

31 32

32 64

31 32

32

31 32

32

32 64

31 32

32

32 64

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SPACING

SMBus Charger Net Properties

SPACING

NET_TYPE

PHYSICAL

NET_TYPE

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

0.1 MM

*

=STANDARD =STANDARD=STANDARD

0.1 MM

=STANDARD

1TO1_DIFFPAIR

0.1 MM

*

2TO1_DIFFPAIR

0.2 MM

=STANDARD

0.1 MM

=STANDARD

0.1 MM

SMC Constraints

SYNC_MASTER=CONSTRAINTS

SYNC_DATE=09/25/2012

CHGR_CSO_P

2TO1_DIFFPAIR

SENSE_DIFFPAIR

CHGR_CSO_R_P

2TO1_DIFFPAIR

CHGR_CSO_N

SENSE_DIFFPAIR

2TO1_DIFFPAIR

SMBUS_SMC_2_S3_SDA

SMB

SMB_45S_R_50S

SMBUS_SMC_2_S3_SDA

SMB_45S_R_50S

SMB

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SDA SMBUS_SMC_5_G3_SCL

SMB_45S_R_50S

SMBUS_SMC_5_G3_SCL

SMB

SMBUS_SMC_3_SCL

SMB_45S_R_50S

SMBUS_SMC_3_SCL

SMB

SMB_45S_R_50S

SMBUS_SMC_5_G3_SDA

SMB

SMBUS_SMC_0_S0_SDA

SMB_45S_R_50S

SMB

SMBUS_SMC_0_S0_SCL

SMB_45S_R_50S

SMBUS_SMC_0_S0_SCL

SMB

SMBUS_SMC_1_S0_SCL

SMB

SMBUS_SMC_1_S0_SCL

SMB_45S_R_50S

SMB

SMB_45S_R_50S

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_1_S0_SDA

SMB

SMBUS_SMC_1_S0_SDA

SMB_45S_R_50S

CHGR_CSI_R_N

2TO1_DIFFPAIR

CHGR_CSI_P

SENSE_DIFFPAIR

CHGR_CSI_R_P

2TO1_DIFFPAIR

CHGR_CSI_N

2TO1_DIFFPAIR

SENSE_DIFFPAIR

CHGR_CSO_R_N

2TO1_DIFFPAIR

<SCH_NUM>

117 OF 121

73 OF 76

50

43 50

50

37 40 61 65

36 37 40 44 64

37 40 48 50 64

36 37 40 44 64

37 40 48 50 64

37 40 60

14 32 37 40 43 44 64 69

37 40 61 65

14 32 37 40 43 44 64 69

50

43 50

w w w . c h i n a f i x . c o m

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

J11/J13 Specific Net Properties

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

I348

I349

SYNC_DATE=12/07/2012

SYNC_MASTER=J41_MLB

Project Specific Constraints

AUDIO

*

=2:1_SPACING

?

GND_P2MM

*

LVDS*

GND

=45_OHM_SE

=1TO1_DIFFPAIR

*

SENSE_1TO1_45S

=45_OHM_SE

=1TO1_DIFFPAIR

=45_OHM_SE

=1TO1_DIFFPAIR

0.100 MM

=1TO1_DIFFPAIR

*

SENSE_1TO1_P2MM

0.200 MM

=1TO1_DIFFPAIR

=1TO1_DIFFPAIR =1TO1_DIFFPAIR

CPU_VCCSENSE

GND_P2MM

GND

*

GND_P2MM

*

SATA*

GND

0.20 MM

GND_P2MM

*

10000

0.300 MM

=1TO1_DIFFPAIR

*

=1TO1_DIFFPAIR

0.100 MM

SPKR_DIFFPAIR

=1TO1_DIFFPAIR

GND_P2MM

*

PCIE*

GND

THERM_1TO1_45S

=45_OHM_SE

=1TO1_DIFFPAIR

=45_OHM_SE

*

=45_OHM_SE

=1TO1_DIFFPAIR

GND

* ?

=STANDARD

SATA*

SB_POWER PWR_P2MM

*

PWR_P2MM

*

10000

0.20 MM

?

=2:1_SPACING

*

SENSE

GND

*

CPU_COMP GND_P2MM

USB*

GND_P2MM

*

GND

*

=2:1_SPACING

THERM

?

GND_P2MMCLK_PCIE

*

GND

SB_POWER PWR_P2MM

*

CLK_PCIE

SB_POWER PWR_P2MM

SATA*

*

ISNS_HS_GAIN_P

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

ISNS_HS_GAIN_N

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

ISNS_PANEL_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_PANEL_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

SENSE_DIFFPAIR

SENSE

ISNS_CPUDDR_P

SENSE_1TO1_P2MM

ISNS_P3V3S5_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_1TO1_45S

ISNS_3V3_S0_P

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

ISNS_1V05_S0_P

SENSE_DIFFPAIR

SENSE

ISNS_1V2_S3_P

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

ISNS_1V2_S3_N

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

ISNS_HS_OTHER_P

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

ISNS_HS_COMPUTING_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_P3V3_S0_N

SENSE_DIFFPAIR SENSE_1TO1_45S

ISNS_AIRPORT_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

ISNS_AIRPORT_P

SENSE

SENSE_DIFFPAIR

ISNS_SSD_N

SENSE_1TO1_45S

CPUVR_ISUM_R_N

SENSE

SENSE_1TO1_45S

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_P2MM

ISNS_CPUDDR_N

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

ISNS_3V3_S0_N

SENSE_1TO1_45S

SENSE

ISNS_CAMERA_P

SENSE_DIFFPAIR

SENSE

ISNS_CAMERA_N

SENSE_1TO1_45S

SENSE_DIFFPAIR

ISNS_P3V3S5_N

SENSE_1TO1_45S

SENSE

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

ISNS_P3V3_S0_P

SENSE_DIFFPAIR SENSE_1TO1_45S

ISNS_SSD_P

SENSE

CPUVR_ISNS1_P_R

SENSE_1TO1_P2MM

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

SENSE

CPUVR_ISNS2_N

SENSE_1TO1_45S

CPUVR_ISNS2_P

SENSE_DIFFPAIR

SENSE

THERM

THERM_1TO1_45SSENSE_DIFFPAIR

TBT_MLBBOT_THMSNS_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

TBTTHMSNS_D2_R_N

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

TBTTHMSNS_D2_R_P

TBTTHMSNS_D2_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_45S

CPUVR_ISNS1_N

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

SENSE

CPUVR_ISUM_R_P

SENSE_1TO1_45S

ISNS_BMON_GAIN_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_45S

ISNS_1V05_S0_N

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

ISNS_HS_COMPUTING_P

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

SENSE

CPUVR_ISNS1_P

SENSE_1TO1_45SSENSE_DIFFPAIR

SENSE

TBDTHMSNS_D2_N

SENSE_DIFFPAIR

SENSE

TBDTHMSNS_D2_P

SENSE_1TO1_45S

SENSE

SENSE_1TO1_45SSENSE_DIFFPAIR

CPUTHMSNS_D2_N

SENSE_DIFFPAIR

SENSE

CPUTHMSNS_D2_P

SENSE_1TO1_45S

THERM

THERM_1TO1_45SSENSE_DIFFPAIR

MLBBOT_THMSNS_D3_N

THERM

THERM_1TO1_45S

MLBBOT_THMSNS_D3_P

SENSE_DIFFPAIR

SENSE_1TO1_P2MM

SENSE_DIFFPAIR

CPUVCCIOS0_CS_N

SENSE

SENSE_1TO1_P2MM

CPUVCCIOS0_CS_P

SENSE_DIFFPAIR

THERM_1TO1_45S

THERM

TBTTHMSNS_D2_N

SENSE_DIFFPAIR

THERM_1TO1_45S

THERM

TBT_MLBBOT_THMSNS_N

SENSE_DIFFPAIR

INLET_THMSNS_D1_P

THERM

THERM_1TO1_45S

SENSE_DIFFPAIR

INLET_THMSNS_D1_N

THERM_1TO1_45S

THERM

SENSE_1TO1_45SSENSE_DIFFPAIR

ISNS_BMON_GAIN_N

SENSE

SENSE_1TO1_45S

ISNS_HS_OTHER_N

SENSE_DIFFPAIR

SENSE

CPUVR_ISNS1_N_R

SENSE_1TO1_P2MM

SENSE

SPKRAMP_INR_P

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

SPKRAMP_INR_N

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

MAX98300_R_P

1TO1_DIFFPAIR

AUDIO

SPKR_DIFFPAIR

AUDIO

SPKR_OUT

SPKRAMP_ROUT_P

MAX98300_R_N

1TO1_DIFFPAIR

AUDIO

SPKR_DIFFPAIR

AUDIO

SPKR_OUT

SPKRAMP_ROUT_N

PP3V3_S0

SB_POWER

PP3V3_S5

ISNS_LCDBKLT_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_45S

SENSE_DIFFPAIR

SENSE

ISNS_LCDBKLT_N

SENSE_1TO1_45S

GND

<SCH_NUM>

118 OF 121

74 OF 76

43 44

43

42

42 55

41 53

41

41 43

41

42

41

42

41

42 43

42 52

44

42 52

42

42 55

41 43

42 52

44

41

42 43

47 61 65

47

47 64

47

47 64

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65

8

11 13 15 16 17 18 28 29 34 42

57 58 59 60 62 64

41

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SD Card Net Properties

SPACING

I346

I347

I348

I349

I350

I351

I352

I353

I354

I355

I356

*

SD_45SE

=45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

Project Specific Constraints

SYNC_MASTER=CONSTRAINTS

SYNC_DATE=09/25/2012

SDCONN_DATA<0..3>

SD_45SE

SDDATA

SDCONN_CLK

SD_45SE

SDCLK

SD_45SE

SDCONN_WP SDCONN_CMD

SD_45SE

SPI

SD_SPI_CS_L

SD_45SE

SPI

SD_SPI_MOSI

SD_45SE

SPI

SD_SPI_MISO

SD_45SE

SDSCLK_CLK_25M_X1

CLK_25M_45S

SDCONN_DETECT_L

SD_45SE

SDCLK_CLK25M_X2_R

CLK_25M_45S

SPI

SD_45SE

SD_SPI_CLK

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

C

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REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

<RDAR://COMPONENT/508945> J43 HW EE SCHEMATIC | DVT

<RDAR://COMPONENT/508941> J43 HW EE SCHEMATIC | EVT

<RDAR://COMPONENT/508937> J43 HW EE SCHEMATIC | PROTO 1

<RDAR://COMPONENT/508934> J43 HW EE SCHEMATIC | PROTO 0

Change List:

Schematic Design Wiki - https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design

Page Allocations - <rdar://problem/11791318> 2012 Schematic Page Allocations

<rdar://component/497587> MobileMac HW | Schematic

Schematic Conventions - https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions

<rdar://component/497590> MobileMac HW | Investigation <rdar://component/497589> MobileMac HW | Architecture

afp://kismet.apple.com/Kismet-Projects/J41-J43

Kismet:

<rdar://component/497588> MobileMac HW | Layout

MobileMac HW Radar:

<rdar://component/497591> MobileMac HW | Task

Other Info:

<rdar://component/497585> MobileMac HW | New Bugs

Useful Wiki Links:

Reference

SYNC_MASTER=J41_MLB

SYNC_DATE=07/03/2012

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