Apple MACKBOOK J113 Schematic

TABLE_TABLEOFCONTENTS_ITEM

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

10/03/14

J113 MLB SCHEMATIC

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE

Schematic / PCB #’s

PRODUCT SAFETY REQUIREMENTS:

ALIASES RESOLVED

1 OF 76

<PART_DESCRIPTION>

<SCH_NUM>

<ECO_DESCRIPTION>

1 OF 121

J41_MLB

60

02/06/2013

45 Fan

J41_MLB

58

02/06/2013

44

Thermal Sensors

J41_MLB

56

03/28/2013

43

Debug Sensors 1

J41_MLB

55

03/28/2013

42

Voltage & Load Side Current Sensing

J41_MLB

54

03/28/2013

41

High Side Current Sensing

J41_MLB

53

02/06/2013

40

SMBus Connections

J41_MLB

52

02/06/2013

39

SMC Project Support

J41_MLB

51

02/06/2013

38

SMC Shared Support

J41_MLB

50

02/06/2013

37 SMC

J41_MLB

48

02/12/2013

36

IPD Connector

J41_MLB

46

02/07/2013

35

External A USB3 Connector

MASTER

45

10/11/2010

34

SD CONTROLLER (GL3219)

MASTER

44

07/01/2011

33

SD READER CONNECTOR

J41_MLB

40

03/20/2013

32

Camera 2 of 2

J41_MLB

39

04/02/2013

31

Camera 1 of 2

J41_MLB

37

04/09/2013

30

SSD Connector

J41_MLB

35

02/06/2013

29

Wireless Connector

J41_MLB

32

02/07/2013

28

Thunderbolt Connector A

J41_MLB

30

02/06/2013

27

TBT Power Support

J41_MLB

29

02/06/2013

26

Thunderbolt Host (2 of 2)

J41_MLB

28

02/06/2013

25

Thunderbolt Host (1 of 2)

J41_MLB

27

02/06/2013

24

LPDDR3 DRAM Termination

J41_MLB

26

02/06/2013

23

LPDDR3 DRAM Channel B (32-63)

J41_MLB

25

02/06/2013

22

LPDDR3 DRAM Channel B (0-31)

J41_MLB

24

02/06/2013

21

LPDDR3 DRAM Channel A (32-63)

J41_MLB

23

02/06/2013

20

LPDDR3 DRAM Channel A (0-31)

J41_MLB

22

02/12/2013

19

DDR3 VREF MARGINING

J41_MLB

20

02/15/2013

18

Project Chipset Support

J41_MLB

19

02/06/2013

17

Chipset Support

J41_MLB

18

02/06/2013

16

CPU/PCH Merged XDP

J41_MLB

16

04/02/2013

15

PCH GPIO/MISC/LPIO

J41_MLB

15

02/06/2013

14

PCH PCIe/USB/LPC/SPI/SMBus

J41_MLB

14

02/06/2013

13

PCH PM/PCI/GFX

J41_MLB

13

02/06/2013

12

PCH Audio/JTAG/SATA/CLK

J41_MLB

12

02/07/2013

11

PCH Decoupling

WILL_J43

10

01/08/2013

10

CPU Decoupling

J41_MLB

9

02/06/2013

9

CPU/PCH GROUNDS

J41_MLB

8

04/09/2013

8

CPU/PCH POWER

J41_MLB

7

02/06/2013

7

CPU DDR3/LPDDR3 Interfaces

J41_MLB

6

04/02/2013

6

CPU Misc/JTAG/CFG/RSVD

J41_MLB

5

02/06/2013

5

CPU GFX/NCTF/RSVD

MASTER

4

MASTER

4

PD PARTS

K21_MLB

3

11/16/2010

3

BOM Variants

J41_MLB

2

04/09/2013

2

BOM Configuration

Reference

76

07/03/2012

J41_MLB

121

Project Specific Constraints

75

09/25/2012

CONSTRAINTS

119

Project Specific Constraints

74

12/07/2012

J41_MLB

118

SMC Constraints

73

09/25/2012

CONSTRAINTS

117

Camera Constraints

72

01/30/2013

J41_MLB

116

Thunderbolt Constraints

71

09/25/2012

CONSTRAINTS

115

Memory Constraints

70

09/25/2012

CONSTRAINTS

114

PCH Constraints 2

69

12/14/2012

J41_MLB

113

PCH Constraints 1

68

11/13/2012

CLEAN_J43

112

CPU Constraints

67

09/25/2012

CONSTRAINTS

111

PCB Rule Definitions

66

10/24/2012

CONSTRAINTS

110

Project FCT/NC/Aliases

65

09/13/2012

J41_MLB

105

Func Test / No Test

64

02/01/2013

J41_MLB

104

Signal Aliases

63

08/30/2012

J41_MLB

102

Power Aliases

62

01/30/2013

J41_MLB

100

Left I/O (LIO) Connector

61

11/13/2012

CLEAN_J43

95

Internal DisplayPort Connector

60

02/06/2013

J41_MLB

83

Power Control

59

02/06/2013

J41_MLB

81

Power FETs

58

02/06/2013

J41_MLB

80

Misc Power Supplies

57

02/06/2013

J41_MLB

78

LCD/KBD Backlight Driver

56

02/06/2013

J41_MLB

77

1.05V S0 Power Supply

55

05/21/2013

J41_MLB

76

5V S4RS3 / 3.3V S5 Power Supply

54

09/17/2012

J41_MLB

75

LPDDR3 Supply

53

05/21/2013

J41_MLB

74

CPU VR12.5 VCC Power Stage

52

05/21/2013

J41_MLB

73

CPU VR12.6 VCC Regulator IC

51

04/09/2013

J41_MLB

72

PBus Supply & Battery Charger

50

05/21/2013

J41_MLB

71

DC-In & G3H Supply

49

02/06/2013

J41_MLB

70

Battery Connector

48

MASTER

69

Audio: Speaker Amp

47

04/26/2013

J41_MLB

64

Date

Page Sync

Contents

(.csa)

LPC+SPI Debug Connector

46

04/02/2013

J41_MLB

61

820-00165

PCBF,MLB,J43

CRITICAL

PCB

1

051-00385

SCH

CRITICAL

1

SCHEM,MLB,J43A

LAST_MODIFIED=Fri Oct 3 11:36:00 2014

TITLE=MLB

ABBREV=DRAWING

(.csa)

Sync

Date

Contents

Page

MASTER

1

MASTER

1

Table of Contents

w w w . c h i n a f i x . c o m

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

Module Parts

DRAM Parts

CFG 0

00

1 0

0 1

CPU DRAM CFG Chart

CFG 1

HYNIX

VENDOR

SAMSUNG

MICRON

0

1

CFG 2

1

0

1

0

1

0

1

CFG 3

RSVD

16GB

8GB

4GB

SIZE

ELPIDA

Current Sensor Configuration

CPU DRAM SPD Straps

Programmable Parts

Alternate Parts

BOM Groups

ALT PWR DIST SW

353S00133

353S2741

ALL

311S0508

311S00013

ALT SNGL BUFFER

ALL

311S0515

311S00014

ALT DUAL BUFFER

ALL

ALT 2-INPT AND

311S0450

311S00015

ALL

311S00008

311S0271

ALT AND GATE

ALL

311S00007

311S0426

ALT SNGL BUFFER

353S3812353S3814

ALT TBT PORT MUX

ALL

341S00153

IC,EFI ROM(V0108)), PROTO 0,J110/J113

1

BOOTROM:PROG

CRITICAL

U6100

341S00159

T29,EEPROM,FALCON RIDGE(V27.1), PROtO 0,J110/J113

CRITICAL

1

TBTROM:PROG

U2890

335S00007

IC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1

BOOTROM_NUM:BLANK

CRITICAL

1

U6100

335S00006

IC,SERIAL FLASH,64 MBIT 3V,WSON,QE=1

1

BOOTROM_MAC:BLANK

CRITICAL

U6100

IC,SMC12-B1,40MHZ/50DMIPS MCU,157BGA

338S1214

1

SMC:BLANK

U5000

CRITICAL

U2300,U2400,U2500,U2600

4

CRITICAL333S0791

IC,SDRAM,16GB,LPDDR3-1600,178P FBGA

DRAM_TYPE:MICRON_8GB

DRAM_TYPE:ELPIDA_16GB

333S0789

IC,SDRAM,25nm,32Gb,LPDDR3-1600,178P FBGA

CRITICAL

4

U2300,U2400,U2500,U2600

CRITICAL

4

DRAM_TYPE:MICRON_4GB

U2300,U2400,U2500,U2600

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

333S0793

333S0791

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

U2300,U2400,U2500,U2600

CRITICAL

4

DRAM_TYPE:ELPIDA_8GB

333S0793

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

CRITICAL

4

U2300,U2400,U2500,U2600

DRAM_TYPE:ELPIDA_4GB

MLB_DEBUG:PVT

BKLT:PROD,XDP,SAMCONN,ISNS:ENG,DBGLED,XDP_CONN

ALT STANDOFF W_O MYLAR

860-1328

ALL

860-3690

DRAM_TYPE:HYNIX_4GB

ALL

ALT STANDOFF W_O MYLAR

333S0787 333S0677

ALT STANDOFF W_O MYLAR

ALL

333S0785 333S0681

DRAM_TYPE:HYNIX_8GB

ALT STANDOFF W_O MYLAR

860-3428 860-1327

ALL

LABEL,TEXT,MLB,K21/K78

1

LABEL

825-7670

NEW_LABEL

LABEL,MLB,J41/J43

825-7987

1

870-5074 870-1938

ALT POGO PIN W_O CAP

ALL

107S0248107S0250

Cyntec alt to TFT

ALL

107S0255 107S0240

Cyntec alt to TFT

ALL

152S1804152S1876

TDK alt to Toko

ALL

376S0761

ALL

Renesas alt to Vishay

376S00014

SYNC_DATE=01/17/2013

SYNC_MASTER=J43_MLB

BOM Configuration

138S0638138S0841

ALL

Murata alt to Samsung

197S0544197S0542

NDK alt to TXC

ALL

377S0104377S0155

ALL

OnSemi alt to Infineon

Taiyo alt to Samsung

138S0638138S0681

ALL

197S0544197S0545

Epson alt to TXC

ALL

128S0220128S0398

Kemet alt to Sanyo

ALL

Kemet alt to Sanyo

128S0397 128S0325

128S0386

ALL

128S0284

Kemet alt to Sanyo

353S3452

Maxim alt to Microchip

ALL

353S1286

Diodes alt to Fairchild

376S0604376S1053

ALL

Diodes alt to ST Micro

ALL

371S0558371S0713

ALL

128S0376128S0371

Kemet alt to Sanyo

152S1757

Cyntec alt to NEC

ALL

152S1821

197S0343

ALL

NDK crystal alt to TXC

197S0480

107S0254 107S0241

ALL

Cyntec sense R alt to TFT

138S0648138S0703

Murata alt to Taiyo Yuden

ALL

152S1301152S0586

ALL

Dale/Vishay alt to Cyntec

372S0186

NXP alt to Diodes

372S0185

ALL

197S0478197S0479

200uW Epson alt to NDK

138S0660138S0684

Murata alt to Taiyo Yuden

ALL

376S1032 376S0855

Toshiba alt for Diodes dual

ALL

376S1089

ALL

NXP alt for Diodes single

376S1128

BKLT:PROD,SAMCONN,XDP,ISNS:PROD

MLB_DEBUG:PROD

XDP_CONN

MLB_DEVEL:PVT

MLB_DEVEL:ENG

ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENG

PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS,SSD_LPSR:S3

MLB_MISC

MLB_COMMON

ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:PVT,MLB_PROGPARTS

ALL

Epson crystal alt to TXC

197S0481 197S0343

376S0855

ALL

NXP alt for Diodes dual

376S1129

RAMCFG0:H,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:MICRON_8GB

DDR3:MICRON_8GB

DDR3:MICRON_16GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:MICRON_16GB

DDR3:HYNIX_16GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:HYNIX_16GB

DDR3:SAMSUNG_16GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:SAMSUNG_16GB

DDR3:ELPIDA_16GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:H,DRAM_TYPE:ELPIDA_16GB

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GB

DDR3:MICRON_4GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

DDR3:ELPIDA_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

DDR3:SAMSUNG_8GB

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

DDR3:ELPIDA_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

DDR3:SAMSUNG_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB

DDR3:HYNIX_8GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

DDR3:HYNIX_4GB

ISNS:PROD

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NO

ISNS:ENG

CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YES

4

CRITICAL

U2300,U2400,U2500,U2600

DRAM_TYPE:SAMSUNG_8GB

IC,SDRAM,23NM,16GB,LPDDR3-1600,178P FBGA

333S00003

U2300,U2400,U2500,U2600

CRITICAL

4

DRAM_TYPE:SAMSUNG_4GB

IC,SDRAM,23NM,8GB,LPDDR3-1600,178P FBGA

333S00001

IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA

U2300,U2400,U2500,U2600

CRITICAL

4

DRAM_TYPE:HYNIX_4GB

333S0677

376S1194 CRITICAL

Q7310,Q7320

2

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

VCORE_FET:VSHY

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

376S1193

Q7311,Q7321

CRITICAL

2

VCORE_FET:VSHY

900-0090

SOLDERPASTE

1

CRITICAL

2

CRITICAL

Q7311,Q7321

VCORE_FET:REN

376S00037

MOSFET,N-CH,30V,64A,3.5M,8P 3.3X3.3 DFN

MOSFET,N-CH,30V,52A,5.9M,8P 3.3X3.3 DFN

376S00036

CRITICAL

Q7310,Q7320

2

VCORE_FET:REN

946-5477 CRITICALGLUE

1

UV GLUE,MLB,J41_J43

U3900

CRITICAL

1

338S1264

IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA

607-6811

1

J6955

CRITICAL

ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99

J113_MLB

1

CRITICAL

U0500

CPU:1.6GHZ

BDW,QGHB,D0,1.6,15W,2+2,0.6,4M,B1168

337S00073

1

CRITICAL

U0500

337S00029

BDW,QGH9,D0,1.8,15W,2+2,0.7,4M,B1168

CPU:2.1GHZ

4

CRITICAL

DRAM_TYPE:HYNIX_8GB

U2300,U2400,U2500,U2600

333S0681

IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA

XDP,SAMCONN

MLB_DEBUG:ENG

EEPROM,4MBIT,SPI,50MHZ,1.8V,USON8

335S0915

U2890

1

CRITICAL

TBTROM:BLANK

338S00069

IC,TBT,FR-2C,288,12x12 ,FC-CSP,TRAY

CRITICAL

U2800

1

<SCH_NUM>

2 OF 121

2 OF 76

w w w . c h i n a f i x . c o m

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM Variants

Programmable Parts

BOM Groups

Alternate Parts

Sub-BOMs

Module Parts

338S1246

U4500

1

CRITICAL

IC,GL3219,USB3 SD CARD READER,46P,LQFN

685-00048

VCORE FET,VSHY,X433

VCORE_FET:VSHY

685-00047

VCORE FET,REN,X433

VCORE_FET:REN

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_4GB

639-00641

PCBA,MLB,BETTER,EL-4GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_16GB

PCBA,MLB,BETTER,MI-16GB,X433

639-00640

MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_8GB

639-00639

PCBA,MLB,BETTER,MI-8GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:MICRON_4GB

PCBA,MLB,BETTER,MI-4GB,X433

639-00638

MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_8GB,ALTERNATE

639-00637

PCBA,MLB,BETTER,SM-8GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:SAMSUNG_4GB,ALTERNATE

PCBA,MLB,BETTER,SM-4GB,X433

639-00636

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_16GB

639-00635

PCBA,MLB,BETTER,HY-16GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_8GB,ALTERNATE

639-00634

PCBA,MLB,BETTER,HY-8GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:HYNIX_4GB,ALTERNATE

PCBA,MLB,BETTER,HY-4GB,X433

639-00633

639-00632

PCBA,MLB,BEST,EL-8GB,X433

MLB_CMNPTS,CPU:2.1GHZ,DDR3:ELPIDA_8GB

MLB_CMNPTS,CPU:2.1GHZ,DDR3:ELPIDA_4GB

PCBA,MLB,BEST,EL-4GB,X433

639-00631

639-00630

PCBA,MLB,BEST,MI-16GB,X433

MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_16GB

MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_8GB

PCBA,MLB,BEST,MI-8GB,X433

639-00629

639-00628

PCBA,MLB,BEST,MI-4GB,X433

MLB_CMNPTS,CPU:2.1GHZ,DDR3:MICRON_4GB

PCBA,MLB,BEST,SM-8GB,X433

639-00627

MLB_CMNPTS,CPU:2.1GHZ,DDR3:SAMSUNG_8GB,ALTERNATE

MLB_CMNPTS,CPU:2.1GHZ,DDR3:SAMSUNG_4GB,ALTERNATE

639-00626

PCBA,MLB,BEST,SM-4GB,X433

639-00624

MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_8GB,ALTERNATE

PCBA,MLB,BEST,HY-8GB,X433

PCBA,MLB,BEST,HY-4GB,X430

MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_4GB,ALTERNATE

639-00623

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

BOM Variants

333S0700333S0704

ALL

Elpida CAM DRAM alt to Hynix

685-00048685-00047

ALL

Renesas alt to Vishay

CMNPTS

1

MLB_CMNPTS

CRITICAL

685-00046

CMN PTS,PCBA,MLB,J113

VCOREFETS

VCORE_FETS

CRITICAL

1

685-00048

VCORE FET,VSHY,J113

MLB_PROGPARTS

BOOTROM:PROG,SMC:PROG,TBTROM:PROG

639-00625

PCBA,MLB,BEST,HY-16GB,X433

MLB_CMNPTS,CPU:2.1GHZ,DDR3:HYNIX_16GB

SMC:PROG

1

CRITICAL

U5000

341S00148

IC,SMC-B1,EXT(Vxxxx),PROTO 0,J113

685-00046

CMN PTS,PCBA,MLB,X433

MLB_COMMON,J113_MLB

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_8GB

639-00642

PCBA,MLB,BETTER,EL-8GB,X433

MLB_CMNPTS,CPU:1.6GHZ,DDR3:ELPIDA_16GB

PCBA,MLB,BETTER,EL-16GB,X433

639-00697

<SCH_NUM>

3 OF 121

3 OF 76

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PD Module Parts

EMI I/O Pogo Pins

USB/SD Card Pogo

Can Slots

2x TBT pin diodes

2x MDP Connector

2x USB Connector

2x TBT chip

DisplayPort Pogo

870-1938

860-1327

Fan Boss

860-1327

X21 Boss

870-1938

SSD Boss

860-1327

4x 860-1327

Plated Board Slot

CPU Heat Sink Mounting Bosses

1

ZS0406

SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

1

Z0414

STDOFF-4.5OD1.9H-SM

1

Z0405

STDOFF-4.5OD1.8H-SM

1

ZS0405

POGO-2.0OD-3.6H-K86-K87

CRITICAL

SM

1

SL0402

TH-NSP

SL-1.1X0.4-1.4X0.7

1

SL0406

TH-NSP

SL-1.1X0.4-1.4X0.7

1

SL0401

TH-NSP

SL-1.1X0.4-1.4X0.7

1

SL0403

SL-1.1X0.4-1.4X0.7

TH-NSP

1

SL0407

SL-1.1X0.45-1.4X0.75

TH-NSP

1

SL0408

SL-1.1X0.4-1.4X0.7

TH-NSP

1

SL0400

TH-NSP

SL-2.3X3.9-2.9X4.5

1

SL0405

TH-NSP

SL-1.1X0.45-1.4X0.75

1

SL0404

TH-NSP

SL-1.1X0.4-1.4X0.7

1

Z0410

STDOFF-4.5OD1.52H-SM

1

Z0412

STDOFF-4.5OD1.52H-SM

1

Z0413

STDOFF-4.5OD1.52H-SM

1

Z0411

STDOFF-4.5OD1.52H-SM

1

Z0415

STDOFF-4.5OD1.9H-SM

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PD PARTS

TBTTOPSIDE_2P_FENCE

CAN,TOPSIDE,ALT,J41/J43

806-5107 CRITICAL

1

806-5108

TBTTOPSIDE_2P_COVER

CAN,TOPSIDE,COVER,ALT,J41/J43

CRITICAL

1

806-3142

CAN,TBT,J11/J13

TBTFENCE CRITICAL

1

806-3215 TBTCOVER

CAN,COVER,TBT,J11/J13

CRITICAL

1

MDPCAN

CAN,MDP,J11/J13

806-3216 CRITICAL

1

USBCAN

SHLD,USB,MLB,J11/J13

806-3083 CRITICAL

1

<SCH_NUM>

4 OF 121

4 OF 76

w w w . c h i n a f i x . c o m

OUT

OUT OUT OUT OUT

BI BI

DDI

EDP

SYM 1 OF 19

EDP_TXN0

EDP_TXP1

EDP_TXN1

EDP_TXP0

DDI1_TXP2

DDI1_TXN2

DDI2_TXP3

DDI2_TXN3

DDI2_TXP2

DDI2_TXN2

DDI2_TXP1

DDI2_TXN1

DDI2_TXP0

DDI1_TXP1

DDI1_TXN1

DDI1_TXP0

DDI1_TXN0

DDI2_TXN0

DDI1_TXP3

DDI1_TXN3

EDP_RCOMP

EDP_DISP_UTIL

EDP_AUXN EDP_AUXP

EDP_TXP3

EDP_TXN3

EDP_TXP2

EDP_TXN2

SYM 17 OF 19

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF

SPARE

SYM 18 OF 19

RSVD

RSVD RSVD

RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

TP

NC NC

NCNC NCNC NCNC

NCNC NCNC NCNC NC NC NC NC

OUT

OUT OUT OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Other corner test signals connected in

MCP Daisy-Chain Strategy:

Each corner of CPU has two testpoints.

NO_TESTNO_TEST

daisy-chain fashion. Continuity should exist between both TP’s on each corner.

eDP Port Assignment:

Internal panel

DDI Port Assignments:

TBT Sink 0

TBT Sink 1 (MUXed with HDMI if necessary)

18 25 67

60 67

64

60 67

B49

C46

B47

B46

A49

C47

A47

C45

D20 A43

B45

A45

B53

B50

B54

C50

A53

C49

C53

C51

B57

A55

C58

C55

A57

B55

B58

C54

U0500

BGA

OMIT_TABLE

CRITICAL

2C+GT2

BROADWELL-ULT

C2

C1

B63

B62

B61

B3

B2

AY62

AY61

AY60

AY3

AY2

AW63

AW62

AW61

AW3

AW2

AW1

AV1

A62

A61

A60

A4

A3

U0500

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

U10

T23

R23

N23

J21

H22

F22

D15

AY14

AW14

AV44

AU44

AU15

AU10

AT2

AP7

AM11

AL1

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

1

TP0531

TP-P6

1

TP0500

TP-P6

1

TP0510

TP-P6

1

TP0501

TP-P6

1

TP0511

TP-P6

1

TP0520

TP-P6

1

TP0521

TP-P6

1

TP0530

TP-P6

2

1

R0530

24.9

1%

MF 201

1/20W

25 67

18 25 67

CPU GFX/NCTF/RSVD

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

TRUE

MCP_DC_A3_B3

MCP_DC_A60

MCP_DC_A4

MCP_DC_A62

MCP_DC_A61_B61

TRUE

MCP_DC_AV1 MCP_DC_AW1 MCP_DC_AW2_AY2

TRUE

MCP_DC_AW61_AY61

TRUE

MCP_DC_AW3_AY3

MCP_DC_AW62_AY62

TRUE

MCP_DC_AW63

MCP_DC_B2

TRUE

MCP_DC_AW62_AY62

MCP_DC_A61_B61

TRUE

MCP_DC_A3_B3

TRUE

MCP_DC_B62_B63

TRUE

MCP_DC_C1_C2

TRUE

MCP_DC_AW61_AY61

MCP_DC_AY60

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW2_AY2

TRUE

DP_INT_ML_C_N<0>

NC_INT_ML_CP<1>

NC_INT_ML_CN<1>

DP_INT_ML_C_P<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

MCP_EDP_RCOMP TP_EDP_DISP_UTIL

DP_INT_AUXCH_C_N DP_INT_AUXCH_C_P

NC_INT_ML_CP<3>

NC_INT_ML_CN<3>

NC_INT_ML_CP<2>

NC_INT_ML_CN<2>

PPVCOMP_S0_CPU

5 OF 76

<SCH_NUM>

5 OF 121

5

8

w w w . c h i n a f i x . c o m

BI BI

BI

NC NC

NC

SYM 2 OF 19

MISC

THERMAL

JTAG

DDR3

PWR

SM_PG_CNTL1

SM_DRAMRST*

SM_RCOMP1 SM_RCOMP2

SM_RCOMP0

PROCHOT*

PROCPWRGD

PECI

CATERR*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

PROC_TDO

PROC_TDI

PROC_TRST*

PROC_TMS

PROC_TCK

PREQ*

PRDY*

PROC_DETECT*

RESERVED

SYM 19 OF 19

VSS VSS

RSVD

CFG_RCOMP

RSVD

RSVD RSVD

TD_IREF

CFG0 CFG1

CFG5

CFG4

CFG3

CFG2

CFG6

CFG10

CFG9

CFG8

CFG7

CFG11

CFG15

CFG14

CFG13

CFG12

CFG18

CFG16

CFG17 CFG19

RSVD RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

PROC_OPI_COMP

RSVD RSVD

RSVD_B43

BI

OUT

NC

BI

OUT

IN

OUT

NC NC

NC NC NC

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

(IPU)

(IPU) (IPU)

(IPU)

(IPU) (IPU)

(IPU)

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

(IPU)

(IPD)

(IPU)

These can be placed close to J1800 and are only for debug access

issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid

CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID

2

1

R0640

NOSTUFF

1K

5%

201

1/20W

MF

2

1

R0639

HSW_PRE_ES2

1K

5%

201

1/20W MF

2

1

R0638

MF

1/20W

201

5%

1K

NOSTUFF

2

1

R0631

MF

1/20W

201

5%

1K

NOSTUFF

2

1

R0630

NOSTUFF

1K

5%

201

1/20W MF

6

16 67

6

16 67

16 64 67

16 67

6

16 67

6

16 67

6

16 67

6

16 67

16

AU61

AV60

AU60

AV61

AV15

C61

K63

E59

E61

F62

F63

E60

D61

K62

J62

N62

K61

J61

K60

H63

K59

H62

H61

H60

J60

U0500

BROADWELL-ULT

2C+GT2

BGA

OMIT_TABLE

CRITICAL

P22 N21

B12

Y22

W23

L60

C63 C62

B51

AV63 AU63

A51

R20

P20

N60

J20 H18

E1

D58

D1

B43

AV62

A5

AY15

V63

V61

V62

Y60

Y61

Y62

AA60

AA63

AC63

U62

U63

AA61

AA62

T60

T61

T62

T63

U60

V60

AC62

AC60

U0500

CRITICAL

OMIT_TABLE

BROADWELL-ULT

2C+GT2

BGA

37 38 51 67

2

1

R0610

5%

1/20W

MF

201

62

2 1

R0611

201

5%

MF

56

1/20W

38 67

37 67

2

1

R0620

PLACE_NEAR=U0500.C61:12.7mm

201

MF

1/20W

5%

10K

16 67

16 64 67

12 16 64 67

16 64 67

2

1

R0652

MF

1/20W

201

100

1%

PLACE_NEAR=U0500.AU61:12.7mm

2

1

R0651

MF

1/20W

201

1%

PLACE_NEAR=U0500.AV60:12.7mm

121

2

1

R0650

1%

200

201

1/20W

MF

PLACE_NEAR=U0500.AU60:12.7mm

18

17

2

1

R0680

1%

1/20W

201

MF

49.9

2

1

R0690

201

MF

1/20W

1%

49.9

2

1

R0685

1/20W MF 201

1%

8.25K

2

1

R0634

1K

5%

201

1/20W MF

EDP

SYNC_DATE=09/13/2012SYNC_MASTER=WILL_J43

CPU Misc/JTAG/CFG/RSVD

CPU_CFG_RCOMP

PCH_TD_IREF

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<5>

CPU_CFG<4>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<6>

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<11>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<12>

CPU_CFG<18>

CPU_CFG<16>

CPU_CFG<17> CPU_CFG<19>

TP_MCP_RSVD_AV63 TP_MCP_RSVD_AU63

TP_MCP_RSVD_C63 TP_MCP_RSVD_C62

TP_MCP_RSVD_A51 TP_MCP_RSVD_B51

TP_MCP_RSVD_L60

CPU_OPI_RCOMP

CPU_MEMVTT_PWR_EN_LSVDDQ

TP_CPU_MEM_RESET_L

CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>

CPU_SM_RCOMP<0>

CPU_PROCHOT_R_L

CPU_PWRGD

CPU_PECI

CPU_CATERR_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPUPCH_TRST_L

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_PREQ_L

XDP_CPU_PRDY_L

CPU_CFG<1>

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

CPU_CFG<0>

CPU_PROCHOT_L

CPU_CFG<4>

PP1V05_S0

6 OF 76

6 OF 121

<SCH_NUM>

67

6

16 67

6

16 67

6

16 67

6

16 67

6

16 67

6

16 67

8

11 15 16 17 38 42 51 55 58

59 62 64

w w w . c h i n a f i x . c o m

BI BI

BI

BI BI BI

BI BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

BI

BI BI BI

BI

OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI BI BI

SYM 3 OF 19

MEMORY CHANNEL A

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ55 SA_DQ56

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ45 SA_DQ46

SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ40 SA_DQ41

SA_DQ39

SA_DQ37 SA_DQ38

SA_DQ34

SA_DQ36

SA_DQ32 SA_DQ33

SA_DQ29 SA_DQ30 SA_DQ31

SA_DQ27 SA_DQ28

SA_DQ24 SA_DQ25

SA_DQ22 SA_DQ23

SA_DQ21

SA_DQ19 SA_DQ20

SA_DQ17 SA_DQ18

SA_DQ16

SA_DQ14 SA_DQ15

SA_DQ11

SA_DQ13

SA_DQ10

SA_DQ9

SA_DQ7 SA_DQ8

SA_DQ6

SA_DQ4 SA_DQ5

SA_DQ3

SA_DQ1

SA_DQ0

SA_CLK1*

SA_CLK0

SA_CLK0*

SA_DQ12

SM_VREF_DQ1

SM_VREF_CA

SM_VREF_DQ0

SA_DQ35

SA_DQ26

SA_DQ2

SA_CLK1

SA_CS0* SA_CS1*

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0

SA_MA2

SA_MA1

SA_MA3 SA_MA4 SA_MA5

SA_MA7

SA_MA6

SA_MA8

SA_MA10

SA_MA9

SA_MA12

SA_MA11

SA_MA13 SA_MA14 SA_MA15

SA_BA2

SA_BA0 SA_BA1

SA_DQSP0

SA_DQSP2

SA_DQSP1

SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SA_DQSN1

SA_DQSN0

SA_DQSN2

SA_DQSN4

SA_DQSN3

SA_DQSN5 SA_DQSN6 SA_DQSN7

SYM 4 OF 19

MEMORY CHANNEL B

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5

SB_CKE0

SB_DQ6

SB_CKE1

SB_DQ7

SB_CKE2

SB_DQ8

SB_CKE3 SB_DQ9 SB_DQ10 SB_CS0* SB_DQ11 SB_CS1* SB_DQ12 SB_DQ13 SB_ODT0 SB_DQ14 SB_DQ15 SB_RAS* SB_DQ16

SB_WE* SB_DQ17 SB_CAS* SB_DQ18 SB_DQ19

SB_BA0 SB_DQ20

SB_BA1 SB_DQ21

SB_BA2 SB_DQ22 SB_DQ23

SB_MA0 SB_DQ24

SB_MA1 SB_DQ25

SB_MA2 SB_DQ26

SB_MA3 SB_DQ27

SB_MA4 SB_DQ28

SB_MA5 SB_DQ29

SB_MA6 SB_DQ30

SB_MA7 SB_DQ31

SB_MA8 SB_DQ32

SB_MA9 SB_DQ33 SB_MA10 SB_DQ34 SB_MA11 SB_DQ35 SB_MA12

SB_MA13 SB_DQ37 SB_MA14 SB_DQ38 SB_MA15 SB_DQ39 SB_DQ40

SB_DQSN0

SB_DQ41

SB_DQSN1

SB_DQ42

SB_DQSN2

SB_DQ43

SB_DQSN3

SB_DQ44

SB_DQSN4

SB_DQ45

SB_DQSN5

SB_DQ46

SB_DQSN6

SB_DQ47

SB_DQSN7 SB_DQ48 SB_DQ49

SB_DQSP0 SB_DQ50

SB_DQSP1 SB_DQ51

SB_DQSP2 SB_DQ52

SB_DQSP3 SB_DQ53

SB_DQSP4 SB_DQ54

SB_DQSP5 SB_DQ55

SB_DQSP6 SB_DQ56

SB_DQSP7 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_DQ36

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE

12

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CAA3

CAA1

CAB7 CAA7

CAA6 CAB0

CAA9

CAA8

CAA5

CAB9

CAB8 CAB5

RSVD1

RSVD2

CAA0

CAA2

CAA4

CAB3

CAB2 CAB1

CAB4 CAB6

LPDDR3

CAA5

CAB9

CAB8 CAB5

CAB3

CAB2 CAB1

CAB4 CAB6

LPDDR3

CAA3

CAA1

CAB7 CAA7

CAA6 CAB0

CAA9

CAA8

CAA0

CAA2

CAA4

RSVD3

RSVD4

63 70

21 63 70

63 70

21 63 70

63 70

63

20 21 24 63 70

20 21 24 70

20 24 70

21 24 70

20 24 70

63

21 24 63 70

63

20 24 63 70

63

63 70

21 63 70

63 70

21 24 70

19

22 24 70

23 24 70

22 24 70

23 24 70

22 23 24 70

22 23 24 63 70

63

23 24 63 70

63

22 24 63 70

63

63 70

23 63 70

63 70

23 63 70

63 70

23 63 70

63 70

AP51

AR51

AP49

AW34

AY34

AP32

AU40

AY39

AW39

AV40

AR36

AU39

AP36

AR38

AU42

AV42

AR35

AU41

AW41

AP35

AY37

AU36

AL49

AL42

AW53

AW57

AN55

AN58

AN61

AJ62

AL48

AL43

AV53

AV57

AM55

AM58

AN62

AJ61

AM62

AM63

AK60

AK51

AM51

AK48

AM48

AK61

AK49

AM49

AK46

AM46

AM42

AM40

AK43

AK45

AM45

AM43

AH60

AK42

AK40

AU52

AV52

AU54

AV54

AW52

AY52

AW54

AY54

AH61

AU56

AV56

AU58

AV58

AW56

AY56

AW58

AY58

AN54

AR54

AK62

AK55

AL55

AK54

AM54

AR55

AP55

AN57

AR57

AK58

AL58

AK63

AK57

AM57

AR58

AP58

AP60

AP61

AM60

AM61

AP62

AP63

AH62

AH63

AR32

AP33

AW36 AY36

AU37 AV37

AY43

AY42

AW43

AU43

AU34

AY41

AV35

AU35

U0500

BGA

2C+GT2

BROADWELL-ULT

OMIT_TABLE

CRITICAL

AK35

AM35

AL32

AU46

AY47

AY46

AW46

AP45

AR45

AR42

AP42

AP46

AR46

AK33

AU47

AV47

AK36

AR40

AP40

AM18

AM21

AW18

AV22

AM25

AM28

AW26

AV30

AN18

AN21

AV18

AW22

AN25

AN28

AV26

AW30

AW27

AY27

AU29

AP18

AR18

AM20

AK20

AV29

AL18

AK18

AR20

AN20

AK22

AK21

AP21

AN22

AM22

AL21

AU31

AR22

AR21

AU17

AV17

AU19

AV19

AW17

AY17

AW19

AY19

AV31

AU21

AV21

AU23

AV23

AW21

AY21

AW23

AY23

AL25

AK25

AW29

AM26

AK26

AP25

AR25

AR26

AN26

AP28

AR28

AN29

AR29

AY29

AK28

AL28

AK29

AM29

AU25

AV25

AU27

AV27

AW25

AY25

AW31

AY31

AK32

AM32

AV50

AW49

AU50

AY49

AK38 AL38

AM38 AN38

AM33

AU49

AM36

AL35

U0500

BGA

OMIT_TABLE

CRITICAL

BROADWELL-ULT

2C+GT2

CPU DDR3/LPDDR3 Interfaces

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<55> MEM_A_DQ<56>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<45> MEM_A_DQ<46>

MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44>

MEM_A_DQ<40> MEM_A_DQ<41>

MEM_A_DQ<39>

MEM_A_DQ<37> MEM_A_DQ<38>

MEM_A_DQ<34>

MEM_A_DQ<36>

MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31>

MEM_A_DQ<27> MEM_A_DQ<28>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<22> MEM_A_DQ<23>

MEM_A_DQ<21>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<17> MEM_A_DQ<18>

MEM_A_DQ<16>

MEM_A_DQ<14> MEM_A_DQ<15>

MEM_A_DQ<11>

MEM_A_DQ<13>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<7> MEM_A_DQ<8>

MEM_A_DQ<6>

MEM_A_DQ<4> MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_DQ<12>

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

CPU_DIMMA_VREFDQ

MEM_A_DQ<35>

MEM_A_DQ<26>

MEM_A_DQ<2>

MEM_A_CLK_P<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_CKE<0> MEM_A_CKE<1> MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_ODT<0>

=MEM_A_RAS_L =MEM_A_WE_L =MEM_A_CAS_L

=MEM_A_A<0>

=MEM_A_A<2>

=MEM_A_A<1>

TP_LPDDR3_RSVD1 TP_LPDDR3_RSVD2 =MEM_A_A<5>

=MEM_A_A<7>

=MEM_A_A<6>

=MEM_A_A<8>

=MEM_A_A<10>

=MEM_A_A<9>

MEM_A_CAA<6>

=MEM_A_A<11>

=MEM_A_A<13> =MEM_A_A<14> =MEM_A_A<15>

=MEM_A_BA<2>

=MEM_A_BA<0> MEM_A_CAB<6>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_DQ<36>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQS_P<7>

MEM_B_DQ<56>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQS_P<5>

MEM_B_DQ<54>

MEM_B_DQS_P<4>

MEM_B_DQ<53>

MEM_B_DQS_P<3>

MEM_B_DQ<52>

MEM_B_DQS_P<2>

MEM_B_DQ<51>

MEM_B_DQS_P<1>

MEM_B_DQ<50>

MEM_B_DQS_P<0>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQS_N<7>

MEM_B_DQ<47>

MEM_B_DQS_N<6>

MEM_B_DQ<46>

MEM_B_DQS_N<5>

MEM_B_DQ<45>

MEM_B_DQS_N<4>

MEM_B_DQ<44>

MEM_B_DQS_N<3>

MEM_B_DQ<43>

MEM_B_DQS_N<2>

MEM_B_DQ<42>

MEM_B_DQS_N<1>

MEM_B_DQ<41>

MEM_B_DQS_N<0>

MEM_B_DQ<40>

MEM_B_DQ<39>

=MEM_B_A<15>MEM_B_DQ<38>

=MEM_B_A<14>MEM_B_DQ<37>

=MEM_B_A<13>

MEM_B_CAA<6>MEM_B_DQ<35>

=MEM_B_A<11>MEM_B_DQ<34>

=MEM_B_A<10>MEM_B_DQ<33>

=MEM_B_A<9>

MEM_B_DQ<32>

=MEM_B_A<8>

MEM_B_DQ<31>

=MEM_B_A<7>

MEM_B_DQ<30>

=MEM_B_A<6>

MEM_B_DQ<29>

=MEM_B_A<5>

MEM_B_DQ<28>

TP_LPDDR3_RSVD4

MEM_B_DQ<27>

TP_LPDDR3_RSVD3

MEM_B_DQ<26>

=MEM_B_A<2>

MEM_B_DQ<25>

=MEM_B_A<1>

MEM_B_DQ<24>

=MEM_B_A<0>

MEM_B_DQ<23>

MEM_B_DQ<22>

=MEM_B_BA<2>MEM_B_DQ<21>

MEM_B_CAB<6>MEM_B_DQ<20>

=MEM_B_BA<0>MEM_B_DQ<19>

MEM_B_DQ<18>

=MEM_B_CAS_LMEM_B_DQ<17>

=MEM_B_WE_L

MEM_B_DQ<16>

=MEM_B_RAS_LMEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_ODT<0>MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_CS_L<1>

MEM_B_DQ<11>

MEM_B_CS_L<0>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_CKE<3>

MEM_B_DQ<8>

MEM_B_CKE<2>

MEM_B_DQ<7>

MEM_B_CKE<1>

MEM_B_DQ<6>

MEM_B_CKE<0>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

7 OF 76

7 OF 121

<SCH_NUM>

w w w . c h i n a f i x . c o m

OUT

IN

NC NC

NC

BI

NC NC

IN OUT IN

NC NC NC

NC

OUT

NC

NC NC

NC

NC NC NC

IN

NC

SUS OSCILLATOR

SERIAL IO

THERMAL SENSOR

SYM 13 OF 19

USB2

LPT LP POWER

CORE

SPI RTC

HSIO

OPI

USB3

AZALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

ICC

VCCHSIO VCCHSIO VCCHSIO

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCDSW3_3

VCCCLK

VCCACLKPLL

DCPSUS4

VCCRTC

DCPRTC

VCCSPI

VCCASW

VCC1P05 VCC1P05

VCC1P05

DCPSUSBYP DCPSUSBYP

VCCASW VCCASW VCCASW

DCPSUS1

VCCTS1_5

VCCSDIO

RSVD

RSVD RSVD RSVD

VCCAPLL

VCC1_05 VCC1_05

VCC3_3

VCCCLK VCCCLK

VCCSUS3_3

VCCSUS3_3 VCCSUS3_3

VCCSUS3_3

HSW ULT POWER

SYM 12 OF 19

VCC

VCCST

RSVD

RSVD RSVD

RSVD

RSVD_TP

VSS

PWR_DEBUG*

VSS

VCC_SENSE

RSVD

VCC RSVD

VDDQ VDDQ

VDDQ

RSVD

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC VCC VCC

VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VCC VCC

VCC VCC VCC

VCC VCC

VCC

VDDQ

VCCIOA_OUT RSVD RSVD

VIDALERT*

RSVD

VIDSOUT

VIDSCLK

VR_EN

VCCST_PWRGD

VR_READY

VCCIO_OUT

RSVD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE

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SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

114mA Max

Max load: 300mA

42mA Max

17mA Max

3mA Max

31mA Max

Powered in DeepSx

11mA Max

18mA Max

???mA Max

32A Max

1.4A Max (DDR3: 1.5-1.35V)

1.1A Max (LPDDR3: 1.2V)

213mA Max[1]3.3mA Max[1]

1mA Max[1]

40mA Max[1]

473mA Max[1]

185mA Max[1]

29mA Max[1]

0.3mA Max[1]

59mA Max[1]

41mA Max

WF: RSVD on Sawtooth Peak rev 1.0

1838mA Max

57mA Max

VCCCLK: 200mA Max

1499mA Max[1]

VCCCLK: 200mA Max

Max load: 300mA

R0802.2:

NOTE: Aliases not used on CPU supply outputs to avoid any extraneous connections.

R0800.2:

R0810.2:

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0. Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.

2

1

R0802

PLACE_NEAR=U0500.L63:2.54mm

1/20W

1%

130

MF 201

51 67

16

2

1

R0860

1/20W

100

PLACE_NEAR=U0500.C50:50.8mm

MF

201

5%

51 67

16 17

17 51

51 67

2

1

C0899

BYPASS=R0899:U0500:2.54mm

402

CERM

1UF

10%

6.3V

21

R0899

1%

MF-LF

5.11

PLACE_NEAR=U0500.AG19:2.54mm

1/20W

201

51 67

2

1

C0895

0.1UF

CERM 402

10V

20%

BYPASS=U0500.AE7:6.35mm

2

1

C0892

402

CERM

10V

20%

0.1UF

BYPASS=U0500.AG10:6.35mm

2

1

C0891

BYPASS=U0500.AG10:6.35mm

0.1UF

402

CERM

10V

20%

2

1

C0890

BYPASS=U0500.AG10:6.35mm

1UF

402

CERM

6.3V

10%

B18

J15

AH11

AE21

AE20

AC9 AA9

Y8

U8 T9

B11

AG10

M9

L10

K9

AH14

AH10

T21

R21

K19

J18

J17

AG8

AG14 AG13

AF9

AE9

W21

AA21

A20

W9

V8

K16

K14

P9

N8

J11

H15

H11

AG17

AG16

AF22

AE8

Y20

V21

M20

K18

AC20

AG20

AG19

AB8

J13

AH13

AD8

AD10

AE7

U0500

BGA

CRITICAL

OMIT_TABLE

BROADWELL-ULT

2C+GT2

P62

D63

C59

F60

L63

N63

L62

AY50

AY44

AY40

AY35

AR48

AP43

AN33

AJ37

AJ33

AJ31

AH26

B59

AE23

AE22

AC22

E20

A59

W57

U57

E63

P57

M57

M23

L22

K57

K23

J23

H23

G57

G55

G53

G51

G49

G47

G45

G43

G41

G39

G37

G35

G33

G31

G29

G27

G25

G23

F56

F52

F48

F44

F40

F36

F32

F28

F24

E57

E55

E53

E51

E49

E47

E45

E43

E41

E39

E37

E35

E33

E31

E29

E27

E25

E23

C56

C52

C48

C44

C40

C36

C32

C28

C24

AG57

AD57

AB57

F59

V59

U59

P61

P60

N61

N59

T59

N58

L59 J58

AG58

AE60

AE59

AD60 AD59

AD23

AC59

AC58

AB23

AA59

AA23

H59

U0500

BGA

CRITICAL

OMIT_TABLE

2C+GT2

BROADWELL-ULT

21

R0811

MF

1/20W

0201

0

5%

21

R0812

MF

1/20W

0201

0

5%

21

R0810

201

1/20W

PLACE_NEAR=U0500.L62:38.1mm

43

5%

MF

2

1

R0800

PLACE_NEAR=R0810.1:2.54mm

75

1/20W

MF

1%

201

SYNC_MASTER=J43_MLB

SYNC_DATE=10/02/2012

CPU/PCH POWER

PPVCC_S0_CPU

PP1V05_S0

TP_CPU_RSVDN61

TP_CPU_RSVD_N59

TP_CPU_RSVDP61

TP_CPU_RSVD_P60

CPU_PWR_DEBUG

CPU_VCCSENSE_P

PPVCC_S0_CPU

PPVMEMIO_S0_CPU

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PPVCOMP_S0_CPU

CPU_VIDALERT_R_L

CPU_VIDSOUT_R

CPU_VIDSCLK_R

CPU_VR_EN

CPU_VCCST_PWRGD

CPU_VR_READY

TP_PPVCCIO_S0_CPU

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V05_S0SW_PCH_HSIO

PP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_S0SW_PCH_VCCSATA3PLL

PP1V05_S0_PCH_VCCAPLL_OPI

PP1V5_S0SW_AUDIO_HDA

PP3V3_S5

PP1V05_S0

PP1V05_S0_PCH_VCCACLKPLL

PPVRTC_G3H

PPVOUT_S0_PCH_DCPRTC

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP3V3_SUS

PP1V05_S0

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP_R

PP1V05_S0

PP1V5_S0

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP1V05_S0_PCH_VCC_ICC

PP3V3_SUS

PP1V05_S0

CPU_VIDSCLK

CPU_VIDALERT_L

CPU_VIDSOUT

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP

<SCH_NUM>

8 OF 121

8 OF 76

8

10 42 52 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

18

8

10 42 52 62 64

10 42

5

11 58 62

11 14

11 12

11

11 17 58

11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74

6 8

11 15 16 17 38 42 51

55 58 59 62 64

11 12

12 13 17 62 64

8

11 14 18 46 57 58 59

62 64

6 8

11 15 16 17 38 42 51

55 58 59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51 55 58

59 62 64

57 58 59 62 64

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

6 8

11 15 16 17 38 42 51 55 58

59 62 64

6 8

11 15 16 17 38 42 51

55 58 59 62 64

8

11 12 13 15 17 18 26 30

36 38 39 40 41 42 43 44 45

56 59 61 62 64 65 74

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

11

8

11 14 18 46 57 58 59 62

64

8

11 14 18 46 57 58 59 62

64

8

11 14 18 46 57 58 59 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

w w w . c h i n a f i x . c o m

OUT

SYM 14 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

SYM 15 OF 19

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS

SYM 16 OF 19

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS VSS VSS

VSS

VSS_SENSE

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

2

1

R0960

201

MF

1/20W

100

5%

PLACE_NEAR=U0500.E62:50.8mm

51 67

AP20

AP17

AP10

AN7

AN63

AN60

AN52

AN51

AN49

AN48

AN46

AN45

AN43

AN42

AN40

AN39

AN36

AN35

AN32

AN31

AN23

AN17

AM52

AM31

AM23

AM17

AM1

AL61

AL60

AL57

AL54

AL52

AL51

AL46

AL45

AL40

AL39

AL36

AL33

AL31

AL29

AL26

AL23

AL22

AL20

AL17

AL13

AL10

AK52

AK3

AK23

AJ63

AJ60

AJ58

AJ56

AJ54

AJ52

AJ50

AJ47

AJ45

AJ43

AJ41

AJ39

AJ35

AJ29

AJ27

AJ25

AJ23

AJ14

AJ13

AH57

AH55

AH53

AH51

AH49

AH44

AH42

AH40

AH38

AH36

AH34

AH32

AH30

AH28

AH24

AH22

AH20

AH19

AH17

AG63

AG62

AG61

AG60

AG23

AG21

AG11

AG1

AF18

AF17

AF15

AF14

AF12

AF11

AE58

AE5

AE10

AD63

AD3

AD21

AC61

AB7

AB22

AB20

AB10

AA58

AA1

A56

A52

A48

A44

A40

A36

A32

A28

A24

A18

A14

A11

U0500

OMIT_TABLE

CRITICAL

BGA

2C+GT2

BROADWELL-ULT

D31

D30

D29

D27

D26

D25

D23

D21

D2

D18

D14

D12

C57

C39

C38

C27

C25

C20

C18

C14

C11

B60

B56

B52

B48

B44

B40

B4

B36

B32

B28

B26

B24

B20

AY6

AY59

AY57

AY53

AY51

AY4

AY33

AY30

AY26

AY24

AY22

AY18

AY16

AY11

AW60

AW59

AW51

AW50

AW47

AW44

AW42

AW40

AW4

AW37

AW35

AW33

AW24

AW16

AV8

AV59

AV55

AV51

AV49

AV46

AV43

AV41

AV39

AV36

AV34

AV33

AV28

AV24

AV20

AV16

AV14

AU59

AU57

AU55

AU53

AU51

AU33

AU30

AU28

AU26

AU24

AU22

AU20

AU18

AU16

AU1

AT63

AT62

AT61

AT49

AT46

AT43

AT42

AT40

AT37

AT35

AT13

AR52

AR5

AR49

AR43

AR39

AR33

AR31

AR23

AR17

AR15

AR11

AP57

AP54

AP52

AP48

AP39

AP38

AP31

AP3

AP29

AP26

AP23

AP22

U0500

BROADWELL-ULT

2C+GT2

CRITICAL

OMIT_TABLE

BGA

Y63

Y59

Y10

W22

W20

V7

V58

V3

V23

V10

U9

U61

U22

U20

T58

T1

E62

R8

R22

R10

P63

P59

N3

N10

M22

L7

L61

L58

L20

L18

L17

L15

L13

K12

K1

J63

J59

J22

J10

H57

H17

H13

G8

G6

G5

G3

G22

G18

F61

F58

F54

F50

F46

F42

F38

F34

F30

F26

F20

E17

E11

D8

D62

D59

D57

D55

D54

D53

D51

D50

D5

D49

D47

D46

D45

D43

D42

D41

D39

D38

D37

D35

D34

D33

AH46

AH16

U0500

BGA

CRITICAL

OMIT_TABLE

2C+GT2

BROADWELL-ULT

CPU/PCH GROUNDS

SYNC_MASTER=J43_MLB

SYNC_DATE=10/02/2012

CPU_VCCSENSE_N

9 OF 76

9 OF 121

<SCH_NUM>

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise

CPU VCC Decoupling

CPU VDDQ DECOUPLING

Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603

2x Bulk nostuff per Harris Beach v1.0 schematic

Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff

Apple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff

2

1

C1000

CRITICAL

4V X6S 0402

20%

10UF

2

1

C1050

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1051

10UF

CERM-X5R

6.3V

20%

0402-1

2

1

C1052

CERM-X5R 0402-1

10UF

6.3V

20%

2

1

C1053

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1054

CERM-X5R

20%

0402-1

10UF

6.3V 2

1

C1055

10UF

0402-1

CERM-X5R

6.3V

20%

2

1

C1040

6.3V CERM 402-LF

2.2UF

20%

2

1

C1041

402-LF

6.3V CERM

2.2UF

20%

2

1

C1042

6.3V CERM 402-LF

20%

2.2UF

2

1

C1043

6.3V

20%

2.2UF

402-LF

CERM

2

1

C1060

TANT

2V

20%

270UF

CASE-B2-SM

2

1

C1061

NO STUFF

CASE-B2-SM

TANT

2V

20%

270UF

2

1

C1001

CRITICAL

20% 4V X6S 0402

10UF

2

1

C1002

CRITICAL

4V X6S

10UF

20%

0402

2

1

C1003

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1004

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1005

NO STUFF

10UF

0402

4V X6S

20%

2

1

C1006

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1007

CRITICAL

10UF

0402

4V X6S

20%

2

1

C1008

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1009

NO STUFF

20%

0402

4V X6S

10UF

2

1

C1010

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1011

0402

4V X6S

10UF

20%

NO STUFF

2

1

C1012

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1013

10UF

0402

4V X6S

20%

NO STUFF

2

1

C1014

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1015

4V X6S

20%

10UF

0402

NO STUFF

2

1

C1016

CRITICAL

4V

20%

0402

X6S

10UF

2

1

C1017

CRITICAL

20%

10UF

X6S

4V

0402

2

1

C1018

CRITICAL

4V

20%

0402

X6S

10UF

2

1

C1019

20% 4V X6S

10UF

0402

NO STUFF

2

1

C1020

20%

X6S

4V

10UF

0402

NO STUFF

2

1

C1021

CRITICAL

0402

4V X6S

10UF

20%

2

1

C1084

CRITICAL

4V X6S

20%

10UF

0402

2

1

C1083

CRITICAL

4V X6S

20%

10UF

0402

2

1

C1082

4V X6S

20%

10UF

0402

NO STUFF

2

1

C1081

20%

0402

X6S

4V

10UF

NO STUFF

2

1

C1080

NO STUFF

4V X6S

10UF

20%

0402

2

1

C1079

4V X6S

20%

10UF

0402

NO STUFF

2

1

C1078

NO STUFF

10UF

20%

X6S

4V

0402

2

1

C1077

CRITICAL

20%

X6S

4V

10UF

0402

2

1

C1076

CRITICAL

4V X6S

10UF

20%

0402

2

1

C1075

NO STUFF

4V X6S

10UF

20%

0402

2

1

C1074

10UF

20% 4V X6S 0402

NO STUFF

2

1

C1073

NO STUFF

X6S

4V

20%

0402

10UF

2

1

C1072

10UF

X6S

4V

20%

0402

NO STUFF

2

1

C1071

NO STUFF

4V X6S

10UF

20%

0402

2

1

C1070

NO STUFF

20%

0402

10UF

X6S

4V

2

1

C1097

NO STUFF

0402

20%

10UF

X6S

4V

2

1

C1096

0402

4V X6S

20%

10UF

NO STUFF

2

1

C1095

0402

20%

10UF

X6S

4V

NO STUFF

2

1

C1094

0402

20%

10UF

X6S

4V

NO STUFF

2

1

C1093

10UF

0402

20%

X6S

4V

NO STUFF

2

1

C1092

NO STUFF

0402

10UF

20%

X6S

4V

2

1

C1091

NO STUFF

0402

4V

20%

X6S

10UF

2

1

C1090

NO STUFF

0402

20%

10UF

X6S

4V

2

1

C1089

CRITICAL

0402

20%

10UF

X6S

4V

2

1

C1088

CRITICAL

0402

20%

10UF

X6S

4V

2

1

C1087

NO STUFF

0402

20%

10UF

X6S

4V

2

1

C1086

NO STUFF

10UF

0402

20% 4V X6S

2

1

C1085

NO STUFF

10UF

0402

20%

X6S

4V

2

1

C1038

NO STUFF

0402

10UF

20% 4V X6S

2

1

C1037

NO STUFF

0402

4V X6S

10UF

20%

2

1

C1036

NO STUFF

4V

0402

X6S

20%

10UF

2

1

C1035

NO STUFF

0402

20%

10UF

4V X6S

2

1

C1034

NO STUFF

X6S 0402

20% 4V

10UF

2

1

C1033

NO STUFF

0402

20% 4V X6S

10UF

2

1

C1032

0402

10UF

20%

X6S

4V

NO STUFF

2

1

C1029

0402

20% 4V X6S

NO STUFF

10UF

2

1

C109A

0402

10UF

20% 4V X6S

NO STUFF

2

1

C1099

NO STUFF

0402

X6S

20%

10UF

4V

2

1

C1098

NO STUFF

0402

4V X6S

20%

10UF

2

1

C107B

NO STUFF

20%

X6S

4V

10UF

0402

2

1

C107A

4V

20%

10UF

X6S 0402

NO STUFF

2

1

C1069

NO STUFF

10UF

X6S

4V

20%

0402

2

1

C1068

NO STUFF

0402

X6S

4V

10UF

20%

2

1

C108F

NO STUFF

20% 4V X6S 0402

10UF

2

1

C1067

NO STUFF

0402

4V X6S

20%

10UF

2

1

C108E

NO STUFF

20% 4V X6S

10UF

0402

2

1

C1066

NO STUFF

0402

10UF

20% 4V X6S

2

1

C108D

NO STUFF

X6S

4V

20%

0402

10UF

2

1

C108C

NO STUFF

X6S

4V

20%

10UF

0402

2

1

C1065

NO STUFF

0402

10UF

4V

20%

X6S

2

1

C1028

NO STUFF

10UF

0402

4V X6S

20%

2

1

C1027

10UF

0402

4V X6S

20%

NO STUFF

2

1

C1049

0402

NO STUFF

4V

20%

X6S

10UF

2

1

C1048

0402

4V

20%

X6S

10UF

NO STUFF

2

1

C1026

10UF

4V X6S 0402

20%

NO STUFF

2

1

C1047

0402

X6S

10UF

4V

20%

NO STUFF

2

1

C1025

NO STUFF

10UF

20% 4V X6S 0402

2

1

C1024

NO STUFF

10UF

0402

4V X6S

20%

2

1

C1046

NO STUFF

0402

X6S

10UF

4V

20%

2

1

C1045

NO STUFF

0402

10UF

4V

20%

X6S

2

1

C1023

NO STUFF

0402

4V X6S

10UF

20%

2

1

C1022

NO STUFF

10UF

0402

20% 4V X6S

2

1

C1044

NO STUFF

0402

20%

X6S

4V

10UF

2

1

C1039

NO STUFF

0402

10UF

X6S

4V

20%

2

1

C1064

NO STUFF

X6S 0402

10UF

20% 4V

2

1

C108B

X6S

20% 4V

0402

10UF

NO STUFF

2

1

C1063

0402

X6S

4V

10UF

20%

NO STUFF

2

1

C108A

NO STUFF

20%

X6S

4V

10UF

0402

2

1

C1062

10UF

20% 4V X6S

NO STUFF

0402

2

1

C109F

NO STUFF

X6S

10UF

4V

20%

0402

2

1

C109E

NO STUFF

X6S

4V

20%

10UF

0402

2

1

C1059

NO STUFF

10UF

0402

20% 4V X6S

2

1

C1058

NO STUFF

0402

10UF

4V X6S

20%

2

1

C109D

NO STUFF

10UF

20% 4V X6S 0402

2

1

C1057

0402

20%

NO STUFF

4V X6S

10UF

2

1

C109C

NO STUFF

X6S

10UF

20% 4V

0402

2

1

C1056

NO STUFF

0402

10UF

4V X6S

20%

2

1

C109B

NO STUFF

X6S

4V

0402

10UF

20%

3 2

1

C1031

CRITICAL

470UF-0.0045OHM

SM

2.5V POLY-TANT

20%

2

1

C1030

0402

4V X6S

10UF

20%

NO STUFF

2

1

C104C

NO STUFF

10UF

0402

4V X6S

20%

2

1

C104D

4V

NO STUFF

20%

X6S

10UF

0402

2

1

C104E

20%

10UF

X6S

4V

0402

NO STUFF

2

1

C104F

NO STUFF

20%

10UF

X6S

4V

0402

2

1

C106A

NO STUFF

20%

10UF

X6S

4V

0402

2

1

C106B

20%

10UF

X6S

4V

0402

NO STUFF

2

1

C106C

20%

10UF

X6S

4V

0402

NO STUFF

2

1

C106D

0402

4V X6S

10UF

20%

NO STUFF

2

1

C106E

0402

4V X6S

10UF

20%

NO STUFF

2

1

C105A

NO STUFF

20%

10UF

X6S

4V

0402

2

1

C105B

NO STUFF

20%

10UF

X6S

4V

0402

2

1

C105C

NO STUFF

4V

20%

10UF

X6S 0402

2

1

C105D

20%

10UF

X6S

4V

0402

NO STUFF

2

1

C105E

0402

4V X6S

10UF

20%

NO STUFF

2

1

C105F

NO STUFF

0402

4V X6S

10UF

20%

2

1

C104A

NO STUFF

10UF

0402

4V X6S

20%

2

1

C104B

NO STUFF

0402

4V X6S

10UF

20%

SYNC_DATE=01/08/2013SYNC_MASTER=WILL_J43

CPU Decoupling

PPVCC_S0_CPU

PPVMEMIO_S0_CPU

10 OF 121

<SCH_NUM>

10 OF 76

8

42 52 62 64

8

42

w w w . c h i n a f i x . c o m

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

??mA Max

PCH OPI VCCAPLL FILTER/BYPASS

57mA Max

31mA Max

??mA Max

42mA Max83mA Max

41mA Max

PCH VCCDSW3_3 BYPASS

PCH VCCSUS3_3 BYPASS

(PCH 1.05V PCIe/SATA/USB3 PWR)

PCH VCCHSIO BYPASS

PCH VCCASW BYPASS (PCH 1.05V ME CORE PWR)

(PCH 1.05V OPI PLL PWR)

(PCH 1.05V CLK PWR)

PCH VCCCLK BYPASS

PCH VCC3_3 BYPASS (PCH 3.3V GPIO/LPC PWR)

PCH VCC3_3 BYPASS (PCH 3.3V THERMAL PWR)

(PCH 1.05V USB2 PWR)

PCH VCCIO BYPASS

(PCH 1.05V VCCCLK PWR)

PCH VCCCLK FILTER/BYPASS

PCH VCCACLKPLL FILTER/BYPASS (PCH 1.05V ACLK PLL PWR)

(PCH 3.3V DSW PWR)

PCH VCCSUS3_3 BYPASS (PCH 3.3V SUSPEND PWR)

PCH VCCSPI BYPASS (PCH 3.3V SPI PWR)

(PCH 3.3V SUSPEND RTC PWR)

(PCH 3.3V/1.5V HDA PWR)

PCH VCCSDIO BYPASS (PCH 3.3V/1.8V SDIO PWR)

PCH VCCSUSHDA BYPASS

LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0 as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

PCH VCCSATA3PLL FILTER/BYPASS

(PCH 1.05V USB3 PLL PWR)

PCH VCCUSB3PLL FILTER/BYPASS

(PCH 1.05V SATA3 PLL PWR)

PCH VCC BYPASS (PCH 1.05V CORE PWR)

2

1

C1202

BYPASS=U0500.Y8:6.35mm

CERM

402

0.1UF

20% 10V

NO STUFF

21

L1280

0603

2.2UH-240MA-0.221OHM

CRITICAL NO STUFF

21

R1280

0

MF-LF

402

5%

1/16W

2

1

C1295

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.B18:12.7mm

2

1

C1296

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.B18:12.7mm

NO STUFF

2

1

C1290

BYPASS=U0500.B11:12.7mm

CERM-X5R

4V

20%

47UF

0805-1

2

1

C1291

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.B11:12.7mm

NO STUFF

2

1

C1280

BYPASS=U0500.AA21:12.7mm

0805-1

47UF

20%

4V

CERM-X5R

NO STUFF

2

1

C1281

CERM-X5R

4V

20%

47UF

BYPASS=U0500.AA21:12.7mm

0805-1

NO STUFF

2

1

C1275

BYPASS=U0500.J18:12.7mm

4V

20%

47UF

0805-1

CERM-X5R

2

1

C1276

0805-1

47UF

20%

4V

CERM-X5R

BYPASS=U0500.J18:12.7mm

2

1

C1270

CERM-X5R

BYPASS=U0500.A20:12.7mm

0805-1

47UF

20%

4V

2

1

C1271

CERM-X5R

4V

20%

47UF

0805-1

BYPASS=U0500.A20:12.7mm

2

1

C1200

6.3V

10%

402

CERM

1UF

BYPASS=U0500.AH10:6.35mm

NO STUFF

2

1

C1210

BYPASS=U0500.AH14:6.35mm

6.3V

10%

1UF

CERM

402

2

1

C1214

BYPASS=U0500.K14:6.35mm

CERM

402

10V

20%

0.1UF

2

1

C1206

BYPASS=U0500.AH11:6.35mm

402

CERM

6.3V

1UF

10%

2

1

C1264

402

CERM

BYPASS=U0500.AG16:6.35mm

1UF

10%

6.3V

2

1

C1261

1UF

CERM

402

10%

6.3V

BYPASS=U0500.L10:6.35mm

2

1

C1262

0402-1

20%

10UF

CERM-X5R

BYPASS=U0500.M9:6.35mm

6.3V

2

1

C1266

6.3V CERM

402

1UF

10%

BYPASS=U0500.J17:6.35mm

2

1

C1255

BYPASS=U0500.J11:12.7mm

6.3V

20%

603

X5R

10UF

2

1

C1250

BYPASS=U0500.AE9:12.7mm

X5R-CERM-1

6.3V

20%

22UF

603

NO STUFF

2

1

C1256

BYPASS=U0500.J11:6.35mm

6.3V 402

10%

1UF

CERM

2

1

C1257

1UF

BYPASS=U0500.AE8:6.35mm

6.3V

10%

402

CERM

2

1

C1251

BYPASS=U0500.AE9:6.35mm

6.3V

10%

402

CERM

1UF

2

1

C1267

6.3V CERM

402

1UF

10%

BYPASS=U0500.R21:6.35mm

2

1

C1204

X5R-CERM-1

6.3V

20%

22UF

603

BYPASS=U0500.AC9:12.7mm

2

1

C1212

22UF

20%

6.3V

X5R-CERM-1

BYPASS=U0500.V8:12.7mm

603

2

1

C1208

BYPASS=U0500.U8:6.35mm

402

CERM

6.3V

1UF

10%

2

1

C1260

BYPASS=U0500.K9:6.35mm

1UF

402

10%

6.3V CERM

2

1

C1277

10V

10%

402

X5R

1UF

BYPASS=U0500.J18:6.35mm

21

L1275

2.2UH-240MA-0.221OHM

0603

CRITICAL

2

1

C1297

10V

10%

402

X5R

1UF

BYPASS=U0500.B18:6.35mm

21

L1295

CRITICAL

0603

2.2UH-240MA-0.221OHM

2

1

C1292

10V

10%

402

X5R

1UF

BYPASS=U0500.B11:6.35mm

21

L1290

2.2UH-240MA-0.221OHM

CRITICAL

0603

21

R1275

0

1/16W

5%

402

MF-LF

2

1

C1272

1UF

X5R 402

10% 10V

BYPASS=U0500.A20:6.35mm

21

L1270

0603

CRITICAL

2.2UH-240MA-0.221OHM

21

R1270

5%

402

MF-LF

1/16W

0

2

1

C1282

1UF

X5R 402

10% 10V

BYPASS=U0500.AA21:6.35mm

SYNC_DATE=02/07/2013

SYNC_MASTER=J41_MLB

PCH Decoupling

PP1V05_S0

PP3V3_SUS

PP3V3_S0

PP1V5_S0SW_AUDIO_HDA

PP3V3_S5

PP3V3_SUS

PP1V05_S0

PP3V3_S0

PP1V05_S0

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCACLKPLL_R

PP1V05_S0

PP1V05_S0SW_PCH_HSIO

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0SW_PCH_VCCUSB3PLL

PP1V05_S0

PP1V05_S0SW_PCH_HSIO

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0SW_PCH_VCCSATA3PLL

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC_R

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCACLKPLL

MIN_NECK_WIDTH=0.075 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCAPLL_OPI

<SCH_NUM>

12 OF 121

11 OF 76

6 8

11 15 16 17 38 42 51 55

58 59 62 64

8

11 14 18 46 57 58 59 62 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8

17 58

8

13 15 16 17 18 28 29 34 42

57 58 59 60 62 64 74

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

6 8

11 15 16 17 38 42 51 55

58 59 62 64

6 8

11 15 16 17 38 42 51 55

58 59 62 64

8

11 58 62

8

14

6 8

11 15 16 17 38 42 51 55

58 59 62 64

8

11 58 62

8

12

8

12

8

w w w . c h i n a f i x . c o m

IN IN

IN

OUT

BI

AUDIO

SYM 5 OF 19

SATA

JTAG

RTC

RSVD

HDA_DOCK_EN*/I2S1_TXD

HDA_BCLK/I2S0_SCLK

RTCX1 RTCX2

RTCRST*

INTVRMEN

INTRUDER*

SRTCRST*

HDA_RST*/I2S_MCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

PCH_TRST*

PCH_TDI

PCH_TCK

PCH_TDO

RSVD

PCH_TMS

JTAGX

RSVD

RSVD SATALED*

SATA_RCOMP

SYM 6 OF 19

CLOCK SIGNALS

CLKOUT_LPC_1

CLKOUT_LPC_0

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

PCIECLKRQ5*/GPIO23

PCIECLKRQ4*/GPIO22

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

PCIECLKRQ3*/GPIO21

CLKOUT_PCIE_P4

CLKOUT_PCIE_N4

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

CLKOUT_PCIE_N0

XTAL24_OUT

XTAL24_IN

CLKOUT_PCIE_P0

TESTLOW

TESTLOW TESTLOW

DIFFCLK_BIASREF

RSVD

OUT

IN

OUT

IN

OUT

OUT OUT

IN

OUT OUT

IN

OUT

IN

NC NC

NC

IN

OUT

IN

OUT

IN

NC NC

OUT OUT

IN IN

OUT

NC NC

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD-PLTRST#)

SSD Lane 1

SATA Port assignments:

Reserved: ODD

Primary HDD/SSD

Unused

Secondary HDD/SSD

(IPD)

(IPU)

(IPD-PLTRST#)

(IPD-PWROK)

SSD Lane 3

PCIe Port assignments:

SSD Lane 2

SSD Lane 0

(IPD)

16 64 69

21

R1345

MF

201

5%

1/20W

100K

21

R1375

201

1/20W

5% MF

100K

16

12 16

15 16

21

R1343

1/20W

MF

201

5%

100K

16 64 69

16

AV6

U3

D17

C15

B17

A15

C17

B14

A17

B15

E5

H6

H8

H5

F5

J6

J8

J5

C12

A12

AC1

V6

U1

V1

AY5

AW5

AU7

L11

K10

AV2

AL11

AC4

AU62

AD62

AE61

AD61

AE62

AE63

AV7

AU6

AY8

AV11

AU11

AU12

AY10

AU8

AV10

AW10

AW8

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

B25

A25

C35 C34

AL8

AK8

M21

K21

T2

U5

N1

AD1

Y5

U2

C26

A37

B39

C37

B42

A41

C42

B37

A39

B38

C41

B41

C43

AP15

AN15

A35

B35

U0500

2C+GT2

BROADWELL-ULT

BGA

OMIT_TABLE

CRITICAL

25 69

12 25

29 64 69

12 29

29 64 69

32 69

12 31

30 64 67

12 30

21

R1376

100K

MF5%

1/20W

201

61 65 69

21

R1377

201

1/20W

5% MF

100K

61 65 69

21

R1312

PLACE_NEAR=U0500.AU8:1.27mm

1/20W

5% MF33201

21

R1311

201

PLACE_NEAR=U0500.AV11:1.27mm

MF5%

1/20W

33

61 65 69

21

R1310

PLACE_NEAR=U0500.AW8:1.27mm

1/20W

5%

201

MF

33

17

2

1

R1302

MF

201

5%

1/20W

330K

2

1

R1301

1M

MF 201

5% 1/20W

2

1

C1300

10V

10%

402

X5R

1UF

2

1

R1300

1/20W

5%

201

MF

20K

2

1

C1303

10V

10%

1UF

402

X5R

2

1

R1303

5%

201

20K

1/20W MF

6

16 64 67

2

1

R1370

PLACE_NEAR=U0500.C12:2.54mm

1% 1/20W

3.01K

MF 201

30 67

30 64 67

30 67

30 64 67

30 67

30 64 67

61 65 69

2

1

R1380

1/20W

PLACE_NEAR=U0500.C26:2.54mm

1%

201

MF

3.01K

17 69

21

R1390

10K

MF

1/20W

5%

201

21

R1391

MF

201

1/20W

10K

5%

21

R1392

201

MF

1/20W

10K

5%

21

R1393

5%

10K

1/20W

MF

201

17

21

R1313

201

PLACE_NEAR=U0500.AU11:1.27mm

33

1/20W

5% MF

21

R1341

1/20W

5%

201

MF

100K

21

R1344

100K

MF

201

5%

1/20W

21

R1340

1/20W

5%

201

MF

100K

21

R1342

5% MF

201

1/20W

100K

PCH Audio/JTAG/SATA/CLK

SYNC_DATE=12/17/2012SYNC_MASTER=WILL_J43

SSD_CLKREQ_L

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

NC_PCIE_CLK100M_FWN NC_PCIE_CLK100M_FWP

FW_CLKREQ_L

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

AP_CLKREQ_L

PCIE_CLK100M_CAMERA_N PCIE_CLK100M_CAMERA_P

CAMERA_CLKREQ_L

TP_PCIE_CLK100M_ENETSDP

TP_PCIE_CLK100M_ENETSDN

ENETSD_CLKREQ_L

TP_LPC_CLK24M_LPCPLUS_R

LPC_CLK24M_SMC_R

TP_ITPXDP_CLK100MN TP_ITPXDP_CLK100MP

PCH_CLK24M_XTALOUT

PCH_CLK24M_XTALIN

PCH_TESTLOW_C34

PCH_TESTLOW_C35

PCH_TESTLOW_AK8 PCH_TESTLOW_AL8

PCH_DIFFCLK_BIASREF

TP_PCH_I2S1_TXD

HDA_BIT_CLK_R

PCH_CLK32K_RTCX1 NC_RTC_CLK32K_RTCX2

RTC_RESET_L

PCH_INTVRMEN

PCH_INTRUDER_L

PCH_SRTCRST_L

HDA_RST_R_L

HDA_SYNC_R

HDA_SDIN0 NC_HDA_SDIN1

HDA_SDOUT_R

TP_PCH_I2S1_SFRM

TP_PCH_I2S1_SCLK

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3>

PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_C_P<0>

XDP_SSD_PCIE0_SEL_L

PP1V05_S0SW_PCH_VCCSATA3PLL

XDP_CPUPCH_TRST_L

XDP_PCH_TDI

XDP_PCH_TCK

XDP_PCH_TDO

XDP_PCH_TMS

PCH_JTAGX

PCH_SATALED_L

PCH_SATA_RCOMP

HDA_RST_L

HDA_SDOUT

HDA_BIT_CLK

HDA_SYNC

PPVRTC_G3H

PP1V05_S0_PCH_VCCACLKPLL

ENETSD_CLKREQ_L CAMERA_CLKREQ_L

FW_CLKREQ_L

AP_CLKREQ_L

TBT_CLKREQ_L SSD_CLKREQ_L

XDP_FW_PME_L XDP_PCH_GPIO35

PCH_SATALED_L

PP3V3_S0

XDP_PCH_UART_SSD_L_BT_H

XDP_PCH_GPIO35

XDP_PCH_UART_SSD_L_BT_H

13 OF 121

<SCH_NUM>

12 OF 76

64

12

69

64

17 69

8

11

12

8

13 17 62 64

8

11

12

12 31

12

12 29

12 25

12 30

12

8

11 13 15 17 18 26 30 36 38 39

40 41 42 43 44 45 56 59 61 62

64 65 74

12 16

w w w . c h i n a f i x . c o m

IN

OUT

IN

OUT

SYSTEM POWER MANAGEMENT

SYM 8 OF 19

SLP_WLAN*/GPIO29

SLP_S0*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

PCH_PWROK

APWROK

SYS_RESET*

SUSACK*

PLTRST*

SYS_PWROK

DPWROK

DSWVRMEN

CLKRUN*/GPIO32

WAKE*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

SIDEBAND

eDP

DISPLAY

PCI

SYM 9 OF 19

GPIO53

GPIO51

GPIO54

GPIO52

GPIO55

PME*

PIRQC*/GPIO79 PIRQD*/GPIO80

PIRQA*/GPIO77 PIRQB*/GPIO78

EDP_BKLEN

EDP_BKLCTL

EDP_HPD

DDPC_HPD

DDPC_AUXP

DDPB_AUXP

DDPB_HPD

DDPB_AUXN DDPC_AUXN

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

EDP_VDDEN

OUT

IN

OUT

BI

IN

OUT

BI BI

BI

OUT

IN

IN IN IN

OUT OUT OUT

OUT

IN

OUT

IN

NC

08

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R1400 kept for debug purposes.

(IPU)

(IPD-PLTRST#)

(IPD-DeepSx)

(IPU)

(IPD-PLTRST#)

U1420 ensures signal will only be high in S0.

SLP_S0# can be driven high outside of S0

SLP_S0# Isolation

59 64

13 18 37

39

AJ5

AC3

AG2

AV4

AE6

AK2

AG4

AM5

AP4

AP5

AJ6

AT4

AF3 AJ7

AL5

AW6

AL7

AG7

AY7

AW7

AV5

V5

AN4

AB5

AJ8

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

AD4

N2

N4

P4

U6

U7

L3

L4

L1

R5

C6

D6

A9

B8

A8

D11

D9

A6

B6

C8

C9

B9

B5

C5

U0500

BGA

CRITICAL

OMIT_TABLE

BROADWELL-ULT

2C+GT2

13 30

15 16 18

21

R1441

100K

MF

1/20W

201

5%

13 17

16 17 37

17 37 64

13 42 59

13 17 18 37 59

13 18 29 36 37 59

13 37 59

38 69

37 64

13 37 64

13 29 31 64

2

1

R1451

5%

201

1/20W MF

100K

37

2

1

R1450

5%

201

1/20W MF

330K

13 56

56

13 60

25 67

18 25 67

25 67

18 28

18

18 28

25

18 25

60

21

R1446

5%

201

1/20W

MF

100K

21

R1445

5%

201

1/20W

MF

100K

21

R1442

5%

201

1/20W

MF

100K

21

R1443

5%

201

1/20W

MF

100K

2

1

R1400

5%

0

0201

1/20W

MF

NO STUFF

21

R1440

100K

MF

1/20W

201

5%

13 26

13 37

13 64

13 27 37

21

R1455

5%

201

1/20W

MF

10K

21

R1410

5%

201

1/20W

MF

10K

21

R1447

5%

201

1/20W

MF

100K

21

R1448

5%

201

1/20W

MF

100K

21

R1449

5%

201

1/20W

MF

100K

21

R1431

5%

201

1/20W

MF

100K

21

R1430

5%

201

1/20W

MF

100K

37 38

13 59 61 65

21

R1405

5%

201

1/20W

MF

1K

21

R1452

5%

201

1/20W

MF

10K

21

R1460

5%

201

1/20W

MF

100K

21

R1461

5%

201

1/20W

MF

100K

21

R1462

5%

201

1/20W

MF

100K

21

R1464

5%

201

1/20W

MF

100K

21

R1463

5%

201

1/20W

MF

100K

13 16 37

4

6

53

1

2

U1420

CRITICAL

74LVC1G08

SOT891

2

1

C1420

0201

X5R-CERM

10% 10V

0.1UF

PCH PM/PCI/GFX

SYNC_DATE=02/20/2013

SYNC_MASTER=J43_MLB

PP3V3_S0

SMC_RUNTIME_SCI_L

AP_PCIE_DEV_WAKE

SSD_BOOT

AUD_PWR_EN

ENET_LOW_PWR

HDMITBTMUX_LATCH

ODD_PWR_EN_L

NC_PCI_PME_L

TBT_PWR_REQ_L SMC_RUNTIME_SCI_L

EDP_BKLT_EN

EDP_BKLT_PWM

DP_INT_HPD

DP_TBTSNK1_HPD

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_HPD

DP_TBTSNK0_AUXCH_C_N DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_DATA

EDP_PANEL_PWR

TP_PCH_SLP_WLAN_L

PCH_PM_SLP_S0_L

PM_BATLOW_L

SMC_ADAPTER_EN

PM_PWRBTN_L

PCH_SUSWARN_L

PM_RSMRST_L

PM_PCH_PWROK

PM_SYSRST_L

PCH_SUSACK_L

PLT_RESET_L

PM_PCH_SYS_PWROK

PM_DSW_PWRGD

PCH_DSWVRMEN

PM_CLKRUN_L

PCIE_WAKE_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PM_SLP_S4_L

PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

TP_PCH_SLP_LAN_L

PM_SLP_SUS_L

EDP_BKLT_EN EDP_PANEL_PWR

HDMITBTMUX_FLAG

PM_SLP_S0_L

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S0_L

PP3V3_S0

PM_BATLOW_L

PM_PWRBTN_L

PP3V3_S5

AUD_PWR_EN AP_PCIE_DEV_WAKE

ENET_LOW_PWR

HDMITBTMUX_LATCH

ODD_PWR_EN_L

SSD_BOOT

TBT_PWR_REQ_L

PM_SLP_S5_L

PM_CLKRUN_L

PCIE_WAKE_L

PPVRTC_G3H

HDMITBTMUX_FLAG

14 OF 121

<SCH_NUM>

13 OF 76

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

13 37

64

13 42 59

13 56

13 60

13 64

13 18 37

13 17 18 37 59

13 18 29 36 37 59

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

13 27 37

13 16 37

8

11 15 16 17 18 28 29 34 42 57

58 59 60 62 64 74

13 59 61 65

13 64

13 30

13 26

13 37 59

13 37 64

13 29 31 64

8

12 17 62 64

w w w . c h i n a f i x . c o m

OUT

IN IN IN

OUT

IN

OUT

USB

PCI-E

SYM 11 OF 19

PCIE_RCOMP PCIE_IREF

RSVD

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP5_L3

PETN5_L3

PETP5_L2

PETN5_L2

PERP5_L2

PERN5_L2

PETP5_L1

PETN5_L1

PERP5_L1

PERN5_L1

USB2P7

USB2N7

PERP5_L3

PERN5_L3

PETP5_L0

PETN5_L0

PERP5_L0

PERN5_L0

OC1*/GPIO41

OC0*/GPIO40

OC2*/GPIO42 OC3*/GPIO43

RSVD RSVD

USBRBIAS*

USBRBIAS

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

PERN1/USB3RN3

PERN2/USB3RN4

PERP1/USB3RP3

PERP2/USB3RP4

PETN1/USB3TN3

PETN2/USB3TN4

PETP1/USB3TP3

PETP2/USB3TP4

USB3RN1

USB3RN2

USB3RP1

USB3RP2

USB3TN1

USB3TN2

USB3TP1

USB3TP2

SYM 7 OF 19

LPC

SMBUS

SPI

C-LINK

SPI_IO3

SPI_MISO

SPI_IO2

SPI_CS2*

SPI_MOSI

SPI_CS0*

SPI_CS1*

LFRAME*

LAD2 LAD3

LAD1

SPI_CLK

LAD0

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1ALERT*/PCHHOT*/GPIO73

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST*

IN IN

OUT OUT

IN IN

OUT OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

NC NC

BI

IN

BI

OUT

BI

OUT

BI BI

BI

OUT

IN

BI

OUT

BI

OUT

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

Otherwise, 100k pull-up to 3.3V SUS required.

Ext A (SS)

SD Card Reader

(IPD)

Reserved: Camera

Trackpad

(IPU)

(IPU/IPD)

(IPU)

(IPU/IPD)

Reserved: SD (HS)

IR

BT

Ext B (LS/FS/HS)

Ext A (LS/FS/HS)

USB Port Assignments:

Ext B (SS)

Camera

AirPort

Reserved: FireWire

Thunderbolt lane 0

USB3 Port Assignments:

PCIe Port Assignments:

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

(& Ethernet if combo)

Unused

SML1ALERT# pull-up not provided on this page, may be wire-ORed into other signals.

25 69

21

R1580

201

1/20W

MF5%

100K

21

R1581

201

MF

1/20W

5%

100K

14 16 35

14 16 61 65

14 16

18 39

14 16

25 69

14 64

AJ10 AJ11

A33

B34

B33

C33

F18

H20

E18

G20

AP13

AN11

AN13

AL15

AT10

AP8

AT7

AM8

AR13

AP11

AM13

AM15

AR10

AR8

AR7

AN8

E15 E13

AN10 AM10

A21

C21

A23

C22

A29

B30

A31

C31

B22

B21

B23

C23

B29

C29

B31

C30

F6

G10

E8

E10

G13

F11

G15

F17

E6

H10

F8

F10

F13

G11

F15

G17

A27 B27 AV3

AH2

AT1

AL3

U0500

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

AA2

AA4

AF1

Y6

AC2

Y4

Y7

AA3

AH3

AU3

AU4

AK1

AN1

AL2

AH1

AP2

AN2

AV12

AW11

AY12

AW12

AU14

AF4

AD2

AF2

U0500

2C+GT2

BROADWELL-ULT

BGA

OMIT_TABLE

CRITICAL

25 69

34 65 68

32 69

29 69

29 64 69

2

1

R1500

1/20W

PLACE_NEAR=U0500.A27:2.54mm

1%

MF

201

3.01K

61 65 68

35 68

25 69

35 68

2

1

R1570

PLACE_NEAR=U0500.AJ10:2.54mm

MF

1/20W

1%

201

22.6

36 64 68

64

25 69

64

29 68

61 65 68

25 69

35 68

37 64 69

21

R1543

33

MF

201

5%

1/20W

21

R1542

33

5% MF

1/20W

201

25 69

21

R1544

1/20W

5%

201

MF

33

21

R1540

33

MF

201

1/20W

5%

21

R1541

33

MF

201

5%

1/20W

46 69

32 37 40 43 44 64 69 73

25 69

32 37 40 43 44 64 69 73

40 69

16 19 40 56 69

46 69

25 69

14 46 69

21

R1591

100K

5% MF

1/20W

201

21

R1549

201

1/20W

MF5%

1K

21

R1590

201

MF

1/20W

5%

100K

21

R1548

201

1/20W

MF5%

1K

21

R1582

201

MF

1/20W

5%

100K

21

R1583

1/20W

5% MF

201

100K

PCH PCIe/USB/LPC/SPI/SMBus

SYNC_MASTER=WILL_J43 SYNC_DATE=09/13/2012

LPC_FRAME_L

LPC_AD<3>

LPC_AD<1>

LPC_AD<0>

LPC_AD<2>

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L

WOL_EN

SPI_IO<3>

PCH_SMBALERT_L

SPI_IO<2>

XDP_USB_EXTD_OC_L

PP3V3_SUS PP3V3_SUS

USB3_EXTB_R2D_C_P

USB3_EXTA_R2D_C_P

USB3_EXTB_R2D_C_N

USB3_EXTA_R2D_C_N

USB3_EXTB_D2R_P

USB3_EXTA_D2R_P

USB3_EXTB_D2R_N

USB3_EXTA_D2R_N

PCIE_CAMERA_R2D_C_P

USB3_SD_R2D_C_P

PCIE_CAMERA_R2D_C_N

USB3_SD_R2D_C_N

PCIE_CAMERA_D2R_P

USB3_SD_D2R_P

PCIE_CAMERA_D2R_N

USB3_SD_D2R_N

NC_USB_CAMERAP

NC_USB_CAMERAN

TP_USB_5P

TP_USB_5N

USB_TPAD_P

USB_TPAD_N

NC_USB_IRP

NC_USB_IRN

USB_BT_P

USB_BT_N

USB_EXTB_P

USB_EXTB_N

USB_EXTA_P

USB_EXTA_N

PCH_USB_RBIAS

XDP_USB_EXTD_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L

PCIE_TBT_D2R_N<0> PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<3> PCIE_TBT_D2R_P<3>

NC_USB_SDN NC_USB_SDP

PCIE_TBT_D2R_N<1> PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1> PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<2> PCIE_TBT_D2R_P<2>

PCIE_TBT_R2D_C_N<2> PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<3> PCIE_TBT_R2D_C_P<3>

PCIE_AP_D2R_N PCIE_AP_D2R_P

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

NC_PCIE_FW_D2RN NC_PCIE_FW_D2RP

NC_PCIE_FW_R2D_CN NC_PCIE_FW_R2D_CP

PP1V05_S0SW_PCH_VCCUSB3PLL

PCH_PCIE_RCOMP

NC_CLINK_RESET_L

NC_CLINK_DATA

NC_CLINK_CLK

SMBUS_SMC_1_S0_SDA

PCH_SML1ALERT_L

SMBUS_SMC_1_S0_SCL

SML_PCH_0_DATA

SML_PCH_0_CLK

WOL_EN

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PCH_SMBALERT_L

LPC_AD_R<0>

SPI_CLK_R

LPC_AD_R<1>

LPC_AD_R<3>

LPC_AD_R<2>

LPC_FRAME_R_L

TP_SPI_CS1_L

SPI_CS0_R_L

SPI_MOSI_R

TP_SPI_CS2_L

SPI_IO<2>

SPI_MISO

SPI_IO<3>

<SCH_NUM>

15 OF 121

14 OF 76

14 16 35

14 16 61 65

14 16

14 64

14 46 69

14

14 46 69

14 16

8

11 14 18 46 57 58 59 62 64

8

11 14 18 46 57 58 59 62 64

64

68

64

8

11

64

14

w w w . c h i n a f i x . c o m

IN

OUT

BI

LPIO

GPIO

CPU/MISC

SYM 10 OF 19

SPKR/GPIO81

GPIO10

GPIO9

GPIO46

GPIO45

GPIO14

GPIO25

GPIO13

HSIOPC/GPIO71

GPIO50

GPIO49

GPIO48

GPIO44

GPIO47

GPIO59

GPIO58

GPIO57

GPIO56

GPIO26

GPIO27

GPIO28

GPIO24

GPIO16

GPIO17

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

BMBUSY*/GPIO76

SDIO_D3/GPIO69

SDIO_D2/GPIO68

SDIO_D1/GPIO67

I2C0_SDA/GPIO4

UART1_TXD/GPIO1

UART1_CTS*/GPIO3

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

GSPI0_MOSI/GPIO86

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85

GSPI0_CS*/GPIO83

RSVD RSVD

PCH_OPI_COMP

RCIN*/GPIO82

SERIRQ

GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART1_RST*/GPIO2

I2C1_SDA/GPIO6

I2C0_SCL/GPIO5

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66

SDIO_POWER_EN/GPIO70

DEVSLP0/GPIO33

DEVSLP1/GPIO38

DEVSLP2/GPIO39

THERMTRIP*

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

NC

OUT

NC

OUT

BI

OUT

IN

OUT

IN

OUT

IN

BI

IN

OUT

BI

OUT

IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SSD_LPSR:S0 BOM option is on R1620

Stuffed R1632

Pull-up on TBT page

TBTLC for CR, S0 for RR

(IPD)

(IPD-RSMRST#)

(IPD-DeepSx)

Requires connection to SMC via 1K series R

(IPD-PLTRST#)

Pull-up/down on chipset support page (depends on TBT controller) Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down. Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

GPIO12:

(IPD-PLTRST#)

platform does not use SD card

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

R1616 should also be stuffed if

No-Stuffed R1634

21

R1652

1/20W

5%

201

MF

10K

21

R1674

MF

201

5%

1/20W

100K

21

R1676

MF

201

5%

1/20W

100K

2

1

R1639

100K

201

MF

1/20W

5%

21

R1641

5% MF1K201

1/20W

21

R1629

5%

1/20W

MF

100K

201

2

1

R1621

201

MF

5%

100K

1/20W

13 15 16 18

18 25

15 37 64

G2

K4

J3

J4

K3

J1

J2

G1

D60

V2

T4

C4

E2

C3

E4

D3

F4

E3

AF20 AB21

V4

AW15

AM7

G4

F1

F2

F3

Y2

K2

N7

R7

L5

L8

N6

R6

L6

AM3

AU2

AT5

AL4

AP1

AG6

P3

Y3

U4

AB6

AG3

AG5

AK4

AD7

AN5

AN3

AM4

AD5

T3

Y1

AD6

AH4

AT3

AM2

N5

L2

P2

P1

U0500

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2

1

R1631

RAMCFG3:H

1/20W

5%

201

MF

100K

15 29

29

2

1

R1671

MF

1/20W

100K

5%

201

13 15 16 18

2

1

R1680

100K

201

MF

1/20W

5%

18 31

2

1

R1681

0201

MF

1/20W

5%

0

2

1

R1682

0

5% 1/20W MF 0201

15 36

21

R1668

MF

201

5%

1/20W

47K

2

1

R1636

1/20W

5%

201

MF

100K

RAMCFG2:H

21

R1669

47K

1/20W

5%

201

MF

21

R1670

MF

201

5%

1/20W

47K

21

R1677

47K

1/20W

5%

201

MF

21

R1672

MF

201

5%

1/20W

47K

21

R1673

47K

1/20W

5%

201

MF

21

R1675

MF

201

5%

1/20W

47K

15 18

15

21

R1678

201

1/20W

5%

2.2K

MF

21

R1679

MF

2.2K

5%

1/20W

201

2

1

R1635

100K

1/20W

MF

201

5%

RAMCFG1:H

15 18 19 33 36 40 41 58 62 64

2

1

R1696

201

MF

5%

100K

1/20W

SSD_LPSR:S3

2

1

R1611

5%

201

MF

1/20W

100K

RAMCFG0:H

26

15 64

39

15 16

15 16 18

15 16 64

15 36

18

15 30 58 59 64

15 64

15 34

15 25

15 16 18 25

15 18

15 58

15 46 64

15 18

15 30 64

15 29

30

15 37

15 34

15

38 67

15 16

15 16 18

18 25

15 36

15 16 33

15 36

15 36 68

2

1

R1650

201

MF

1/20W

1K

5%

15 36 68

21

R1610

100K

1/20W

5% MF

201

21

R1614

100K

5%

201

1/20W

MF

21

R1615

100K

1/20W

201

MF5%

21

R1616

SD_ON_MLB

1/20W

MF

201

5%

100K

21

R1617

201

MF5%

1/20W

100K

21

R1618

MF

201

5%

1/20W

100K

21

R1619

5% MF

1/20W

100K

201

21

R1620

SSD_LPSR:S0

MF5%

100K

201

1/20W

21

R1622

MF

201

1/20W

5%

100K

21

R1623

MF

100K

1/20W

5%

201

21

R1624

100K

5%

1/20W

201

MF

21

R1625

201

100K

1/20W

5% MF

21

R1626

1/20W

5%

100K

201

MF

21

R1627

MF

201

100K

1/20W

5%

21

R1628

100K

5% MF

201

1/20W

21

R1630

100K

1/20W

5%

201

MF

21

R1632

MF

201

5%

1/20W

100K

21

R1633

1/20W

5%

201

MF

100K

21

R1634

NOSTUFF

MF

201

5%

1/20W

100K

21

R1640

MF

201

5%

1/20W

100K

21

R1637

100K

5%

201

MF

1/20W

21

R1638

MF

201

5%

1/20W

100K

21

R1691

100K

MF

201

5%

1/20W

21

R1694

100K

1/20W

5%

201

MF

21

R1693

100K

1/20W

5%

201

MF

2

1

R1655

PLACE_NEAR=U0500.AW15:2.54mm

49.9

201

1% 1/20W MF

21

R1695

100K

1/20W

5%

201

MF

21

R1660

MF

201

5%

1/20W

100K

21

R1661

100K

MF

201

5%

1/20W

21

R1662

100K

1/20W

5%

201

MF

21

R1663

MF

201

5%

1/20W

100K

21

R1664

MF

201

5%

1/20W

47K

21

R1665

MF

201

5%

1/20W

47K

21

R1666

1/20W

5%

201

MF

47K

21

R1667

MF

201

5%

1/20W

47K

PCH GPIO/MISC/LPIO

SYNC_MASTER=WILL_J43 SYNC_DATE=01/14/2013

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

TPAD_SPI_INT_GPIO46_L

JTAG_ISP_TDO

PCH_UART1_CTS_L

PCH_UART1_RXD PCH_UART1_TXD

PCH_BT_UART_CTS_L

PCH_BT_UART_RTS_L

PCH_BT_UART_CTS_L

PCH_BT_UART_RTS_L

PCH_BT_UART_R2D

PCH_BT_UART_D2R

TPAD_SPI_INT_GPIO46_L

TPAD_SPI_INT_L

PP3V3_S5

SPIROM_USE_MLB

XDP_MLB_RAMCFG0

XDP_MLB_RAMCFG3

PP3V3_S0

PP3V3_S3

PP3V3_S0

BT_PWRRST_L

LPC_SERIRQ

XDP_FW_PME_L

PCH_HSIO_PWR_EN TPAD_SPI_IF_EN

CAMERA_PWR_EN_PCH

LCD_IRQ_L

ENET_MEDIA_SENSE

PP1V05_S0

XDP_MLB_RAMCFG2

XDP_MLB_RAMCFG1

LCD_PSR_EN

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

XDP_PCH_GPIO76

PP3V3_S0SW_SD

PP3V3_S3RS0_CAMERA

PP3V3_S3

JTAG_ISP_TDO

AP_S0IX_WAKE_L

AUD_SPI_CS_L AUD_SPI_CLK AUD_SPI_MISO AUD_SPI_MOSI

TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI

XDP_LPCPLUS_GPIO

SD_RESET_L

JTAG_TBT_TMS_PCH

TPAD_USB_IF_EN

XDP_SDCONN_STATE_CHANGE_L

PP3V3_S0

TBT_PWR_EN

SD_PWR_EN

SSD_PWR_EN

HDD_PWR_EN

SMC_WAKE_SCI_L

XDP_PCH_GPIO17

PM_THRMTRIP_L

SSD_SR_EN_L

AP_S0IX_WAKE_SEL

PCH_STRP_TOPBLK_SWP_L

BT_PWRRST_L

TBT_POC_RESET_L

PCH_BT_UART_R2D

TPAD_SPI_MOSI

TPAD_SPI_MISO

LPC_SERIRQ

TBT_CIO_PLUG_EVENT_L

PCH_OPI_COMP

AUD_SPI_CS_L

AUD_SPI_MISO

AUD_SPI_CLK

TPAD_SPI_CLK

TPAD_SPI_CS_L

AUD_SPI_MOSI

PCH_UART1_RXD

PCH_UART1_CTS_L

PCH_UART1_TXD

ENET_MEDIA_SENSE

LCD_IRQ_L

LCD_PSR_EN

XDP_PCH_GPIO76

XDP_MLB_RAMCFG0

HDMITBTMUX_SEL_TBT

TP_MEM_VDD_SEL_1V5_L

XDP_PCH_GPIO17

XDP_LPCPLUS_GPIO

SD_RESET_L

TPAD_SPI_INT_GPIO28_L

SMC_WAKE_SCI_L

TPAD_USB_IF_EN

PCH_TBT_PCIE_RESET_L

HDD_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

TBT_PWR_EN

SD_PWR_EN

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

JTAG_TBT_TMS_PCH

PCH_HSIO_PWR_EN

TPAD_SPI_IF_EN

SPIROM_USE_MLB

XDP_MLB_RAMCFG3

CAMERA_PWR_EN_PCH

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG2

PCH_TCO_TIMER_DISABLE

PCH_BT_UART_D2R

PCH_I2C1_SCL

PCH_I2C1_SDA

AP_S0IX_WAKE_L

PLT_RESET_L

AP_RESET_L

PLT_RESET_L

SSD_RESET_L

CAM_PCIE_RESET_L

PCH_I2C1_SDA

PP3V3_S0

PCH_I2C1_SCL

TPAD_SPI_INT_GPIO28_L

SSD_PWR_EN

PP3V3_S3

AP_S0IX_WAKE_SEL

PP3V3_S0

SSD_SR_EN_L

15 OF 76

<SCH_NUM>

16 OF 121

15

15 64

15

15 36

8

11 13 16 17 18 28 29 34 42 57

58 59 60 62 64 74

15 46 64

15 16 18

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

15 18 19 33 36 40 41 58 62 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

15 64

15 37 64

12 16

15 58

15 36

15 18

15 64

6 8

11 16 17 38 42 51 55 58

59 62 64

15 16 18

15 64

15 16 18 25

15 16

34 37 39 65

31 41

15 18 19 33 36 40 41 58 62 64

15 18

15 29

15 64

15 36

15 36 68

15 16 64

15 34

15 18

15 36

15 16 33

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

15 25

15 34

15 30 58 59 64

15 64

15 37

15 16

15 64

15

15 64

15

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

15

15 29

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44

45 56 59 61 62 64 65 74

15 30 64

w w w . c h i n a f i x . c o m

IN

IN IN

IN

OUT

IN

OUT

IN

OUT OUT

IN

NC NC

IN IN

IN

TP

OUT

IN

OUT

IN

OUT

IN

TP

OUT

IN

BI

OUT

TP

BI

TP

BI

TP

BI

IN

OUT

BI

IN

OUT

IN

OUT

BI

TP

IN

OUT

Y

NC NC

VCC

GND

A

NC

IN

NC

IN

TP

IN

TP

IN

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

OUT

TP

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

OBSFN_A0 OBSFN_A1

VCC_OBS_CD

Extra BPM Testpoints

support chipset debug.

OBSFN_C0

OBSDATA_C0

OBSFN_C1

OBSDATA_C1

OBSDATA_C3

OBSDATA_C2

OBSDATA_D0

OBSFN_D1

ITPCLK#/HOOK5

OBSDATA_D3

DBR#/HOOK7

XDP_PRESENT#

ITPCLK/HOOK4

TMS

TDI

OBSDATA_A0

OBSFN_B1

OBSDATA_A3

OBSDATA_A2

OBSFN_B0

OBSDATA_B0 OBSDATA_B1

HOOK3

HOOK1

SDA

TCK1

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to

OBSDATA_A1

OBSDATA_D2

SCL

OBSFN_D0

Merged (CPU/PCH) Micro2-XDP

TRSTn

TDO

HOOK2

TDI and TMS are terminated in CPU.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

Unused & MLB_RAMCFGx GPIOs have TPs.

SSD_PCIEx_SEL_L straps are connected via 1K to common net.

PCH/XDP Signals

RESET#/HOOK6

PCH XDP Signals

Non-XDP Signals

These signals do not connect to XDP connector in this architecture, only accessible via Top-Side Probe. Nets are listed here to show XDP associations and to make clear what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

NOTE: Must not short XDP pins together!

OBSDATA_B3

OBSDATA_D1

TCK0

CPU JTAG Isolation

518S0847

OBSDATA_B2

PWRGD/HOOK0

VCC_OBS_AB

6

13 15 18

6

67

6

64 67

6

67

6

67

6

67

6

67

13 37

13 17 37

12 16 64 69

17 67

6

12 16 64 69

21

R1805

5%

201

1/20W

MF

PLACE_NEAR=U0500.AG7:2.54mm

1K

XDP

12

R1813

5%

201

1/20W

MF

PLACE_NEAR=U0500.E60:28mm

51

XDP

21

R1804

5%

0

XDP

402

MF-LF1/16W

21

R1802

5%

0

0201

1/20W

MF

PLACE_NEAR=U5000.J3:2.54mm

XDP

21

R1800

5%

201

1/20W

MF

PLACE_NEAR=U0500.C61:2.54mm

XDP

1K

6

67

9

8 7

64 63

62

61

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1800

XDP_CONN

DF40RC-60DP-0.4V

CRITICAL

M-ST-SM1

6

67

6

67

6

67

6

67

6

67

6

67

6

67

6

67

6

67

6

67

1

TP1806

TP-P6

1

TP1807

TP-P6

1

TP1805

TP-P6

1

TP1804

TP-P6

1

TP1803

TP-P6

1

TP1802

TP-P6

8

2

1

R1830

5% 1/16W MF-LF 402

150

21

R1810

5%

201

1/20W

MF

PLACE_NEAR=U0500.F62:28mm

XDP

51

12 16 64 69

2

1

R1831

5%

XDP

MF-LF 402

1/16W

1K

12

R1896

5%

201

1/20W

MF

NO STUFF

PLACE_NEAR=U0500.AE62:28mm

51

12

R1892

5%

201

1/20W

MF

PLACE_NEAR=U0500.AD62:28mm

XDP

51

12

R1891

5%

201

1/20W

MF

PLACE_NEAR=U0500.AD61:28mm

XDP

51

12

R1890

5%

201

1/20W

MF

PLACE_NEAR=U0500.AE61:28mm

51

XDP

12

R1899

5%

201

1/20W

MF

NO STUFF

PLACE_NEAR=U0500.AE63:28mm

1K

21

R1835

5%

0

0201

1/20W

MF

PLACE_NEAR=J1800.58:28mm

XDP

12 16

6

12 16 64 67

6

64 67

6

64 67

6

16 64 67

2

1

C1801

XDP

6.3V CERM-X5R 0201

0.1UF

10%

15 16 33

14

14 16 61 65

6

67

14 16 61 65

1

TP1870

TP-P6

14 16 35 14 16 35

15 18

14

1

TP1874

TP-P6

2

1

C1800

XDP

6.3V

CERM-X5R

0201

0.1UF

10%

1

TP1876

TP-P6

15 18

1

TP1877

TP-P6

15 18

1

TP1878

TP-P6

15 18

15

15 16 18 25 15 16 18 25

12

6

64 67

21

R1884

5%

201

1/20W

MF

1K

15 16 64

6

64 67

15

15 16 18 25 15 16 18 25

15 16 64

1

TP1887

TP-P6

2

1

C1804

XDP

6.3V

CERM-X5R

0201

0.1UF

10%

2

1

C1806

XDP

6.3V CERM-X5R 0201

0.1UF

10%

6

67

6

12 16 64 67

12

R1897

5%

201

1/20W

MF

51

NO STUFF

PLACE_NEAR=U0500.AU62:28mm

4

6

5

1

3

2

U1845

SOT891

74LVC1G07GF

2

1

C1845

X5R-CERM

0201

16V

0.1UF

10%

6

67

2

1

R1845

5%

201

1/20W MF

330K

17 37 59

1

TP1873

TP-P6

15 16 33

1

TP1886

TP-P6

6

67

4

5

3

Q1842

PLACE_NEAR=J1800.55:28mm

DMN5L06VK-7

CRITICAL

XDP

SOT563

1

2

6

Q1842

SOT563

DMN5L06VK-7

CRITICAL

XDP

1

2

6

Q1840

DMN5L06VK-7

XDP

CRITICAL

SOT563

4

5

3

Q1840

PLACE_NEAR=J1800.51:28MM

SOT563

DMN5L06VK-7

XDP

CRITICAL

12 15

1

TP1879

TP-P6

1

TP1880

TP-P6

1

TP1881

TP-P6

6

67

14 19 40 56 69

6

16 64 67

6

8

17

6

67

6

67

SYNC_DATE=12/17/2012

CPU/PCH Merged XDP

SYNC_MASTER=WILL_J43

XDP_PCH_UART_SSD_L_BT_H

XDP_PCH_GPIO35

XDP_FW_PME_L

XDP_CPU_TDO

XDP_JTAG_CPU_ISOL_L

XDP_PCH_TDO

XDP_TRST_L

XDP_CPU_PRESENT_L

CPU_CFG<6> CPU_CFG<7>

CPU_PWR_DEBUG

PP1V05_S0

XDP_CPU_PWRBTN_L

XDP_BPM_L<0>

CPU_CFG<3>

XDP_CPU_PRDY_L

XDP_CPU_VCCST_PWRGD

XDP_CPURST_L XDP_DBRESET_L

XDP_JTAG_ISP_TCK

XDP_USB_EXTA_OC_L

XDP_SDCONN_STATE_CHANGE_L

XDP_MLB_RAMCFG3

PCH_JTAGX

PP3V3_S5

XDP_SYS_PWROK

XDP_CPU_PREQ_L

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<19> CPU_CFG<18>

CPU_CFG<13>

XDP_MLB_RAMCFG2

XDP_PCH_GPIO17

XDP_SSD_PCIE0_SEL_L

SMBUS_PCH_DATA

XDP_PCH_GPIO76

XDP_MLB_RAMCFG1

XDP_USB_EXTD_OC_L

XDP_USB_EXTC_OC_L

XDP_MLB_RAMCFG0

XDP_USB_EXTB_OC_L

XDP_CPU_TCK

XDP_PCH_TCK

CPU_CFG<11>

CPU_CFG<10>

XDP_CPUPCH_TRST_L

PLT_RESET_L

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<9>

CPU_CFG<8>

PM_PCH_SYS_PWROK

PM_PWRBTN_L

CPU_VCCST_PWRGD

XDP_PCH_TCK

SMBUS_PCH_CLK

CPU_CFG<5>

CPU_CFG<4>

XDP_BPM_L<1>

CPU_CFG<2>

CPU_CFG<0>

PP1V05_S0

XDP_PCH_TDO

XDP_CPU_TDO

XDP_PCH_TDI

PCH_JTAGX

PP1V05_SUS

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_CPU_TCK

CPU_CFG<1>

XDP_CPUPCH_TRST_L

XDP_PCH_TMS

PP5V_S0

ALL_SYS_PWRGD

XDP_JTAG_ISP_TDI

XDP_LPCPLUS_GPIO

XDP_PCH_TMS

XDP_CPU_TMS

XDP_PCH_TDI

XDP_CPU_TDI

XDP_LPCPLUS_GPIO

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_JTAG_ISP_TCK

XDP_SDCONN_STATE_CHANGE_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTA_OC_L

XDP_CPUPCH_TRST_L

MAKE_BASE=TRUE

16 OF 76

<SCH_NUM>

18 OF 121

6 8

11 15 16 17 38 42 51 55

58 59 62 64

64

67

8

11 13 15 17 18 28 29 34 42

57 58 59 60 62 64 74

64

12 16 64 69

6 8

11 15 16 17 38 42 51 55

58 59 62 64

12 16 64 69

6

16 64 67

12 16 64 69

12 16

57 62

6

16 64 67

6

12 16 64 67

12 16 64 69

17 32 45 51 52 56 58 59 61 62 64

6

12 16 64 67

w w w . c h i n a f i x . c o m

OUT

NC NC

OUT

IN

BIIN

OUT

IN

OUT

NC

NC NC

OUT

IN

NC

OUT

IN

NC

A Y

NC NC

VCC

GND

NC

IN

OUT

IN

OUT

IN

OUT

IN

YA

B

NC

GND

VCC

32.768K

GND

THRM

VOUT

X2 X1

25M_A 25M_B 25M_C

VIOE_25M_A VIOE_25M_B VIOE_25M_C

VG3HOT

NC

VDD

PAD

NC NC

VER 3

D

S G

VER 3

D

SG

Y

A

B

08

Y

A

B

08

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Must be powered if any VDDIO is powered.

available ~3.3V power

WF: Do we need this?

TPS51916 I(leak) = +/- 1uA, Vih(min) = 1.8V 33uW when driven-low

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

Memory VTT Enable Level-Shifter

SMC controls strap enable to allow in-field control of strap setting.

VCCST (1.05V S0) PWRGD

IPD = 9-50k

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

PCH Reset Button

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

CAM XTAL Power

PCH PWROK Generation

PCH 24MHz Outputs

No bypass necessary

No Coin-Cell: 3.3V S5

Coin-Cell & No G3Hot: 3.3V S5

TBT XTAL Power

GreenCLK 25MHz Power

PCH 24MHz Crystal

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell: VBAT (300-ohm & 10uF RC)

System RTC Power Source & 32kHz / 25MHz Clock Generator

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

VBAT and +V3.3A are internally ORed to create VDD_RTC_OUT.

+V3.3A should be first

to reduce VBAT draw.

For SB RTC Power

PCH ME Disable Strap

NOTE: 30 PPM or better required for RTC accuracy

pin 5 must receive S5 power (Stuff R2042)

new and old parts. With GreenCLK Rev C

This looks a little ugly to support

12

25 69

2

1

C1902

X5R

1UF

0201

20%

6.3V

2

1

C1910

0201

6.3V

20%

1UF

X5R

31

42

Y1905

SM-3.2X2.5MM

CRITICAL

25.000MHZ-12PF-20PPM

17 37 69

21

R1927

PLACE_NEAR=U0500.AN15:5.1mm

22

MF

1/20W

201

5%

12 69

13 37 64 16 67

2

1

C1924

0201

X5R-CERM

16V

10%

0.1UF

21

R1905

MF

1/20W

0201

0

5%

2

1

R1906

NO STUFF

1M

MF

1/20W

201

5%

21

R1996

XDP

MF

1/20W

0201

0

5%

2

1

R1997

402

1/16W MF-LF

SILK_PART=SYS RESET

NO STUFF

0

5%

2

1

R1995

10K

MF

1/20W

201

5%

2

1

R1920

100K

MF

1/20W 201

5%

2

1

R1921

1K

MF

1/20W 201

5%

12 69

37

2

1

C1922

0.1UF

10% 16V

0201

X5R-CERM

32 69

2

1

R1916

1M

MF

1/20W

201

5%

21

R1915

MF

1/20W

0201

0

5%

21

C1915

C0G

6.8PF

0201

+/-0.1PF

25V

21

C1916

6.8PF

0201

C0G

25V

+/-0.1PF

12

12 17

8

16

2

1

R1931

10K

MF

1/20W

201

5%

2

1

C1930

0201

16V

X5R-CERM

10%

0.1UF

13 18 37 59

2

1

R1970

330K

MF

1/20W

201

5%

4

6

5

1

3

2

U1970

SOT891

74AUP1G07GF

2

1

C1970

0.1UF

10% 16V

0201

X5R-CERM

6

17 53

26 27 37 38

16 17 37 59

2

1

C1950

X5R-CERM

10%

0201

16V

0.1UF

BYPASS=U1950:5MM

1

2

R1963

MF

1/20W

0201

0

5%

1

2

R1960

NO STUFF

MF

1/20W

0201

0

5%

21

R1962

1K

MF

1/20W

201

5%

13 16 37

13 17

21

R1951

NO STUFF

MF

1/20W

0201

0

5%

2

1

R1950

10K

MF

1/20W

201

5%

2

1

R1955

10K

MF

1/20W

201

5%

8

51

8

17 51

8

17 51

2

1

R1961

NO STUFF

100K

MF

1/20W

201

5%

4

6

5

3

1

2

U1930

74AUP1G09

SOT891

CRITICAL

3 4

1

14

6

11

13

5

17216107

12

15

8

9

U1900

SLG3NB148CV

CRITICAL

TQFN

CKPLUS_WAIVE=PwrTerm2Gnd

3 1

4 2

Y1915

CRITICAL

3.20X2.50MM-SM1

24.000MHZ-20PPM-6PF

4

5

3

Q1920

DMN5L06VK-7

SOT563

1

2

6

Q1920

SOT563

DMN5L06VK-7

2 1

C1905

0201

5%

25V

CERM

12PF

7

8

4

2

1

U1950

74LVC2G08GT/S505

SOT833

3

8

4

6

5

U1950

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

74LVC2G08GT/S505

21

C1906

0201

5%

25V

CERM

12PF

Chipset Support

SYNC_DATE=01/09/2013SYNC_MASTER=J43_MLB1

SYSCLK_CLK25M_X1

LPC_CLK24M_SMC

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_RTC_CLK32K_RTCX2

MEMVTT_PWR_EN

MAKE_BASE=TRUE

CPU_VR_READY

PM_PCH_PWROK

MAKE_BASE=TRUE

SYS_PWROK_R

SMC_DELAYED_PWRGD

PM_S0_PGOOD

CPUVR_PGOOD_R

ALL_SYS_PWRGD

PP3V42_G3H

SPI_DESCRIPTOR_OVERRIDE_L

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE

PP1V5_S0SW_AUDIO_HDA

PP3V3_S5

PP3V3_S5RS3RS0_SYSCLKGEN

NC_RTC_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PP3V3_TBTLC

PP3V42_G3H

PP1V2_CAM_XTALPCIEVDD

PCH_CLK24M_XTALOUT_R

PCH_CLK24M_XTALIN

PM_SLP_S3_L

ALL_SYS_PWRGD

PP3V3_S5

CPU_VCCST_PWRGD

PP1V05_S0

CPU_VR_EN

CPU_VR_READY

XDP_DBRESET_L

PM_SYSRST_L

PP3V3_S0

HDA_SDOUT_R

PCH_CLK24M_XTALOUT

LPC_CLK24M_SMC_R

PP5V_S0

CPU_MEMVTT_PWR_EN_LSVDDQ

PP1V2_S3

PP3V3_S0

MEMVTT_PWR_EN

PM_PCH_SYS_PWROK

PM_PCH_PWROK

PP3V3_S0

LPC_CLK24M_SMC

PPVRTC_G3H

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_CAMERA SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_X2

<SCH_NUM>

19 OF 121

17 OF 76

69

17 37 69

12 17

17 53

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

8

11 58

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

18

18 25 26 62 64

17 30 35 36 37 38 40 46 49 50 59 61 62 64 65

31

16 17 37 59

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

6 8

11 15 16 38 42 51 55 58 59

62 64

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

16 32 45 51 52 56 58 59 61 62 64

19 20 21 22 23 42 53 62 70

8

11 12 13 15 17 18 26 30 36 38

39 40 41 42 43 44 45 56 59 61

62 64 65 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

8

12 13 62 64

69 69

w w w . c h i n a f i x . c o m

OUT

IN

IN IN IN IN

IN OUT OUT

BI

OUT

BI

OUT IN IN

IN

OUT

IN

OUT

IN

IN BI

BIBI

NC

08

NC

OUT

IN

OUT OUT

IN IN

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

OUT

VCC

1A 1Y

2A 2Y

GND

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

No MAKE_BASE on TCK/TDI as these are provided on XDP page.

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC (on TBT page)

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

Falcon Ridge PLUG_EVENT is active-low, always driven (pull-up)

NOTE: Only DDC_DATA is sensed by PCH, so

Unbuffered

to indicate active display interface.

DDC_CLK pull-ups are unstuffed.

LPDDR3 Alias Support

MAKE_BASE

DDC Pull-Ups

GreenCLK 25MHz Power

R2041/2 should be stuffed for

DP++ spec violation, should remove!

TBTSNK1_DDC is pulled-up just to indicate that DP port is used. No DDC on this port, AUX-only.

2.2k pull-ups are required by PCH

Required for unused second TBT port

R2042 should be stuffed for GreenCLK C

GreekCLK A or B depending on S2 rail

Buffered

TBT Aliases

MAKE_BASE

Scrub for Layout Optimization

Platform Reset Connections

Pull-downs for chip-down RAM systems

RAM Configuration Straps

Single-port TBT implementation does not require DDC Crossbar

MAKE_BASE

Thunderbolt Pull-up/downs

(For development only)

Power State Debug LEDs

To RR

To PCH

S0 pull-up on PCH page

Redwood Ridge JTAG Isolation

TBTLC can be on when S0 is off, and vice-versa

Isolation ensures no leakage to RR or PCH

S0 pull-up on PCH page

From PCH

From RR

and TDI as well for PCH glitch-prevention.

different isolation techniques will likely be necessary.

Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK

Pin N61 needs a TP for Power to perform iFDIM test

Renaming the pins N61 and P61 to remove automatic diffpari property

2

1

R2022

5%

201

1/20W

MF

NO STUFF

2.2K

2

1

R2023

5%

201

1/20W MF

2.2K

2

1

R2020

5%

201

1/20W

MF

2.2K

NO STUFF

2

1

R2021

5%

201

1/20W MF

2.2K

2

1

R2050

5%

201

1/20W

MF

RAMCFG3:L

10K

2

1

R2051

5%

201

1/20W

MF

RAMCFG2:L

10K

2

1

R2052

5%

201

1/20W

MF

RAMCFG1:L

10K

2

1

R2053

5%

201

1/20W

MF

RAMCFG0:L

10K

2

1

R2016

5%

201

1/20W

MF

10K

2

1

R2017

5%

201

1/20W MF

10K

2

1

R2018

5%

201

1/20W

MF

10K

2

1

R2019

5%

201

1/20W MF

10K

2

1

R2014

5%

201

1/20W MF

10K

K

A

D2090

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S5_ON

K

A

D2091

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=STBY_ON

2

1

R2090

5%

201

1/20W

MF

DBGLED

20K

2 1

R2094

5%

0

402

MF-LF

1/16W

PLACE_SIDE=BOTTOM

DBGLED

2

1

R2091

5%

201

1/20W

MF

DBGLED

20K

K

A

D2092

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S3_ON

GREEN-56MCD-2MA-2.65V LTQH9G-SM

2

1

R2092

5%

201

1/20W

MF

DBGLED

20K

K

A

D2093

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON

DBGLED

2

1

R2093

5%

201

1/20W

MF

DBGLED

20K

15 16

25

6

18

15 18

28 58 59

13 18 29 36 37 59

13 17 37 59

2

1

R2095

5%

201

1/20W

MF

20K

DBGLED

K

A

D2095

GREEN-56MCD-2MA-2.65V LTQH9G-SM

PLACE_SIDE=BOTTOM

DBGLED

SILK_PART=S0_ON

13 37

13 18 25

5

25 67

5

25 67

13 18 28

13 18 25 67

13 18 28

13 18

13 18 25 67

13 18 25

13 18

2

1

C2071

10% 16V

0.1UF

X5R-CERM 0201

5

4

1

2

3

U2071

SC70-HF

CRITICAL MC74VHC1G08

2

1

R2070

5%

201

1/20W MF

100K

21

R2088

5%

0

0201

1/20W

MF

21

R2072

5%

0

0201

1/20W

MF

13 15 16

21

R2071

5%

0

0201

1/20W

MF

56

37

19

15 18 25 15 18 25

21

R2089

5%

0

0201

1/20W

MF

NOSTUFF

15 31

15 18 25 15 18 25

21

R2040

5%

0

0201

1/20W

MF

NO STUFF

21

R2041

5%

0

0201

1/20W

MF

NO STUFF

13 18 28

15 18 25 15 18 25

4

6

5 3

1

2

U2030

CRITICAL

74LVC1G08

SOT891

NOSTUFF

2

1

C2030

NOSTUFF

0.1UF

BYPASS=U2030:3mm

0201

X5R-CERM

10% 10V

21

R2030

5%

0

0201

1/20W

MF

31

15

13 18 29 36 37 59

21

R2042

5%

0

0201

1/20W

MF

15 16 18 25

1

2

6

Q2090

DBGLED

DMN5L06VK-7

SOT563

4

5

3

Q2090

DBGLED

DMN5L06VK-7

SOT563

1

2

6

Q2091

SOT563

DMN5L06VK-7

DBGLED

4

5

3

Q2091

SOT563

DMN5L06VK-7

DBGLED

2

1

R2015

100K

MF

1/20W

201

5%

15

25

2

1

R2062

100K

1/20W 201

5%

MF

52

4

3

6

1

U2060

SOT891

74LVC2G07

2

1

C2060

10V

20%

402

CERM

0.1UF

2

1

R2061

1/20W

100K

5%

201

MF

25

15

2

1

R2010

100K

1/20W 201

5%

MF

14 39

SYNC_MASTER=J43_MLB

Project Chipset Support

SYNC_DATE=01/17/2013

PCH_SML1ALERT_L

PP3V3_SUS

TP_CPU_RSVDN61

MAKE_BASE=TRUE

TP_CPU_RSVDN61

MAKE_BASE=TRUE

TP_CPU_RSVDP61TP_CPU_RSVDP61

JTAG_TBT_TMS_PCH

PP3V3_TBTLC

JTAG_TBT_TDO JTAG_ISP_TDO

JTAG_TBT_TMS

PM_SLP_S4_L

CAMERA_PWR_EN_PCH

CAMERA_PWR_EN

PP3V3_S5

PM_SLP_S0_L

DBGLED_S0_D

PM_SLP_S3_L

DBGLED_S0I3_D

PM_SLP_S4_L

DBGLED_S3_D

S4_PWR_EN

DBGLED_S4_D

PP3V3_S5

TRUE

DP_TBTSNK1_HPD DP_TBTSNK1_ML_C_P<3..0>

TRUE

=DP_TBTSNK1_ML_C_P<3..0> =DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_DATA

PP3V3_S5_DBGLED

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=3.3V

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5RS3RS0_SYSCLKGEN

BKLT_PLT_RST_L

TRUE

DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK1_HPD

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

TRUE

PCH_TBT_PCIE_RESET_L

CAM_PCIE_RESET_L

SMC_LRESET_L

PCH_TBT_PCIE_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

PP3V3_S0

PLT_RESET_L

PCA9557D_RESET_L

DP_TBTSNK0_DDC_DATA

PP3V3_S3

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK

PP3V3_S0

PP3V3_S5RS3RS0_SYSCLKGEN

HDMITBTMUX_SEL_TBT

XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1

TBT_CIO_PLUG_EVENT_L

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_DDC_DATA

TRUE

DP_TBTSNK1_DDC_DATA

TRUE

DP_TBTSNK1_DDC_CLK

TRUE

DP_TBTSNK1_AUXCH_C_P

TRUE

DP_TBTSNK0_DDC_CLK

TBT_B_CONFIG1_BUF

TBT_B_CONFIG2_RC

DP_TBTPB_HPD

TBT_B_CIO_SEL

PP0V6_S3_MEM_VREFCA_B PP0V6_S3_MEM_VREFCA_B

VOLTAGE=0.6V

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_B PP0V6_S3_MEM_VREFDQ_B

VOLTAGE=0.6V

MAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5_L

TP_CPU_MEM_RESET_L

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_A

VOLTAGE=0.6V

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_A

VOLTAGE=0.6V

MAKE_BASE=TRUE

PP0V6_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

TP_MEM_VDD_SEL_1V5_L

MAKE_BASE=TRUE

TP_CPU_MEM_RESET_L

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG2

DP_TBTSNK1_DDC_CLK

DBGLED_S0

DBGLED_S0I3

DBGLED_S5

DP_TBTSNK0_DDC_CLK

TRUE

DP_TBTSNK1_DDC_CLK

XDP_JTAG_ISP_TCKXDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI XDP_JTAG_ISP_TDI

PP3V3_S5

DBGLED_S3DBGLED_S4

TBT_CIO_PLUG_EVENT_L

TRUE

PP3V3_S0

TBT_B_LSRX

HDMITBTMUX_SEL_TBT

TRUE

<SCH_NUM>

20 OF 121

18 OF 76

8

11 14 46 57 58 59 62 64

8

18

8

18

8

18

8

18

17 25 26 62 64

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

8

11 13 15 16 17 18 28 29 34

42 57 58 59 60 62 64 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

17 18

8

11 12 13 15

17 18 26 30 36

38 39 40 41 42

43 44 45 56 59

61 62 64 65 74

13 18 28

15 19 33 36 40 41 58 62 64

13 18

13 18 28

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

17 18

13 18

18 19 22 23 70 18 19 22 23 70

18 19 20 21 70 18 19 20 21 70

15 18

6

18

13 18

8

11 13

15 16 17

18 28 29

34 42 57

58 59 60

62 64 74

8

11 12 13 15 17 18 26 30 36

38 39 40 41 42 43 44 45 56 59

61 62 64 65 74

25

w w w . c h i n a f i x . c o m

OUT

V-

V+

V-

V+

IN

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

VER 3

D

S G

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VRef Dividers

of margining option.

+21uA - -21uA (- = sourced)

0.000V - 2.397V (0x00 - 0xBA)

0.800V - 1.600V (+/- 400mV)

NOTE: Margining will be disabled across all

Always used, regardless

Addr=0x98(WR)/0x99(RD)

NOTE: CPU DAC output step sizes: DDR3 (1.5V) 7.70mV per step

FETs for CPU isolation during DAC margining

R22x6 pin 2:

Q2265 pin 6:

to remove short due to CPU.

and disables margining after platform reset.

DAC sets voltage level, PCA9557 & FETs enable outputs

Addr=0x30(WR)/0x31(RD)

soft-resets and sleep/wake cycles.

watchdog will disable margining.

RST* on ’platform reset’ so that system

3.53mV / step @ output

+25uA - -25uA (- = sourced)

1.343V (DAC: 0x68)

0.972V - 1.714V (+/- 371mV)

DDR3L (1.35V)

DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider

1.200V (DAC: 0x5D)

5

D

MEM VREG

LPDDR3 (1.2V)

DAC Channel:

PCA9557D Pin:

MEM A VREF DQ

1

A B

2

MEM A VREF CA

C

3

MEM B VREF CA

DDR3L (1.35V)

C

4

6.36mV / step @ output

+82uA - -82uA (- = sourced)

DAC output, cannot enable

NOTE: MEMVREG and SPARE share a

(All 4 R’s)

+73uA - -73uA (- = sourced)

0.600V (DAC: 0x2E.5)

0.675V (DAC: 0x34)

Margined target:

0.300V - 0.900V (+/- 300mV)

0.000V - 1.199V (0x00 - 0x5D)

CPU-Based Margining

margining support. When

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

Pins B1 & B4:

both at the same time!

(OD)

Q2225 pin 6:

DDR3L (1.35V) 6.99mV per step

VREFMRGN_CPU_EN is low

VREFCA. Split into two

- =I2C_VREFDACS_SCL

DAC range:

Nominal value

VRef current:

DAC step size:

- =PP3V3_S3_VREFMRGN

- =PPDDR_S3_MEMVREF

- =I2C_VREFDACS_SDA

0.000V - 2.694V (0x00 - 0xD1)0.000V - 1.354V (0x00 - 0x69)

BOM options provided by this page:

- DDRVREF_DAC - Stuffs DAC margining circuit.

EN RC’s to avoid drain glitches May not be necessary due to C22x0

LPDDR3 (1.2V) ?.??mV per step

DAC margining VREFCA ensure

LPDDR3 (1.2V)

4.28mV / step @ output

DAC-Based Margining

signals for independent DAC

NOTE: CPU has single output for

MEM B VREF DQ

0.337V - 1.013V (+/- 337.5mV)

6.36mV / step @ output

53

2

1

C2202

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

21

R2214

201

PLACE_NEAR=R7415.2:1mm

1%

DDRVREF_DAC

1/20W

MF

38.3K

2

1

R2213

201

5%

100K

1/20W

MF

DDRVREF_DAC

2

1

R2212

201

5%

100K

1/20W

MF

DDRVREF_DAC

B4

B1

A4

A1

A2

A3

U2204

CKPLUS_WAIVE=unconnected_pinsCKPLUS_WAIVE=unconnected_pins

MAX4253

UCSP

CRITICAL DDRVREF_DAC

B4

B1

C4

C1

C2

C3

U2204

UCSP

DDRVREF_DAC

MAX4253

CRITICAL

21

R2218

SHORT

NONE NONE

NONE

OMIT

402

18

7

2

1

R2202

201

1/20W

5%

MF

DDRVREF_DAC

100K

7

2

1

R2201

201

100K

DDRVREF_DAC

5%

1/20W

MF

21

R2225

201

1/20W

5%

MF

DDRVREF_DAC

100K

2

1

C2225

10%

6.3V

DDRVREF_DAC

0.1UF

0201

CERM-X5R

2

1

C2245

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

21

R2245

201

MF

1/20W

DDRVREF_DAC

5%

100K

21

R2265

201

MF

1/20W

5%

DDRVREF_DAC

100K

2

1

C2265

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

2

1

C2285

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

2

1

R2215

201

100K

5%

1/20W

MF

DDRVREF_DAC

21

R2285

201

DDRVREF_DAC

MF

1/20W

5%

100K

2

1

R2207

201

DDRVREF_DAC

100K

5%

1/20W

MF

21

R2226

201

1%

1/20W

MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2225.1:2.54mm

21

R2246

201

1%

1/20W

MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2265.1:2.54mm

21

R2266

201

1%

1/20W

MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2225.4:2.54mm

21

R2286

201

1%

1/20W

MF

4.02K

DDRVREF_DAC

PLACE_NEAR=Q2265.4:2.54mm

2

1

R2217

201

MF

1/20W

5%

DDRVREF_DAC

1M

2

1

R2200

201

100K

5%

1/20W

MF

2

1

R2221

201

PLACE_NEAR=Q2220.6:3mm

MF

1%

8.2K

1/20W

21

R2280

201

MF

1/20W

1%

24.9

2

1

C2280

10%

0.022UF

0201

X5R-CERM

6.3V

PLACE_NEAR=Q2260.3:2mm

21

R2283

201

MF

1/20W

10

1%

2

1

R2281

201

PLACE_NEAR=Q2260.3:3mm

1%

8.2K

1/20W MF

2

1

R2282

201

1%

8.2K

1/20W

MF

PLACE_NEAR=R2281.2:1mm

2

1

R2262

201

PLACE_NEAR=R2261.2:1mm

1%

8.2K

1/20W

MF

21

R2260

201

MF

1/20W

1%

24.9

21

R2263

201

MF

1/20W

10

1%

2

1

C2260

10%

0.022UF

0201

X5R-CERM

6.3V

PLACE_NEAR=Q2220.3:2mm

2

1

R2261

201

PLACE_NEAR=Q2220.3:3mm

1%

8.2K

1/20W MF

2

1

R2242

201

PLACE_NEAR=R2241.2:1mm

1%

8.2K

1/20W

MF

21

R2240

201

MF

1/20W

1%

24.9

21

R2243

201

10

MF

1/20W

1%

2

1

C2240

6.3V X5R-CERM 0201

0.022UF

10%

PLACE_NEAR=Q2260.6:2mm

2

1

R2241

201

8.2K

PLACE_NEAR=Q2260.6:3mm

1% 1/20W MF

21

R2223

201

1/20W

MF

10

1%

2

1

R2222

201

PLACE_NEAR=R2221.2:1mm

1%

8.2K

MF

1/20W

21

R2220

201

MF

1/20W

1%

24.9

2

1

C2220

10%

0.022UF

0201

X5R-CERM

6.3V

PLACE_NEAR=Q2220.6:2mm

4

5

3

Q2265

SOT563

DMN5L06VK-7

DDRVREF_DAC

CRITICAL

1

2

6

Q2265

PLACE_NEAR=Q2260.6:2.54mm

SOT563

CRITICAL

DDRVREF_DAC

DMN5L06VK-7

4

5

3

Q2225

SOT563

DMN5L06VK-7

DDRVREF_DAC

CRITICAL

1

2

6

Q2225

CRITICAL

DDRVREF_DAC

DMN5L06VK-7

SOT563

PLACE_NEAR=Q2220.6:2.54mm

1

2

6

Q2220

CRITICAL

DMN5L06VK-7

SOT563

1

2

6

Q2260

SOT563

CRITICAL

DMN5L06VK-7

4

5

3

Q2220

SOT563

CRITICAL

DMN5L06VK-7

4

5

3

Q2260

SOT563

CRITICAL

DMN5L06VK-7

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2201

DDRVREF_DAC

CRITICAL

QFN

PCA9557

14 16 19 40 56 69

5

4

2

1

8

7

6

3

10

9

U2200

MSOP

DDRVREF_DAC

CRITICAL

DAC5574

14 16 19 40 56 69

2

1

C2201

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

2

1

C2200

6.3V

20%

CERM

2.2UF

DDRVREF_DAC

402-LF

2

1

C2205

10%

6.3V

0.1UF

0201

CERM-X5R

DDRVREF_DAC

SYNC_DATE=02/12/2013

DDR3 VREF MARGINING

SYNC_MASTER=J41_MLB

PP3V3_S3

VREFMRGN_SPARE_BUF

VREFMRGN_MEMVREG_BUF

MEM_VREFCA_A_RC

MEM_VREFDQ_B_RC

SMBUS_PCH_CLK

SMBUS_PCH_DATA

DDRREG_FB

MEM_VREFCA_B_RC

VREFMRGN_DQ_A

VREFMRGN_CA_AB

PP1V2_S3

VREFMRGN_DQ_B

VREFMRGN_MEMVREG

MEM_VREFDQ_A_RC

PCA9557D_RESET_L

SMBUS_PCH_CLK SMBUS_PCH_DATA

VREFMRGN_DQ_A_EN VREFMRGN_DQ_B_EN

VREFMRGN_MEMVREG_EN

VREFMRGN_CA_A_EN VREFMRGN_CA_B_EN

VREFMRGN_SPARE_EN

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP0V6_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V6_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V6_S3_MEM_VREFDQ_A

VREFMRGN_CA_B_EN_RC

VREFMRGN_CA_B_RDIV

VREFMRGN_DQ_B_EN_RC

VREFMRGN_DQ_B_RDIV

VREFMRGN_CA_A_EN_RC

VREFMRGN_CA_A_RDIV

VREFMRGN_DQ_A_EN_RC

VREFMRGN_DQ_A_RDIV

CPU_MEM_VREFDQ_A_ISOL

CPU_DIMMA_VREFDQ

CPU_MEM_VREFDQ_B_ISOL

CPU_DIMMB_VREFDQ

CPU_MEM_VREFCA_B_ISOL

CPU_MEM_VREFCA_A_ISOL

VREFMRGN_CPU_EN

CPU_DIMM_VREFCA

<SCH_NUM>

22 OF 121

19 OF 76

15 18 19 33 36 40 41 58 62 64

17 20 21 22 23 42 53 62 70

18 22 23 70

18 20 21 70

w w w . c h i n a f i x . c o m

BI BI BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10uF caps are shared between DRAM.

PLACEMENT_NOTE:

LPDDR3 CHANNEL A (0-31)

Distribute evenly.

63

2

1

C2306

10UF

20% 25V X5R-CERM 0603

2

1

C2307

25V

0603

10UF

20%

X5R-CERM

2

1

C2302

402

10V X5R

1UF

10%

63

2

1

C2300

10%

0.1UF

X5R-CERM

16V

0201

2

1

C2303

402

10V X5R

1UF

10%

2

1

C2304

10V X5R 402

1UF

10%

2

1

C2301

10%

0.1UF

0201

X5R-CERM

16V

2

1

C2305

10V X5R 402

1UF

10%

63

2

1

C2310

10V X5R 402

1UF

10%

2

1

C2311

10V X5R 402

1UF

10%

2

1

C2312

25V

0603

10UF

20%

X5R-CERM

2

1

C2320

10%

1UF

402

X5R

10V

2

1

C2321

10%

1UF

402

X5R

10V

2

1

C2322

10%

1UF

402

X5R

10V

63

2

1

C2324

X5R-CERM

20%

10UF

0603

25V

2

1

C2323

X5R-CERM

20%

10UF

0603

25V

2

1

C2333

10UF

20%

0603

25V X5R-CERM

2

1

C2332

25V

0603

10UF

20%

X5R-CERM

2

1

C2331

10%

1UF

402

X5R

10V

2

1

C2330

10%

1UF

X5R

10V

402

63

2

1

C2341

0.047UF

201

10%

X5R

6.3V

2

1

C2340

201

0.047UF

X5R

6.3V

10%

63

24 63 70

7

24 63 70

63

24 63 70

7

24 70

7

24 70

7

24 70

7

24 70

7

21 24 70

7

21 24 70

7

21 24 63 70

63

2

1

R2300

201

MF

1/20W

1%

243

2

1

R2301

1%

243

1/20W

MF

201

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2300

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2300

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

63

LPDDR3 DRAM Channel A (0-31)

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

PP1V2_S3

MEM_A_CAA<1>

MEM_A_CAA<3>

MEM_A_CKE<0>

PP1V8_S3

MEM_A_ODT<0>

MEM_A_CS_L<1>

=MEM_A_DQ<0> =MEM_A_DQ<1> =MEM_A_DQ<2>

=MEM_A_DQ<5> =MEM_A_DQ<6> =MEM_A_DQ<7> =MEM_A_DQ<8> =MEM_A_DQ<9>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<12>

=MEM_A_DQ<21>

=MEM_A_DQ<26>

=MEM_A_DQ<28>

=MEM_A_DQ<27>

=MEM_A_DQ<29> =MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<2> =MEM_A_DQS_N<3>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<1>

=MEM_A_DQS_P<3>

=MEM_A_DQ<19>

=MEM_A_DQS_N<1>

=MEM_A_DQ<3>

PP1V2_S3

=MEM_A_DQS_P<0>

=MEM_A_DQ<25>

PP1V2_S3

=MEM_A_DQ<17>

=MEM_A_DQ<24>

MEM_A_CAA<0>

MEM_A_CAA<2>

=MEM_A_DQ<20>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<18>

=MEM_A_DQ<16>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

PP1V2_S3

=MEM_A_DQ<4>

MEM_A_CAA<6>

MEM_A_CAA<9>

PP1V8_S3

MEM_A_CAA<4>

MEM_A_CAA<8>

MEM_A_CKE<1>

MEM_A_CLK_P<0>

MEM_A_CAA<7>

MEM_A_CAA<5>

MEM_A_CS_L<0>

MEM_A_CLK_N<0>

MEM_A_ZQ<1>

PP0V6_S3_MEM_VREFDQ_A

PP0V6_S3_MEM_VREFCA_A

MEM_A_ZQ<0>

PP1V2_S3

23 OF 121

<SCH_NUM>

20 OF 76

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

18 19 21 70

17 19 20 21 22 23 42 53 62 70

w w w . c h i n a f i x . c o m

BI BI

IN

BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Distribute evenly.

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

LPDDR3 CHANNEL A (32-63)

63

2

1

C2423

25V

0603

10UF

20%

X5R-CERM

2

1

C2403

10%

1UF

402

X5R

10V

2

1

C2404

10%

1UF

402

X5R

10V

2

1

C2405

10%

1UF

402

X5R

10V

2

1

C2406

0603

X5R-CERM

25V

20%

10UF

63

7

20 24 63 70

2

1

R2400

243

1%

1/20W

MF

201

2

1

R2401

201

MF

1/20W

243

1%

2

1

C2440

6.3V X5R

0.047UF

201

10%

63

2

1

C2441

6.3V X5R

10%

0.047UF

201

63

7

63 70

63

7

63 70

7

63 70

63

24 63 70

7

24 63 70

63

24 63 70

7

24 70

7

24 70

7

24 70

7

24 70

7

20 24 70

7

20 24 70

63

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2400

OMIT_TABLE

FBGA

EDFA232A1MA-GD-F

CRITICAL

LPDDR3-16GB

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2400

FBGA

EDFA232A1MA-GD-F

LPDDR3-16GB

CRITICAL

OMIT_TABLE

2

1

C2430

10V X5R 402

1UF

10%

2

1

C2431

10V X5R 402

1UF

10%

2

1

C2410

10%

1UF

402

X5R

10V

2

1

C2411

10%

1UF

402

X5R

10V

63

2

1

C2432

X5R-CERM

20%

10UF

0603

25V

2

1

C2412

10UF

X5R-CERM

20%

0603

25V

2

1

C2420

10V X5R 402

1UF

10%

2

1

C2400

10%

0.1UF

X5R-CERM

16V

0201

2

1

C2421

10V X5R 402

1UF

10%

2

1

C2401

0.1UF

16V X5R-CERM

10%

0201

2

1

C2422

10V X5R 402

1UF

10%

2

1

C2402

10V

10%

1UF

402

X5R

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

LPDDR3 DRAM Channel A (32-63)

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

MEM_A_ZQ<3>

MEM_A_ZQ<2>

MEM_A_ODT<0>

MEM_A_CS_L<0>

MEM_A_CKE<3>

MEM_A_CKE<2>

MEM_A_CAB<5>

MEM_A_CAB<3>

MEM_A_CAB<2>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_CAB<4>

PP1V2_S3

PP1V8_S3

PP1V2_S3

PP1V8_S3

PP1V2_S3

MEM_A_CS_L<1>

=MEM_A_DQ<32> =MEM_A_DQ<33>

=MEM_A_DQ<35>

=MEM_A_DQ<34>

=MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<38> =MEM_A_DQ<39> =MEM_A_DQ<40> =MEM_A_DQ<41>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

MEM_A_DQ<33> =MEM_A_DQ<46> =MEM_A_DQ<47> =MEM_A_DQ<48> =MEM_A_DQ<49> =MEM_A_DQ<50> =MEM_A_DQ<51> =MEM_A_DQ<52> =MEM_A_DQ<53> =MEM_A_DQ<54> =MEM_A_DQ<55> =MEM_A_DQ<56> =MEM_A_DQ<57> =MEM_A_DQ<58>

=MEM_A_DQ<60>

=MEM_A_DQ<59>

=MEM_A_DQ<61> =MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<4>

MEM_A_DQS_N<6> =MEM_A_DQS_N<7>

=MEM_A_DQS_P<4>

MEM_A_DQS_P<6>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<7>

MEM_A_CLK_N<1>

=MEM_A_DQ<44>

MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9>

MEM_A_CLK_P<1>

<SCH_NUM>

21 OF 76

24 OF 121

18 19 20 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

w w w . c h i n a f i x . c o m

BI BI

IN

BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

LPDDR3 CHANNEL B (0-31)

63

2

1

C2523

25V

0603

10UF

20%

X5R-CERM

2

1

C2503

10%

1UF

402

X5R

10V

2

1

C2504

10%

1UF

402

X5R

10V

2

1

C2505

10%

1UF

402

X5R

10V

2

1

C2506

0603

X5R-CERM

25V

20%

10UF

63

7

23 24 63 70

2

1

R2500

201

MF

1/20W

1%

243

2

1

R2501

1%

243

1/20W

MF

201

2

1

C2540

201

0.047UF

X5R

6.3V

10%

2

1

C2541

201

0.047UF

10%

X5R

6.3V

63

24 63 70

7

24 63 70

63

24 63 70

7

24 70

7

24 70

7

24 70

7

24 70

7

23 24 70

7

23 24 70

63

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2500

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2500

EDFA232A1MA-GD-F

LPDDR3-16GB

FBGA

CRITICAL

OMIT_TABLE

2

1

C2530

10V X5R 402

1UF

10%

2

1

C2531

10V X5R 402

1UF

10%

2

1

C2510

10%

1UF

402

X5R

10V

2

1

C2511

10%

1UF

402

X5R

10V

63

2

1

C2532

X5R-CERM

20%

10UF

0603

25V

2

1

C2512

X5R-CERM

20%

10UF

0603

25V

2

1

C2520

10V X5R 402

1UF

10%

2

1

C2500

10%

0.1UF

X5R-CERM

16V

0201

2

1

C2521

10V X5R 402

1UF

10%

2

1

C2501

16V X5R-CERM

0.1UF

10%

0201

2

1

C2522

10V X5R 402

1UF

10%

2

1

C2502

10%

1UF

402

X5R

10V

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

LPDDR3 DRAM Channel B (0-31)

PP1V8_S3

PP1V2_S3

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

MEM_B_CKE<0> MEM_B_CKE<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<0>

PP1V8_S3

PP1V2_S3

MEM_B_CS_L<1>

=MEM_B_DQ<0> =MEM_B_DQ<1>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<4> =MEM_B_DQ<5> =MEM_B_DQ<6> =MEM_B_DQ<7> =MEM_B_DQ<8> =MEM_B_DQ<9>

=MEM_B_DQ<11>

=MEM_B_DQ<10>

=MEM_B_DQ<12> =MEM_B_DQ<13> =MEM_B_DQ<14> =MEM_B_DQ<15> =MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQ<18> =MEM_B_DQ<19> =MEM_B_DQ<20> =MEM_B_DQ<21> =MEM_B_DQ<22> =MEM_B_DQ<23> =MEM_B_DQ<24> =MEM_B_DQ<25> =MEM_B_DQ<26>

=MEM_B_DQ<28>

=MEM_B_DQ<27>

=MEM_B_DQ<29> =MEM_B_DQ<30> =MEM_B_DQ<31>

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<2> =MEM_B_DQS_N<3>

=MEM_B_DQS_P<0>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<3>

MEM_B_ODT<0>

MEM_B_ZQ<0> MEM_B_ZQ<1>

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_B

22 OF 76

25 OF 121

<SCH_NUM>

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

18 19 23 70

w w w . c h i n a f i x . c o m

BI

IN

BI BI BI BI

BI

NC

IN IN IN IN IN IN IN IN

BI

IN IN

BI

(1 OF 2)

CA5

CK_T

CKE1

CK_C

DM1

CA0 CA1 CA2 CA3 CA4

CA6 CA7 CA8 CA9

CKE0

DM0

DM2 DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C

DQS0_T

DQS1_C

DQS1_T

DQS2_C

DQS2_T

DQS3_C

DQS3_T

NC

ODT

VREFCA VREFDQ

ZQ0 ZQ1

CS0* CS1*

NU

VDDCA

VDDQ

VSS

VSSCA

VSSQ

VDD2

VDD1

(2 OF 2)

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LPDDR3 CHANNEL B (32-63)

PLACEMENT_NOTE:

Distribute evenly.

10uF caps are shared between DRAM.

63

2

1

C2623

X5R-CERM

20%

10UF

0603

25V

2

1

C2603

10V X5R 402

1UF

10%

2

1

C2604

10V X5R 402

1UF

10%

2

1

C2605

10V X5R 402

1UF

10%

2

1

C2606

10UF

20% 25V X5R-CERM 0603

7

22 24 63 70

63

2

1

R2600

201

MF

1/20W

1%

243

2

1

R2601

1%

243

1/20W

MF

201

2

1

C2640

201

0.047UF

X5R

6.3V

10%

2

1

C2641

201

0.047UF

10%

X5R

6.3V

63

7

63 70

63

7

63 70

63

7

63 70

24 63 70

7

24 63 70

63

24 63 70

7

24 70

7

24 70

7

24 70

7

24 70

7

22 24 70

7

22 24 70

63

B4

B3

J11

H4

J8

U2

U1

T13

T1

B13

B1

A13

A12

U13

U12

A2

A1

R3

K9

C4

D10

D11

P10

P11

G10

G11

L10

L11

F10

F11

M11

M10

M9

M8

B8

B9

N11

B10

B11

C8

C9

C10

C11

R11

R10

R9

R8

N10

T11

T10

T9

T8

D9

E9

E10

E11

F8

F9

N9

P9

D8

P8

G8

L8

L4

L3

K4

K3

J3

J2

C2

D2

E2

E3

F3

M3

N3

N2

P2

R2

U2600

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

CRITICAL

OMIT_TABLE

H10

G9

G6

F12

F6

E6

D12

C6

T12

T6

R6

P12

N6

M12

M6

L9

K10

B12

B6

J4

M4

P3

G4

G3

F4

D3

C3

M5

L6

K2

J12

F5

E5

E4

C5

H2

T5

T4

T3

T2

R5

R4

N5

N4

B5

B2

J10

J9

H11

H9

H8

G12

E12

E8

U11

R12

N12

N8

L12

K11

K8

C12

A11

M2

L2

H3

G2

F2

J5

H12

H6

H5

G5

D6

D5

D4

U9

U8

P6

P5

P4

L5

K12

K6

K5

J6

A9

A8

U10

U6

U5

U4

U3

A10

A6

A5

A4

A3

U2600

OMIT_TABLE

CRITICAL

FBGA

LPDDR3-16GB

EDFA232A1MA-GD-F

2

1

C2630

10%

1UF

402

X5R

10V

2

1

C2631

10%

1UF

402

X5R

10V

2

1

C2610

10V X5R 402

1UF

10%

2

1

C2611

X5R

10V

402

1UF

10%

63

2

1

C2632

25V

0603

10UF

20%

X5R-CERM

2

1

C2620

10%

1UF

402

X5R

10V

2

1

C2600

0201

16V X5R-CERM

0.1UF

10%

2

1

C2621

10%

1UF

402

X5R

10V

2

1

C2601

0201

10%

0.1UF

X5R-CERM

16V

2

1

C2622

10%

1UF

402

X5R

10V

2

1

C2602

10V X5R 402

1UF

10%

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

LPDDR3 DRAM Channel B (32-63)

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_B

MEM_B_ZQ<2> MEM_B_ZQ<3>

MEM_B_DQS_P<6>

=MEM_B_DQS_P<5> =MEM_B_DQS_P<6>

=MEM_B_DQS_P<4>

MEM_B_DQS_N<6>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<4> =MEM_B_DQS_N<5>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=MEM_B_DQ<61>

=MEM_B_DQ<59> =MEM_B_DQ<60>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DQ<53>

=MEM_B_DQ<52>

=MEM_B_DQ<51>

=MEM_B_DQ<50>

=MEM_B_DQ<49>

=MEM_B_DQ<48>

=MEM_B_DQ<47>

=MEM_B_DQ<46>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQ<42> =MEM_B_DQ<43>

=MEM_B_DQ<41>

MEM_B_DQ<32>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQ<34> =MEM_B_DQ<35>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

PP1V2_S3

PP1V8_S3

PP1V2_S3

MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9>

MEM_B_CKE<2> MEM_B_CKE<3>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CS_L<1>

PP1V2_S3

PP1V8_S3

MEM_B_CS_L<0>

MEM_B_ODT<0>

23 OF 76

<SCH_NUM>

26 OF 121

18 19 22 70

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

17 19 20 21 22 23 42 53 62 70

20 21 22 23 57 62

w w w . c h i n a f i x . c o m

Apple MACKBOOK J113 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual