Apple MACBOOK PRO TOUCH BAR X362 Schematics

8

www.schematic-x.blogspot.com

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

X362 MLB SCHEMATIC

LAST_MODIFICATION=Tue Aug 30 11:06:16 2016

2 1

CK

ECNREV DESCRIPTION OF REVISION

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

APPD

DATE

2016-08-3000069392729 ENGINEERING RELEASED

D

1 2

3 4 5 6 7 8 9 10 11 12 13 14

1 05/13/2016 2 3 4 5 6 7 8 9 10 11 12 13 14

Table of Contents BOM Configuration

BOM Configuration PD Parts CPU GFX CPU MISC/JTAG/CFG/RSVD CPU LPDDR3 Interface CPU & PCH Power CPU & PCH Grounds CPU Core Decoupling CPU GT Decoupling PCH Decoupling PCH Audio/LPC/SPI/SMBus PCH Power Management

SHART_J44 J79_JACK LDUNN_J44 J130_DEV_MLB_U

J130_DEV_MLB_U J52_MLB

J79_JSHAO J79_ALFRED

J79_JSHAO J79_JSHAO

J79_JSHAO J130_MLB J130_MLB

11/27/2012 04/07/2016 01/13/2013 04/29/2015 04/28/2015 05/12/2015 03/14/2016 05/12/2015 08/28/2015 08/28/2015 03/14/2016 02/22/2016 05/04/2016

61 62 63 64 65 66 67 68 69 70 71 72 73 74

63 64 65 66 69 70 71 72 73 74 75 76 77 78

AUDIO JACK CODEC Left Speaker Amps & Conn

Right Speaker Amps & Conn AUDIO JACK CONNECTOR DC-In & Battery Connectors PBUS Supply & Battery Charger CORE & SA IMVP IC CORE & SA IMVP POWER BLOCK Empty GT & GTX IMVP POWER BLOCK Empty Power - 5V 3.3V Supply Power - EOPIO EDRAM Supply PMIC-1 & Power Control

J79_JCURCIO J79_JCURCIO J79_JCURCIO J79_JCURCIO J79_JSHAO J79_JSHAO J79_JSHAO J79_JSHAO J79_SILUCHEN J79_JSHAO J79_SILUCHEN J79_JSHAO J79_JSHAO J79_JSHAO

11/18/2015 12/03/2015 12/18/2015 12/03/2015 12/03/2015 03/02/2016 12/03/2015 04/02/2015 09/25/2015 03/27/2015 03/23/2016 04/12/2016 09/09/2015

D

C

15 16 17 18 19 20 21 22 23 24 25 26 27 28

15 16 18 19 20 22 23 24 25 26 27 28 29 30

PCH PCIE/USB/CLKS PCH SPI/UART/GPIO CPU/PCH Merged XDP Chipset Support 1 Chipset Support 2 LPDDR3 VREF Margining LPDDR3 DRAM Channel A (00-31) LPDDR3 DRAM Channel A (32-63) LPDDR3 DRAM Channel B (00-31) LPDDR3 DRAM Channel B (32-63) LPDDR3 DRAM Termination USB-C HIGH SPEED 1 USB-C HIGH SPEED 2 USB-C Support

J130_MLB J130_MLB J130_MLB J79_GREG J79_GREG J52_MLB J52_MLB J52_MLB J52_MLB J52_MLB J52_MLB J79_GREG J79_GREG J79_GREG

06/23/2015 12/08/2015 12/08/2015 09/09/2015 07/05/2016 05/12/2015 05/12/2015 05/12/2015 05/12/2015 05/12/2015 05/12/2015 07/27/2015 09/09/2015 08/08/2016

75 76 77 78 79 80 81 82 83 84 85 86 87 88

79 80 81 82 84 85 86 87 88 89 90 91 92 93

PMIC-1 1.2V 0.6V VCCIO PMIC-1 1V 1.8V VCCPCH PMIC-1 Aliases & TPs Power FETs LCD Backlight Driver eDP Display Connector S3X CORE PCIE S3X POWER S3X GND Connector NAND VR, I2C ROM, TEMP SENSORS ANI[3:0] ANI[7:4] PICCOLO PMIC

J79_JSHAO J79_JSHAO J79_SILUCHEN J79_JSHAO J79_RUENJOU J79_RUENJOU J79_RUENJOU J79_RIO J79_RIO J79_RUENJOU J79_RUENJOU J79_RUENJOU J79_RUENJOU J79_RUENJOU

12/03/2015 12/03/2015 07/17/2015 03/14/2016 09/09/2015 09/12/2015 08/20/2015

C

06/18/2015 06/18/2015 09/09/2015 09/12/2015 09/25/2015 09/25/2015 09/24/2015

B

29 30 31 32 33 34 35 36 37 38 39 40 41 42

31 32 33 34 35 36 37 38 39 40 41 42 43 44

USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B USB-C CONNECTOR A USB-C CONNECTOR B TBT 5V REGULATOR Display Mux WIFI/BT: MODULE 1 WIFI/BT: MODULE 2 Camera/DFR 1 Camera/DFR 2 Camera/DFR 3 Berkelium - 1 Berkelium - 2 T208 Support

J79_GREG J79_GREG J79_GREG J79_GREG J79_JSHAO J79_GREG J79_METE

J79_METE J80_MLB_BAFFIN

J79_ANDREW J79_ANDREW J79_ANDREW J79_ANDREW J79_ANDREW

08/08/2016 02/28/2016 07/05/2016 03/24/2016 12/18/2015 02/28/2016 05/17/2016 03/02/2016 07/22/2016 03/22/2016 04/25/2016 03/14/2016 02/01/2016 07/01/2016

89 90 91 92 93 94

96 97 98 99 100 101 102

94 95 96 110 111 112 11395 114 115 116 117 120 121 122

SSD NAND VR Empty LIFEBOAT USB-C HIGH SPEED 1 USB-C HIGH SPEED 2 USB-C Support USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B USB-C CONNECTOR A USB-C CONNECTOR B TBT 5V REGULATOR Power Aliases - 1 Power Aliases - 2

Signal Aliases

J79_JSHAO J14 J79_RUENJOU J79_GREG J79_GREG J79_GREG J79_GREG J79_GREG J79_GREG J79_GREG J79_JSHAO J79_ALFRED J79_ALFRED SHART_J44

12/18/2015 10/23/2012 09/09/2015

07/28/2015 08/28/2015 07/05/2016 02/28/2016 02/28/2016 07/05/2016 03/24/2016 12/18/2015 06/17/2015 06/18/2015 11/19/2012

B

A

Schematic / PCB #'s

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

SCHEM,MLB,X362 CRITICAL051-00515 1 SCH

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Connectors&ESD Empty Empty Empty MESA SMC SMC Shared Support SMC Project Support SMBus Connections Power Sensors: High Side Power Sensors: Load Side Power Sensors: Extended Power Sensors: Extended 2 Thermal Sensors Power Sensors:Extended 3 Fans SPI Debug Connector HDA Bridge

J79_GAREN J79_DAYU J79_DAYU J79_DAYU J79_ANDREW J79_JACK J79_JACK J79_JACK

J79_JACK J79_JACK J79_JACK J79_JACK J79_JACK J79_JACK J79_JACK J79_JACK J52_MLB J79_JCURCIO

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALPCBF,MLB,X362820-00239 1 PCB

11/21/2015 05/26/2015 05/26/2015 05/12/2015 01/06/2016 04/11/2016 04/14/2016 04/11/2016 03/31/2016 12/07/2015 04/03/2016 01/08/2016 05/10/2016 09/24/2015 04/14/2016 08/21/2015 05/12/2015 03/24/2016

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119

123 124 125 127 129 130 131 132 133 134 135 136 137 138 139 140 145

LPDDR3 Bit & Byte Swizzle ICT FCT 1 ICT FCT 2 Desense Capacitors Empty PCB Rule Definitions CPU Constraints PCH Constraints Memory Constraints TBT DP HDMI Constraints PCIe Constraints USB Constraints SMC Constraints Camera Constraints Sensors & Audio Constraints References Alternates BOM Table

AHARTMAN_J52 YHARTANTO_J44 YHARTANTO_J44 YHARTANTO_J44 J79_RIO YHARTANTO_J44 YHARTANTO_J44 YHARTANTO_J44 YHARTANTO_J44 J79_JACK J79_JACK J79_JACK YHARTANTO_J44 YHARTANTO_J44 YHARTANTO_J44 J79_RUENJOU_CONSTRAINTS J80_MLB

10/29/2013 12/18/2012 12/18/2012 01/09/2013 06/18/2015 12/14/2012 01/13/2013 01/08/2013 01/02/2013 05/19/2015 05/19/2015 05/21/2015 01/02/2013 01/09/2013 01/04/2013 06/11/2015 12/12/2015

DRAWING TITLE

SCHEM,MLB,X362

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

?

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

1 OF 145

SHEET

1 OF 119

A

SIZEDRAWING NUMBER

D

3

1245678

D

BOM Groups

BOM GROUP BOM OPTIONS

X362_COMMON

X362_COMMON1

X362_COMMON2

X362_COMMON3

X362_PROGPARTS

X362_DEVEL:ENG

X362_DEVEL:DVT

X362_DEVEL:PVT

Module Parts

337S00266 U0500 CRITICAL1

337S00267 1 CRITICAL CPU_SKL23:3.1GU0500

353S00961

338S00276 U86001

343S00147 U3620 CRITICAL1

4

1 POP_4GBITPOP8600333S00055

ALTERNATE,COMMON,X362_COMMON1,X362_COMMON2,X362_COMMON3,X362_PROGPARTS

SE:PROD,BOARD_ID:8,T208_PROG:REV5,TBTTHRM_SNS,S3XCLK:INT

EDP_ENABLE,XDP:YES,PCH_CLK:GRNCLK,TBT_DBG,SAMCONN,SKIP_5V3V3:AUDIBLE,SOC_BOOT:SPI

CPUTHRM:ALRT,TBTTHRM:ALRT,LOADRC:NO,CUMULUS_IPD,S3_STATE:YES,VCCPLLOC:S3

BOOTROM_PROG,SMC_PROG,AR_LT_PROG,AR_RT_PROG,WIFI_PROG,BTROM_PROG

ALTERNATE,DBGLED,USBC_DBG,XDP_CONN:YES,WIFI_DBG,S3X_DBG,DEBUG_BUTTON,LOADISNS

ALTERNATE,USBC_DBG,XDP_CONN:YES,WIFI_DBG

ALTERNATE

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CPU,SKLU,SR2JK,PRQ,2.9,28W,1.05,B1356

CPU,SKLU,SR2JJ,PRQ,3.1,28W,1.1,B1356

CPU,SKLU,SR2JH,PRQ,3.3,28W,1.1,B1356

INTERPOSER,VTT ADAPTER,SKL-U,BGA1356

IC,TBT,ALPINE RIDGE,QSTY,PRQ,C1,CSP337

IC,CD3215,ACE,C00,USB PWR SW,BLNK,BGA96

IC,CNTLR,S3X,B1,FCBGA900

IC,LPDDR3-1600,4GBIT,25NM,A,276B

IC,LPDDR3-1600,8GBIT,25NM,A,276B

IC,SLG4AP41172,PAK3,STQFN20

U2800,UB000338S00254 CRITICAL2

U3100,U3200,UB300,UB400

CRITICAL CPU_SKL23:3.3GU0500337S00268 1

CRITICALU0500 CPU_SOCKET1998-04195

CRITICAL

CPU_SKL23:2.9G

POP_8GBITPOP86001333S00056

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

345678

Variable BOM Groups Development/Base BOMs

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1685-00055

COMMON PARTS,MLB,X362

DEV,MLB,X362

CRITICAL BASE_BOMBASE

CRITICAL985-00070

DEVEL_BOMDEVEL1

Main DRAM Parts

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

333S00069

4

333S00070 4

4333S00068

333S00050

4

IC,SDRAM,LPDDR3-2133,16GBIT,20NM,BGA178 U2300,U2400,U2500,U2600

IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178

IC,SDRAM,LPDDR3-2133,16GBIT,20NM,BGA178

IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178

U2300,U2400,U2500,U2600

CRITICAL CRITICAL CRITICAL 8G_SAMSUNG_2133 CRITICAL

8G_MICRON_2133

16G_MICRON_2133

16G_SAMSUNG_2133

Main DRAM SPD Straps

BOM GROUP BOM OPTIONS

8G_MICRON_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG1_LRAM_8G_MICRON_2133

16G_MICRON_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG1_LRAM_16G_MICRON_2133

RAM_8G_SAMSUNG_2133 8G_SAMSUNG_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG0_L

RAM_16G_SAMSUNG_2133

16G_SAMSUNG_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG0_L

2 1

CPU DRAM CFG Chart

A 0

B

SPEED

2133

1866

CAPACITY

8GB

16GB

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

VENDOR

HYNIX

MICRON

SAMSUNG

N/A

CFG 1

CFG 4DIE REV

1

D

CFG 3

0

1

CFG 2

0

1

CFG 0

0

1

0

1

0

1

C

1 CRITICALU7800338S00221

1 U7000353S01016

IC,PMU,SN650839,7X7MM,BGA168

IC,ISL9239HIZ,PMU,TUBA,WCSP40,2.1X3.3MM

IC,PMU,PICCOLO,D2231A0,OTP-AK,WLCSP96

Programmables (All Builds)

EFI ROM

341S00698

SMC ROM

341S00700

TBT ROMs

341S00717

341S00718

WIFI/BT ROM

1

IC,EFI ROM (V0193) DVT,X362

IC,SMC-B1,EXT (V2.37F6) PVT,X362

T29,AR1 (VTBD) PVT,X362

T29,AR2 (VTBD) PVT,X362

U6100

U5000

U2890

UB090

CRITICAL

CRITICAL1 U9300338S00227

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1

BOOTROM_PROGCRITICAL

SMC_PROGCRITICAL

AR_LT_PROG

AR_RT_PROGCRITICAL

NAND Parts

335S00124 4 335S00125 335S00126 335S00261

4 CRITICAL 4 4

335S00262 335S00263

4

NAND Straps

BOM GROUP BOM OPTIONS

SAND_256G SAND_512G

SAND_1T TOSH_256G TOSH_512G

TOSH_1T

NAND,1ZNM,128GB,TOGG,HPN,128G,LGA60

NAND,1ZNM,256GB,TOGG,HPN,128G,LGA60

NAND,TGDDR2,128GX4,15NM,HP,USHD,T2,LGA60

NAND,TGDDR2,128GX8,15NM,HP,USHD,T2,LGA60

NAND,TGDDR2,128GX16,15NM,HP,UHD,T2,LGA60

ALTERNATE,NAND_SDISK_256GB,POP_4GBIT,CAPACITY1,CAPACITY0

ALTERNATE,NAND_SDISK_1TB,POP_8GBIT,CAPACITY2,CAPACITY0

ALTERNATE,NAND_TSHBA_256GB,POP_4GBIT,CAPACITY1,CAPACITY0

ALTERNATE,NAND_TSHBA_1TB,POP_8GBIT,CAPACITY2,CAPACITY0

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

U9100,U9120,U9200,U9220NAND,1ZNM,64GB,TOGG,HPN,128G,LGA60

U9100,U9120,U9200,U9220

CRITICAL

CRITICAL CRITICAL CRITICAL4 CRITICAL

NAND_SDISK_256GB

NAND_SDISK_512GB

NAND_SDISK_1TB

NAND_TSHBA_256GB

NAND_TSHBA_512GB

NAND_TSHBA_1TB

ALTERNATE,NAND_SDISK_512GB,POP_4GBIT,CAPACITY2

ALTERNATE,NAND_TSHBA_512GB,POP_4GBIT,CAPACITY2

C

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

B

A

341S00715

341S00716

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1 CRITICALU3750 BTROM_PROG

IC,BT ROM (V32) PVT,X362/X363

WIFI ROM (P108) PVT,WW1,X362/X363

CRITICAL WIFI_PROGU37101

Strategic Silicon

PART# COMMENT

337S00266

337S00267 08

337S00268

333S00068 07

333S00069

335S00124

335S00125

335S00126

335S00261

335S00262

335S00263

333S00026 02

333S00108

STRATEGIC VALUE

08

07333S00050

07

07333S00070

02

02333S00025

02333S00055

02333S00056

02333S00107

02

02998-06736

CPU

MEMORY

NAND

S3X DRAM

S3X CONTROLLER

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

PART# COMMENT

338S00227

343S00135

343S00136

343S00137

343S00138

353S3978

338S00147

338S00254 08

338S00142

353S4316

353S01016

343S00147

STRATEGIC VALUE

02

10

09338S00193

02

09353S00961

09

07353S00685

08

08338S00221

09

05339S00056

08

08359S00006

09353S00795

PICCOLO

T208

BERKELIUM

MOJAVE

SECURE ELEMENT

ALPINE RIDGE

ACE

CLIFDEN

AUDIO AMP

BAYSIDE

BANJO

TUBA

ICEBOCK

PAK

GREEN CLOCK

DEBUG MUX

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

SYNC_MASTER=SHART_J44 SYNC_DATE=11/27/2012

PAGE TITLE

BOM Configuration

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

2 OF 145

SHEET

2 OF 119

D

B

A

8 7 5 4 2 1

36

D

C

BOM Variants

BOM NUMBER BOM NAME BOM OPTIONS

685-00055 COMMON PARTS,MLB,X362 X362_COMMON

985-00070 DEV,MLB,X362 X362_DEVEL:DVT

639-01870

MLB,2.9G,SAM-8G,SAND-256G,X362

639-01871 MLB,2.9G,SAM-16G,SAND-256G,X362

639-01872 MLB,2.9G,MIC-8G,SAND-256G,X362

639-01873 MLB,2.9G,MIC-16G,SAND-256G,X362

639-01984

MLB,2.9G,SAM-8G,SAND-512G,X362

639-01985 MLB,2.9G,SAM-16G,SAND-512G,X362

639-01986

MLB,2.9G,MIC-8G,SAND-512G,X362

639-01987 MLB,2.9G,MIC-16G,SAND-512G,X362

639-02517

MLB,2.9G,SAM-8G,SAND-1T,X362

639-02518 MLB,2.9G,SAM-16G,SAND-1T,X362

639-02519 MLB,2.9G,MIC-8G,SAND-1T,X362

639-02520 MLB,2.9G,MIC-16G,SAND-1T,X362

639-01874 MLB,3.1G,SAM-8G,SAND-256G,X362

639-01875

639-01876

MLB,3.1G,SAM-16G,SAND-256G,X362

MLB,3.1G,MIC-8G,SAND-256G,X362

639-01877 MLB,3.1G,MIC-16G,SAND-256G,X362

639-01883 MLB,3.1G,SAM-8G,SAND-512G,X362

639-01884 MLB,3.1G,SAM-16G,SAND-512G,X362

639-01885 MLB,3.1G,MIC-8G,SAND-512G,X362

639-01886 MLB,3.1G,MIC-16G,SAND-512G,X362

639-01887

MLB,3.1G,SAM-8G,SAND-1T,X362

639-01888 MLB,3.1G,SAM-16G,SAND-1T,X362

639-01889 MLB,3.1G,MIC-8G,SAND-1T,X362

639-01890 MLB,3.1G,MIC-16G,SAND-1T,X362

639-02221 MLB,3.3G,SAM-8G,SAND-256G,X362

639-02222 MLB,3.3G,SAM-16G,SAND-256G,X362

639-02223 MLB,3.3G,MIC-8G,SAND-256G,X362

639-02224

MLB,3.3G,MIC-16G,SAND-256G,X362

639-01891 MLB,3.3G,SAM-8G,SAND-512G,X362

639-01892 MLB,3.3G,SAM-16G,SAND-512G,X362

639-01893 MLB,3.3G,MIC-8G,SAND-512G,X362

639-01894 MLB,3.3G,MIC-16G,SAND-512G,X362

639-01895 MLB,3.3G,SAM-8G,SAND-1T,X362

639-01896 MLB,3.3G,SAM-16G,SAND-1T,X362

639-01897 MLB,3.3G,MIC-8G,SAND-1T,X362

639-01898

MLB,3.3G,MIC-16G,SAND-1T,X362

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,SAND_1T

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

345678

BOM NUMBER BOM NAME BOM OPTIONS

MLB,NO CPU,X362639-01988

MLB,CPU SOCKET,X362639-01989

639-02521

639-02522

639-02523

639-02524

639-02525

639-02526

639-02527

639-02528

639-02529

MLB,2.9G,SAM-8G,TOSH-256G,X362

MLB,2.9G,SAM-16G,TOSH-256G,X362

MLB,2.9G,MIC-8G,TOSH-256G,X362

MLB,2.9G,MIC-16G,TOSH-256G,X362

MLB,2.9G,SAM-8G,TOSH-512G,X362

MLB,2.9G,SAM-16G,TOSH-512G,X362

MLB,2.9G,MIC-8G,TOSH-512G,X362

MLB,2.9G,MIC-16G,TOSH-512G,X362

MLB,2.9G,SAM-8G,TOSH-1T,X362

639-02530 MLB,2.9G,SAM-16G,TOSH-1T,X362

639-02531 MLB,2.9G,MIC-8G,TOSH-1T,X362

639-02532 MLB,2.9G,MIC-16G,TOSH-1T,X362

639-02533 MLB,3.1G,SAM-8G,TOSH-256G,X362

639-02534

MLB,3.1G,SAM-16G,TOSH-256G,X362

639-02535 MLB,3.1G,MIC-8G,TOSH-256G,X362

639-02536

MLB,3.1G,MIC-16G,TOSH-256G,X362

639-02537 MLB,3.1G,SAM-8G,TOSH-512G,X362

639-02538

MLB,3.1G,SAM-16G,TOSH-512G,X362

639-02539 MLB,3.1G,MIC-8G,TOSH-512G,X362

639-02540

639-02541

MLB,3.1G,MIC-16G,TOSH-512G,X362

MLB,3.1G,SAM-8G,TOSH-1T,X362

639-02542 MLB,3.1G,SAM-16G,TOSH-1T,X362

639-02543 MLB,3.1G,MIC-8G,TOSH-1T,X362

639-02544 MLB,3.1G,MIC-16G,TOSH-1T,X362

639-02545 MLB,3.3G,SAM-8G,TOSH-256G,X362

639-02546 MLB,3.3G,SAM-16G,TOSH-256G,X362

639-02547 MLB,3.3G,MIC-8G,TOSH-256G,X362

639-02548 MLB,3.3G,MIC-16G,TOSH-256G,X362

639-02549 MLB,3.3G,SAM-8G,TOSH-512G,X362

639-02550 MLB,3.3G,SAM-16G,TOSH-512G,X362

639-02551

639-02552

639-02553

639-02554

639-02555

MLB,3.3G,MIC-8G,TOSH-512G,X362

MLB,3.3G,MIC-16G,TOSH-512G,X362

MLB,3.3G,SAM-8G,TOSH-1T,X362

MLB,3.3G,SAM-16G,TOSH-1T,X362

MLB,3.3G,MIC-8G,TOSH-1T,X362

639-02556 MLB,3.3G,MIC-16G,TOSH-1T,X362

BASE_BOM,DEVEL_BOM,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SOCKET,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,TOSH_1T

2 1

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

C

B

Alternate Parts

TABLE_ALT_HEAD

PART NUMBER

ALL152S00269152S00368 Text note to be updated

152S00370 152S00270 ALL Text note to be updated

ALL138S0884138S00086 Text note to be updated

152S1829 Text note to be updatedALL152S00434

371S00019

353S00107

371S0463

ALL Rohm alt to Rohm

ALL353S3239

ALL353S00231 NXP alt to TI353S3987

POP_4GBIT ALL MICRON SSD POP ALT for HYNIX333S00025 333S00055

POP_8GBIT ALL MICRON SSD POP ALT for HYNIX333S00026 333S00056

ALL HYNIX SSD POP REPLACEMENT for HYNIX333S00107 POP_4GBIT333S00055

POP_8GBIT HYNIX SSD POP REPLACEMENT for HYNIXALL333S00056333S00108

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

Text note to be updatedALL353S4068 353S4070

TABLE_ALT_ITEM

Text note to be updatedALL353S00772 353S4070

TABLE_ALT_ITEM

TFT alt to CyntecALL107S0250107S0248

TABLE_ALT_ITEM

Onsemi alt to IntersilANY

TABLE_ALT_ITEM

138S0701 ALL Text note to be updated138S0689

TABLE_ALT_ITEMTABLE_ALT_ITEM

138S0771 Text note to be updatedALL138S00012152S00266 ALL152S00367 Text note to be updated

TABLE_ALT_ITEM

ALL138S00013 Text note to be updated138S0772

TABLE_ALT_ITEM

152S00401 ALL Text note to be updated152S0529

TABLE_ALT_ITEM

Text note to be updated152S00344 ALL152S1683

TABLE_ALT_ITEM

152S00331 ALL Text note to be updated152S00283

TABLE_ALT_ITEM

ALL152S2034 Text note to be updated152S00190

TABLE_ALT_ITEM

197S0613 197S0612 ALL Text note to be updated

TABLE_ALT_ITEM

ALL Text note to be updated311S0398311S00121

TABLE_ALT_ITEM

Text note to be updated371S0558 ALL371S0713

TABLE_ALT_ITEM

371S0602 Text note to be updatedALL371S00074

B

A

PAGE TITLE

BOM Configuration

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=04/07/2016SYNC_MASTER=J79_JACK

051-00515

9.0.0

dvt-fab09-0

3 OF 145

3 OF 119

A

D

BOARD MECHANICALS

345678

2 1

D

Shield Cans - BOTTOM SIDE

ALPINE RIDGE - LIO (U2800) - 806-06077

1

SH0418

SM

SHLD-FENCE-ALPINE-X379

LPDDR3 (U2300 ~ U2600) - 806-06167

1

SH0415

SM

SHLD-FENCE-X379

NAND - BOTTOM SOUTH (U9120) - 806-05945

T208 (U3900) - 806-06264

1

SH0412

SM

SHLD-FENCE-M8-X379

DIPLEXERS - 806-06266

1

SH0411

SM

SHLD-MLB-DIPLEXER-X379

NAND - TOP SOUTH (U9100) - 806-06262

POGO PINSShield Cans - TOP SIDE

LIO and RIO -2X (870-5071)

SH0471

POGO-2.0OD-2.95H-SM

SM

1

AROUND THE FAN AND CENTER - 8X (870-01518)

POGO-2.0OD-2.95H-SM

SH0463

POGO-2.3OD-4.0H-SM

SM

1

POGO-2.3OD-4.0H-SM

SH0472

SM

1

SH0464

SM

1

SH0465

POGO-2.3OD-4.0H-SM

SM

1

SH0466

POGO-2.3OD-4.0H-SM

SM

1

Cowling Bosses - BOTTOM SIDE

DFR TOUCH CONN (J4402) - 860-00414

SH0425

6.25X3.85R-1.75ID-1.938H-SM

1

USB-C CONN - LIO (J3300) - 860-00392

SH0445

3.4OD1.75ID-1.12H-SM

1

DFR DISPLAY CONN (J4401) - 860-00412

D

SH0446

3.4OD1.75ID-1.12H-SM

1

C

1

SH0417

SM

SHLD-FENCE-NAND-BOT-SOUTH-X379

S3X (U8600) - 806-06023

1

SH0414

SM

SHLD-FENCE-S3X-X379

NAND - BOTTOM NORTH (U9200) - 806-06265

1

SH0419

SM

SHLD-FENCE-MLB-NAND-BTM-NORTH-X379

1

SH0416

SM

SHLD-FENCE-MLB-NAND-TOP-SOUTH-X379

NAND - TOP NORTH (9220) - 806-06258

1

SH0413

SM

SHLD-FENCE-MLB-NAND-NORTH-X379

SH0467

POGO-2.3OD-4.0H-SM

SM

1

SH0468

POGO-2.3OD-4.0H-SM

SM

1

SH0469

POGO-2.3OD-4.0H-SM

SM

1

SH0470

POGO-2.3OD-4.0H-SM

SM

1

SH0426

3.4OD1.75ID-1.7H-SM

1

IPD CONN (J4501) - 860-00412

3.4OD1.75ID-1.7H-SM

1

SH0428

3.4OD1.75ID-1.7H-SM

1

KBD CONN (J4500) - 860-00412

3.4OD1.75ID-1.7H-SM

1

SH0430

3.4OD1.75ID-1.7H-SM

1

3.4OD1.75ID-1.7H-SM

1

SH0427

SH0429

C

SH0431

B

ALPINE RIDGE - RIO (UB000) - 806-06077

1

SH0420

SM

SHLD-FENCE-ALPINE-X379

Shield CAN Alignment Slots 14X - 998-04440 (1.2mm X 0.4mm)

SH0449

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0454

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0459

TH-NSP

1

SH0450

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0455

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0460

TH-NSP

1

SH0451

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0461

TH-NSP

1

SH0452

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0457

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0453

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0458

TH-NSP

1

SL-1.2X0.4-1.5X0.7

Thermal Stage Mounting Holes

Plated Through Hole - 3.15mm - APN 998-0845

SH0490

3P9R3P15

1

Plated Through Hole - 3.6mm - APN 998-03850

SH0491

4.0R3.6-NSP

1

SH0492

4.0R3.6-NSP

1

SH0493

4.0R3.6-NSP

1

USB-C CONN - RIO (JB500) - 860-00392

SH0447

3.4OD1.75ID-1.12H-SM

1

AUDIO JACK CONN (J6600) - 860-00399

SH0432

3.3X1.8R-1.4ID-1.64H-SM

1

MESA CONN (J4900) - 860-00399

SH0433

3.3X1.8R-1.4ID-1.64H-SM

1

SH0448

3.4OD1.75ID-1.12H-SM

1

B

A

SL-1.2X0.4-1.5X0.7

TOP Rubber Mount Standoffs - 12X - (860-00430)

SH0400

2.8OD1.2ID-1.435H-SM

1

2

SH0404

2.8OD1.2ID-1.435H-SM

1

2

SH0408

2.8OD1.2ID-1.435H-SM

1

2

SH0401

2.8OD1.2ID-1.435H-SM

1

2

SH0405

2.8OD1.2ID-1.435H-SM

1

2

SH0409

2.8OD1.2ID-1.435H-SM

1

2

2.8OD1.2ID-1.435H-SM

SH0402

1

2

SH0406

1

2

SH0410

1

2

SH0403

2.8OD1.2ID-1.435H-SM

1

2

SH0407

2.8OD1.2ID-1.435H-SM

1

2

SH0436

2.8OD1.2ID-1.435H-SM

1

2

Bottom Rubber Mount Standoffs - 1X - (860-00476)

SH0437

2.8OD1.2ID-3.25H-SM

1

2

LIFEBOAT CONN (J9600) - 860-00413

3.4OD1.75ID-1.57H-SM

Cowling Bosses - TOP SIDE

eDP CONN (J8500) - 860-00415

3.4OD1.75ID-0.844H-SM

BOM_COST_GROUP=MECHANICALS

SH0473

SH0474

3.4OD1.75ID-1.57H-SM

1

SH0421

1

SH0422

3.4OD1.75ID-0.844H-SM

1

SYNC_MASTER=LDUNN_J44 SYNC_DATE=01/13/2013

PAGE TITLE

1

PD Parts

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

4 OF 145

SHEET

4 OF 119

A

D

8 7 5 4 2 1

36

345678

2 1

D

105 34

34

105 34

34

OUT

DP_DDI1_ML_C_N<0> DP_DDI1_ML_C_P<0> DP_DDI1_ML_C_N<1> DP_DDI1_ML_C_P<1> DP_DDI1_ML_C_N<2> DP_DDI1_ML_C_P<2> DP_DDI1_ML_C_N<3> DP_DDI1_ML_C_P<3>

DP_DDI2_ML_C_N<0> DP_DDI2_ML_C_P<0> DP_DDI2_ML_C_N<1> DP_DDI2_ML_C_P<1> DP_DDI2_ML_C_N<2>

DP_DDI2_ML_C_N<3> DP_DDI2_ML_C_P<3>

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 1 OF 20

EDP

DDI

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48

EDP_INT_ML_N<0> EDP_INT_ML_P<0> EDP_INT_ML_N<1> EDP_INT_ML_P<1> EDP_INT_ML_N<2> EDP_INT_ML_P<2> EDP_INT_ML_N<3> EDP_INT_ML_P<3>

EDP_INT_AUX_N EDP_INT_AUX_P

NC

DP_DDI1_AUXCH_C_N DP_DDI1_AUXCH_C_PDP_DDI2_ML_C_P<2> DP_DDI2_AUXCH_C_N DP_DDI2_AUXCH_C_P

OUT

BI

D

80

34

C

PPVCCIO_S0_CPU

8 100

PLACE_NEAR=U0500.E52:15.24MM

1

R0530

24.9

1% 1/20W MF 201

2

94 17 5

34

94 28 5

104 80

IN

OUT

IN

XDP_USB_EXTD_OC_L DP_DDPB_HPD

DP_DDPC_HPD NC_PCH_GPP_E15

19

JTAG_ISP_TDO DP_INT_HPD

EDP_COMP

DISPLAY SIDEBANDS

B9

GPP_E12/USB2_OC3*

L9

GPP_E13/DDPB_HPD0

L7

GPP_E14/DDPC_HPD1

L6

GPP_E15/DDPD_HPD2

N9

GPP_E16/DDPE_HPD3

L10

GPP_E17/EDP_HPD

E52

EDP_RCOMP

GPP_E7/CPU_GP1

GPP_E8/SATALED*

GPP_E9/USB2_OC0* GPP_E10/USB2_OC1* GPP_E11/USB2_OC2*

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

A7 H1 A9 C9 D9

R12 R11 U13

XDP_PCH_OBSDATA_A3 XDP_PCH_OBSDATA_B0 XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L

EDP_BKLT_EN BKLT_PWM_MLB2TCON EDP_PANEL_PWR_EN

OUT

IN

17

79

80

28 17 5

94 17 5

104 80

C

B

12

FOR FUTURE PRODUCT PER PDG

PP1V8_SUS_PCH_VCC1P8 PP1V8_SUS_PCH_VCC1P8

NC NC NC NC NC

NC NC

AW69 AW68 AU56 AW48

C7 U12 U11

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 20 OF 20

SPARE

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVDRSVD RSVDRSVD

F6 E3 C11 B11 A11 D12 C12 F52H11 F46G46

NC NC NC NC NC NC NC NC NC

B

A

PP3V3_SUS

R0550 R0551 R0552 R0553

R0554

100K 100K 100K 100K

PP3V3_S0

10K

1 2 1 2 1 2 1 2

1 2

8 12 101

1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF

13 14 16 19 94 101

1/20W5% 201MF

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L

JTAG_ISP_TDO

28 17 5

94 17 5

DESIGN: X502/DEV_MLB_U LAST CHANGE: Tue Apr 28 20:32:21 2015

SYNC_DATE=04/29/2015SYNC_MASTER=J130_DEV_MLB_U

PAGE TITLE

A

CPU GFX

94 28 5

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

5 OF 145

SHEET

5 OF 119

8 7 5 4 2 1

36

D

PP1V0_S0SW

8 10 17 101

67 49 48

BI

PLACE_NEAR=R0611:1MM

R0610

CPU_PROCHOT_L

PLACE_NEAR=U0500.C65:25.4MM

PP1V0_S3

8 10 14 19 101

1

1K

5%

1/20W

MF

201

2

R0611

499

1%

1/20W

MF

201

12

49 48

OUT

PLACE_NEAR=U0500.C63:254MM

1

R0612

1K

5% 1/20W MF 201

2

48 19

49

OUT

BI

CPU_CATERR_L CPU_PECI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

105

102

13

17

105 13

35 13

BI

XDP_BPM_L<0> NC_XDP_BPM_L<1> NC_XDP_BPM_L<2> NC_XDP_BPM_L<3>

MLB_RAMCFG4

IN

XDP_PCH_OBSDATA_D2

OUT

BT_PWRRST_L

OUT

BT_TIMESTAMP

OUT

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP

OPC_RCOMP

NC

D63 A54 C65 C63 A65

C55 D55 B54 C56

V1

H3 BA5 AY5

AT16 AU16

H66 H65

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

CATERR* PECI PROCHOT* THERMTRIP* SKTOCC*

BPM[0]* BPM[1]* BPM[2]* BPM[3]*

GPP_D21/SPI1_IO2 GPP_E1/SATAXPCIE1/SATAGP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

SYM 4 OF 20

CPU MISC

JTAG

PROC_TCK PROC_TDI PROC_TDO PROC_TMS

PROC_TRST*

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST*

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

345678

XDP_CPU_TCK XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TRST_L

XDP_PCH_TCK XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS XDP_PCH_TRST_L PCH_JTAGX

OUT

IN

BI

2 1

D

17

C

B

A

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CPU_CFG<4>

17 6

EDP_ENABLE

1

R0634

1K

5% 1/20W MF 201

2

R0681

49.9

1%

1/20W

MF

201

49.9

1%

1/20W

MF

201

49.9

1%

1/20W

MF

201

1

2

PLACE_NEAR=U0500.AU16:12.7MM

1

2

R0683

17

17 6

17

1

2

PLACE_NEAR=U0500.AT16:12.7MM

R0682

R0680

49.9

1%

1/20W

MF

201

BI

OUT

102

1

2

49.9

1%

1/20W

MF

201

1

2

PLACE_NEAR=U0500.H65:12.7MM

R0684

PLACE_NEAR=U0500.H66:12.7MM

CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

CPU_CFG<16> CPU_CFG<17>

CPU_CFG<18> CPU_CFG<19>

CPU_CFG_RCOMP

ITP_PMODE

NC NC

NC

NC_CPU_RSVD_BA70 NC_CPU_RSVD_BA68

NC NC

NC

E68 B67 D65 D67 E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70

E63 F63

E66 F66

E60

E8

AY2 AY1

D1 D3

K46 K45

AL25 AL27

C71 B70

F60

A52

BA70 BA68

J71 J68

F65 G65

F61 E61

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD RSVD

RSVD

RSVD_TP RSVD_TP

RSVD RSVD

VSS VSS

RSVD RSVD

(IPU)

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 19 OF 20

RESERVED

PROC_SELECT*

RSVD_TP RSVD_TP

RSVD RSVD

TP5 TP6

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD

RSVD RSVD

TP4

RSVD RSVD

RSVD

RSVD RSVD

TP1 TP2

VSS

ZVM*

RSVD_TP RSVD_TP

MSM*

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

A69 B69

AY3

D71 C70

C54 D54

AY4 BB3

AY71 AR56

AW71 AW70

AP56 C64

NC_CPU_RSVD_BB68 NC_CPU_RSVD_BB69

NC_CPU_RSVD_AK13 NC_CPU_RSVD_AK12

NC NC

NC_CPU_AU5 NC_CPU_AT5

NC NC NC NC

NC NC

NC

NC NC

NC_CPU_BB5

NC NC

NC

NC NC

NC_CPU_AY4 NC_CPU_BB3

CPU_ZVM_L

NC_CPU_RSVD_AW71 NC_CPU_RSVD_AW70

NC_CPU_MSM_L

NCNC

102

DESIGN: X502/DEV_MLB_U LAST CHANGE: Mon Apr 27 22:56:39 2015

73

OUT

102

73

OUT

BOM_COST_GROUP=CPU & CHIPSET

CONNECT TO OPC VRS

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CPU MISC/JTAG/CFG/RSVD

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

6 OF 145

SHEET

6 OF 119

C

B

SYNC_DATE=04/28/2015SYNC_MASTER=J130_DEV_MLB_U

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

103

BI

OMIT_TABLE

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQS_P<3> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31] DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47] DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

U0500

SKL-ULT-2+3E

TBD

BGA

SYM 2 OF 20

LPDDR3 NON-INTERLEAVED0

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKP[1] DDR0_CKN[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS[0]* DDR0_CS[1]*

DDR0_ODT[0] DDR0_ODT[1]

DDR0_CAA[0] DDR0_CAA[1] DDR0_CAA[2] DDR0_CAA[3] DDR0_CAA[4] DDR0_CAA[5] DDR0_CAA[6] DDR0_CAA[7] DDR0_CAA[8] DDR0_CAA[9]

DDR0_CAB[0] DDR0_CAB[1] DDR0_CAB[2] DDR0_CAB[3] DDR0_CAB[4] DDR0_CAB[5] DDR0_CAB[6] DDR0_CAB[7] DDR0_CAB[8] DDR0_CAB[9]

DDR0_DQSN[0] DDR0_DQSN[1] DDR0_DQSN[2] DDR0_DQSN[3] DDR0_DQSN[4] DDR0_DQSN[5] DDR0_DQSN[6] DDR0_DQSN[7]

DDR0_DQSP[0] DDR0_DQSP[1] DDR0_DQSP[2] DDR0_DQSP[3] DDR0_DQSP[4] DDR0_DQSP[5] DDR0_DQSP[6] DDR0_DQSP[7]

DDR0_ALERT*

DDR0_PAR

DDR0_MA[3] DDR0_MA[4]

DDR_VREF_CA

DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

AT53 AU53 AT55 AU55

BA56 BB56 AW56 AY56

AU45 AU43

AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50

AM70 AT69 AH66 AG69 BA64 AY60 AR66 AR61

AM69 AT70 AH65 AG70 AY64 BA60 AR65 AR60

AW50 AT52

BA50 BB52

AY67

AY68 BA67

AW67

MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_B_CLK_N<0> MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CKE<0> MEM_A_CKE<1> MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_CAA<0> MEM_A_CAA<1> MEM_A_CAA<2> MEM_A_CAA<3> MEM_A_CAA<4> MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<8> MEM_B_DQ<24> MEM_A_CAA<9>

MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<4> MEM_A_CAB<5> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2>

MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

NC NC

CPU_DIMM_VREFCA

CPU_DIMMA_VREFDQ CPU_DIMMB_VREFDQ

PM_MEMVTT_EN

OUT

BI

103

20

75

D

OMIT_TABLE

25 21

25 22

25 21

25 22

25 22 21

25 21

25 22

103

BI

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23>

MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9] DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15] DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31] DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

U0500

SKL-ULT-2+3E

TBD

BGA

SYM 3 OF 20

LPDDR3 NON-INTERLEAVED

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKP[1] DDR1_CKN[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS[0]* DDR1_CS[1]*

DDR1_ODT[0] DDR1_ODT[1]

DDR1_CAA[0] DDR1_CAA[1] DDR1_CAA[2] DDR1_CAA[3] DDR1_CAA[4] DDR1_CAA[5] DDR1_CAA[6] DDR1_CAA[7] DDR1_CAA[8] DDR1_CAA[9]

DDR1_CAB[0] DDR1_CAB[1] DDR1_CAB[2] DDR1_CAB[3] DDR1_CAB[4] DDR1_CAB[5] DDR1_CAB[6] DDR1_CAB[7] DDR1_CAB[8] DDR1_CAB[9]

DDR1_DQSN[0] DDR1_DQSN[1] DDR1_DQSN[2] DDR1_DQSN[3] DDR1_DQSN[4] DDR1_DQSN[5] DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[0] DDR1_DQSP[1] DDR1_DQSP[2] DDR1_DQSP[3] DDR1_DQSP[4] DDR1_DQSP[5] DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_ALERT*

DDR1_PAR

DDR1_MA[3] DDR1_MA[4]

DRAM_RESET*

DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

AP45 AN45 AP46 AN46

AN56 AP55 AN55 AP53

BB42 AY42

BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46

BA38 AY34 AT38 AT32 BA30 AY26 AR25 AR22

AY38 BA34 AR38 AR32 AY30 BA26 AR27 AR21

AN43 AP43

BB46 BA47

AT13

AR18 AT18 AU18

MEM_B_CLK_P<0>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CKE<0> MEM_B_CKE<1> MEM_B_CKE<2> MEM_B_CKE<3>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0>

NCNC

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9>

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

NCNC

NC NC

NC

CPU_DDR_RCOMP<0> CPU_DDR_RCOMP<1> CPU_DDR_RCOMP<2>

OUT

BI

103

25 23

25 24

25 23

25 24

25 24 23

25 23

25 24

C

B

A

BOM_COST_GROUP=CPU & CHIPSET

1

R0700

162

1% 1/20W MF 201

2

PLACE_NEAR=U0500.AU18:6MM

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

CPU LPDDR3 Interface

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

1

R0701

80.6

1% 1/20W MF 201

2

PLACE_NEAR=U0500.AT18:6MM

Apple Inc.

1

R0702

200

1% 1/20W MF 201

2

PLACE_NEAR=U0500.AR18:6MM

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

7 OF 145

SHEET

7 OF 119

A

8 7 5 4 2 1

36

D

C

B

A

PP1V2_S3_CPUDDR

100

PP1V2_S3_CPUDDR

100

PP1V0_S3

6 8 10 14 19 101

PP1V0_S0SW

6 8 10 17 101

PP1V2_S0SW

10 100

PP1V0_S3

10 101

PP1V0_SUS

8 12 101

PPVCCPRIMCORE_SUS_PCH

12 55 100

PP1V_S5_PCH_DCPDSW

19 12

PP1V0_SUS

12 101

PP1V0_SUSSW

12 101

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

12

PP1V_SUS_PCH_VCCAPLL_F

12

PP1V0_SUS

8 12 101

PP3V3_S5

14 101

PP1V8_S0_PCH_VCCHDA_F

12

PP3V3_SUS

13 101

PP1V0_SUSSW

12 101

PP3V3_SUS

5 8 12 101

PP1V0_SUSFUSE

78 12

PP1V0_SUSSW

12 101

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18

A22

AL23

K20 K21

AB19 AB20

P18

AF18 AF19

V20 V21

AL1

K17

L1

N15 N16 N17 P15 P16

K15 L15

V15

AB17

Y18

AD17 AD18 AJ17

AJ19

AJ16

AF20 AF21

T19 T20

AJ21

AK20

N18

OMIT_TABLE

SKL-ULT-2+3E

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQC

VCCST

VCCSTG

VCCPLL_OC

VCCPLL VCCPLL

OMIT_TABLE

SKL-ULT-2+3E

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0 VCCMPHYAON_1P0

VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0

VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0 VCCPRIM_1P0

VCCDSW_3P3 VCCDSW_3P3 VCCDSW_3P3

VCCHDA

VCCSPI

VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0

VCCPRIM_3P3

VCCPRIM_1P0

VCCAPLLEBB_1P0

U0500

TBD

BGA

SYM 14 OF 20

CPU POWER 3

U0500

TBD

BGA

SYM 15 OF 20

CPU POWER 4

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC VCCRTC

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

PPVCCIO_S0_CPU

PPVCCSA_S0_CPU

CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N

CPU_VCCSASENSE_N CPU_VCCSASENSE_P

PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP1V8_SUS PP3V3_SUS

PP3V3_SUS

PP1V0_SUS

PP1V8_SUS

PP3V3_SUS

PP3V0_G3H

PPDCPRTC_PCH

PP1V0_SUS

PP1V_SUS_PCH_VCCCLK2_F

PP1V0_SUS

PP1V_SUS_PCH_VCCCLK4_F

PP1V_SUS_PCH_VCCCLK5_F

PP1V0_SUS

NC_VCCPRIM_CORE_VID0 NC_VCCPRIM_CORE_VID1

PPVCCEDRAM_S0_CPU

8 100

PPVCCEDRAM_S0_CPU

100

PPVCCEDRAM_S0_CPU

100

PP1V8_SUS

100

PP1V8_SUS

100

CPU_VCCOPCSENSE_P

8

CPU_VCCOPCSENSE_N

8

PPVCCEDRAM_S0_CPU

8 100

PPVCCEDRAM_S0_CPU

100

CPU_VCCEOPIOSENSE_P

8

CPU_VCCEOPIOSENSE_N

8

5 8 100

8 55 100

OUT

13 14 15 16 101

12 101

101

12 101

14 19 100

101

5 8 12 101

8 12 101

12 100

12 101

12 14 15 100

101

12

101

12

101

OUT

75 8

67 8

19 12

19

PPVCCIO_S0_CPU

5 8 100

PPVCCSA_S0_CPU

8 55 100

PPVCCGT_S0_CPU

8 54 100

PPVCCGT_S0_CPU

8 100

PPVCCEDRAM_S0_CPU

8 100

PPVCCEDRAM_S0_CPU

8 100

PPVCC_S0_CPU

8 54 100 104

PPVCC_S0_CPU

A30

VCC

A34

VCC

A39

VCC

A44

VCC

NC

AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40 AM32 AM33 AM35 AM37 AM38

AK32

AB62

AC63 AE63

AE62 AG62

AL63 AJ62

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

G30

VCC

K32

RSVD

VCCOPC

P62

VCCOPC

V62

VCCOPC

H63

VCC_OPC_1P8

G61

VCC_OPC_1P8

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

8 54 100 104

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD

BGA

SYM 12 OF 20

CPU POWER 1

PLACE_NEAR=U0500.AM23:50.8MM

R0801

PLACE_NEAR=U0500.H20:50.8MM

R0804

PLACE_NEAR=U0500.J70:50.8MM

R0811

PLACE_NEAR=U0500.AK62:50.8MM

R0813

PLACE_NEAR=U0500.AC63:50.8MM

R0821

PLACE_NEAR=U0500.AL63:50.8MM

R0823

PLACE_NEAR=U0500.E32:50.8MM

R0825

1 2

PLACE_NEAR=U0500.AM22:50.8MM

R0802

PLACE_NEAR=U0500.H21:50.8MM

R0803

PLACE_NEAR=U0500.J69:50.8MM

R0812

PLACE_NEAR=U0500.AL61:50.8MM

R0814

PLACE_NEAR=U0500.AE63:50.8MM

R0822

PLACE_NEAR=U0500.AJ62:50.8MM

R0824

PLACE_NEAR=U0500.E33:50.8MM

R0826

G32

VCC

G33

VCC

G35

VCC

G37

VCC

G38

VCC

G40

VCC

G42

VCC

J30

VCC

J33

VCC

J37

VCC

J40

VCC

K33

VCC

K35

VCC

K37

VCC

K38

VCC

K40

VCC

K42

VCC

K43

VCC

E32

VCC_SENSE VSS_SENSE

VIDALERT*

VIDSCK

VIDSOUT

VCCSTG

CPU_VCCSENSE_P

E33

CPU_VCCSENSE_N

B63

CPU_VIDALERT_R_L

A63

CPU_VIDSCLK_R

D64

CPU_VIDSOUT_R

G20

PP1V0_S0SW

12

100

5% 1/20W MF 201

100

5% 1/20W MF 201

100

5% 2011/20W MF

100

5%

CPU_VCCIOSENSE_P

MF1/20W5% 201

CPU_VCCSASENSE_P

1/20W5% MF 201

CPU_VCCGTSENSE_P

CPU_VCCGTXSENSE_P

1/20W5% MF 201

CPU_VCCOPCSENSE_P

CPU_VCCEOPIOSENSE_P

MF 2011/20W5%

CPU_VCCSENSE_P

1/20W MF 2015%

CPU_VCCIOSENSE_N

MF1/20W 2015%

CPU_VCCSASENSE_N

MF5% 2011/20W

CPU_VCCGTSENSE_N

MF1/20W5%

201

CPU_VCCGTXSENSE_N

CPU_VCCOPCSENSE_N

201MF1/20W5%

CPU_VCCEOPIOSENSE_N

1/20W MF 2015%

CPU_VCCSENSE_N

MF1/20W 201

OUT

67 8

8 67

6 8 10

67 8

R0829

220

1 2

1%

1/20W

MF

201

17 101

1 2

R0831

1 2

5%

1/20W

MF

0201

345678

PPVCCGT_S0_CPU

8 54 100

75 8

67 8

8

67 8

75 8

67 8

8

67 8

OUT

R0830

0

CPU_VCCGTSENSE_P CPU_VCCGTSENSE_N

PP1V0_S3

1

R0827

56

1% 1/20W MF 201

2

0

5%

1/20W

MF

0201

2 1

OMIT_TABLE

SKL-ULT-2+3E

A48

VCCGT

A53

VCCGT

A58

VCCGT

A62

VCCGT

A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

1

R0828

100

1% 1/20W MF 201

2

PLACE_NEAR=U0500.B63:12.7MM

CPU_VIDALERT_L

PLACE_NEAR=U0500.A63:12.7MM

CPU_VIDSCLK

PLACE_NEAR=U0500.D64:12.7MM

CPU_VIDSOUT

BOM_COST_GROUP=CPU & CHIPSET

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

J43

VCCGT

J45

VCCGT

J46

VCCGT

J48

VCCGT

J50

VCCGT

J52

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K48

VCCGT

K50

VCCGT

K52

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_SENSE

J69 AL61

VSSGT_SENSE

6 8 10 14 19 101

67

IN

67

OUT

BI

67

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

U0500

TBD

BGA

SYM 13 OF 20

CPU POWER 2

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGTX_SENSE VSSGTX_SENSE

CPU & PCH Power

Apple Inc.

R

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62

PPVCCGT_S0_CPU

CPU_VCCGTXSENSE_P CPU_VCCGTXSENSE_N

DRAWING NUMBER SIZE

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

8 OF 145

SHEET

8 OF 119

8

SYNC_DATE=03/14/2016SYNC_MASTER=J79_JSHAO

9.0.0

D

8 100

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

NC_CPU_NCTFVSS_A5

102

NC_CPU_NCTFVSS_A70

102

A5 A67 A70 AA2 AA4

AA65 AA68 AB15 AB16 AB18 AB21

AB8

AD13 AD16 AD19 AD20 AD21 AD62

AD8

AE64 AE65 AE66 AE67 AE68 AE69

AF1

AF10 AF15 AF17

AF2 AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH6

AH63 AH64 AH67 AJ15 AJ18 AJ20

AJ4

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8 AL2

AL28 AL32 AL35 AL38

AL4

AL45 AL48 AL52 AL55 AL58 AL64

OMIT_TABLE

U0500

SKL-ULT-2+3E

SYM 16 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

TBD BGA

GND1

VSSVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

NC_CPU_NCTFVSS_AV1

102

NC_CPU_NCTFVSS_B71

102

NC_CPU_NCTFVSS_BA1

102

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8 AY66

B10

B14

B18

B22

B30

B34

B39

B44

B48

B53

B58

B62

B66

B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68 BA45

OMIT_TABLE

U0500

SKL-ULT-2+3E

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SYM 17 OF 20

TBD

BGA

GND2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

NC_CPU_NCTFVSS_BA71

NC_CPU_NCTFVSS_BB70 NC_CPU_NCTFVSS_C1

102

F8 G10 G22 G43 G45 G48

G5 G52 G55 G58

G6 G60 G63 G66 H15 H18 H71 J11 J13 J25 J28 J32 J35 J38 J42

J8 K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD

BGA

SYM 18 OF 20

GND 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

D

C

B

A

PAGE TITLE

CPU & PCH Grounds

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=05/12/2015SYNC_MASTER=J79_ALFRED

051-00515

9.0.0

dvt-fab09-0

9 OF 145

9 OF 119

A

D

345678

2 1

D

PPVCC_S0_CPU

100

1

C1000

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100I

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1010

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1001

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100J

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1011

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1002

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100K

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1012

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1003

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100L

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1013

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1004

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100M

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1014

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1005

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100N

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1015

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1006

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100O

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1016

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1007

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100P

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1017

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1008

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100Q

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1018

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1009

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100R

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1019

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C100A

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100S

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100B

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100T

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100C

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100U

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100D

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100V

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100E

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100W

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100F

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100X

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100G

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100Y

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100H

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V2_S3_CPUDDR

100

PP1V2_S3_CPUDDR

100

1

C1050

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1060

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1051

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1061

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1062

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1063

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1052

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1064

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1053

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1065

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1054

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1066

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1055

1UF

20%

6.3V

2

X6S-CERM 0201

D

C

1

C1020

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10G0

220UF

20% 2V

23

ELEC SM-COMBO

1

C1021

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1022

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10G1

220UF

20% 2V

23

ELEC SM-COMBO

1

C1023

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1024

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10H1

220UF

20% 2V

23

ELEC SM-COMBO

1

C1025

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1026

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10G3

220UF

20% 2V

23

ELEC SM-COMBO

1

C1027

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1028

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1029

20UF

20%

2.5V

2

X6S-CERM 0402-1

PPVCCIO_S0_CPU

100

1

C1070

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1071

1UF

20%

6.3V

2

X6S-CERM 0201

Primary Backside

1

C1080

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1090

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1081

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1091

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1092

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1093

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1082

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1094

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1083

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1095

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1084

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1085

1UF

20%

6.3V

2

X6S-CERM 0201

C

B

PPVCCEDRAM_S0_CPU

100

1

C10D0

2

PPVCCEDRAM_S0_CPU

100

1

C10E0

2

20UF

20%

2.5V X6S-CERM 0402-1

20UF

20%

2.5V X6S-CERM 0402-1

1

C10E1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10D1

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D2

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D3

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D4

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D5

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D6

1UF

20%

6.3V

2

X6S-CERM 0201

PPVCCSA_S0_CPU

100

1

C10A0

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10B0

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C0

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A1

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10B1

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A2

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C10B2

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C2

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A3

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C10B3

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A4

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10B4

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C4

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A5

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10B5

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C5

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A6

1UF

20%

6.3V

2

X6S-CERM 0201

B

A

PP1V0_S3

8 101

1

C10F0

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V2_S0SW

8 100

1

C10F1

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V0_S3

6 8 14 19 101

1

C10F2

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V0_S0SW

6 8 17 101

1

C10F3

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10H0

220UF

20% 2V

23

ELEC SM-COMBO

SYNC_MASTER=J79_JSHAO SYNC_DATE=08/28/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

CPU Core Decoupling

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

10 OF 145

SHEET

10 OF 119

A

D

8 7 5 4 2 1

36

PPVCCGT_S0_CPU

100

345678

2 1

D

1

C1100

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110E

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1110

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1101

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110F

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1111

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1102

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110G

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1112

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1103

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110H

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1113

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1104

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110I

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1114

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1105

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110J

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1115

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1106

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110K

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1116

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1107

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110L

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1117

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1108

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110M

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1118

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1109

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110N

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1119

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C110A

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110O

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110B

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110P

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110C

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110Q

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110D

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110R

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110S

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110T

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110U

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110V

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110W

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110X

1UF

20%

6.3V

2

X6S-CERM 0201

D

C

NOSTUFF

1

C1120

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1121

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1122

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1161

220UF

20%

2.0V

23

POLY-TANT D15T-D1L-COMBO

NOSTUFF

1

C1123

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1124

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1162

220UF

20% 2V

23

ELEC SM-COMBO

1

C1125

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1126

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1163

220UF

20% 2V

23

ELEC SM-COMBO

1

C1127

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1128

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

23

C1164

220UF

20% 2V ELEC SM-COMBO

1

C1129

20UF

20%

2.5V

2

X6S-CERM 0402-1

C

B

PPVCCGT_S0_CPU

100

1

C1170

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1180

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1171

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1181

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1172

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1182

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1173

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1183

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1174

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1184

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1175

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1185

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1176

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1186

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1177

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1187

20UF

20%

2.5V

2

X6S-CERM 0402-1

B

A

1

C1190

220UF

20% 2V

23

ELEC SM-COMBO

8 7 5 4 2 1

1

C1191

220UF

20% 2V

23

ELEC SM-COMBO

SYNC_MASTER=J79_JSHAO SYNC_DATE=08/28/2015

PAGE TITLE

CPU GT Decoupling

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

11 OF 145

11 OF 119

A

D

345678

2 1

D

78 8

PP1V0_SUSFUSE

BYPASS=U0500.AK20::10MM

PP1V0_SUS

8 101

BYPASS=U0500.AB19::10MM

PP1V0_SUS

8 101

BYPASS=U0500.K17::3MM

1

C1208

1000PF

10% 25V

2

X7R 0201

1

C1200

1000PF

10% 25V

2

X7R 0201

1

C1201

1UF

20%

6.3V

2

X6S-CERM 0201

PP3V3_SUS

5 8 101

PP3V3_SUS

8 101

BYPASS=U0500.T16::3MM

BYPASS=U0500.AK17::3MM

1

C1220

1000PF

10% 25V

2

X7R 0201

1

C1221

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1222

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U0500.AK17::3MM

101

PP1V0_SUSSW

1

C1204

1UF

20%

6.3V

2

X6S-CERM 0201

FILTER PLACEHOLDERS ONLY

OMIT_TABLE

L1250

2.2UH-240MA-0.221OHM

1 2

0603

CRITICAL NOSTUFF

1

C1250

47UF

20%

6.3V

2

POLY-TANT 0805

BYPASS=U0500.K15::3MM

PCH SIDERAIL SIDE

PP1V_SUSSW_PCH_VCCAMPHYPLL_F PP1V_SUSSW_PCH_VCCAMPHYPLL_F

MAKE_BASE=TRUE

8

D

19

C

PP1V0_SUSSW

8 101

PP1V0_SUSSW

8 101

PP1V0_SUSSW

8 101

BYPASS=U0500.N15::3MM

BYPASS=U0500.AF20::10MM

BYPASS=U0500.N18::3MM

1

C1202

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1205

1000PF

10% 25V

2

X7R 0201

1

C1206

1UF

20%

6.3V

2

X6S-CERM 0201

CRITICAL NOSTUFF

1

C1203

47UF

20%

6.3V

2

POLY-TANT 0805

8 101

BYPASS=U0500.N15::10MM

8 101

8 14 15 100

PP3V3_SUS

BYPASS=U0500.AG15::3MM

PP3V3_SUS

BYPASS=U0500.V19::10MM

PP3V3_SUS

BYPASS=U0500.Y16::10MM

PP3V0_G3H

BYPASS=U0500.AK19::3MM

1

C1223

1000PF

10% 25V

2

X7R 0201

1

C1224

1000PF

10% 25V

2

X7R 0201

1

C1225

1000PF

10% 25V

2

X7R 0201

1

C1227

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1228

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U0500.AK19::3MM

101

PP1V0_SUS

OMIT_TABLE

L1252

2.2UH-240MA-0.221OHM

1 2

0603

CRITICAL NOSTUFF

1

C1252

47UF

20%

6.3V

2

POLY-TANT 0805

OMIT_TABLE

L1253

2.2UH-240MA-0.221OHM

1 2

0603

CRITICAL NOSTUFF

1

C1253

47UF

20%

6.3V

2

POLY-TANT 0805

OMIT_TABLE

L1254

2.2UH-240MA-0.221OHM

1 2

0603

CRITICAL NOSTUFF

1

C1254

47UF

20%

6.3V

2

POLY-TANT 0805

MAKE_BASE=TRUE

PP1V_SUS_PCH_VCCCLK5_F PP1V_SUS_PCH_VCCCLK5_F

PP1V_SUS_PCH_VCCCLK4_F PP1V_SUS_PCH_VCCCLK4_F

PP1V_SUS_PCH_VCCCLK2_F PP1V_SUS_PCH_VCCCLK2_F

8

19

8

19

8

19

C

B

19 8

PPVCCPRIMCORE_SUS_PCH

8 55 100

BYPASS=U0500.AF18::10MM

PPDCPRTC_PCH

100

1

C1210

1000PF

10% 25V

2

X7R 0201

1

C1231

0.1UF

10% 10V

2

X5R-CERM 0201

PP1V8_S0

1

C1264

12PF

5% 25V

2

NP0-C0G 0201

1

C1265

2.9PF

+/-0.05PF 25V

2

C0G-CERM 0201

8 100

19 8

R1260

0

1 2

5%

1/20W

MF

0201

PP1V8_SUS

BYPASS=U0500.AA1::10MM

PP1V_S5_PCH_DCPDSW

BYPASS=U0500.AL1::3MM

10% 25V X7R

0201

1

2

C1226

1000PF

C1260

2.9PF

+/-0.05PF

25V

C0G-CERM

0201

1

C1230

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1232

1UF

20%

6.3V

2BYPASS=U0500.BB10::3MM

X6S-CERM 0201

1

2

PP1V8_S0_PCH_VCCHDA_F

MAKE_BASE=TRUE

BYPASS=U0500.AJ19::10MM

8

19

100

PP1V8_SUS

NOSTUFF

R1251

0

1 2

5%

1/20W

MF

0201

BYPASS=U0500.U11::10MM

L1250,L1252,L1253,L12544113S0022 RES,MF,1A MAX,0OHM,5%,0603

NOSTUFF

1

C1251

1UF

20%

6.3V

2

X6S-CERM 0201

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

FOR FUTURE PRODUCT PER PDG

PP1V8_SUS_PCH_VCC1P8 PP1V8_SUS_PCH_VCC1P8

PP1V8_SUS_PCH_VCC1P8

MAKE_BASE=TRUE

B

5

19

A

BYPASS=U0500.AJ19::10MM

R1261

0

PP1V0_SUS

15 101

1

C1267

2.9PF

+/-0.05PF 25V

2

C0G-CERM 0201

1 2

5%

1/20W

MF

0201

10% 25V X7R

0201

1

2

C1262

2.9PF

+/-0.05PF

C0G-CERM

C1261

1000PF

BYPASS=U0500.V15::10MM

25V

0201

1

2

BYPASS=U0500.V15::10MM

8 7 5 4 2 1

PP1V_SUS_PCH_VCCAPLL_F PP1V_SUS_PCH_VCCAPLL_F

MAKE_BASE=TRUE

8

19

BOM_COST_GROUP=CPU & CHIPSET

36

PAGE TITLE

PCH Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

12 OF 145

12 OF 119

D

A

SYNC_DATE=03/14/2016SYNC_MASTER=J79_JSHAO

345678

2 1

D

60

105 60

60

OUT

IN

OUT

HDA_SYNC

OUT

HDA_BIT_CLK

OUT

HDA_SDOUT HDA_SDIN0

HDA_RST_L

PLACE_NEAR=U0500.BA22:10mm

R1300

PLACE_NEAR=U0500.AY22:10mm

R1301

PLACE_NEAR=U0500.BB22:10mm

R1302

PLACE_NEAR=U0500.AW22:10mm

R1303

33

1 2

33

1 2

33

1 2

33

1 2

5% 1/20W

5%

MF 201

1/20W

HDA_SYNC_R

19

MF

HDA_BIT_CLK_R HDA_SDOUT_R

19 18

HDA_RST_R_L

19

MF 2015% 1/20W

MF5% 1/20W

201

28 13

94 28

17

19

13

19

49

XDP_PCH_OBSDATA_C0

OUT

CKPLUS_WAIVE=CLK_DATA_CON

PCH_DDPB_CTRLDATA

IN

JTAG_TBT_X_TMS

OUT

JTAG_TBT_T_TMS

BI

PCH_DDPC_CTRLDATA

IN

MLB_RAMCFG0

13

MLB_RAMCFG1

13

NC_PCH_BSSB_CLK

IN

NC_PCH_BSSB_DATA

IN

PCH_STRP_TOPBLK_SWP_L

IN

NC

NC NC

BA22 AY22 BB22 BA21 AY21 AW22

D8 AY20 AW20

L12 L13

N7

N8

U1

U2

P4

P1

AW5

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD

HDA_RST*/I2S1_SCLK GPP_D17/DMIC_CLK1 I2S1_SFRM I2S1_TXD

GPP_E19/DDPB_CTRLDATA GPP_E18/DDPB_CTRLCLK GPP_E20/DDPC_CTRLCLK GPP_E21/DDPC_CTRLDATA

GPP_D13/ISH_UART0_RXD/

SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/

SML0BCLK/I2C4B_SCL

GPP_D11 GPP_D12

GPP_B14/SPKR

(BSSB_CLK) (BSSB_DATA_IN)

(STRAP)

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 7 OF 20

(1.8V)

(STRAP)

GPP_A17/SD_PWR_EN*/ISH_GP7

(1.8V)

SDIO/SDXC

GPP_F18/EMMC_DATA5HDA_SDI1/I2S1_RXD GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F23

GPP_G0/SD_CMD

GPP_G1/SD_DATA0

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F17/EMMC_DATA4

AN2 AM4 AM1 AM2 AM3 AF13 AB11 AB13

BA9 BB9

AB7

AN1

ALL GPP_F* PINS ARE 1.8V ONLY!

SD_RCOMP

R1370

200

1%

1/20W

MF

201

PCH_SOC_DFU_STATUS

SOC_PANIC_L

SOC_S2R_ACK_L

SOC_PCH_DBELL_L

DEBUGUART_SEL_SOC

SSD_PWR_EN_L TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

NC_CAMERA_RESET_L

CAMERA_PWR_EN

PCH_SOC_WDOG

1

2

37 19

38 19

19 38

OUT

IN

D

19

104 91

28 13

19

37

C

59

59 17

59

59 13

19 13

48 13

OUT

BI

OUT

IN

SPI_CLK_R SPI_MISO SPI_MOSI_R SPI_IO<2> SPI_IO<3> SPI_CS0_R_L NC_SPI_CS1_L

102

NC_SPI_CS2_L

102

ALS_SOC_UART_R2D PD_LCD_PSR_EN PD_SSD_UART_CTS_L MLB_RAMCFG2

13

MLB_RAMCFG3

13

ALS_SOC_UART_D2R

PU_PCH_RCIN_L

13

LPC_SERIRQ

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0*

AU2

SPI0_CS1*

AU1

SPI0_CS2*

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS*

AD4

GPP_C23/UART2_CTS*

U3

GPP_D15/ISH_UART0_RTS*

U4

GPP_D16/ISH_UART0_CTS*/

SML0BALERT*

AD1

GPP_C20/UART2_RXD

G3

NC NC NC

AW13 AY11 AW11

CL_CLK

G2

CL_DATA

G1

CL_RST*

GPP_A0/RCIN* GPP_A6/SERIRQ

IO1

IO0

SYM 5 OF 20

SPI-FLASH

SMBUS,SMLINK

(STRAP)

SPI-TOUCH

LPC

C LINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

(STRAP)

GPP_B23/SML1ALERT*/PCHHOT*

GPP_A5/LFRAME*/ESPI_CS*

GPP_A14/SUS_STAT*/ESPI_RESET*

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C2/SMBALERT*

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT*

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN*

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9

PLACE_NEAR=U0500.AB7:12.7MM

SMBUS_PCH_CLK SMBUS_PCH_DATA NC_PCH_STRP_TLSCONF

SML_PCH_0_CLK SML_PCH_0_DATA NC_PCH_STRP_ESPI

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA NC_PCH_STRP_BSSB_SEL_GPIO

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3> LPC_FRAME_R_L LPC_PWRDWN_L

LPC_CLK24M_SMC_R NC_PCH_CLKOUT_LPC1 LPC_CLKRUN_L

OUT

19

OUT

19

OUT

19

R1320 R1321 R1322 R1323 R1325

OUT

R1327

19

BI

51

48

51

33 33 33 33 33

22

48 13

1 2 1 2 1 2 1 2 1 2

1 2

C

MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W

LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L

LPC_CLK24M_SMC

MF 2015% 1/20W

LPC_AD<0>

BI

OUT

48

105 48

B

A

PP3V3_SUS

R1344 R1343 R1342 R1341 R1340 R1350 R1351 R1352 R1353 R1354 R1355 R1356 R1357 R1358 R1359

10K

1K

10K 100K 100K

10K 100K

47K

10K

10K 100K 100K 100K

PP3V3_S0

PP3V3_SUS

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

5% 1/20W 201MF

5 14 16 19 94 101

8 14 15 16 101

8 101

MF 2015% 1/20W

1/20W5% MF

MF1/20W 2015%

1/20W5% 201MF

MF1/20W 2015%

MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W

201

2015% 1/20W MF 2015% MF1/20W

2015% 1/20W MF

PU_PCH_RCIN_L

SPI_CS0_R_L LPC_SERIRQ BT_PWRRST_L BT_TIMESTAMP

LPC_CLKRUN_L

CAMERA_PWR_EN

ALS_SOC_UART_D2R

ALS_SOC_UART_R2D

PD_SSD_UART_CTS_L

JTAG_TBT_X_TMS

JTAG_TBT_T_TMS

TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

PD_LCD_PSR_EN

13

59 13

48 13

105 6

35 6

48 13

19

13 19

13 28

13 28 94

28 13

13 19

MEMORY CONFIGURATION STRAPS.

PCH INTERNAL PULL-UPS ARE TO 3.3V.

MLB_RAMCFG0

13

MLB_RAMCFG1

13

MLB_RAMCFG2

13

MLB_RAMCFG3

13

MLB_RAMCFG4

6

RAMCFG4_L

1

R1334

1K

5% 1/20W MF 201

2

BOM GROUP BOM OPTIONS

RAMCFG_SLOT RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG1_L,RAMCFG0_L

RAMCFG3_L

1

R1333

1K

5% 1/20W MF 201

2

RAMCFG2_L

1

R1332

1K

5% 1/20W MF 201

2

RAMCFG1_L

1

R1331

1K

5% 1/20W MF 201

2

RAMCFG0_L

1

R1330

1K

5% 1/20W MF 201

2

PAGE TITLE

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM_COST_GROUP=CPU & CHIPSET

DESIGN: X502/MLB LAST CHANGE: Tue Feb 2 13:18:21 2016

PCH Audio/LPC/SPI/SMBus

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

13 OF 145

SHEET

13 OF 119

9.0.0

D

B

A

SYNC_DATE=02/22/2016SYNC_MASTER=J130_MLB

8 7 5 4 2 1

36

PCH Reset Button

345678

2 1

D

48 17

74

48

IN

8 13 15 16 101

5 13 14 16 19 94 101

PP1V0_S3

6 8 10 19 101

PP3V3_S0

R1405

PM_SYSRST_L

CPU_VCCST_PWRGD

VCCST_PWRGD 1V TOLERANT

PM_DSW_PWRGD

R1403

PP3V3_SUS

1

1K

5%

1/20W

MF

201

2

1

100K

5%

1/20W

MF

201

2

NOSTUFF

1

R1407

2.2K

5% 1/20W MF 201

2

1

R1408

2.2K

5% 1/20W MF 201

2

R1406

60.4

1 2

201 MF

PLACE_NEAR=U0500.B65:38mm

50

NO STUFF

50

1%

1/20W

OUT

R1400

0

5%

1/20W

MF

0201

IN

2

1

104 35 19

77 48 17

104 73 48

74

18 14

48 14

OUT

IN

PLT_RST_L

PM_RSMRST_L

TP_CPU_PWRGD CPU_VCCST_PWRGD_R

PM_PCH_SYS_PWROK PM_PCH_PWROK

SMC_PCH_SUSWARN_L SMC_PCH_SUSACK_L

PCIE_WAKE_L SMC_WAKE_SCI_L NC_PCH_LANPHYPC

102

NC_PCH_GPD7

102

AN10

B5

AY17

A68 B65

B6 BA20 BB20

AR13 AP11

BB15 AM15 AW17 AT15

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 11 OF 20

SYSTEM POWER MANAGEMENT

GPP_B13/PLTRST* SYS_RESET* RSMRST*

PROCPWRGD VCCST_PWRGD

SYS_PWROK PCH_PWROK DSW_PWROK

GPP_A13/SUSWARN*/SUSPWRDNACK GPP_A15/SUSACK*

WAKE* GPD2/LAN_WAKE* GPD11/LANPHYPC GPD7/RSVD

(1V ONLY)

GPP_B12/SLP_S0*

GPD4/SLP_S3* GPD5/SLP_S4*

GPD10/SLP_S5*

SLP_SUS* SLP_LAN*

GPD9/SLP_WLAN*

GPD6/SLP_A*

GPD3/PWRBTN*

GPD1/ACPRESENT

GPD0/BATLOW*

GPP_A11/PME*

INTRUDER*

GPP_B11/EXT_PWR_GATE*

GPP_B2/VRALERT*

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

NC

PM_SLP_S0_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L

PM_SLP_SUS_L

NC_PCH_SLP_WLAN_L NC_PCH_SLP_A_L

PM_PWRBTN_L SSD_SR_EN_L PM_BATLOW_L

NC_PCH_PME_L PCH_INTRUDER_L

PCH_HSIO_PWR_EN BT_LOW_PWR_L

OUT

102

OUT

102

OUT

IN

78

D

104 74 48 19 14

104 92 80 77 74 73 48 26 19 14

104 77 74 48 43 19 14

104 77 48 19 14

104 77 74 14

PP3V0_G3H

50 14

102 14

94 48 28 14

35 14

1

R1401

1M

5% 1/20W MF 201

2

8 12 15 100

C

R1400 kept for debug purposes.

C

B

A

R1446 R1445 R1444 R1443 R1442 R1441 R1440 R1450 R1451 R1452 R1453

R1454 R1455 R1456 R1457 R1458

PP1V8_SUS

PP3V3_S5 PP3V3_S4 PP3V3_S0

100K 100K 100K 100K 100K

10K

100K

1K 10K 10K

100K

100K 100K 100K 220K 100K

NOTE: PM_SLP_S0_L HAS INTERNAL PULL-UP BEFORE RSMRST_L IS RELEASED. THIS CAUSES A VOLTAGE DIVIDER WITH THE PULL-DOWN HERE. THE SIGNAL IS DRIVEN HI AFTER RSMRST_L IS RELEASED.

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2

5% 1/20W 201MF

5% 201 5% MF 5% 201MF

5% 201MF

8 19 100

8 101

101

5 13 14 16 19 94 101

1/20W5% 201MF

MF1/20W5%

MF1/20W5% 201

MF 1/20W5% MF 1/20W5% MF 1/20W MF 1/20W 201 1/20W

1/20W5% 201MF 1/20W 1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF

201

2015% MF1/20W 2011/20W5% 201 201

SOC_SWD_CLK PCH_SWD_IO PCH_SWD_MUX_SEL PCH_SOC_DBELL SSD_BOOT_L BT_LOW_PWR_L SSD_SR_EN_L PM_PWRBTN_L PM_BATLOW_L PCIE_WAKE_L SMC_WAKE_SCI_L

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L PM_SLP_SUS_L

14 19 42

42 14

14 19 37

104 91 14

35 14

102 14

14 50

18 14

48 14

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 9 OF 20

A36

NC NC NC NC NC NC NC NC

NC NC

94 48 28 14

104 77 48 19 14

104 77 74 48 43 19 14

104 92 80 77 74 73 48 26 19 14

104 74 48 19 14

104 77 74 14

NC NC NC NC NC NC

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27 AT1

CSI2_DP11

CSI-2

EMMC

(1.8V)

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_F12/EMMC_CMD GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1

GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D0/SPI1_CS*

GPP_F7/I2C3_SCL GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

GPP_F6/I2C3_SDA

EMMC_RCOMP

C37 D37 C32 D32 C29 D29 B26 A26

E13 M1

AH12 AF11 AF12 AD11 AD12 AP4 AP2 AP1

AP3 AN3 AH11

NC NC NC NC NC NC NC NC

CSI2_COMP

NC_PCH_GPP_D0

ALL GPP_F* PINS ARE 1.8V ONLY!

NC_PCH_GPP_F8 NC_PCH_GPP_F9

NC_PCH_GPP_F10

PCH_BT_ROM_BOOT

PCH_SWD_MUX_SEL

PCH_SOC_DBELL

PCH_SOC_FORCE_DFU

NC_UPC_I2C_INT_L

EMMC_RCOMP

200

1%

1/20W

MF

201

1

2

R1481

PLACE_NEAR=U0500.AT1:12.7MM

100

1%

1/20W

MF

201

1

2

102

OUT

102

35 19

OUT

BI

OUT

14 19 37

OUT

IN

104 91 14

42 19 14

42 14

38

19

R1480

PLACE_NEAR=U0500.E13:12.7MM

SSD_BOOT_L

SOC_SWD_CLK

PCH_SWD_IO

BOM_COST_GROUP=CPU & CHIPSET

DESIGN: X502/MLB LAST CHANGE: Tue May 3 17:45:28 2016

PAGE TITLE

PCH Power Management

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

14 OF 145

SHEET

14 OF 119

9.0.0

D

B

A

SYNC_DATE=05/04/2016SYNC_MASTER=J130_MLB

8 7 5 4 2 1

36

D

C

PCIe Port Assignments:

SSD LANE 0

SSD LANE 1

SSD LANE 2

SSD LANE 3

Thunderbolt X lane 0

Thunderbolt X lane 1

Thunderbolt X lane 2

Thunderbolt X lane 3

AirPort

CAMERA

PLACE_NEAR=U0500.F5:12.7mm

100

1%

1/20W

MF

201

1

2

R1504

Thunderbolt T lane 0

Thunderbolt T lane 1

105 91

105 81

105 84

105 81

105 84

105 81

105 84

105 28

28

35

102

17

48 15

105 94

94

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

PCIE_SSD_D2R_N<0> USB3_EXTA_D2R_N PCIE_SSD_D2R_P<0> PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_C_P<0>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1> PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2> PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3> PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

PCIE_TBT_X_D2R_N<0> PCIE_TBT_X_D2R_P<0> PCIE_TBT_X_R2D_C_N<0> PCIE_TBT_X_R2D_C_P<0>

PCIE_TBT_X_D2R_N<1> PCIE_TBT_X_D2R_P<1> PCIE_TBT_X_R2D_C_N<1> PCIE_TBT_X_R2D_C_P<1>

PCIE_TBT_X_D2R_N<2> PCIE_TBT_X_D2R_P<2> PCIE_TBT_X_R2D_C_N<2> PCIE_TBT_X_R2D_C_P<2>

PCIE_TBT_X_D2R_N<3> PCIE_TBT_X_D2R_P<3> PCIE_TBT_X_R2D_C_N<3> PCIE_TBT_X_R2D_C_P<3>

PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

NC_PCIE_CAMERA_D2R_N

NC_PCIE_CAMERA_D2R_P NC_PCIE_CAMERA_R2D_C_N NC_PCIE_CAMERA_R2D_C_P

PCH_PCIE_RCOMP_N PCH_PCIE_RCOMP_P

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

SMC_RUNTIME_SCI_L

PCIE_TBT_T_D2R_N<0> PCIE_TBT_T_D2R_P<0> PCIE_TBT_T_R2D_C_N<0> PCIE_TBT_T_R2D_C_P<0> PCIE_TBT_T_D2R_N<1> PCIE_TBT_T_D2R_P<1> PCIE_TBT_T_R2D_C_N<1> PCIE_TBT_T_R2D_C_P<1>

H13 G13 B17 A17

G11 F11 D16 C16

H16 G16 D17 C17

G15 F15 B19 A19

F16 E16 C19 D19

G18 F18 D20 C20

F20 E20 B21 A21

G21 F21 D21 C21

E22 E23 B23 A23

F25 E25 D23 C23

F5 E5

D56 D61

BB11

E28 E27 D24 C24 E30 F30 A25 B25

PCIE1_RXP/USB3_5_RXP PCIE1_TXN/USB3_5_TXN PCIE1_TXP/USB3_5_TXP

PCIE2_RXN/USB3_6_RXN PCIE2_RXP/USB3_6_RXP PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP

PCIE3_RXN PCIE3_RXP PCIE3_TXN PCIE3_TXP

PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP

PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP

PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP

PCIE7_RXN/SATA0_RXN PCIE7_RXP/SATA0_RXP PCIE7_TXN/SATA0_TXN PCIE7_TXP/SATA0_TXP

PCIE8_RXN/SATA1A_RXN PCIE8_RXP/SATA1A_RXP PCIE8_TXN/SATA1A_TXN PCIE8_TXP/SATA1A_TXP

PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

PCIE_RCOMPN PCIE_RCOMPP

PROC_PRDY* PROC_PREQ* GPP_A7/PIRQA*

PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP PCIE11_TXN/SATA1B_TXN PCIE11_TXP/SATA1B_TXP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_TXN PCIE12_TXP/SATA2_TXP

SYM 8 OF 20

SSIC/USB3

USB2

PCIE/USB3/SATA

USB3_1_RXNPCIE1_RXN/USB3_5_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_2_RXN/SSIC_RXN USB3_2_RXP/SSIC_RXP USB3_2_TXN/SSIC_TXN USB3_2_TXP/SSIC_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E3/CPU_GP0 GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_D22/SPI1_IO3 GPP_D23/I2S_MCLK

GPP_E0/SATAXPCIE0/SATAGP0

GPP_D18/DMIC_DATA1

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

GPP_E2/SATAXPCIE2/SATAGP2

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A6 J1 J2 J3

V2 J5 H2

C8 H5 D7

G4

USB3_EXTA_D2R_P USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P

NC_USB3_EXTB_D2R_N NC_USB3_EXTB_D2R_P NC_USB3_EXTB_R2D_C_N NC_USB3_EXTB_R2D_C_P

TP_USB3_03_D2RN TP_USB3_03_D2RP TP_USB3_03_R2DN TP_USB3_03_R2DP

NC_USB3_04_D2RN NC_USB3_04_D2RP NC_USB3_04_R2DN NC_USB3_04_R2DP

NC_USB_EXTA_N NC_USB_EXTA_P

NC_USB_EXTB_N NC_USB_EXTB_P

USB_CAMERA_DFR_N USB_CAMERA_DFR_P

TP_USB_TESTERN TP_USB_TESTERP

NC_USB2_05N NC_USB2_05P

USB_UPC_PCH_XA_N USB_UPC_PCH_XA_P

USB_UPC_PCH_TA_N USB_UPC_PCH_TA_P

USB_UPC_PCH_XB_N USB_UPC_PCH_XB_P

USB_UPC_PCH_TB_N USB_UPC_PCH_TB_P

NC_USB2_10N NC_USB2_10P

PCH_USB2_COMP

PCH_USB2_VBUSSENSE

XDP_PCH_OBSFN_C1 XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI

XDP_PCH_OBSDATA_A2

XDP_PCH_OBSDATA_D0 XDP_PCH_OBSDATA_D1

XDP_PCH_OBSDATA_C1 XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3

XDP_PCH_OBSDATA_D3

NC_SPKR_ID0

OUT

104

19

104

19

28

94

28

94

19

IN

BI

345678

28

102

105 38

17

19

CKPLUS_WAIVE=CLK_DATA_CON

17

CKPLUS_WAIVE=CLK_DATA_CON

17

EXT A (SS,DCI)

EXT B (SS)

EXT A (LS/FS/HS)

EXT B (LS/FS/HS)

GROUNDED PER SKYLAKE MOW 2015WW10.

1

R1503

1K

5% 1/20W MF 201

2

PLACE_NEAR=U0500.AG4:12.7MM

2 1

1

R1501

113

1% 1/20W MF 201

2

PLACE_NEAR=U0500.AB6:12.7MM

D

C

B

A

R1550

100K

PP3V3_SUS

1 2

8 13 14 16 101

1/20W5% 201

ANY CLKREQ CAN MAP TO ANY CLK. ANY CLKREQ OR CLK CAN MAP TO ANY PCIE PORT. UNUSED CLKREQS AND CLKS SHOULD BE DISABLED. PER SKYLAKE PDG, SKYLAKE PCH EDS.

SMC_RUNTIME_SCI_L

MF

OMIT_TABLE

B

U0500

SKL-ULT-2+3E

TBD BGA

SYM 10 OF 20

CLOCK SIGNALS

91

OUT

91

OUT

19

IN

105 26

105 92

105 35

48 15

19

102

19

OUT

IN

OUT

IN

OUT

IN

OUT

IN

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P SSD_CLKREQ_L_R

PCIE_CLK100M_TBT_X_N PCIE_CLK100M_TBT_X_P TBT_X_CLKREQ_L_R

PCIE_CLK100M_TBT_T_N PCIE_CLK100M_TBT_T_P TBT_T_CLKREQ_L_R

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P AP_CLKREQ_L_R

NC_PCIE_CLK100M_CAMERA_N NC_PCIE_CLK100M_CAMERA_P NC_PCH_CLKREQ4_L

NC_PCIE_CLK100M5N

19

NC_PCIE_CLK100M5P

19

NC_PCH_CLKREQ5_L

19

D42 C42

AR10

B42 A42 AT7

D41 C41 AT8

D40 C40

AT10

B40 A40 AU8

E40 E38 AU7

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0*

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1*

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2*

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3*

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4*

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5*

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST*

RTCRST*

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

NC_ITPXDP_CLK100M_N NC_ITPXDP_CLK100M_P

PM_CLK32K_SUSCLK_R

PCH_CLK24M_XTALIN NC_PCH_CLK24M_XTALOUT

PCH_DIFFCLK_BIASREF

SYSCLK_CLK32K_PCH NC_PCH_CLK32K_RTCX2

PCH_SRTCRST_L RTC_RESET_L

19

OUT

IN

49

19

PP1V0_SUS

PLACE_NEAR=U0500.E42:2.54mm

1

R1520

2.7K

1% 1/20W MF 201

2

20K

1%

1/20W

MF

201

1UF

20%

6.3V 0201

1

2

1

2

R1530

C1530

X6S-CERM

BOM_COST_GROUP=CPU & CHIPSET

12 101

1

R1531

20K

1% 1/20W MF 201

2

1

C1531

1UF

20%

6.3V

2

X6S-CERM 0201

PP3V0_G3H

DESIGN: X502/MLB LAST CHANGE: Thu Jun 18 20:05:18 2015

SYNC_MASTER=J130_MLB SYNC_DATE=06/23/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

8 12 14 100

PCH PCIE/USB/CLKS

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

SHEET

A

D

9.0.0

15 OF 145

15 OF 119

8 7 5 4 2 1

36

345678

2 1

D

C

19 16

43 16

35 16

18 16

28 16

94 16

19 16

104 91 19

94 28 16

PU_AUD_SPI_CS_L

OUT

PD_AUD_SPI_CLK

OUT

PD_AUD_SPI_MISO

IN

PU_AUD_SPI_MOSI

OUT

TPAD_SPI_CS_L

OUT

TPAD_SPI_CLK

OUT

TPAD_SPI_MISO

IN

TPAD_SPI_MOSI

OUT

PCH_BT_UART_D2R

IN

PCH_BT_UART_R2D

OUT

PCH_BT_UART_RTS_L

OUT

PCH_BT_UART_CTS_L

IN

AP_S0IX_WAKE_SEL

OUT

AP_S0IX_WAKE_L

IN

TBT_X_CIO_PLUG_EVENT_L

IN

TBT_T_CIO_PLUG_EVENT_L

IN

PCH_SSD_SOC_UART_D2R

IN

PCH_SSD_SOC_UART_R2D

OUT

PU_SOC_UART_RTS_L

OUT

PD_SOC_UART_CTS_L

IN

SSD_RESET_L

IN

TBT_POC_RESET

OUT

BT_I2S_CLK_1V8

19

BT_I2S_SYNC_1V8

19

BT_I2S_R2D_1V8

19

BT_I2S_D2R_1V8

19

AN8 AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

W4

AB3

U7 U6 U8 U9

AC1 AC2

AC3 AB4

N11 N12

AK6 AK7

AK9

AK10

ALL GPP_F* PINS ARE 1.8V ONLY!

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD

LPSS ISH

GPP_B15/GSPI0_CS* GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS* GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS* GPP_C11/UART0_CTS*

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS*/ISH_UART1_RTS* GPP_C15/UART1_CTS*/ISH_UART1_CTS*

GPP_E22 GPP_E23

GPP_F0/I2S2_SCLK GPP_F1/I2S2_SFRM

GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

(STRAP)

(1.8V)

BGA

SYM 6 OF 20

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_D1/SPI1_CLK

GPP_D2/SPI1_MISO

GPP_D3/SPI1_MOSI GPP_D4/FLASHTRIG

(1.8V)

SX_EXIT_HOLDOFF*/GPP_A12/

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_G6/SD_CLK

GPP_D9

GPP_D10

GPP_G7/SD_WP

GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD*

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

BM_BUSY*/ISH_GP6

M4 N3 N1 N2

M2 M3

J4 B7

AH9 AH10

W8 P2 P3 W7

AB12 W12 W11 W10

AY8 BA8 BB7 BA7 AY7 AW7 AP13

MLB_BOARD_ID0 MLB_BOARD_ID1 MLB_BOARD_ID2 MLB_BOARD_ID3

NC_PCH_GPP_D1

NC_SPKR_ID1

NC_PCH_GPP_D3 NC_PCH_GPP_D4

16

102

19

102

NC_I2C_UPC_SDA NC_I2C_UPC_SCL

AP_RESET_L

MLB_BOARD_ID4

16

NC_MLB_DEV_L

PD_AP_DEV_WAKE

TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN TBT_X_PCI_RESET_L TBT_T_PCI_RESET_L

SPIROM_USE_MLB

LCD_IRQ_L DDI1_MUX_SEL DDI2_MUX_SEL

TPAD_SPI_IF_EN TPAD_SPI_INT_L

AUD_PWR_EN

OUT

IN

BI

19

94

19

28

D

36 35 19

19 16

C

59 16

104 80 16

43 16

61 16

B

A

R1643 R1642 R1641 R1640

R1650 R1652

R1653 R1654 R1655 R1656

R1657 R1658 R1659 R1660 R1674 R1676 R1673 R1675

R1661 R1662 R1663 R1664

R1665 R1666 R1667

R1669

R1668 R1671 R1672

47K 47K 47K 47K

100K

47K 47K 47K

1K

47K 47K

47K 150K 100K

10K 100K 100K

47K

100K 100K 100K

100K

100K 100K 100K

PP3V3_S0

PP3V3_SUS

1 2 1 2 1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

1 2 1 2 1 2

1 2

1 2 1 2 1 2

5 13 14 19 94 101

8 13 14 15 101

1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF

5% 201MF

1/20W

5% 1/20W

1/20W5% 201 1/20W 201MF

5% 5% 1/20W MF 201

1/20W5% 201

5% 2011/20W 5% 201MF1/20W

5% MF 2011/20W

5% 1/20W

1/20W5% MF 201 1/20W 201MF5%

5% 1/20W 201MF

1/20W5% 201MF 1/20W5% 201MF

1/20W5% MF 1/20W5% 201MF 1/20W5% 201MF

1/20W5% 201

1/20W

5% 201MF

1/20W5% 201MF 1/20W5% 201MF

MF

MF5% 2011/20W

MF 201

MF

201MF

2011/20W5% MF

201MF1/20W5%

2015% 1/20W MF

201

NOSTUFF NOSTUFF

NOSTUFF

PCH_SSD_SOC_UART_D2R PCH_SSD_SOC_UART_R2D PU_SOC_UART_RTS_L PD_SOC_UART_CTS_L

SPIROM_USE_MLB

AUD_PWR_EN PU_AUD_SPI_CS_L PD_AUD_SPI_CLK PD_AUD_SPI_MISO PU_AUD_SPI_MOSI

TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI

TPAD_SPI_INT_L

TPAD_SPI_IF_EN

PCH_BT_UART_D2R PCH_BT_UART_R2D PCH_BT_UART_RTS_L PCH_BT_UART_CTS_L

AP_S0IX_WAKE_SEL AP_S0IX_WAKE_L PD_AP_DEV_WAKE

LCD_IRQ_L

DRIVEN PUSH PULL FROM SWITCHED RAIL.

TBT_X_CIO_PLUG_EVENT_L TBT_T_CIO_PLUG_EVENT_L

TBT_POC_RESET

16 19

59 16

61 16

16 19

43 16

35 16

18 16

16 19

16 28

16 94

MLB ID STRAPS.

PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V.

16

104 80 16

94 28 16

MLB_BOARD_ID0 MLB_BOARD_ID1 MLB_BOARD_ID2 MLB_BOARD_ID3 MLB_BOARD_ID4

OMIT_TABLE

1

R1694

1K

5% 1/20W MF 201

2

PART# DESCRIPTIONQTY

OMIT_TABLE

1

R1693

1K

5% 1/20W MF 201

2

RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:32 R1691,R1690117S0006

RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:4R1692117S0006 1

RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:73 R1692,R1691,R1690117S0006

OMIT_TABLE

1

R1692

1K

5% 1/20W MF 201

2

OMIT_TABLE

1

R1691

1K

5% 1/20W MF 201

2

BOM OPTIONREFERENCE DESIGNATOR(S)

BOARD_ID:00 RES,MF,1/20W/1K OHM,5,0201,SMD117S0006

BOARD_ID:1R16901117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:2RES,MF,1/20W/1K OHM,5,0201,SMD R1691117S0006 1

BOARD_ID:52 R1692,R1690117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

R1692,R1691 BOARD_ID:62117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:8117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD1 R1693

BOARD_ID:9R1693,R16902117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:10R1693,R16912117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:11R1693,R1691,R16903117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:16R1694117S0006 1 RES,MF,1/20W/1K OHM,5,0201,SMD

OMIT_TABLE

1

R1690

1K

5% 1/20W MF 201

2

TABLE_5_HEAD

TABLE_5_ITEM

CODE

<11111>

<11110>

<11101>

<11100>

<11011>

<11010>

<11001>

<11000>

<10111>

<10110>

<10101>

<10100>

<01111>

SYNC_MASTER=J130_MLB SYNC_DATE=12/08/2015

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

DESIGN: X502/MLB LAST CHANGE: Wed Oct 28 12:50:22 2015

PCH SPI/UART/GPIO

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

16 OF 145

SHEET

16 OF 119

B

A

D

8 7 5 4 2 1

36

D

C

77 48 14

50 48

17 6

345678

2 1

Primary / Merged (CPU/PCH) Micro2-XDP

PP1V0_SUS

101

NOTE: This is not the standard XDP pinout.

PLACE_NEAR=U0500.D67:2.54MM

XDP:YES

1K

5%

1/20W

MF

201

1

NO_XNET_CONNECTION

2

NC NC

XDP_PIN_1

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

HOOK0 HOOK1

VCC_OBS_AB

HOOK2 HOOK3

SDA

SCL TCK1 TCK0

IN

OUT

PM_RSMRST_L

PM_PWRBTN_L

XDP_CPU_TCK

XDP:YES

PLACE_NEAR=U0500.AY17:18MM

R1800

1K

1 2

XDP:YES

1 2

R1802

PLACE_NEAR=U0500.BA15:2.54MM

10

5% 1/20W

MF 2015% 1/20W

MF 201

15

17 6

PULL CFG<3> LOW

R1801

WHEN XDP PRESENT

XDP_PRESENT_CPU

BI

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

XDP_CPU_PREQ_L XDP_CPU_PRDY_L

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

XDP_PM_RSMRST_L XDP_CPU_PWRBTN_L

XDP_PCH_TCK

OUT

XDP:YES

0

6

PCH_JTAGX

OUT

R1835

1 2

5% MF1/20W

PLACE_NEAR=J1800.58:28MM

0201

XDP:YES

10% 10V

0201

1

2

C1804

0.1UF

X5R-CERM

PLACE_NEAR=J1800.42:28MM

XDP:YES

C1800

0.1UF

10% 10V

X5R-CERM

0201

PLACE_NEAR=J1800.44:28MM

1

2

XDP_CONN:YES

J1800

DF40RC-60DP-0.4V

M-ST-SM1

62

20

61

12 34 56 78 910 1112 1314 1516 1718 19 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344 4546 4748 4950 5152 5354 5556 5758 5960

6364

518S0847

PLACE_NEAR=J1800.43:28MM

Use with 921-0133 Adapter Flex to support chipset debug.

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7

TDO TRSTn TDI TMS XDP_PRESENT#

XDP:YES

1

C1801

0.1UF

10% 10V

2

X5R-CERM 0201

PLACE_NEAR=J1800.47:28MM

NC NC

1

2

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<10> CPU_CFG<11>

CPU_CFG<19> CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<14> CPU_CFG<15>

ITP_PMODE XDP_DBRESET_L

XDP:YES

C1806

0.1UF

10% 10V X5R-CERM 0201

IN

6

1

R1830

1K

5% 1/20W MF 201

2

ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.

R1821

PLACE_NEAR=J1800.51:2.54MM

R1822

PLACE_NEAR=J1800.53:2.54MM

R1823

PLACE_NEAR=J1800.55:2.54MM

R1824

PLACE_NEAR=J1800.57:2.54MM

XDP_PCH_TDO

17 6

XDP_PCH_TDI

17 6

XDP_PCH_TMS

17 6

XDP_CPU_TDO

17 6

XDP_CPU_TCK

17 6

XDP_PCH_TCK

17 6

PLACE_NEAR=U0500.E8:2.54MM

6

IN

0

1 2

XDP:YES

1 2

5% 1/20W

XDP:YES

0

1 2

XDP:YES

1 2

1/20W5% MF00201

R1890

R1891

R1892

R1810

R1813

R1897

XDP:YES

R1806

0

1 2

5%

1/20W

MF

0201

XDP_CPU_TDO

MF

0201

XDP_CPU_TRST_L

MF5% 1/20W

0201

XDP_CPU_TDI

MF5% 1/20W

0201

XDP_CPU_TMS

PM_SYSRST_L

XDP:YES

PP1V0_S0SW

6 8 10 101

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

NOSTUFF

51

2 1

IN

OUT

MF 201PLACE_NEAR=U0500.A56:28MM 5% 1/20W

MF 201PLACE_NEAR=U0500.D59:28MM 5% 1/20W

D

MF 201PLACE_NEAR=U0500.C59:28MM 5% 1/20W

MF 201PLACE_NEAR=U0500.A61:28MM 5% 1/20W

MF 201PLACE_NEAR=U0500.B61:28MM 5% 1/20W

MF 201PLACE_NEAR=U0500.C61:28MM 5% 1/20W

BI

48 14

C

17 6

6

B

A

15

13

15

28 5

94 5

XDP_PCH_TDO XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS

OUT

IN

17 6

6

17 6

PCH XDP Signals

PP3V3_SUS

These signals do not connect to the Primary (Merged) XDP connector in this architecture. The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation. They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.

PCH/XDP Signals

Non-XDP Signals

17 77 101

XDP:YES

6

VCC

U1830

IN

BI

5

BI

5

BI

6

BI

OUT

XDP_JTAG_ISP_TCK

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_PCH_OBSDATA_A2

XDP_PCH_OBSDATA_A3

XDP_PCH_OBSDATA_B0

XDP_PCH_OBSDATA_C0

XDP_PCH_OBSDATA_C1

XDP_PCH_OBSDATA_C2

XDP_PCH_OBSDATA_C3

XDP_PCH_OBSDATA_D0

XDP_PCH_OBSDATA_D1

XDP_PCH_OBSDATA_D2

XDP_PCH_OBSDATA_D3

XDP_PCH_OBSFN_C1

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUEMAKE_BASE=TRUE

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1870 TP1871 TP1872 TP1873 TP1874 TP1875 TP1876 TP1877 TP1878 TP1879 TP1880 TP1881

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTD_OC_L

MAKE_BASE=TRUEMAKE_BASE=TRUE

Unused GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

OUT

IN

94

105

PP3V3_SUS

17 77 101

XDP:YES

R1850

100K

5%

1/20W

MF

201

NC NC

1

2

NEED TO CONNECT TO VCCST, *STG POWER LOGIC

74AUP1G07GF

SOT891

2

1

GND

3

(OD)

NCNC

4

YA

5

BOM_COST_GROUP=DEBUG

XDP:YES

1

C1830

0.1UF

10% 10V

2

X5R-CERM 0201

SPI_IO2_STRAP_L

NOSTUFF

1

R1832

0

5% 1/20W MF 0201

2

XDP_PRESENT_L

XDP:YES

R1831

1.5K

1 2

5%

1/20W

MF

201

PLACE_NEAR=U0500.AW2:10MM

NO_XNET_CONNECTION=1

PULL STRAP LOW WHEN XDP IS PLUGGED IN. (UNDOCUMENTED STRAP FUNCTION)

77

OUT

SPI_IO<2>

DESIGN: X502/MLB LAST CHANGE: Thu Oct 22 19:53:09 2015

PAGE TITLE

CPU/PCH Merged XDP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

OUT

(STRAP TO PCH)

59 13

DRAWING NUMBER SIZE

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

18 OF 145

SHEET

17 OF 119

D

B

A

SYNC_DATE=12/08/2015SYNC_MASTER=J130_MLB

8 7 5 4 2 1

36

345678

2 1

D

CRITICAL

C1907

9.5PF

1 2

+/-0.1PF

50V

CER-C0G

0201

System 32kHz / 12MHz / 24MHz Clock Generator

SYSCLK_CLK24M_X2

R1900

0

1 2

5%

1/20W

MF

0201

100 35 19

101 19

19

48

IN

PP3V3_G3H

100

PP1V8_S4 PP1V0_SUS NC_PPVIOE_CAMCLK PD_PPVIOE_SSDCLK SMC_CLK12M_EN

SYSCLK_CLK24M_X2_R

12

VIO_32K_B

2

VIOE_24M_A

5

VIOE_24M_B

15

VIOE_24M_C

8

OE_12M

19

X2

20

X1

1

VDD

U1900

SLG3AP3444

STQFN

32.768K_A

32.768K_B

GND

11

VRTC

24M_A 24M_B 24M_C

VOUT

12M

BYPASS=U1900.11:18:5MM

1

C1901

1.0UF

20%

6.3V

2

X5R 0201-1

PP2V9_SYSCLK

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=2.9V

17

10 13

3 6 16

7

SYSCLK_CLK32K_PCH SYSCLK_CLK32K_CAMERA_BT_AP_SOC

SYSCLK_CLK24M_PCH NC_SYSCLK_CLK24M_CAMERA SYSCLK_CLK24M_SSD

SYSCLK_CLK12M_SMC

BYPASS=U1900.17:18:5MM

1

C1900

2.2UF

20%

6.3V

2

X5R-CERM 0201

19

81

48

100

IN

PP1V8_S0

PCH ME Disable Strap

SPI_DESCRIPTOR_OVERRIDE_L

1

G

S

2

Q1930

DMP31D0UFB4

DFN1006H4-3

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. ***** Circuit does not support HDA voltage >3.3V.

D

3

SPI_DESCRIPTOR_OVERRIDE

48

IN

1

R1930

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

PCH IPD = 9-50k

OUT

D

19 13

C

2 4

CRITICAL

C1908

9.5PF

1 2

+/-0.1PF

50V

CER-C0G

0201

CRITICAL

Y1900

1 3

2.5X2.0MM-SM

NO STUFF

1

R1901

1M

5%

24MHZ-10PPM-8PF-40OHM

1/20W MF 201

2

SYSCLK_CLK24M_X1

NOTE: 30 PPM or better required for SKL PCH

14

4

9

18

C

B

35

PP3V3_S5

101

1

R1910

100K

5% 1/20W MF 201

2

PCIe Wake Muxing

C1910

0.1UF

10%

6.3V

CERM-X5R

0201

AP_PCIE_WAKE_L

AP_S0IX_WAKE_SEL

CRITICAL

1

U1910

PI5A3157B

6

2

SEL

1

VCC

3 4

A

DFN

1

0

VER 1

B1

GND

B0

2

5

SEL OUTPUT

L PCIE_WAKE_L (B0) H AP_S0IX_WAKE_L (B1)

AP_S0IX_WAKE_L

PCIE_WAKE_L

IN

OUT

OUTIN

16

B

14

A

PAGE TITLE

Chipset Support 1

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=09/09/2015SYNC_MASTER=J79_GREG

051-00515

9.0.0

dvt-fab09-0

19 OF 145

18 OF 119

A

D

345678

2 1

D

C

B

A

Platform Reset Connections NO TEST

104 35 14

IN

PLT_RST_L

PCIE CLKREQS

PP3V3_S0

R2080

R2081

R2082

R2083

47K

1 2

ENABLE DDPB DDPC INTERFACES

PP3V3_S0

2.2K

R2050

12

R2051

12

201 1/20WMF 5%

T208 PCH GPIO PUs/PDs & ALIASES

R2054 R2055 R2056

R2053

100K

Desense Decoupling Caps on HDA Lines

HDA_SYNC_R HDA_SDOUT_R

NOSTUFF

1

C2020

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

Power State Debug LEDs

(For development only)

PP3V3_S5

101

DBGLED

R2090

20K

5%

1/20W

MF

201

DBGLED_S5 DBGLED_S4

DBGLED

A

D2090

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S5_ON

104 77 48 14

104 77 74 48 43 14

104 92 80 77 74 73 48 26 14

104 74 48 14

5 13 14 16 19 94 101

PCH_DDPB_CTRLDATA

PCH_DDPC_CTRLDATA

1/20W201 5%MF

PP1V8_SUS

1 2

13 18 13

1

2

A

K

DBGLED_S4_D

IN

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L

Unbuffered

5 13 14 16 19 94 101

SSD_CLKREQ_L

MF

TBT_X_CLKREQ_L

1/20W 201

1/20W MF5% 201

1/20W MF5%

8 14 100

5% MF

5% 201

1/20W MF

NOSTUFF

1

C2050

100PF

5% 25V

2

C0G 0201

NOSTUFF

1

C2021

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

MF5%

TBT_T_CLKREQ_L

AP_CLKREQ_L

MF1/20W5% 201

DBGLED

R2091

DBGLED

100K

20K

1/20W

12

2015% 1/20W

201

2011/20W

SOC_PCH_DBELL_L

14 37

14 42

2015%

1

5% MF

201

2

D2091

GRN-90MCD-5MA-2.85V

0402

PLACE_SIDE=BOTTOM SILK_PART=STBY_ON

DBGLED

Q2090

6

DMN5L06VK-7

SOT563

VER 3

2

G S

D

1

R2000

1/20W MF 2015%

R2001

5% 1/20W

R2002

R2003

1/20W MF5%

R2004

13

201MF

MF5% 1/20W 201

201

2015% MF1/20W

R2084

5%

1/20W 201MF

R2085

5%

R2086

5% MF1/20W

R2087

TBT_X_PCI_RESET_L

26 28

TBT_T_PCI_RESET_L

92 94

AP_RESET_L

SSD_RESET_L

SMC_LRESET_L

1 2

MF1/20W 201

1 2

201

1 2

2015% MF1/20W

SOC_PANIC_L

SOC_S2R_ACK_L

PCH_SOC_DBELL

SOC_SWD_CLK

PCH_SOC_DFU_STATUS

SOC_TO_STOCKHOLM_EN

HDA_RST_R_L

NOSTUFF

1

C2022

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

DBGLED

R2092

1/20W

DBGLED_S3 DBGLED_S0

DBGLED

A

D2092

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S3_ON

DBGLED_S3_D

DBGLED

Q2090

DMN5L06VK-7

SOT563

VER 3

5

1K

1

20K

5% MF

201

2

G S

GREENCLK VIOEs

15

NO_TEST=1

MAKE_BASE=TRUE

OUT

SSD_CLKREQ_L_R

15

TBT_X_CLKREQ_L_R

15

TBT_T_CLKREQ_L_R

15

AP_CLKREQ_L_R

15

TBT_X_PCI_RESET_L

MAKE_BASE=TRUE

TBT_T_PCI_RESET_L

36 35 16

104 91 16

48

MAKE_BASE=TRUE

SSD_CLKREQ_L_R

MAKE_BASE=TRUE

TBT_X_CLKREQ_L_R

MAKE_BASE=TRUE

TBT_T_CLKREQ_L_R

MAKE_BASE=TRUE

AP_CLKREQ_L_R

OUT

16

104 88 87 86 85 84 82 81

MAKE_BASE=TRUE

18

IN

SYSCLK_CLK32K_PCH

MAKE_BASE=TRUE

NO_TEST=1

CATERR PU

PP1V0_S3

R2059

51

WIFI GPIO PD

R2058

38 13

MAKE_BASE=TRUE

SOC_PCH_DBELL_L

MAKE_BASE=TRUE

PCH_SOC_DBELL

MAKE_BASE=TRUE

SOC_SWD_CLK

37 13

38 37

13

DBGLED_S0I3

DBGLED

A

D2093

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON

DBGLED_S0I3_D

3

D

4

DMN5L06VK-7

100K

DBGLED

R2093

DBGLED

Q2091

SOT563

VER 3

2

G S

6 8 10 14 101

1 2

1

20K

5%

1/20W

MF

201

2

D

SYSCLK_CLK24M_PCH

CPU_CATERR_L

1/20W5%

18

IN

201MF

48 6

MAKE_BASE=TRUE

SYSCLK_CLK32K_CAMERA_BT_AP_SOC

PCH_BT_ROM_BOOT

1/20W5% 201

MF

35 14

35

18

IN

SYSCLK_CLK32K_CAMERA_BT_AP_SOC

IN

SYSCLK_CLK32K_OSC_OUT

BT_I2S_SYNC_1V8

16 35

IN OUT

16 35

BI BI

BT_I2S_R2D_1V8

BT_I2S_D2R_1V8

OUT IN

BT_I2S_CLK_1V8

DBGLED

20K

5%

1/20W

MF

201

1

2

PCH_SSD_SOC_UART_D2R

16

PCH_SSD_SOC_UART_R2D

16

R2095

DBGLED

A

D2095

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S0_ON

DBGLED_S0_D

DBGLED

Q2091

6

1

DMN5L06VK-7

SOT563

VER 3

5

G S

3

D

DEBUGUART_SEL_SOC

13

4

MAKE_BASE=TRUE

NC_PPVIOE_CAMCLK

MAKE_BASE=TRUE

PP1V8_SSD_COLD

NOSTUFF

R2010

0

1 2

5%

1/20W

MF

0201

NC_PPVIOE_CAMCLK

PP1V0_SUS

18 101

PP1V8_S4

18 35 100

PD_PPVIOE_SSDCLK

NOSTUFF

1

C2002

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U1900.15:18:5MM

GREENCLK CLOCK OUT ALIASES

SYSCLK_CLK32K_PCH

NC_PCH_CLK32K_RTCX2

NOSTUFF

R2044

0

1 2

5%

1/20W

MF

0201

100 106

MAKE_BASE=TRUE

BT_I2S_SYNC_1V8

MAKE_BASE=TRUE

BT_I2S_R2D_1V8

MAKE_BASE=TRUE

BT_I2S_CLK_1V8

PP3V3_S0

101

PP1V8_S0

100

MAKE_BASE=TRUE

PCH_SSD_SOC_UART_D2R PCH_SSD_SOC_UART_R2D

MAKE_BASE=TRUE

PCH_CLK:GRNCLK

PP1V8_S0

R2066

100K

PLACE_NEAR=U1900.3:5MM

5%

1/20W

MF

201

NC_PCH_CLK32K_RTCX2

R2024

0

1 2

5%

1/20W

MF

0201

NOSTUFF

PCH_CLK24M_XTALIN

R2042

0

1 2

5%

1/20W

MF

0201

SYSCLK_CLK32K_WIFIBT

R2043

0

1 2

5%

1/20W

MF

0201

SOC_PMU_CLK_32K

x100 I2S Level Translator

1

C2010

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

VL VCC

U2010

NLSX5014MU_G

12

2

3

4

5

EN

IOLV[1]

IOLV[2]

IOLV[3]

IOLV[4]

UQFN

GND

6

BT/SSD DEBUG UART MUX

1

C2060

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

Y+

2

Y-

1

2

10

PI3USB102EZLE

R2067

5% 1/20W

R2068

9

VCC

CRITICAL

U2060

TQFN

GND

3

0201MF

02015% MF1/20W

18

18 19

1

C2001

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U1900.12:18:5MM

PP3V3_S0

C2011

0.1UF

100K

1/20W

M+ M-

D+ D-

OE*SEL

CERM-X5R

10

9

8

7

1

5%

MF

201

2

5 4

7 6

8

11

IOVCC[1]

IOVCC[2]

IOVCC[3]

IOVCC[4]

R2060

1

C2000

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U1900.02:18:5MM

OUT

IN

OUT

1

10%

6.3V 2

0201

BT_I2S_SYNC

BT_I2S_R2D

BT_I2S_D2RBT_I2S_D2R_1V8

BT_I2S_CLK

1

R2061

100K

5% 1/20W MF 201

2

SSD_DBG_UART_D2R SSD_DBG_UART_R2D_R

SOC_DBG_UART_D2R SOC_DBG_UART_R2D

NO STUFF

0

1 2

0

1 2

NO STUFF

15

35

Voltage Props

VOLTAGE=1.0V

12 15

IN IN

12

IN

12

IN

12 8

IN

12

IN

12

IN

12

IN

12

IN

12 8

IN

VOLTAGE=1.0V

PP1V_SUS_PCH_VCCCLK4_F

VOLTAGE=1.0V

PP1V_SUS_PCH_VCCCLK5_F

VOLTAGE=1.0V

PP1V_S5_PCH_DCPDSW

VOLTAGE=1.0V

PP1V_SUS_PCH_VCCAPLL_F

VOLTAGE=1.0V

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

VOLTAGE=1.8V

PP1V8_SUS_PCH_VCC1P8

VOLTAGE=1.8V

PP1V8_S0_PCH_VCCHDA_F

VOLTAGE=3.0V

PPDCPRTC_PCH

Unused GPIOs with PUs/PDs

16

13

16

IN

OUT

IN

PD_AP_DEV_WAKE

PU_AUD_SPI_CS_L PD_AUD_SPI_CLK PD_AUD_SPI_MISO PU_AUD_SPI_MOSI PD_LCD_PSR_EN PD_SSD_UART_CTS_L PU_SOC_UART_RTS_L PD_SOC_UART_CTS_L

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

SIGNAL ALIASES

PD_PPVIOE_SSDCLK

18 19

13

ALS_SOC_UART_D2R

13

ALS_SOC_UART_R2D

13

41 37

NC_PCH_CLKREQ4_L

15

NC_PCIE_CLK100M5N

15

NC_PCIE_CLK100M5P

15

NC_PCH_CLKREQ5_L

101

35 16

BIBI

R2062

100K

1/20W

201

5%

MF

1

2

1

R2063

100K

5% 1/20W MF 201

2

88

42

13

104 88 84

15

NC_SPKR_ID1

16

NC_PCH_CLK24M_XTALOUT

15

NC_PCH_GPP_E15

5

NC_PCH_BSSB_CLK

13

NC_PCH_BSSB_DATA

13

NC_ITPXDP_CLK100M_N

15

NC_ITPXDP_CLK100M_P

15

NC_UPC_I2C_INT_L

14

NC_SPKR_ID0

15

NC_USB3_04_D2RN

15

NC_USB3_04_D2RP

15

NC_USB3_04_R2DN

15

NC_USB3_04_R2DP

15

NC_I2C_UPC_SDA

16

NC_I2C_UPC_SCL

16

NC_MLB_DEV_L

16

NC_SYSCLK_CLK24M_CAMERA

18

NC_PCH_STRP_TLSCONF

13

NC_PCH_STRP_ESPI

13

NC_PCH_STRP_BSSB_SEL_GPIO

NC_PCH_CLKOUT_LPC1

13

NC_VCCPRIM_CORE_VID0

8

NC_VCCPRIM_CORE_VID1

8

NC_CAMERA_RESET_L

13

SYNC_MASTER=J79_GREG SYNC_DATE=07/05/2016

PAGE TITLE

CAMERA_PWR_EN

NC SIGNAL ALIASES

Chipset Support 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IN

15

IN

15

IN

PD_AP_DEV_WAKE

PU_AUD_SPI_CS_L PD_AUD_SPI_CLK PD_AUD_SPI_MISO PU_AUD_SPI_MOSI

PD_LCD_PSR_EN PD_SSD_UART_CTS_L PU_SOC_UART_RTS_L PD_SOC_UART_CTS_L

MAKE_BASE=TRUE

PD_PPVIOE_SSDCLK

MAKE_BASE=TRUE

ALS_SOC_UART_D2R

MAKE_BASE=TRUE

ALS_SOC_UART_R2D

MAKE_BASE=TRUE

NC_PCH_CLKREQ4_L

MAKE_BASE=TRUE

NC_PCIE_CLK100M5N

MAKE_BASE=TRUE

NC_PCIE_CLK100M5P

MAKE_BASE=TRUE

NC_PCH_CLKREQ5_L

MAKE_BASE=TRUE

NC_SPKR_ID1

MAKE_BASE=TRUE

NC_PCH_CLK24M_XTALOUT

MAKE_BASE=TRUE

NC_PCH_GPP_E15

MAKE_BASE=TRUE

NC_PCH_BSSB_CLK

MAKE_BASE=TRUE

NC_PCH_BSSB_DATA

MAKE_BASE=TRUE

NC_ITPXDP_CLK100M_N

MAKE_BASE=TRUE

NC_ITPXDP_CLK100M_P

MAKE_BASE=TRUE

NC_USB3_04_D2RN

MAKE_BASE=TRUE

NC_USB3_04_D2RP

MAKE_BASE=TRUE

NC_USB3_04_R2DN

MAKE_BASE=TRUE

NC_USB3_04_R2DP

MAKE_BASE=TRUE

NC_SYSCLK_CLK24M_CAMERA

MAKE_BASE=TRUE

NC_PCH_STRP_TLSCONF

MAKE_BASE=TRUE

NC_PCH_STRP_ESPI

MAKE_BASE=TRUE

NC_PCH_STRP_BSSB_SEL_GPIO

MAKE_BASE=TRUE

NC_PCH_CLKOUT_LPC1

MAKE_BASE=TRUE

NC_VCCPRIM_CORE_VID0

MAKE_BASE=TRUE

NC_VCCPRIM_CORE_VID1

MAKE_BASE=TRUE

NC_CAMERA_RESET_L

NC_USB2_10N

NO_TEST=1

NC_USB2_10P

NO_TEST=1

NC_USB2_05N

NO_TEST=1

NC_USB2_05PPP1V_SUS_PCH_VCCCLK2_F

NO_TEST=1

CAMERA_PWR_EN

NO_TEST=1

NC_UPC_I2C_INT_L

NO_TEST=1

NC_SPKR_ID0

NO_TEST=1

NC_I2C_UPC_SDA

NO_TEST=1

NC_I2C_UPC_SCL

NO_TEST=1

NC_MLB_DEV_L

NO_TEST=1

DRAWING NUMBER SIZE

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

20 OF 145

SHEET

19 OF 119

13

42

9.0.0

D

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

7

IN

7

IN

7

IN

NOTE: CPU has single output for VREFCA. VREFCA. Connected to 4 DRAMs.

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

CPU-Based Margining

VRef Dividers

R2223

10

1 2

1%

1/20W

MF

201

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_A_RC

R2243

10

1 2

1%

1/20W

MF

201

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_B_RC

R2263

5.1

1 2

1%

1/20W

MF

0201

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFCA_RC

PLACE_NEAR=R2221.2:1mm

8.2K

1%

1/20W

MF

201

1

2

R2222

R2220

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=R2241.2:1mm

8.2K

1%

1/20W

MF

201

1

2

R2242

R2240

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=R2261.2:1mm

8.2K

1%

1/20W

MF

201

1

2

R2262

R2260

24.9

1 2

1%

1/20W

MF

201

PP1V2_S3

1

R2221

8.2K

1% 1/20W MF 201

2

PP0V6_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

R2241

8.2K

1% 1/20W MF 201

2

PP0V6_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

R2261

8.2K

1% 1/20W MF 201

2

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

D

100

C

100

B

A

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

LPDDR3 VREF Margining

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

22 OF 145

20 OF 119

A

D

LPDDR3 CHANNEL A (0-31)

345678

2 1

D

C

B

R2300

243

1%

1/20W

MF

201

U2300

LPDDR3-1600-32GB

EDFB232A1MA

25 7

25 22 7

IN

MEM_A_CAA<0> MEM_A_CAA<1> MEM_A_CAA<2> MEM_A_CAA<3> MEM_A_CAA<4> MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<8> MEM_A_CAA<9>

MEM_A_CKE<0> MEM_A_CKE<1>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<0> MEM_A_ZQ<1>

243

1%

1/20W

MF

201

1

2

C2340

0.047UF

10%

6.3V X5R 201

1

2

100 22

1

C2341

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

PP1V2_S3

21 22 23 24 100

NC NC NC NC NC NC NC NC NC NC NC NC

1

C2300

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2301

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8 G8 P8 D8

J8

B3 B4

H4

J11

A1

A2 A12 A13

B1 B13

T1 T13

U1

U2 U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

1

2

OMIT_TABLE

C2301

0.1UF

10% 16V X5R-CERM 0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2302

1UF

20% 10V

2

X5R 0201

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC NC NC

1

C2303

1UF

20% 10V

2

X5R 0201

MEM_A_DQ<17> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<16> MEM_A_DQ<6> MEM_A_DQ<1> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<7> MEM_A_DQ<0> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<26> MEM_A_DQ<30> MEM_A_DQ<24> MEM_A_DQ<29> MEM_A_DQ<27> MEM_A_DQ<31> MEM_A_DQ<28> MEM_A_DQ<25> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<10> MEM_A_DQ<15> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<14> MEM_A_DQ<11>

MEM_A_DQS_N<2> MEM_A_DQS_N<0> MEM_A_DQS_N<3> MEM_A_DQS_N<1>

MEM_A_DQS_P<2> MEM_A_DQS_P<0> MEM_A_DQS_P<3> MEM_A_DQS_P<1>

1

C2304

1UF

20% 10V

2

X5R 0201

1

C2305

1UF

20% 10V

2

X5R 0201

BI

103

1

C2306

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2307

10UF

20% 10V

2

X5R-CERM 0402-7

PP1V8_S3_MEM

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

CRITICAL

1

C2334

12PF

5% 25V

2

NP0-C0G 0201

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5 J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3 L2 M2

A11 C12

E8 E12 G12

H8

H9 H11

J9 J10

K8 K11 L12

N8 N12 R12 U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2300

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V8_S3_MEM

21 22 23 24 100

1

C2320

1UF

20% 10V

2

X5R 0201

1

C2310

1UF

20% 10V

2

X5R 0201

1

C2330

1UF

20% 10V

2

X5R 0201

1

C2321

1UF

20% 10V

2

X5R 0201

1

C2311

1UF

20% 10V

2

X5R 0201

1

C2331

1UF

20% 10V

2

X5R 0201

1

C2322

1UF

20% 10V

2

X5R 0201

1

C2312

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2332

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2323

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2333

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2336

12PF

5% 25V

2

NP0-C0G 0201

1

C2324

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2335

12PF

5% 25V

2

NP0-C0G 0201

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

CRITICAL

1

C2338

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2339

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2337

12PF

5% 25V

2

NP0-C0G 0201

BOM_COST_GROUP=DRAM

PAGE TITLE

LPDDR3 DRAM Channel A (00-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=05/12/2015SYNC_MASTER=J52_MLB

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

23 OF 145

SHEET

21 OF 119

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL A (32-63)

345678

2 1

D

C

B

R2400

243

1%

1/20W

MF

201

U2400

LPDDR3-1600-32GB

EDFB232A1MA

25 7

25 21 7

IN

MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<4> MEM_A_CAB<5> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9>

MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<2> MEM_A_ZQ<3>

243

1%

1/20W

MF

201

1

2

C2440

0.047UF

10%

6.3V X5R 201

1

2

100 21

1

C2441

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

PP1V2_S3

21 22 23 24 100

NC NC NC NC NC NC NC NC NC NC NC NC

1

C2400

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2401

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8 G8 P8 D8

J8

B3 B4

H4

J11

A1

A2 A12 A13

B1 B13

T1 T13

U1

U2 U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

1

2

OMIT_TABLE

C2401

0.1UF

10% 16V X5R-CERM 0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2402

1UF

20% 10V

2

X5R 0201

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC NC NC

1

C2403

1UF

20% 10V

2

X5R 0201

MEM_A_DQ<41> MEM_A_DQ<46> MEM_A_DQ<42> MEM_A_DQ<40> MEM_A_DQ<43> MEM_A_DQ<47> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<55> MEM_A_DQ<49> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<50> MEM_A_DQ<54> MEM_A_DQ<48> MEM_A_DQ<51> MEM_A_DQ<37> MEM_A_DQ<32> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<36> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<59> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<63> MEM_A_DQ<58>

MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<4> MEM_A_DQS_N<7>

MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<4> MEM_A_DQS_P<7>

1

C2404

1UF

20% 10V

2

X5R 0201

1

C2405

1UF

20% 10V

2

X5R 0201

BI

103

1

C2406

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2407

10UF

20% 10V

2

X5R-CERM 0402-7

PP1V8_S3_MEM

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5 J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3 L2 M2

A11 C12

E8 E12 G12

H8

H9 H11

J9 J10

K8 K11 L12

N8 N12 R12 U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2400

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V8_S3_MEM

21 22 23 24 100

1

C2420

1UF

20% 10V

2

X5R 0201

1

C2410

1UF

20% 10V

2

X5R 0201

1

C2430

1UF

20% 10V

2

X5R 0201

1

C2421

1UF

20% 10V

2

X5R 0201

1

C2411

1UF

20% 10V

2

X5R 0201

1

C2431

1UF

20% 10V

2

X5R 0201

1

C2422

1UF

20% 10V

2

X5R 0201

1

C2412

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2432

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2423

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2433

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2435

12PF

5% 25V

2

NP0-C0G 0201

1

C2424

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2434

12PF

5% 25V

2

NP0-C0G 0201

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

CRITICAL

1

C2437

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2436

12PF

5% 25V

2

NP0-C0G 0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

24 OF 145

SHEET

22 OF 119

D

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (0-31)

345678

2 1

D

C

B

R2500

243

1%

1/20W

MF

201

U2500

LPDDR3-1600-32GB

EDFB232A1MA

25 7

25 24 7

IN

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

MEM_B_CKE<0> MEM_B_CKE<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<0> MEM_B_ZQ<1>

243

1%

1/20W

MF

201

1

100 24

2

C2540

0.047UF

10%

6.3V X5R 201

1

2

1

C2541

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_MEM_VREFCA_A

24 100

PP0V6_S3_MEM_VREFDQ_B

PP1V2_S3

21 22 23 24 100

NC NC NC NC NC NC NC NC NC NC NC NC

1

C2500

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2501

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8 G8 P8 D8

J8

B3 B4

H4

J11

A1

A2 A12 A13

B1 B13

T1 T13

U1

U2 U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

1

2

OMIT_TABLE

C2501

0.1UF

10% 16V X5R-CERM 0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2502

1UF

20% 10V

2

X5R 0201

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC NC NC

1

C2503

1UF

20% 10V

2

X5R 0201

MEM_B_DQ<9> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<15> MEM_B_DQ<8> MEM_B_DQ<19> MEM_B_DQ<21> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<18> MEM_B_DQ<20> MEM_B_DQ<0> MEM_B_DQ<5> MEM_B_DQ<3> MEM_B_DQ<6> MEM_B_DQ<1> MEM_B_DQ<4> MEM_B_DQ<7> MEM_B_DQ<2> MEM_B_DQ<26> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<27> MEM_B_DQ<30> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<31>

MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<0> MEM_B_DQS_N<3>

MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<0> MEM_B_DQS_P<3>

1

C2504

1UF

20% 10V

2

X5R 0201

1

C2505

1UF

20% 10V

2

X5R 0201

BI

103

1

C2506

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2507

10UF

20% 10V

2

X5R-CERM 0402-7

PP1V8_S3_MEM

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5 J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3 L2 M2

A11 C12

E8 E12 G12

H8

H9 H11

J9 J10

K8 K11 L12

N8 N12 R12 U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2500

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V8_S3_MEM

21 22 23 24 100

1

C2520

1UF

20% 10V

2

X5R 0201

1

C2510

1UF

20% 10V

2

X5R 0201

1

C2530

1UF

20% 10V

2

X5R 0201

1

C2521

1UF

20% 10V

2

X5R 0201

1

C2511

1UF

20% 10V

2

X5R 0201

1

C2531

1UF

20% 10V

2

X5R 0201

1

C2522

1UF

20% 10V

2

X5R 0201

1

C2512

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2532

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2523

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2533

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2535

12PF

5% 25V

2

NP0-C0G 0201

1

C2524

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2534

12PF

5% 25V

2

NP0-C0G 0201

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

CRITICAL

1

C2537

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2536

12PF

5% 25V

2

NP0-C0G 0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

LPDDR3 DRAM Channel B (00-31)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

25 OF 145

SHEET

23 OF 119

D

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (32-63)

345678

2 1

D

C

B

R2600

243

1%

1/20W

MF

201

U2600

LPDDR3-1600-32GB

EDFB232A1MA

25 7

25 23 7

IN

MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9>

MEM_B_CKE<2> MEM_B_CKE<3>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<2> MEM_B_ZQ<3>

243

1%

1/20W

MF

201

1

2

C2640

0.047UF

10%

6.3V X5R 201

1

2

1

C2641

0.047UF

10%

6.3V

2

X5R 201

23 100

100 23

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_B

PP1V2_S3

21 22 23 24 100

NC NC NC NC NC NC NC NC NC NC NC NC

1

C2600

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2601

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8 G8 P8 D8

J8

B3 B4

H4

J11

A1

A2 A12 A13

B1 B13

T1 T13

U1

U2 U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

1

2

OMIT_TABLE

C2601

0.1UF

10% 16V X5R-CERM 0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2602

1UF

20% 10V

2

X5R 0201

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC NC NC

1

C2603

1UF

20% 10V

2

X5R 0201

MEM_B_DQ<41> MEM_B_DQ<47> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<46> MEM_B_DQ<40> MEM_B_DQ<55> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<54> MEM_B_DQ<37> MEM_B_DQ<33> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<36> MEM_B_DQ<32> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<62> MEM_B_DQ<63> MEM_B_DQ<56> MEM_B_DQ<59> MEM_B_DQ<61> MEM_B_DQ<60>

MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<4> MEM_B_DQS_N<7>

MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<4> MEM_B_DQS_P<7>

1

C2604

1UF

20% 10V

2

X5R 0201

1

C2605

1UF

20% 10V

2

X5R 0201

BI

103

1

C2606

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2607

10UF

20% 10V

2

X5R-CERM 0402-7

PP1V8_S3_MEM

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5 J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3 L2 M2

A11 C12

E8 E12 G12

H8

H9 H11

J9 J10

K8 K11 L12

N8 N12 R12 U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2600

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V8_S3_MEM

21 22 23 24 100

1

C2620

1UF

20% 10V

2

X5R 0201

1

C2610

1UF

20% 10V

2

X5R 0201

1

C2630

1UF

20% 10V

2

X5R 0201

1

C2621

1UF

20% 10V

2

X5R 0201

1

C2611

1UF

20% 10V

2

X5R 0201

1

C2631

1UF

20% 10V

2

X5R 0201

1

C2622

1UF

20% 10V

2

X5R 0201

1

C2612

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2632

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2623

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2633

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2635

12PF

5% 25V

2

NP0-C0G 0201

1

C2624

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2634

12PF

5% 25V

2

NP0-C0G 0201

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

CRITICAL

1

C2637

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2636

12PF

5% 25V

2

NP0-C0G 0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

26 OF 145

SHEET

24 OF 119

D

A

8 7 5 4 2 1

36

345678

2 1

D

C

21 7

22 7

22 21 7

Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

PP0V6_S0_DDRVTT

100

IN

MEM_A_CAA<9> MEM_A_CAA<8> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<5> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CKE<1> MEM_A_CKE<0> MEM_A_CAA<4> MEM_A_CAA<3> MEM_A_CAA<2> MEM_A_CAA<1> MEM_A_CAA<0> MEM_A_CAB<9> MEM_A_CAB<8> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<5> MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CKE<2> MEM_A_CKE<3> MEM_A_CAB<4> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<1> MEM_A_CAB<0> MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_ODT<0>

R2700 R2701 R2702 R2703 R2704 R2705 R2706 R2707 R2708 R2709 R2710 R2711 R2712 R2713 R2714 R2715 R2716 R2717 R2718 R2719 R2720 R2721 R2722 R2723 R2724 R2725 R2726 R2727 R2728 R2729 R2730

68 68 68 68 68 39 39 82 82 68 68 68 68 68 68 68 68 68 68 39 39 82 82 68 68 68 68 68 82 82 82

1 2

1/20W 201 MF1%

1/20W MF201

1%

1/20W 201 MF1% 1/20W1%

MF2011/20W1%

201 MF1/20W1%

MF2011/20W1% MF2011/20W1% MF2011/20W1%

201 MF1/20W1%

MF2011/20W1%

201 MF1/20W1%

MF2011/20W1% MF2011/20W1%

201 MF1/20W1%

MF2011/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1%

MF2011/20W1% 201 MF1% 1/20W 201 MF1/20W1%

MF2011/20W1%

MF2011/20W1% 201 MF1/20W1%

MF2011/20W1% 201 MF1/20W1% 2011/20W1%

MF 201 MF1/20W1%

201 MF

MF1/20W1%

201 201 MF1% 1/20W

1

C2700

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2701

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2703

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2705

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2707

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2709

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2730

12PF

5% 25V

2

NP0-C0G 0201

1

C2702

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2704

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2706

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2708

0.47UF

20% 4V

2

CERM-X5R-1 201

23 7

24 7

24 23 7

IN

MEM_B_CAA<9> MEM_B_CAA<8> MEM_B_CAA<7> MEM_B_CAA<6> MEM_B_CAA<5> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CKE<1> MEM_B_CKE<0> MEM_B_CAA<4> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<1> MEM_B_CAA<0> MEM_B_CAB<9> MEM_B_CAB<8> MEM_B_CAB<7> MEM_B_CAB<6> MEM_B_CAB<5> MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<2> MEM_B_CKE<3> MEM_B_CAB<4> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<1> MEM_B_CAB<0> MEM_B_CS_L<0> MEM_B_CS_L<1> MEM_B_ODT<0>

R2740 R2741 R2742 R2743 R2744 R2745 R2746 R2747 R2748 R2749 R2750 R2751 R2752 R2753 R2754 R2755 R2756 R2757 R2758 R2759 R2760 R2761 R2762 R2763 R2764 R2765 R2766 R2767 R2768 R2769 R2770

68 68 68 68 68 39 39 82 82 68 68 68 68 68 68 68 68 68 68 39 39 82 82 68 68 68 68 68 82 82 82

PP0V6_S0_DDRVTT

100

1 2

1% 201 MF1/20W

D

MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1%

MF2011/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1%

MF1/20W 2011%

MF2011/20W1%

MF2011/20W1% 201 MF1/20W1%

MF2011/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1%

MF2011/20W1%

1

C2710

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2711

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2713

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2715

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2717

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2719

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2731

12PF

5% 25V

2

NP0-C0G 0201

1

C2712

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2714

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2716

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2718

0.47UF

20% 4V

2

CERM-X5R-1 201

C

B

CRITICAL

1

C2720

20UF

20%

6.3V

2

CERM-X5R 0402

1

C2722

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C2740

20UF

20%

6.3V

2

CERM-X5R 0402

1

C2742

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

B

A

SYNC_MASTER=J52_MLB

PAGE TITLE

LPDDR3 DRAM Termination

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=05/12/2015

051-00515

D

9.0.0

dvt-fab09-0

27 OF 145

25 OF 119

A

345678

2 1

D

C

B

A

1

R2890

3.3K

5% 1/20W MF 201

2

TBT_X_SPI_CLK

28

TBT_X_SPI_CS_L

28

TBT_X_ROM_WP_L

26

TBT_X_ROM_HOLD_L

34

BI

34

BI

34

BI

34

BI

100K

1 2

100K

1 2

DP_X_SNK0_ML_C_P<0>

IN

DP_X_SNK0_ML_C_N<0>

IN

DP_X_SNK0_ML_C_P<1>

IN

DP_X_SNK0_ML_C_N<1>

IN

DP_X_SNK0_ML_C_P<2>

IN

DP_X_SNK0_ML_C_N<2>

IN

DP_X_SNK0_ML_C_P<3>

IN

DP_X_SNK0_ML_C_N<3>

IN

DP_X_SNK0_AUXCH_C_P

DP_X_SNK0_AUXCH_C_N

DP_X_SNK1_ML_C_P<0>

IN

DP_X_SNK1_ML_C_N<0>

IN

DP_X_SNK1_ML_C_P<1>

IN

DP_X_SNK1_ML_C_N<1>

IN

DP_X_SNK1_ML_C_P<2>

IN

DP_X_SNK1_ML_C_N<2>

IN

DP_X_SNK1_ML_C_P<3>

IN

DP_X_SNK1_ML_C_N<3>

IN

DP_X_SNK1_AUXCH_C_P

DP_X_SNK1_AUXCH_C_N

5% MF

1M

5%

1M

1/20W5% 201MF

1M

5% MF1/20W 201

R2891

3.3K

1/20W

R2862

2015% 1/20W MF

R2872

1/20W 201

R2860

MF 2011/20W

R2861

MF5%

2011/20W

R2870

R2871

1

5%

MF

201

2

GND_VOID=TRUE

R2893

3.3K

5% 1/20W MF 201

2

6

1

3

7

DP_XA_HPD

DP_XB_HPD

TBT_XA_LSTX

TBT_XA_LSRX

TBT_XB_LSTX

TBT_XB_LSRX

PP3V3_UPC_XB_LDO

R2892

3.3K

5%

1/20W

8

VCC

MF

201

U2890

8MBIT-3.0V

W25Q80DVUXIE

CLK

CS*

WP*(IO2)

HOLD*(IO3)

GND EPAD

4

USON

DI(IO0) DO(IO1)

OMIT_TABLE

CRITICAL

9

5 2

SNK0 AC Coupling

C2820

0.1UF

C2821

0.1UF

C2822

0.1UF

C2823

0.1UF

C2824

0.1UF

C2825

0.1UF

C2826

0.1UF

C2827

0.1UF

C2828

0.1UF

C2829

0.1UF

1 2

X5R-CERM

1 2

X5R-CERM

1 2

10% 16V 0201 X5R-CERM

1 2

X5R-CERM

1 2

10% 16V 0201 X5R-CERM

1 2

X5R-CERM

1 2

10% 16V X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

16V 020110%

16V10%

SNK1 AC Coupling

C2830

0.1UF

C2831

0.1UF

C2832

0.1UF

C2833

0.1UF

C2834

0.1UF

C2835

0.1UF

C2836

0.1UF

C2837

0.1UF

C2838

0.1UF

C2839

0.1UF

1 2

X5R-CERM

1 2

X5R-CERM

1 2

10% X5R-CERM

1 2

X5R-CERM

1 2

10% X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

1 2

16V10%

X5R-CERM

1 2

X5R-CERM

1 2

16V10% 0201

X5R-CERM

29 28 26

30 26

29 26

30 26

28

1

2

C2890

1UF

10%

6.3V

2

CERM 402

TBT_X_SPI_MOSI TBT_X_SPI_MISO

DP_X_SNK0_ML_P<0>

020110% 16V

DP_X_SNK0_ML_N<0>

020116V10%

DP_X_SNK0_ML_P<1>

DP_X_SNK0_ML_N<1>

020110% 16V

DP_X_SNK0_ML_P<2>

DP_X_SNK0_ML_N<2>

020116V10%

DP_X_SNK0_ML_P<3>

0201

DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P

0201

DP_X_SNK0_AUXCH_N

020116V10%

DP_X_SNK1_ML_P<0>

020116V10%

DP_X_SNK1_ML_N<0>

020116V10%

DP_X_SNK1_ML_P<1>

020116V

DP_X_SNK1_ML_N<1>

020116V10%

DP_X_SNK1_ML_P<2>

020116V

DP_X_SNK1_ML_N<2>

020116V10%

DP_X_SNK1_ML_P<3>

020116V10%

DP_X_SNK1_ML_N<3>

0201

DP_X_SNK1_AUXCH_P

020116V10%

DP_X_SNK1_AUXCH_N

26

28

29

PLACE_NEAR=U2800.H6:2MM PLACE_NEAR=U2800.J6:2MM

DP_XA_AUXCH_P

BI

DP_XA_AUXCH_N

BI

10K PU ON CLOCKS PAGE

34 28

OUT

R2830

100K

1/20W

34 28

OUT

R2831

100K

5%

1/20W

MF

201

1 2

TF

1

2

1/20W

R2855

GND_VOID=TRUE

12

0201

PLACE_NEAR=U2800.H19:2MM

16V

10%

X5R-CERM

16V

10%

X5R-CERM

12

GND_VOID=TRUE

R2854

499

1%

1/20W

MF

1

5% MF

201

2

C2810

0.1UF

C2811

0.1UF

1

2

201

28

IN

28

IN

28

IN

28

IN

28

IN

28

IN

28

IN

28

IN

PCIE_CLK100M_TBT_X_P

IN

PCIE_CLK100M_TBT_X_N

IN

TBT_X_CLKREQ_L

OUT

28

IN

28

BI

28

IN

28

BI

1/20W

14K

105 15

19

12 201

1% MF

R2850

94 92 28

4.75K

0.5% 0201

TBT_XA_USB2_RBIAS

31

28

29 26

29 28 26

56

OUT

IN

OUT

IN

DP_XA_AUXCH_C_P DP_XA_AUXCH_C_N

BI

OUT

IN

TBTTHMSNS_D1_P

PCIE_TBT_X_R2D_P<0> PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1> PCIE_TBT_X_R2D_N<1>

PCIE_TBT_X_R2D_P<2> PCIE_TBT_X_R2D_N<2>

PCIE_TBT_X_R2D_P<3> PCIE_TBT_X_R2D_N<3>

DP_X_SNK0_ML_P<0>

26

DP_X_SNK0_ML_N<0>

26

DP_X_SNK0_ML_P<1>

26

DP_X_SNK0_ML_N<1>

26

DP_X_SNK0_ML_P<2>

26

DP_X_SNK0_ML_N<2>

26

DP_X_SNK0_ML_P<3>

26

DP_X_SNK0_ML_N<3>

26

DP_X_SNK0_AUXCH_P

26

DP_X_SNK0_AUXCH_N

26

DP_X_SNK0_HPD

DP_X_SNK0_DDC_CLK DP_X_SNK0_DDC_DATA

DP_X_SNK1_ML_P<0>

26

DP_X_SNK1_ML_N<0>

26

DP_X_SNK1_ML_P<1>

26

DP_X_SNK1_ML_N<1>

26

DP_X_SNK1_ML_P<2>

26

DP_X_SNK1_ML_N<2>

26

DP_X_SNK1_ML_P<3>

26

DP_X_SNK1_ML_N<3>

26

DP_X_SNK1_AUXCH_P

26

DP_X_SNK1_AUXCH_N

26

DP_X_SNK1_HPD

DP_X_SNK1_DDC_CLK DP_X_SNK1_DDC_DATA

DP_X_SNK_RBIAS

PLACE_NEAR=U2800.Y18:2MM

94 92

28

94 92

IN

OUT

JTAG_TBT_TDI JTAG_TBT_X_TMS JTAG_TBT_TCK JTAG_ISP_TDO

TBT_X_RBIAS TBT_X_RSENSE

USBC_XA_D2R_P<2> USBC_XA_D2R_N<2>

USBC_XA_R2D_C_P<2> USBC_XA_R2D_C_N<2>

USBC_XA_R2D_C_P<1> USBC_XA_R2D_C_N<1>

USBC_XA_D2R_P<1> USBC_XA_D2R_N<1>

USB_UPC_XA_P USB_UPC_XA_N

TBT_XA_LSTX TBT_XA_LSRX DP_XA_HPD

USE NEAREST GND BALL

(AC22) FOR THERM_D_N

NC

Y23 Y22

T23 T22

PCIE_RX0_P PCIE_RX0_N

PCIE_RX1_P PCIE_RX1_N

U2800

TBT-AR-4C-CNTRL

SYM 1 OF 2

FCBGA

OMIT_TABLE

PCIE_TX0_P PCIE_TX0_N

PCIE_TX1_P PCIE_TX1_N

CRITICAL

M23

PCIE_RX2_P

M22

PCIE_RX2_N

H23

PCIE_RX3_P

H22

PCIE_RX3_N

V19

PCIE_REFCLK_100_IN_P

T19

PCIE_REFCLK_100_IN_N

AC5 N16

PCIE_CLKREQ*

AB7

DPSNK0_ML0_P

AC7

DPSNK0_ML0_N

AB9

DPSNK0_ML1_P

AC9

DPSNK0_ML1_N

AB11 AC11

AB13 AC13

AB15 AC15

AB17 AC17

AB19 AC19

AB21 AC21

AC23 AB23

DPSNK0_ML2_P DPSNK0_ML2_N

DPSNK0_ML3_P DPSNK0_ML3_N

Y11

DPSNK0_AUX_P

W11

DPSNK0_AUX_N

AA2

DPSNK0_HPD

Y5

DPSNK0_DDC_CLK

R4

DPSNK0_DDC_DATA

DPSNK1_ML0_P DPSNK1_ML0_N

DPSNK1_ML1_P DPSNK1_ML1_N

DPSNK1_ML2_P DPSNK1_ML2_N

DPSNK1_ML3_P DPSNK1_ML3_N

Y12

DPSNK1_AUX_P

W12

DPSNK1_AUX_N

Y6

DPSNK1_HPD

Y8

DPSNK1_DDC_CLK

N4

DPSNK1_DDC_DATA

Y18

DPSNK_RBIAS

Y4

TDI

V4

TMS

T4

TCK

W4

TDO

H6

RBIAS

J6

RSENSE

A15

PA_RX1_P

B15

PA_RX1_N

A17

PA_TX1_P

B17

PA_TX1_N

A19

PA_TX0_P

B19

PA_TX0_N

B21

PA_RX0_P

A21

PA_RX0_N

Y15

PA_DPSRC_AUX_P

W15

PA_DPSRC_AUX_N

E20

PA_USB2_D_P

D20

PA_USB2_D_N

A5

PA_LSTX

A4

PA_LSRX

M4

PA_DPSRC_HPD

H19

PA_USB2_RBIAS

THERMDA THERMDA

V18

PCIE_ATEST

AC1

TEST_EDM

L15

FUSE_VQPS_64

N15

FUSE_VQPS_128

C23

MONDC_CIO_0

C22

MONDC_CIO_1

SINK PORT 0

SINK PORT 1

PORT A

PCIE GEN3

SOURCE PORT 0

MISC

PORT B POC GPIO LC GPIO

TBT PORTS

DEBUG

PCIE_TX2_P PCIE_TX2_N

PCIE_TX3_P PCIE_TX3_N

PERST*

PCIE_RBIAS

DPSRC_ML0_P DPSRC_ML0_N

DPSRC_ML1_P DPSRC_ML1_N

DPSRC_ML2_P DPSRC_ML2_N

DPSRC_ML3_P DPSRC_ML3_N

DPSRC_AUX_P DPSRC_AUX_N

DPSRC_HPD

DPSRC_RBIAS

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7

GPIO_8 POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4 POC_GPIO_5 POC_GPIO_6

TEST_EN

TEST_PWR_GOOD

RESET*

XTAL_25_IN

XTAL_25_OUT

EE_DI EE_DO

EE_CS*

EE_CLK

PB_RX1_P PB_RX1_N

PB_TX1_P PB_TX1_N

PB_TX0_P PB_TX0_N

PB_RX0_P PB_RX0_N

PB_DPSRC_AUX_P PB_DPSRC_AUX_N

PB_USB2_D_P PB_USB2_D_N

PB_LSTX PB_LSRX

PB_DPSRC_HPD

PB_USB2_RBIAS

MONDC_SVR

ATEST_P ATEST_N

USB2_ATEST

MONDC_DPSNK_0 MONDC_DPSNK_1

MONDC_DPSRC

V23 V22

P23 P22

K23 K22

F23 F22

L4

PCIE_TBT_X_D2R_C_P<0> PCIE_TBT_X_D2R_C_N<0>

PCIE_TBT_X_D2R_C_P<1> PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2> PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_P<3> PCIE_TBT_X_D2R_C_N<3>

TBT_X_PCI_RESET_L

TBT_X_PCIE_BIAS

R2 R1

N2 N1

L2 L1

J2 J1

W19 Y19

G1

N6

U1 U2 V1 V2 W1 W2 Y1 Y2 AA1 J4 E2 D4 H4 F2 D2 F1

E1

AB5

F4

D22 D23

AB3 AC4 AC3 AB4

B7 A7

A9 B9

A11 B11

A13 B13

Y16 W16

E19 D19

B4 B5 G2

F19

D6

A23 B23

E18

W13 W18

AB2

NC_DP_X_SRC_ML_P<0> NC_DP_X_SRC_ML_N<0>

NC_DP_X_SRC_ML_P<1> NC_DP_X_SRC_ML_N<1>

NC_DP_X_SRC_ML_P<2> NC_DP_X_SRC_ML_N<2>

NC_DP_X_SRC_ML_P<3> NC_DP_X_SRC_ML_N<3>

NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N

DP_X_SRC_HPD

28

DP_X_SRC_RBIAS

I2C_TBT_X_SDA I2C_TBT_X_SCL

TBT_X_ROM_WP_L

26

TBT_X_TMU_CLK_OUT SMC_PME_S4_DARK_L TBT_X_CIO_PLUG_EVENT_L DDI1_MUX_SEL DDI2_MUX_SEL TBT_X_TMU_CLK_IN I2C_TBT_XA_INT_L I2C_TBT_XB_INT_L TBT_X_USB_PWR_EN TBT_X_FORCE_PWR PM_BATLOW_L PM_SLP_S3_L TBT_X_CIO_PWR_EN

TBT_X_TEST_EN

TBT_X_TEST_PWR_GOOD

USBC_X_RESET_L

TBT_X_XTAL25M_IN TBT_X_XTAL25M_OUT

UPC_X_SPI_MOSI UPC_X_SPI_MISO UPC_X_SPI_CS_L UPC_X_SPI_CLK

USBC_XB_D2R_P<2> USBC_XB_D2R_N<2>

USBC_XB_R2D_C_P<2> USBC_XB_R2D_C_N<2>

USBC_XB_R2D_C_P<1> USBC_XB_R2D_C_N<1>

USBC_XB_D2R_P<1> USBC_XB_D2R_N<1>

DP_XB_AUXCH_C_P DP_XB_AUXCH_C_N

USB_UPC_XB_P USB_UPC_XB_N

TBT_XB_LSTX TBT_XB_LSRX DP_XB_HPD

BI

OUT

IN

TBT_XB_USB2_RBIAS

PLACE_NEAR=U2800.F19:2MM

1

R2853

NC NC

NC

499

1% 1/20W MF 201

2

BOM_COST_GROUP=TBT

28

IN

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

IN

OUT

28

32 28

28

To SPI Flash

31

IN

31

IN

31

OUT

31

OUT

31

OUT

31

OUT

31

IN

31

IN

30 26

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28 19

PLACE_NEAR= U2800.N6:2MM

R2852

1/20W

1 2

1%

28

OUT

BI

OUT

IN

92 28

28

34

94

30 29 28

PU at PCH

28

PU at PCH

28

30 29

1

R2829

100

5% 1/20W MF 201

2

GND_VOID=TRUE

C2812

0.1UF

C2813

0.1UF

GND_VOID=TRUE

DRAWING

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

PLACE_NEAR=U2800.N16:2MM

R2851

3.01K

1 2

1%

1/20W

MF

201

201MF

14K

PP3V3_S5_TBT_X_SW

1

R2836

2.2K

5% 1/20W MF 201

2

28

IN

104 92 80 77 74 73 48 19 14

1

R2825

100

5% 1/20W MF 201

2

1 2

DP_XB_AUXCH_P

10% 16V

X5R-CERM

10% 16V

X5R-CERM

0201

DP_XB_AUXCH_N

0201

LAST_MODIFIED=Tue Aug 30 11:06:20 2016

USB-C HIGH SPEED 1

Apple Inc.

R

PP3V3_S5_TBT_X_SW

26 32

30

1

R2835

2.2K

5% 1/20W MF 201

2

BI

1

R2834

2.2K

5% 1/20W MF 201

2

1

R2837

2.2K

5% 1/20W MF 201

2

IN

not used

1

R2827

100K

5% 1/20W MF 201

2

BI

28

BI

26 32

28

SYNC_DATE=07/27/2015SYNC_MASTER=J79_GREG

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

28 OF 145

SHEET

26 OF 119

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

1

C2930

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2931

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2984

1.0UF

20%

6.3V

2

X5R 0201-1

C2945

1.0UF

20%

6.3V X5R

0201-1

1

C2932

1.0UF

20%

6.3V

2

X5R 0201-1

1

2

1

C2933

2

1

C2964

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2985

1.0UF

20%

6.3V

2

X5R 0201-1

C2946

1.0UF

20%

6.3V X5R

0201-1

1.0UF

20%

6.3V X5R 0201-1

1

2

SOURCED BY INTERNAL SWITCH

1

C2934

2

1

C2965

1.0UF

20%

6.3V

2

X5R 0201-1

SOURCED BY INTERNAL SWITCH

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

C2947

1.0UF

20%

6.3V X5R

0201-1

1.0UF

20%

6.3V X5R 0201-1

VOLTAGE=3.3V

1

2

1

C2935

2

1

C2966

1.0UF

20%

6.3V

2

X5R 0201-1

PP0V9_TBT_X_DP

1

C2936

1.0UF

20%

6.3V X5R 0201-1

SOURCED BY INTERNAL SWITCH

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2967

1.0UF

20%

6.3V

2

X5R 0201-1

28

PP0V9_TBT_X_PCIE

28

PP0V9_TBT_X_USB

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=0.9V

28

PP0V9_TBT_X_CIO

PP3V3_TBT_X_ANA_PCIE

PP3V3_TBT_X_ANA_USB2

1

C2920

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

C2921

1.0UF

20%

6.3V

2

X5R 0201-1

SOURCED BY

INTERNAL SWITCH

L8

VCC0P9_DP

L11

VCC0P9_DP

L12

VCC0P9_DP

M8

VCC0P9_DP

T11

VCC0P9_DP

T12

VCC0P9_DP

L6

VCC0P9_ANA_DPSRC

M6

VCC0P9_ANA_DPSRC

V11

VCC0P9_ANA_DPSNK

V12

VCC0P9_ANA_DPSNK

V13

VCC0P9_ANA_DPSNK

M13

VCC0P9_PCIE

M15

VCC0P9_PCIE

M16

VCC0P9_PCIE

L19

VCC0P9_ANA_PCIE_1

N19

VCC0P9_ANA_PCIE_1

L18

VCC0P9_ANA_PCIE_2

M18

VCC0P9_ANA_PCIE_2

N18

VCC0P9_ANA_PCIE_2

R15

VCC0P9_USB

R16

VCC0P9_USB

R8

VCC0P9_CIO

R9

VCC0P9_CIO

R11

VCC0P9_CIO

R12

VCC0P9_CIO

L16

VCC3P3_ANA_PCIE

J16

VCC3P3_ANA_USB2

A6

VSS_ANA

A8

VSS_ANA

A10

VSS_ANA

A12 A14

VSS_ANA

A16

VSS_ANA

A18

VSS_ANA

A20

VSS_ANA

A22

VSS_ANA

B6

VSS_ANA

B8

VSS_ANA

B10

VSS_ANA

B12

VSS_ANA

B14

VSS_ANA

B16

VSS_ANA

B18

VSS_ANA

B20

VSS_ANA

B22

VSS_ANA

D8

VSS_ANA

D9

VSS_ANA

D11

VSS_ANA

D12

VSS_ANA

D13

VSS_ANA

D15

VSS_ANA

D16

VSS_ANA

D18

VSS_ANA

E8

VSS_ANA

E9

VSS_ANA

E11

VSS_ANA

E15

VSS_ANA

E16

VSS_ANA

E22

VSS_ANA

E23

VSS_ANA

F9

VSS_ANA

F20

VSS_ANA

F16

VSS_ANA

G22

VSS_ANA

G23

VSS_ANA

H1

VSS_ANA

H2

VSS_ANA

H12

VSS_ANA

H13

VSS_ANA

H15

VSS_ANA

H16

VSS_ANA

H20

VSS_ANA

J5

VSS_ANA

J19

VSS_ANA

J20

VSS_ANA

J18

VSS_ANA

J22

VSS_ANA

J23

VSS_ANA

K1

VSS_ANA

K2

VSS_ANA

L5

VSS_ANA

L20

VSS_ANA

L22

VSS_ANA

L23

VSS_ANA

M1

VSS_ANA

M2

VSS_ANA

M5

VSS_ANA

M19

VSS_ANA

M20

VSS_ANA

N5

VSS_ANA

N20

VSS_ANA

N22

VSS_ANA

N23

VSS_ANA

P1

VSS_ANA

P2

VSS_ANA

R5

VSS_ANA

R18

VSS_ANA

R19

VSS_ANA

R20

VSS_ANA

R22

VSS_ANA

U2800

TBT-AR-4C-CNTRL

SYM 2 OF 2

FCBGA

OMIT_TABLE

CRITICAL

VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA

VCC0P9_SVR_SENSE

VCC

VCC0P9_LVR_SENSE

GND

VCC3P3_LC

VCC3P3_SX

VCC3P3_S0

VCC3P3A

VCC3P3_SVR VCC3P3_SVR VCC3P3_SVR

VCC0P9_SVR VCC0P9_SVR

SVR_IND SVR_IND SVR_IND

SVR_VSS SVR_VSS

SVR_VSS

VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR

VSS_ANA VSS_ANA VSS_ANA VSS_ANAVSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

R6

F8

R13

H9

A2 A3 B3

L9 M9 E12 E13 F11 F12 F13 F15 J9

C1 C2 D1

A1 B1 B2

F18 H18 J11 H11

R23 T1 T2 T5 T20 U23 U22 V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2 M11

PP3V3_TBT_X_LC

PP3V3_S5_TBT_X_SW

1

C2991

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2975

10UF

20%

6.3V

2

CERM-X5R 0402-4

BYPASS=U2800.A2:A1:3MM

1

C2976

10UF

20%

6.3V

2

CERM-X5R 0402-4

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

DIDT=TRUE SWITCH_NODE=TRUE

0.68UH-20%-6.1A-0.020OHM

VR0V9_IND_TBT_X

PP0V9_TBT_X_LVR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

C2992

1.0UF

0201-1

1

20%

6.3V 2

X5R

Add XW or alias on support page

XW

XW2900

SM

1 2

PLACE_NEAR=U2800.AC22:2MM

NO_XNET_CONNECTION=1

PP3V3_TBT_X_F

VOLTAGE=3.3V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

C2977

10UF

20%

6.3V

2

CERM-X5R 0402-4

CRITICAL

L2950

1 2

1210

SOURCED BY INTERNAL SWITCH

20%

6.3V X5R

1

2

C2993

1.0UF

0201-1

28

TBTTHMSNS_D1_N

C2954

10UF

20%

6.3V

CERM-X5R

0402-4

1

C2978

10UF

20%

6.3V

2

CERM-X5R 0402-4

1

2

OUT

C2990

1.0UF

0201-1

1

2

C2955

10UF

CERM-X5R

0402-4

2x 10uF outside BGA area

1

20%

6.3V 2

X5R

1

2

C2950

47UF

20%

6.3V CER-X5R 0603

1

20%

6.3V 2

C2994

47UF

CER-X5R

C2917

12PF

5% 25V NP0-C0G 0201

20%

6.3V

0603

1

C2951

47UF

20%

6.3V

2

CER-X5R 0603

1

2

P0V9_TBT_X_SVR_AGND

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0V

56

BOM_COST_GROUP=TBT

C2995

47UF

CER-X5R

1

C2910

1.0UF

20%

6.3V

2

X5R 0201-1

20%

6.3V

0603

1

2

1

2

1

2

1 2

0603

L2990

1.0UH-20%-2.1A-0.128OHM

CRITICAL

C2911

1.0UF

20%

6.3V X5R 0201-1

C2952

47UF

20%

6.3V CER-X5R 0603

FROM USB-C PORT CONTROLLER (UPC)

1

C2981

1.0UF

20%

6.3V

2

X5R 0201-1

PP3V3_TBT_X_S0

1

C2912

1.0UF

20%

6.3V

2

X5R 0201-1

INTERNAL SWITCHING VR OUTPUT

1

C2913

1.0UF

20%

6.3V

2

X5R 0201-1

SYNC_MASTER=J79_GREG SYNC_DATE=09/09/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

28

28 32

1

C2914

1.0UF

20%

6.3V

2

X5R 0201-1

ISOLATE GND OF SVR_IND CAPS

AND GND OF VCC3P3_SVR CAPS

FROM SYSTEM GND IN LAYOUT

(SEE INTEL LAYOUT GUIDELINES)

28 101

1

C2915

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2980

0.1UF

10% 16V

2

X5R-CERM 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

C2916

1.0UF

20%

6.3V

2

X5R 0201-1

USB-C HIGH SPEED 2

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

29 OF 145

SHEET

27 OF 119

SOURCED BY INTERNAL SWITCH

9.0.0

D

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

TMU CLKs

TBT_X_TMU_CLK_OUT

26

MAKE_BASE=TRUE

TBT_X_TMU_CLK_OUT

Ridge 0.9V SVR XW

P0V9_TBT_X_SVR_AGND

27

DP SRC OPTIONS

IF DP SRC NOT USED

NC_DP_X_SRC_ML_P<0>

26

NC_DP_X_SRC_ML_P<1>

26

NC_DP_X_SRC_ML_P<2>

26

NC_DP_X_SRC_ML_P<3>

26

NC_DP_X_SRC_ML_N<0>

26

NC_DP_X_SRC_ML_N<1>

26

NC_DP_X_SRC_ML_N<2>

26

NC_DP_X_SRC_ML_N<3>

26

NC_DP_X_SRC_AUX_P

26

NC_DP_X_SRC_AUX_N

26

AR xtal

26

IN

OUT

TBT_X_XTAL25M_OUT

1

NOSTUFF

R3006

1M

5% 1/20W MF 201

2

TBT_X_XTAL25M_IN

25MHZ-25PPM-20PF-50OHM

RIDGE DEBUG CONN

USBC_DBG

28 26

34 26

28 29 30

27

Ridge PDs

TBT_X_CIO_PLUG_EVENT_L DP_X_SNK0_HPD DP_X_SNK1_HPD

TBT_POC_RESET PP3V3_TBT_X_LC

DP_X_SNK0_DDC_CLK

26

DP_X_SNK0_DDC_CLK

DP_X_SNK0_DDC_DATA

26

DP_X_SNK0_DDC_DATA

DP_X_SNK1_DDC_CLK

26

DP_X_SNK1_DDC_CLK

DP_X_SNK1_DDC_DATA

26

DP_X_SNK1_DDC_DATA

15

USB3_EXTA_R2D_C_P

IN

USB3_EXTA_R2D_C_N

IN

R3025

15

1 2

5%

1/20W

MF

201

NC_DP_X_SRC_ML_P<0> NC_DP_X_SRC_ML_P<1> NC_DP_X_SRC_ML_P<2> NC_DP_X_SRC_ML_P<3>

NC_DP_X_SRC_ML_N<0> NC_DP_X_SRC_ML_N<1> NC_DP_X_SRC_ML_N<2>

NC_DP_X_SRC_ML_N<3>

NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N

R3007

1 2

1/20W5%MF

2.00X1.60-SM

J3001

505070-1220

M-ST-SM

13 14

1 2

3 4

5 6

7 8

9 10

11 12

15

MAKE_BASE=TRUE

DCI

PCH USB3

PLACE_NEAR=U2800.V2:5mm

5%

XW3000

SHORT-L6-SM

1 2

DP_X_SRC_HPD

26

0

TBT_X_XTAL25M_OUT_R

201

CRITICAL

Y3000

TBT_X_PCI_RESET_L USBC_X_RESET_L PP3V3_S5_TBT_X_SW PP0V9_TBT_X_PCIEDP_XA_HPD PP0V9_TBT_X_USB PP0V9_TBT_X_CIO

16

C3020

0.1UF

1 2

10% 16V

X5R-CERM

0201

C3021

0.1UF

1 2

10% 16V

X5R-CERM

0201

TBT_T_TMU_CLK_IN

MAKE_BASE=TRUE

TBT_T_TMU_CLK_IN

R3024

1/20W MF 201

NO_XNET_CONNECTION=1

100K

1 2

R3040

1M

1 2

5%

1/20W

MF

201

1

2

2 4

1 3

2

1

R3067

5% MF 2011/20W

R3068

1/20W5% 201MF

R3069

1/20W 2015% MF

R3070

201

MF1/20W5%

15

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE NO_TEST=1

C3002

20PF

5% 25V C0G 0201

0201 C0G 25V 5%

20PF

C3003

19 26

27 32

27 29 26

27

100K

1 2

100K

1 2

100K

1 2

100K

1 2

OUT

92

X ACE-SMC I2C SERIES R'S

I2C_UPC_X_SDA2

29

I2C_UPC_X_SDA2

30

28

29

30

28

MAKE_BASE=TRUE

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2

MAKE_BASE=TRUE

I2C_UPC_X_SCL2

ACE A/B RPD STRAPPING

USBC_XA_CC1

29

USBC_XA_CC2

29

USBC_XB_CC1

30

USBC_XB_CC2

30

ACE PDs

33 28

94 51 48

UPC_X_5V_EN

28 26

28 32 26

28

30 29

FUSES FOR UPC

28 29

28 30

DCI ALIASES

MAKE_BASE=TRUE

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_P

USB3_EXTA_R2D_N

MAKE_BASE=TRUE

R3041

1/20W MF332015%

R3042

5% MF

ACE DEBUG CONN

USBC_DBG

I2C_TBT_XB_INT_L I2C_UPC_X_SCL2

I2C_UPC_X_SDA2 SMC_USBC_INT_L TBT_X_SPI_CLK_DBG UPC_XA_UART_TX

PP20V_USBC_XA_VBUS

PP20V_USBC_XB_VBUS

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_P

USB3_EXTA_R2D_N

PLACE_NEAR=U5000:5mm

1 2

PLACE_NEAR=U5000:5mm

33

1 2

201MF5% 1/20W

MAKE_BASE=TRUE

SMBUS_SMC_4_G3H_SDA

SMBUS_SMC_4_G3H_SCL

USBC_XA_CC1

MAKE_BASE=TRUE

USBC_XA_CC2

MAKE_BASE=TRUE

USBC_XB_CC1

MAKE_BASE=TRUE

USBC_XB_CC2

R3032

100K

1 2

2011/20W

J3000

505070-1220

M-ST-SM

13 14

1 2

3 4

5 6

7 8

9 10

11 12

15

PLACE_NEAR=Q3100:5MM

16

CRITICAL

0603

F3000

6AMP-32V-0.0095OHM

1 2

PLACE_NEAR=Q3200:5MM

CRITICAL

0603

740S0135

F3001

6AMP-32V-0.0095OHM

1 2

SMBUS_SMC_4_G3H_SDA

SMBUS_SMC_4_G3H_SCL

104 31 29

104 31 30

ACE Debug Support

UPC_XA_DBG_UART_TX

29

UPC_XA_DBG_UART_RX

29

UPC_XB_DBG_UART_TX

30

UPC_XB_DBG_UART_RX

30

I2C_TBT_XA_INT_L I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_UPC_XA_DBG_CTL_SDA I2C_UPC_XA_DBG_CTL_SCL UPC_XA_UART_RX

PP20V_USBC_XA_VBUS_F

PP20V_USBC_XB_VBUS_F

29

IN

OUT

29

DCI Ace

51

OMIT

R3089

NOSTUFF

NONE NONE NONE

OMIT

R3088

NOSTUFF

NONE NONE NONE

28 26

29

30 29

29

30

402

0

1 2

201

0

1 2

201

0

1 2

201

0

1 2

201

AR/ACE SPI BUS SERIES R'S

R3094

TBT_X_SPI_CLK

26

TBT_X_SPI_CS_L

26

TBT_X_SPI_MOSI

26

TBT_X_SPI_MISO

26

ROM

R3095 R3096 R3097 R3098 R3090 R3091 R3092 R3093

100

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

USBC DEBUG CONN

TBT_X_SPI_CLK_DBG

5% 1/20W MF 201

UPC_XB_SPI_CLK

1/20W

UPC_XB_SPI_CS_L

UPC_XB_SPI_MOSI

5% 1/20W 201

UPC_XB_SPI_MISO

5% MF1/20W

UPC_X_SPI_CLK

UPC_X_SPI_CS_L

5% 201

1/20W MF

UPC_X_SPI_MOSI

1/20W 201

5% MF

UPC_X_SPI_MISO

5% 1/20W 201MF

201MF5%

2015% 1/20W MF

MF

201

MF1/20W 2015%

28

OUT

IN

30

28 26

Ace

D

AR

USB2 AR PDs

GND ALIASES

GND

29

GND

30

GND

29 30 95 96

GND

29

GND

29

GND

29

USB_UPC_XA_P

26

USB_UPC_XA_N

26

USB_UPC_XB_P

26

USB_UPC_XB_N

26

29

30

29

30

29

R3020

5% MF1/20W

R3021

MF1/20W5%

R3022

5% MF1/20W

R3023

MF5% 1/20W

GND GND GND GND GND

GND

NC ALIASES / NO TEST

NO_TEST=1

30

IN

NC_UPC_XB_I2C_ADDR

TBT to ACE

SIGNAL ALIASES

MAKE_BASE=TRUE

UPC_X_5V_EN

29

UPC_X_5V_EN

30

1

2

1

2

106 34

TBT_X_CIO_PWR_EN

26 29 30

TBT_X_USB_PWR_EN

26 29 30

PM_BATLOW_L

26

SMC_PME_S4_DARK_L

26 92

SMC_PME_S4_DARK_L

29 30 95 96

UPC_X_SPI_CLK

26 28

UPC_X_SPI_CS_L

26 28

UPC_X_SPI_MOSI

26 28

UPC_X_SPI_MISO

26 28

UPC_T_SPI_CLK

92 94

UPC_T_SPI_CS_L

92 94

UPC_T_SPI_MOSI

92 94

UPC_T_SPI_MISO

92 94

JTAG_ISP_TDO

26 92 94

TBT_POC_RESET

28 29 30

DDI1_MUX_SEL

DDI2_MUX_SEL

TBT_X_CIO_PLUG_EVENT_L

16

XDP_USB_EXTA_OC_L

29

XDP_USB_EXTB_OC_L

30

JTAG_TBT_X_TMS

13

JTAG_TBT_T_TMS

13 94

SMC_DEBUGPRT_TX_L

30

SMC_DEBUGPRT_RX_L

30

NC_USBC_XA_RESET_L

29

USB_UPC_PCH_XA_N

15

USB_UPC_PCH_XA_N

29

USB_UPC_PCH_XA_P

15

USB_UPC_PCH_XA_P

29

USB_UPC_PCH_XB_N

15

USB_UPC_PCH_XB_N

30

USB_UPC_PCH_XB_P

15

USB_UPC_PCH_XB_P

30

UPC_X_5V_EN

MAKE_BASE=TRUE

TBT_X_CIO_PWR_EN

MAKE_BASE=TRUE

TBT_X_USB_PWR_EN

MAKE_BASE=TRUE

PM_BATLOW_L

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

UPC_X_SPI_CLK

MAKE_BASE=TRUE

UPC_X_SPI_CS_L

MAKE_BASE=TRUE

UPC_X_SPI_MOSI

MAKE_BASE=TRUE

UPC_X_SPI_MISO

MAKE_BASE=TRUE

UPC_T_SPI_CLK

MAKE_BASE=TRUE

UPC_T_SPI_CS_L

MAKE_BASE=TRUE

UPC_T_SPI_MOSI

MAKE_BASE=TRUE

UPC_T_SPI_MISO

MAKE_BASE=TRUE

JTAG_ISP_TDO

MAKE_BASE=TRUE

TBT_POC_RESET

MAKE_BASE=TRUE

DDI1_MUX_SEL

MAKE_BASE=TRUE

DDI2_MUX_SEL

MAKE_BASE=TRUE

TBT_X_CIO_PLUG_EVENT_L

MAKE_BASE=TRUE

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

JTAG_TBT_X_TMS

MAKE_BASE=TRUE

JTAG_TBT_T_TMS

MAKE_BASE=TRUE

SMC_DEBUGPRT_TX_L

MAKE_BASE=TRUE

SMC_DEBUGPRT_RX_L

MAKE_BASE=TRUE

NC_USBC_XA_RESET_L

MAKE_BASE=TRUE

USB_UPC_PCH_XA_N

MAKE_BASE=TRUE

USB_UPC_PCH_XA_P

MAKE_BASE=TRUE

USB_UPC_PCH_XB_N

MAKE_BASE=TRUE

USB_UPC_PCH_XB_P

13

16

33 28

94 5

94 16

26

102

Alpine Ridge U2800

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

94 48 14

50 49 48

26 105 15

26

28 26

17 5

94 92

104 49 48

26

15

MAKE_BASE=TRUE

PCIE_TBT_X_D2R_C_P<0> PCIE_TBT_X_D2R_P<0>

IN OUT

PCIE_TBT_X_D2R_C_N<0>

IN

PCIE_TBT_X_D2R_C_P<1>

IN

PCIE_TBT_X_D2R_C_N<1> PCIE_TBT_X_D2R_N<1>

IN

PCIE_TBT_X_D2R_C_P<2> PCIE_TBT_X_D2R_P<2>

IN

PCIE_TBT_X_D2R_C_N<2> PCIE_TBT_X_D2R_N<2>

IN

PCIE_TBT_X_D2R_C_P<3>

IN

PCIE_TBT_X_D2R_C_N<3> PCIE_TBT_X_D2R_N<3>

IN

PCIE_TBT_X_R2D_C_P<0>

IN

PCIE_TBT_X_R2D_C_N<0>

IN

PCIE_TBT_X_R2D_C_P<1>

IN

PCIE_TBT_X_R2D_C_N<1>

IN

POWER ALIASES

PCIE_TBT_X_R2D_C_P<2>

IN

PCIE_TBT_X_R2D_C_N<2>

IN

PCIE_TBT_X_R2D_C_P<3>

IN

PCIE_TBT_X_R2D_C_N<3>

IN

PP3V3_UPC_XA_LDO

29

PP3V3_UPC_XA_LDO

29

PP3V3_UPC_XA_LDO

29

PP3V3_UPC_XB_LDO

26

PP3V3_UPC_XB_LDO

30

PP3V3_UPC_XB_LDO

30

PP3V3_UPC_XB_LDO

30

PP20V_USBC_XA_VBUS

28 29

PP20V_USBC_XB_VBUS

28 30

PP5V_S4_X_USBC

29

PP5V_S4_X_USBC

30

PP5V_S4_X_USBC

33

PP3V3_TBT_X_S0

27 101

MAKE_BASE=TRUE

PP3V3_UPC_XA_LDO

MAKE_BASE=TRUE

PP3V3_UPC_XB_LDO

MAKE_BASE=TRUE

PP20V_USBC_XA_VBUS

MAKE_BASE=TRUE

PP20V_USBC_XB_VBUS

MAKE_BASE=TRUE

PP5V_S4_X_USBC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=5V

MAKE_BASE=TRUE

PP3V3_TBT_X_S0

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

29

31

30

15

BOM_COST_GROUP=TBT

TBT

(MASTER)

I2C_TBT_X_SCL

26 28

I2C_TBT_X_SDA

26 28

I2C_TBT_XA_INT_L

26 28

I2C_TBT_XB_INT_L

26 28

Ridge PCIE Caps

GND_VOID=TRUE

X5R 20%6.3V0201

GND_VOID=TRUE

X5R0201 6.3V 20%

GND_VOID=TRUE

X5R 20%0201 6.3V

GND_VOID=TRUE

0201 20% GND_VOID=TRUE

GND_VOID=TRUE

0201 20%X5R GND_VOID=TRUE

GND_VOID=TRUE

0201 GND_VOID=TRUE

0201 X5R 20% GND_VOID=TRUE

GND_VOID=TRUE

0201 X5R

SYNC_MASTER=J79_GREG SYNC_DATE=08/08/2016

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6.3V

X5R

6.3V0201

X5R 20%0201

6.3V

X5R 20%0201 6.3V

6.3V

6.3V 20%X5R0201

6.3V0201 20%X5R

X5R 6.3V 20%

6.3V

D2R

20%X5R

20%0201 X5R 6.3V

R2D

20%X5R0201 6.3V

20%X5R0201

20%6.3V

R

(Write: 0x70 Read: 0x71)

I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XA_INT_L

(Write: 0x7E Read: 0x7F)

I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XB_INT_L

C3050

12

0.22UF

C3051

12

PCIE_TBT_X_D2R_N<0>

0.22UF

C3052

12

PCIE_TBT_X_D2R_P<1>

0.22UF

C3053

12

0.22UF

C3054

12

0.22UF

C3055

12

0.22UF

C3056

12

PCIE_TBT_X_D2R_P<3>

0.22UF

C3057

12

0.22UF

C3040

12

PCIE_TBT_X_R2D_P<0>

0.22UF

C3041

12

PCIE_TBT_X_R2D_N<0>

0.22UF

C3042

12

PCIE_TBT_X_R2D_P<1>

0.22UF

C3043

12

PCIE_TBT_X_R2D_N<1>

0.22UF

C3044

12

PCIE_TBT_X_R2D_P<2>

0.22UF

C3045

12

PCIE_TBT_X_R2D_N<2>

0.22UF

C3046

12

PCIE_TBT_X_R2D_P<3>

0.22UF

C3047

12

PCIE_TBT_X_R2D_N<3>

0.22UF

USB-C Support

Apple Inc.

Pri ACE

U3100

Sec ACE

U3200

DRAWING NUMBER SIZE

051-00515

REVISION

BRANCH

PAGE

SHEET

29

30

OUT

15

OUT

15

OUT

15

OUT

15

OUT

15

OUT

15

OUT

26

OUT

26

OUT

26

OUT

26

OUT

26

OUT

26

OUT

26

OUT

26

OUT

D

9.0.0

dvt-fab09-0

30 OF 145

28 OF 119

C

105 15

B

A

8 7 5 4 2 1

36

D

PRIMARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3100

FDPC4044

PWR-CLIP-33

345678

2 1

D

C

PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES

CAP FOR PP_5V0 ON VR PAGE

PP20V_USBC_XA_VBUS

28

PP3V3_UPC_XA_LDO

28

PP3V3_G3H

100

GND

28 30 95 96

PP5V_S4_X_USBC

28

FUSE

Add on support page

1

C3100

10UF

20%

6.3V

2

CERM-X5R 0402-1

28

PP20V_USBC_XA_VBUS_F

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=20V

1

C3101

1UF

10% 35V

2

X5R 0402

A11

B11

C11

PP_5V0

D11

PP_5V0

A6A7A8

PP_HV

B7

PP_HV

H10

H11

PP_CABLE

J10

VBUS

S2 5

J11

VBUS

G2 4

K11B1H1

VBUS

VIN_3V3

NC

VDDIO

LDO_3V3

G1

2

3

1

UPC_XA_GATE1

TP_Q3100_DRAIN

UPC_XA_GATE2

K1

H2

VOUT_3V3

A2G1E1

LDO_BMC

LDO_1V8D

LDO_1V8A

S1

8

PP1V8_UPC_XA_LDOA

PP1V8_UPC_XA_LDOD

PP1V1_UPC_XA_LDO_BMC

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.1V

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

1

C3104

2.2UF

20% 4V

2

X5R-CERM 0201

30 94 95 96 100

P3V3_TBT_X_SX_EN_R

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.8V

1

C3105

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

PP3V3_UPC_XA_LDO

32

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=1.8V

1

C3106

0.47UF

10%

6.3V

2

CERM-X5R 0201

1

C3108

10UF

20%

6.3V

2

CERM-X5R 0402-1

28

C

B

PP3V3_UPC_XA_LDO

1M

1 2

1M

1 2

1M

1 2

R3109

5% 201MF1/20W

R3108

1/20W

5% 201MF

R3105

5% MF1/20W

28

I2C_UPC_XA_DBG_CTL_SCL

I2C_UPC_XA_DBG_CTL_SDA

UPC_XA_UART_RX

201

30 28

TESTPOINTS MUST BE

29 28

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

29 28

USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR

USE GPIO3 FOR POWER_GATE_EN

ON BANSURI DESIGNS

30 28 26

28 26

96 95 30 28

GND I2C_ADDR PRIMARY ONLY

28

IN

OUT

IN

OUT

IN

TBT_POC_RESET NC_USBC_XA_RESET_L

UPC_XA_DBG_UART_TX

UPC_XA_DBG_UART_RX

TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

DP_XA_HPD

GND

UPC_X_5V_EN

SMC_PME_S4_DARK_L

XDP_USB_EXTA_OC_L

GND

UPC_XA_R_OSC

CRITICAL

R3103

30 29 28

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

1

15K

0.1% 1/20W TF-LF

0201

2

TO SMC

28

51

28

29 28

BI

OUT

BI

OUT

IN

OUT

I2C_UPC_XA_DBG_CTL_SCL I2C_UPC_XA_DBG_CTL_SDA

I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_TBT_XA_INT_L

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2

SMC_USBC_INT_L

GND GND GND GND

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

PRIMARY ONLY

U3100

CD3215A

BGA

HV FET/SENSE

TYPE-C

CRITICAL OMIT_TABLE

SS

SENSEP SENSEN

HV_GATE1 HV_GATE2

C_CC1 C_CC2

RPD_G1 RPD_G2

C_USB_TP C_USB_TN

C_USB_BP C_USB_BN

C_SBU1 C_SBU2

NC

H7

B10 A10

B9 A9

L9

USBC_XA_CC1

L10

USBC_XA_CC2

K9

USBC_XA_CC1

K10

USBC_XA_CC2

K6 L6

K7 L7

K8 L8

L11

USBC_XA_USB_DBG_TOP_P USBC_XA_USB_DBG_TOP_N

USBC_XA_USB_DBG_BOT_P USBC_XA_USB_DBG_BOT_N

USBC_XA_SBU1 USBC_XA_SBU2

GROUND

NC or GND to dissipate heat

UPC_XA_SS

1

C3109

0.47UF

10%

6.3V

2

CERM-X5R 0201

BI

28

31

BI

31

1

C3114

220PF

10% 16V

2

CER-X7R 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.2000

BI

31 28

BI

1

C3113

220PF

10% 16V

2

CER-X7R 0201

104

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.2000

B

A

28

PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XA_LDO

USB_UPC_PCH_XA_P

BI

USB_UPC_PCH_XA_N

BI

PP3V3_UPC_XA_LDO

28

NO_XNET_CONNECTION=1

PLACE_NEAR=U3100:5mm

26

BI

26

BI

L3100

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

2 3

1

R3110

100K

5% 1/20W MF 201

2

TP_UPC_XA_SWD_DATA

TP_UPC_XA_SWD_CLK

30 29 28

30 28

4

26

IN

OUT

IN

OUT

UPC_XA_UART_RX UPC_XA_UART_TX

TBT_XA_LSTX TBT_XA_LSRX

USB_UPC_XA_F_P USB_UPC_XA_F_N

DP_XA_AUXCH_P DP_XA_AUXCH_N

28

BI

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_P USB3_EXTA_R2D_N

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

A1D6E5E6E7F5G5H4H5G8H8L1B8D8E8F6F7F8G6

GND

G7

SYNC_MASTER=J79_GREG SYNC_DATE=08/08/2016

PAGE TITLE

A

1

R3111

100K

NO_XNET_CONNECTION=1

8 7 5 4 2 1

5% 1/20W MF 201

2

GND

PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION

28

BOM_COST_GROUP=USB-C

36

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

USB-C PORT CONTROLLER A

DRAWING NUMBER SIZE

Apple Inc.

R

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

31 OF 145

29 OF 119

D

SECONDARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3200

FDPC4044

PWR-CLIP-33

PP20V_USBC_XB_VBUS

28

FUSE

Add on support page

PP20V_USBC_XB_VBUS_F

28

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=20V

S2 5

G2 4

NC

345678

2 1

D

G1

S1

2

3

1

8

UPC_XB_GATE1

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

29 94 95 96 100

C

B

PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES

PP3V3_UPC_XB_LDO

1M

1 2

1M

1 2

R3209

5%

R3208

R3205

1/20W MF 201

5%

MF1/20W 201

28

I2C_UPC_XB_DBG_CTL_SCL

I2C_UPC_XB_DBG_CTL_SDA

201MF5%1M1/20W

UPC_XA_UART_TX

30

PP3V3_UPC_XB_LDO

28

1

C3201

1UF

10% 35V

2

X5R 0402

TP_Q3200_DRAIN

UPC_XB_GATE2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

PP3V3_UPC_XB_LDO

P3V3_TBT_X_SX_EN_R

28

32

PP1V8_UPC_XB_LDOA

PP3V3_G3H

100

GND

28 29 95 96

PP5V_S4_X_USBC

28

CAP FOR PP_5V0 ON VR PAGE

TBT_POC_RESET USBC_X_RESET_L_R

UPC_XB_DBG_UART_TX

28

UPC_XB_DBG_UART_RX

28

TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

26

28

OUT

IN

DP_XB_HPD

GND

UPC_X_5V_EN

SMC_PME_S4_DARK_L

XDP_USB_EXTB_OC_L

GND

NC_UPC_XB_I2C_ADDR

TESTPOINTS MUST BE

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

29 28 26

29 28

IN

32

OUT

IN

96 95 29 28

UPC_XB_R_OSC

CRITICAL

15K

0.1% 1/20W TF-LF

0201

1

2

TO SMC

R3203

30 29 28

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

NEED 0.1%

I2C_UPC_XB_DBG_CTL_SCL

30

I2C_UPC_XB_DBG_CTL_SDA

30

28

51

28

BI

OUT

BI

OUT

IN

OUT

I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_TBT_XB_INT_L

I2C_UPC_X_SDA2 I2C_UPC_X_SCL2 SMC_USBC_INT_L

UPC_XB_SPI_CLK UPC_XB_SPI_MOSI UPC_XB_SPI_MISO UPC_XB_SPI_CS_L

1

C3200

10UF

20%

6.3V

2

CERM-X5R 0402-1

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

A11

B11

PP_5V0

C11

D11

PP_5V0

A6A7A8

PP_HV

B7

PP_HV

H10

H11

J10

VBUS

PP_CABLE

U3200

CD3215A

BGA

J11

K11B1H1

VBUS

HV FET/SENSE

TYPE-C

VDDIO

VIN_3V3

CRITICAL OMIT_TABLE

K1

H2

LDO_3V3

VOUT_3V3

A2G1E1

LDO_BMC

LDO_1V8D

LDO_1V8A

SS

SENSEP SENSEN

HV_GATE1 HV_GATE2

C_CC1 C_CC2

RPD_G1 RPD_G2

C_USB_TP C_USB_TN

C_USB_BP C_USB_BN

C_SBU1 C_SBU2

NC

H7

B10 A10

B9 A9

L9

USBC_XB_CC1

L10

USBC_XB_CC2

K9

USBC_XB_CC1

K10

USBC_XB_CC2

K6

USBC_XB_USB_TOP_P

L6

USBC_XB_USB_TOP_N

K7

USBC_XB_USB_BOT_P

L7

USBC_XB_USB_BOT_N

K8

USBC_XB_SBU1

L8

USBC_XB_SBU2

GROUND

L11

NC or GND to dissipate heat

PP1V8_UPC_XB_LDOD

PP1V1_UPC_XB_LDO_BMC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.1V

UPC_XB_SS

1

C3209

0.47UF

10%

6.3V

2

CERM-X5R 0201

28

BI

28

BI

31

BI

31

BI

31

BI

31

BI

31

BI

31

BI

1

C3204

2.2UF

20% 4V

2

X5R-CERM 0201

1

C3214

220PF

10% 16V

2

CER-X7R 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V

1

C3205

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.0900

BI

1

C3213

220PF

10% 16V

2

CER-X7R 0201

104 31 28

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.0900

104 31 28

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

C3206

0.47UF

10%

6.3V

2

CERM-X5R 0201

1

C3208

10UF

20%

6.3V

2

CERM-X5R 0402-1

C

B

28

BI

USB_UPC_PCH_XB_P

USB_UPC_PCH_XB_N

PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XB_LDO

NO_XNET_CONNECTION=1

1

2 3

28

L3200

90-OHM-0.1A

EXCX4CE

SYM_VER-1

4

PLACE_NEAR=U3200.L5:5mm

PLACE_NEAR=U3200.K5:5mm

PP3V3_UPC_XB_LDO

1

R3210

2

26

BI

26

BI

100K

5% 1/20W MF 201

30 29 28

29 28

26

42

28

TP_UPC_XB_SWD_DATA TP_UPC_XB_SWD_CLK

IN

OUT

IN

OUT

UPC_XA_UART_TX

UPC_XA_UART_RX

TBT_XB_LSTX

TBT_XB_LSRX

USB_UPC_XB_F_P USB_UPC_XB_F_N

DP_XB_AUXCH_P DP_XB_AUXCH_N

BI

SOC_SWCLK_DBG SOC_SWDIO_DBG

SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

A1D6E5E6E7F5G5H4H5G8H8L1B8D8E8F6F7F8G6

GND

G7

A

100K

5%

1/20W

MF

201

1

2

GND

PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION

28

R3211

NO_XNET_CONNECTION=1

BOM_COST_GROUP=USB-C

8 7 5 4 2 1

36

SYNC_MASTER=J79_GREG SYNC_DATE=02/28/2016

PAGE TITLE

USB-C PORT CONTROLLER B

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

32 OF 145

30 OF 119

A

D

Apple MACBOOK PRO TOUCH BAR X362 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual