Apple MACBOOK PRO TOUCH BAR X362 Schematics

8

www.schematic-x.blogspot.com

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

X362 MLB SCHEMATIC

LAST_MODIFICATION=Tue Aug 30 11:06:16 2016

2 1

CK

ECNREV DESCRIPTION OF REVISION

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

APPD

DATE

2016-08-3000069392729 ENGINEERING RELEASED

D

1 2

3 4 5 6 7 8 9 10 11 12 13 14

1 05/13/2016 2 3 4 5 6 7 8 9 10 11 12 13 14

Table of Contents BOM Configuration

BOM Configuration PD Parts CPU GFX CPU MISC/JTAG/CFG/RSVD CPU LPDDR3 Interface CPU & PCH Power CPU & PCH Grounds CPU Core Decoupling CPU GT Decoupling PCH Decoupling PCH Audio/LPC/SPI/SMBus PCH Power Management

SHART_J44 J79_JACK LDUNN_J44 J130_DEV_MLB_U

J130_DEV_MLB_U J52_MLB

J79_JSHAO J79_ALFRED

J79_JSHAO J79_JSHAO

J79_JSHAO J130_MLB J130_MLB

11/27/2012 04/07/2016 01/13/2013 04/29/2015 04/28/2015 05/12/2015 03/14/2016 05/12/2015 08/28/2015 08/28/2015 03/14/2016 02/22/2016 05/04/2016

61 62 63 64 65 66 67 68 69 70 71 72 73 74

63 64 65 66 69 70 71 72 73 74 75 76 77 78

AUDIO JACK CODEC Left Speaker Amps & Conn

Right Speaker Amps & Conn AUDIO JACK CONNECTOR DC-In & Battery Connectors PBUS Supply & Battery Charger CORE & SA IMVP IC CORE & SA IMVP POWER BLOCK Empty GT & GTX IMVP POWER BLOCK Empty Power - 5V 3.3V Supply Power - EOPIO EDRAM Supply PMIC-1 & Power Control

J79_JCURCIO J79_JCURCIO J79_JCURCIO J79_JCURCIO J79_JSHAO J79_JSHAO J79_JSHAO J79_JSHAO J79_SILUCHEN J79_JSHAO J79_SILUCHEN J79_JSHAO J79_JSHAO J79_JSHAO

11/18/2015 12/03/2015 12/18/2015 12/03/2015 12/03/2015 03/02/2016 12/03/2015 04/02/2015 09/25/2015 03/27/2015 03/23/2016 04/12/2016 09/09/2015

D

C

15 16 17 18 19 20 21 22 23 24 25 26 27 28

15 16 18 19 20 22 23 24 25 26 27 28 29 30

PCH PCIE/USB/CLKS PCH SPI/UART/GPIO CPU/PCH Merged XDP Chipset Support 1 Chipset Support 2 LPDDR3 VREF Margining LPDDR3 DRAM Channel A (00-31) LPDDR3 DRAM Channel A (32-63) LPDDR3 DRAM Channel B (00-31) LPDDR3 DRAM Channel B (32-63) LPDDR3 DRAM Termination USB-C HIGH SPEED 1 USB-C HIGH SPEED 2 USB-C Support

J130_MLB J130_MLB J130_MLB J79_GREG J79_GREG J52_MLB J52_MLB J52_MLB J52_MLB J52_MLB J52_MLB J79_GREG J79_GREG J79_GREG

06/23/2015 12/08/2015 12/08/2015 09/09/2015 07/05/2016 05/12/2015 05/12/2015 05/12/2015 05/12/2015 05/12/2015 05/12/2015 07/27/2015 09/09/2015 08/08/2016

75 76 77 78 79 80 81 82 83 84 85 86 87 88

79 80 81 82 84 85 86 87 88 89 90 91 92 93

PMIC-1 1.2V 0.6V VCCIO PMIC-1 1V 1.8V VCCPCH PMIC-1 Aliases & TPs Power FETs LCD Backlight Driver eDP Display Connector S3X CORE PCIE S3X POWER S3X GND Connector NAND VR, I2C ROM, TEMP SENSORS ANI[3:0] ANI[7:4] PICCOLO PMIC

J79_JSHAO J79_JSHAO J79_SILUCHEN J79_JSHAO J79_RUENJOU J79_RUENJOU J79_RUENJOU J79_RIO J79_RIO J79_RUENJOU J79_RUENJOU J79_RUENJOU J79_RUENJOU J79_RUENJOU

12/03/2015 12/03/2015 07/17/2015 03/14/2016 09/09/2015 09/12/2015 08/20/2015

C

06/18/2015 06/18/2015 09/09/2015 09/12/2015 09/25/2015 09/25/2015 09/24/2015

B

29 30 31 32 33 34 35 36 37 38 39 40 41 42

31 32 33 34 35 36 37 38 39 40 41 42 43 44

USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B USB-C CONNECTOR A USB-C CONNECTOR B TBT 5V REGULATOR Display Mux WIFI/BT: MODULE 1 WIFI/BT: MODULE 2 Camera/DFR 1 Camera/DFR 2 Camera/DFR 3 Berkelium - 1 Berkelium - 2 T208 Support

J79_GREG J79_GREG J79_GREG J79_GREG J79_JSHAO J79_GREG J79_METE

J79_METE J80_MLB_BAFFIN

J79_ANDREW J79_ANDREW J79_ANDREW J79_ANDREW J79_ANDREW

08/08/2016 02/28/2016 07/05/2016 03/24/2016 12/18/2015 02/28/2016 05/17/2016 03/02/2016 07/22/2016 03/22/2016 04/25/2016 03/14/2016 02/01/2016 07/01/2016

89 90 91 92 93 94

96 97 98 99 100 101 102

94 95 96 110 111 112 11395 114 115 116 117 120 121 122

SSD NAND VR Empty LIFEBOAT USB-C HIGH SPEED 1 USB-C HIGH SPEED 2 USB-C Support USB-C PORT CONTROLLER A USB-C PORT CONTROLLER B USB-C CONNECTOR A USB-C CONNECTOR B TBT 5V REGULATOR Power Aliases - 1 Power Aliases - 2

Signal Aliases

J79_JSHAO J14 J79_RUENJOU J79_GREG J79_GREG J79_GREG J79_GREG J79_GREG J79_GREG J79_GREG J79_JSHAO J79_ALFRED J79_ALFRED SHART_J44

12/18/2015 10/23/2012 09/09/2015

07/28/2015 08/28/2015 07/05/2016 02/28/2016 02/28/2016 07/05/2016 03/24/2016 12/18/2015 06/17/2015 06/18/2015 11/19/2012

B

A

Schematic / PCB #'s

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

SCHEM,MLB,X362 CRITICAL051-00515 1 SCH

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Connectors&ESD Empty Empty Empty MESA SMC SMC Shared Support SMC Project Support SMBus Connections Power Sensors: High Side Power Sensors: Load Side Power Sensors: Extended Power Sensors: Extended 2 Thermal Sensors Power Sensors:Extended 3 Fans SPI Debug Connector HDA Bridge

J79_GAREN J79_DAYU J79_DAYU J79_DAYU J79_ANDREW J79_JACK J79_JACK J79_JACK

J79_JACK J79_JACK J79_JACK J79_JACK J79_JACK J79_JACK J79_JACK J79_JACK J52_MLB J79_JCURCIO

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICALPCBF,MLB,X362820-00239 1 PCB

11/21/2015 05/26/2015 05/26/2015 05/12/2015 01/06/2016 04/11/2016 04/14/2016 04/11/2016 03/31/2016 12/07/2015 04/03/2016 01/08/2016 05/10/2016 09/24/2015 04/14/2016 08/21/2015 05/12/2015 03/24/2016

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119

123 124 125 127 129 130 131 132 133 134 135 136 137 138 139 140 145

LPDDR3 Bit & Byte Swizzle ICT FCT 1 ICT FCT 2 Desense Capacitors Empty PCB Rule Definitions CPU Constraints PCH Constraints Memory Constraints TBT DP HDMI Constraints PCIe Constraints USB Constraints SMC Constraints Camera Constraints Sensors & Audio Constraints References Alternates BOM Table

AHARTMAN_J52 YHARTANTO_J44 YHARTANTO_J44 YHARTANTO_J44 J79_RIO YHARTANTO_J44 YHARTANTO_J44 YHARTANTO_J44 YHARTANTO_J44 J79_JACK J79_JACK J79_JACK YHARTANTO_J44 YHARTANTO_J44 YHARTANTO_J44 J79_RUENJOU_CONSTRAINTS J80_MLB

10/29/2013 12/18/2012 12/18/2012 01/09/2013 06/18/2015 12/14/2012 01/13/2013 01/08/2013 01/02/2013 05/19/2015 05/19/2015 05/21/2015 01/02/2013 01/09/2013 01/04/2013 06/11/2015 12/12/2015

DRAWING TITLE

SCHEM,MLB,X362

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

?

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

1 OF 145

SHEET

1 OF 119

A

SIZEDRAWING NUMBER

D

3

1245678

D

BOM Groups

BOM GROUP BOM OPTIONS

X362_COMMON

X362_COMMON1

X362_COMMON2

X362_COMMON3

X362_PROGPARTS

X362_DEVEL:ENG

X362_DEVEL:DVT

X362_DEVEL:PVT

Module Parts

337S00266 U0500 CRITICAL1

337S00267 1 CRITICAL CPU_SKL23:3.1GU0500

353S00961

338S00276 U86001

343S00147 U3620 CRITICAL1

4

1 POP_4GBITPOP8600333S00055

ALTERNATE,COMMON,X362_COMMON1,X362_COMMON2,X362_COMMON3,X362_PROGPARTS

SE:PROD,BOARD_ID:8,T208_PROG:REV5,TBTTHRM_SNS,S3XCLK:INT

EDP_ENABLE,XDP:YES,PCH_CLK:GRNCLK,TBT_DBG,SAMCONN,SKIP_5V3V3:AUDIBLE,SOC_BOOT:SPI

CPUTHRM:ALRT,TBTTHRM:ALRT,LOADRC:NO,CUMULUS_IPD,S3_STATE:YES,VCCPLLOC:S3

BOOTROM_PROG,SMC_PROG,AR_LT_PROG,AR_RT_PROG,WIFI_PROG,BTROM_PROG

ALTERNATE,DBGLED,USBC_DBG,XDP_CONN:YES,WIFI_DBG,S3X_DBG,DEBUG_BUTTON,LOADISNS

ALTERNATE,USBC_DBG,XDP_CONN:YES,WIFI_DBG

ALTERNATE

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CPU,SKLU,SR2JK,PRQ,2.9,28W,1.05,B1356

CPU,SKLU,SR2JJ,PRQ,3.1,28W,1.1,B1356

CPU,SKLU,SR2JH,PRQ,3.3,28W,1.1,B1356

INTERPOSER,VTT ADAPTER,SKL-U,BGA1356

IC,TBT,ALPINE RIDGE,QSTY,PRQ,C1,CSP337

IC,CD3215,ACE,C00,USB PWR SW,BLNK,BGA96

IC,CNTLR,S3X,B1,FCBGA900

IC,LPDDR3-1600,4GBIT,25NM,A,276B

IC,LPDDR3-1600,8GBIT,25NM,A,276B

IC,SLG4AP41172,PAK3,STQFN20

U2800,UB000338S00254 CRITICAL2

U3100,U3200,UB300,UB400

CRITICAL CPU_SKL23:3.3GU0500337S00268 1

CRITICALU0500 CPU_SOCKET1998-04195

CRITICAL

CPU_SKL23:2.9G

POP_8GBITPOP86001333S00056

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

345678

Variable BOM Groups Development/Base BOMs

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1685-00055

COMMON PARTS,MLB,X362

DEV,MLB,X362

CRITICAL BASE_BOMBASE

CRITICAL985-00070

DEVEL_BOMDEVEL1

Main DRAM Parts

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

333S00069

4

333S00070 4

4333S00068

333S00050

4

IC,SDRAM,LPDDR3-2133,16GBIT,20NM,BGA178 U2300,U2400,U2500,U2600

IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178

IC,SDRAM,LPDDR3-2133,16GBIT,20NM,BGA178

IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178

U2300,U2400,U2500,U2600

CRITICAL CRITICAL CRITICAL 8G_SAMSUNG_2133 CRITICAL

8G_MICRON_2133

16G_MICRON_2133

16G_SAMSUNG_2133

Main DRAM SPD Straps

BOM GROUP BOM OPTIONS

8G_MICRON_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG1_LRAM_8G_MICRON_2133

16G_MICRON_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG1_LRAM_16G_MICRON_2133

RAM_8G_SAMSUNG_2133 8G_SAMSUNG_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG0_L

RAM_16G_SAMSUNG_2133

16G_SAMSUNG_2133,RAMCFG4_L,RAMCFG3_L,RAMCFG0_L

2 1

CPU DRAM CFG Chart

A 0

B

SPEED

2133

1866

CAPACITY

8GB

16GB

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

VENDOR

HYNIX

MICRON

SAMSUNG

N/A

CFG 1

CFG 4DIE REV

1

D

CFG 3

0

1

CFG 2

0

1

CFG 0

0

1

0

1

0

1

C

1 CRITICALU7800338S00221

1 U7000353S01016

IC,PMU,SN650839,7X7MM,BGA168

IC,ISL9239HIZ,PMU,TUBA,WCSP40,2.1X3.3MM

IC,PMU,PICCOLO,D2231A0,OTP-AK,WLCSP96

Programmables (All Builds)

EFI ROM

341S00698

SMC ROM

341S00700

TBT ROMs

341S00717

341S00718

WIFI/BT ROM

1

IC,EFI ROM (V0193) DVT,X362

IC,SMC-B1,EXT (V2.37F6) PVT,X362

T29,AR1 (VTBD) PVT,X362

T29,AR2 (VTBD) PVT,X362

U6100

U5000

U2890

UB090

CRITICAL

CRITICAL1 U9300338S00227

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1

BOOTROM_PROGCRITICAL

SMC_PROGCRITICAL

AR_LT_PROG

AR_RT_PROGCRITICAL

NAND Parts

335S00124 4 335S00125 335S00126 335S00261

4 CRITICAL 4 4

335S00262 335S00263

4

NAND Straps

BOM GROUP BOM OPTIONS

SAND_256G SAND_512G

SAND_1T TOSH_256G TOSH_512G

TOSH_1T

NAND,1ZNM,128GB,TOGG,HPN,128G,LGA60

NAND,1ZNM,256GB,TOGG,HPN,128G,LGA60

NAND,TGDDR2,128GX4,15NM,HP,USHD,T2,LGA60

NAND,TGDDR2,128GX8,15NM,HP,USHD,T2,LGA60

NAND,TGDDR2,128GX16,15NM,HP,UHD,T2,LGA60

ALTERNATE,NAND_SDISK_256GB,POP_4GBIT,CAPACITY1,CAPACITY0

ALTERNATE,NAND_SDISK_1TB,POP_8GBIT,CAPACITY2,CAPACITY0

ALTERNATE,NAND_TSHBA_256GB,POP_4GBIT,CAPACITY1,CAPACITY0

ALTERNATE,NAND_TSHBA_1TB,POP_8GBIT,CAPACITY2,CAPACITY0

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

U9100,U9120,U9200,U9220NAND,1ZNM,64GB,TOGG,HPN,128G,LGA60

U9100,U9120,U9200,U9220

CRITICAL

CRITICAL CRITICAL CRITICAL4 CRITICAL

NAND_SDISK_256GB

NAND_SDISK_512GB

NAND_SDISK_1TB

NAND_TSHBA_256GB

NAND_TSHBA_512GB

NAND_TSHBA_1TB

ALTERNATE,NAND_SDISK_512GB,POP_4GBIT,CAPACITY2

ALTERNATE,NAND_TSHBA_512GB,POP_4GBIT,CAPACITY2

C

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

B

A

341S00715

341S00716

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1 CRITICALU3750 BTROM_PROG

IC,BT ROM (V32) PVT,X362/X363

WIFI ROM (P108) PVT,WW1,X362/X363

CRITICAL WIFI_PROGU37101

Strategic Silicon

PART# COMMENT

337S00266

337S00267 08

337S00268

333S00068 07

333S00069

335S00124

335S00125

335S00126

335S00261

335S00262

335S00263

333S00026 02

333S00108

STRATEGIC VALUE

08

07333S00050

07

07333S00070

02

02333S00025

02333S00055

02333S00056

02333S00107

02

02998-06736

CPU

MEMORY

NAND

S3X DRAM

S3X CONTROLLER

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

PART# COMMENT

338S00227

343S00135

343S00136

343S00137

343S00138

353S3978

338S00147

338S00254 08

338S00142

353S4316

353S01016

343S00147

STRATEGIC VALUE

02

10

09338S00193

02

09353S00961

09

07353S00685

08

08338S00221

09

05339S00056

08

08359S00006

09353S00795

PICCOLO

T208

BERKELIUM

MOJAVE

SECURE ELEMENT

ALPINE RIDGE

ACE

CLIFDEN

AUDIO AMP

BAYSIDE

BANJO

TUBA

ICEBOCK

PAK

GREEN CLOCK

DEBUG MUX

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

SYNC_MASTER=SHART_J44 SYNC_DATE=11/27/2012

PAGE TITLE

BOM Configuration

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

2 OF 145

SHEET

2 OF 119

D

B

A

8 7 5 4 2 1

36

D

C

BOM Variants

BOM NUMBER BOM NAME BOM OPTIONS

685-00055 COMMON PARTS,MLB,X362 X362_COMMON

985-00070 DEV,MLB,X362 X362_DEVEL:DVT

639-01870

MLB,2.9G,SAM-8G,SAND-256G,X362

639-01871 MLB,2.9G,SAM-16G,SAND-256G,X362

639-01872 MLB,2.9G,MIC-8G,SAND-256G,X362

639-01873 MLB,2.9G,MIC-16G,SAND-256G,X362

639-01984

MLB,2.9G,SAM-8G,SAND-512G,X362

639-01985 MLB,2.9G,SAM-16G,SAND-512G,X362

639-01986

MLB,2.9G,MIC-8G,SAND-512G,X362

639-01987 MLB,2.9G,MIC-16G,SAND-512G,X362

639-02517

MLB,2.9G,SAM-8G,SAND-1T,X362

639-02518 MLB,2.9G,SAM-16G,SAND-1T,X362

639-02519 MLB,2.9G,MIC-8G,SAND-1T,X362

639-02520 MLB,2.9G,MIC-16G,SAND-1T,X362

639-01874 MLB,3.1G,SAM-8G,SAND-256G,X362

639-01875

639-01876

MLB,3.1G,SAM-16G,SAND-256G,X362

MLB,3.1G,MIC-8G,SAND-256G,X362

639-01877 MLB,3.1G,MIC-16G,SAND-256G,X362

639-01883 MLB,3.1G,SAM-8G,SAND-512G,X362

639-01884 MLB,3.1G,SAM-16G,SAND-512G,X362

639-01885 MLB,3.1G,MIC-8G,SAND-512G,X362

639-01886 MLB,3.1G,MIC-16G,SAND-512G,X362

639-01887

MLB,3.1G,SAM-8G,SAND-1T,X362

639-01888 MLB,3.1G,SAM-16G,SAND-1T,X362

639-01889 MLB,3.1G,MIC-8G,SAND-1T,X362

639-01890 MLB,3.1G,MIC-16G,SAND-1T,X362

639-02221 MLB,3.3G,SAM-8G,SAND-256G,X362

639-02222 MLB,3.3G,SAM-16G,SAND-256G,X362

639-02223 MLB,3.3G,MIC-8G,SAND-256G,X362

639-02224

MLB,3.3G,MIC-16G,SAND-256G,X362

639-01891 MLB,3.3G,SAM-8G,SAND-512G,X362

639-01892 MLB,3.3G,SAM-16G,SAND-512G,X362

639-01893 MLB,3.3G,MIC-8G,SAND-512G,X362

639-01894 MLB,3.3G,MIC-16G,SAND-512G,X362

639-01895 MLB,3.3G,SAM-8G,SAND-1T,X362

639-01896 MLB,3.3G,SAM-16G,SAND-1T,X362

639-01897 MLB,3.3G,MIC-8G,SAND-1T,X362

639-01898

MLB,3.3G,MIC-16G,SAND-1T,X362

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,SAND_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,SAND_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,SAND_1T

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

345678

BOM NUMBER BOM NAME BOM OPTIONS

MLB,NO CPU,X362639-01988

MLB,CPU SOCKET,X362639-01989

639-02521

639-02522

639-02523

639-02524

639-02525

639-02526

639-02527

639-02528

639-02529

MLB,2.9G,SAM-8G,TOSH-256G,X362

MLB,2.9G,SAM-16G,TOSH-256G,X362

MLB,2.9G,MIC-8G,TOSH-256G,X362

MLB,2.9G,MIC-16G,TOSH-256G,X362

MLB,2.9G,SAM-8G,TOSH-512G,X362

MLB,2.9G,SAM-16G,TOSH-512G,X362

MLB,2.9G,MIC-8G,TOSH-512G,X362

MLB,2.9G,MIC-16G,TOSH-512G,X362

MLB,2.9G,SAM-8G,TOSH-1T,X362

639-02530 MLB,2.9G,SAM-16G,TOSH-1T,X362

639-02531 MLB,2.9G,MIC-8G,TOSH-1T,X362

639-02532 MLB,2.9G,MIC-16G,TOSH-1T,X362

639-02533 MLB,3.1G,SAM-8G,TOSH-256G,X362

639-02534

MLB,3.1G,SAM-16G,TOSH-256G,X362

639-02535 MLB,3.1G,MIC-8G,TOSH-256G,X362

639-02536

MLB,3.1G,MIC-16G,TOSH-256G,X362

639-02537 MLB,3.1G,SAM-8G,TOSH-512G,X362

639-02538

MLB,3.1G,SAM-16G,TOSH-512G,X362

639-02539 MLB,3.1G,MIC-8G,TOSH-512G,X362

639-02540

639-02541

MLB,3.1G,MIC-16G,TOSH-512G,X362

MLB,3.1G,SAM-8G,TOSH-1T,X362

639-02542 MLB,3.1G,SAM-16G,TOSH-1T,X362

639-02543 MLB,3.1G,MIC-8G,TOSH-1T,X362

639-02544 MLB,3.1G,MIC-16G,TOSH-1T,X362

639-02545 MLB,3.3G,SAM-8G,TOSH-256G,X362

639-02546 MLB,3.3G,SAM-16G,TOSH-256G,X362

639-02547 MLB,3.3G,MIC-8G,TOSH-256G,X362

639-02548 MLB,3.3G,MIC-16G,TOSH-256G,X362

639-02549 MLB,3.3G,SAM-8G,TOSH-512G,X362

639-02550 MLB,3.3G,SAM-16G,TOSH-512G,X362

639-02551

639-02552

639-02553

639-02554

639-02555

MLB,3.3G,MIC-8G,TOSH-512G,X362

MLB,3.3G,MIC-16G,TOSH-512G,X362

MLB,3.3G,SAM-8G,TOSH-1T,X362

MLB,3.3G,SAM-16G,TOSH-1T,X362

MLB,3.3G,MIC-8G,TOSH-1T,X362

639-02556 MLB,3.3G,MIC-16G,TOSH-1T,X362

BASE_BOM,DEVEL_BOM,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SOCKET,RAM_16G_SAMSUNG_2133,SAND_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_8G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:2.9G,RAM_16G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_8G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.1G,RAM_16G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,TOSH_256G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,TOSH_512G

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_SAMSUNG_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_8G_MICRON_2133,TOSH_1T

BASE_BOM,DEVEL_BOM,CPU_SKL23:3.3G,RAM_16G_MICRON_2133,TOSH_1T

2 1

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

C

B

Alternate Parts

TABLE_ALT_HEAD

PART NUMBER

ALL152S00269152S00368 Text note to be updated

152S00370 152S00270 ALL Text note to be updated

ALL138S0884138S00086 Text note to be updated

152S1829 Text note to be updatedALL152S00434

371S00019

353S00107

371S0463

ALL Rohm alt to Rohm

ALL353S3239

ALL353S00231 NXP alt to TI353S3987

POP_4GBIT ALL MICRON SSD POP ALT for HYNIX333S00025 333S00055

POP_8GBIT ALL MICRON SSD POP ALT for HYNIX333S00026 333S00056

ALL HYNIX SSD POP REPLACEMENT for HYNIX333S00107 POP_4GBIT333S00055

POP_8GBIT HYNIX SSD POP REPLACEMENT for HYNIXALL333S00056333S00108

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

Text note to be updatedALL353S4068 353S4070

TABLE_ALT_ITEM

Text note to be updatedALL353S00772 353S4070

TABLE_ALT_ITEM

TFT alt to CyntecALL107S0250107S0248

TABLE_ALT_ITEM

Onsemi alt to IntersilANY

TABLE_ALT_ITEM

138S0701 ALL Text note to be updated138S0689

TABLE_ALT_ITEMTABLE_ALT_ITEM

138S0771 Text note to be updatedALL138S00012152S00266 ALL152S00367 Text note to be updated

TABLE_ALT_ITEM

ALL138S00013 Text note to be updated138S0772

TABLE_ALT_ITEM

152S00401 ALL Text note to be updated152S0529

TABLE_ALT_ITEM

Text note to be updated152S00344 ALL152S1683

TABLE_ALT_ITEM

152S00331 ALL Text note to be updated152S00283

TABLE_ALT_ITEM

ALL152S2034 Text note to be updated152S00190

TABLE_ALT_ITEM

197S0613 197S0612 ALL Text note to be updated

TABLE_ALT_ITEM

ALL Text note to be updated311S0398311S00121

TABLE_ALT_ITEM

Text note to be updated371S0558 ALL371S0713

TABLE_ALT_ITEM

371S0602 Text note to be updatedALL371S00074

B

A

PAGE TITLE

BOM Configuration

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=04/07/2016SYNC_MASTER=J79_JACK

051-00515

9.0.0

dvt-fab09-0

3 OF 145

3 OF 119

A

D

BOARD MECHANICALS

345678

2 1

D

Shield Cans - BOTTOM SIDE

ALPINE RIDGE - LIO (U2800) - 806-06077

1

SH0418

SM

SHLD-FENCE-ALPINE-X379

LPDDR3 (U2300 ~ U2600) - 806-06167

1

SH0415

SM

SHLD-FENCE-X379

NAND - BOTTOM SOUTH (U9120) - 806-05945

T208 (U3900) - 806-06264

1

SH0412

SM

SHLD-FENCE-M8-X379

DIPLEXERS - 806-06266

1

SH0411

SM

SHLD-MLB-DIPLEXER-X379

NAND - TOP SOUTH (U9100) - 806-06262

POGO PINSShield Cans - TOP SIDE

LIO and RIO -2X (870-5071)

SH0471

POGO-2.0OD-2.95H-SM

SM

1

AROUND THE FAN AND CENTER - 8X (870-01518)

POGO-2.0OD-2.95H-SM

SH0463

POGO-2.3OD-4.0H-SM

SM

1

POGO-2.3OD-4.0H-SM

SH0472

SM

1

SH0464

SM

1

SH0465

POGO-2.3OD-4.0H-SM

SM

1

SH0466

POGO-2.3OD-4.0H-SM

SM

1

Cowling Bosses - BOTTOM SIDE

DFR TOUCH CONN (J4402) - 860-00414

SH0425

6.25X3.85R-1.75ID-1.938H-SM

1

USB-C CONN - LIO (J3300) - 860-00392

SH0445

3.4OD1.75ID-1.12H-SM

1

DFR DISPLAY CONN (J4401) - 860-00412

D

SH0446

3.4OD1.75ID-1.12H-SM

1

C

1

SH0417

SM

SHLD-FENCE-NAND-BOT-SOUTH-X379

S3X (U8600) - 806-06023

1

SH0414

SM

SHLD-FENCE-S3X-X379

NAND - BOTTOM NORTH (U9200) - 806-06265

1

SH0419

SM

SHLD-FENCE-MLB-NAND-BTM-NORTH-X379

1

SH0416

SM

SHLD-FENCE-MLB-NAND-TOP-SOUTH-X379

NAND - TOP NORTH (9220) - 806-06258

1

SH0413

SM

SHLD-FENCE-MLB-NAND-NORTH-X379

SH0467

POGO-2.3OD-4.0H-SM

SM

1

SH0468

POGO-2.3OD-4.0H-SM

SM

1

SH0469

POGO-2.3OD-4.0H-SM

SM

1

SH0470

POGO-2.3OD-4.0H-SM

SM

1

SH0426

3.4OD1.75ID-1.7H-SM

1

IPD CONN (J4501) - 860-00412

3.4OD1.75ID-1.7H-SM

1

SH0428

3.4OD1.75ID-1.7H-SM

1

KBD CONN (J4500) - 860-00412

3.4OD1.75ID-1.7H-SM

1

SH0430

3.4OD1.75ID-1.7H-SM

1

3.4OD1.75ID-1.7H-SM

1

SH0427

SH0429

C

SH0431

B

ALPINE RIDGE - RIO (UB000) - 806-06077

1

SH0420

SM

SHLD-FENCE-ALPINE-X379

Shield CAN Alignment Slots 14X - 998-04440 (1.2mm X 0.4mm)

SH0449

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0454

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0459

TH-NSP

1

SH0450

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0455

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0460

TH-NSP

1

SH0451

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0461

TH-NSP

1

SH0452

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0457

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0453

TH-NSP

1

SL-1.2X0.4-1.5X0.7

SH0458

TH-NSP

1

SL-1.2X0.4-1.5X0.7

Thermal Stage Mounting Holes

Plated Through Hole - 3.15mm - APN 998-0845

SH0490

3P9R3P15

1

Plated Through Hole - 3.6mm - APN 998-03850

SH0491

4.0R3.6-NSP

1

SH0492

4.0R3.6-NSP

1

SH0493

4.0R3.6-NSP

1

USB-C CONN - RIO (JB500) - 860-00392

SH0447

3.4OD1.75ID-1.12H-SM

1

AUDIO JACK CONN (J6600) - 860-00399

SH0432

3.3X1.8R-1.4ID-1.64H-SM

1

MESA CONN (J4900) - 860-00399

SH0433

3.3X1.8R-1.4ID-1.64H-SM

1

SH0448

3.4OD1.75ID-1.12H-SM

1

B

A

SL-1.2X0.4-1.5X0.7

TOP Rubber Mount Standoffs - 12X - (860-00430)

SH0400

2.8OD1.2ID-1.435H-SM

1

2

SH0404

2.8OD1.2ID-1.435H-SM

1

2

SH0408

2.8OD1.2ID-1.435H-SM

1

2

SH0401

2.8OD1.2ID-1.435H-SM

1

2

SH0405

2.8OD1.2ID-1.435H-SM

1

2

SH0409

2.8OD1.2ID-1.435H-SM

1

2

2.8OD1.2ID-1.435H-SM

SH0402

1

2

SH0406

1

2

SH0410

1

2

SH0403

2.8OD1.2ID-1.435H-SM

1

2

SH0407

2.8OD1.2ID-1.435H-SM

1

2

SH0436

2.8OD1.2ID-1.435H-SM

1

2

Bottom Rubber Mount Standoffs - 1X - (860-00476)

SH0437

2.8OD1.2ID-3.25H-SM

1

2

LIFEBOAT CONN (J9600) - 860-00413

3.4OD1.75ID-1.57H-SM

Cowling Bosses - TOP SIDE

eDP CONN (J8500) - 860-00415

3.4OD1.75ID-0.844H-SM

BOM_COST_GROUP=MECHANICALS

SH0473

SH0474

3.4OD1.75ID-1.57H-SM

1

SH0421

1

SH0422

3.4OD1.75ID-0.844H-SM

1

SYNC_MASTER=LDUNN_J44 SYNC_DATE=01/13/2013

PAGE TITLE

1

PD Parts

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

4 OF 145

SHEET

4 OF 119

A

D

8 7 5 4 2 1

36

345678

2 1

D

105 34

34

105 34

34

OUT

DP_DDI1_ML_C_N<0> DP_DDI1_ML_C_P<0> DP_DDI1_ML_C_N<1> DP_DDI1_ML_C_P<1> DP_DDI1_ML_C_N<2> DP_DDI1_ML_C_P<2> DP_DDI1_ML_C_N<3> DP_DDI1_ML_C_P<3>

DP_DDI2_ML_C_N<0> DP_DDI2_ML_C_P<0> DP_DDI2_ML_C_N<1> DP_DDI2_ML_C_P<1> DP_DDI2_ML_C_N<2>

DP_DDI2_ML_C_N<3> DP_DDI2_ML_C_P<3>

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 1 OF 20

EDP

DDI

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48

EDP_INT_ML_N<0> EDP_INT_ML_P<0> EDP_INT_ML_N<1> EDP_INT_ML_P<1> EDP_INT_ML_N<2> EDP_INT_ML_P<2> EDP_INT_ML_N<3> EDP_INT_ML_P<3>

EDP_INT_AUX_N EDP_INT_AUX_P

NC

DP_DDI1_AUXCH_C_N DP_DDI1_AUXCH_C_PDP_DDI2_ML_C_P<2> DP_DDI2_AUXCH_C_N DP_DDI2_AUXCH_C_P

OUT

BI

D

80

34

C

PPVCCIO_S0_CPU

8 100

PLACE_NEAR=U0500.E52:15.24MM

1

R0530

24.9

1% 1/20W MF 201

2

94 17 5

34

94 28 5

104 80

IN

OUT

IN

XDP_USB_EXTD_OC_L DP_DDPB_HPD

DP_DDPC_HPD NC_PCH_GPP_E15

19

JTAG_ISP_TDO DP_INT_HPD

EDP_COMP

DISPLAY SIDEBANDS

B9

GPP_E12/USB2_OC3*

L9

GPP_E13/DDPB_HPD0

L7

GPP_E14/DDPC_HPD1

L6

GPP_E15/DDPD_HPD2

N9

GPP_E16/DDPE_HPD3

L10

GPP_E17/EDP_HPD

E52

EDP_RCOMP

GPP_E7/CPU_GP1

GPP_E8/SATALED*

GPP_E9/USB2_OC0* GPP_E10/USB2_OC1* GPP_E11/USB2_OC2*

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

A7 H1 A9 C9 D9

R12 R11 U13

XDP_PCH_OBSDATA_A3 XDP_PCH_OBSDATA_B0 XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L

EDP_BKLT_EN BKLT_PWM_MLB2TCON EDP_PANEL_PWR_EN

OUT

IN

17

79

80

28 17 5

94 17 5

104 80

C

B

12

FOR FUTURE PRODUCT PER PDG

PP1V8_SUS_PCH_VCC1P8 PP1V8_SUS_PCH_VCC1P8

NC NC NC NC NC

NC NC

AW69 AW68 AU56 AW48

C7 U12 U11

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 20 OF 20

SPARE

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVDRSVD RSVDRSVD

F6 E3 C11 B11 A11 D12 C12 F52H11 F46G46

NC NC NC NC NC NC NC NC NC

B

A

PP3V3_SUS

R0550 R0551 R0552 R0553

R0554

100K 100K 100K 100K

PP3V3_S0

10K

1 2 1 2 1 2 1 2

1 2

8 12 101

1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF

13 14 16 19 94 101

1/20W5% 201MF

XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L

JTAG_ISP_TDO

28 17 5

94 17 5

DESIGN: X502/DEV_MLB_U LAST CHANGE: Tue Apr 28 20:32:21 2015

SYNC_DATE=04/29/2015SYNC_MASTER=J130_DEV_MLB_U

PAGE TITLE

A

CPU GFX

94 28 5

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

5 OF 145

SHEET

5 OF 119

8 7 5 4 2 1

36

D

PP1V0_S0SW

8 10 17 101

67 49 48

BI

PLACE_NEAR=R0611:1MM

R0610

CPU_PROCHOT_L

PLACE_NEAR=U0500.C65:25.4MM

PP1V0_S3

8 10 14 19 101

1

1K

5%

1/20W

MF

201

2

R0611

499

1%

1/20W

MF

201

12

49 48

OUT

PLACE_NEAR=U0500.C63:254MM

1

R0612

1K

5% 1/20W MF 201

2

48 19

49

OUT

BI

CPU_CATERR_L CPU_PECI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

105

102

13

17

105 13

35 13

BI

XDP_BPM_L<0> NC_XDP_BPM_L<1> NC_XDP_BPM_L<2> NC_XDP_BPM_L<3>

MLB_RAMCFG4

IN

XDP_PCH_OBSDATA_D2

OUT

BT_PWRRST_L

OUT

BT_TIMESTAMP

OUT

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP

OPC_RCOMP

NC

D63 A54 C65 C63 A65

C55 D55 B54 C56

V1

H3 BA5 AY5

AT16 AU16

H66 H65

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

CATERR* PECI PROCHOT* THERMTRIP* SKTOCC*

BPM[0]* BPM[1]* BPM[2]* BPM[3]*

GPP_D21/SPI1_IO2 GPP_E1/SATAXPCIE1/SATAGP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

SYM 4 OF 20

CPU MISC

JTAG

PROC_TCK PROC_TDI PROC_TDO PROC_TMS

PROC_TRST*

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST*

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

345678

XDP_CPU_TCK XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TRST_L

XDP_PCH_TCK XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS XDP_PCH_TRST_L PCH_JTAGX

OUT

IN

BI

2 1

D

17

C

B

A

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CPU_CFG<4>

17 6

EDP_ENABLE

1

R0634

1K

5% 1/20W MF 201

2

R0681

49.9

1%

1/20W

MF

201

49.9

1%

1/20W

MF

201

49.9

1%

1/20W

MF

201

1

2

PLACE_NEAR=U0500.AU16:12.7MM

1

2

R0683

17

17 6

17

1

2

PLACE_NEAR=U0500.AT16:12.7MM

R0682

R0680

49.9

1%

1/20W

MF

201

BI

OUT

102

1

2

49.9

1%

1/20W

MF

201

1

2

PLACE_NEAR=U0500.H65:12.7MM

R0684

PLACE_NEAR=U0500.H66:12.7MM

CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

CPU_CFG<16> CPU_CFG<17>

CPU_CFG<18> CPU_CFG<19>

CPU_CFG_RCOMP

ITP_PMODE

NC NC

NC

NC_CPU_RSVD_BA70 NC_CPU_RSVD_BA68

NC NC

NC

E68 B67 D65 D67 E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70

E63 F63

E66 F66

E60

E8

AY2 AY1

D1 D3

K46 K45

AL25 AL27

C71 B70

F60

A52

BA70 BA68

J71 J68

F65 G65

F61 E61

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD RSVD

RSVD

RSVD_TP RSVD_TP

RSVD RSVD

VSS VSS

RSVD RSVD

(IPU)

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 19 OF 20

RESERVED

PROC_SELECT*

RSVD_TP RSVD_TP

RSVD RSVD

TP5 TP6

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD

RSVD RSVD

TP4

RSVD RSVD

RSVD

RSVD RSVD

TP1 TP2

VSS

ZVM*

RSVD_TP RSVD_TP

MSM*

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

A69 B69

AY3

D71 C70

C54 D54

AY4 BB3

AY71 AR56

AW71 AW70

AP56 C64

NC_CPU_RSVD_BB68 NC_CPU_RSVD_BB69

NC_CPU_RSVD_AK13 NC_CPU_RSVD_AK12

NC NC

NC_CPU_AU5 NC_CPU_AT5

NC NC NC NC

NC NC

NC

NC NC

NC_CPU_BB5

NC NC

NC

NC NC

NC_CPU_AY4 NC_CPU_BB3

CPU_ZVM_L

NC_CPU_RSVD_AW71 NC_CPU_RSVD_AW70

NC_CPU_MSM_L

NCNC

102

DESIGN: X502/DEV_MLB_U LAST CHANGE: Mon Apr 27 22:56:39 2015

73

OUT

102

73

OUT

BOM_COST_GROUP=CPU & CHIPSET

CONNECT TO OPC VRS

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CPU MISC/JTAG/CFG/RSVD

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

6 OF 145

SHEET

6 OF 119

C

B

SYNC_DATE=04/28/2015SYNC_MASTER=J130_DEV_MLB_U

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

103

BI

OMIT_TABLE

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQS_P<3> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31] DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47] DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

U0500

SKL-ULT-2+3E

TBD

BGA

SYM 2 OF 20

LPDDR3 NON-INTERLEAVED0

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKP[1] DDR0_CKN[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS[0]* DDR0_CS[1]*

DDR0_ODT[0] DDR0_ODT[1]

DDR0_CAA[0] DDR0_CAA[1] DDR0_CAA[2] DDR0_CAA[3] DDR0_CAA[4] DDR0_CAA[5] DDR0_CAA[6] DDR0_CAA[7] DDR0_CAA[8] DDR0_CAA[9]

DDR0_CAB[0] DDR0_CAB[1] DDR0_CAB[2] DDR0_CAB[3] DDR0_CAB[4] DDR0_CAB[5] DDR0_CAB[6] DDR0_CAB[7] DDR0_CAB[8] DDR0_CAB[9]

DDR0_DQSN[0] DDR0_DQSN[1] DDR0_DQSN[2] DDR0_DQSN[3] DDR0_DQSN[4] DDR0_DQSN[5] DDR0_DQSN[6] DDR0_DQSN[7]

DDR0_DQSP[0] DDR0_DQSP[1] DDR0_DQSP[2] DDR0_DQSP[3] DDR0_DQSP[4] DDR0_DQSP[5] DDR0_DQSP[6] DDR0_DQSP[7]

DDR0_ALERT*

DDR0_PAR

DDR0_MA[3] DDR0_MA[4]

DDR_VREF_CA

DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

AT53 AU53 AT55 AU55

BA56 BB56 AW56 AY56

AU45 AU43

AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50

AM70 AT69 AH66 AG69 BA64 AY60 AR66 AR61

AM69 AT70 AH65 AG70 AY64 BA60 AR65 AR60

AW50 AT52

BA50 BB52

AY67

AY68 BA67

AW67

MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_B_CLK_N<0> MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CKE<0> MEM_A_CKE<1> MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_CAA<0> MEM_A_CAA<1> MEM_A_CAA<2> MEM_A_CAA<3> MEM_A_CAA<4> MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<8> MEM_B_DQ<24> MEM_A_CAA<9>

MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<4> MEM_A_CAB<5> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2>

MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

NC NC

CPU_DIMM_VREFCA

CPU_DIMMA_VREFDQ CPU_DIMMB_VREFDQ

PM_MEMVTT_EN

OUT

BI

103

20

75

D

OMIT_TABLE

25 21

25 22

25 21

25 22

25 22 21

25 21

25 22

103

BI

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23>

MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9] DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15] DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31] DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

U0500

SKL-ULT-2+3E

TBD

BGA

SYM 3 OF 20

LPDDR3 NON-INTERLEAVED

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKP[1] DDR1_CKN[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS[0]* DDR1_CS[1]*

DDR1_ODT[0] DDR1_ODT[1]

DDR1_CAA[0] DDR1_CAA[1] DDR1_CAA[2] DDR1_CAA[3] DDR1_CAA[4] DDR1_CAA[5] DDR1_CAA[6] DDR1_CAA[7] DDR1_CAA[8] DDR1_CAA[9]

DDR1_CAB[0] DDR1_CAB[1] DDR1_CAB[2] DDR1_CAB[3] DDR1_CAB[4] DDR1_CAB[5] DDR1_CAB[6] DDR1_CAB[7] DDR1_CAB[8] DDR1_CAB[9]

DDR1_DQSN[0] DDR1_DQSN[1] DDR1_DQSN[2] DDR1_DQSN[3] DDR1_DQSN[4] DDR1_DQSN[5] DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[0] DDR1_DQSP[1] DDR1_DQSP[2] DDR1_DQSP[3] DDR1_DQSP[4] DDR1_DQSP[5] DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_ALERT*

DDR1_PAR

DDR1_MA[3] DDR1_MA[4]

DRAM_RESET*

DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

AP45 AN45 AP46 AN46

AN56 AP55 AN55 AP53

BB42 AY42

BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46

BA38 AY34 AT38 AT32 BA30 AY26 AR25 AR22

AY38 BA34 AR38 AR32 AY30 BA26 AR27 AR21

AN43 AP43

BB46 BA47

AT13

AR18 AT18 AU18

MEM_B_CLK_P<0>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CKE<0> MEM_B_CKE<1> MEM_B_CKE<2> MEM_B_CKE<3>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0>

NCNC

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9>

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

NCNC

NC NC

NC

CPU_DDR_RCOMP<0> CPU_DDR_RCOMP<1> CPU_DDR_RCOMP<2>

OUT

BI

103

25 23

25 24

25 23

25 24

25 24 23

25 23

25 24

C

B

A

BOM_COST_GROUP=CPU & CHIPSET

1

R0700

162

1% 1/20W MF 201

2

PLACE_NEAR=U0500.AU18:6MM

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

CPU LPDDR3 Interface

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

1

R0701

80.6

1% 1/20W MF 201

2

PLACE_NEAR=U0500.AT18:6MM

Apple Inc.

1

R0702

200

1% 1/20W MF 201

2

PLACE_NEAR=U0500.AR18:6MM

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

7 OF 145

SHEET

7 OF 119

A

8 7 5 4 2 1

36

D

C

B

A

PP1V2_S3_CPUDDR

100

PP1V2_S3_CPUDDR

100

PP1V0_S3

6 8 10 14 19 101

PP1V0_S0SW

6 8 10 17 101

PP1V2_S0SW

10 100

PP1V0_S3

10 101

PP1V0_SUS

8 12 101

PPVCCPRIMCORE_SUS_PCH

12 55 100

PP1V_S5_PCH_DCPDSW

19 12

PP1V0_SUS

12 101

PP1V0_SUSSW

12 101

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

12

PP1V_SUS_PCH_VCCAPLL_F

12

PP1V0_SUS

8 12 101

PP3V3_S5

14 101

PP1V8_S0_PCH_VCCHDA_F

12

PP3V3_SUS

13 101

PP1V0_SUSSW

12 101

PP3V3_SUS

5 8 12 101

PP1V0_SUSFUSE

78 12

PP1V0_SUSSW

12 101

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18

A22

AL23

K20 K21

AB19 AB20

P18

AF18 AF19

V20 V21

AL1

K17

L1

N15 N16 N17 P15 P16

K15 L15

V15

AB17

Y18

AD17 AD18 AJ17

AJ19

AJ16

AF20 AF21

T19 T20

AJ21

AK20

N18

OMIT_TABLE

SKL-ULT-2+3E

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VDDQC

VCCST

VCCSTG

VCCPLL_OC

VCCPLL VCCPLL

OMIT_TABLE

SKL-ULT-2+3E

VCCPRIM_1P0 VCCPRIM_1P0 VCCPRIM_1P0

VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0 VCCMPHYAON_1P0

VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0 VCCMPHYGT_1P0

VCCAMPHYPLL_1P0 VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0 VCCPRIM_1P0

VCCDSW_3P3 VCCDSW_3P3 VCCDSW_3P3

VCCHDA

VCCSPI

VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0 VCCSRAM_1P0

VCCPRIM_3P3

VCCPRIM_1P0

VCCAPLLEBB_1P0

U0500

TBD

BGA

SYM 14 OF 20

CPU POWER 3

U0500

TBD

BGA

SYM 15 OF 20

CPU POWER 4

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC VCCRTC

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

PPVCCIO_S0_CPU

PPVCCSA_S0_CPU

CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N

CPU_VCCSASENSE_N CPU_VCCSASENSE_P

PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP1V8_SUS PP3V3_SUS

PP3V3_SUS

PP1V0_SUS

PP1V8_SUS

PP3V3_SUS

PP3V0_G3H

PPDCPRTC_PCH

PP1V0_SUS

PP1V_SUS_PCH_VCCCLK2_F

PP1V0_SUS

PP1V_SUS_PCH_VCCCLK4_F

PP1V_SUS_PCH_VCCCLK5_F

PP1V0_SUS

NC_VCCPRIM_CORE_VID0 NC_VCCPRIM_CORE_VID1

PPVCCEDRAM_S0_CPU

8 100

PPVCCEDRAM_S0_CPU

100

PPVCCEDRAM_S0_CPU

100

PP1V8_SUS

100

PP1V8_SUS

100

CPU_VCCOPCSENSE_P

8

CPU_VCCOPCSENSE_N

8

PPVCCEDRAM_S0_CPU

8 100

PPVCCEDRAM_S0_CPU

100

CPU_VCCEOPIOSENSE_P

8

CPU_VCCEOPIOSENSE_N

8

5 8 100

8 55 100

OUT

13 14 15 16 101

12 101

101

12 101

14 19 100

101

5 8 12 101

8 12 101

12 100

12 101

12 14 15 100

101

12

101

12

101

OUT

75 8

67 8

19 12

19

PPVCCIO_S0_CPU

5 8 100

PPVCCSA_S0_CPU

8 55 100

PPVCCGT_S0_CPU

8 54 100

PPVCCGT_S0_CPU

8 100

PPVCCEDRAM_S0_CPU

8 100

PPVCCEDRAM_S0_CPU

8 100

PPVCC_S0_CPU

8 54 100 104

PPVCC_S0_CPU

A30

VCC

A34

VCC

A39

VCC

A44

VCC

NC

AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40 AM32 AM33 AM35 AM37 AM38

AK32

AB62

AC63 AE63

AE62 AG62

AL63 AJ62

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

G30

VCC

K32

RSVD

VCCOPC

P62

VCCOPC

V62

VCCOPC

H63

VCC_OPC_1P8

G61

VCC_OPC_1P8

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO VCCEOPIO

VCCEOPIO_SENSE VSSEOPIO_SENSE

8 54 100 104

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD

BGA

SYM 12 OF 20

CPU POWER 1

PLACE_NEAR=U0500.AM23:50.8MM

R0801

PLACE_NEAR=U0500.H20:50.8MM

R0804

PLACE_NEAR=U0500.J70:50.8MM

R0811

PLACE_NEAR=U0500.AK62:50.8MM

R0813

PLACE_NEAR=U0500.AC63:50.8MM

R0821

PLACE_NEAR=U0500.AL63:50.8MM

R0823

PLACE_NEAR=U0500.E32:50.8MM

R0825

1 2

PLACE_NEAR=U0500.AM22:50.8MM

R0802

PLACE_NEAR=U0500.H21:50.8MM

R0803

PLACE_NEAR=U0500.J69:50.8MM

R0812

PLACE_NEAR=U0500.AL61:50.8MM

R0814

PLACE_NEAR=U0500.AE63:50.8MM

R0822

PLACE_NEAR=U0500.AJ62:50.8MM

R0824

PLACE_NEAR=U0500.E33:50.8MM

R0826

G32

VCC

G33

VCC

G35

VCC

G37

VCC

G38

VCC

G40

VCC

G42

VCC

J30

VCC

J33

VCC

J37

VCC

J40

VCC

K33

VCC

K35

VCC

K37

VCC

K38

VCC

K40

VCC

K42

VCC

K43

VCC

E32

VCC_SENSE VSS_SENSE

VIDALERT*

VIDSCK

VIDSOUT

VCCSTG

CPU_VCCSENSE_P

E33

CPU_VCCSENSE_N

B63

CPU_VIDALERT_R_L

A63

CPU_VIDSCLK_R

D64

CPU_VIDSOUT_R

G20

PP1V0_S0SW

12

100

5% 1/20W MF 201

100

5% 1/20W MF 201

100

5% 2011/20W MF

100

5%

CPU_VCCIOSENSE_P

MF1/20W5% 201

CPU_VCCSASENSE_P

1/20W5% MF 201

CPU_VCCGTSENSE_P

CPU_VCCGTXSENSE_P

1/20W5% MF 201

CPU_VCCOPCSENSE_P

CPU_VCCEOPIOSENSE_P

MF 2011/20W5%

CPU_VCCSENSE_P

1/20W MF 2015%

CPU_VCCIOSENSE_N

MF1/20W 2015%

CPU_VCCSASENSE_N

MF5% 2011/20W

CPU_VCCGTSENSE_N

MF1/20W5%

201

CPU_VCCGTXSENSE_N

CPU_VCCOPCSENSE_N

201MF1/20W5%

CPU_VCCEOPIOSENSE_N

1/20W MF 2015%

CPU_VCCSENSE_N

MF1/20W 201

OUT

67 8

8 67

6 8 10

67 8

R0829

220

1 2

1%

1/20W

MF

201

17 101

1 2

R0831

1 2

5%

1/20W

MF

0201

345678

PPVCCGT_S0_CPU

8 54 100

75 8

67 8

8

67 8

75 8

67 8

8

67 8

OUT

R0830

0

CPU_VCCGTSENSE_P CPU_VCCGTSENSE_N

PP1V0_S3

1

R0827

56

1% 1/20W MF 201

2

0

5%

1/20W

MF

0201

2 1

OMIT_TABLE

SKL-ULT-2+3E

A48

VCCGT

A53

VCCGT

A58

VCCGT

A62

VCCGT

A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

1

R0828

100

1% 1/20W MF 201

2

PLACE_NEAR=U0500.B63:12.7MM

CPU_VIDALERT_L

PLACE_NEAR=U0500.A63:12.7MM

CPU_VIDSCLK

PLACE_NEAR=U0500.D64:12.7MM

CPU_VIDSOUT

BOM_COST_GROUP=CPU & CHIPSET

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

J43

VCCGT

J45

VCCGT

J46

VCCGT

J48

VCCGT

J50

VCCGT

J52

VCCGT

J53

VCCGT

J55

VCCGT

J56

VCCGT

J58

VCCGT

J60

VCCGT

K48

VCCGT

K50

VCCGT

K52

VCCGT

K53

VCCGT

K55

VCCGT

K56

VCCGT

K58

VCCGT

K60

VCCGT

L62

VCCGT

L63

VCCGT

L64

VCCGT

L65

VCCGT

L66

VCCGT

L67

VCCGT

L68

VCCGT

L69

VCCGT

L70

VCCGT

L71

VCCGT

M62

VCCGT

N63

VCCGT

N64

VCCGT

N66

VCCGT

N67

VCCGT

N69

VCCGT

J70

VCCGT_SENSE

J69 AL61

VSSGT_SENSE

6 8 10 14 19 101

67

IN

67

OUT

BI

67

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

U0500

TBD

BGA

SYM 13 OF 20

CPU POWER 2

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGTX_SENSE VSSGTX_SENSE

CPU & PCH Power

Apple Inc.

R

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62

PPVCCGT_S0_CPU

CPU_VCCGTXSENSE_P CPU_VCCGTXSENSE_N

DRAWING NUMBER SIZE

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

8 OF 145

SHEET

8 OF 119

8

SYNC_DATE=03/14/2016SYNC_MASTER=J79_JSHAO

9.0.0

D

8 100

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

NC_CPU_NCTFVSS_A5

102

NC_CPU_NCTFVSS_A70

102

A5 A67 A70 AA2 AA4

AA65 AA68 AB15 AB16 AB18 AB21

AB8

AD13 AD16 AD19 AD20 AD21 AD62

AD8

AE64 AE65 AE66 AE67 AE68 AE69

AF1

AF10 AF15 AF17

AF2 AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH6

AH63 AH64 AH67 AJ15 AJ18 AJ20

AJ4

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8 AL2

AL28 AL32 AL35 AL38

AL4

AL45 AL48 AL52 AL55 AL58 AL64

OMIT_TABLE

U0500

SKL-ULT-2+3E

SYM 16 OF 20

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

TBD BGA

GND1

VSSVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

NC_CPU_NCTFVSS_AV1

102

NC_CPU_NCTFVSS_B71

102

NC_CPU_NCTFVSS_BA1

102

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8 AY66

B10

B14

B18

B22

B30

B34

B39

B44

B48

B53

B58

B62

B66

B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68 BA45

OMIT_TABLE

U0500

SKL-ULT-2+3E

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SYM 17 OF 20

TBD

BGA

GND2

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

NC_CPU_NCTFVSS_BA71

NC_CPU_NCTFVSS_BB70 NC_CPU_NCTFVSS_C1

102

F8 G10 G22 G43 G45 G48

G5 G52 G55 G58

G6 G60 G63 G66 H15 H18 H71 J11 J13 J25 J28 J32 J35 J38 J42

J8 K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD

BGA

SYM 18 OF 20

GND 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

D

C

B

A

PAGE TITLE

CPU & PCH Grounds

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=05/12/2015SYNC_MASTER=J79_ALFRED

051-00515

9.0.0

dvt-fab09-0

9 OF 145

9 OF 119

A

D

345678

2 1

D

PPVCC_S0_CPU

100

1

C1000

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100I

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1010

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1001

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100J

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1011

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1002

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100K

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1012

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1003

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100L

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1013

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1004

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100M

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1014

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1005

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100N

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1015

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1006

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100O

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1016

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1007

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100P

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1017

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1008

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100Q

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1018

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1009

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100R

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1019

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C100A

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100S

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100B

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100T

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100C

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100U

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100D

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100V

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100E

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100W

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100F

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100X

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100G

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100Y

1UF

20%

6.3V

2

X6S-CERM 0201

1

C100H

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V2_S3_CPUDDR

100

PP1V2_S3_CPUDDR

100

1

C1050

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1060

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1051

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1061

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1062

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1063

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1052

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1064

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1053

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1065

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1054

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1066

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1055

1UF

20%

6.3V

2

X6S-CERM 0201

D

C

1

C1020

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10G0

220UF

20% 2V

23

ELEC SM-COMBO

1

C1021

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1022

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10G1

220UF

20% 2V

23

ELEC SM-COMBO

1

C1023

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1024

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10H1

220UF

20% 2V

23

ELEC SM-COMBO

1

C1025

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1026

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10G3

220UF

20% 2V

23

ELEC SM-COMBO

1

C1027

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1028

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1029

20UF

20%

2.5V

2

X6S-CERM 0402-1

PPVCCIO_S0_CPU

100

1

C1070

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1071

1UF

20%

6.3V

2

X6S-CERM 0201

Primary Backside

1

C1080

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1090

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1081

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1091

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1092

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1093

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1082

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1094

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1083

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1095

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1084

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1085

1UF

20%

6.3V

2

X6S-CERM 0201

C

B

PPVCCEDRAM_S0_CPU

100

1

C10D0

2

PPVCCEDRAM_S0_CPU

100

1

C10E0

2

20UF

20%

2.5V X6S-CERM 0402-1

20UF

20%

2.5V X6S-CERM 0402-1

1

C10E1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10D1

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D2

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D3

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D4

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D5

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10D6

1UF

20%

6.3V

2

X6S-CERM 0201

PPVCCSA_S0_CPU

100

1

C10A0

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10B0

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C0

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A1

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10B1

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C1

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A2

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C10B2

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C2

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A3

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C10B3

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C3

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A4

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10B4

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C4

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A5

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10B5

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C10C5

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C10A6

1UF

20%

6.3V

2

X6S-CERM 0201

B

A

PP1V0_S3

8 101

1

C10F0

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V2_S0SW

8 100

1

C10F1

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V0_S3

6 8 14 19 101

1

C10F2

1UF

20%

6.3V

2

X6S-CERM 0201

PP1V0_S0SW

6 8 17 101

1

C10F3

1UF

20%

6.3V

2

X6S-CERM 0201

1

C10H0

220UF

20% 2V

23

ELEC SM-COMBO

SYNC_MASTER=J79_JSHAO SYNC_DATE=08/28/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

CPU Core Decoupling

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

10 OF 145

SHEET

10 OF 119

A

D

8 7 5 4 2 1

36

PPVCCGT_S0_CPU

100

345678

2 1

D

1

C1100

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110E

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1110

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1101

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110F

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1111

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1102

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110G

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1112

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1103

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110H

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1113

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1104

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110I

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1114

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1105

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110J

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1115

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1106

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110K

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1116

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1107

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110L

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1117

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1108

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110M

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1118

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1109

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110N

1UF

20%

6.3V

2

X6S-CERM 0201

NOSTUFF

1

C1119

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C110A

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110O

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110B

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110P

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110C

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110Q

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110D

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110R

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110S

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110T

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110U

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110V

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110W

1UF

20%

6.3V

2

X6S-CERM 0201

1

C110X

1UF

20%

6.3V

2

X6S-CERM 0201

D

C

NOSTUFF

1

C1120

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1121

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1122

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1161

220UF

20%

2.0V

23

POLY-TANT D15T-D1L-COMBO

NOSTUFF

1

C1123

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1124

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1162

220UF

20% 2V

23

ELEC SM-COMBO

1

C1125

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1126

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1163

220UF

20% 2V

23

ELEC SM-COMBO

1

C1127

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1128

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

23

C1164

220UF

20% 2V ELEC SM-COMBO

1

C1129

20UF

20%

2.5V

2

X6S-CERM 0402-1

C

B

PPVCCGT_S0_CPU

100

1

C1170

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1180

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1171

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1181

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1172

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1182

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1173

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1183

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1174

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1184

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1175

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1185

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1176

20UF

20%

2.5V

2

X6S-CERM 0402-1

NOSTUFF

1

C1186

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1177

20UF

20%

2.5V

2

X6S-CERM 0402-1

1

C1187

20UF

20%

2.5V

2

X6S-CERM 0402-1

B

A

1

C1190

220UF

20% 2V

23

ELEC SM-COMBO

8 7 5 4 2 1

1

C1191

220UF

20% 2V

23

ELEC SM-COMBO

SYNC_MASTER=J79_JSHAO SYNC_DATE=08/28/2015

PAGE TITLE

CPU GT Decoupling

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

11 OF 145

11 OF 119

A

D

345678

2 1

D

78 8

PP1V0_SUSFUSE

BYPASS=U0500.AK20::10MM

PP1V0_SUS

8 101

BYPASS=U0500.AB19::10MM

PP1V0_SUS

8 101

BYPASS=U0500.K17::3MM

1

C1208

1000PF

10% 25V

2

X7R 0201

1

C1200

1000PF

10% 25V

2

X7R 0201

1

C1201

1UF

20%

6.3V

2

X6S-CERM 0201

PP3V3_SUS

5 8 101

PP3V3_SUS

8 101

BYPASS=U0500.T16::3MM

BYPASS=U0500.AK17::3MM

1

C1220

1000PF

10% 25V

2

X7R 0201

1

C1221

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1222

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U0500.AK17::3MM

101

PP1V0_SUSSW

1

C1204

1UF

20%

6.3V

2

X6S-CERM 0201

FILTER PLACEHOLDERS ONLY

OMIT_TABLE

L1250

2.2UH-240MA-0.221OHM

1 2

0603

CRITICAL NOSTUFF

1

C1250

47UF

20%

6.3V

2

POLY-TANT 0805

BYPASS=U0500.K15::3MM

PCH SIDERAIL SIDE

PP1V_SUSSW_PCH_VCCAMPHYPLL_F PP1V_SUSSW_PCH_VCCAMPHYPLL_F

MAKE_BASE=TRUE

8

D

19

C

PP1V0_SUSSW

8 101

PP1V0_SUSSW

8 101

PP1V0_SUSSW

8 101

BYPASS=U0500.N15::3MM

BYPASS=U0500.AF20::10MM

BYPASS=U0500.N18::3MM

1

C1202

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1205

1000PF

10% 25V

2

X7R 0201

1

C1206

1UF

20%

6.3V

2

X6S-CERM 0201

CRITICAL NOSTUFF

1

C1203

47UF

20%

6.3V

2

POLY-TANT 0805

8 101

BYPASS=U0500.N15::10MM

8 101

8 14 15 100

PP3V3_SUS

BYPASS=U0500.AG15::3MM

PP3V3_SUS

BYPASS=U0500.V19::10MM

PP3V3_SUS

BYPASS=U0500.Y16::10MM

PP3V0_G3H

BYPASS=U0500.AK19::3MM

1

C1223

1000PF

10% 25V

2

X7R 0201

1

C1224

1000PF

10% 25V

2

X7R 0201

1

C1225

1000PF

10% 25V

2

X7R 0201

1

C1227

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1228

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U0500.AK19::3MM

101

PP1V0_SUS

OMIT_TABLE

L1252

2.2UH-240MA-0.221OHM

1 2

0603

CRITICAL NOSTUFF

1

C1252

47UF

20%

6.3V

2

POLY-TANT 0805

OMIT_TABLE

L1253

2.2UH-240MA-0.221OHM

1 2

0603

CRITICAL NOSTUFF

1

C1253

47UF

20%

6.3V

2

POLY-TANT 0805

OMIT_TABLE

L1254

2.2UH-240MA-0.221OHM

1 2

0603

CRITICAL NOSTUFF

1

C1254

47UF

20%

6.3V

2

POLY-TANT 0805

MAKE_BASE=TRUE

PP1V_SUS_PCH_VCCCLK5_F PP1V_SUS_PCH_VCCCLK5_F

PP1V_SUS_PCH_VCCCLK4_F PP1V_SUS_PCH_VCCCLK4_F

PP1V_SUS_PCH_VCCCLK2_F PP1V_SUS_PCH_VCCCLK2_F

8

19

8

19

8

19

C

B

19 8

PPVCCPRIMCORE_SUS_PCH

8 55 100

BYPASS=U0500.AF18::10MM

PPDCPRTC_PCH

100

1

C1210

1000PF

10% 25V

2

X7R 0201

1

C1231

0.1UF

10% 10V

2

X5R-CERM 0201

PP1V8_S0

1

C1264

12PF

5% 25V

2

NP0-C0G 0201

1

C1265

2.9PF

+/-0.05PF 25V

2

C0G-CERM 0201

8 100

19 8

R1260

0

1 2

5%

1/20W

MF

0201

PP1V8_SUS

BYPASS=U0500.AA1::10MM

PP1V_S5_PCH_DCPDSW

BYPASS=U0500.AL1::3MM

10% 25V X7R

0201

1

2

C1226

1000PF

C1260

2.9PF

+/-0.05PF

25V

C0G-CERM

0201

1

C1230

1UF

20%

6.3V

2

X6S-CERM 0201

1

C1232

1UF

20%

6.3V

2BYPASS=U0500.BB10::3MM

X6S-CERM 0201

1

2

PP1V8_S0_PCH_VCCHDA_F

MAKE_BASE=TRUE

BYPASS=U0500.AJ19::10MM

8

19

100

PP1V8_SUS

NOSTUFF

R1251

0

1 2

5%

1/20W

MF

0201

BYPASS=U0500.U11::10MM

L1250,L1252,L1253,L12544113S0022 RES,MF,1A MAX,0OHM,5%,0603

NOSTUFF

1

C1251

1UF

20%

6.3V

2

X6S-CERM 0201

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

FOR FUTURE PRODUCT PER PDG

PP1V8_SUS_PCH_VCC1P8 PP1V8_SUS_PCH_VCC1P8

PP1V8_SUS_PCH_VCC1P8

MAKE_BASE=TRUE

B

5

19

A

BYPASS=U0500.AJ19::10MM

R1261

0

PP1V0_SUS

15 101

1

C1267

2.9PF

+/-0.05PF 25V

2

C0G-CERM 0201

1 2

5%

1/20W

MF

0201

10% 25V X7R

0201

1

2

C1262

2.9PF

+/-0.05PF

C0G-CERM

C1261

1000PF

BYPASS=U0500.V15::10MM

25V

0201

1

2

BYPASS=U0500.V15::10MM

8 7 5 4 2 1

PP1V_SUS_PCH_VCCAPLL_F PP1V_SUS_PCH_VCCAPLL_F

MAKE_BASE=TRUE

8

19

BOM_COST_GROUP=CPU & CHIPSET

36

PAGE TITLE

PCH Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

12 OF 145

12 OF 119

D

A

SYNC_DATE=03/14/2016SYNC_MASTER=J79_JSHAO

345678

2 1

D

60

105 60

60

OUT

IN

OUT

HDA_SYNC

OUT

HDA_BIT_CLK

OUT

HDA_SDOUT HDA_SDIN0

HDA_RST_L

PLACE_NEAR=U0500.BA22:10mm

R1300

PLACE_NEAR=U0500.AY22:10mm

R1301

PLACE_NEAR=U0500.BB22:10mm

R1302

PLACE_NEAR=U0500.AW22:10mm

R1303

33

1 2

33

1 2

33

1 2

33

1 2

5% 1/20W

5%

MF 201

1/20W

HDA_SYNC_R

19

MF

HDA_BIT_CLK_R HDA_SDOUT_R

19 18

HDA_RST_R_L

19

MF 2015% 1/20W

MF5% 1/20W

201

28 13

94 28

17

19

13

19

49

XDP_PCH_OBSDATA_C0

OUT

CKPLUS_WAIVE=CLK_DATA_CON

PCH_DDPB_CTRLDATA

IN

JTAG_TBT_X_TMS

OUT

JTAG_TBT_T_TMS

BI

PCH_DDPC_CTRLDATA

IN

MLB_RAMCFG0

13

MLB_RAMCFG1

13

NC_PCH_BSSB_CLK

IN

NC_PCH_BSSB_DATA

IN

PCH_STRP_TOPBLK_SWP_L

IN

NC

NC NC

BA22 AY22 BB22 BA21 AY21 AW22

D8 AY20 AW20

L12 L13

N7

N8

U1

U2

P4

P1

AW5

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD

HDA_RST*/I2S1_SCLK GPP_D17/DMIC_CLK1 I2S1_SFRM I2S1_TXD

GPP_E19/DDPB_CTRLDATA GPP_E18/DDPB_CTRLCLK GPP_E20/DDPC_CTRLCLK GPP_E21/DDPC_CTRLDATA

GPP_D13/ISH_UART0_RXD/

SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/

SML0BCLK/I2C4B_SCL

GPP_D11 GPP_D12

GPP_B14/SPKR

(BSSB_CLK) (BSSB_DATA_IN)

(STRAP)

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 7 OF 20

(1.8V)

(STRAP)

GPP_A17/SD_PWR_EN*/ISH_GP7

(1.8V)

SDIO/SDXC

GPP_F18/EMMC_DATA5HDA_SDI1/I2S1_RXD GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F23

GPP_G0/SD_CMD

GPP_G1/SD_DATA0

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F17/EMMC_DATA4

AN2 AM4 AM1 AM2 AM3 AF13 AB11 AB13

BA9 BB9

AB7

AN1

ALL GPP_F* PINS ARE 1.8V ONLY!

SD_RCOMP

R1370

200

1%

1/20W

MF

201

PCH_SOC_DFU_STATUS

SOC_PANIC_L

SOC_S2R_ACK_L

SOC_PCH_DBELL_L

DEBUGUART_SEL_SOC

SSD_PWR_EN_L TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

NC_CAMERA_RESET_L

CAMERA_PWR_EN

PCH_SOC_WDOG

1

2

37 19

38 19

19 38

OUT

IN

D

19

104 91

28 13

19

37

C

59

59 17

59

59 13

19 13

48 13

OUT

BI

OUT

IN

SPI_CLK_R SPI_MISO SPI_MOSI_R SPI_IO<2> SPI_IO<3> SPI_CS0_R_L NC_SPI_CS1_L

102

NC_SPI_CS2_L

102

ALS_SOC_UART_R2D PD_LCD_PSR_EN PD_SSD_UART_CTS_L MLB_RAMCFG2

13

MLB_RAMCFG3

13

ALS_SOC_UART_D2R

PU_PCH_RCIN_L

13

LPC_SERIRQ

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0*

AU2

SPI0_CS1*

AU1

SPI0_CS2*

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS*

AD4

GPP_C23/UART2_CTS*

U3

GPP_D15/ISH_UART0_RTS*

U4

GPP_D16/ISH_UART0_CTS*/

SML0BALERT*

AD1

GPP_C20/UART2_RXD

G3

NC NC NC

AW13 AY11 AW11

CL_CLK

G2

CL_DATA

G1

CL_RST*

GPP_A0/RCIN* GPP_A6/SERIRQ

IO1

IO0

SYM 5 OF 20

SPI-FLASH

SMBUS,SMLINK

(STRAP)

SPI-TOUCH

LPC

C LINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

(STRAP)

GPP_B23/SML1ALERT*/PCHHOT*

GPP_A5/LFRAME*/ESPI_CS*

GPP_A14/SUS_STAT*/ESPI_RESET*

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C2/SMBALERT*

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT*

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN*

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9

PLACE_NEAR=U0500.AB7:12.7MM

SMBUS_PCH_CLK SMBUS_PCH_DATA NC_PCH_STRP_TLSCONF

SML_PCH_0_CLK SML_PCH_0_DATA NC_PCH_STRP_ESPI

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA NC_PCH_STRP_BSSB_SEL_GPIO

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3> LPC_FRAME_R_L LPC_PWRDWN_L

LPC_CLK24M_SMC_R NC_PCH_CLKOUT_LPC1 LPC_CLKRUN_L

OUT

19

OUT

19

OUT

19

R1320 R1321 R1322 R1323 R1325

OUT

R1327

19

BI

51

48

51

33 33 33 33 33

22

48 13

1 2 1 2 1 2 1 2 1 2

1 2

C

MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W

LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L

LPC_CLK24M_SMC

MF 2015% 1/20W

LPC_AD<0>

BI

OUT

48

105 48

B

A

PP3V3_SUS

R1344 R1343 R1342 R1341 R1340 R1350 R1351 R1352 R1353 R1354 R1355 R1356 R1357 R1358 R1359

10K

1K

10K 100K 100K

10K 100K

47K

10K

10K 100K 100K 100K

PP3V3_S0

PP3V3_SUS

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

5% 1/20W 201MF

5 14 16 19 94 101

8 14 15 16 101

8 101

MF 2015% 1/20W

1/20W5% MF

MF1/20W 2015%

1/20W5% 201MF

MF1/20W 2015%

MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W MF 2015% 1/20W

201

2015% 1/20W MF 2015% MF1/20W

2015% 1/20W MF

PU_PCH_RCIN_L

SPI_CS0_R_L LPC_SERIRQ BT_PWRRST_L BT_TIMESTAMP

LPC_CLKRUN_L

CAMERA_PWR_EN

ALS_SOC_UART_D2R

ALS_SOC_UART_R2D

PD_SSD_UART_CTS_L

JTAG_TBT_X_TMS

JTAG_TBT_T_TMS

TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

PD_LCD_PSR_EN

13

59 13

48 13

105 6

35 6

48 13

19

13 19

13 28

13 28 94

28 13

13 19

MEMORY CONFIGURATION STRAPS.

PCH INTERNAL PULL-UPS ARE TO 3.3V.

MLB_RAMCFG0

13

MLB_RAMCFG1

13

MLB_RAMCFG2

13

MLB_RAMCFG3

13

MLB_RAMCFG4

6

RAMCFG4_L

1

R1334

1K

5% 1/20W MF 201

2

BOM GROUP BOM OPTIONS

RAMCFG_SLOT RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG1_L,RAMCFG0_L

RAMCFG3_L

1

R1333

1K

5% 1/20W MF 201

2

RAMCFG2_L

1

R1332

1K

5% 1/20W MF 201

2

RAMCFG1_L

1

R1331

1K

5% 1/20W MF 201

2

RAMCFG0_L

1

R1330

1K

5% 1/20W MF 201

2

PAGE TITLE

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM_COST_GROUP=CPU & CHIPSET

DESIGN: X502/MLB LAST CHANGE: Tue Feb 2 13:18:21 2016

PCH Audio/LPC/SPI/SMBus

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

13 OF 145

SHEET

13 OF 119

9.0.0

D

B

A

SYNC_DATE=02/22/2016SYNC_MASTER=J130_MLB

8 7 5 4 2 1

36

PCH Reset Button

345678

2 1

D

48 17

74

48

IN

8 13 15 16 101

5 13 14 16 19 94 101

PP1V0_S3

6 8 10 19 101

PP3V3_S0

R1405

PM_SYSRST_L

CPU_VCCST_PWRGD

VCCST_PWRGD 1V TOLERANT

PM_DSW_PWRGD

R1403

PP3V3_SUS

1

1K

5%

1/20W

MF

201

2

1

100K

5%

1/20W

MF

201

2

NOSTUFF

1

R1407

2.2K

5% 1/20W MF 201

2

1

R1408

2.2K

5% 1/20W MF 201

2

R1406

60.4

1 2

201 MF

PLACE_NEAR=U0500.B65:38mm

50

NO STUFF

50

1%

1/20W

OUT

R1400

0

5%

1/20W

MF

0201

IN

2

1

104 35 19

77 48 17

104 73 48

74

18 14

48 14

OUT

IN

PLT_RST_L

PM_RSMRST_L

TP_CPU_PWRGD CPU_VCCST_PWRGD_R

PM_PCH_SYS_PWROK PM_PCH_PWROK

SMC_PCH_SUSWARN_L SMC_PCH_SUSACK_L

PCIE_WAKE_L SMC_WAKE_SCI_L NC_PCH_LANPHYPC

102

NC_PCH_GPD7

102

AN10

B5

AY17

A68 B65

B6 BA20 BB20

AR13 AP11

BB15 AM15 AW17 AT15

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 11 OF 20

SYSTEM POWER MANAGEMENT

GPP_B13/PLTRST* SYS_RESET* RSMRST*

PROCPWRGD VCCST_PWRGD

SYS_PWROK PCH_PWROK DSW_PWROK

GPP_A13/SUSWARN*/SUSPWRDNACK GPP_A15/SUSACK*

WAKE* GPD2/LAN_WAKE* GPD11/LANPHYPC GPD7/RSVD

(1V ONLY)

GPP_B12/SLP_S0*

GPD4/SLP_S3* GPD5/SLP_S4*

GPD10/SLP_S5*

SLP_SUS* SLP_LAN*

GPD9/SLP_WLAN*

GPD6/SLP_A*

GPD3/PWRBTN*

GPD1/ACPRESENT

GPD0/BATLOW*

GPP_A11/PME*

INTRUDER*

GPP_B11/EXT_PWR_GATE*

GPP_B2/VRALERT*

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

NC

PM_SLP_S0_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L

PM_SLP_SUS_L

NC_PCH_SLP_WLAN_L NC_PCH_SLP_A_L

PM_PWRBTN_L SSD_SR_EN_L PM_BATLOW_L

NC_PCH_PME_L PCH_INTRUDER_L

PCH_HSIO_PWR_EN BT_LOW_PWR_L

OUT

102

OUT

102

OUT

IN

78

D

104 74 48 19 14

104 92 80 77 74 73 48 26 19 14

104 77 74 48 43 19 14

104 77 48 19 14

104 77 74 14

PP3V0_G3H

50 14

102 14

94 48 28 14

35 14

1

R1401

1M

5% 1/20W MF 201

2

8 12 15 100

C

R1400 kept for debug purposes.

C

B

A

R1446 R1445 R1444 R1443 R1442 R1441 R1440 R1450 R1451 R1452 R1453

R1454 R1455 R1456 R1457 R1458

PP1V8_SUS

PP3V3_S5 PP3V3_S4 PP3V3_S0

100K 100K 100K 100K 100K

10K

100K

1K 10K 10K

100K

100K 100K 100K 220K 100K

NOTE: PM_SLP_S0_L HAS INTERNAL PULL-UP BEFORE RSMRST_L IS RELEASED. THIS CAUSES A VOLTAGE DIVIDER WITH THE PULL-DOWN HERE. THE SIGNAL IS DRIVEN HI AFTER RSMRST_L IS RELEASED.

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2

5% 1/20W 201MF

5% 201 5% MF 5% 201MF

5% 201MF

8 19 100

8 101

101

5 13 14 16 19 94 101

1/20W5% 201MF

MF1/20W5%

MF1/20W5% 201

MF 1/20W5% MF 1/20W5% MF 1/20W MF 1/20W 201 1/20W

1/20W5% 201MF 1/20W 1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF

201

2015% MF1/20W 2011/20W5% 201 201

SOC_SWD_CLK PCH_SWD_IO PCH_SWD_MUX_SEL PCH_SOC_DBELL SSD_BOOT_L BT_LOW_PWR_L SSD_SR_EN_L PM_PWRBTN_L PM_BATLOW_L PCIE_WAKE_L SMC_WAKE_SCI_L

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L PM_SLP_SUS_L

14 19 42

42 14

14 19 37

104 91 14

35 14

102 14

14 50

18 14

48 14

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

SYM 9 OF 20

A36

NC NC NC NC NC NC NC NC

NC NC

94 48 28 14

104 77 48 19 14

104 77 74 48 43 19 14

104 92 80 77 74 73 48 26 19 14

104 74 48 19 14

104 77 74 14

NC NC NC NC NC NC

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27 AT1

CSI2_DP11

CSI-2

EMMC

(1.8V)

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_F12/EMMC_CMD GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1

GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D0/SPI1_CS*

GPP_F7/I2C3_SCL GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

GPP_F6/I2C3_SDA

EMMC_RCOMP

C37 D37 C32 D32 C29 D29 B26 A26

E13 M1

AH12 AF11 AF12 AD11 AD12 AP4 AP2 AP1

AP3 AN3 AH11

NC NC NC NC NC NC NC NC

CSI2_COMP

NC_PCH_GPP_D0

ALL GPP_F* PINS ARE 1.8V ONLY!

NC_PCH_GPP_F8 NC_PCH_GPP_F9

NC_PCH_GPP_F10

PCH_BT_ROM_BOOT

PCH_SWD_MUX_SEL

PCH_SOC_DBELL

PCH_SOC_FORCE_DFU

NC_UPC_I2C_INT_L

EMMC_RCOMP

200

1%

1/20W

MF

201

1

2

R1481

PLACE_NEAR=U0500.AT1:12.7MM

100

1%

1/20W

MF

201

1

2

102

OUT

102

35 19

OUT

BI

OUT

14 19 37

OUT

IN

104 91 14

42 19 14

42 14

38

19

R1480

PLACE_NEAR=U0500.E13:12.7MM

SSD_BOOT_L

SOC_SWD_CLK

PCH_SWD_IO

BOM_COST_GROUP=CPU & CHIPSET

DESIGN: X502/MLB LAST CHANGE: Tue May 3 17:45:28 2016

PAGE TITLE

PCH Power Management

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

14 OF 145

SHEET

14 OF 119

9.0.0

D

B

A

SYNC_DATE=05/04/2016SYNC_MASTER=J130_MLB

8 7 5 4 2 1

36

D

C

PCIe Port Assignments:

SSD LANE 0

SSD LANE 1

SSD LANE 2

SSD LANE 3

Thunderbolt X lane 0

Thunderbolt X lane 1

Thunderbolt X lane 2

Thunderbolt X lane 3

AirPort

CAMERA

PLACE_NEAR=U0500.F5:12.7mm

100

1%

1/20W

MF

201

1

2

R1504

Thunderbolt T lane 0

Thunderbolt T lane 1

105 91

105 81

105 84

105 81

105 84

105 81

105 84

105 28

28

35

102

17

48 15

105 94

94

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD BGA

PCIE_SSD_D2R_N<0> USB3_EXTA_D2R_N PCIE_SSD_D2R_P<0> PCIE_SSD_R2D_C_N<0> PCIE_SSD_R2D_C_P<0>

PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1> PCIE_SSD_R2D_C_N<1> PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2> PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_C_P<2>

PCIE_SSD_D2R_N<3> PCIE_SSD_D2R_P<3> PCIE_SSD_R2D_C_N<3> PCIE_SSD_R2D_C_P<3>

PCIE_TBT_X_D2R_N<0> PCIE_TBT_X_D2R_P<0> PCIE_TBT_X_R2D_C_N<0> PCIE_TBT_X_R2D_C_P<0>

PCIE_TBT_X_D2R_N<1> PCIE_TBT_X_D2R_P<1> PCIE_TBT_X_R2D_C_N<1> PCIE_TBT_X_R2D_C_P<1>

PCIE_TBT_X_D2R_N<2> PCIE_TBT_X_D2R_P<2> PCIE_TBT_X_R2D_C_N<2> PCIE_TBT_X_R2D_C_P<2>

PCIE_TBT_X_D2R_N<3> PCIE_TBT_X_D2R_P<3> PCIE_TBT_X_R2D_C_N<3> PCIE_TBT_X_R2D_C_P<3>

PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

NC_PCIE_CAMERA_D2R_N

NC_PCIE_CAMERA_D2R_P NC_PCIE_CAMERA_R2D_C_N NC_PCIE_CAMERA_R2D_C_P

PCH_PCIE_RCOMP_N PCH_PCIE_RCOMP_P

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

SMC_RUNTIME_SCI_L

PCIE_TBT_T_D2R_N<0> PCIE_TBT_T_D2R_P<0> PCIE_TBT_T_R2D_C_N<0> PCIE_TBT_T_R2D_C_P<0> PCIE_TBT_T_D2R_N<1> PCIE_TBT_T_D2R_P<1> PCIE_TBT_T_R2D_C_N<1> PCIE_TBT_T_R2D_C_P<1>

H13 G13 B17 A17

G11 F11 D16 C16

H16 G16 D17 C17

G15 F15 B19 A19

F16 E16 C19 D19

G18 F18 D20 C20

F20 E20 B21 A21

G21 F21 D21 C21

E22 E23 B23 A23

F25 E25 D23 C23

F5 E5

D56 D61

BB11

E28 E27 D24 C24 E30 F30 A25 B25

PCIE1_RXP/USB3_5_RXP PCIE1_TXN/USB3_5_TXN PCIE1_TXP/USB3_5_TXP

PCIE2_RXN/USB3_6_RXN PCIE2_RXP/USB3_6_RXP PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP

PCIE3_RXN PCIE3_RXP PCIE3_TXN PCIE3_TXP

PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP

PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP

PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP

PCIE7_RXN/SATA0_RXN PCIE7_RXP/SATA0_RXP PCIE7_TXN/SATA0_TXN PCIE7_TXP/SATA0_TXP

PCIE8_RXN/SATA1A_RXN PCIE8_RXP/SATA1A_RXP PCIE8_TXN/SATA1A_TXN PCIE8_TXP/SATA1A_TXP

PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

PCIE_RCOMPN PCIE_RCOMPP

PROC_PRDY* PROC_PREQ* GPP_A7/PIRQA*

PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP PCIE11_TXN/SATA1B_TXN PCIE11_TXP/SATA1B_TXP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_TXN PCIE12_TXP/SATA2_TXP

SYM 8 OF 20

SSIC/USB3

USB2

PCIE/USB3/SATA

USB3_1_RXNPCIE1_RXN/USB3_5_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_2_RXN/SSIC_RXN USB3_2_RXP/SSIC_RXP USB3_2_TXN/SSIC_TXN USB3_2_TXP/SSIC_TXP

USB3_3_RXN USB3_3_RXP USB3_3_TXN USB3_3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E3/CPU_GP0 GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_D22/SPI1_IO3 GPP_D23/I2S_MCLK

GPP_E0/SATAXPCIE0/SATAGP0

GPP_D18/DMIC_DATA1

GPP_D19/DMIC_CLK0

GPP_D20/DMIC_DATA0

GPP_E2/SATAXPCIE2/SATAGP2

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A6 J1 J2 J3

V2 J5 H2

C8 H5 D7

G4

USB3_EXTA_D2R_P USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P

NC_USB3_EXTB_D2R_N NC_USB3_EXTB_D2R_P NC_USB3_EXTB_R2D_C_N NC_USB3_EXTB_R2D_C_P

TP_USB3_03_D2RN TP_USB3_03_D2RP TP_USB3_03_R2DN TP_USB3_03_R2DP

NC_USB3_04_D2RN NC_USB3_04_D2RP NC_USB3_04_R2DN NC_USB3_04_R2DP

NC_USB_EXTA_N NC_USB_EXTA_P

NC_USB_EXTB_N NC_USB_EXTB_P

USB_CAMERA_DFR_N USB_CAMERA_DFR_P

TP_USB_TESTERN TP_USB_TESTERP

NC_USB2_05N NC_USB2_05P

USB_UPC_PCH_XA_N USB_UPC_PCH_XA_P

USB_UPC_PCH_TA_N USB_UPC_PCH_TA_P

USB_UPC_PCH_XB_N USB_UPC_PCH_XB_P

USB_UPC_PCH_TB_N USB_UPC_PCH_TB_P

NC_USB2_10N NC_USB2_10P

PCH_USB2_COMP

PCH_USB2_VBUSSENSE

XDP_PCH_OBSFN_C1 XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TDI

XDP_PCH_OBSDATA_A2

XDP_PCH_OBSDATA_D0 XDP_PCH_OBSDATA_D1

XDP_PCH_OBSDATA_C1 XDP_PCH_OBSDATA_C2 XDP_PCH_OBSDATA_C3

XDP_PCH_OBSDATA_D3

NC_SPKR_ID0

OUT

104

19

104

19

28

94

28

94

19

IN

BI

345678

28

102

105 38

17

19

CKPLUS_WAIVE=CLK_DATA_CON

17

CKPLUS_WAIVE=CLK_DATA_CON

17

EXT A (SS,DCI)

EXT B (SS)

EXT A (LS/FS/HS)

EXT B (LS/FS/HS)

GROUNDED PER SKYLAKE MOW 2015WW10.

1

R1503

1K

5% 1/20W MF 201

2

PLACE_NEAR=U0500.AG4:12.7MM

2 1

1

R1501

113

1% 1/20W MF 201

2

PLACE_NEAR=U0500.AB6:12.7MM

D

C

B

A

R1550

100K

PP3V3_SUS

1 2

8 13 14 16 101

1/20W5% 201

ANY CLKREQ CAN MAP TO ANY CLK. ANY CLKREQ OR CLK CAN MAP TO ANY PCIE PORT. UNUSED CLKREQS AND CLKS SHOULD BE DISABLED. PER SKYLAKE PDG, SKYLAKE PCH EDS.

SMC_RUNTIME_SCI_L

MF

OMIT_TABLE

B

U0500

SKL-ULT-2+3E

TBD BGA

SYM 10 OF 20

CLOCK SIGNALS

91

OUT

91

OUT

19

IN

105 26

105 92

105 35

48 15

19

102

19

OUT

IN

OUT

IN

OUT

IN

OUT

IN

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P SSD_CLKREQ_L_R

PCIE_CLK100M_TBT_X_N PCIE_CLK100M_TBT_X_P TBT_X_CLKREQ_L_R

PCIE_CLK100M_TBT_T_N PCIE_CLK100M_TBT_T_P TBT_T_CLKREQ_L_R

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P AP_CLKREQ_L_R

NC_PCIE_CLK100M_CAMERA_N NC_PCIE_CLK100M_CAMERA_P NC_PCH_CLKREQ4_L

NC_PCIE_CLK100M5N

19

NC_PCIE_CLK100M5P

19

NC_PCH_CLKREQ5_L

19

D42 C42

AR10

B42 A42 AT7

D41 C41 AT8

D40 C40

AT10

B40 A40 AU8

E40 E38 AU7

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0*

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1*

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2*

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3*

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4*

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5*

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST*

RTCRST*

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

NC_ITPXDP_CLK100M_N NC_ITPXDP_CLK100M_P

PM_CLK32K_SUSCLK_R

PCH_CLK24M_XTALIN NC_PCH_CLK24M_XTALOUT

PCH_DIFFCLK_BIASREF

SYSCLK_CLK32K_PCH NC_PCH_CLK32K_RTCX2

PCH_SRTCRST_L RTC_RESET_L

19

OUT

IN

49

19

PP1V0_SUS

PLACE_NEAR=U0500.E42:2.54mm

1

R1520

2.7K

1% 1/20W MF 201

2

20K

1%

1/20W

MF

201

1UF

20%

6.3V 0201

1

2

1

2

R1530

C1530

X6S-CERM

BOM_COST_GROUP=CPU & CHIPSET

12 101

1

R1531

20K

1% 1/20W MF 201

2

1

C1531

1UF

20%

6.3V

2

X6S-CERM 0201

PP3V0_G3H

DESIGN: X502/MLB LAST CHANGE: Thu Jun 18 20:05:18 2015

SYNC_MASTER=J130_MLB SYNC_DATE=06/23/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

8 12 14 100

PCH PCIE/USB/CLKS

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

SHEET

A

D

9.0.0

15 OF 145

15 OF 119

8 7 5 4 2 1

36

345678

2 1

D

C

19 16

43 16

35 16

18 16

28 16

94 16

19 16

104 91 19

94 28 16

PU_AUD_SPI_CS_L

OUT

PD_AUD_SPI_CLK

OUT

PD_AUD_SPI_MISO

IN

PU_AUD_SPI_MOSI

OUT

TPAD_SPI_CS_L

OUT

TPAD_SPI_CLK

OUT

TPAD_SPI_MISO

IN

TPAD_SPI_MOSI

OUT

PCH_BT_UART_D2R

IN

PCH_BT_UART_R2D

OUT

PCH_BT_UART_RTS_L

OUT

PCH_BT_UART_CTS_L

IN

AP_S0IX_WAKE_SEL

OUT

AP_S0IX_WAKE_L

IN

TBT_X_CIO_PLUG_EVENT_L

IN

TBT_T_CIO_PLUG_EVENT_L

IN

PCH_SSD_SOC_UART_D2R

IN

PCH_SSD_SOC_UART_R2D

OUT

PU_SOC_UART_RTS_L

OUT

PD_SOC_UART_CTS_L

IN

SSD_RESET_L

IN

TBT_POC_RESET

OUT

BT_I2S_CLK_1V8

19

BT_I2S_SYNC_1V8

19

BT_I2S_R2D_1V8

19

BT_I2S_D2R_1V8

19

AN8 AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

W4

AB3

U7 U6 U8 U9

AC1 AC2

AC3 AB4

N11 N12

AK6 AK7

AK9

AK10

ALL GPP_F* PINS ARE 1.8V ONLY!

OMIT_TABLE

U0500

SKL-ULT-2+3E

TBD

LPSS ISH

GPP_B15/GSPI0_CS* GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS* GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS* GPP_C11/UART0_CTS*

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS*/ISH_UART1_RTS* GPP_C15/UART1_CTS*/ISH_UART1_CTS*

GPP_E22 GPP_E23

GPP_F0/I2S2_SCLK GPP_F1/I2S2_SFRM

GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

(STRAP)

(1.8V)

BGA

SYM 6 OF 20

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_D1/SPI1_CLK

GPP_D2/SPI1_MISO

GPP_D3/SPI1_MOSI GPP_D4/FLASHTRIG

(1.8V)

SX_EXIT_HOLDOFF*/GPP_A12/

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_G6/SD_CLK

GPP_D9

GPP_D10

GPP_G7/SD_WP

GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD*

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

BM_BUSY*/ISH_GP6

M4 N3 N1 N2

M2 M3

J4 B7

AH9 AH10

W8 P2 P3 W7

AB12 W12 W11 W10

AY8 BA8 BB7 BA7 AY7 AW7 AP13

MLB_BOARD_ID0 MLB_BOARD_ID1 MLB_BOARD_ID2 MLB_BOARD_ID3

NC_PCH_GPP_D1

NC_SPKR_ID1

NC_PCH_GPP_D3 NC_PCH_GPP_D4

16

102

19

102

NC_I2C_UPC_SDA NC_I2C_UPC_SCL

AP_RESET_L

MLB_BOARD_ID4

16

NC_MLB_DEV_L

PD_AP_DEV_WAKE

TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN TBT_X_PCI_RESET_L TBT_T_PCI_RESET_L

SPIROM_USE_MLB

LCD_IRQ_L DDI1_MUX_SEL DDI2_MUX_SEL

TPAD_SPI_IF_EN TPAD_SPI_INT_L

AUD_PWR_EN

OUT

IN

BI

19

94

19

28

D

36 35 19

19 16

C

59 16

104 80 16

43 16

61 16

B

A

R1643 R1642 R1641 R1640

R1650 R1652

R1653 R1654 R1655 R1656

R1657 R1658 R1659 R1660 R1674 R1676 R1673 R1675

R1661 R1662 R1663 R1664

R1665 R1666 R1667

R1669

R1668 R1671 R1672

47K 47K 47K 47K

100K

47K 47K 47K

1K

47K 47K

47K 150K 100K

10K 100K 100K

47K

100K 100K 100K

100K

100K 100K 100K

PP3V3_S0

PP3V3_SUS

1 2 1 2 1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

1 2 1 2 1 2

1 2

1 2 1 2 1 2

5 13 14 19 94 101

8 13 14 15 101

1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF

5% 201MF

1/20W

5% 1/20W

1/20W5% 201 1/20W 201MF

5% 5% 1/20W MF 201

1/20W5% 201

5% 2011/20W 5% 201MF1/20W

5% MF 2011/20W

5% 1/20W

1/20W5% MF 201 1/20W 201MF5%

5% 1/20W 201MF

1/20W5% 201MF 1/20W5% 201MF

1/20W5% MF 1/20W5% 201MF 1/20W5% 201MF

1/20W5% 201

1/20W

5% 201MF

1/20W5% 201MF 1/20W5% 201MF

MF

MF5% 2011/20W

MF 201

MF

201MF

2011/20W5% MF

201MF1/20W5%

2015% 1/20W MF

201

NOSTUFF NOSTUFF

NOSTUFF

PCH_SSD_SOC_UART_D2R PCH_SSD_SOC_UART_R2D PU_SOC_UART_RTS_L PD_SOC_UART_CTS_L

SPIROM_USE_MLB

AUD_PWR_EN PU_AUD_SPI_CS_L PD_AUD_SPI_CLK PD_AUD_SPI_MISO PU_AUD_SPI_MOSI

TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI

TPAD_SPI_INT_L

TPAD_SPI_IF_EN

PCH_BT_UART_D2R PCH_BT_UART_R2D PCH_BT_UART_RTS_L PCH_BT_UART_CTS_L

AP_S0IX_WAKE_SEL AP_S0IX_WAKE_L PD_AP_DEV_WAKE

LCD_IRQ_L

DRIVEN PUSH PULL FROM SWITCHED RAIL.

TBT_X_CIO_PLUG_EVENT_L TBT_T_CIO_PLUG_EVENT_L

TBT_POC_RESET

16 19

59 16

61 16

16 19

43 16

35 16

18 16

16 19

16 28

16 94

MLB ID STRAPS.

PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V.

16

104 80 16

94 28 16

MLB_BOARD_ID0 MLB_BOARD_ID1 MLB_BOARD_ID2 MLB_BOARD_ID3 MLB_BOARD_ID4

OMIT_TABLE

1

R1694

1K

5% 1/20W MF 201

2

PART# DESCRIPTIONQTY

OMIT_TABLE

1

R1693

1K

5% 1/20W MF 201

2

RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:32 R1691,R1690117S0006

RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:4R1692117S0006 1

RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:73 R1692,R1691,R1690117S0006

OMIT_TABLE

1

R1692

1K

5% 1/20W MF 201

2

OMIT_TABLE

1

R1691

1K

5% 1/20W MF 201

2

BOM OPTIONREFERENCE DESIGNATOR(S)

BOARD_ID:00 RES,MF,1/20W/1K OHM,5,0201,SMD117S0006

BOARD_ID:1R16901117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:2RES,MF,1/20W/1K OHM,5,0201,SMD R1691117S0006 1

BOARD_ID:52 R1692,R1690117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

R1692,R1691 BOARD_ID:62117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:8117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD1 R1693

BOARD_ID:9R1693,R16902117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:10R1693,R16912117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:11R1693,R1691,R16903117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD

BOARD_ID:16R1694117S0006 1 RES,MF,1/20W/1K OHM,5,0201,SMD

OMIT_TABLE

1

R1690

1K

5% 1/20W MF 201

2

TABLE_5_HEAD

TABLE_5_ITEM

CODE

<11111>

<11110>

<11101>

<11100>

<11011>

<11010>

<11001>

<11000>

<10111>

<10110>

<10101>

<10100>

<01111>

SYNC_MASTER=J130_MLB SYNC_DATE=12/08/2015

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

DESIGN: X502/MLB LAST CHANGE: Wed Oct 28 12:50:22 2015

PCH SPI/UART/GPIO

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

16 OF 145

SHEET

16 OF 119

B

A

D

8 7 5 4 2 1

36

D

C

77 48 14

50 48

17 6

345678

2 1

Primary / Merged (CPU/PCH) Micro2-XDP

PP1V0_SUS

101

NOTE: This is not the standard XDP pinout.

PLACE_NEAR=U0500.D67:2.54MM

XDP:YES

1K

5%

1/20W

MF

201

1

NO_XNET_CONNECTION

2

NC NC

XDP_PIN_1

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

HOOK0 HOOK1

VCC_OBS_AB

HOOK2 HOOK3

SDA

SCL TCK1 TCK0

IN

OUT

PM_RSMRST_L

PM_PWRBTN_L

XDP_CPU_TCK

XDP:YES

PLACE_NEAR=U0500.AY17:18MM

R1800

1K

1 2

XDP:YES

1 2

R1802

PLACE_NEAR=U0500.BA15:2.54MM

10

5% 1/20W

MF 2015% 1/20W

MF 201

15

17 6

PULL CFG<3> LOW

R1801

WHEN XDP PRESENT

XDP_PRESENT_CPU

BI

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

6

IN

XDP_CPU_PREQ_L XDP_CPU_PRDY_L

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

XDP_PM_RSMRST_L XDP_CPU_PWRBTN_L

XDP_PCH_TCK

OUT

XDP:YES

0

6

PCH_JTAGX

OUT

R1835

1 2

5% MF1/20W

PLACE_NEAR=J1800.58:28MM

0201

XDP:YES

10% 10V

0201

1

2

C1804

0.1UF

X5R-CERM

PLACE_NEAR=J1800.42:28MM

XDP:YES

C1800

0.1UF

10% 10V

X5R-CERM

0201

PLACE_NEAR=J1800.44:28MM

1

2

XDP_CONN:YES

J1800

DF40RC-60DP-0.4V

M-ST-SM1

62

20

61

12 34 56 78 910 1112 1314 1516 1718 19 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940 4142 4344 4546 4748 4950 5152 5354 5556 5758 5960

6364

518S0847

PLACE_NEAR=J1800.43:28MM

Use with 921-0133 Adapter Flex to support chipset debug.

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7

TDO TRSTn TDI TMS XDP_PRESENT#

XDP:YES

1

C1801

0.1UF

10% 10V

2

X5R-CERM 0201

PLACE_NEAR=J1800.47:28MM

NC NC

1

2

CPU_CFG<17> CPU_CFG<16>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<10> CPU_CFG<11>

CPU_CFG<19> CPU_CFG<18>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<14> CPU_CFG<15>

ITP_PMODE XDP_DBRESET_L

XDP:YES

C1806

0.1UF

10% 10V X5R-CERM 0201

IN

6

1

R1830

1K

5% 1/20W MF 201

2

ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.

R1821

PLACE_NEAR=J1800.51:2.54MM

R1822

PLACE_NEAR=J1800.53:2.54MM

R1823

PLACE_NEAR=J1800.55:2.54MM

R1824

PLACE_NEAR=J1800.57:2.54MM

XDP_PCH_TDO

17 6

XDP_PCH_TDI

17 6

XDP_PCH_TMS

17 6

XDP_CPU_TDO

17 6

XDP_CPU_TCK

17 6

XDP_PCH_TCK

17 6

PLACE_NEAR=U0500.E8:2.54MM

6

IN

0

1 2

XDP:YES

1 2

5% 1/20W

XDP:YES

0

1 2

XDP:YES

1 2

1/20W5% MF00201

R1890

R1891

R1892

R1810

R1813

R1897

XDP:YES

R1806

0

1 2

5%

1/20W

MF

0201

XDP_CPU_TDO

MF

0201

XDP_CPU_TRST_L

MF5% 1/20W

0201

XDP_CPU_TDI

MF5% 1/20W

0201

XDP_CPU_TMS

PM_SYSRST_L

XDP:YES

PP1V0_S0SW

6 8 10 101

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

XDP:YES

51

2 1

NOSTUFF

51

2 1

IN

OUT

MF 201PLACE_NEAR=U0500.A56:28MM 5% 1/20W

MF 201PLACE_NEAR=U0500.D59:28MM 5% 1/20W

D

MF 201PLACE_NEAR=U0500.C59:28MM 5% 1/20W

MF 201PLACE_NEAR=U0500.A61:28MM 5% 1/20W

MF 201PLACE_NEAR=U0500.B61:28MM 5% 1/20W

MF 201PLACE_NEAR=U0500.C61:28MM 5% 1/20W

BI

48 14

C

17 6

6

B

A

15

13

15

28 5

94 5

XDP_PCH_TDO XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS

OUT

IN

17 6

6

17 6

PCH XDP Signals

PP3V3_SUS

These signals do not connect to the Primary (Merged) XDP connector in this architecture. The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation. They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.

PCH/XDP Signals

Non-XDP Signals

17 77 101

XDP:YES

6

VCC

U1830

IN

BI

5

BI

5

BI

6

BI

OUT

XDP_JTAG_ISP_TCK

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_PCH_OBSDATA_A2

XDP_PCH_OBSDATA_A3

XDP_PCH_OBSDATA_B0

XDP_PCH_OBSDATA_C0

XDP_PCH_OBSDATA_C1

XDP_PCH_OBSDATA_C2

XDP_PCH_OBSDATA_C3

XDP_PCH_OBSDATA_D0

XDP_PCH_OBSDATA_D1

XDP_PCH_OBSDATA_D2

XDP_PCH_OBSDATA_D3

XDP_PCH_OBSFN_C1

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUEMAKE_BASE=TRUE

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP1870 TP1871 TP1872 TP1873 TP1874 TP1875 TP1876 TP1877 TP1878 TP1879 TP1880 TP1881

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTD_OC_L

MAKE_BASE=TRUEMAKE_BASE=TRUE

Unused GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

OUT

IN

94

105

PP3V3_SUS

17 77 101

XDP:YES

R1850

100K

5%

1/20W

MF

201

NC NC

1

2

NEED TO CONNECT TO VCCST, *STG POWER LOGIC

74AUP1G07GF

SOT891

2

1

GND

3

(OD)

NCNC

4

YA

5

BOM_COST_GROUP=DEBUG

XDP:YES

1

C1830

0.1UF

10% 10V

2

X5R-CERM 0201

SPI_IO2_STRAP_L

NOSTUFF

1

R1832

0

5% 1/20W MF 0201

2

XDP_PRESENT_L

XDP:YES

R1831

1.5K

1 2

5%

1/20W

MF

201

PLACE_NEAR=U0500.AW2:10MM

NO_XNET_CONNECTION=1

PULL STRAP LOW WHEN XDP IS PLUGGED IN. (UNDOCUMENTED STRAP FUNCTION)

77

OUT

SPI_IO<2>

DESIGN: X502/MLB LAST CHANGE: Thu Oct 22 19:53:09 2015

PAGE TITLE

CPU/PCH Merged XDP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

OUT

(STRAP TO PCH)

59 13

DRAWING NUMBER SIZE

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

18 OF 145

SHEET

17 OF 119

D

B

A

SYNC_DATE=12/08/2015SYNC_MASTER=J130_MLB

8 7 5 4 2 1

36

345678

2 1

D

CRITICAL

C1907

9.5PF

1 2

+/-0.1PF

50V

CER-C0G

0201

System 32kHz / 12MHz / 24MHz Clock Generator

SYSCLK_CLK24M_X2

R1900

0

1 2

5%

1/20W

MF

0201

100 35 19

101 19

19

48

IN

PP3V3_G3H

100

PP1V8_S4 PP1V0_SUS NC_PPVIOE_CAMCLK PD_PPVIOE_SSDCLK SMC_CLK12M_EN

SYSCLK_CLK24M_X2_R

12

VIO_32K_B

2

VIOE_24M_A

5

VIOE_24M_B

15

VIOE_24M_C

8

OE_12M

19

X2

20

X1

1

VDD

U1900

SLG3AP3444

STQFN

32.768K_A

32.768K_B

GND

11

VRTC

24M_A 24M_B 24M_C

VOUT

12M

BYPASS=U1900.11:18:5MM

1

C1901

1.0UF

20%

6.3V

2

X5R 0201-1

PP2V9_SYSCLK

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=2.9V

17

10 13

3 6 16

7

SYSCLK_CLK32K_PCH SYSCLK_CLK32K_CAMERA_BT_AP_SOC

SYSCLK_CLK24M_PCH NC_SYSCLK_CLK24M_CAMERA SYSCLK_CLK24M_SSD

SYSCLK_CLK12M_SMC

BYPASS=U1900.17:18:5MM

1

C1900

2.2UF

20%

6.3V

2

X5R-CERM 0201

19

81

48

100

IN

PP1V8_S0

PCH ME Disable Strap

SPI_DESCRIPTOR_OVERRIDE_L

1

G

S

2

Q1930

DMP31D0UFB4

DFN1006H4-3

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. ***** Circuit does not support HDA voltage >3.3V.

D

3

SPI_DESCRIPTOR_OVERRIDE

48

IN

1

R1930

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

PCH IPD = 9-50k

OUT

D

19 13

C

2 4

CRITICAL

C1908

9.5PF

1 2

+/-0.1PF

50V

CER-C0G

0201

CRITICAL

Y1900

1 3

2.5X2.0MM-SM

NO STUFF

1

R1901

1M

5%

24MHZ-10PPM-8PF-40OHM

1/20W MF 201

2

SYSCLK_CLK24M_X1

NOTE: 30 PPM or better required for SKL PCH

14

4

9

18

C

B

35

PP3V3_S5

101

1

R1910

100K

5% 1/20W MF 201

2

PCIe Wake Muxing

C1910

0.1UF

10%

6.3V

CERM-X5R

0201

AP_PCIE_WAKE_L

AP_S0IX_WAKE_SEL

CRITICAL

1

U1910

PI5A3157B

6

2

SEL

1

VCC

3 4

A

DFN

1

0

VER 1

B1

GND

B0

2

5

SEL OUTPUT

L PCIE_WAKE_L (B0) H AP_S0IX_WAKE_L (B1)

AP_S0IX_WAKE_L

PCIE_WAKE_L

IN

OUT

OUTIN

16

B

14

A

PAGE TITLE

Chipset Support 1

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=09/09/2015SYNC_MASTER=J79_GREG

051-00515

9.0.0

dvt-fab09-0

19 OF 145

18 OF 119

A

D

345678

2 1

D

C

B

A

Platform Reset Connections NO TEST

104 35 14

IN

PLT_RST_L

PCIE CLKREQS

PP3V3_S0

R2080

R2081

R2082

R2083

47K

1 2

ENABLE DDPB DDPC INTERFACES

PP3V3_S0

2.2K

R2050

12

R2051

12

201 1/20WMF 5%

T208 PCH GPIO PUs/PDs & ALIASES

R2054 R2055 R2056

R2053

100K

Desense Decoupling Caps on HDA Lines

HDA_SYNC_R HDA_SDOUT_R

NOSTUFF

1

C2020

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

Power State Debug LEDs

(For development only)

PP3V3_S5

101

DBGLED

R2090

20K

5%

1/20W

MF

201

DBGLED_S5 DBGLED_S4

DBGLED

A

D2090

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S5_ON

104 77 48 14

104 77 74 48 43 14

104 92 80 77 74 73 48 26 14

104 74 48 14

5 13 14 16 19 94 101

PCH_DDPB_CTRLDATA

PCH_DDPC_CTRLDATA

1/20W201 5%MF

PP1V8_SUS

1 2

13 18 13

1

2

A

K

DBGLED_S4_D

IN

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L PM_SLP_S0_L

Unbuffered

5 13 14 16 19 94 101

SSD_CLKREQ_L

MF

TBT_X_CLKREQ_L

1/20W 201

1/20W MF5% 201

1/20W MF5%

8 14 100

5% MF

5% 201

1/20W MF

NOSTUFF

1

C2050

100PF

5% 25V

2

C0G 0201

NOSTUFF

1

C2021

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

MF5%

TBT_T_CLKREQ_L

AP_CLKREQ_L

MF1/20W5% 201

DBGLED

R2091

DBGLED

100K

20K

1/20W

12

2015% 1/20W

201

2011/20W

SOC_PCH_DBELL_L

14 37

14 42

2015%

1

5% MF

201

2

D2091

GRN-90MCD-5MA-2.85V

0402

PLACE_SIDE=BOTTOM SILK_PART=STBY_ON

DBGLED

Q2090

6

DMN5L06VK-7

SOT563

VER 3

2

G S

D

1

R2000

1/20W MF 2015%

R2001

5% 1/20W

R2002

R2003

1/20W MF5%

R2004

13

201MF

MF5% 1/20W 201

201

2015% MF1/20W

R2084

5%

1/20W 201MF

R2085

5%

R2086

5% MF1/20W

R2087

TBT_X_PCI_RESET_L

26 28

TBT_T_PCI_RESET_L

92 94

AP_RESET_L

SSD_RESET_L

SMC_LRESET_L

1 2

MF1/20W 201

1 2

201

1 2

2015% MF1/20W

SOC_PANIC_L

SOC_S2R_ACK_L

PCH_SOC_DBELL

SOC_SWD_CLK

PCH_SOC_DFU_STATUS

SOC_TO_STOCKHOLM_EN

HDA_RST_R_L

NOSTUFF

1

C2022

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

DBGLED

R2092

1/20W

DBGLED_S3 DBGLED_S0

DBGLED

A

D2092

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S3_ON

DBGLED_S3_D

DBGLED

Q2090

DMN5L06VK-7

SOT563

VER 3

5

1K

1

20K

5% MF

201

2

G S

GREENCLK VIOEs

15

NO_TEST=1

MAKE_BASE=TRUE

OUT

SSD_CLKREQ_L_R

15

TBT_X_CLKREQ_L_R

15

TBT_T_CLKREQ_L_R

15

AP_CLKREQ_L_R

15

TBT_X_PCI_RESET_L

MAKE_BASE=TRUE

TBT_T_PCI_RESET_L

36 35 16

104 91 16

48

MAKE_BASE=TRUE

SSD_CLKREQ_L_R

MAKE_BASE=TRUE

TBT_X_CLKREQ_L_R

MAKE_BASE=TRUE

TBT_T_CLKREQ_L_R

MAKE_BASE=TRUE

AP_CLKREQ_L_R

OUT

16

104 88 87 86 85 84 82 81

MAKE_BASE=TRUE

18

IN

SYSCLK_CLK32K_PCH

MAKE_BASE=TRUE

NO_TEST=1

CATERR PU

PP1V0_S3

R2059

51

WIFI GPIO PD

R2058

38 13

MAKE_BASE=TRUE

SOC_PCH_DBELL_L

MAKE_BASE=TRUE

PCH_SOC_DBELL

MAKE_BASE=TRUE

SOC_SWD_CLK

37 13

38 37

13

DBGLED_S0I3

DBGLED

A

D2093

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S0I3_ON

DBGLED_S0I3_D

3

D

4

DMN5L06VK-7

100K

DBGLED

R2093

DBGLED

Q2091

SOT563

VER 3

2

G S

6 8 10 14 101

1 2

1

20K

5%

1/20W

MF

201

2

D

SYSCLK_CLK24M_PCH

CPU_CATERR_L

1/20W5%

18

IN

201MF

48 6

MAKE_BASE=TRUE

SYSCLK_CLK32K_CAMERA_BT_AP_SOC

PCH_BT_ROM_BOOT

1/20W5% 201

MF

35 14

35

18

IN

SYSCLK_CLK32K_CAMERA_BT_AP_SOC

IN

SYSCLK_CLK32K_OSC_OUT

BT_I2S_SYNC_1V8

16 35

IN OUT

16 35

BI BI

BT_I2S_R2D_1V8

BT_I2S_D2R_1V8

OUT IN

BT_I2S_CLK_1V8

DBGLED

20K

5%

1/20W

MF

201

1

2

PCH_SSD_SOC_UART_D2R

16

PCH_SSD_SOC_UART_R2D

16

R2095

DBGLED

A

D2095

GRN-90MCD-5MA-2.85V

0402

K

PLACE_SIDE=BOTTOM SILK_PART=S0_ON

DBGLED_S0_D

DBGLED

Q2091

6

1

DMN5L06VK-7

SOT563

VER 3

5

G S

3

D

DEBUGUART_SEL_SOC

13

4

MAKE_BASE=TRUE

NC_PPVIOE_CAMCLK

MAKE_BASE=TRUE

PP1V8_SSD_COLD

NOSTUFF

R2010

0

1 2

5%

1/20W

MF

0201

NC_PPVIOE_CAMCLK

PP1V0_SUS

18 101

PP1V8_S4

18 35 100

PD_PPVIOE_SSDCLK

NOSTUFF

1

C2002

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U1900.15:18:5MM

GREENCLK CLOCK OUT ALIASES

SYSCLK_CLK32K_PCH

NC_PCH_CLK32K_RTCX2

NOSTUFF

R2044

0

1 2

5%

1/20W

MF

0201

100 106

MAKE_BASE=TRUE

BT_I2S_SYNC_1V8

MAKE_BASE=TRUE

BT_I2S_R2D_1V8

MAKE_BASE=TRUE

BT_I2S_CLK_1V8

PP3V3_S0

101

PP1V8_S0

100

MAKE_BASE=TRUE

PCH_SSD_SOC_UART_D2R PCH_SSD_SOC_UART_R2D

MAKE_BASE=TRUE

PCH_CLK:GRNCLK

PP1V8_S0

R2066

100K

PLACE_NEAR=U1900.3:5MM

5%

1/20W

MF

201

NC_PCH_CLK32K_RTCX2

R2024

0

1 2

5%

1/20W

MF

0201

NOSTUFF

PCH_CLK24M_XTALIN

R2042

0

1 2

5%

1/20W

MF

0201

SYSCLK_CLK32K_WIFIBT

R2043

0

1 2

5%

1/20W

MF

0201

SOC_PMU_CLK_32K

x100 I2S Level Translator

1

C2010

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

VL VCC

U2010

NLSX5014MU_G

12

2

3

4

5

EN

IOLV[1]

IOLV[2]

IOLV[3]

IOLV[4]

UQFN

GND

6

BT/SSD DEBUG UART MUX

1

C2060

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

Y+

2

Y-

1

2

10

PI3USB102EZLE

R2067

5% 1/20W

R2068

9

VCC

CRITICAL

U2060

TQFN

GND

3

0201MF

02015% MF1/20W

18

18 19

1

C2001

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U1900.12:18:5MM

PP3V3_S0

C2011

0.1UF

100K

1/20W

M+ M-

D+ D-

OE*SEL

CERM-X5R

10

9

8

7

1

5%

MF

201

2

5 4

7 6

8

11

IOVCC[1]

IOVCC[2]

IOVCC[3]

IOVCC[4]

R2060

1

C2000

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U1900.02:18:5MM

OUT

IN

OUT

1

10%

6.3V 2

0201

BT_I2S_SYNC

BT_I2S_R2D

BT_I2S_D2RBT_I2S_D2R_1V8

BT_I2S_CLK

1

R2061

100K

5% 1/20W MF 201

2

SSD_DBG_UART_D2R SSD_DBG_UART_R2D_R

SOC_DBG_UART_D2R SOC_DBG_UART_R2D

NO STUFF

0

1 2

0

1 2

NO STUFF

15

35

Voltage Props

VOLTAGE=1.0V

12 15

IN IN

12

IN

12

IN

12 8

IN

12

IN

12

IN

12

IN

12

IN

12 8

IN

VOLTAGE=1.0V

PP1V_SUS_PCH_VCCCLK4_F

VOLTAGE=1.0V

PP1V_SUS_PCH_VCCCLK5_F

VOLTAGE=1.0V

PP1V_S5_PCH_DCPDSW

VOLTAGE=1.0V

PP1V_SUS_PCH_VCCAPLL_F

VOLTAGE=1.0V

PP1V_SUSSW_PCH_VCCAMPHYPLL_F

VOLTAGE=1.8V

PP1V8_SUS_PCH_VCC1P8

VOLTAGE=1.8V

PP1V8_S0_PCH_VCCHDA_F

VOLTAGE=3.0V

PPDCPRTC_PCH

Unused GPIOs with PUs/PDs

16

13

16

IN

OUT

IN

PD_AP_DEV_WAKE

PU_AUD_SPI_CS_L PD_AUD_SPI_CLK PD_AUD_SPI_MISO PU_AUD_SPI_MOSI PD_LCD_PSR_EN PD_SSD_UART_CTS_L PU_SOC_UART_RTS_L PD_SOC_UART_CTS_L

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

SIGNAL ALIASES

PD_PPVIOE_SSDCLK

18 19

13

ALS_SOC_UART_D2R

13

ALS_SOC_UART_R2D

13

41 37

NC_PCH_CLKREQ4_L

15

NC_PCIE_CLK100M5N

15

NC_PCIE_CLK100M5P

15

NC_PCH_CLKREQ5_L

101

35 16

BIBI

R2062

100K

1/20W

201

5%

MF

1

2

1

R2063

100K

5% 1/20W MF 201

2

88

42

13

104 88 84

15

NC_SPKR_ID1

16

NC_PCH_CLK24M_XTALOUT

15

NC_PCH_GPP_E15

5

NC_PCH_BSSB_CLK

13

NC_PCH_BSSB_DATA

13

NC_ITPXDP_CLK100M_N

15

NC_ITPXDP_CLK100M_P

15

NC_UPC_I2C_INT_L

14

NC_SPKR_ID0

15

NC_USB3_04_D2RN

15

NC_USB3_04_D2RP

15

NC_USB3_04_R2DN

15

NC_USB3_04_R2DP

15

NC_I2C_UPC_SDA

16

NC_I2C_UPC_SCL

16

NC_MLB_DEV_L

16

NC_SYSCLK_CLK24M_CAMERA

18

NC_PCH_STRP_TLSCONF

13

NC_PCH_STRP_ESPI

13

NC_PCH_STRP_BSSB_SEL_GPIO

NC_PCH_CLKOUT_LPC1

13

NC_VCCPRIM_CORE_VID0

8

NC_VCCPRIM_CORE_VID1

8

NC_CAMERA_RESET_L

13

SYNC_MASTER=J79_GREG SYNC_DATE=07/05/2016

PAGE TITLE

CAMERA_PWR_EN

NC SIGNAL ALIASES

Chipset Support 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

IN

15

IN

15

IN

PD_AP_DEV_WAKE

PU_AUD_SPI_CS_L PD_AUD_SPI_CLK PD_AUD_SPI_MISO PU_AUD_SPI_MOSI

PD_LCD_PSR_EN PD_SSD_UART_CTS_L PU_SOC_UART_RTS_L PD_SOC_UART_CTS_L

MAKE_BASE=TRUE

PD_PPVIOE_SSDCLK

MAKE_BASE=TRUE

ALS_SOC_UART_D2R

MAKE_BASE=TRUE

ALS_SOC_UART_R2D

MAKE_BASE=TRUE

NC_PCH_CLKREQ4_L

MAKE_BASE=TRUE

NC_PCIE_CLK100M5N

MAKE_BASE=TRUE

NC_PCIE_CLK100M5P

MAKE_BASE=TRUE

NC_PCH_CLKREQ5_L

MAKE_BASE=TRUE

NC_SPKR_ID1

MAKE_BASE=TRUE

NC_PCH_CLK24M_XTALOUT

MAKE_BASE=TRUE

NC_PCH_GPP_E15

MAKE_BASE=TRUE

NC_PCH_BSSB_CLK

MAKE_BASE=TRUE

NC_PCH_BSSB_DATA

MAKE_BASE=TRUE

NC_ITPXDP_CLK100M_N

MAKE_BASE=TRUE

NC_ITPXDP_CLK100M_P

MAKE_BASE=TRUE

NC_USB3_04_D2RN

MAKE_BASE=TRUE

NC_USB3_04_D2RP

MAKE_BASE=TRUE

NC_USB3_04_R2DN

MAKE_BASE=TRUE

NC_USB3_04_R2DP

MAKE_BASE=TRUE

NC_SYSCLK_CLK24M_CAMERA

MAKE_BASE=TRUE

NC_PCH_STRP_TLSCONF

MAKE_BASE=TRUE

NC_PCH_STRP_ESPI

MAKE_BASE=TRUE

NC_PCH_STRP_BSSB_SEL_GPIO

MAKE_BASE=TRUE

NC_PCH_CLKOUT_LPC1

MAKE_BASE=TRUE

NC_VCCPRIM_CORE_VID0

MAKE_BASE=TRUE

NC_VCCPRIM_CORE_VID1

MAKE_BASE=TRUE

NC_CAMERA_RESET_L

NC_USB2_10N

NO_TEST=1

NC_USB2_10P

NO_TEST=1

NC_USB2_05N

NO_TEST=1

NC_USB2_05PPP1V_SUS_PCH_VCCCLK2_F

NO_TEST=1

CAMERA_PWR_EN

NO_TEST=1

NC_UPC_I2C_INT_L

NO_TEST=1

NC_SPKR_ID0

NO_TEST=1

NC_I2C_UPC_SDA

NO_TEST=1

NC_I2C_UPC_SCL

NO_TEST=1

NC_MLB_DEV_L

NO_TEST=1

DRAWING NUMBER SIZE

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

20 OF 145

SHEET

19 OF 119

13

42

9.0.0

D

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

7

IN

7

IN

7

IN

NOTE: CPU has single output for VREFCA. VREFCA. Connected to 4 DRAMs.

CPU_DIMMA_VREFDQ

CPU_DIMMB_VREFDQ

CPU_DIMM_VREFCA

CPU-Based Margining

VRef Dividers

R2223

10

1 2

1%

1/20W

MF

201

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_A_RC

R2243

10

1 2

1%

1/20W

MF

201

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFDQ_B_RC

R2263

5.1

1 2

1%

1/20W

MF

0201

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM 0201

MEM_VREFCA_RC

PLACE_NEAR=R2221.2:1mm

8.2K

1%

1/20W

MF

201

1

2

R2222

R2220

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=R2241.2:1mm

8.2K

1%

1/20W

MF

201

1

2

R2242

R2240

24.9

1 2

1%

1/20W

MF

201

PLACE_NEAR=R2261.2:1mm

8.2K

1%

1/20W

MF

201

1

2

R2262

R2260

24.9

1 2

1%

1/20W

MF

201

PP1V2_S3

1

R2221

8.2K

1% 1/20W MF 201

2

PP0V6_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

R2241

8.2K

1% 1/20W MF 201

2

PP0V6_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

R2261

8.2K

1% 1/20W MF 201

2

PP0V6_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

D

100

C

100

B

A

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

LPDDR3 VREF Margining

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

22 OF 145

20 OF 119

A

D

LPDDR3 CHANNEL A (0-31)

345678

2 1

D

C

B

R2300

243

1%

1/20W

MF

201

U2300

LPDDR3-1600-32GB

EDFB232A1MA

25 7

25 22 7

IN

MEM_A_CAA<0> MEM_A_CAA<1> MEM_A_CAA<2> MEM_A_CAA<3> MEM_A_CAA<4> MEM_A_CAA<5> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<8> MEM_A_CAA<9>

MEM_A_CKE<0> MEM_A_CKE<1>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<0> MEM_A_ZQ<1>

243

1%

1/20W

MF

201

1

2

C2340

0.047UF

10%

6.3V X5R 201

1

2

100 22

1

C2341

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

PP1V2_S3

21 22 23 24 100

NC NC NC NC NC NC NC NC NC NC NC NC

1

C2300

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2301

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8 G8 P8 D8

J8

B3 B4

H4

J11

A1

A2 A12 A13

B1 B13

T1 T13

U1

U2 U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

1

2

OMIT_TABLE

C2301

0.1UF

10% 16V X5R-CERM 0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2302

1UF

20% 10V

2

X5R 0201

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC NC NC

1

C2303

1UF

20% 10V

2

X5R 0201

MEM_A_DQ<17> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<16> MEM_A_DQ<6> MEM_A_DQ<1> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<7> MEM_A_DQ<0> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<26> MEM_A_DQ<30> MEM_A_DQ<24> MEM_A_DQ<29> MEM_A_DQ<27> MEM_A_DQ<31> MEM_A_DQ<28> MEM_A_DQ<25> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<10> MEM_A_DQ<15> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<14> MEM_A_DQ<11>

MEM_A_DQS_N<2> MEM_A_DQS_N<0> MEM_A_DQS_N<3> MEM_A_DQS_N<1>

MEM_A_DQS_P<2> MEM_A_DQS_P<0> MEM_A_DQS_P<3> MEM_A_DQS_P<1>

1

C2304

1UF

20% 10V

2

X5R 0201

1

C2305

1UF

20% 10V

2

X5R 0201

BI

103

1

C2306

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2307

10UF

20% 10V

2

X5R-CERM 0402-7

PP1V8_S3_MEM

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

CRITICAL

1

C2334

12PF

5% 25V

2

NP0-C0G 0201

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5 J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3 L2 M2

A11 C12

E8 E12 G12

H8

H9 H11

J9 J10

K8 K11 L12

N8 N12 R12 U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2300

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V8_S3_MEM

21 22 23 24 100

1

C2320

1UF

20% 10V

2

X5R 0201

1

C2310

1UF

20% 10V

2

X5R 0201

1

C2330

1UF

20% 10V

2

X5R 0201

1

C2321

1UF

20% 10V

2

X5R 0201

1

C2311

1UF

20% 10V

2

X5R 0201

1

C2331

1UF

20% 10V

2

X5R 0201

1

C2322

1UF

20% 10V

2

X5R 0201

1

C2312

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2332

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2323

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2333

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2336

12PF

5% 25V

2

NP0-C0G 0201

1

C2324

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2335

12PF

5% 25V

2

NP0-C0G 0201

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

CRITICAL

1

C2338

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2339

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2337

12PF

5% 25V

2

NP0-C0G 0201

BOM_COST_GROUP=DRAM

PAGE TITLE

LPDDR3 DRAM Channel A (00-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=05/12/2015SYNC_MASTER=J52_MLB

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

23 OF 145

SHEET

21 OF 119

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL A (32-63)

345678

2 1

D

C

B

R2400

243

1%

1/20W

MF

201

U2400

LPDDR3-1600-32GB

EDFB232A1MA

25 7

25 21 7

IN

MEM_A_CAB<0> MEM_A_CAB<1> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<4> MEM_A_CAB<5> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<8> MEM_A_CAB<9>

MEM_A_CKE<2> MEM_A_CKE<3>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<2> MEM_A_ZQ<3>

243

1%

1/20W

MF

201

1

2

C2440

0.047UF

10%

6.3V X5R 201

1

2

100 21

1

C2441

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_A

PP1V2_S3

21 22 23 24 100

NC NC NC NC NC NC NC NC NC NC NC NC

1

C2400

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2401

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8 G8 P8 D8

J8

B3 B4

H4

J11

A1

A2 A12 A13

B1 B13

T1 T13

U1

U2 U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

1

2

OMIT_TABLE

C2401

0.1UF

10% 16V X5R-CERM 0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2402

1UF

20% 10V

2

X5R 0201

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC NC NC

1

C2403

1UF

20% 10V

2

X5R 0201

MEM_A_DQ<41> MEM_A_DQ<46> MEM_A_DQ<42> MEM_A_DQ<40> MEM_A_DQ<43> MEM_A_DQ<47> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<55> MEM_A_DQ<49> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<50> MEM_A_DQ<54> MEM_A_DQ<48> MEM_A_DQ<51> MEM_A_DQ<37> MEM_A_DQ<32> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<36> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<59> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<63> MEM_A_DQ<58>

MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<4> MEM_A_DQS_N<7>

MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<4> MEM_A_DQS_P<7>

1

C2404

1UF

20% 10V

2

X5R 0201

1

C2405

1UF

20% 10V

2

X5R 0201

BI

103

1

C2406

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2407

10UF

20% 10V

2

X5R-CERM 0402-7

PP1V8_S3_MEM

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5 J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3 L2 M2

A11 C12

E8 E12 G12

H8

H9 H11

J9 J10

K8 K11 L12

N8 N12 R12 U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2400

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V8_S3_MEM

21 22 23 24 100

1

C2420

1UF

20% 10V

2

X5R 0201

1

C2410

1UF

20% 10V

2

X5R 0201

1

C2430

1UF

20% 10V

2

X5R 0201

1

C2421

1UF

20% 10V

2

X5R 0201

1

C2411

1UF

20% 10V

2

X5R 0201

1

C2431

1UF

20% 10V

2

X5R 0201

1

C2422

1UF

20% 10V

2

X5R 0201

1

C2412

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2432

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2423

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2433

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2435

12PF

5% 25V

2

NP0-C0G 0201

1

C2424

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2434

12PF

5% 25V

2

NP0-C0G 0201

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

CRITICAL

1

C2437

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2436

12PF

5% 25V

2

NP0-C0G 0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

24 OF 145

SHEET

22 OF 119

D

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (0-31)

345678

2 1

D

C

B

R2500

243

1%

1/20W

MF

201

U2500

LPDDR3-1600-32GB

EDFB232A1MA

25 7

25 24 7

IN

MEM_B_CAA<0> MEM_B_CAA<1> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<4> MEM_B_CAA<5> MEM_B_CAA<6> MEM_B_CAA<7> MEM_B_CAA<8> MEM_B_CAA<9>

MEM_B_CKE<0> MEM_B_CKE<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<0> MEM_B_ZQ<1>

243

1%

1/20W

MF

201

1

100 24

2

C2540

0.047UF

10%

6.3V X5R 201

1

2

1

C2541

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_MEM_VREFCA_A

24 100

PP0V6_S3_MEM_VREFDQ_B

PP1V2_S3

21 22 23 24 100

NC NC NC NC NC NC NC NC NC NC NC NC

1

C2500

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2501

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8 G8 P8 D8

J8

B3 B4

H4

J11

A1

A2 A12 A13

B1 B13

T1 T13

U1

U2 U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

1

2

OMIT_TABLE

C2501

0.1UF

10% 16V X5R-CERM 0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2502

1UF

20% 10V

2

X5R 0201

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC NC NC

1

C2503

1UF

20% 10V

2

X5R 0201

MEM_B_DQ<9> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<15> MEM_B_DQ<8> MEM_B_DQ<19> MEM_B_DQ<21> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<18> MEM_B_DQ<20> MEM_B_DQ<0> MEM_B_DQ<5> MEM_B_DQ<3> MEM_B_DQ<6> MEM_B_DQ<1> MEM_B_DQ<4> MEM_B_DQ<7> MEM_B_DQ<2> MEM_B_DQ<26> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<27> MEM_B_DQ<30> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<31>

MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<0> MEM_B_DQS_N<3>

MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<0> MEM_B_DQS_P<3>

1

C2504

1UF

20% 10V

2

X5R 0201

1

C2505

1UF

20% 10V

2

X5R 0201

BI

103

1

C2506

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2507

10UF

20% 10V

2

X5R-CERM 0402-7

PP1V8_S3_MEM

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5 J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3 L2 M2

A11 C12

E8 E12 G12

H8

H9 H11

J9 J10

K8 K11 L12

N8 N12 R12 U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2500

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V8_S3_MEM

21 22 23 24 100

1

C2520

1UF

20% 10V

2

X5R 0201

1

C2510

1UF

20% 10V

2

X5R 0201

1

C2530

1UF

20% 10V

2

X5R 0201

1

C2521

1UF

20% 10V

2

X5R 0201

1

C2511

1UF

20% 10V

2

X5R 0201

1

C2531

1UF

20% 10V

2

X5R 0201

1

C2522

1UF

20% 10V

2

X5R 0201

1

C2512

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2532

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2523

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2533

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2535

12PF

5% 25V

2

NP0-C0G 0201

1

C2524

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2534

12PF

5% 25V

2

NP0-C0G 0201

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

CRITICAL

1

C2537

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2536

12PF

5% 25V

2

NP0-C0G 0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

LPDDR3 DRAM Channel B (00-31)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

25 OF 145

SHEET

23 OF 119

D

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (32-63)

345678

2 1

D

C

B

R2600

243

1%

1/20W

MF

201

U2600

LPDDR3-1600-32GB

EDFB232A1MA

25 7

25 23 7

IN

MEM_B_CAB<0> MEM_B_CAB<1> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5> MEM_B_CAB<6> MEM_B_CAB<7> MEM_B_CAB<8> MEM_B_CAB<9>

MEM_B_CKE<2> MEM_B_CKE<3>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<2> MEM_B_ZQ<3>

243

1%

1/20W

MF

201

1

2

C2640

0.047UF

10%

6.3V X5R 201

1

2

1

C2641

0.047UF

10%

6.3V

2

X5R 201

23 100

100 23

PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFDQ_B

PP1V2_S3

21 22 23 24 100

NC NC NC NC NC NC NC NC NC NC NC NC

1

C2600

0.1UF

10% 16V

2

X5R-CERM 0201

1

2

R2601

R2 P2 N2 N3 M3 F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8 G8 P8 D8

J8

B3 B4

H4

J11

A1

A2 A12 A13

B1 B13

T1 T13

U1

U2 U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

1

2

OMIT_TABLE

C2601

0.1UF

10% 16V X5R-CERM 0201

FBGA

SYM 1 OF 2

CRITICAL

1

C2602

1UF

20% 10V

2

X5R 0201

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC NC NC

1

C2603

1UF

20% 10V

2

X5R 0201

MEM_B_DQ<41> MEM_B_DQ<47> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<46> MEM_B_DQ<40> MEM_B_DQ<55> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<54> MEM_B_DQ<37> MEM_B_DQ<33> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<36> MEM_B_DQ<32> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<62> MEM_B_DQ<63> MEM_B_DQ<56> MEM_B_DQ<59> MEM_B_DQ<61> MEM_B_DQ<60>

MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<4> MEM_B_DQS_N<7>

MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<4> MEM_B_DQS_P<7>

1

C2604

1UF

20% 10V

2

X5R 0201

1

C2605

1UF

20% 10V

2

X5R 0201

BI

103

1

C2606

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2607

10UF

20% 10V

2

X5R-CERM 0402-7

PP1V8_S3_MEM

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5 J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3 L2 M2

A11 C12

E8 E12 G12

H8

H9 H11

J9 J10

K8 K11 L12

N8 N12 R12 U11

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2600

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

A

PP1V2_S3

21 22 23 24 100

PP1V2_S3

21 22 23 24 100

PP1V8_S3_MEM

21 22 23 24 100

1

C2620

1UF

20% 10V

2

X5R 0201

1

C2610

1UF

20% 10V

2

X5R 0201

1

C2630

1UF

20% 10V

2

X5R 0201

1

C2621

1UF

20% 10V

2

X5R 0201

1

C2611

1UF

20% 10V

2

X5R 0201

1

C2631

1UF

20% 10V

2

X5R 0201

1

C2622

1UF

20% 10V

2

X5R 0201

1

C2612

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2632

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2623

10UF

20% 10V

2

X5R-CERM 0402-7

1

C2633

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2635

12PF

5% 25V

2

NP0-C0G 0201

1

C2624

10UF

20% 10V

2

X5R-CERM 0402-7

CRITICAL

1

C2634

12PF

5% 25V

2

NP0-C0G 0201

PLACEMENT_NOTE:

10uF caps are shared between DRAM. Distribute evenly.

CRITICAL

1

C2637

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C2636

12PF

5% 25V

2

NP0-C0G 0201

BOM_COST_GROUP=DRAM

SYNC_MASTER=J52_MLB SYNC_DATE=05/12/2015

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

26 OF 145

SHEET

24 OF 119

D

A

8 7 5 4 2 1

36

345678

2 1

D

C

21 7

22 7

22 21 7

Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

PP0V6_S0_DDRVTT

100

IN

MEM_A_CAA<9> MEM_A_CAA<8> MEM_A_CAA<6> MEM_A_CAA<7> MEM_A_CAA<5> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CKE<1> MEM_A_CKE<0> MEM_A_CAA<4> MEM_A_CAA<3> MEM_A_CAA<2> MEM_A_CAA<1> MEM_A_CAA<0> MEM_A_CAB<9> MEM_A_CAB<8> MEM_A_CAB<6> MEM_A_CAB<7> MEM_A_CAB<5> MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CKE<2> MEM_A_CKE<3> MEM_A_CAB<4> MEM_A_CAB<2> MEM_A_CAB<3> MEM_A_CAB<1> MEM_A_CAB<0> MEM_A_CS_L<0> MEM_A_CS_L<1> MEM_A_ODT<0>

R2700 R2701 R2702 R2703 R2704 R2705 R2706 R2707 R2708 R2709 R2710 R2711 R2712 R2713 R2714 R2715 R2716 R2717 R2718 R2719 R2720 R2721 R2722 R2723 R2724 R2725 R2726 R2727 R2728 R2729 R2730

68 68 68 68 68 39 39 82 82 68 68 68 68 68 68 68 68 68 68 39 39 82 82 68 68 68 68 68 82 82 82

1 2

1/20W 201 MF1%

1/20W MF201

1%

1/20W 201 MF1% 1/20W1%

MF2011/20W1%

201 MF1/20W1%

MF2011/20W1% MF2011/20W1% MF2011/20W1%

201 MF1/20W1%

MF2011/20W1%

201 MF1/20W1%

MF2011/20W1% MF2011/20W1%

201 MF1/20W1%

MF2011/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1%

MF2011/20W1% 201 MF1% 1/20W 201 MF1/20W1%

MF2011/20W1%

MF2011/20W1% 201 MF1/20W1%

MF2011/20W1% 201 MF1/20W1% 2011/20W1%

MF 201 MF1/20W1%

201 MF

MF1/20W1%

201 201 MF1% 1/20W

1

C2700

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2701

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2703

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2705

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2707

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2709

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2730

12PF

5% 25V

2

NP0-C0G 0201

1

C2702

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2704

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2706

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2708

0.47UF

20% 4V

2

CERM-X5R-1 201

23 7

24 7

24 23 7

IN

MEM_B_CAA<9> MEM_B_CAA<8> MEM_B_CAA<7> MEM_B_CAA<6> MEM_B_CAA<5> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CKE<1> MEM_B_CKE<0> MEM_B_CAA<4> MEM_B_CAA<2> MEM_B_CAA<3> MEM_B_CAA<1> MEM_B_CAA<0> MEM_B_CAB<9> MEM_B_CAB<8> MEM_B_CAB<7> MEM_B_CAB<6> MEM_B_CAB<5> MEM_B_CLK_N<1> MEM_B_CLK_P<1> MEM_B_CKE<2> MEM_B_CKE<3> MEM_B_CAB<4> MEM_B_CAB<2> MEM_B_CAB<3> MEM_B_CAB<1> MEM_B_CAB<0> MEM_B_CS_L<0> MEM_B_CS_L<1> MEM_B_ODT<0>

R2740 R2741 R2742 R2743 R2744 R2745 R2746 R2747 R2748 R2749 R2750 R2751 R2752 R2753 R2754 R2755 R2756 R2757 R2758 R2759 R2760 R2761 R2762 R2763 R2764 R2765 R2766 R2767 R2768 R2769 R2770

68 68 68 68 68 39 39 82 82 68 68 68 68 68 68 68 68 68 68 39 39 82 82 68 68 68 68 68 82 82 82

PP0V6_S0_DDRVTT

100

1 2

1% 201 MF1/20W

D

MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1% MF2011/20W1%

MF2011/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1%

MF1/20W 2011%

MF2011/20W1%

MF2011/20W1% 201 MF1/20W1%

MF2011/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1% 201 MF1/20W1%

MF2011/20W1%

1

C2710

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2711

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2713

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2715

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2717

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2719

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2731

12PF

5% 25V

2

NP0-C0G 0201

1

C2712

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2714

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2716

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2718

0.47UF

20% 4V

2

CERM-X5R-1 201

C

B

CRITICAL

1

C2720

20UF

20%

6.3V

2

CERM-X5R 0402

1

C2722

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C2740

20UF

20%

6.3V

2

CERM-X5R 0402

1

C2742

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

B

A

SYNC_MASTER=J52_MLB

PAGE TITLE

LPDDR3 DRAM Termination

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DRAM

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=05/12/2015

051-00515

D

9.0.0

dvt-fab09-0

27 OF 145

25 OF 119

A

345678

2 1

D

C

B

A

1

R2890

3.3K

5% 1/20W MF 201

2

TBT_X_SPI_CLK

28

TBT_X_SPI_CS_L

28

TBT_X_ROM_WP_L

26

TBT_X_ROM_HOLD_L

34

BI

34

BI

34

BI

34

BI

100K

1 2

100K

1 2

DP_X_SNK0_ML_C_P<0>

IN

DP_X_SNK0_ML_C_N<0>

IN

DP_X_SNK0_ML_C_P<1>

IN

DP_X_SNK0_ML_C_N<1>

IN

DP_X_SNK0_ML_C_P<2>

IN

DP_X_SNK0_ML_C_N<2>

IN

DP_X_SNK0_ML_C_P<3>

IN

DP_X_SNK0_ML_C_N<3>

IN

DP_X_SNK0_AUXCH_C_P

DP_X_SNK0_AUXCH_C_N

DP_X_SNK1_ML_C_P<0>

IN

DP_X_SNK1_ML_C_N<0>

IN

DP_X_SNK1_ML_C_P<1>

IN

DP_X_SNK1_ML_C_N<1>

IN

DP_X_SNK1_ML_C_P<2>

IN

DP_X_SNK1_ML_C_N<2>

IN

DP_X_SNK1_ML_C_P<3>

IN

DP_X_SNK1_ML_C_N<3>

IN

DP_X_SNK1_AUXCH_C_P

DP_X_SNK1_AUXCH_C_N

5% MF

1M

5%

1M

1/20W5% 201MF

1M

5% MF1/20W 201

R2891

3.3K

1/20W

R2862

2015% 1/20W MF

R2872

1/20W 201

R2860

MF 2011/20W

R2861

MF5%

2011/20W

R2870

R2871

1

5%

MF

201

2

GND_VOID=TRUE

R2893

3.3K

5% 1/20W MF 201

2

6

1

3

7

DP_XA_HPD

DP_XB_HPD

TBT_XA_LSTX

TBT_XA_LSRX

TBT_XB_LSTX

TBT_XB_LSRX

PP3V3_UPC_XB_LDO

R2892

3.3K

5%

1/20W

8

VCC

MF

201

U2890

8MBIT-3.0V

W25Q80DVUXIE

CLK

CS*

WP*(IO2)

HOLD*(IO3)

GND EPAD

4

USON

DI(IO0) DO(IO1)

OMIT_TABLE

CRITICAL

9

5 2

SNK0 AC Coupling

C2820

0.1UF

C2821

0.1UF

C2822

0.1UF

C2823

0.1UF

C2824

0.1UF

C2825

0.1UF

C2826

0.1UF

C2827

0.1UF

C2828

0.1UF

C2829

0.1UF

1 2

X5R-CERM

1 2

X5R-CERM

1 2

10% 16V 0201 X5R-CERM

1 2

X5R-CERM

1 2

10% 16V 0201 X5R-CERM

1 2

X5R-CERM

1 2

10% 16V X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

16V 020110%

16V10%

SNK1 AC Coupling

C2830

0.1UF

C2831

0.1UF

C2832

0.1UF

C2833

0.1UF

C2834

0.1UF

C2835

0.1UF

C2836

0.1UF

C2837

0.1UF

C2838

0.1UF

C2839

0.1UF

1 2

X5R-CERM

1 2

X5R-CERM

1 2

10% X5R-CERM

1 2

X5R-CERM

1 2

10% X5R-CERM

1 2

X5R-CERM

1 2

X5R-CERM

1 2

16V10%

X5R-CERM

1 2

X5R-CERM

1 2

16V10% 0201

X5R-CERM

29 28 26

30 26

29 26

30 26

28

1

2

C2890

1UF

10%

6.3V

2

CERM 402

TBT_X_SPI_MOSI TBT_X_SPI_MISO

DP_X_SNK0_ML_P<0>

020110% 16V

DP_X_SNK0_ML_N<0>

020116V10%

DP_X_SNK0_ML_P<1>

DP_X_SNK0_ML_N<1>

020110% 16V

DP_X_SNK0_ML_P<2>

DP_X_SNK0_ML_N<2>

020116V10%

DP_X_SNK0_ML_P<3>

0201

DP_X_SNK0_ML_N<3>

DP_X_SNK0_AUXCH_P

0201

DP_X_SNK0_AUXCH_N

020116V10%

DP_X_SNK1_ML_P<0>

020116V10%

DP_X_SNK1_ML_N<0>

020116V10%

DP_X_SNK1_ML_P<1>

020116V

DP_X_SNK1_ML_N<1>

020116V10%

DP_X_SNK1_ML_P<2>

020116V

DP_X_SNK1_ML_N<2>

020116V10%

DP_X_SNK1_ML_P<3>

020116V10%

DP_X_SNK1_ML_N<3>

0201

DP_X_SNK1_AUXCH_P

020116V10%

DP_X_SNK1_AUXCH_N

26

28

29

PLACE_NEAR=U2800.H6:2MM PLACE_NEAR=U2800.J6:2MM

DP_XA_AUXCH_P

BI

DP_XA_AUXCH_N

BI

10K PU ON CLOCKS PAGE

34 28

OUT

R2830

100K

1/20W

34 28

OUT

R2831

100K

5%

1/20W

MF

201

1 2

TF

1

2

1/20W

R2855

GND_VOID=TRUE

12

0201

PLACE_NEAR=U2800.H19:2MM

16V

10%

X5R-CERM

16V

10%

X5R-CERM

12

GND_VOID=TRUE

R2854

499

1%

1/20W

MF

1

5% MF

201

2

C2810

0.1UF

C2811

0.1UF

1

2

201

28

IN

28

IN

28

IN

28

IN

28

IN

28

IN

28

IN

28

IN

PCIE_CLK100M_TBT_X_P

IN

PCIE_CLK100M_TBT_X_N

IN

TBT_X_CLKREQ_L

OUT

28

IN

28

BI

28

IN

28

BI

1/20W

14K

105 15

19

12 201

1% MF

R2850

94 92 28

4.75K

0.5% 0201

TBT_XA_USB2_RBIAS

31

28

29 26

29 28 26

56

OUT

IN

OUT

IN

DP_XA_AUXCH_C_P DP_XA_AUXCH_C_N

BI

OUT

IN

TBTTHMSNS_D1_P

PCIE_TBT_X_R2D_P<0> PCIE_TBT_X_R2D_N<0>

PCIE_TBT_X_R2D_P<1> PCIE_TBT_X_R2D_N<1>

PCIE_TBT_X_R2D_P<2> PCIE_TBT_X_R2D_N<2>

PCIE_TBT_X_R2D_P<3> PCIE_TBT_X_R2D_N<3>

DP_X_SNK0_ML_P<0>

26

DP_X_SNK0_ML_N<0>

26

DP_X_SNK0_ML_P<1>

26

DP_X_SNK0_ML_N<1>

26

DP_X_SNK0_ML_P<2>

26

DP_X_SNK0_ML_N<2>

26

DP_X_SNK0_ML_P<3>

26

DP_X_SNK0_ML_N<3>

26

DP_X_SNK0_AUXCH_P

26

DP_X_SNK0_AUXCH_N

26

DP_X_SNK0_HPD

DP_X_SNK0_DDC_CLK DP_X_SNK0_DDC_DATA

DP_X_SNK1_ML_P<0>

26

DP_X_SNK1_ML_N<0>

26

DP_X_SNK1_ML_P<1>

26

DP_X_SNK1_ML_N<1>

26

DP_X_SNK1_ML_P<2>

26

DP_X_SNK1_ML_N<2>

26

DP_X_SNK1_ML_P<3>

26

DP_X_SNK1_ML_N<3>

26

DP_X_SNK1_AUXCH_P

26

DP_X_SNK1_AUXCH_N

26

DP_X_SNK1_HPD

DP_X_SNK1_DDC_CLK DP_X_SNK1_DDC_DATA

DP_X_SNK_RBIAS

PLACE_NEAR=U2800.Y18:2MM

94 92

28

94 92

IN

OUT

JTAG_TBT_TDI JTAG_TBT_X_TMS JTAG_TBT_TCK JTAG_ISP_TDO

TBT_X_RBIAS TBT_X_RSENSE

USBC_XA_D2R_P<2> USBC_XA_D2R_N<2>

USBC_XA_R2D_C_P<2> USBC_XA_R2D_C_N<2>

USBC_XA_R2D_C_P<1> USBC_XA_R2D_C_N<1>

USBC_XA_D2R_P<1> USBC_XA_D2R_N<1>

USB_UPC_XA_P USB_UPC_XA_N

TBT_XA_LSTX TBT_XA_LSRX DP_XA_HPD

USE NEAREST GND BALL

(AC22) FOR THERM_D_N

NC

Y23 Y22

T23 T22

PCIE_RX0_P PCIE_RX0_N

PCIE_RX1_P PCIE_RX1_N

U2800

TBT-AR-4C-CNTRL

SYM 1 OF 2

FCBGA

OMIT_TABLE

PCIE_TX0_P PCIE_TX0_N

PCIE_TX1_P PCIE_TX1_N

CRITICAL

M23

PCIE_RX2_P

M22

PCIE_RX2_N

H23

PCIE_RX3_P

H22

PCIE_RX3_N

V19

PCIE_REFCLK_100_IN_P

T19

PCIE_REFCLK_100_IN_N

AC5 N16

PCIE_CLKREQ*

AB7

DPSNK0_ML0_P

AC7

DPSNK0_ML0_N

AB9

DPSNK0_ML1_P

AC9

DPSNK0_ML1_N

AB11 AC11

AB13 AC13

AB15 AC15

AB17 AC17

AB19 AC19

AB21 AC21

AC23 AB23

DPSNK0_ML2_P DPSNK0_ML2_N

DPSNK0_ML3_P DPSNK0_ML3_N

Y11

DPSNK0_AUX_P

W11

DPSNK0_AUX_N

AA2

DPSNK0_HPD

Y5

DPSNK0_DDC_CLK

R4

DPSNK0_DDC_DATA

DPSNK1_ML0_P DPSNK1_ML0_N

DPSNK1_ML1_P DPSNK1_ML1_N

DPSNK1_ML2_P DPSNK1_ML2_N

DPSNK1_ML3_P DPSNK1_ML3_N

Y12

DPSNK1_AUX_P

W12

DPSNK1_AUX_N

Y6

DPSNK1_HPD

Y8

DPSNK1_DDC_CLK

N4

DPSNK1_DDC_DATA

Y18

DPSNK_RBIAS

Y4

TDI

V4

TMS

T4

TCK

W4

TDO

H6

RBIAS

J6

RSENSE

A15

PA_RX1_P

B15

PA_RX1_N

A17

PA_TX1_P

B17

PA_TX1_N

A19

PA_TX0_P

B19

PA_TX0_N

B21

PA_RX0_P

A21

PA_RX0_N

Y15

PA_DPSRC_AUX_P

W15

PA_DPSRC_AUX_N

E20

PA_USB2_D_P

D20

PA_USB2_D_N

A5

PA_LSTX

A4

PA_LSRX

M4

PA_DPSRC_HPD

H19

PA_USB2_RBIAS

THERMDA THERMDA

V18

PCIE_ATEST

AC1

TEST_EDM

L15

FUSE_VQPS_64

N15

FUSE_VQPS_128

C23

MONDC_CIO_0

C22

MONDC_CIO_1

SINK PORT 0

SINK PORT 1

PORT A

PCIE GEN3

SOURCE PORT 0

MISC

PORT B POC GPIO LC GPIO

TBT PORTS

DEBUG

PCIE_TX2_P PCIE_TX2_N

PCIE_TX3_P PCIE_TX3_N

PERST*

PCIE_RBIAS

DPSRC_ML0_P DPSRC_ML0_N

DPSRC_ML1_P DPSRC_ML1_N

DPSRC_ML2_P DPSRC_ML2_N

DPSRC_ML3_P DPSRC_ML3_N

DPSRC_AUX_P DPSRC_AUX_N

DPSRC_HPD

DPSRC_RBIAS

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7

GPIO_8 POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4 POC_GPIO_5 POC_GPIO_6

TEST_EN

TEST_PWR_GOOD

RESET*

XTAL_25_IN

XTAL_25_OUT

EE_DI EE_DO

EE_CS*

EE_CLK

PB_RX1_P PB_RX1_N

PB_TX1_P PB_TX1_N

PB_TX0_P PB_TX0_N

PB_RX0_P PB_RX0_N

PB_DPSRC_AUX_P PB_DPSRC_AUX_N

PB_USB2_D_P PB_USB2_D_N

PB_LSTX PB_LSRX

PB_DPSRC_HPD

PB_USB2_RBIAS

MONDC_SVR

ATEST_P ATEST_N

USB2_ATEST

MONDC_DPSNK_0 MONDC_DPSNK_1

MONDC_DPSRC

V23 V22

P23 P22

K23 K22

F23 F22

L4

PCIE_TBT_X_D2R_C_P<0> PCIE_TBT_X_D2R_C_N<0>

PCIE_TBT_X_D2R_C_P<1> PCIE_TBT_X_D2R_C_N<1>

PCIE_TBT_X_D2R_C_P<2> PCIE_TBT_X_D2R_C_N<2>

PCIE_TBT_X_D2R_C_P<3> PCIE_TBT_X_D2R_C_N<3>

TBT_X_PCI_RESET_L

TBT_X_PCIE_BIAS

R2 R1

N2 N1

L2 L1

J2 J1

W19 Y19

G1

N6

U1 U2 V1 V2 W1 W2 Y1 Y2 AA1 J4 E2 D4 H4 F2 D2 F1

E1

AB5

F4

D22 D23

AB3 AC4 AC3 AB4

B7 A7

A9 B9

A11 B11

A13 B13

Y16 W16

E19 D19

B4 B5 G2

F19

D6

A23 B23

E18

W13 W18

AB2

NC_DP_X_SRC_ML_P<0> NC_DP_X_SRC_ML_N<0>

NC_DP_X_SRC_ML_P<1> NC_DP_X_SRC_ML_N<1>

NC_DP_X_SRC_ML_P<2> NC_DP_X_SRC_ML_N<2>

NC_DP_X_SRC_ML_P<3> NC_DP_X_SRC_ML_N<3>

NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N

DP_X_SRC_HPD

28

DP_X_SRC_RBIAS

I2C_TBT_X_SDA I2C_TBT_X_SCL

TBT_X_ROM_WP_L

26

TBT_X_TMU_CLK_OUT SMC_PME_S4_DARK_L TBT_X_CIO_PLUG_EVENT_L DDI1_MUX_SEL DDI2_MUX_SEL TBT_X_TMU_CLK_IN I2C_TBT_XA_INT_L I2C_TBT_XB_INT_L TBT_X_USB_PWR_EN TBT_X_FORCE_PWR PM_BATLOW_L PM_SLP_S3_L TBT_X_CIO_PWR_EN

TBT_X_TEST_EN

TBT_X_TEST_PWR_GOOD

USBC_X_RESET_L

TBT_X_XTAL25M_IN TBT_X_XTAL25M_OUT

UPC_X_SPI_MOSI UPC_X_SPI_MISO UPC_X_SPI_CS_L UPC_X_SPI_CLK

USBC_XB_D2R_P<2> USBC_XB_D2R_N<2>

USBC_XB_R2D_C_P<2> USBC_XB_R2D_C_N<2>

USBC_XB_R2D_C_P<1> USBC_XB_R2D_C_N<1>

USBC_XB_D2R_P<1> USBC_XB_D2R_N<1>

DP_XB_AUXCH_C_P DP_XB_AUXCH_C_N

USB_UPC_XB_P USB_UPC_XB_N

TBT_XB_LSTX TBT_XB_LSRX DP_XB_HPD

BI

OUT

IN

TBT_XB_USB2_RBIAS

PLACE_NEAR=U2800.F19:2MM

1

R2853

NC NC

NC

499

1% 1/20W MF 201

2

BOM_COST_GROUP=TBT

28

IN

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

IN

OUT

28

32 28

28

To SPI Flash

31

IN

31

IN

31

OUT

31

OUT

31

OUT

31

OUT

31

IN

31

IN

30 26

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28 19

PLACE_NEAR= U2800.N6:2MM

R2852

1/20W

1 2

1%

28

OUT

BI

OUT

IN

92 28

28

34

94

30 29 28

PU at PCH

28

PU at PCH

28

30 29

1

R2829

100

5% 1/20W MF 201

2

GND_VOID=TRUE

C2812

0.1UF

C2813

0.1UF

GND_VOID=TRUE

DRAWING

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

PLACE_NEAR=U2800.N16:2MM

R2851

3.01K

1 2

1%

1/20W

MF

201

201MF

14K

PP3V3_S5_TBT_X_SW

1

R2836

2.2K

5% 1/20W MF 201

2

28

IN

104 92 80 77 74 73 48 19 14

1

R2825

100

5% 1/20W MF 201

2

1 2

DP_XB_AUXCH_P

10% 16V

X5R-CERM

10% 16V

X5R-CERM

0201

DP_XB_AUXCH_N

0201

LAST_MODIFIED=Tue Aug 30 11:06:20 2016

USB-C HIGH SPEED 1

Apple Inc.

R

PP3V3_S5_TBT_X_SW

26 32

30

1

R2835

2.2K

5% 1/20W MF 201

2

BI

1

R2834

2.2K

5% 1/20W MF 201

2

1

R2837

2.2K

5% 1/20W MF 201

2

IN

not used

1

R2827

100K

5% 1/20W MF 201

2

BI

28

BI

26 32

28

SYNC_DATE=07/27/2015SYNC_MASTER=J79_GREG

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

28 OF 145

SHEET

26 OF 119

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

1

C2930

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2931

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2984

1.0UF

20%

6.3V

2

X5R 0201-1

C2945

1.0UF

20%

6.3V X5R

0201-1

1

C2932

1.0UF

20%

6.3V

2

X5R 0201-1

1

2

1

C2933

2

1

C2964

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2985

1.0UF

20%

6.3V

2

X5R 0201-1

C2946

1.0UF

20%

6.3V X5R

0201-1

1.0UF

20%

6.3V X5R 0201-1

1

2

SOURCED BY INTERNAL SWITCH

1

C2934

2

1

C2965

1.0UF

20%

6.3V

2

X5R 0201-1

SOURCED BY INTERNAL SWITCH

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

C2947

1.0UF

20%

6.3V X5R

0201-1

1.0UF

20%

6.3V X5R 0201-1

VOLTAGE=3.3V

1

2

1

C2935

2

1

C2966

1.0UF

20%

6.3V

2

X5R 0201-1

PP0V9_TBT_X_DP

1

C2936

1.0UF

20%

6.3V X5R 0201-1

SOURCED BY INTERNAL SWITCH

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2967

1.0UF

20%

6.3V

2

X5R 0201-1

28

PP0V9_TBT_X_PCIE

28

PP0V9_TBT_X_USB

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=0.9V

28

PP0V9_TBT_X_CIO

PP3V3_TBT_X_ANA_PCIE

PP3V3_TBT_X_ANA_USB2

1

C2920

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

C2921

1.0UF

20%

6.3V

2

X5R 0201-1

SOURCED BY

INTERNAL SWITCH

L8

VCC0P9_DP

L11

VCC0P9_DP

L12

VCC0P9_DP

M8

VCC0P9_DP

T11

VCC0P9_DP

T12

VCC0P9_DP

L6

VCC0P9_ANA_DPSRC

M6

VCC0P9_ANA_DPSRC

V11

VCC0P9_ANA_DPSNK

V12

VCC0P9_ANA_DPSNK

V13

VCC0P9_ANA_DPSNK

M13

VCC0P9_PCIE

M15

VCC0P9_PCIE

M16

VCC0P9_PCIE

L19

VCC0P9_ANA_PCIE_1

N19

VCC0P9_ANA_PCIE_1

L18

VCC0P9_ANA_PCIE_2

M18

VCC0P9_ANA_PCIE_2

N18

VCC0P9_ANA_PCIE_2

R15

VCC0P9_USB

R16

VCC0P9_USB

R8

VCC0P9_CIO

R9

VCC0P9_CIO

R11

VCC0P9_CIO

R12

VCC0P9_CIO

L16

VCC3P3_ANA_PCIE

J16

VCC3P3_ANA_USB2

A6

VSS_ANA

A8

VSS_ANA

A10

VSS_ANA

A12 A14

VSS_ANA

A16

VSS_ANA

A18

VSS_ANA

A20

VSS_ANA

A22

VSS_ANA

B6

VSS_ANA

B8

VSS_ANA

B10

VSS_ANA

B12

VSS_ANA

B14

VSS_ANA

B16

VSS_ANA

B18

VSS_ANA

B20

VSS_ANA

B22

VSS_ANA

D8

VSS_ANA

D9

VSS_ANA

D11

VSS_ANA

D12

VSS_ANA

D13

VSS_ANA

D15

VSS_ANA

D16

VSS_ANA

D18

VSS_ANA

E8

VSS_ANA

E9

VSS_ANA

E11

VSS_ANA

E15

VSS_ANA

E16

VSS_ANA

E22

VSS_ANA

E23

VSS_ANA

F9

VSS_ANA

F20

VSS_ANA

F16

VSS_ANA

G22

VSS_ANA

G23

VSS_ANA

H1

VSS_ANA

H2

VSS_ANA

H12

VSS_ANA

H13

VSS_ANA

H15

VSS_ANA

H16

VSS_ANA

H20

VSS_ANA

J5

VSS_ANA

J19

VSS_ANA

J20

VSS_ANA

J18

VSS_ANA

J22

VSS_ANA

J23

VSS_ANA

K1

VSS_ANA

K2

VSS_ANA

L5

VSS_ANA

L20

VSS_ANA

L22

VSS_ANA

L23

VSS_ANA

M1

VSS_ANA

M2

VSS_ANA

M5

VSS_ANA

M19

VSS_ANA

M20

VSS_ANA

N5

VSS_ANA

N20

VSS_ANA

N22

VSS_ANA

N23

VSS_ANA

P1

VSS_ANA

P2

VSS_ANA

R5

VSS_ANA

R18

VSS_ANA

R19

VSS_ANA

R20

VSS_ANA

R22

VSS_ANA

U2800

TBT-AR-4C-CNTRL

SYM 2 OF 2

FCBGA

OMIT_TABLE

CRITICAL

VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA

VCC0P9_SVR_SENSE

VCC

VCC0P9_LVR_SENSE

GND

VCC3P3_LC

VCC3P3_SX

VCC3P3_S0

VCC3P3A

VCC3P3_SVR VCC3P3_SVR VCC3P3_SVR

VCC0P9_SVR VCC0P9_SVR

SVR_IND SVR_IND SVR_IND

SVR_VSS SVR_VSS

SVR_VSS

VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR

VSS_ANA VSS_ANA VSS_ANA VSS_ANAVSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

R6

F8

R13

H9

A2 A3 B3

L9 M9 E12 E13 F11 F12 F13 F15 J9

C1 C2 D1

A1 B1 B2

F18 H18 J11 H11

R23 T1 T2 T5 T20 U23 U22 V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2 M11

PP3V3_TBT_X_LC

PP3V3_S5_TBT_X_SW

1

C2991

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2975

10UF

20%

6.3V

2

CERM-X5R 0402-4

BYPASS=U2800.A2:A1:3MM

1

C2976

10UF

20%

6.3V

2

CERM-X5R 0402-4

PP0V9_TBT_X_SVR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

DIDT=TRUE SWITCH_NODE=TRUE

0.68UH-20%-6.1A-0.020OHM

VR0V9_IND_TBT_X

PP0V9_TBT_X_LVR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

C2992

1.0UF

0201-1

1

20%

6.3V 2

X5R

Add XW or alias on support page

XW

XW2900

SM

1 2

PLACE_NEAR=U2800.AC22:2MM

NO_XNET_CONNECTION=1

PP3V3_TBT_X_F

VOLTAGE=3.3V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

C2977

10UF

20%

6.3V

2

CERM-X5R 0402-4

CRITICAL

L2950

1 2

1210

SOURCED BY INTERNAL SWITCH

20%

6.3V X5R

1

2

C2993

1.0UF

0201-1

28

TBTTHMSNS_D1_N

C2954

10UF

20%

6.3V

CERM-X5R

0402-4

1

C2978

10UF

20%

6.3V

2

CERM-X5R 0402-4

1

2

OUT

C2990

1.0UF

0201-1

1

2

C2955

10UF

CERM-X5R

0402-4

2x 10uF outside BGA area

1

20%

6.3V 2

X5R

1

2

C2950

47UF

20%

6.3V CER-X5R 0603

1

20%

6.3V 2

C2994

47UF

CER-X5R

C2917

12PF

5% 25V NP0-C0G 0201

20%

6.3V

0603

1

C2951

47UF

20%

6.3V

2

CER-X5R 0603

1

2

P0V9_TBT_X_SVR_AGND

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0V

56

BOM_COST_GROUP=TBT

C2995

47UF

CER-X5R

1

C2910

1.0UF

20%

6.3V

2

X5R 0201-1

20%

6.3V

0603

1

2

1

2

1

2

1 2

0603

L2990

1.0UH-20%-2.1A-0.128OHM

CRITICAL

C2911

1.0UF

20%

6.3V X5R 0201-1

C2952

47UF

20%

6.3V CER-X5R 0603

FROM USB-C PORT CONTROLLER (UPC)

1

C2981

1.0UF

20%

6.3V

2

X5R 0201-1

PP3V3_TBT_X_S0

1

C2912

1.0UF

20%

6.3V

2

X5R 0201-1

INTERNAL SWITCHING VR OUTPUT

1

C2913

1.0UF

20%

6.3V

2

X5R 0201-1

SYNC_MASTER=J79_GREG SYNC_DATE=09/09/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

28

28 32

1

C2914

1.0UF

20%

6.3V

2

X5R 0201-1

ISOLATE GND OF SVR_IND CAPS

AND GND OF VCC3P3_SVR CAPS

FROM SYSTEM GND IN LAYOUT

(SEE INTEL LAYOUT GUIDELINES)

28 101

1

C2915

1.0UF

20%

6.3V

2

X5R 0201-1

1

C2980

0.1UF

10% 16V

2

X5R-CERM 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

C2916

1.0UF

20%

6.3V

2

X5R 0201-1

USB-C HIGH SPEED 2

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

29 OF 145

SHEET

27 OF 119

SOURCED BY INTERNAL SWITCH

9.0.0

D

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

TMU CLKs

TBT_X_TMU_CLK_OUT

26

MAKE_BASE=TRUE

TBT_X_TMU_CLK_OUT

Ridge 0.9V SVR XW

P0V9_TBT_X_SVR_AGND

27

DP SRC OPTIONS

IF DP SRC NOT USED

NC_DP_X_SRC_ML_P<0>

26

NC_DP_X_SRC_ML_P<1>

26

NC_DP_X_SRC_ML_P<2>

26

NC_DP_X_SRC_ML_P<3>

26

NC_DP_X_SRC_ML_N<0>

26

NC_DP_X_SRC_ML_N<1>

26

NC_DP_X_SRC_ML_N<2>

26

NC_DP_X_SRC_ML_N<3>

26

NC_DP_X_SRC_AUX_P

26

NC_DP_X_SRC_AUX_N

26

AR xtal

26

IN

OUT

TBT_X_XTAL25M_OUT

1

NOSTUFF

R3006

1M

5% 1/20W MF 201

2

TBT_X_XTAL25M_IN

25MHZ-25PPM-20PF-50OHM

RIDGE DEBUG CONN

USBC_DBG

28 26

34 26

28 29 30

27

Ridge PDs

TBT_X_CIO_PLUG_EVENT_L DP_X_SNK0_HPD DP_X_SNK1_HPD

TBT_POC_RESET PP3V3_TBT_X_LC

DP_X_SNK0_DDC_CLK

26

DP_X_SNK0_DDC_CLK

DP_X_SNK0_DDC_DATA

26

DP_X_SNK0_DDC_DATA

DP_X_SNK1_DDC_CLK

26

DP_X_SNK1_DDC_CLK

DP_X_SNK1_DDC_DATA

26

DP_X_SNK1_DDC_DATA

15

USB3_EXTA_R2D_C_P

IN

USB3_EXTA_R2D_C_N

IN

R3025

15

1 2

5%

1/20W

MF

201

NC_DP_X_SRC_ML_P<0> NC_DP_X_SRC_ML_P<1> NC_DP_X_SRC_ML_P<2> NC_DP_X_SRC_ML_P<3>

NC_DP_X_SRC_ML_N<0> NC_DP_X_SRC_ML_N<1> NC_DP_X_SRC_ML_N<2>

NC_DP_X_SRC_ML_N<3>

NC_DP_X_SRC_AUX_P NC_DP_X_SRC_AUX_N

R3007

1 2

1/20W5%MF

2.00X1.60-SM

J3001

505070-1220

M-ST-SM

13 14

1 2

3 4

5 6

7 8

9 10

11 12

15

MAKE_BASE=TRUE

DCI

PCH USB3

PLACE_NEAR=U2800.V2:5mm

5%

XW3000

SHORT-L6-SM

1 2

DP_X_SRC_HPD

26

0

TBT_X_XTAL25M_OUT_R

201

CRITICAL

Y3000

TBT_X_PCI_RESET_L USBC_X_RESET_L PP3V3_S5_TBT_X_SW PP0V9_TBT_X_PCIEDP_XA_HPD PP0V9_TBT_X_USB PP0V9_TBT_X_CIO

16

C3020

0.1UF

1 2

10% 16V

X5R-CERM

0201

C3021

0.1UF

1 2

10% 16V

X5R-CERM

0201

TBT_T_TMU_CLK_IN

MAKE_BASE=TRUE

TBT_T_TMU_CLK_IN

R3024

1/20W MF 201

NO_XNET_CONNECTION=1

100K

1 2

R3040

1M

1 2

5%

1/20W

MF

201

1

2

2 4

1 3

2

1

R3067

5% MF 2011/20W

R3068

1/20W5% 201MF

R3069

1/20W 2015% MF

R3070

201

MF1/20W5%

15

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE NO_TEST=1

C3002

20PF

5% 25V C0G 0201

0201 C0G 25V 5%

20PF

C3003

19 26

27 32

27 29 26

27

100K

1 2

100K

1 2

100K

1 2

100K

1 2

OUT

92

X ACE-SMC I2C SERIES R'S

I2C_UPC_X_SDA2

29

I2C_UPC_X_SDA2

30

28

29

30

28

MAKE_BASE=TRUE

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2

MAKE_BASE=TRUE

I2C_UPC_X_SCL2

ACE A/B RPD STRAPPING

USBC_XA_CC1

29

USBC_XA_CC2

29

USBC_XB_CC1

30

USBC_XB_CC2

30

ACE PDs

33 28

94 51 48

UPC_X_5V_EN

28 26

28 32 26

28

30 29

FUSES FOR UPC

28 29

28 30

DCI ALIASES

MAKE_BASE=TRUE

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_P

USB3_EXTA_R2D_N

MAKE_BASE=TRUE

R3041

1/20W MF332015%

R3042

5% MF

ACE DEBUG CONN

USBC_DBG

I2C_TBT_XB_INT_L I2C_UPC_X_SCL2

I2C_UPC_X_SDA2 SMC_USBC_INT_L TBT_X_SPI_CLK_DBG UPC_XA_UART_TX

PP20V_USBC_XA_VBUS

PP20V_USBC_XB_VBUS

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_P

USB3_EXTA_R2D_N

PLACE_NEAR=U5000:5mm

1 2

PLACE_NEAR=U5000:5mm

33

1 2

201MF5% 1/20W

MAKE_BASE=TRUE

SMBUS_SMC_4_G3H_SDA

SMBUS_SMC_4_G3H_SCL

USBC_XA_CC1

MAKE_BASE=TRUE

USBC_XA_CC2

MAKE_BASE=TRUE

USBC_XB_CC1

MAKE_BASE=TRUE

USBC_XB_CC2

R3032

100K

1 2

2011/20W

J3000

505070-1220

M-ST-SM

13 14

1 2

3 4

5 6

7 8

9 10

11 12

15

PLACE_NEAR=Q3100:5MM

16

CRITICAL

0603

F3000

6AMP-32V-0.0095OHM

1 2

PLACE_NEAR=Q3200:5MM

CRITICAL

0603

740S0135

F3001

6AMP-32V-0.0095OHM

1 2

SMBUS_SMC_4_G3H_SDA

SMBUS_SMC_4_G3H_SCL

104 31 29

104 31 30

ACE Debug Support

UPC_XA_DBG_UART_TX

29

UPC_XA_DBG_UART_RX

29

UPC_XB_DBG_UART_TX

30

UPC_XB_DBG_UART_RX

30

I2C_TBT_XA_INT_L I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_UPC_XA_DBG_CTL_SDA I2C_UPC_XA_DBG_CTL_SCL UPC_XA_UART_RX

PP20V_USBC_XA_VBUS_F

PP20V_USBC_XB_VBUS_F

29

IN

OUT

29

DCI Ace

51

OMIT

R3089

NOSTUFF

NONE NONE NONE

OMIT

R3088

NOSTUFF

NONE NONE NONE

28 26

29

30 29

29

30

402

0

1 2

201

0

1 2

201

0

1 2

201

0

1 2

201

AR/ACE SPI BUS SERIES R'S

R3094

TBT_X_SPI_CLK

26

TBT_X_SPI_CS_L

26

TBT_X_SPI_MOSI

26

TBT_X_SPI_MISO

26

ROM

R3095 R3096 R3097 R3098 R3090 R3091 R3092 R3093

100

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

USBC DEBUG CONN

TBT_X_SPI_CLK_DBG

5% 1/20W MF 201

UPC_XB_SPI_CLK

1/20W

UPC_XB_SPI_CS_L

UPC_XB_SPI_MOSI

5% 1/20W 201

UPC_XB_SPI_MISO

5% MF1/20W

UPC_X_SPI_CLK

UPC_X_SPI_CS_L

5% 201

1/20W MF

UPC_X_SPI_MOSI

1/20W 201

5% MF

UPC_X_SPI_MISO

5% 1/20W 201MF

201MF5%

2015% 1/20W MF

MF

201

MF1/20W 2015%

28

OUT

IN

30

28 26

Ace

D

AR

USB2 AR PDs

GND ALIASES

GND

29

GND

30

GND

29 30 95 96

GND

29

GND

29

GND

29

USB_UPC_XA_P

26

USB_UPC_XA_N

26

USB_UPC_XB_P

26

USB_UPC_XB_N

26

29

30

29

30

29

R3020

5% MF1/20W

R3021

MF1/20W5%

R3022

5% MF1/20W

R3023

MF5% 1/20W

GND GND GND GND GND

GND

NC ALIASES / NO TEST

NO_TEST=1

30

IN

NC_UPC_XB_I2C_ADDR

TBT to ACE

SIGNAL ALIASES

MAKE_BASE=TRUE

UPC_X_5V_EN

29

UPC_X_5V_EN

30

1

2

1

2

106 34

TBT_X_CIO_PWR_EN

26 29 30

TBT_X_USB_PWR_EN

26 29 30

PM_BATLOW_L

26

SMC_PME_S4_DARK_L

26 92

SMC_PME_S4_DARK_L

29 30 95 96

UPC_X_SPI_CLK

26 28

UPC_X_SPI_CS_L

26 28

UPC_X_SPI_MOSI

26 28

UPC_X_SPI_MISO

26 28

UPC_T_SPI_CLK

92 94

UPC_T_SPI_CS_L

92 94

UPC_T_SPI_MOSI

92 94

UPC_T_SPI_MISO

92 94

JTAG_ISP_TDO

26 92 94

TBT_POC_RESET

28 29 30

DDI1_MUX_SEL

DDI2_MUX_SEL

TBT_X_CIO_PLUG_EVENT_L

16

XDP_USB_EXTA_OC_L

29

XDP_USB_EXTB_OC_L

30

JTAG_TBT_X_TMS

13

JTAG_TBT_T_TMS

13 94

SMC_DEBUGPRT_TX_L

30

SMC_DEBUGPRT_RX_L

30

NC_USBC_XA_RESET_L

29

USB_UPC_PCH_XA_N

15

USB_UPC_PCH_XA_N

29

USB_UPC_PCH_XA_P

15

USB_UPC_PCH_XA_P

29

USB_UPC_PCH_XB_N

15

USB_UPC_PCH_XB_N

30

USB_UPC_PCH_XB_P

15

USB_UPC_PCH_XB_P

30

UPC_X_5V_EN

MAKE_BASE=TRUE

TBT_X_CIO_PWR_EN

MAKE_BASE=TRUE

TBT_X_USB_PWR_EN

MAKE_BASE=TRUE

PM_BATLOW_L

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

UPC_X_SPI_CLK

MAKE_BASE=TRUE

UPC_X_SPI_CS_L

MAKE_BASE=TRUE

UPC_X_SPI_MOSI

MAKE_BASE=TRUE

UPC_X_SPI_MISO

MAKE_BASE=TRUE

UPC_T_SPI_CLK

MAKE_BASE=TRUE

UPC_T_SPI_CS_L

MAKE_BASE=TRUE

UPC_T_SPI_MOSI

MAKE_BASE=TRUE

UPC_T_SPI_MISO

MAKE_BASE=TRUE

JTAG_ISP_TDO

MAKE_BASE=TRUE

TBT_POC_RESET

MAKE_BASE=TRUE

DDI1_MUX_SEL

MAKE_BASE=TRUE

DDI2_MUX_SEL

MAKE_BASE=TRUE

TBT_X_CIO_PLUG_EVENT_L

MAKE_BASE=TRUE

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

JTAG_TBT_X_TMS

MAKE_BASE=TRUE

JTAG_TBT_T_TMS

MAKE_BASE=TRUE

SMC_DEBUGPRT_TX_L

MAKE_BASE=TRUE

SMC_DEBUGPRT_RX_L

MAKE_BASE=TRUE

NC_USBC_XA_RESET_L

MAKE_BASE=TRUE

USB_UPC_PCH_XA_N

MAKE_BASE=TRUE

USB_UPC_PCH_XA_P

MAKE_BASE=TRUE

USB_UPC_PCH_XB_N

MAKE_BASE=TRUE

USB_UPC_PCH_XB_P

13

16

33 28

94 5

94 16

26

102

Alpine Ridge U2800

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

94 48 14

50 49 48

26 105 15

26

28 26

17 5

94 92

104 49 48

26

15

MAKE_BASE=TRUE

PCIE_TBT_X_D2R_C_P<0> PCIE_TBT_X_D2R_P<0>

IN OUT

PCIE_TBT_X_D2R_C_N<0>

IN

PCIE_TBT_X_D2R_C_P<1>

IN

PCIE_TBT_X_D2R_C_N<1> PCIE_TBT_X_D2R_N<1>

IN

PCIE_TBT_X_D2R_C_P<2> PCIE_TBT_X_D2R_P<2>

IN

PCIE_TBT_X_D2R_C_N<2> PCIE_TBT_X_D2R_N<2>

IN

PCIE_TBT_X_D2R_C_P<3>

IN

PCIE_TBT_X_D2R_C_N<3> PCIE_TBT_X_D2R_N<3>

IN

PCIE_TBT_X_R2D_C_P<0>

IN

PCIE_TBT_X_R2D_C_N<0>

IN

PCIE_TBT_X_R2D_C_P<1>

IN

PCIE_TBT_X_R2D_C_N<1>

IN

POWER ALIASES

PCIE_TBT_X_R2D_C_P<2>

IN

PCIE_TBT_X_R2D_C_N<2>

IN

PCIE_TBT_X_R2D_C_P<3>

IN

PCIE_TBT_X_R2D_C_N<3>

IN

PP3V3_UPC_XA_LDO

29

PP3V3_UPC_XA_LDO

29

PP3V3_UPC_XA_LDO

29

PP3V3_UPC_XB_LDO

26

PP3V3_UPC_XB_LDO

30

PP3V3_UPC_XB_LDO

30

PP3V3_UPC_XB_LDO

30

PP20V_USBC_XA_VBUS

28 29

PP20V_USBC_XB_VBUS

28 30

PP5V_S4_X_USBC

29

PP5V_S4_X_USBC

30

PP5V_S4_X_USBC

33

PP3V3_TBT_X_S0

27 101

MAKE_BASE=TRUE

PP3V3_UPC_XA_LDO

MAKE_BASE=TRUE

PP3V3_UPC_XB_LDO

MAKE_BASE=TRUE

PP20V_USBC_XA_VBUS

MAKE_BASE=TRUE

PP20V_USBC_XB_VBUS

MAKE_BASE=TRUE

PP5V_S4_X_USBC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=5V

MAKE_BASE=TRUE

PP3V3_TBT_X_S0

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

29

31

30

15

BOM_COST_GROUP=TBT

TBT

(MASTER)

I2C_TBT_X_SCL

26 28

I2C_TBT_X_SDA

26 28

I2C_TBT_XA_INT_L

26 28

I2C_TBT_XB_INT_L

26 28

Ridge PCIE Caps

GND_VOID=TRUE

X5R 20%6.3V0201

GND_VOID=TRUE

X5R0201 6.3V 20%

GND_VOID=TRUE

X5R 20%0201 6.3V

GND_VOID=TRUE

0201 20% GND_VOID=TRUE

GND_VOID=TRUE

0201 20%X5R GND_VOID=TRUE

GND_VOID=TRUE

0201 GND_VOID=TRUE

0201 X5R 20% GND_VOID=TRUE

GND_VOID=TRUE

0201 X5R

SYNC_MASTER=J79_GREG SYNC_DATE=08/08/2016

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6.3V

X5R

6.3V0201

X5R 20%0201

6.3V

X5R 20%0201 6.3V

6.3V

6.3V 20%X5R0201

6.3V0201 20%X5R

X5R 6.3V 20%

6.3V

D2R

20%X5R

20%0201 X5R 6.3V

R2D

20%X5R0201 6.3V

20%X5R0201

20%6.3V

R

(Write: 0x70 Read: 0x71)

I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XA_INT_L

(Write: 0x7E Read: 0x7F)

I2C_TBT_X_SCL I2C_TBT_X_SDA I2C_TBT_XB_INT_L

C3050

12

0.22UF

C3051

12

PCIE_TBT_X_D2R_N<0>

0.22UF

C3052

12

PCIE_TBT_X_D2R_P<1>

0.22UF

C3053

12

0.22UF

C3054

12

0.22UF

C3055

12

0.22UF

C3056

12

PCIE_TBT_X_D2R_P<3>

0.22UF

C3057

12

0.22UF

C3040

12

PCIE_TBT_X_R2D_P<0>

0.22UF

C3041

12

PCIE_TBT_X_R2D_N<0>

0.22UF

C3042

12

PCIE_TBT_X_R2D_P<1>

0.22UF

C3043

12

PCIE_TBT_X_R2D_N<1>

0.22UF

C3044

12

PCIE_TBT_X_R2D_P<2>

0.22UF

C3045

12

PCIE_TBT_X_R2D_N<2>

0.22UF

C3046

12

PCIE_TBT_X_R2D_P<3>

0.22UF

C3047

12

PCIE_TBT_X_R2D_N<3>

0.22UF

USB-C Support

Apple Inc.

Pri ACE

U3100

Sec ACE

U3200

DRAWING NUMBER SIZE

051-00515

REVISION

BRANCH

PAGE

SHEET

29

30

OUT

15

OUT

15

OUT

15

OUT

15

OUT

15

OUT

15

OUT

26

OUT

26

OUT

26

OUT

26

OUT

26

OUT

26

OUT

26

OUT

26

OUT

D

9.0.0

dvt-fab09-0

30 OF 145

28 OF 119

C

105 15

B

A

8 7 5 4 2 1

36

D

PRIMARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3100

FDPC4044

PWR-CLIP-33

345678

2 1

D

C

PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES

CAP FOR PP_5V0 ON VR PAGE

PP20V_USBC_XA_VBUS

28

PP3V3_UPC_XA_LDO

28

PP3V3_G3H

100

GND

28 30 95 96

PP5V_S4_X_USBC

28

FUSE

Add on support page

1

C3100

10UF

20%

6.3V

2

CERM-X5R 0402-1

28

PP20V_USBC_XA_VBUS_F

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=20V

1

C3101

1UF

10% 35V

2

X5R 0402

A11

B11

C11

PP_5V0

D11

PP_5V0

A6A7A8

PP_HV

B7

PP_HV

H10

H11

PP_CABLE

J10

VBUS

S2 5

J11

VBUS

G2 4

K11B1H1

VBUS

VIN_3V3

NC

VDDIO

LDO_3V3

G1

2

3

1

UPC_XA_GATE1

TP_Q3100_DRAIN

UPC_XA_GATE2

K1

H2

VOUT_3V3

A2G1E1

LDO_BMC

LDO_1V8D

LDO_1V8A

S1

8

PP1V8_UPC_XA_LDOA

PP1V8_UPC_XA_LDOD

PP1V1_UPC_XA_LDO_BMC

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.1V

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

1

C3104

2.2UF

20% 4V

2

X5R-CERM 0201

30 94 95 96 100

P3V3_TBT_X_SX_EN_R

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.8V

1

C3105

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

PP3V3_UPC_XA_LDO

32

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=1.8V

1

C3106

0.47UF

10%

6.3V

2

CERM-X5R 0201

1

C3108

10UF

20%

6.3V

2

CERM-X5R 0402-1

28

C

B

PP3V3_UPC_XA_LDO

1M

1 2

1M

1 2

1M

1 2

R3109

5% 201MF1/20W

R3108

1/20W

5% 201MF

R3105

5% MF1/20W

28

I2C_UPC_XA_DBG_CTL_SCL

I2C_UPC_XA_DBG_CTL_SDA

UPC_XA_UART_RX

201

30 28

TESTPOINTS MUST BE

29 28

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

29 28

USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR

USE GPIO3 FOR POWER_GATE_EN

ON BANSURI DESIGNS

30 28 26

28 26

96 95 30 28

GND I2C_ADDR PRIMARY ONLY

28

IN

OUT

IN

OUT

IN

TBT_POC_RESET NC_USBC_XA_RESET_L

UPC_XA_DBG_UART_TX

UPC_XA_DBG_UART_RX

TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

DP_XA_HPD

GND

UPC_X_5V_EN

SMC_PME_S4_DARK_L

XDP_USB_EXTA_OC_L

GND

UPC_XA_R_OSC

CRITICAL

R3103

30 29 28

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

1

15K

0.1% 1/20W TF-LF

0201

2

TO SMC

28

51

28

29 28

BI

OUT

BI

OUT

IN

OUT

I2C_UPC_XA_DBG_CTL_SCL I2C_UPC_XA_DBG_CTL_SDA

I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_TBT_XA_INT_L

I2C_UPC_X_SDA2

I2C_UPC_X_SCL2

SMC_USBC_INT_L

GND GND GND GND

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

PRIMARY ONLY

U3100

CD3215A

BGA

HV FET/SENSE

TYPE-C

CRITICAL OMIT_TABLE

SS

SENSEP SENSEN

HV_GATE1 HV_GATE2

C_CC1 C_CC2

RPD_G1 RPD_G2

C_USB_TP C_USB_TN

C_USB_BP C_USB_BN

C_SBU1 C_SBU2

NC

H7

B10 A10

B9 A9

L9

USBC_XA_CC1

L10

USBC_XA_CC2

K9

USBC_XA_CC1

K10

USBC_XA_CC2

K6 L6

K7 L7

K8 L8

L11

USBC_XA_USB_DBG_TOP_P USBC_XA_USB_DBG_TOP_N

USBC_XA_USB_DBG_BOT_P USBC_XA_USB_DBG_BOT_N

USBC_XA_SBU1 USBC_XA_SBU2

GROUND

NC or GND to dissipate heat

UPC_XA_SS

1

C3109

0.47UF

10%

6.3V

2

CERM-X5R 0201

BI

28

31

BI

31

1

C3114

220PF

10% 16V

2

CER-X7R 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.2000

BI

31 28

BI

1

C3113

220PF

10% 16V

2

CER-X7R 0201

104

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.2000

B

A

28

PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XA_LDO

USB_UPC_PCH_XA_P

BI

USB_UPC_PCH_XA_N

BI

PP3V3_UPC_XA_LDO

28

NO_XNET_CONNECTION=1

PLACE_NEAR=U3100:5mm

26

BI

26

BI

L3100

90-OHM-0.1A

EXCX4CE

SYM_VER-1

1

2 3

1

R3110

100K

5% 1/20W MF 201

2

TP_UPC_XA_SWD_DATA

TP_UPC_XA_SWD_CLK

30 29 28

30 28

4

26

IN

OUT

IN

OUT

UPC_XA_UART_RX UPC_XA_UART_TX

TBT_XA_LSTX TBT_XA_LSRX

USB_UPC_XA_F_P USB_UPC_XA_F_N

DP_XA_AUXCH_P DP_XA_AUXCH_N

28

BI

USB3_EXTA_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_R2D_P USB3_EXTA_R2D_N

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

A1D6E5E6E7F5G5H4H5G8H8L1B8D8E8F6F7F8G6

GND

G7

SYNC_MASTER=J79_GREG SYNC_DATE=08/08/2016

PAGE TITLE

A

1

R3111

100K

NO_XNET_CONNECTION=1

8 7 5 4 2 1

5% 1/20W MF 201

2

GND

PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION

28

BOM_COST_GROUP=USB-C

36

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

USB-C PORT CONTROLLER A

DRAWING NUMBER SIZE

Apple Inc.

R

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

31 OF 145

29 OF 119

D

SECONDARY ACE USB-C PORT CONTROLLER (UPC)

CRITICAL

Q3200

FDPC4044

PWR-CLIP-33

PP20V_USBC_XB_VBUS

28

FUSE

Add on support page

PP20V_USBC_XB_VBUS_F

28

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=20V

S2 5

G2 4

NC

345678

2 1

D

G1

S1

2

3

1

8

UPC_XB_GATE1

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

29 94 95 96 100

C

B

PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES

PP3V3_UPC_XB_LDO

1M

1 2

1M

1 2

R3209

5%

R3208

R3205

1/20W MF 201

5%

MF1/20W 201

28

I2C_UPC_XB_DBG_CTL_SCL

I2C_UPC_XB_DBG_CTL_SDA

201MF5%1M1/20W

UPC_XA_UART_TX

30

PP3V3_UPC_XB_LDO

28

1

C3201

1UF

10% 35V

2

X5R 0402

TP_Q3200_DRAIN

UPC_XB_GATE2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

PP3V3_UPC_XB_LDO

P3V3_TBT_X_SX_EN_R

28

32

PP1V8_UPC_XB_LDOA

PP3V3_G3H

100

GND

28 29 95 96

PP5V_S4_X_USBC

28

CAP FOR PP_5V0 ON VR PAGE

TBT_POC_RESET USBC_X_RESET_L_R

UPC_XB_DBG_UART_TX

28

UPC_XB_DBG_UART_RX

28

TBT_X_CIO_PWR_EN TBT_X_USB_PWR_EN

26

28

OUT

IN

DP_XB_HPD

GND

UPC_X_5V_EN

SMC_PME_S4_DARK_L

XDP_USB_EXTB_OC_L

GND

NC_UPC_XB_I2C_ADDR

TESTPOINTS MUST BE

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

29 28 26

29 28

IN

32

OUT

IN

96 95 29 28

UPC_XB_R_OSC

CRITICAL

15K

0.1% 1/20W TF-LF

0201

1

2

TO SMC

R3203

30 29 28

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

NEED 0.1%

I2C_UPC_XB_DBG_CTL_SCL

30

I2C_UPC_XB_DBG_CTL_SDA

30

28

51

28

BI

OUT

BI

OUT

IN

OUT

I2C_TBT_X_SDA I2C_TBT_X_SCL I2C_TBT_XB_INT_L

I2C_UPC_X_SDA2 I2C_UPC_X_SCL2 SMC_USBC_INT_L

UPC_XB_SPI_CLK UPC_XB_SPI_MOSI UPC_XB_SPI_MISO UPC_XB_SPI_CS_L

1

C3200

10UF

20%

6.3V

2

CERM-X5R 0402-1

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

A11

B11

PP_5V0

C11

D11

PP_5V0

A6A7A8

PP_HV

B7

PP_HV

H10

H11

J10

VBUS

PP_CABLE

U3200

CD3215A

BGA

J11

K11B1H1

VBUS

HV FET/SENSE

TYPE-C

VDDIO

VIN_3V3

CRITICAL OMIT_TABLE

K1

H2

LDO_3V3

VOUT_3V3

A2G1E1

LDO_BMC

LDO_1V8D

LDO_1V8A

SS

SENSEP SENSEN

HV_GATE1 HV_GATE2

C_CC1 C_CC2

RPD_G1 RPD_G2

C_USB_TP C_USB_TN

C_USB_BP C_USB_BN

C_SBU1 C_SBU2

NC

H7

B10 A10

B9 A9

L9

USBC_XB_CC1

L10

USBC_XB_CC2

K9

USBC_XB_CC1

K10

USBC_XB_CC2

K6

USBC_XB_USB_TOP_P

L6

USBC_XB_USB_TOP_N

K7

USBC_XB_USB_BOT_P

L7

USBC_XB_USB_BOT_N

K8

USBC_XB_SBU1

L8

USBC_XB_SBU2

GROUND

L11

NC or GND to dissipate heat

PP1V8_UPC_XB_LDOD

PP1V1_UPC_XB_LDO_BMC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.1V

UPC_XB_SS

1

C3209

0.47UF

10%

6.3V

2

CERM-X5R 0201

28

BI

28

BI

31

BI

31

BI

31

BI

31

BI

31

BI

31

BI

1

C3204

2.2UF

20% 4V

2

X5R-CERM 0201

1

C3214

220PF

10% 16V

2

CER-X7R 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V

1

C3205

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.0900

BI

1

C3213

220PF

10% 16V

2

CER-X7R 0201

104 31 28

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.0900

104 31 28

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

C3206

0.47UF

10%

6.3V

2

CERM-X5R 0201

1

C3208

10UF

20%

6.3V

2

CERM-X5R 0402-1

C

B

28

BI

USB_UPC_PCH_XB_P

USB_UPC_PCH_XB_N

PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_XB_LDO

NO_XNET_CONNECTION=1

1

2 3

28

L3200

90-OHM-0.1A

EXCX4CE

SYM_VER-1

4

PLACE_NEAR=U3200.L5:5mm

PLACE_NEAR=U3200.K5:5mm

PP3V3_UPC_XB_LDO

1

R3210

2

26

BI

26

BI

100K

5% 1/20W MF 201

30 29 28

29 28

26

42

28

TP_UPC_XB_SWD_DATA TP_UPC_XB_SWD_CLK

IN

OUT

IN

OUT

UPC_XA_UART_TX

UPC_XA_UART_RX

TBT_XB_LSTX

TBT_XB_LSRX

USB_UPC_XB_F_P USB_UPC_XB_F_N

DP_XB_AUXCH_P DP_XB_AUXCH_N

BI

SOC_SWCLK_DBG SOC_SWDIO_DBG

SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

A1D6E5E6E7F5G5H4H5G8H8L1B8D8E8F6F7F8G6

GND

G7

A

100K

5%

1/20W

MF

201

1

2

GND

PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION

28

R3211

NO_XNET_CONNECTION=1

BOM_COST_GROUP=USB-C

8 7 5 4 2 1

36

SYNC_MASTER=J79_GREG SYNC_DATE=02/28/2016

PAGE TITLE

USB-C PORT CONTROLLER B

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

32 OF 145

30 OF 119

A

D

345678

2 1

D

C

B

CC1

104 30 28

TBT_R2D0

TBT_D2R0

SBU2

USB2 BOT

SBU1

TBT_R2D1

TBT_D2R1

CC2

104 29 28

28

CRITICAL

D3300

NSR20F40NX_G

BI

26

IN

26

IN

26

OUT

26

OUT

30

BI

30

BI

30

BI

29

BI

29

BI

29

BI

26

IN

26

IN

26

OUT

26

OUT

BI

VOLTAGE=20V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

USBC_XB_CC1

USBC_XB_R2D_C_N<1>

USBC_XB_R2D_C_P<1> USBC_XB_D2R_N<1> USBC_XB_D2R_P<1> USBC_XB_SBU2 USBC_XB_USB_BOT_N USBC_XB_USB_BOT_P

USBC_XA_USB_DBG_BOT_N USBC_XA_USB_DBG_BOT_P

USBC_XA_SBU1

USBC_XA_R2D_C_P<2>

USBC_XA_R2D_C_N<2>

USBC_XA_D2R_P<2>

USBC_XA_D2R_N<2>

USBC_XA_CC2

PP20V_USBC_XA_VBUS

OMIT_TABLE

K

DSN2

A

C3304

1UF

10% 25V X5R 402

VOLTAGE=20V

28

GND_VOID=TRUE

DZ3301

0201-THICKSTNCL

1

2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

PP20V_USBC_XB_VBUS

GND_VOID=TRUE

C3391

GND_VOID=TRUE

C3390

GND_VOID=TRUE

2

ESD8011

D3354

1

X3DFN2-THICKSTNCL

1

GND_VOID=TRUE

C3373

GND_VOID=TRUE

C3372

GND_VOID=TRUE

2

ESD8011

1

5.5V-6.2PF

K

D3327

1610

X3DFN2-THICKSTNCL

XW3300

SM

ESDA25P35-1U1M

D3301

A

CRITICAL

D3370

DSN2

NSR20F40NX_G

1 2

ESD8011

D3349

DZ3350

X3DFN2-THICKSTNCL

1 2

GND_VOID=TRUE

2

1

12

0.22UF

10%

0.22UF

10%

D3326

VOLTAGE=20V

OMIT_TABLE

K

A

0.22UF

2

1

5.5V-6.2PF

0201-THICKSTNCL

GND_VOID=TRUE

C3354

GND_VOID=TRUE

6.3V10% X5R-CERM 0201

GND_VOID=TRUE

6.3V

X5R-CERM10%

1

1UF

10% 25V

2

X5R 402

0201

GND_VOID=TRUE

ESD8011

D3353

X3DFN2-THICKSTNCL

GND_VOID=TRUE

2

1

USBC_XA_R2D_P<2>

0201X5R-CERM6.3V

GND_VOID=TRUE

USBC_XA_R2D_N<2>

X5R-CERM

GND_VOID=TRUE

ESD8011

X3DFN2-THICKSTNCL

ESD8011

D3325

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

02016.3V

GND_VOID=TRUE

2

1

X3DFN2-THICKSTNCL

D3324

PP20V_USBC_XA_VBUS_CONN

BYPASS=J3300.59::2MM

K

1610

ESDA25P35-1U1M

D3302

A

USBC_XB_R2D_N<1>

USBC_XB_R2D_P<1>

2

ESD8011

1

ESD8011

X3DFN2-THICKSTNCL

D3352

5.5V-6.2PF

DZ3303

0201-THICKSTNCL

CRITICAL

1

C3300

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3306

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.59::2MM

XW3350

SM

12

GND_VOID=TRUE

2

ESD8011

D3351

X3DFN2-THICKSTNCL

2

1

BYPASS=J3300.59::2MM

X3DFN2-THICKSTNCL

GND_VOID=TRUE

ESD8011

D3312

X3DFN2-THICKSTNCL

1

2

1

BYPASS=J3300.59::2MM

CRITICAL

1

C3301

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3307

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.59::2MM

VOLTAGE=20V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

ESD8011

D3350

X3DFN2-THICKSTNCL

ESD8011

D3328

X3DFN2-THICKSTNCL

PLACE VBUS CAP NEAR EACH VBUS PIN

CRITICAL

1

C3302

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3308

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.59::2MM

PP20V_USBC_XB_VBUS_CONN

2

5.5V-6.2PF

DZ3352

0201-THICKSTNCL

BYPASS=J3300.59::2MM

1

BYPASS=J3300.59::2MM

CRITICAL

1

C3303

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3309

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.59::2MM

CRITICAL

1

C3312

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3305

0.01UF

10% 25V

2

X5R-CERM 0201

TP_USBC_PP20V_XB

J3300

20759-056E-02

F-ST-SM

57 58

PWR

SIGNAL

1 2 3 4 5 6

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE

7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

PWR

59 60

GND

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

NC_USBC_PP20V_XA

BYPASS=J3300.58::2MM

104

OUT

2

1

5.5V-6.2PF

DZ3351

0201-THICKSTNCL

2

1

5.5V-6.2PF

DZ3300

0201-THICKSTNCL

NC_USBC_PP20V_XA

MAKE_BASE=TRUE NO_TEST=1

D3321

PP20V_USBC_XA_VBUS_CONN

CRITICAL

1

C3350

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3356

0.01UF

10% 25V

2

X5R-CERM 0201

1

C3360

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

GND_VOID=TRUE

2

ESD8011

D3355

GND_VOID=TRUE

2

ESD8011

1

X3DFN2-THICKSTNCL

1

X3DFN2-THICKSTNCL

2

1

BYPASS=J3300.58::2MM

CRITICAL

1

C3351

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.58::2MM

CRITICAL

1

C3357

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.58::2MM

1

C3366

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

USBC_XB_R2D_N<2>

USBC_XB_R2D_P<2>

2

ESD8011

1

D3356

D3358

X3DFN2-THICKSTNCL

USBC_XA_R2D_P<1>

USBC_XA_R2D_N<1>

GND_VOID=TRUE

2

ESD8011

D3320

X3DFN2-THICKSTNCL

ESD8011

D3304

1

X3DFN2-THICKSTNCL

PLACE VBUS CAP NEAR EACH VBUS PIN

BYPASS=J3300.58::2MM

CRITICAL

1

C3352

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=J3300.58::2MM

CRITICAL

1

C3358

0.01UF

10% 25V

2

X5R-CERM 0201

1

C3361

12PF

5% 25V

2

NP0-C0G 0201

GND_VOID=TRUE

2

ESD8011

1

X3DFN2-THICKSTNCL

2

ESD8011

1

104 31

D3329

BYPASS=J3300.58::2MM

CRITICAL

1

C3353

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

C3359

0.01UF

10% 25V

2

X5R-CERM 0201

1

C3363

12PF

5% 25V

2

NP0-C0G 0201

GND_VOID=TRUE

C3392

GND_VOID=TRUE

C3393

GND_VOID=TRUE

ESD8011

D3360

ESD8011

D3359

X3DFN2-THICKSTNCL

GND_VOID=TRUE

X3DFN2-THICKSTNCL

C3370

GND_VOID=TRUE

C3371

GND_VOID=TRUE

2

ESD8011

D3323

X3DFN2-THICKSTNCL

1

X3DFN2-THICKSTNCL

CRITICAL

1

C3362

0.01UF

10% 25V

2

X5R-CERM 0201

1

C3364

12PF

5% 25V

2

NP0-C0G 0201

1 2

10% 6.3V

GND_VOID=TRUE

2

1

1 2

10%

2

ESD8011

1

D3322

BYPASS=J3300.58::2MM

CRITICAL

1

C3355

0.01UF

10% 25V

2

X5R-CERM 0201

1

C3365

12PF

5% 25V

2

NP0-C0G 0201

USBC_XB_CC2

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

ESD8011

D3357

X5R-CERM 0201

X3DFN2-THICKSTNCL

DZ3353

USBC_XB_R2D_C_N<2>

0201X5R-CERM6.3V10%

USBC_XB_R2D_C_P<2>

2

1

5.5V-6.2PF

0201-THICKSTNCL

USBC_XA_SBU2

GND_VOID=TRUE

0.22UF

6.3V10% 0201

GND_VOID=TRUE

0.22UF

6.3V 0201X5R-CERM

X5R-CERM

USBC_XA_USB_DBG_TOP_P USBC_XA_USB_DBG_TOP_N

USBC_XA_D2R_P<1> USBC_XA_D2R_N<1>

USBC_XA_CC1

2

X3DFN2-THICKSTNCL

5.5V-6.2PF

DZ3302

1

0201-THICKSTNCL

USBC_XB_USB_TOP_P USBC_XB_USB_TOP_N USBC_XB_D2R_N<2> USBC_XB_D2R_P<2>

USBC_XB_SBU1

USBC_XA_R2D_C_P<1>

USBC_XA_R2D_C_N<1>

IN

OUT

BI

IN

OUT

BI

26

30

26

29

104

104 30 28

CC2

TBT_R2D1

USB2 TOP

TBT_D2R1

SBU1

SBU2

TBT_R2D0

USB2 BOT

TBT_D2R0

29 28

CC1

D

C

B

A

1

C3310

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C3316

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C3311

12PF

5% 25V

2

NP0-C0G 0201

1

C3313

12PF

5% 25V

2

NP0-C0G 0201

1

C3314

12PF

5% 25V

2

NP0-C0G 0201

1

C3315

12PF

5% 25V

2

NP0-C0G 0201

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

138S0683 2 NOSTUFF

CAP,CER,X5R,1UF,10%,25V,0402

C3304, C3354

CRITICAL

LAST CHANGE: Wed Apr 1 22:57:37 2015

SYNC_MASTER=J79_GREG SYNC_DATE=07/05/2016

PAGE TITLE

USB-C CONNECTOR A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=USB-C

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

33 OF 145

SHEET

31 OF 119

A

8 7 5 4 2 1

36

345678

2 1

D

TBT X "POC" Power-up Reset

C

29

30

IN

P3V3_TBT_X_SX_EN_R

MAKE_BASE=TRUE

P3V3_TBT_X_SX_EN_R

R3401

0

1 2

5%

1/20W

MF

201

1

R3404

100K

5% 1/20W MF 201

2

P3V3_TBT_X_SX_EN

30

IN

1

USBC_X_RESET_L_R

NOSTUFF

R3400

0

1 2

5%

402

1/16WMF-LF

CRITICAL

U3400

SLG5AP1449V

STDFN

ON

GND

4

2

D

3

S

1

R3402

100K

1% 1/20W MF 201

2

MAKE_BASE=TRUE

PP3V3_S5

USBC_X_RESET_L_R

TBTXPOCRST_SNS

CRITICAL

TPS3895ADRY

1

3

SENSE

6

VCC

U3401

USON

SENSE_OUTENABLE

MAKE_BASE=TRUE

101

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

PP3V3_S5_TBT_X_SW

Output Push-pull

Delay

Vth

4

USBC_X_RESET_L

5

CT

TBTXPOCRST_CT

27 28

26

U3401

440us +/- 20us

2.508V nominal

OUT

C

28 26

B

1

R3403

24.9K

1% 1/20W MF 201

2

NOSTUFF

GND

2

NOSTUFF

R3431

10K

1 2

5%

1/20W

MF

201

D3400

SC2

AK

DSF01S30SCAP

1

C3431

1.0UF

20%

6.3V

2

X5R 0201-1

C3400

100PF

5% 25V C0G

0201

NOSTUFF

1

2

B

A

DESIGN: X502/DEV_MLB_U

LAST CHANGE: Wed Feb 18 17:12:24 2015

SYNC_MASTER=J79_GREG

PAGE TITLE

USB-C CONNECTOR B

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=USB-C

8 7 5 4 2 1

36

.

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2016

051-00515

9.0.0

dvt-fab09-0

34 OF 145

32 OF 119

A

D

345678

2 1

D

PP5V_S4_X_USBC

28 33

2

XW3502

R3503

NO_XNET_CONNECTION=1

SM

27.4K

0.1%

1/20W

MF

0201

1

2

XW3501

SM

1

P5VUSBC_X_SENSE_DIV_XW

P5VUSBC_X_RTN_DIV_XW

1

R3531

27.4K

0.1% 1/20W MF 0201

2

NO_XNET_CONNECTION=1

1

R3517

191K

0.1% 1/20W MF 0201

2

1

C3517

22PF

5% 50V

2

C0G 0201

PP5V_USBC_X_VCC

MIN_NECK_WIDTH=0.0520 VOLTAGE=5V

1

C3522

2.2UF

10% 10V

2

X6S-CERM 0402

28

IN

33

PP5V_S4

101

UPC_X_5V_EN

P5VUSBC_X_SENSE_DIV

P5VUSBC_X_SREF

P5VUSBC_X_VO

P5VUSBC_X_OCSET

P5VUSBC_X_PGOOD

P5VUSBC_X_RTN_DIV

P5VUSBC_X_FSEL

10

7

12

11

14

13

4

R3501

EN

FB

SREF

VO

OCSET

PGOOD

RTN

FSEL

1

2.2

5%

1/20W

MF

201

2

19

U3500

ISL95870AH

UTQFN

CRITICAL

1

2

20

PVCCVCC

R3506

2.2

5% 1/20W

PP5V_USBC_X_PVCC

MF 201

UGATE

PHASE

LGATE

BOOT

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=5V

1

2

1815

17

16

1

C3521

10UF

20% 10V X5R-CERM 0402-7

P5VUSBC_X_VBST

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

GATE_NODE=TRUE MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

P5VUSBC_X_DRVH

P5VUSBC_X_LL

MIN_LINE_WIDTH=0.0900

DIDT=TRUE MIN_NECK_WIDTH=0.0520 SWITCH_NODE=TRUE

DIDT=TRUE

P5VUSBC_X_DRVL

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUE DIDT=TRUE

PPBUS_G3H

99 100

R3509

2.2

5%

1/20W

MF

201

P5VUSBC_X_BOOT_RC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

1

2

C3516

0.1UF

10% 16V

2

X7R-CERM 0402

R3539

1 2

GATE_NODE=TRUE MIN_NECK_WIDTH=0.0520

0

MIN_LINE_WIDTH=0.0900

5%

1/20W

P5VUSBC_X_DRVH_R

MF

201

C3504

33UF

TANT-POLY

CASE-B3

Q3501

FDPC1012S

1

HSG

2

SW

3 4

20% 16V

1

2

LLP

C3503

33UF

20% 16V

TANT-POLY

CASE-B3

V+

8

V+

9

LSG

7

1

C3500

2.2UF

20% 25V

2

X5R-CERM 0402-1

20% 16V

1

2

1

C3502

33UF

2

TANT-POLY

CASE-B3

L3500

1.5UH-20%-12.5A-0.017OHM

1 2

PIMB062D-SM

1

C3501

2.2UF

20% 25V

2

X5R-CERM 0402-1

P5VUSBC_X_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=5V

P5VUSBC_X_POS

CRITICAL

R3530

0.002

1%

1/2W

MF

0306

12 34

C3505

2.2UF

20% 25V

X5R-CERM

0402-1

PP5V_S4_X_USBC

CRITICAL

1

C3510

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE

20% 25V

1

2

1

C3506

2.2UF

2

X5R-CERM

0402-1

5G DESENSE

1

C3508

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

CRITICAL

1

C3511

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

2

C3507

150UF

20%

6.3V TANT-POLY CASE-B1S-1

28 33 MIN_LINE_WIDTH=0.0900

D

C

1

C3526

10PF

5% 50V

2

C0G 0201

1

R3504

10K

0.1% 1/20W MF 0201-1

2

1

R3502

10K

0.1% 1/20W MF 0201-1

2

C3523

1

C3515

10PF

5% 50V

2

C0G 0201

0.1UF

10% 16V

X5R-CERM

0201

P5VUSBC_X_SET0

P5VUSBC_X_SET1

1

2

1

R3518

95.3K

0.1% 1/20W MF 0201

2

P5VUSBC_X_SET_R

NOSTUFF

R3513

5%

1/20W

MF

201

1

0

2

R3500

11K

1 2

1%

1/20W

MF

201

8

SET0

9

SET1

6

VID0

5

VID1

PGNDGND

3

2

GND

5

GND

6

GND

10

R3521

2.55K

1%

1/20W

MF

201

1

C3570

2

2200PF

12

P5VUSBC_X_NEG

1

C3509

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

Vout = 5.036V

10% 25V

CER-X7R

0201

1

R3572

2.55K

1% 1/20W MF 201

2

Freq = 500 kHz Max OCP = 13.05A

Nom OCP = 10.84A

C

Min OCP = 7.94A

P5VUSBC_X_AGND

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0V

XW3500

SM

1 2

PLACE_NEAR=U3500.2:1mm

33

P5VUSBC_X_PGOOD

P2MM

1

SM

PP

PP3500

IccMax = 6.6A

B

A

PAGE TITLE

TBT 5V REGULATOR

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=USB-C

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=12/18/2015SYNC_MASTER=J79_JSHAO

051-00515

9.0.0

dvt-fab09-0

35 OF 145

33 OF 119

A

D

PP3V3_S0

34 101 106

345678

2 1

D

C

OUTPUT CONNECTIONS SWAPPED COMPARED TO ARCHITECTURE

SEL LOGIC INVERTED TO MAINTAIN CORRECT PAK LOGIC

MANUAL STRAPS

PP3V3_S0

34 101 106

TOWARDS AR T SNK1

TOWARDS AR X SNK0

1

R3604

100K

5%

1/20W

MF

201

2

92

26

OUT

BI

OUT

94 92 34

34 28 26

DP_T_SNK1_ML_C_P<0> DP_T_SNK1_ML_C_N<0>

DP_T_SNK1_ML_C_P<1> DP_T_SNK1_ML_C_N<1>

DP_T_SNK1_ML_C_P<2> DP_T_SNK1_ML_C_N<2>

DP_T_SNK1_ML_C_P<3> DP_T_SNK1_ML_C_N<3>

DP_T_SNK1_AUXCH_C_P DP_T_SNK1_AUXCH_C_N

IN

DP_T_SNK1_HPD

DP_X_SNK0_ML_C_P<0> DP_X_SNK0_ML_C_N<0>

DP_X_SNK0_ML_C_P<1> DP_X_SNK0_ML_C_N<1>

DP_X_SNK0_ML_C_P<2> DP_X_SNK0_ML_C_N<2>

DP_X_SNK0_ML_C_P<3> DP_X_SNK0_ML_C_N<3>

DP_X_SNK0_AUXCH_C_P DP_X_SNK0_AUXCH_C_N

IN

DP_X_SNK0_HPD

DDI1_MUX_SEL_INV

NC NC

B4 A4

B5 A5

B6 A6

A8 A9

H9 J9

H8 J8

J2

B8 B9

D8 D9

E8 E9

F8 F9

H6 J6

H5 J5

H3

A1

D0+A D0-A

D1+A D1-A

D2+A D2-A

D3+A D3-A

AUX+A AUX-A

SCL_A SDA_A

HPD_A

D0+B D0-B

D1+B D1-B

D2+B D2-B

D3+B D3-B

AUX+B AUX-B

SCL_B SDA_B

HPD_B

GPU_SEL

A2

J4

VDD

U3600

PI3WVR12612NEE

BGA

CRITICAL

D0+ D0-

D1+ D1-

D2+ D2-

D3+ D3-

AUX+ AUX-

HPD

SCL SDA

DDC_AUX_SEL

B2 B1

D2 D1

E2 E1

F2 F1

H2 H1

J1

J3 J7 C2

1

C3600

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U3600.J4::5MM

DP_DDI1_ML_C_P<0> DP_DDI1_ML_C_N<0>

DP_DDI1_ML_C_P<1> DP_DDI1_ML_C_N<1>

DP_DDI1_ML_C_P<2> DP_DDI1_ML_C_N<2>

DP_DDI1_ML_C_P<3> DP_DDI1_ML_C_N<3>

DP_DDI1_AUXCH_C_P DP_DDI1_AUXCH_C_N

DP_DDPB_HPD

NC NC

IN

5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

BI

OUT

1

R3600

100K

5% 1/20W MF

2

201

D

105 5

FROM CPU

5

C

B

A

94 92 34

34 28 26

92

26

OUT

IN

DDI1_MUX_SEL

DP_T_SNK0_HPD DP_T_SNK1_HPD

DP_X_SNK0_HPD DP_X_SNK1_HPD

PP3V3_S0

34 101 106

BYPASS=U3620.1::5MM

26

92

OUT

10%

6.3V 0201

1

2

C3620

0.1UF

CERM-X5R

SLG4AP4971

3

HPD_T0

2

HPD_T1

5

HPD_X0

4

HPD_X1

OMIT_TABLE

DDI2_MUX_SEL

DDI1_MUX_SEL

1

VDD

U3620

STQFN

GND

11

MAKE_BASE=TRUE

100K

5%

1/20W

MF

201

SEL_GM0 SEL_GM1

OE_GM_0 OE_GM_1

FLAG

NC

1

2

10 9

12 13

8 7

6

14 15 16 17 18 19 20

R3621

SEL_GM0_INV SEL_GM1_INV

TP_DPMUX_SAK_13

TP_DPMUX_SAK_6

NC_DPMUX_SAK_14 NC_DPMUX_SAK_15 NC_DPMUX_SAK_16 NC_DPMUX_SAK_17 NC_DPMUX_SAK_18 NC_DPMUX_SAK_19 NC_DPMUX_SAK_20

106

102

R3602

100K

5%

1/20W

MF

201

TOWARDS AR T

SNK0

TOWARDS AR X

SNK1

R3611

100K

5%

1/20W

MF

201

DDI1_MUX_EN

1

DISP MUX GPU_SEL

B7

OE

GND

B3C8G8H4H7

GND

G2

0 = TBT T 1 = TBT X

2

PP3V3_S0

34 101 106

1

C3610

A2

J4

92

26

OUT

BI

94 92 34

OUT

34 28 26

DP_T_SNK0_ML_C_P<0> DP_T_SNK0_ML_C_N<0>

DP_T_SNK0_ML_C_P<1> DP_T_SNK0_ML_C_N<1>

DP_T_SNK0_ML_C_P<2> DP_T_SNK0_ML_C_N<2>

DP_T_SNK0_ML_C_P<3> DP_T_SNK0_ML_C_N<3>

DP_T_SNK0_AUXCH_C_P DP_T_SNK0_AUXCH_C_N

IN

DP_T_SNK0_HPD

DP_X_SNK1_ML_C_P<0> DP_X_SNK1_ML_C_N<0>

DP_X_SNK1_ML_C_P<1> DP_X_SNK1_ML_C_N<1>

DP_X_SNK1_ML_C_P<2> DP_X_SNK1_ML_C_N<2>

DP_X_SNK1_ML_C_P<3> DP_X_SNK1_ML_C_N<3>

DP_X_SNK1_AUXCH_C_P DP_X_SNK1_AUXCH_C_N

IN

DP_X_SNK1_HPD

MAKE_BASE=TRUE

NC NC

DDI2_MUX_SEL

DDI2_MUX_EN

1

R3612

100K

5%

1/20W

MF

2

201

2

DISP MUX GPU_SEL

0 = TBT T 1 = TBT X

B4 A4

B5 A5

B6 A6

A8 A9

H9 J9

H8 J8

J2

B8 B9

D8 D9

E8 E9

F8 F9

H6 J6

H5 J5

H3

A1

B7

D0+A D0-A

D1+A D1-A

D2+A D2-A

D3+A D3-A

AUX+A AUX-A

SCL_A SDA_A

HPD_A

D0+B D0-B

D1+B D1-B

D2+B D2-B

D3+B D3-B

AUX+B AUX-B

SCL_B SDA_B

HPD_B

GPU_SEL

OE

VDD

U3610

PI3WVR12612NEE

BGA

CRITICAL

DDC_AUX_SEL

GND

B3C8G8H4H7

GND

G2

D0+ D0-

D1+ D1-

D2+ D2-

D3+ D3-

AUX+ AUX-

HPD

SCL SDA

B2 B1

D2 D1

E2 E1

F2 F1

H2 H1

J1

J3 J7 C2

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U3610.J4::5MM

DP_DDI2_ML_C_P<0> DP_DDI2_ML_C_N<0>

DP_DDI2_ML_C_P<1> DP_DDI2_ML_C_N<1>

DP_DDI2_ML_C_P<2> DP_DDI2_ML_C_N<2>

DP_DDI2_ML_C_P<3> DP_DDI2_ML_C_N<3>

DP_DDI2_AUXCH_C_P DP_DDI2_AUXCH_C_N

DP_DDPC_HPD

NC NC

105 5

IN

105 5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

5

BI

5

BI

OUT

1

FROM CPU

5

R3610

100K

5% 1/20W MF

2

201

BOM_COST_GROUP=GRAPHICS

SYNC_MASTER=J79_GREG SYNC_DATE=02/28/2016

PAGE TITLE

Display Mux

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

36 OF 145

SHEET

34 OF 119

D

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196

U3730

LBEE5UQ1HG-844

LGA

SYM 2 OF 2

THRM_PADTHRM_PAD

197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292

PP3V3_S4_BT

101

MAKE_BASE=TRUE

PP3V3_S4_BT

35

1

C3761

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

2

PP3V3_S4_BT

C3740

12PF

5% 25V NP0-C0G 0201

1

C3736

10UF

20%

6.3V

2

CERM-X5R 0402-4

35

106 53 36 35

35

1

C3762

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

FEM SUPPLY SHUNT CAPACITORS PLACE ON THE TOP SIDE CLOSE TO U3730

SROM_STRAPS

PP3V3_S4_WLAN_SW

35

NOSTUFF

R3731

10K

5%

1/20W

MF

201

WLAN_STRAP_0

35

STRAP_0 HI:SROM (Default) STRAP_1 LO:16kb SROM

19 14

IN

PP3V3_S4_BT

35

R3751

BT_SPI2_CSN

35

PP3V3_S4_WLAN_SW

35

SPROM_DOUT SPROM_DIN

35 35

SPROM_CS

35

SPROM_CLK

35

NC

WLAN_STRAP_1

35

1

2

R3734

10K

5%

1/20W

MF

201

PCH_BT_ROM_BOOT

100K

5%

1/20W

MF

201

1

2

R3752

100K

1/20W

201

8

VCC

U3710

CAS93C86B

3 4 1 2

7

UDFN8

CS SK

PE

OMIT_TABLE

5

DODI

ORG

EPADGND

9

1

2

5%

MF

2

1

2

R3754

1 2

1/20W

1

C3711

0.1UF

10% 35V

2

CER-X5R 0201

6

WIFI_SROM_ORG

1

GS

Q3701

DMN32D2LFB4

DFN1006H4-3

R3753

100K

1/20W

1K

5%

MF

201

BT_SFLASH_WP_L

BT_SFLASH_HOLD_L

WLAN SERIAL EEPROM

1

C3763

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

35

NOSTUFF

1

R3701

1K

5% 1/20W MF 201

2

SYM_VER_3

D

3

BLUETOOTH SERIAL FLASH

1

5%

MF

201

2

R3712

10K

5%

MF

201

PP3V3_S4_WLAN_SW

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S4_WLAN_SW

35

1

C3742

12PF

5% 25V

2

NP0-C0G 0201

1

R3759

270K

5% 1/20W MF 201

2

BT_SPI2_CLK

35

BT_SFLASH_CS_L

12

PP3V3_S4_WLAN_SW

1

C3741

12PF

5% 25V

2

NP0-C0G 0201

35

1

C3737

10UF

20%

6.3V

2

CERM-X5R 0402-4

50 35

WLAN_UART_RX WLAN_UART_TX

WLAN_JTAG_TDI WLAN_JTAG_TMS WLAN_JTAG_TCK WLAN_JTAG_TRST_L

WLAN_JTAG_SEL WLAN_EXT_POR_L

35

35 13 6

35

35 19

35

NC

IN

CORE2_5G_CTL2_WLAN_JTAG_TDO

WLAN_STRAP_0

35

WLAN_STRAP_1

SPROM_CLK SPROM_DOUT SPROM_CS SPROM_DIN

BT_SPI2_MOSI BT_SPI2_CSN BT_SPI2_MISO BT_SPI2_CLK

BT_ROM_BOOT_L

35

BT_TIMESTAMP

8

OMIT_TABLE

VCC

U3750

2MBIT

6

SCLK

USON

SI/SIO0

MX25L2006EZUI-12G

1

3

7

CS* WP*

HOLD*

GND

4

SO/SIO1

THRM

PAD

9

PP1V8_S4

1

C3780

0.1UF

10% 10V

2

X5R-CERM

4

VCC

CRITICAL

0201

BYPASS=U3780.4::5MM

U3780

32.768KHZ-25PPM-15PF-5.5V

2.50X2.00-SM-COMBO

1

EN/DIS OUT

GND

2

3

19

SYSCLK_CLK32K_OSC_OUT

PRECISION ELPO

35

1

C3738

10UF

20%

6.3V

2

CERM-X5R 0402-4

36

BI

36

BI

36

BI

36

BI

36

BI

36

BI

5

2

R3780

1 2

FOR JTAG MODE REMOVE R3735

NO_XNET_CONNECTION=1

R3735

0

12

WLAN_1P2V_EN

5%

1/20W

MF

201

45

NC

50_G_0_MATCH 50_G_1_MATCH

50_G_2_MATCH

50_A_0_MATCH 50_A_1_MATCH

50_A_2_MATCH

1

C3756

0.1UF

10% 35V

2

CER-X5R 0201

BT_SPI2_MOSI

BT_SPI2_MISO

18 19 100

0

5%

1/20W

MF

201

SYSCLK_CLK32K_WIFIBT

35

BT_RF1

47

2G_ANT_CORE0

63

2G_ANT_CORE1

78

2G_ANT_CORE2

61

5G_ANT_CORE0

74

5G_ANT_CORE1

85

5G_ANT_CORE2

22

WL_GPIO_6/UART_RX

23

WL_GPIO_7/UART_TX

93

WL_JTAG_TDI/GPIO_3

72

WL_JTAG_TMS

71

WL_JTAG_TCK

70

WL_JTAG_TRST*

94

WL_JTAG_SEL

21

WLAN_EXT_POR*

92

WL_JTAG_TDO

91

C0_FEMCTRL_2/STRAP_0

90

C2_FEMCTRL_2/STRAP_1

97

SPROM_CLK

98

SPROM_DOUT

99

SPROM_CS

100

SPROM_DIN

58

BT_SPI2_MOSI

59

BT_SPI2_CSN

65

BT_SPI2_MISO

66

BT_SPI2_CLK

29

BT_GPIO_2/BT_JTAG_TRST_N

28

BT_GPIO_3

27

BT_GPIO_4

35 35 35

1

2

30

32

BT_VDDIO

C3757

12PF

5% 25V NP0-C0G 0201

35

19

WL_VDDIO

1

2

95

2

VDD3P3

1P2V_EN

89

96

88

68

1

C3758

12PF

5% 25V

2

NP0-C0G 0201

PP3V3_S4_BT

55

81

24

VDD_BT

VDD3P3_PAD

VDD3P3_REG1P2

VDD3P3_REG1P8

VDD3P3_FEM_CORE1

VDD3P3_FEM_CORE2

VDD3P3_FEM_CORE0

BT_OTP_VDD3P3V

PCIE_REFCLK_PC

U3730

PCIE_REFCLK_NC

LBEE5UQ1HG-844

LGA

SYM 1 OF 2

CRITICAL

BT_RX_ACTIVE/BT_GPIO_5

BT_UART_CTS*/BT_JTAG_TMS BT_UART_RTS*/BT_JTAG_TCK

BT_UART_RXD/BT_JTAG_TDI BT_UART_TXD/BT_JTAG_TDO

BT_HOST_WAKE/BT_HOST_WAKE*

GND

1

GND

3

GND

5

8

1114182026

GND

3839404446485154606264676973757677798082838486

GND

R3781

0

BT_SPI2_CLK BT_SPI2_CLK_R BT_SPI2_MISO

WIFI_DBG

1 2

5%

1/20W

MF

201

WIFI_DBG

R3782

0

1 2

5%

1/20W

MF

201

WIFI_DBG

BT_SPI2_CSN_RBT_SPI2_CSN

35 35

BT_SPI2_MOSI BT_SPI2_MOSI_R

35 35

WIFI_DBG

DEBUG CONNECTOR

WIFI_DBG

J3701

AA25D-S038VA1

F-ST-SM

39 40

50 48 36

CORE2_5G_CTL2_WLAN_JTAG_TDO

35

35 19

SMC_WIFI_PWR_EN

50 35

35 18

WLAN_UART_TX WLAN_UART_RX

WLAN_JTAG_TCK

35

WLAN_JTAG_TMS

35

WLAN_JTAG_TDI

35

WLAN_JTAG_TRST_L

35

WLAN_JTAG_SEL

35

35 19

36 19 16

AP_CLKREQ_L

AP_RESET_L AP_PCIE_WAKE_L PP3V3_S4_WLAN_SW

35

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

41 42

BT_LOW_PWR_L SMC_PME_S4_DARK_L SMC_BT_PWR_EN BT_UART_D2R BT_UART_R2D BT_UART_CTS_R2D_L BT_UART_RTS_D2R_L BT_SPI2_CLK_R BT_SPI2_CSN_R BT_SPI2_MISO_R BT_SPI2_MOSI_R BT_ROM_BOOT_L BT_TIMESTAMP BT_SWDIO

BT_SWDCLK

SYSCLK_CLK32K_WIFIBT

PP3V3_S4_WLAN_SW

C3704

10UF

20%

6.3V CERM-X5R 0402-4

PCIE_RDP PCIE_RDN PCIE_TDP PCIE_TDN

PCIE_WAKE_CL PCIE_CLKREQ*

PCIE_PRST*

BT_SWDIO

BT_SWDCLK

WL_XTAL32 BT_XTAL32

BT_DEV_WAKE

BT_PCM_SYNC

BT_PCM_IN BT_PCM_OUT BT_PCM_CLK

BT_RST*

BT_JTAG_SEL

GND

87

R3783

0

1 2

5%

1/20W

MF

201

35

35 50

48 35

35

BOM_COST_GROUP=WIRELESS

PP3V3_S4_WLAN_SW

1

C3705

0.1UF

10% 35V

2

CER-X5R 0201

C3739

10UF

CERM-X5R

0402-4

6

PCIE_AP_R2D_P

7

PCIE_AP_R2D_N

10

PCIE_AP_D2R_P

9

PCIE_AP_D2R_N

13

PCIE_CLK100M_AP_P

12

PCIE_CLK100M_AP_N

15

AP_PCIE_WAKE_L

16

AP_CLKREQ_L

17

AP_RESET_CONN_L

43

41

BT_UART_CTS_R2D_L

42

BT_UART_RTS_D2R_L

36

BT_UART_R2D

37

BT_UART_D2R

57

BT_SWDIO

56

BT_SWDCLK

4 25

33 35

49 50 52 53

31

34

WL_CLK32K

BT_LOW_PWR_L

35

BT_I2S_SYNC BT_I2S_R2D BT_I2S_D2R BT_I2S_CLK

SMC_BT_PWR_EN

NC

BT_SPI2_MISO_R

R3784

0

1 2

5%

1/20W

MF

201

BT_ROM_BOOT_L BT_TIMESTAMP

35 19

1

20%

6.3V 2

BT_RX_ACTIVE

SMC_PME_S4_DARK_L

35

OUT

IN

OUT

BI

IN

35

19

48 35

104 35 19 14

35 13 6

PP3V3_S4_BT

1

C3701

0.1UF

10% 35V

2

CER-X5R 0201

15

105 15

35 18

35 19

36

PP3V3_S4_WLAN_SW

BT_LOW_PWR_L

MAKE_BASE=TRUE

BT UART TX & RTS ISOLATION CIRCUIT

35

IN

35

BT UART RX & CTS ISOLATION CIRCUIT

16

IN

16

IN

35

PP3V3_S4_BT

1

C3703

0.1UF

10% 35V

2

CER-X5R 0201

PP3V3_S4_WLAN_SW

35

1

C3702

0.1UF

10% 35V

2

CER-X5R 0201

35

C3760

C3759

0.1UF

12

GND_VOID=TRUEGND_VOID=TRUE

10%

6.3V X7R

0201

R3762

10K

5%

MF

201

12

0.1UF

12

10%

6.3V X7R

0201

35

GND_VOID=TRUEGND_VOID=TRUE

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

BT_UART_CTS_R2D_L

BT_UART_RTS_D2R_L

IN

R3766

100K

5%

1/20W

MF

201

R3767

100K

5%

1/20W

MF

201

15

IN

15

12

PP3V3_S4_BT

12

R3776

100K

1/20W

R3777

100K

1/20W

Q3702

DMN32D2LFB4

1

GS

2

DFN1006H4-3

SYM_VER_3

D

3

BT_UART_R2D

35

106 53 36 35

BT_UART_D2R

35

SYSCLK_CLK32K_WIFIBT

50 35

PP3V3_S4_BT

35

8

VCC

IN

OUT

14

U3760

74LVC2G126

X2-DFN2010

2

CRITICAL

1

1OE

BT_UART_D2R PCH_BT_UART_D2R PLT_RST_L

5

A2

7

2OE

GND

4

PP3V3_S4_BT

35

8

VCC

Y1A1

Y2

6

3

PCH_BT_UART_CTS_LBT_UART_RTS_D2R_L

U3770

74LVC2G126

X2-DFN2010

PCH_BT_UART_RTS_L

PLT_RST_L

SYNC_MASTER=J79_METE SYNC_DATE=05/17/2016

PAGE TITLE

2

1

1OE

5

7

CRITICAL

A2

2OE

GND

6

Y1A1

3

Y2

4

BT_UART_CTS_R2D_L

BT_UART_R2DPCH_BT_UART_R2D

5%

MF

201

5%

MF

201

12

1

C3764

0.1UF

10% 35V

2

CER-X5R 0201

1

C3774

0.1UF

10% 35V

2

CER-X5R 0201

WIFI/BT: MODULE 1

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

37 OF 145

SHEET

35 OF 119

35

OUT

D

35

C

35 19

16

B

A

D

8 7 5 4 2 1

36

345678

CORE0 DIPLEXER AND MATCHING

50_G_0_DIPLEXER

NO STUFF

C3812

0.2PF

+/-0.05PF

25V

COG-CERM

0201

2 1

CRITICAL

L3811

2.7NH+/-0.1NH-0.6A

1 2

0201

1

2

50_G_0_MATCH

NO STUFF

1

C3810

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

35

D

C

35

WLAN Power Switch

1

VDD

U3840

SLG5AP1443V

WIFI_SW_CAP

1

C3841

4700PF

10% 10V

2

X7R 201

7 3

CAP

2 5

ON S

TDFN

GND

8

PP3V3_S4

D

36 101 106

PP3V3_S4_WLAN_SW_RSMC_WIFI_PWR_EN

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

CRITICAL

J3810

20449-001E-03

53 50 48 36

F-ST-SM

2

3

4

1

50_0_ANT

NO STUFF

C3817

0.2PF

+/-0.05PF

COG-CERM

25V

0201

1.2NH-+/-0.05NH-1.1A-0.04OHM

1

2

CRITICAL

L3810

1 2

0201

CRITICAL

1

C3816

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

LFD212G45MJCD900

50_0_COM

2

U3810

P3

5

LLP

GND

D

CRITICAL

4

P1

6

P2

1

3

50_A_0_DIPLEXER

NO STUFF

C3815

0.2PF

+/-0.05PF

COG-CERM

0201

1.0NH-+/-0.05NH-1.1A-0.04OHM

1

25V

2

L3814

1 2

0201

CRITICAL

50_A_0_MATCH

1

CRITICAL

L3813

5.1NH-3%-0.4A

0201

2

35

L3821

2.7NH+/-0.1NH-0.6A

CRITICAL

J3820

20449-001E-03

F-ST-SM

2

3

4

1

50_1_ANT

NO STUFF

C3827

0.2PF

+/-0.05PF

COG-CERM

25V

0201

CORE1 DIPLEXER AND MATCHING

2

U3820

P3

CRITICAL

L3820

1.2NH-+/-0.05NH-1.1A-0.04OHM

1 2

0201

1

2

CRITICAL

1

C3826

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

LFD212G45MJCD900

50_1_COM

LLP

GND

5

50_G_1_DIPLEXER

NO STUFF

25V

0201

25V

0201

1

2

1.2NH-+/-0.05NH-1.1A-0.04OHM

1

2

C3822

0.2PF

+/-0.05PF

COG-CERM

4

P1

6

P2

1

3

50_A_1_DIPLEXER

NO STUFF

C3825

0.2PF

+/-0.05PF

COG-CERM

1 2

0201

CRITICAL

L3824

1 2

0201

50_G_1_MATCH

NO STUFF

1

C3820

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

50_A_1_MATCH

1

CRITICAL

L3823

5.1NH-3%-0.4A

0201

35

C

35

B

35

AP_RESET_CONN_L

OUT

106 53 35

NOSTUFF

R3859

0

1 2

5%

1/20W

MF

201

Supervisor & CLKREQ# Isolation

PP3V3_S4_WLAN_SW

NOSTUFF

R3856

232K

1%

1/20W

MF

201

NOSTUFF

R3857

100K

5%

1/20W

MF

201

1

2

WLAN_3V3_VMON

AP_RESET_CONN_R_L

1

2

Delay = 130ms +/- 20%

NOSTUFF

PP3V3_S4

1

VDD

NOSTUFF

1

C3851

0.1UF

10% 25V

2

X6S-CERM 0201

U3850

SLG4AP041V

TDFN

2

SENSE

4

RESET*

7

IN

VREF

THRM

PAD

9

+

-

DLY

3

MR*

6

EN

8

OUT

(OD)

GND

5

36 101 106

AP_RESET_L

SMC_WIFI_PWR_EN

NC

IN

50

2

CRITICAL

L3831

2.9NH+/-0.1NH-0.6A

50_G_2_DIPLEXER

25V

0201

25V

0201

1

2

1.2NH-+/-0.05NH-1.1A-0.04OHM

1

2

CORE2 DIPLEXER AND MATCHING

CRITICAL

J3830

20449-001E-03

IN

48 36 35

35 19 16

F-ST-SM

2

3

4

1

50_2_ANT

NO STUFF

C3837

0.2PF

+/-0.05PF

25V

COG-CERM

0201

1.2NH-+/-0.05NH-1.1A-0.04OHM

1

2

CRITICAL

L3830

1 2

0201

CRITICAL

1

C3836

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

LFD212G45MJCD900

50_2_COM

2

U3830

P3

5

LLP

GND

4

P1

6

P2

1

3

50_A_2_DIPLEXER

C3832

0.2PF

+/-0.05PF

COG-CERM

NO STUFF

C3835

0.2PF

+/-0.05PF

COG-CERM

1 2

0201

CRITICAL

L3834

1 2

0201

NO STUFF

1

C3830

0.2PF

+/-0.05PF 25V

2

COG-CERM 0201

1

CRITICAL

L3833

5.1NH-3%-0.4A

0201

2

50_G_2_MATCH

50_A_2_MATCH

35

B

35

A

R3854

0

1 2

5%

1/20W

MF

201

BOM_COST_GROUP=WIRELESS

8 7 5 4 2 1

36

SYNC_MASTER=J79_METE SYNC_DATE=03/02/2016

PAGE TITLE

WIFI/BT: MODULE 2

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

SHEET

A

D

9.0.0

38 OF 145 36 OF 119

345678

2 1

D

C

B

343S00135

1 CRITICALU3900 CRITICAL SE:DEV1338S00147

IC,M8+512MB 20NM DDR,A12,S,SCK,BGA700

L3900

120-OHM-0.1A-1.5-OHM

PP1V1_SLEEP1_SW2

41

unstuff R3951 and stuff R3952 to enable boundary scan

PP1V8_SLEEP2_SW3A

NOSTUFF

1K

5%

1/20W

R3952

R3951

MF

201

1 2

SOC_JTAG_SEL

10K

5%

1/20W

MF

201

1 2

M7 needed stronger PU but should be fixed on M8

PP1V8_AWAKE_SW3C

37 38 39 41

R3953

SOC_SWDIO

42 37

PP1V8_SLEEP2_SW3A

39 41

41 37

PMU_TO_SOC_RESET_L

1 2

41 40

37

NOSTUFF

1/20W

1 2

R3973

0201

1K

5%

MF

201

1/20W

1 2

1

C3960

2

10K

5%

MF

201

100PF

5% 25V C0G 0201

32K CLK OPTION

PLACE_NEAR=U3900.AA22:3mm

R3990

0

41 19

41

IN

SOC_PMU_CLK_32K SOC_CLK_32K

IN

GREENCLK

PMU_TO_SOC_CLK_32K

SOC PMU

PP1V1_SLEEP1_SW2

41

R3901

1 2

5%

1/20W

MF

0201

SOC

R3925

0

1 2

5%

1/20W

MF

0201

PLACE_NEAR=U3900.AA22:3mm

240

1%

1/20W

MF

201

1 2

NOSTUFF

R3902

240

1/20W

1 2

SOC_DDR_RREF

41 37

41

PMU_TO_SOC_SLEEP1_PWRGD

IN

PMU_TO_SOC_SYS_ALIVE

IN

1%

MF

201

VOLTAGE=1.1V

1

C3900

0.22UF

10%

6.3V

2

X5R-CERM 0201

37

SOC_PAD_ZQ_A

NC NC NC NC NC NC

NC NC

NC

NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

NC

PP1V1_SLEEP1_PLL_DDR_FILT

PP1V1_SLEEP3_BUCK2

41

L25

DDR0_CA_0

L26

DDR0_CA_1

N26

DDR0_CA_2

N27

DDR0_CA_3

P26

DDR0_CA_4

P25

DDR0_CA_5

M26

DDR0_CK_P

M27

DDR0_CK_N

M25

DDR0_CKE

L27

DDR0_CS

J26

DDR0_DMI_0

V27

DDR0_DMI_1

E26

DDR0_DQ_0

F26

DDR0_DQ_1

G26

DDR0_DQ_2

H26

DDR0_DQ_3

G27

DDR0_DQ_4

K25

DDR0_DQ_5

H27

DDR0_DQ_6

K26

DDR0_DQ_7

AA25

DDR0_DQ_8

Y25

DDR0_DQ_9

W25

DDR0_DQ_10

Y26

DDR0_DQ_11

V26

DDR0_DQ_12

U26

DDR0_DQ_13

T26

DDR0_DQ_14

T27

DDR0_DQ_15

E27

DDR0_DQS_P_0

F27

DDR0_DQS_N_0

W26

DDR0_DQS_P_1

W27

DDR0_DQS_N_1

R26

PAD_ZQ_A

M24

DDR0_RESET_N

N24

DDR0_RREF

L24

DDR0_RET_N

P24

DDR0_SYS_ALIVE

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

N25

U21

SEP_ROM_WC

1

R3970

10K

5% 1/20W MF 201

2

39 37 38 41

PP1V8_AWAKE_SW3C

37 38 39 41

1

C3903

2

PP1V8_AWAKE_SW3C

SEP_I2C_SCL

0.1UF

10%

6.3V CERM-X5R 0201

T208

PLACE_NEAR=U3901.8:2mm

SEP ROM

8

VCC

U3901

M24128

EEPROM

VSS

MLP

THM_P

4

9

3

E2

2

E1

1

E0

7

WC*

6 5

SCL SDA

SEP_I2C_SDA

IC,RTM2,DEV,PN549A1,P61D0

IC,RTM2,MP,PN549A1,P61D0

R3900

499

PP1V8_SLEEP2_LPPLL_FILT

1

VOLTAGE=1.8V

BIIN

38 37 38 37

AA23

C3902

0.47UF

10%

6.3V

2

CERM-X5R 0201

1 2

1%

1/20W

MF

201

PP1V8_SLEEP2_SW3A

U3905

41

41 40 38 37

1

2

PP1V8_AWAKE_SW3C

1

C3918

1.0UF

20%

6.3V

2

X5R 0201-1

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

PP3V3_S0101

C3919

4.7UF

20%

6.3V X5R 402

CRITICAL SE:PRODU39051338S00097

STOCKHOLM

NC

D3

B5

C7

C6

VDD

VBAT

SIM_PMU_VCC

PVDD

G2

VUP

PP_STOCKHOLM_TVDD

PPVDD_STOCKHOLM

37

PPSVDD_STOCKHOLM

D7

E7

AVDD

TVDD

B7

SVDD

C5

VOLTAGE=1.8V

ESE_VDD

1

C3916

0.1UF

2

VOLTAGE=1.8V

1

C3915

0.1UF

10%

6.3V

2

CERM-X5R 0201

10%

6.3V CERM-X5R 0201

VOLTAGE=1.8V

1

C3925

1.0UF

20%

6.3V

2

X5R 0201-1

1

2

C3917

1.0UF

20%

6.3V X5R 0201-1

D

OMIT_TABLE

VDDIO11_PLL_DDR

VDDIO11_RET_DDR

OMIT_TABLE

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

(1 OF 7)

AOP_PSENSE_CTRL_4 AOP_PSENSE_CTRL_5 AOP_PSENSE_CTRL_6 AOP_PSENSE_CTRL_7

AOP_PSPI_CS_TRIG_3 AOP_PSPI_CS_TRIG_4

DDR0

AOP_SWD_TCK_OUT

AOP_DETECT_0 AOP_DETECT_1

AOP_PDM_CLK AOP_PDM_DAT

AOP_PLED_0 AOP_PLED_1 AOP_PLED_2 AOP_PLED_3 AOP_PLED_4 AOP_PLED_5 AOP_PLED_6 AOP_PLED_7

AOP_PSPI_MISO AOP_PSPI_MOSI AOP_PSPI_SCLK

AOP_SPI0_MISO AOP_SPI0_MOSI AOP_SPI0_SCLK

AOP_MON_0 AOP_MON_1 AOP_MON_2 AOP_MON_3 AOP_MON_4 AOP_MON_5 AOP_MON_6 AOP_MON_7

AOP_I2S0_MCK AOP_I2S1_MCK

AOP_SWD_TMS0 AOP_SWD_TMS1

AD26 AD27

AA10 AB10

AC10 Y10 AC14 AA13 AD12 AD13 AC15 AB14

AA24 W24 AA21 Y24

AD22 AD23

AD24 Y20 AB21

AC22 AC23 AD21

AE13 AE14 AB15 Y14 AE15 AD15 AA14 AC16

AA9 AB9

AE16 AD16 AB16

DFR_TOUCH_RESET_L

NC

NC NC

NC NC NC NC NC

OUT

42 37

TP_SOC_CLKOUT

41 37

NC NC

NC NC NC NC

DFR_TOUCH_SPI_CS_L

NC

DFR_TOUCH_SPI_MISO DFR_TOUCH_SPI_MOSI DFR_TOUCH_SPI_CLK

NC NC NC

SOC_TO_STOCKHOLM_DWLD_REQ

PCH_SOC_DBELL

NC

IN

PMU_TO_SOC_IRQ_L

NC NC

41 38

NC

41

41 37

NC NC

NC NC NC

SOC_JTAG_SEL

37

42

104 42

BI

IN

TP_SOC_JTAG_TRST_L

SOC_SWDIO

SOC_SWCLK TP_SOC_JTAG_TDI TP_SOC_JTAG_TDO

41 37

IN

OUT

19 14

IN

OUT

IN

PMU_TO_SOC_RESET_L

IN

PMU_TO_SOC_SLEEP1_PWRGD

41

IN

SOC_SLEEP1_REQ

OUT

SOC_WDOG_RST

37

104 42

41

42

41

37

SOC_VDD_HI_LO

OUT

37

NC NC

SOC_CLK_32K

PMU_TO_SOC_AWAKE_PWRGD SOC_AWAKE_REQ PMU_TO_SOC_RESET_L

AB12

AB11

AC13 AD10

AD9

AA11

AE10

Y12

AB13

AE11

AE12

AC11 AC12

AA22

AB24

AD11 AA12

JTAG_SEL

JTAG_TRSTN

JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO

CFSB_AOP

AOP_DDR_PWRGOOD

AOP_DDR_REQ

WDOG

SOC_VDD_HI_LO

AOP_DOCK_ATTENTION AOP_DOCK_CONNECT

RT_CLK32768

AWAKE_PWRGOOD AWAKE_REQ COLD_RESETN

I2C Pullups

VDD18_LPPLL

OMIT_TABLE

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

(2 OF 7)

AOP_SPI_CS_TRIG_10 AOP_SPI_CS_TRIG_11 AOP_SPI_CS_TRIG_12 AOP_SPI_CS_TRIG_13 AOP_SPI_CS_TRIG_14 AOP_SPI_CS_TRIG_15

AOP_LSPI_MISO AOP_LSPI_MOSI AOP_LSPI_SCLK

AOP_SPI_CS_TRIG_0 AOP_SPI_CS_TRIG_1 AOP_SPI_CS_TRIG_2 AOP_SPI_CS_TRIG_3 AOP_SPI_CS_TRIG_4 AOP_SPI_CS_TRIG_5 AOP_SPI_CS_TRIG_6 AOP_SPI_CS_TRIG_7 AOP_SPI_CS_TRIG_8 AOP_SPI_CS_TRIG_9

AOP_UART0_CTSN AOP_UART0_RTSN

AOP_UART0_RXD AOP_UART0_TXD

AOP_UART1_CTSN AOP_UART1_RTSN

AOP_UART1_RXD AOP_UART1_TXD

AOP_UART2_RXD AOP_UART2_TXD

AA20 AB22 AD25

AE20 AB17 AB18 AE21 AD19 AA17 AC19 AE22 AE23 AB19 AA18 AE24 AD20 AC21 Y18 AE25

AC17 AE18 AE17 AA15

AA16 AE19 AD17 AC18

AD18 Y16

38

IN

38

OUT

38

IN

38

OUT

38 19

MESA_PWR_EN

SOC_TO_STOCKHOLM_DEV_WAKE

SOC_SPI_BOOT_STATUS

NC NC NC

NC

NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC

NC NC

IN

1/20W

OUT

SOC_TO_STOCKHOLM_DWLD_REQ

37

UART_SOC_TO_STOCKHOLM_TXD

UART_STOCKHOLM_TO_SOC_TXD

UART_SOC_TO_STOCKHOLM_RTS_L

UART_STOCKHOLM_TO_SOC_RTS_L

SOC_TO_STOCKHOLM_EN

R3943

78.7K

1%

MF

201

47

37

1

R3941

10K

5% 1/20W MF 201

2

1

2

37

41 40 38 37

PPSVDD_STOCKHOLM

37

PP1V8_AWAKE_SW3C

1

R3942

10K

5% 1/20W MF 201

2

42

IN

38

IN

SOC_ROM_SPI_RST_L

D1

NC NC

NC NC NC NC NC

NC

SOC_ROM_SPI_CLK_R

SOC_ROM_SPI_CS_L

SOC_ROM_SPI_WP_L

IRQ

A5

SVDD_REQ

B2

DWL

A2

CLK_REQ

A3

NFC_CLK_XTAL1

C1

RX

B1

TX

D2

CTS

A1

RTS

E1

VEN

E3

SMX_RST*

E4

SMX_CLK

F4

ESE_IO1

B3

SPIM_MOSI

B4

SPIM_MISO

E6

SPIM_SCK

C3

XTAL2

1

C3920

0.1UF

10%

6.3V

2

CERM-X5R 0201

U3905

PN66VEU3-A101D004

UFLGA

AVSS

VSS

E2

D4D6F3

DVSS

B6

DVSS

C4

4MB SPI ROM

8

OMIT_TABLE

VCC

U3906

4MX8-1.8V

UFDFPN

6

C

N25Q032A11E

1

S*

3

W*/VPP/DQ2

7

HOLD*/DQ3

SPIM_IRQ SIM_SWIO

GPIO0

SPIM_NSS

TX_PWR_REQ

ESE_DWPM_DBG ESE_DWPS_DBG

WKUP_REQ

VMID

SE2_PWR_REQ SE2_SVDD_IN

TVSS

PVSS

C2

G4

DQ0

DQ1

F1

NC

A4

NC

A7

NC

A6

NC

D5

NC

G7

NC

G6

NC

F6

RXP RXN

TX1

TX2

5

2

NC

F5

NC

G3

NC

G5

NC

E5

SOC_TO_STOCKHOLM_DEV_WAKE

F7

PP_STOCKHOLM_VMID

VOLTAGE=1.8V

F2

NC

G1

NC

SOC_ROM_SPI_MOSI_R

SOC_ROM_SPI_MISO_R

1

C3926

0.1UF

10%

6.3V

2

CERM-X5R 0201

IN

OUT

42

37

C

B

THRM_PADVSS

PP1V8_S0SW_DFRPP1V8_AWAKE_SW3C

1

R3915

2.2K

5% 1/20W MF 201

2

1

R3916

2.2K

5% 1/20W MF 201

2

9

4

10

AOP_I2C0_SCL AOP_I2C0_SDA

AOP_I2C1_SCL AOP_I2C1_SDA

AB20

MESA_I2C_SCL

AE26

MESA_I2C_SDA

AE27 AA19

ALS_SCL_I2C_1V8 ALS_SDA_I2C_1V8

OUT

BI

OUT

BI

40 38 37

41

104 47

42 37

1

R3904

2.2K

5% 1/20W MF 201

2

1

R3905

2.2K

5% 1/20W MF 201

2

PP1V8_AWAKE_SW3C

1

R3911

2.2K

5% 1/20W MF 201

2

104 42 37 41 40 38 37

1

R3912

2.2K

5% 1/20W MF 201

2

106

A

38

IN

SOC_SPI_BOOT_STATUS

37

DFU_STATUS

SOC_PMU_I2C_SCL

41 38

SOC_PMU_I2C_SDA

41 38

100

104 80 38

PP1V8_S0

I2C_CAM_SCL

I2C_CAM_SDA

1

R3906

1K

5% 1/20W MF 201

2

104 42 38

R3981

0

1 2

5%

1/20W

MF

0201

R3980

0

1 2

5%

1/20W

MF

0201

T208 DFU_STATUS Isolation

37 38 42 100

DFU_SPI_STATUS

NOSTUFF

PP1V8_S0

DFU_STATUS can be driven high outside of S0 U3910 creates version that is only high in S0

74LVC2G08GT/S505

8

4

SOT833

PCH_SOC_DFU_STATUS

3

Y

5

6

A

B

U3910

08

OUT

37

19 13

SOC_WDOG_RST

PP1V8_S0

37 38 42 100

1

2

C3950

0.1UF

10%

6.3V CERM-X5R 0201

1

R3972

300K

5% 1/20W MF 201

2

T208 WDOG Isolation

SOC_WDOG_RESET can be driven high outside of S0

U3910 creates version that is only high in S0

74LVC2G08GT/S505

8

4

SOT833

7

Y

PCH_SOC_WDOG

1

2

A

U3910

B

08

1

R3971

100K

5% 1/20W MF 201

2

OUT

13

38 37

PP1V8_S0

42 100

ALS_SCL_I2C_1V8

42 37

ALS_SDA_I2C_1V8

42 37

SEP_I2C_SCL

SEP_I2C_SDA

1

R3960

3.0K

5% 1/20W MF 201

2

1

R3961

3.0K

5% 1/20W MF 201

2

8 7 5 4 2 1

DFR_TOUCH_ROM_I2C_SCL

DFR_TOUCH_ROM_I2C_SDA

42 38

104

42 37

106 104

1

R3907

1K

5% 1/20W MF 201

2

42 38

104

104 42 38

PP1V8_S0SW_DFR

DFRDRV_I2C_SCL

DFRDRV_I2C_SDA

1

R3917

4.7K

5% 1/20W MF 201

2

36

37

1

R3918

4.7K

5% 1/20W MF 201

2

335S00203

SOC_TO_STOCKHOLM_DWLD_REQ

BOM_COST_GROUP=T151

IC,FLASH,SERIAL,SPI,4MX8,4X3MM,DFN8

SYNC_MASTER=J80_MLB_BAFFIN

NOSTUFF

1

R3940

100K

5% 1/20W MF 201

2

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

Camera/DFR 1

Apple Inc.

R

U39061

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

BOM OPTIONCRITICAL

051-00515

9.0.0

dvt-fab09-0

39 OF 145

37 OF 119

TABLE_5_HEAD

TABLE_5_ITEM

D

SYNC_DATE=07/22/2016

A

345678

2 1

D

C

B

PP1V8_AWAKE_SW3C

41

1

C4002

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V8_S4

42 100

38

SOC_BOOT:SPI

PP1V8_AWAKE_SW3C

37 38 39 41

1

R4023

100K

5% 1/20W MF 201

2

NOSTUFF

104 42 37

PP1V8_AWAKE_SW3C

37 38 39 41

PP1V1_SLEEP1_SW2

41

SOC_BOOT:DFU

1

R4035

47K

5% 1/20W MF 201

2

SOC_FORCE_DFU

41

IN

PMU_TO_SOC_AWAKE_PWRGD

IN

1 2

41 37

R4017

2.2K

5%

1/20W

MF

201

SOC_BOOT_CONFIG_0

39

42

104 42

47

41 37

37 19

104 42

OUT

BI

OUT

BI

104 42 37

OUT

IN

DFR_TOUCH_ROM_I2C_SCL

DFR_TOUCH_ROM_I2C_SDA

OUT

BI

42 39

37

47

42

SOC_XTAL_24M_I

1

C4001

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

2

37

OUT

SOC_REQUEST_DFU1

38

SOC_REQUEST_DFU2

38

41

C4000

0.1UF

10%

6.3V CERM-X5R 0201

DFU_STATUS

PMU_TO_SOC_VDD_OK

TP_SOC_TST_CKOUT

OUT

IN

OUT

IN

DFR_CLKIN_RESET_L

NC NC

NC

NC NC

SOC_BOARD_ID_3 SOC_BOARD_REV_0 SOC_BOARD_REV_1 SOC_BOARD_REV_2

PP1V8_AWAKE_SW3C

DFR_DISP_RST_L

DFR_TOUCH_INT_L

MESA_SNSR_INT

SOC_TO_STOCKHOLM_EN

DFR_DISP_INT

NC NC

SOC_PMU_I2C_SCL

SOC_PMU_I2C_SDA

DFRDRV_I2C_SCL DFRDRV_I2C_SDA

IN

SOC_ROM_SPI_MISO SOC_ROM_SPI_MOSI

OUT

SOC_ROM_SPI_CLK

OUT

SOC_ROM_SPI_CS_L

OUT

MESA_SPI_MISO MESA_SPI_MOSI

OUT

MESA_SPI_CLK

OUT

PP1V1_SLEEP1_SW2

P1

DFU_STATUS

F4

FORCE_DFU

E3

REQUEST_DFU1

D1

REQUEST_DFU2

R3

DROOP_N

D3

CFSB

C3

HOLD_RESET

T6

TST_CLKOUT

A3

TESTMODE

E2

CLK32K_OUT

C23

GPIO_0

F20

GPIO_1

C22

GPIO_2

E20

GPIO_3

D25

GPIO_4

C24

GPIO_5

D21

GPIO_6

C25

GPIO_7

E19

GPIO_8

D20

GPIO_9

C21

GPIO_10

A22

GPIO_11

B22

GPIO_12

B23

GPIO_13

D19

GPIO_14

F18

GPIO_15

C19

GPIO_16

B21

GPIO_17

B8

I2C0_SCL

C8

I2C0_SDA

A8

I2C1_SCL

D8

I2C1_SDA

E8

I2C2_0_SCL

B7

I2C2_0_SDA

C7

NC NC

NC

I2C2_1_SCL

A7

I2C2_1_SDA

E10

SPI0_MISO

D10

SPI0_MOSI

B10

SPI0_SCLK

A10

SPI0_SSIN

A9

SPI1_MISO

C9

SPI1_MOSI

B9

SPI1_SCLK

E9

SPI1_SSIN

AA8

XI0

AB8

XO0

J12

H12

H10Y8J22

VDD11_UVD

J6

H3

VDD30_USB

VDD18_USB

J5

VDD18_TSADC

VDD11_PLL_SOC1

VDD11_PLL_SOC0

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

(3 OF 7)

OMIT_TABLE

PP1V1_SLEEP1_XTAL_FILT

VDD11_XTAL

VDD_FIXED_USB

USB_DP USB_DM

USB_VBUS

USB_ID

USB_REXT

TMR32_PWM0 TMR32_PWM1 TMR32_PWM2

UART0_RXD UART0_TXD

UART1_RTSN UART1_CTSN

UART1_RXD UART1_TXD

UART2_RTSN UART2_CTSN

UART2_RXD UART2_TXD

UART3_RTXD

UART4_RXD UART4_TXD UART5_RXD UART5_TXD

I2S0_BCLK I2S0_LRCK

I2S0_DIN

I2S0_DOUT

I2S1_BCLK I2S1_LRCK

I2S1_DIN

I2S1_DOUT

I2S2_BCLK I2S2_LRCK

I2S2_DIN

I2S2_DOUT

1

C4004

0.1UF

10%

6.3V

2

CERM-X5R 0201

120-OHM-0.2A-0.5-OHM

VOLTAGE=1.1V

1

C4050

0.22UF

10%

6.3V

2

X5R-CERM 0201

G1

USB_CAMERA_DFR_P

G2

USB_CAMERA_DFR_N

K6

SOC_USB_VBUS

J3

H4

SOC_USB_REXT

D18 E18 A23

A6

PCH_TO_SOC_UART_TXD

D7

SOC_TO_PCH_UART_TXD

D5 B3 C4

PCH_ALS_TO_SOC_UART_TXD

B4

SOC_TO_PCH_ALS_UART_TXD

E6 A4 B5 D6

UART_SOC_TO_STOCKHOLM_RTS_L UART_STOCKHOLM_TO_SOC_RTS_L

UART_STOCKHOLM_TO_SOC_TXD

UART_SOC_TO_STOCKHOLM_TXD

E7

A5 B6 C5 C6

B17 C15 E15 A17

C14 B16 E14 A16

B15 F14 D13 A15

NC

PLACE_NEAR=U3900.H4:2mm

NC

NC NC NC NC

PP3V0_AWAKE_LDO7

38 41

1

C4005

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP0V8_SLEEP1_SW1

41

L4010

1 2

0201

BI

R4001

200

1 2

1/20W

201

NC NC NC

NC NC

BI

1%

MF

105 15

To/From PCH for logging/debug

42

IN

42

OUT

To/From PCH for ALS

IN

OUT

42

1

C4003

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V1_SLEEP1_SW2

PP3V0_AWAKE_LDO7

1

R4022

10K

5% 1/20W MF 201

2

PLACE_NEAR=U3900.K1:2mm

37

OUT

37

IN

37

IN

37

OUT

PP1V8_AWAKE_SW3C

41

1

C4006

1.0UF

20%

6.3V

2

X5R 0201-1

41

38 41

PP3V3_S4_SOC_PMU

1

R4042

10K

5% 1/20W MF 201

2

NOSTUFF

R4003

4.02K

1 2

1%

1/20W

MF

201

SOC_MIPI1C_REXT

104 80 37

42 101

105 38

1

C4007

0.1UF

10%

6.3V

2

CERM-X5R 0201

MIPIC_DATA_P MIPIC_DATA_N

MIPIC_CLK_P MIPIC_CLK_N

I2C_CAM_SDA

BI

I2C_CAM_SCL

OUT

NC NC

NC NC NC

NC NC

NC NC NC NC

NC

NC NC

NC

CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND

G24

G23

V23

U23

VDD18_EFUSE4

VDD18_EFUSE2

VDD18_EFUSE1

VDD18_EFUSE3

M3

MIPI1C_DPDATA0

M2

MIPI1C_DNDATA0

L1

MIPI1C_DPCLK

L2

MIPI1C_DNCLK

K1

MIPI1C_REXT

B2

ISP0_SDA

A2

ISP0_SCL

D12

ENET_MDC

C12

ENET_MDIO

A12

RMII_CLK

A11

RMII_CRSDV

B11

RMII_RXD_0

F10

RMII_RXD_1

B12

RMII_RXER

E11

RMII_TXD_0

C10

RMII_TXD_1

C11

RMII_TXEN

B14

SD_CLKOUT

E13

SD_CMD_IO

A14

SD_DATA_IO_0

C13

SD_DATA_IO_1

F12

SD_DATA_IO_2

B13

SD_DATA_IO_3

A13

SDIO_IRQ

E12

WL_HOST_WAKE

B1

SWD_TMS2

F5

SWD_TMS3

C1

ANALOGMUX_OUT

H6

BB_HSIC_DATA

F2

BB_HSIC_STROBE

F24

VDD18_EFUSE5

G3

F3

G5

VDD12_HSIC

VDD18_EFUSE6

L4

M4

VDD18_MIPI

VDD_FIXED_HSIC

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

(4 OF 7)

OMIT_TABLE

PP1V8_AWAKE_SW3C

N4

G4

K4

VDD18_AMUX

VDD_FIXED_MIPI

MIPI0D_DPDATA0 MIPI0D_DNDATA0

MIPI0D_DPCLK MIPI0D_DNCLK

SEP_SPI0_MISO SEP_SPI0_MOSI SEP_SPI0_SCLK

PP0V8_SLEEP1_SW1

1

2

MIPI0D_REXT

DISP_VSYNC

DISP_TE

NAND_CEN_0 NAND_CEN_1

NAND_ALE NAND_CLE

NAND_REN NAND_WEN

NAND_IO_0 NAND_IO_1 NAND_IO_2 NAND_IO_3 NAND_IO_4 NAND_IO_5 NAND_IO_6 NAND_IO_7

MON_0 MON_1 MON_2 MON_3 MON_4 MON_5 MON_6 MON_7

SEP_GPIO0 SEP_GPIO1

SEP_I2C_SCL SEP_I2C_SDA

C4008

0.1UF

10%

6.3V CERM-X5R 0201

H1 H2

J2 J1

K2

C2 D2

D17 B20

D15 C16

A20 A18

E16 A19 B18 D16 C17 A21 B19 E17

N3 P6 P4 P3 N2 P5 R4 P2

D24 E21

D22 F22 E24

E22 D23

MIPID_DATA_P MIPID_DATA_N

MIPID_CLK_P MIPID_CLK_N

SOC_MIPI0D_REXT

DFR_DISP_VSYNC

DFR_DISP_TE

SOC_NAND_CEN_0

DFR_TOUCH_PANEL_DETECT

DFR_TOUCH_GPIO2

DFR_TOUCH_ROM_WC

SOC_PANIC_L

S2R_ACK_L

SOC_PCH_DBELL_L

SEP_I2C_SCL SEP_I2C_SDA

37 38 39 41

41

PP1V8_AWAKE_SW3C

1

R4036

10K

5% 1/20W MF 201

2

42

BI

42

BI

42

OUT

42

OUT

PP1V8_AWAKE_SW3C

1

R4024

100K

5% 1/20W MF 201

2

104 42

42

104 42

19 13

MIPIC_DATA_P

MIPIC_DATA_N

MIPIC_CLK_P

NC

NC NC

NC NC NC NC NC NC NC NC

NC

38

NC

NC NC

NC NC NC

OUT

IN

105 38

BI

105 38

OUT

37

BI

38 105

104 42

BI

IN

41 40 38 37

PP1V8_AWAKE_SW3C

1

R4037

10K

5% 1/20W MF 201

2

SOC_REQUEST_DFU2SOC_REQUEST_DFU1

38 38

R4004

4.02K

1 2

1%

1/20W

MF

201

41 40 38 37

MIPIC FILTERING

L4002

3.25-OHM-0.1A-2.4GHZ

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

TAM0605-4SM

SYM_VER-1

1

2 3

L4003

3.25-OHM-0.1A-2.4GHZ TAM0605-4SM

SYM_VER-1

1

PLACE_NEAR=U3900.K2:2mm

PLACE_NEAR=J8500:2.54mm

GND_VOID=TRUE

4

MIPI_DATA_CONN_P

MIPI_DATA_CONN_N

PLACE_NEAR=J8500:2.54mm

GND_VOID=TRUEGND_VOID=TRUE

4

MIPI_CLK_CONN_P

D

41 40 38 37

C

B

BI

OUT

104 80 105

A

1

C4041

12PF

5% 50V

2

C0G-CERM 0201

R4010

499K

1 2

1%

1/20W

MF

201

SOC_XTAL_24M_O

Y4000

1.60X1.20MM-SM

24.000MHZ-30PPM-9.5PF-60OHM

1 3

SOC_XTAL_24M_O_R

2 4

1

R4020

0.00

1% 1/20W MF 0201

2

38 19 13

1

C4040

12PF

5% 50V

2

C0G-CERM 0201

BI

PCH

T208 SOC_S2R_ACK_L bi-directional Isolation

PP3V3_S0

42 101

NOSTUFF

1

R4080

200K

5% 1/20W MF 201

2

S

SYM_VER_1

Q4000 to act as bi-directional islation for SOC_S2R_ACK_L When in system S0 and M8 AWAKE, FET will be on & line will be pulled high Below S0, SOC_S2R_ACK_L will be low and FET will be open (isolated from M8 power rails) When M8 enters S2R, FET will be on, PP1V8_AWAKE_SW3C will turn off and SOC_S2R_ACK_L will be low

PP1V8_AWAKE_SW3C

1

G

D

3

Q4000

DMN32D2LFB4

DFN1006H4-3

S2R_ACK_LSOC_S2R_ACK_L

1

R4082

10K

5% 1/20W MF 201

2

T208

38

37 38 42 100

PP1V8_S0

1

C4080

0.1UF

10%

6.3V

2

CERM-X5R 0201

38

NOSTUFF

S2R_ACK_L

T208

T208 SOC_S2R_ACK_L Isolation (NOSTUFF)

NOSTUFF

6

2

B

U4080

1

A

NC

5

NC

74LVC1G08FW5

DFN1010

4

Y

3

SOC_S2R_ACK_L

OUT

PCH

38 19 13

PCH

14

IN

SOC_BOOT:DFU

1

R4070

47K

5% 1/20W MF 201

2

PCH_SOC_FORCE_DFU

PP1V8_S037 38 42 100

SOC_BOOT:DFU

1

C4070

0.1UF

10%

6.3V

2

CERM-X5R 0201

T208 FORCE_DFU Isolation

SOC_FORCE_DFU should be pulled up to S4 In the SOC_BOOT:DFU option

U4070 prevents it from leaking into PCH

SOC_BOOT:DFU

6

2

B

1

A

NC

R4071

1 2

201

U4070

NC

5

5%

1/20W

MF

74LVC1G08FW5

DFN1010

4

Y

3

0

SOC_BOOT:SPI

SOC_FORCE_DFU

BOM_COST_GROUP=T151

T208

105 38

106 101

38

GND_VOID=TRUE GND_VOID=TRUE

MIPIC_CLK_N

2 3

FERR-120-OHM-1.5A

PP5V_S0

SYNC_MASTER=J79_ANDREW

PAGE TITLE

1 2

Camera/DFR 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

L4004

0402A

MIPI_CLK_CONN_N

PP5V_S0_ALSCAM_F

VOLTAGE=5V

1

C4062

0.1UF

10% 10V

2

X5R-CERM 0201

DRAWING NUMBER SIZE

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

40 OF 145

SHEET

38 OF 119

OUT

D

SYNC_DATE=03/22/2016

106 104 80

A

8 7 5 4 2 1

36

345678

2 1

U5

V5

U4

T4

D

C

B

A

PP1V1_SLEEP3_BUCK2

41

1

C4106

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V1_SLEEP1_SW2

41

1

C4116

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C4119

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP0V8_SLEEP1_SW1

39 41

1

C4121

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

PP1V8_SLEEP2_SW3A

37 41

1

C4112

1.0UF

20%

6.3V

2

X5R 0201-1

PP1V8_AWAKE_SW3C

37 38 39 41

1

C4114

1.0UF

20%

6.3V

2

X5R 0201-1

1

PP0V8_SLEEP2_BUCK1

41

1

C4141

2

41

234

1.0UF

20%

6.3V X5R 0201-1

PP1V8_SLEEP3_BUCK3

1

C4100

1.0UF

20%

6.3V

2

X5R 0201-1

C4107

4.3UF

20%

4V

CER-X5R

0402

C4117

4.3UF

20%

4V

CER-X5R

0402

C4122

4.3UF

20%

4V

CER-X5R

0402

1

C4113

0.1UF

10%

6.3V

2

X5R 0201

1

C4115

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

2

1

2

234

1

234

C4142

2.2UF

20%

6.3V X5R-CERM 0201

C4101

0.1UF

10%

6.3V CERM-X5R 0201

C4108

4.3UF

20%

4V

CER-X5R

0402

C4118

4.3UF

20%

4V

CER-X5R

0402

C4123

4.3UF

20%

4V

CER-X5R

0402

A24 AC24 AC28

C27

K28

R28

A27 AC25 AC27

B24

J28

K27

M28

P28

T28

AB23

W12

W16

W18

Y13

Y15

Y19

Y22

F19

F21

G10

G12

G14

G16

H23

AB25 AB26

B25

B26

D28

F28

H28

J23

K23

L23

M23

N23

P23

R23

R27

T23

U27

U28

Y28

W10

W15

W19

Y21

L17

M14

M18

M20

M22

N11

P12

P14

P18

P20

P22

T12

T14

T18

T20

T22

V13

V21

W13

Y23

VDD1

N1

VDD2

M1

VDDIO18_AOP

Y9

E5

F7 F9

VDDIO18_GRP0

R5

VDDIO18_GRP1

VDD18_FMON

VDDIO11_DDR

VDD_SRAM_AON

M8

N5

P8

W9

M8-LPDDR4-H-A-FUSE

VDD_SRAM

U3900

UFBGA

(5 OF 7)

OMIT_TABLE

VDD_SOC

VDD_SOC_AON

VDD_SRAM

E4 F11 F15 G17 G19 G22 G6 G8 H14 H16 H18 H8 J15 J19 J21 J9 K10 K12 K16 K18 L13 L15 L19 L21 L5 L7 L9 M10 M12 M16 N13 N15 N17 N19 N21 N6 N9 P10 P16 R11 R13 R15 R17 R19 R21 R9 T10 T16 U11 U13 U15 U17 U19 U9 V10 V12 V22 W11 W23

V14 V16 V18 V20 W17 W21 Y11

F13 F17 F23 F6 F8 G11 G13 G15 G18 G21 G9 H17 H20 H22 J11 J13 J17 J7 K14 K20 K22 K5 K8 L11

1

C4102

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C4109

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

234

1

234

PP0V6_SLEEP2_LDO0

PP0V8_SLEEP1_SW1

PP0V6_SLEEP1_BUCK0

1

C4103

4.3UF

20%

4V

CER-X5R

0402

234

1

C4110

4.3UF

20%

4V

CER-X5R

0402

1

C4120

0.1UF

10%

6.3V

2

CERM-X5R 0201

234

41

C4104

4.3UF

20%

4V

CER-X5R

0402

C4111

4.3UF

20%

4V

CER-X5R

0402

1

C4105

12PF

5% 25V

2

NP0-C0G 0201

1

C4124

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

A1 A25 A26 A28 AA1

AA26 AA27 AA28

AA4

AB27 AB28 AC20 AC26

AC9

AD14 AD28

AD5 AE1

AE28

B27 B28 C18 C20 C26 C28 D11 D14 D26 D27

D4

D9

E1 E23 E25 E28

F1 F16 F25 G20 G25 G28

G7 H11 H13 H15 H19 H21 H24 H25

H5

H7

H9 J10 J14 J16 J18 J20 J24 J25 J27

J4

J8 K11 K13 K15 K17 K19 K21 K24

K3

K7

K9 L10 L12 L14 L16 L18 L20

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

(6 OF 7)

OMIT_TABLE

VSS

BOM GROUP BOM OPTIONS

T208_PROG:REV0 T208_PROG:REV1

T208_PROG:REV2

T208_PROG:REV3

T208_PROG:REV4

T208_PROG:REV5

T208_CONFIG2_H,T208_CONFIG1_H,T208_CONFIG0_H

T208_CONFIG2_H,T208_CONFIG1_H

T208_CONFIG2_H,T208_CONFIG0_H

T208_CONFIG2_H

T208_CONFIG1_H, T208_CONFIG0_H

T208_CONFIG1_H

L22 L28 L3 L6 L8 M11 M13 M15 M17 M19 M21 M5 M9 N10 N12 N14 N16 N18 N20 N22 N28 N8 P11 P13 P15 P17 P19 P21 P27 P9 R10 R12 R14 R16 R18 R20 R22 R24 R25 R8 T11 T13 T15 T17 T19 T21 T24 T25 T7 T9 U10 U12 U14 U16 U18 U20 U22 U24 U25 U6 U8 V11 V15 V17 V19 V24 V25 V28 V7 V9 W14 W20 W22 W28 W6 W8 Y17 Y27

CKPLUS_WAIVE=PWRTERM2GND

VDD12_MAR_LV

VDD12_MAR_HV

VDD12_MAR_PLL

OMIT_TABLE

CKPLUS_WAIVE=PWRTERM2GNDCKPLUS_WAIVE=PWRTERM2GND

CKPLUS_WAIVE=PWRTERM2GND

VDD12_MAR_BG

U3900

M8-LPDDR4-H-A-FUSE

UFBGA

AC8

CFSB_MAR

T2

MAX_RX_IP

T1

MAX_RX_IM

R1

MAX_RX_QP

R2

MAX_RX_QM

V1

MAX_TX_IP

V2

MAX_TX_IM

W1

MAX_TX_QP

W2

MAX_TX_QM

U1

MAX_TX_BTAP

U2

MAX_TX_BTAM

Y1

MAX_TX_WLETP

Y2

MAX_TX_WLETM

T3

MAX_FREF

T5

MAX_TEST_OUT

CKPLUS_WAIVE=PWRTERM2GND

M7 N7

CKPLUS_WAIVE=PWRTERM2GND CKPLUS_WAIVE=PWRTERM2GND

R6

CKPLUS_WAIVE=PWRTERM2GND

R7

VDD_SOC_MAR

U7

CKPLUS_WAIVE=PWRTERM2GND

V4

CKPLUS_WAIVE=PWRTERM2GND

V6

CKPLUS_WAIVE=PWRTERM2GND

AA3

CKPLUS_WAIVE=PWRTERM2GND

M6

CKPLUS_WAIVE=PWRTERM2GND

P7

CKPLUS_WAIVE=PWRTERM2GND

T8

VDD_SRAM_MAR

CKPLUS_WAIVE=PWRTERM2GND

V8

CKPLUS_WAIVE=PWRTERM2GND

W5

CKPLUS_WAIVE=PWRTERM2GND

W7

CKPLUS_WAIVE=PWRTERM2GND

Y4

CKPLUS_WAIVE=PWRTERM2GND

Y5

CKPLUS_WAIVE=PWRTERM2GND

VDDIO18_MAR

Y6

CKPLUS_WAIVE=PWRTERM2GND

Y7

CKPLUS_WAIVE=PWRTERM2GND

(7 OF 7)

VSS_MXL

U3V3W3W4Y3

T208 BOARD REV/BOARD ID

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

4. DISABLE PD AND ENABLE PU

PP1V8_AWAKE_SW3C 37 38 39 41

T208_CONFIG1_H

R4101

2.2K

5%

1/20W

MF

201

1 2

PP1V8_AWAKE_SW3C38

SOC_BOARD_REV_2

38

SOC_BOARD_REV_1

38

SOC_BOARD_REV_0

38

T208_CONFIG2_H

R4100

2.2K

5%

1/20W

MF

201

1 2

BOARD REV[3:0] MODE

1111 T208_Rev0 (X362 P0) 1110 T208_Rev1 (X363 P0) 1101 T208_Rev2 (X362 P1) 1100 T208_Rev3 (X362 P2) 1011 T208_Rev4 (X363 P2/X362 localEVT) 1010 T208_Rev5 (X363 EVT/X362 EVT1)

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM_COST_GROUP=T151

T208_CONFIG0_H

R4102

2.2K

5%

1/20W

MF

201

1 2

SYNC_MASTER=J79_ANDREW SYNC_DATE=04/25/2016

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

ID_3 reserved for DEV

MAR_SYSALIVE

MAR_TX_THROTTLE_N

MAR_BT_RFIC_IRQ MAR_WL_RFIC_IRQ

MAR_RFIC_PDET_0 MAR_RFIC_PDET_1

MAR_VDD1V2_PWR_REQ

MAR_VDD1V2_FORCE_PWM

MAR_RF_SWITCH_CTRL_0 MAR_RF_SWITCH_CTRL_1 MAR_RF_SWITCH_CTRL_2

MAR_RFIC_EN

MAR_PA_EN

MAR_PA_CTRL

MAR_ETIC_GPIO_0 MAR_ETIC_GPIO_1

MAR_RFFE_SCLK

MAR_RFFE_SDATA

MAR_SPARE_0 MAR_SPARE_1 MAR_SPARE_2

MAR_SPI_CLK

MAR_SPI_CS MAR_SPI_DATA_0 MAR_SPI_DATA_1 MAR_SPI_DATA_2 MAR_SPI_DATA_3 MAR_SPI_DATA_4 MAR_SPI_DATA_5 MAR_SPI_DATA_6 MAR_SPI_DATA_7

MAR_COEX_UART_RXD MAR_COEX_UART_TXD

PP1V8_AWAKE_SW3C

37 38 39 41

SOC_BOARD_ID_3

38

SOC_ROM_SPI_MISO

42 38

SOC_ROM_SPI_MOSI

42 38

SOC_ROM_SPI_CLK

42 38

AC6

AD2

AB1 AC1

AC2 AB2

AB3 AD1

AD8 AE7 AE9

AA7 AC7 AD7

AD6 AE8

AD3 AA5

AA2 AB4 AC3

AD4 AE2 AC4 AB5 AE3 AE4 AE5 AA6 AC5 AB6

AB7 AE6

1 2

BOARD ID[3:0] MODE

1XXX T202 DEV 0010 T208

Camera/DFR 3

Apple Inc.

R

NOSTUFF

R4103

2.2K

5%

1/20W

MF

201

NOSTUFF

R4104

2.2K

5%

1/20W

MF

201

1 2

DRAWING NUMBER SIZE

1/20W

1 2

R4105

2.2K

5%

MF

201

051-00515

REVISION

NOSTUFF

R4106

2.2K

5%

1/20W

MF

201

1 2

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

41 OF 145

SHEET

39 OF 119

D

C

B

A

8 7 5 4 2 1

36

Berkelium

345678

2 1

D

C

B

41 40

SW1_EXT_ON

40

PP0V8_SLEEP1_SW1

1 2 5 6 8

3

G

D

S

4 7

PP0V8_SLEEP2_BUCK1

Q4201

CSD58892Q2

SON2X2

PLACE_NEAR=U4200.M4:2mm

VOLTAGE=1.8V

PP1V8_ALWAYS_LDO9

1

C4227

0.22UF

20% 10V

2

CERM-X5R 0201

41 40

PLACE_NEAR=U4200.A7:2mm

40 41 101

C4220

2.2UF

20%

6.3V

X5R-CERM

0201

1

C4226

0.022UF

10%

6.3V

2

X5R-CERM 0201

PLACE_NEAR=U4200.E1:3mm

PP3V3_S4_SOC_PMU

40 41 101

1

C4219

2.2UF

20%

6.3V

2

X5R-CERM 0201

PLACE_NEAR=U4200.L8:2mm

1

2

41

PP3V3_S4_SOC_PMU40 41 101

CRITICAL

1

C4204

15UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C4207

15UF

20%

6.3V

2

CERM 0402

1

C4218

2.2UF

20%

6.3V

2

X5R-CERM 0201

41

PP3V0_AWAKE_LDO7

40 41 101

PP0V6_SLEEP2_LDO0

1

2

PLACE_NEAR=U4200.A2:2mm

NC

40

PP3V3_S4_SOC_PMU

PP0V8_SLEEP2_BUCK1

41 40

PP0V8_SLEEP1_SW1

41 40

PP3V3_S4_SOC_PMU40 41 101

CRITICAL

1

C4203

15UF

20%

6.3V

2

CERM 0402

PLACE_NEAR=U4200.K11:2mm

PP3V3_S4_SOC_PMU

40 41 101

PLACE_NEAR=U4200.F12:2mm

CRITICAL

C4205

15UF

20%

6.3V CERM 0402

SW1_EXT_ON

NC NC NC NC

NC

M10

NC NC NC

NC

N10

B10

A11 C10

CRITICAL

1

C4206

15UF

20%

6.3V

2

CERM 0402

C6

SW0_EXT

D7

SW1_EXT

E1

BB_LX1

G1

BB_LX2

J3

BB_FB

H1

BB_OUT

M4

VDD_HVLDO_237

N2

VDD_HVLDO_45

L8

VDD_HVLDO_RTC

L3

VDD_HVLDO_SW6

M5

LDO2_OUT

N4

LDO3_OUT

M1

LDO4_OUT

N3

LDO5_OUT

N5

LDO7_OUT

M2

SW4_OUT

VDD_MAIN_LDO_16

M6

VDD_MAIN_LDO_8

M9

VDD_MAIN_LDO_9

N7

VDD_MAIN_LDO_AUX

CKPLUS_WAIVE=PWRTERM2GND

LDO1_OUT

N9

LDO6_OUT

N6

LDO8_OUT

M8

LDO9_OUT

N8

AUX_PWR_OUT

SW1_IN

SW1_OUT LDO0_OUT

A7A8A2

VDD_MAIN_BUCK0

F12

G12

VDD_MAIN_BUCK1

VDD_MAIN_BUCK2

VDD_MAIN_BUCK4

VDD_MAIN_BUCK3

D1

K11

L11

M11

VDD_MAIN_BB

VDD_MAIN_CHG

U4200

D2346A1-OTP-CE

WLCSP

SYM 1 OF 2

NC

J1

VDD_MAIN_BBCORE

K3

L2

ACT_DIODE*

VDD_MAIN_SW4

NC

K12

VBAT

NC

L12

VBAT

NC

M12

VBAT

NC

K10

VBAT_S

BUCK0_LX

BUCK0_FB

BUCK1_LX

BUCK1_FB

BUCK2_LX

BUCK2_FB

BUCK3_LX

BUCK3_FB

A6

SOC_PMU_BUCK0_LX

C9

SOC_PMU_BUCK0_FB

A9

SOC_PMU_BUCK1_LX

D9

SOC_PMU_BUCK1_FB

A3

SOC_PMU_BUCK2_LX

C2

SOC_PMU_BUCK2_FB

E12

SOC_PMU_BUCK3_LX

D10

SOC_PMU_BUCK3_FB

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

PP3V3_S4_SOC_PMU

CRITICAL

Place same side as PMU

L4202

1.0UH-1.82A-0.203OHM

1 2

MCFK2012-SM

40

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

CRITICAL

Place same side as PMU

L4203

1.0UH-1.3A-0.326OHM

1 2

MCFK1608T1R0M NA

40

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

CRITICAL

Place same side as PMU

L4204

1.0UH-1.3A-0.326OHM

1 2

MCFK1608T1R0M NA

40

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

CRITICAL

Place same side as PMU

L4205

1.0UH-1.3A-0.326OHM

1 2

MCFK1608T1R0M NA

40

40 41 101

PLACE_NEAR=U4200.D1:2mm

CRITICAL

1

C4202

15UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C4208

15UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C4211

4.2UF

10% 16V

2

X5R-CERM 0402-1

CRITICAL

1

C4238

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

1

C4234

4.7UF

20%

6.3V

2

CER-X5R 0402

CRITICAL

1

C4235

4.7UF

20%

6.3V

2

CER-X5R 0402

CRITICAL

1

C4209

15UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C4231

4.2UF

10% 16V

2

X5R-CERM 0402-1

CRITICAL

1

C4239

10UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

1

C4236

4.7UF

20%

6.3V

2

CER-X5R 0402

SOC_PMU_BUCK1_FB

40

SOC_PMU_BUCK2_FB PP1V1_SLEEP3_BUCK2

40 41 40

SOC_PMU_BUCK3_FB

40

PP0V6_SLEEP1_BUCK0

1

C4210

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

C4230

2.2UF

20%

6.3V

2

X5R-CERM 0201

Mirror Capacitors in Layout

PP0V8_SLEEP2_BUCK1

1

C4233

4.7UF

20%

6.3V

2

CER-X5R 0402

CRITICAL

Mirror Capacitors in Layout

CRITICAL

1

C4240

4.7UF

20%

6.3V

2

CER-X5R 0402

Mirror Capacitors in Layout

PP1V1_SLEEP3_BUCK2

1

C4241

4.7UF

20%

6.3V

2

CER-X5R 0402

1

2

CRITICAL

PP1V8_SLEEP3_BUCK3

CRITICAL

1

C4237

4.7UF

20%

6.3V

2

CER-X5R 0402

C4232

4.7UF

20%

6.3V CER-X5R 0402

CRITICAL

FB for Bucks

R4200

0

1 2

5% 1/16W MF-LF

402

R4201

0

1 2

5% 1/16W MF-LF

402

R4202

0

1 2

5% 1/16W MF-LF

402

R4203

0

1 2

5% 1/16W MF-LF

402

41 40

VDD_SOC

501MA MAX

41 40

VDD_SRAM_AON VDD_SRAM VDD_SOC_AON

VDD_FIXED_MIPI VDD_FIXED_USB 300MA MAX

VDD2

41 40

VDDQ

VDD11_XTAL

460MA MAX

VDD1 VDD18_USB VDDIO18_GRP0

100MA MAX

PP0V6_SLEEP1_BUCK0SOC_PMU_BUCK0_FB

PP0V8_SLEEP1_SW1

PP1V8_SLEEP3_BUCK3

41 40 40

D

41 40

C

B

A

VOLTAGE=0.6V

1

C4228

2.2UF

20%

6.3V

2

X5R-CERM 0201

41 40

41

41 40

41 37

41 38 37

PP1V1_SLEEP3_BUCK2

PP1V1_SLEEP1_SW2

PP1V8_SLEEP3_BUCK3

PP1V8_SLEEP2_SW3A

NC

PP1V8_AWAKE_SW3C

NC

B1

C1

B12

B11 C11 C12

K1

L1

K2

SW2_IN

SW2_OUT

SW3_IN

SW3A_OUT SW3B_OUT SW3C_OUT

SW5_IN

SW5_OUT

SW6_OUT

B2B9C4C5E5E6H5H6F5F6G5G6M3M7G8H7H8E7F7F8G7

VSS1

VSS2

VSS3

VSS4

VSS7

VSS6

VSS8

VSS9

VSS8

A1

BUCK4_LX

BUCK4_FB

VSS_BUCK0 VSS_BUCK1 VSS_BUCK2 VSS_BUCK3 VSS_BUCK4

VSS9

A12N1N12

VSS_BB

Not using Buck4

H12

J10

F1 A5 A10 A4 D12 J12

NC

Mirror Capacitors in Layout

BOM_COST_GROUP=T151

PAGE TITLE

Berkelium - 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

42 OF 145

SHEET

40 OF 119

A

SYNC_DATE=03/14/2016SYNC_MASTER=J79_ANDREW

8 7 5 4 2 1

36

D

C

B

NOSTUFF

1

C4300

100PF

5% 25V

2

C0G 0201

PMU_TCAL_GND

1

2

1 2

PMU_VREF

1

C4301

0.1UF

10% 16V

2

X5R-CERM 0201

PP1V8_SLEEP2_SW3A

R4305

10K

5% 1/20W MF 201

PMU_TO_SOC_SYS_ALIVE

PMU_TCAL_PWR

NOSTUFF

R4307

3.92K

1%

1/20W

MF

201

OMIT

XW4300

SHORT-8L-0.1MM-SM

1 2

PMU_IREF

R4308

200K

1 2

0.1%

1/20W

TF

0201

37 19

1

C4302

0.1UF

10% 16V

2

X5R-CERM 0201

NC

SOC_PMU_CLK_32K

IN

41

41 37

PMU_VDD_RTC

PMU_VPUMP

1

C4303

0.01UF

10% 25V

2

X5R-CERM 0201

F4

CLK_32K_ALT

F3

CLK_32K_IN

L9

TCAL

L6

VREF

N11

IREF

J5

VDD_RTC_DIG

L7

VDD_RTC

D2

VPUMP

U4200

D2346A1-OTP-CE

WLCSP

SYM 2 OF 2

ACTIVE_REQUEST ACTIVE_PWRGOOD SLEEP1_REQUEST SLEEP1_PWRGOOD

SOC_VDD_CORE_HI_LO

VSS8

E8J7J8K8K7

VSS8

I2C1_SCL I2C1_SDA I2C2_SCL I2C2_SDA

BB_FORCE_PWM

VBUS_DET*

SHDN RESET_IN1 RESET_IN2 INCKT_OTP

IRQ*

RESET* VDD_OK

SYS_ALIVE

UWAKE*

BUTTON1 BUTTON2 BUTTON3

DBLCLICK_DET

GPIO1 GPIO2

GPI3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9

GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15

AMUX_IN1 AMUX_IN2 AMUX_IN3 AMUX_IN4 AMUX_OUT

NTC1

NTC2

NTC3

NTC4

TBAT

E3 E4 G3 G4

B4

K9 G2 H2 H3 B3

E11 B7 B8

D11 D6 E9 D5 E10 F2

H4

E2 D3 D4 C3

C7 B5 B6 C8 D8 F9 F10 F11 G9 G10 G11 H9 H10 H11 J11

K6 L4 J6 K5 L5

J9 J2 K4 J4 L10

SOC_PMU_I2C_SCL

SOC_PMU_I2C_SDA

SMBUS_SOC_PMU_BR_SCL

SMBUS_SOC_PMU_BR_SDA

BB_FORCE_PWM

PMU_SOC_VBUS_DET_L

SMC_SOCPMU_RESET SOC_PMU_INCKT_OTP

PMU_TO_SOC_IRQ_L PMU_TO_SOC_RESET_L PMU_TO_SOC_VDD_OK

PMU_TO_SOC_SYS_ALIVE

SOC_AWAKE_REQ

PMU_TO_SOC_AWAKE_PWRGD

SOC_SLEEP1_REQ

PMU_TO_SOC_SLEEP1_PWRGD

SOC_VDD_HI_LO

PMU_SOC_UWAKE_L

PMU_TO_SOC_CLK_32K

Berkelium - 2

41

37

OUT

38 37

BI

1 2

R4321

41

37

OUT

37

OUT

38

OUT

IN

OUT

37

IN

37

38 37

37

OUT

R4320

5%

MF

2011/20W

0

SMBUS_SMC_2_S4_SCL

SMBUS_SMC_2_S4_SDA

1/20W5% 201

41 37

38 37

37

0

MF

PMU_SOC_VBUS_DET_L

R4301

100K

1 2

5%

1/20W

MF

201

We can remove R4304 this once we verify grounding is ok

IN

41

NC NC

41

IN

41

NC NC NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC NC

To T208, Device ID=0x3C, READ=0x79, WRITE-0x78

51

IN

51

BI

To SMC, Device ID=0x3C, READ=0x79, WRITE-0x78

R4302

100K

PP3V3_S4_SOC_PMU

5%

1/20W

MF

201

1 2

PMU_SOC_UWAKE_L

41

BB_FORCE_PWM

SOC_PMU_INCKT_OTP

40 101

41

R4303

R4315

0

5%

1/20W

MF

201

1 2

100K

5%

1/20W

MF

201

345678

BUCK0

BUCK1

BUCK2

BUCK3

SW3C

LDO7

LDO0

SW1

SW2

SW3A

38

39

PP1V1_SLEEP3_BUCK2

37

39

37 39

PP0V6_SLEEP1_BUCK0

PP0V8_SLEEP2_BUCK1

PP0V6_SLEEP2_LDO0

PP0V8_SLEEP1_SW1

PP1V1_SLEEP1_SW2

PP1V8_SLEEP3_BUCK3

PP1V8_SLEEP2_SW3A

PP1V8_AWAKE_SW3C

PP3V0_AWAKE_LDO7

2 1

T208 POWER ALIASES

PP0V6_SLEEP1_BUCK0

VOLTAGE=0.6V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP0V8_SLEEP2_BUCK1

VOLTAGE=0.8V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP0V6_SLEEP2_LDO0

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V8_SLEEP1_SW1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP0V8_SLEEP1_SW1

PP1V1_SLEEP3_BUCK2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP1V1_SLEEP3_BUCK2

PP1V1_SLEEP1_SW2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP1V1_SLEEP1_SW2

PP1V8_SLEEP3_BUCK3

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_SLEEP2_SW3A

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP1V8_SLEEP2_SW3A

PP1V8_AWAKE_SW3C

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

PP1V8_AWAKE_SW3C

PP3V0_AWAKE_LDO7

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 MAKE_BASE=TRUE

VOLTAGE=3.0V

VOLTAGE=1.1V

VOLTAGE=1.8V

40

VOLTAGE=0.8V

40

39

40

37

38

37

40

40 37

37

41

40 38 37

38

37 38 39

40

D

38

C

B

A

48

SMC_SOCPMU_RESET

Signal Aliases

SMC_SOCPMU_RESET

41

MAKE_BASE=TRUE

BOM_COST_GROUP=T151

SYNC_MASTER=J79_ANDREW SYNC_DATE=02/01/2016

PAGE TITLE

Berkelium - 2

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

43 OF 145

SHEET

41 OF 119

D

A

8 7 5 4 2 1

36

T208 Support

345678

2 1

D

PP1V8_S0SW_DFR

1

R4491

24K

5% 1/20W MF 201

2

38

BI

IN

104 42

38 37

IN

104 38 37

BI

104

104 37

IN

R4481

4.7K

5%

1/20W

MF

201

1

SMC_LID

SYM_VER_2

D

3

S G

2

Q4400

DMN32D2LFB4

DFN1006H4-3

DFR_TOUCH_LID

104

DFR_TOUCH_GPIO2

DFR_TOUCH_SPI_CS_L

DFR_TOUCH_SPI_MOSI_R

DFR_TOUCH_ROM_I2C_SCL DFR_TOUCH_ROM_I2C_SDA

DFR_TOUCH_RESET_L

104 42 37

1

2

PP1V8_S0SW_DFR

106

PP5V_S0_T139

101 104

106 104 42 37

DFR Connectors

1

C4490

100PF

5% 25V

2

C0G 0201

106 104 42 37

104 50 49 43

DFR Touch Conn

J4402

AA07-S022VA1

F-ST-SM

24

23

12

34

56

78

910

1112

1314

1516

1718

1920

2122

25

26

106 104 42 37

DFR_TOUCH_PANEL_DETECT DFR_DISP_VSYNC

DFR_TOUCH_SPI_MISO_R DFR_TOUCH_SPI_CLK_R

DFR_TOUCH_INT_L DFR_CLKIN_RESET_L

DFR_TOUCH_ROM_WC

PP1V8_S0SW_DFR

42 37

106 104

R4480

10K

5%

1/20W

MF

201

PP1V8_S0SW_DFR

IN

104 38

104 42 38

104 38

BI

OUT

104 42

IN

1

NOSTUFF

2

80 42

IN

NOSTUFF

1

R4485

4.7K

5% 1/20W MF 201

2

38

80

OUT

P3V3S0SW_RAMP

1

2

C4410

2200PF

10% 10V

X7R-CERM

0201

DFR_DISP_PWR_EN

R4492

IN

104 38

100K

1/20W

201

DFR_DISP_RST_L

DFR_DISP_SMC_RST_L

1

100

5%

MF

2

3.3V DFR Switch

1

VDD

U4405

SLG5AP1443V

7 3

CAP

2 5

ON S

TDFN

42

PP1V8_S037 38

1

C4403

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP3V3_S5_T139

1

2

D

EDP: 182mA

1/20W

2

B

1

A

NC

C4400

1.0UF

20%

6.3V X5R

0201-1

R4490

0

1 2

5%

6

U4406

NC

3

5

104

NOSTUFF

MF

201

74LVC1G08FW5

DFN1010

4

Y

R4400

100K

5%

1/20W

MF

201

42 101

PP3V3_S0SW_DFR

DFR Disp Conn

J4401

DF40PG(1.5)-26DS-04V(51)

42

38

104

104 38

1

2

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

OUT

VOLTAGE=3.3V

DFR_DISP_VSYNC

DFR_DISP_TE

DFR_DISP_INT

DFR_DISP_RESET_L

104

10%

6.3V X5R

0201

1

2

C4470

0.1UF

F-ST-SM

GND

2728

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2930

GND_VOID=TRUE

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

VOLTAGE=1.8V

DFRDRV_I2C_SCL DFRDRV_I2C_SDA

105 104

IN

BI

MIPID_CLK_CONN_P

MIPID_CLK_CONN_N

MIPID_DATA_CONN_P

MIPID_DATA_CONN_N

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

PP1V8_S0SW_DFR

1

104 38 37

PLACE_NEAR=J4401:5mm

2

GND_VOID=TRUE

C4471

1UF

10%

10V

X5R-CERM 0402

1

2

MIPID FILTERING

L4401

3.25-OHM-0.1A-2.4GHZ TAM0605-4SM

SYM_VER-1

4

L4400

3.25-OHM-0.1A-2.4GHZ TAM0605-4SM

SYM_VER-1

4

1

EDP: 32.6mA

OUT

C4401

1UF

10%

10V

X5R-CERM 0402

PLACE_NEAR=J4401:2.54mm

GND_VOID=TRUE

1

23

GND_VOID=TRUE

1

23

MIPID_CLK_P

GND_VOID=TRUE

MIPID_CLK_N

PLACE_NEAR=J4401:2.54mm

MIPID_DATA_P

GND_VOID=TRUEGND_VOID=TRUE

MIPID_DATA_N

U4404

NCP160AMX180

XDFN-COMBO

EPAD GND

5

2

IN

EN

4

3

DFR_DISP_PWR_EN

IN

38

PP3V3_S5_T139

IN

D

42 101

1

80 42

C4402

1UF

10%

10V

2

X5R-CERM 0402

C

B

14

IN

PP3V3_S4_SOC_PMU

38 42 101

SOC

37

OUT

BI

SOC_SWCLK

SOC_SWDIO

INT PU SOC 50k

PCH_SWD_MUX_SEL

SWD DEBUG MUX

9

VCC

5

M+

4

M-

7

D+

6

D-

8

OE*SEL

10

1

Y+

2

Y-

U4408

PI3USB102EZLE

TQFN

GND

3

PLACE_NEAR=U4408:2mm

1

C4444

0.1UF

10%

6.3V

2

CERM-X5R 0201

SOC_XB_DBG1_1V8 SOC_XB_DBG2_1V8

SOC_SWD_CLK PCH_SWD_IO

(When SEL driven high)

ACE

(Default)

42

IN

14

BI

PCH

GND

8

Part

Type

R(on)

SLG5AP1443V

Load Switch

17 mOhm Typ

U4405

C

@ 3.3V 19 mOhm Max

Current

T208 I2C Mapping

Bus

AP0

AP1

19 14

AP2_0 Tesla

AOP0

Device

PMU

Touch EEPROM

Mesa EEPROM

AOP1 ALS

SEP

M34128 EEPROM

2.5A Max

7-bit Address

0011110 (0x3C)

1010000 (0x50)

1010100 (0x4C)

101000x (0x50/0x51)

0111001 (0x39)

1010001 (0x51)

8-bit Address

Read

Write

0x79 0x78

0xA1 0xA0

0x99 0x98

0xA1/A3 0xA0/A2

0x73 0x72

0xA3 0xA2

37

OUT

37

38

DFR_TOUCH_SPI_MISO

PLACE_NEAR=U3900.Y20:5mm

37

IN

PLACE_NEAR=U3900.AB21:5mm

IN

PLACE_NEAR=U3900.C9:5mm

IN

PLACE_NEAR=U3900.B9:5mm

IN

DFR_TOUCH_SPI_MOSI

DFR_TOUCH_SPI_CLK

MESA_SPI_MOSI

MESA_SPI_CLK

R4453

0

1 2

5%

1/20W

MF

201

R4455

0

1 2

5%

1/20W

MF

201

R4456

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=J4402.7:5mm

DFR_TOUCH_SPI_MISO_R

R4454

0

1 2

5%

1/20W

MF

201

DFR_TOUCH_SPI_MOSI_R

DFR_TOUCH_SPI_CLK_R

MESA_SPI_MOSI_R

R4457

0

1 2

5%

1/20W

MF

201

MESA_SPI_CLK_R

SPI TERM

104 42

OUT

39 38

104 42

39 38

47

OUT

104 42

39 38

PLACE_NEAR=U3900.B10:5mm

IN

47

SOC_ROM_SPI_MISO

PLACE_NEAR=U3900.D10:5mm

IN

SOC_ROM_SPI_MOSI

SOC_ROM_SPI_CLK

R4450

100

1 2

5%

1/20W

MF

201

R4452

0

1 2

5%

1/20W

MF

201

SOC_BOOT:SPI

PLACE_NEAR=U3906.2:5mm

SOC_ROM_SPI_MISO_R

R4451

0

1 2

5%

1/20W

MF

201

SOC_ROM_SPI_CLK_R

SOC_BOOT:SPI

SOC_ROM_SPI_MOSI_R

SOC_BOOT:SPI

IN

OUT

37

OUT

37

B

A

T208

37

BI

ALS I2C

8

VCCVL

IO/VCC1 IO/VCC2

PP3V3_S0101

1

C4451

0.1UF

10% 16V

2

X5R-CERM 0201

R4420

100

1/20W

201

MF

7

I2C_ALS_SCL_R

6

I2C_ALS_SDA_R

5%

1

R4421

100

1/20W

201 MF

2

5%

PP1V8_S0

37 100

1

C4450

0.1UF

10% 16V

2

X5R-CERM 0201

1/20W

1 2

R4470

100K

5%

MF

201

1

U4403

NLSX4402

ALS_SCL_I2C_1V8 I2C_ALS_SCL ALS_SDA_I2C_1V8

IN

SOC_ALS_LS_EN

2 3

5

IO/VL1 IO/VL2

EN

UDFN

GND

4

PP1V8_S037 38 42 100

R4440

47K

5%

1/20W

MF

201

1 2

PCH_TO_SOC_UART_TXD

PCH_ALS_TO_SOC_UART_TXD

SOC_TO_PCH_ALS_UART_TXD

38

R4441

47K

5%

1/20W

MF

201

1 2

OUT

R4471

1/20W

1 2

R4472

1K

5%

MF

201

BI

38

R4442

47K

38

1 2

5%

1/20W

MF

201

IN

R4443

47K

5%

1/20W

104 80

IN

MF

201

1 2

38

OUT

1K

5%

1/20W

MF

201

1 2

ALS

80

OUT

I2C_ALS_SDA SOC_TO_PCH_UART_TXD

104

1

C4440

0.1UF

10% 16V

2

X5R-CERM 0201

SOC_UART_LS_EN

T208

T208 LEVEL SHIFTING

ALS/DEBUG UART

1 2

R4444

100K

5%

1/20W

MF

201

12

2

3

4

5

1

VL VCC

U4401

NLSX5014MU_G

EN

IOLV[1]

IOLV[2]

IOLV[3]

IOLV[4]

UQFN

GND

6

PP3V3_S0

11

IOVCC[1]

IOVCC[2]

IOVCC[3]

IOVCC[4]

1

C4441

0.1UF

10% 16V

2

X5R-CERM 0201

10

9

8

7

SOC_DBG_UART_R2D

SOC_DBG_UART_D2R

ALS_SOC_UART_R2D

ALS_SOC_UART_D2R

38 101

IN

OUT

PCH

IN

OUT

19

ACE SWD DBG

38 100

T208 SWD MUX ACE DBG

PP1V8_S4

1

C4460

0.1UF

10% 16V

2

X5R-CERM 0201

1/20W

1 2

R4460

100K

5%

MF

201

1

U4402

NLSX4402

SOC_XB_DBG1_1V8

42

SOC_XB_DBG2_1V8

42

SOC_SWD_LS_EN

2 3

5

IO/VL1 IO/VL2

EN

UDFN

GND

4

BOM_COST_GROUP=T151

PP3V3_S4_SOC_PMU

8

VCCVL

IO/VCC1 IO/VCC2

7 6

38 42 101

1

C4461

0.1UF

10% 16V

2

X5R-CERM 0201

MAKE_BASE=TRUE

SOC_SWCLK_DBG SOC_SWDIO_DBG

MAKE_BASE=TRUE

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SOC_SWCLK_DBG

SOC_SWDIO_DBG

T208 Support

DRAWING NUMBER SIZE

REVISION

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PAGE

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051-00515

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dvt-fab09-0

44 OF 145

42 OF 119

30

D

A

SYNC_DATE=07/01/2016SYNC_MASTER=J79_ANDREW

8 7 5 4 2 1

36

D

C

GND_FAN

104 43

PP5V_S0_FAN_CONN

FAN_LT_TACH

104 58

FAN_LT_PWM

104 58

PP5V_S0_KBD

43 101 104

PP3V3_G3H

50 100 104

KBD_BLC_GSSOUT

104 43

KBD_BLC_GSLAT

PP3V3_S4

101 104

KBD_BLC_GSSIN

104 43

KBD_BLC_XBLANK

104 43

KBD CONNECTOR

J4500

DF40PC-40DS-0.4V-51

F-ST-SM

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

104 43

GND_FAN

VOLTAGE=0V

PP5V_S0_FAN_CONN

VOLTAGE=5V

FAN_RT_TACH

FAN_RT_PWM

PP5V_S0_KBD

KBD_I2C_SDA KBD_INT_L KBD_I2C_SCL SMC_LSOC_RST_L

KBD_BLC_GSSCK

516S00177 (RCPT, 0.3A per pin)

MATE WITH PLUG 516S00054

XW4500

SM

1 2

43 101 104

345678

2 1

R4513

33

TPAD CONNECTOR

R4512

33

1 2

5%

1/20W

MF

201

J4501

DF40C-50DS-0.4V-51

SMBUS_SMC_3_SCL

51 104

SMBUS_SMC_3_SDA

51 104

104 43

XW4502

SM

1 2

104 58

104 43

104 50

104 43

PP5V_S0

1

C4501

12PF

5% 25V

2

NP0-C0G 0201

58 101

C4501 FOR DESENSE

104 43

KBD_INT_L KBD_I2C_SDA

KBD_I2C_SCL KBD_BLC_XBLANK

KBD_BLC_GSSIN

KBD_BLC_GSSOUT

KBD_BLC_GSSCK KBD_BLC_GSLAT

104 43

ACT_GND

F-ST-SM

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

SMC_LID SMC_PME_S4_WAKE_L SMC_ACTUATOR_DISABLE_L TPAD_SPI_INT_CONN_L

104

TPAD_SPI_MOSI_R TPAD_SPI_CS_CONN_R_L

104

TPAD_SPI_MISO_R TPAD_SPI_IF_EN_CONN

104

TPAD_SPI_CLK_R

104

PP5V_S4_TPAD_CONN

VOLTAGE=5V

PP3V3_S4_TPAD

PP3V3_S0

SMC_VIBE_L

XW4501

SM

104 43

ACT_GND

1 2

50 104

OUT

104 43

43 101 104

43 101

50

104 50 49 42

104 43

C4500

0.1UF

10% 25V X5R 402

1

2

FERR-120-OHM-1.5A

1

2

1 2

5%

1/20W

MF

201

TPAD_SPI_CS_CONN_L

R4511

33

1 2

5%

1/20W

MF

201

NOSTUFF

C4511

12PF

5% 25V NP0-C0G 0201

R4510

33

1 2

5%

1/20W

MF

201

L4500

1 2

0402A

TPAD_SPI_MOSI

TPAD_SPI_MISO

TPAD_SPI_CLK

PP5V_S4

16

43

16

D

101

F4500

PPBUS_S4_HS_TPAD

100

2.5A-16V-0.1OHM

1 2

104

PPVIN_S4_TPAD_FUSE

C

B

16

104 77 74 48 19 14

PP3V3_S4_TPAD

43 101 104

TPAD_SPI_IF_EN

IN

PM_SLP_S4_L

IN

C4530

0.1UF

10% 10V

X5R-CERM

0201

NOSTUFF

R4535

0

1 2

5%

1/20W

MF

201

1812

VOLTAGE=12.6V

516S00187, MATE WITH 516S00188

TRACKPAD ISOLATION

PP3V3_SUS

101

10% 10V

0201

1

2

CRITICAL

U4531

74LVC1G08GW

SOT353

5

4

Y

3

1

B

2

A

NOSTUFF

R4537

0

1 2

5%

1/20W

MF

201

C4531

PP3V3_S4_TPAD

1

2

1

B

2

A

CRITICAL

U4530

5

74LVC1G08GW

SOT353

4

Y

3

TPAD_SPI_IF_EN_CONN

101 43

104 43

16

IN

PP3V3_S0

TPAD_SPI_CS_L

43 101 104

1

GS

2

SIGNAL_MODEL=TPAD_FET

Q4530

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

1

R4530

100K

5% 1/20W MF 201

2

TPAD_SPI_CS_CONN_L

NOSTUFF

R4536

0

1 2

5%

1/20W

MF

201

43

16

IN

0.1UF

X5R-CERM

TPAD_SPI_INT_L

PP3V3_S4_TPAD

1

R4531

100K

5% 1/20W MF 201

2

TPAD_SPI_INT_CONN_L

43 101 104

B

104 43

A

SYNC_MASTER=J79_GAREN

PAGE TITLE

Connectors&ESD

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=KEYBOARD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/21/2015

051-00515

9.0.0

dvt-fab09-0

45 OF 145

43 OF 119

A

D

345678

2 1

D

C

B

A

SYNC_MASTER=J79_DAYU SYNC_DATE=05/26/2015

PAGE TITLE

Empty

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

46 OF 145

44 OF 119

A

D

345678

2 1

D

C

B

A

SYNC_MASTER=J79_DAYU SYNC_DATE=05/26/2015

PAGE TITLE

Empty

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

47 OF 145

45 OF 119

A

D

345678

2 1

D

C

B

A

PAGE TITLE

Empty

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=05/12/2015SYNC_MASTER=J79_DAYU

051-00515

9.0.0

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48 OF 145

46 OF 119

A

D

MOJAVE 16V BOOST

345678

2 1

ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE

D

C

PP3V3_S4_MESA

47 101

1

C4910

10UF

20%

6.3V

2

CERM-X5R 0402-9

PP3V3_S4_MESA

47 101

47

MESA_BOOST_EN

3.0V MESA

MIN_LINE_WIDTH=0.0900

L4901

MIN_NECK_WIDTH=0.0520

1.0UH-0.4A-0.636OHM

1 2

0402

PP3V3_S4_MESA_SW

DIDT=TRUE VOLTAGE=3.3V

MOJAVE_EN_M

NOSTUFF

R4915

0

1 2

5%

1/20W

MF

0201

R4916

0

1 2

5%

1/20W

MF

0201

Option to feed LDO from 5V in case of dropout issue

B1

A2

B2 A3

C2

SW

VIN

EN_M EN_S

LDOIN

U4900

LM3638

BGA

PGND

AGND

B3

A1

XW4900

SHORT-0201

1 2

C3

VOUT

C1

PMID

P16V0_AGND

PP16V0_MESA

VOLTAGE=17V

PP17V0_MOJAVE_LDOIN

1

C4923

2.2UF

20% 25V

2

X5R 0402-3

VOLTAGE=0V

1

C4924

2.2UF

20% 25V

2

X5R 0402-3

42

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=16V

1

C4925

2.2UF

20% 25V

2

X5R 0402-3

1

C4926

56PF

5% 25V

2

NP0-C0G 0201

EDP:12.5mA

47 104

42

38

IN

MESA_SPI_MISO

OUT

FL4900

80-OHM-25%-500MA

104 47 47

PP16V0_MESA PP16V0_MESA_CONN

1 2

0201

1

C4927

100PF

5% 25V

2

C0G 0201

VOLTAGE=16V MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

R4950

0

1 2

5%

1/20W

MF

0201

R4951

56

1 2

5%

1/20W

MF

201

R4912

0

1 2

5%

1/20W

MF

0201

PLACE_NEAR=J4900:3MM

MESA_SPI_MOSI_CONN

1

C4950

56PF

5% 25V

2

NP0-C0G 0201

MESA_SPI_CLK_CONNMESA_SPI_CLK_R

1

C4951

56PF

5% 25V

2

NP0-C0G 0201

1

C4952

56PF

5% 25V

2

NP0-C0G 0201

ESD_GND

104

MIN_LINE_WIDTH=0.0900

MESA FLEX CONNECTOR

Proto1 Connector for X434/X435 Support

PLUG (516S00115) - X434/ X435 Jumper Recptacle (516S00203) - X362/X363 MLB

MESA_SNSR_INTMESA_SPI_MOSI_R

OUTIN

MESA_BOOST_EN

104 47

SMC_ONOFF_LMESA_SPI_MISO_CONN

OUT

104 47

R4953

1 2

R4954

1 2

R4911

1 2

P2MM

SM

1

PP

P2MM

SM

1

PP

680

5%

1/20W

MF

201

680

5%

1/20W

MF

201

0

5%

1/20W

MF

201

PP4900

PP4901

MESA_SNSR_INT_CONN

1

C4953

100PF

5% 25V

2

C0G 0201

MESA_BOOST_EN_CONN

1

C4954

100PF

5% 25V

2

C0G 0201

MENU_KEY_L

1

C4955

100PF

5% 25V

2

C0G 0201

104 47

D

104 47

C

PP3V3_S4_MESA

47 101

1

C4911

1UF

10% 10V

2

X5R-CERM 0402

104 47

PP1V8_MESA

PP3V0_MESA_CONN

47

U4910

NCP160AMX300

4

IN

3

EN

XDFN-COMBO

EPADGND

5

2

OUT

1

PP3V0_MESA

1

C4916

1UF

10% 10V

2

X5R-CERM 0402

EDP:100mA

104 47

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

104 47

PP3V0_MESA

VOLTAGE=3.0V

1

C4920

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

C4921

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

C4922

2.2UF

20%

6.3V

2

X5R-CERM 0201

FL4910

80-OHM-25%-500MA

1 2

0201

C4928

0.1UF

10% 10V

X6S-CERM

0201

PP3V0_MESA_CONN

1

C4929

100PF

2

5% 25V C0G

0201

1

2

47

VOLTAGE=3.0V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

J4900

505066-1220

F-ST-SM

1314

12

104 47

MESA_SPI_MISO_CONN MESA_SNSR_INT_CONN

104 47

MESA_BOOST_EN_CONN MESA_SPI_MOSI_CONN

104 47 37

MESA_I2C_SDA MESA_I2C_SCL

Mesa Power Sequencing Requirements

PP1V8_MESA_CONN

34

56

78

MENU_KEY_L

910

1112

1516

MESA_SPI_CLK_CONN

PP16V0_MESA_CONN

47

47 104

104 47

B

1.8V MESA

47 101

PP3V3_S4_MESA

1

C4912

1UF

10% 10V

2

X5R-CERM 0402

MESA_PWR_EN

U4920

LP5907SNX-1.825

4 1

VIN

3

EN

X2SON

2

VOUT

EPADGND

5

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

PP1V8_MESA

1

C4914

1UF

10% 10V

2

X5R-CERM 0402

EDP:1.5mA

FL4920

80-OHM-25%-500MA

PP1V8_MESA PP1V8_MESA_CONN

104 47 47

1

C4918

2.2UF

20%

6.3V

2

X5R-CERM 0201

1 2

0201

1

C4917

100PF

5% 25V

2

C0G 0201

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

VOLTAGE=1.8V

Power On: 1V8 -> 3V3 -> 16V0

1

2

104 47 37 37

104 47 37

MESA_I2C_SCL

ININ

MESA_I2C_SDA

BI

PP1V8_MESA_CONN

R4920

2.2K

5% 1/20W MF 201

1

R4921

2.2K

5% 1/20W MF 201

2

B

47

I2C pullups on same rail as EEPROM VCC

A

SYNC_MASTER=J79_ANDREW

PAGE TITLE

MESA

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=T151

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

49 OF 145

47 OF 119

D

SYNC_DATE=01/06/2016

A

345678

2 1

D

C

B

13

105 13

13

19

13

15

14

51

50

51

50

51

58

49

50

18

50

49

105 49

50

50 49

50 49 28

74 49

50 49

50

94 51 28

50 49

104 74 19 14

92 80 77 74 73 26 19 14

104 77 74 43 19 14

104

104 77 19 14

104 50 49 47

50

50 36 35

BI

IN

BI

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

BI

OUT

BI

OUT

BI

OUT

IN

BI

IN

OUT

IN

OUT

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_CLK24M_SMC LPC_FRAME_L SMC_LRESET_L LPC_SERIRQ LPC_CLKRUN_L LPC_PWRDWN_L SMC_RUNTIME_SCI_L SMC_WAKE_SCI_L

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SDA SMBUS_SMC_2_S4_SCL SMBUS_SMC_2_S4_SDA SMBUS_SMC_3_SCL SMBUS_SMC_3_SDA SMBUS_SMC_4_G3H_SCL SMBUS_SMC_4_G3H_SDA SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA

SMC_FAN_0_CTL SMC_FAN_0_TACH SMC_FAN_1_CTL SMC_FAN_1_TACH SMC_TOPBLK_SWP_L SMC_SENSOR_PWR_EN

SMC_DEV_SUPPLY_L SMC_ACTUATOR_DISABLE_L NC_SMC_GFX_SELF_THROTTLE NC_SYS_ONEWIRE SMC_CLK12M_EN SMC_PCH_SUSACK_L

CPU_PECI_R SMC_PECI_L

SMC_CHGR_INT_L NC_SMC_DP_HPD_L SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_PMIC_INT_L SMC_SENSOR_ALERT_L SMC_VIBE_L SMC_LID_LEFT

SMC_PCH_SUSWARN_L SMC_USBC_INT_L SMC_AUX_OK PM_SLP_S0_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_ONOFF_L

WLAN_UART_TX WLAN_UART_RX

SMC_LID_RIGHT

(IPD when sampling)

SMC_WIFI_PWR_EN

(OD) (OD)

(OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD) (OD)

(IPU) (OD) (IPD)

(OD)

D10

PL3

B13

PL2

C11

PL1

A13

PL0

H10

PM5

C12

PL4

C13

PL5

G10

PM4

G11

PM2

F10

PM0

G12

PM1

B11

PK5

D13

PB2/I2C0SCL

D12

PB3/I2C0SDA

N4

PA6

L5

PA7

N10

PF6

K8

PF7

N9

PG0

M9

PG1

L9

PG2

L8

PG3

N5

PG6

M5

PG7

H13

PM6

H11

PM7

A12

PK6

B12

PK7

K4

PN2

A9

PN3

L12

PN4

M12

PN5

N13

PN6

L11

PN7

K3

PH2

K2

PH3

C6

PJ7

C7

PJ6

J10

PP0

H12

PP1

K6

PP2

J11

PP3

J12

PP4

K7

PP5

A7

PP6

L6

PP7

D2

PQ0

D1

PQ1

F1

PQ2

M6

PQ3

N6

PQ4

L7

PQ5

M7

PQ6

N7

PQ7

L3

PA0/U0RX

K5

PA1/U0TX

E13

PL7

E12

PL6

U5000

TM4EA231H6ZXRI

BGA

SYM 1 OF 2

OMIT_TABLE

PA2/SSI0CLK PA3/SSI0FSS

PA4/SSI0RX PA5/SSI0TX

PE3 PE2 PE1 PE0 PD7 PD6 PD5 PD4 PE5 PE4 PB4 PB5 PD3 PD2 PD1 PD0 PK0 PK1 PK2 PK3 PE7 PE6 PN1 PN0

PC7 PC6 PC4 PC5 PJ5 PJ4

PB0 PB1 PB6 PB7

PF0 PF1 PF2 PF3 PF4 PF5

PG4 PG5

PH0 PH1

PH4 PH5 PH6 PH7

PJ0 PJ1 PJ2 PJ3

PM3

G4 G3 G2 G1 C2 C3 A1 A2 A3 B3 A4 B4 D4 D3 C1 B1 H4 H3 H1 H2 C4 C5 B5 A5

M1 N1 M3 M2 B6 A6

N2 N3 L4 M4

E11 D11 E3 E4

L10 N11 N12 M11 K10 M10

M8 N8

L2 L1

K1 J3 J2 J4

D8 A8 B8 C8

G13

SMC_CPU_HI_ISENSE SMC_PBUS_VSENSE SMC_BMON_ISENSE SMC_DCIN_ISENSE SMC_DCIN_VSENSE SMC_CPUGT_ISENSE SMC_CPU_ISENSE SMC_OTHER5V_HI_ISENSE SMC_OTHER3V3_HI_ISENSE SMC_DDR1V2_ISENSE SMC_CPUEDRAM_ISENSE SMC_PCH_ISENSE SMC_TPAD_ISENSE SMC_PICCOLO_ISENSE SMC_SSDNAND_ISENSE SMC_PCHPRIMCORE_ISENSE SMC_DDR1V8_ISENSE SMC_CPUSA_ISENSE SMC_CPUDDR_ISENSE SMC_CPUSA_VSENSE SMC_CPU_VSENSE SMC_CPUGT_VSENSE SMC_CPU_IMON_ISENSE SMC_CPUGT_IMON_ISENSE

CPU_PROCHOT_L SMC_VCCIO_CPU_DIV2 PM_THRMTRIP_L

SPI_DESCRIPTOR_OVERRIDE_L

CPU_CATERR_L SMC_BT_PWR_EN

SMC_PM_G2_EN PM_DSW_PWRGD SMC_DELAYED_PWRGD SMC_PROCHOT

SMC_DEBUGPRT_RX_L SMC_DEBUGPRT_TX_L PM_RSMRST_L NC_SMC_GFX_THROTTLE_L

NC_SPI_SMC_MISO NC_SPI_SMC_MOSI NC_SPI_SMC_CLK NC_SPI_SMC_CS_L S5_PWRGD PM_PCH_SYS_PWROK

SMC_CBC_ON NC_SMC_GFX_OVERTEMP

ALL_SYS_PWRGD SMC_THRMTRIP

PM_PWRBTN_L PM_SYSRST_L BKLT_PWM_TCON2MLB SMC_ADAPTER_EN

SMC_OOB1_D2R_L SMC_OOB1_R2D_L SMC_SOCPMU_RESET NC_SMC_DEBUGPRT_EN_L

PM_BATLOW_L

(IPU)

(IPD)

(OD) (OD)

OUT

IN

BI

IN

50

49

18

35

14

49

50

77

66

50

49

50

41

50

D

PP3V3_G3H_SMC_ISNS

BYPASS=U5000.E6::5MM

1

C5002

1.0UF

20%

6.3V

2

X5R 0201-1

67 49 6

49 6

19 6

77 74 49

104 49 28

77 17 14

104 73 14

77 74 73

50 17

17 14

104 80

94 28 14

BYPASS=U5000.E6::5MM

1

C5003

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.G8::5MM

1

C5007

0.1UF

10% 10V

2

X5R-CERM 0201

49 57 100

BYPASS=U5000.F6::5MM

1

C5004

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.H6::5MM

1

C5008

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.F8::5MM

1

C5005

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.H7::5MM

1

C5009

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.G6::5MM

1

C5006

0.1UF

10% 10V

2

X5R-CERM 0201

1

R5002

1M

5% 1/20W MF 201

2

80

49

IN

BI

BUF_SMC_RESET_L

SMC_WIFI_EVENT_L SMC_WAKE_L NC_SMC_HIB_L

NO_TEST=1

49

IN

SMC_CLK32K NC_SMC_XOSC1

NO_TEST=1

18

IN

SYSCLK_CLK12M_SMC NC_SMC_OSC1

NO_TEST=1

PP1V2_G3H_SMC_VDDC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.2V

BYPASS=U5000.D7::5MM

1

C5010

1.0UF

20%

6.3V

2

X5R 0201-1

BYPASS=U5000.H9::5MM

1

C5017

1.0UF

20%

6.3V

2

X5R 0201-1

L5001

30-OHM-1.7A

1 2

0402

TM4EA231H6ZXRI

F11

RST*

(OD)

BYPASS=U5000.D7::5MM

1

C5015

0.1UF

10% 10V

2

X5R-CERM 0201

PK4

M13

WAKE*

L13

HIB*

K11

XOSC0

K12

XOSC1

F13

OSC0

F12

OSC1

K13

VBAT

E6

VDDS

E7

VDDS

F6

VDDS

F7

VDDS

F8

VDDS

G6

VDDS

G7

VDDS

G8

VDDS

H6

VDDS

H7

VDDS

D7

VDDC

H9

VDDC

J1

VDDC

J9

VDDC

J13

VDDC

BYPASS=U5000.H9::5MM

1

C5016

0.1UF

10% 10V

2

X5R-CERM 0201

U5000

BGA

SYM 2 OF 2

PC0/SWCLK/TCK PC1/SWDIO/TMS

PC3/SWO/TDO

PC2/TDI

OMIT_TABLE

BYPASS=U5000.J9::5MM

1

C5014

1.0UF

20%

6.3V

2

X5R 0201-1

PP3V3_G3H_SMC_VDDA

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

NC

VDDA

VREFA+ VREFA-

GNDA GNDA

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

B9 C9 C10A11 B10

B7

F3

E1 E2

F2 F4

A10 D5 D6 D9 E5 E8 E9 E10 F5 F9 G5 G9 H5 H8 J5 J6 J7 J8 K9

SMC_TCK SMC_TMS SMC_TDO SMC_TDI

NC

PP3V0_G3H_AVREF_SMC

49

55 54 53 52 50

GND_SMC_AVSS

49

BYPASS=U5000.J1::5MM

1

C5012

0.1UF

10% 10V

2

X5R-CERM 0201

59 49

49

BYPASS=U5000.E1:F2:1MM

BYPASS=U5000.J9::5MM

1

C5013

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.J13::5MM

1

C5011

0.1UF

10% 10V

2

X5R-CERM 0201

1

C5001

0.1UF

10% 10V

2

X5R-CERM 0201

XW5000

SM

12

PLACE_NEAR=U5000.A10:4MM

1

C5020

0.01UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5000.E1:F2:1MM

1

C5021

1.0UF

2

20%

6.3V X5R 0201-1

C

B

A

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

NOTE: Unused pins have "SMC_Pxx" names. Unused

SYNC_MASTER=J79_JACK SYNC_DATE=04/11/2016

PAGE TITLE

pins designed as outputs can be left floating, those designated as inputs require pull-ups.

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

SMC

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

50 OF 145

48 OF 119

A

D

345678

2 1

D

PP3V3_G3H

100

C5165

1.0UF

20%

6.3V X5R

0201-1

SMC AVREF Supply

U5165

REF3330-COMBO

QFN

CRITICAL

5

IN

1

2

GND

4

OUT

NC0 NC1

NC2

NC3 NC4

8

1

NC

2

NC

3

NC

6

NC

7

NC

C5166

CERM-X5R

0402-1

10UF

20%

6.3V

PROCHOT/THRMTRIP Support

PECI Support

PP1V0_S3

49 101

CRITICAL

R5158

100

PP3V0_G3H_AVREF_SMC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.0V

1

2

1

C5167

0.1UF

10% 10V

2

X5R-CERM 0201

GND_SMC_AVSS

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0V

48

67 48 6

55 54 53 52 50 48

48 6

BI

OUT

PLACE_NEAR=Q5159.6:5MM

PM_THRMTRIP_L

PLACE_NEAR=Q5159.3:5MM

1 2

1%

1/20W

MF

201

R5159

100

1 2

1%

1/20W

MF

201

SMC_PROCHOT_LCPU_PROCHOT_L

SMC_THRMTRIP_L

DMN32D2LFB4

Q5159

6

D

1

DMN5L06VK-7

SOT563

VER 3

2

GS

SMC_PROCHOT

IN

48

105 48

IN

SMC_PECI_L

From SMC

48 6

OUT BI

CPU_PECI_R

To SMC

Q5159

3

D

DMN5L06VK-7

SOT563

VER 3

PLACE_NEAR=Q5150.2:5MM

Q5150

DFN1006H4-3

SYM_VER_2

NOSTUFF

C5134

47PF

5% 25V C0G

0201

1

2

3

D

SG

2

1

R5151

330

5% 1/20W MF 201

2

R5134

43

1 2

5%

1/20W

MF

201

D

CPU_PECI

From/To CPU/PCH

C

B

48

Top-Block Swap

R5182

1/20W

SMC_TOPBLK_SWP_L

1K

5%

MF

201

PP3V3_S0

1

2

R5183

1 2

1/20W

1K

5%

MF

201

PCH_STRP_TOPBLK_SWP_L

101

5

4

GS

SMC_THRMTRIP

IN

49 48

C

SMC_AUX_OK

50

SMC_AUX_OK

MAKE_BASE=TRUE

48 49 50

R5112

22

15

PM_CLK32K_SUSCLK_R

Place near CPU

13

OUTIN

1 2

5%

1/20W

MF

201

SMC_CLK32K

48

OUTIN

PP1V0_S3

49 101

SMC_VCCIO_CPU_DIV2

48

1

R5197

100K

1% 1/20W MF 201

2

1

R5196

100K

1% 1/20W MF 201

2

PP3V3_G3H_SMC_ISNS

48 57 100

PP3V3_S4

50 101

PP3V3_S0

101

B

50 48

50 48 28

48

74 48

104 50 48 47

50 48

104 50 43 42

104 48

104 48 28

28

59 48

48

59 48

48 49 50

48

49 48

48

77 74 48

SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_WIFI_EVENT_L SMC_PMIC_INT_L SMC_ONOFF_L SMC_SENSOR_ALERT_L SMC_LID

SMC_DEBUGPRT_TX_L SMC_DEBUGPRT_RX_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_AUX_OK

NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF

SMC_ADAPTER_EN SMC_THRMTRIP SMC_DELAYED_PWRGD

SMC_PM_G2_EN

R5166 R5167 R5168 R5169 R5170 R5172 R5171

R5175 R5176 R5177 R5178 R5179 R5180 R5187 R5185 R5186 R5191 R5192

100K 100K 100K 100K

10K 10K

330K

20K 20K 10K 10K 10K

10K 100K 100K

1 2

1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

1/20W 2015% MF

5% 201

1/20W5% 201

1/20W MF

1/20W5% MF 1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF 1/20W5% 201MF

5% 1/20W MF 201

1/20W

5% MF 201

MF1/20W MF MF5% 1/20W 201 MF5% 1/20W 201

201

MF1/20W5%

2015%

201

2011/20W5% MF 2011/20W5% MF

A

SYNC_MASTER=J79_JACK SYNC_DATE=04/14/2016

PAGE TITLE

SMC Shared Support

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SMC

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

51 OF 145

49 OF 119

A

D

345678

2 1

D

C

B

A

SMC12 ADC Assignments

48

OUT

SMC_CPU_HI_ISENSE

SMC_PBUS_VSENSE

SMC_BMON_ISENSE

SMC_DCIN_ISENSE

SMC_DCIN_VSENSE

SMC_CPUGT_ISENSE

SMC_CPU_ISENSE

SMC_OTHER5V_HI_ISENSE

SMC_OTHER3V3_HI_ISENSE

SMC_DDR1V2_ISENSE

SMC_CPUEDRAM_ISENSE

SMC_PCH_ISENSE

SMC_TPAD_ISENSE

SMC_PICCOLO_ISENSE

SMC_SSDNAND_ISENSE

SMC_PCHPRIMCORE_ISENSE

SMC_DDR1V8_ISENSE

SMC_CPUSA_ISENSE

SMC_CPUDDR_ISENSE

SMC_CPUSA_VSENSE

SMC_CPU_VSENSE

SMC_CPUGT_VSENSE

SMC_CPU_IMON_ISENSE

SMC_CPUGT_IMON_ISENSE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_CPUGT_ISENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_OTHER5V_HI_ISENSE

MAKE_BASE=TRUE

SMC_OTHER3V3_HI_ISENSE

MAKE_BASE=TRUE

SMC_DDR1V2_ISENSE

MAKE_BASE=TRUE

SMC_CPUEDRAM_ISENSE

MAKE_BASE=TRUE

SMC_PCH_ISENSE

MAKE_BASE=TRUE

SMC_TPAD_ISENSE

MAKE_BASE=TRUE

SMC_PICCOLO_ISENSE

MAKE_BASE=TRUE

SMC_SSDNAND_ISENSE

MAKE_BASE=TRUE

SMC_PCHPRIMCORE_ISENSE

MAKE_BASE=TRUE

SMC_DDR1V8_ISENSE

MAKE_BASE=TRUE

SMC_CPUSA_ISENSE

MAKE_BASE=TRUE

SMC_CPUDDR_ISENSE

MAKE_BASE=TRUE

SMC_CPUSA_VSENSE

MAKE_BASE=TRUE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_CPUGT_VSENSE

MAKE_BASE=TRUE

SMC_CPU_IMON_ISENSE

MAKE_BASE=TRUE

SMC_CPUGT_IMON_ISENSE

MAKE_BASE=TRUE

SMC12 Pin Assignments

NC_SMC_GFX_THROTTLE_L

48

NC_SMC_GFX_OVERTEMP

48

NC_SMC_GFX_SELF_THROTTLE

48

NC_SMC_DP_HPD_L

48

NC_SYS_ONEWIRE

48

NC_SMC_DEBUGPRT_EN_L

48

SMC_LID_RIGHT

48

NC_SPI_SMC_MISO

48

NC_SPI_SMC_MOSI

48

NC_SPI_SMC_CLK

48

NC_SPI_SMC_CS_L

48

SMC_VIBE_L

48

MAKE_BASE=TRUE

48 14

OUT IN

SMC_PCH_SUSWARN_L

MAKE_BASE=TRUE

SMC_PCH_SUSACK_L

MAKE_BASE=TRUE

50 48

48 17

SMC_SENSOR_PWR_EN

MAKE_BASE=TRUE

WLAN_UART_RX

48 50

WLAN_UART_TX

48 50

SMC_AUX_OK

66

MAKE_BASE=TRUE

PM_PWRBTN_L

MAKE_BASE=TRUE

SMC_AUX_OK

48 49

MAKE_BASE=TRUE

SMBUS_SMC_4_G3H_SCL

51

MAKE_BASE=TRUE

SMBUS_SMC_4_G3H_SDA

51

MAKE_BASE=TRUE

SMBUS_SMC_2_S4_SCL

51

MAKE_BASE=TRUE

SMBUS_SMC_2_S4_SDA

51

MAKE_BASE=TRUE

SMC_OOB1_D2R_L

48

MAKE_BASE=TRUE

SMC_OOB1_R2D_L

48

MAKE_BASE=TRUE

SMC_ACTUATOR_DISABLE_L

48

MAKE_BASE=TRUE

SMC_CHGR_INT_L

48

MAKE_BASE=TRUE

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

NO_TEST=1

NC_SMC_GFX_OVERTEMP

MAKE_BASE=TRUE

NO_TEST=1

NC_SMC_GFX_SELF_THROTTLE

MAKE_BASE=TRUE

NO_TEST=1

NC_SMC_DP_HPD_L

MAKE_BASE=TRUE

NO_TEST=1

NC_SYS_ONEWIRE

MAKE_BASE=TRUE

NO_TEST=1

NC_SMC_DEBUGPRT_EN_L

MAKE_BASE=TRUE

NO_TEST=1

SMC_LID_RIGHT

MAKE_BASE=TRUE

NC_SPI_SMC_MISO NC_SPI_SMC_MOSI

NO_TEST=1 NO_TEST=1

NC_SPI_SMC_CLK NC_SPI_SMC_CS_L

SMC_VIBE_L

NO_TEST=1 NO_TEST=1

43

SMC_PCH_SUSWARN_L

SMC_PCH_SUSACK_L

SMC_SENSOR_PWR_EN

WLAN_UART_RX

MAKE_BASE=TRUE

WLAN_UART_TX

MAKE_BASE=TRUE

SMC_AUX_OK

PM_PWRBTN_L

SMC_AUX_OK

SMBUS_SMC_4_G3H_SCL

SMBUS_SMC_4_G3H_SDA

SMBUS_SMC_2_S4_SCL

SMBUS_SMC_2_S4_SDA

SMC_OOB1_D2R_L

SMC_OOB1_R2D_L

SMC_ACTUATOR_DISABLE_L

SMC_CHGR_INT_L

14 48

OUTIN

50

IN

104 50

TRUE TRUE

78

52

35

49

14

52

48

88

43 104

66

52

55

53

52

53

55

53

52

55

53

55

54

104 43

49 48 47

Debug Power "Buttons"

PLACE_SIDE=TOP SILK_PART=PWR_BTN

1 2

PLACE_SIDE=BOTTOM

1 2

Thermal Alerts

53

56

IN

56

IN

56

IN

56

IN

56

IN

SMC_LSOC_RST_L

IN

SMC_ONOFF_L

IN

SMC_CPUHI_COMP_ALERT_L

IN

CPUTHMSNS_THM_L

CPUTHMSNS_ALERT_L

TBTTHMSNS_THM_L

TBTTHMSNS_ALERT_L

TBTTHMSNS_THM_T_L

TBTTHMSNS_ALERT_T_L

S4 SMC Wake Sources

104 43

50

IN

35

HALL_SENSOR_LEFT

HALL_SENSOR_RIGHT

SMC_PME_S4_WAKE_L

SMC_PME_S4_DARK_L

DEBUG_BUTTON

CRITICAL

R5226

SOX-152HNT

SM

SILK_PART=PWR_BTN

CRITICAL

R5225

SOX-152HNT

SM

DEBUG_BUTTON

1

R5258

100K

5% 1/20W MF 201

2

R5251

10K

1 2

5%

1/20W

MF

201

R5261

10K

1 2

5%

1/20W

MF

201

SMC_DEV_SUPPLY_L

48

SMC_ONOFF_L

R5216

100

1 2

5%

1/20W

MF

201

R5220

100

1 2

5%

1/20W

MF

201

R5221

100

1 2

5%

1/20W

MF

201

C5256

0.1UF

X5R-CERM

5

1

2

SN74LVC1G02

SOT553-5

02

U5256

3

CRITICAL

PP3V3_G3H

50 100

BYPASS=U5255.6::5MM

OUT

NOSTUFF

R5217

100

1 2

5%

1/20W

MF

201

R5214

100

1 2

5%

1/20W

MF

201

R5210

100

1 2

5%

1/20W

MF

201

R5211

100

1 2

5%

1/20W

MF

201

PP3V3_G3H

BYPASS=U5256.5::5MM

1

10% 10V

2

0201

4

SMC_4FINGERS_RST

SMC_LID_LEFT_R

C5255

0.1UF

10% 10V

X5R-CERM

0201

R5259

0

1 2

5%

1/20W

MF

0201

Debug RESET "Buttons"

104 50 49 48 47

CPUTHRM_THRM:SMC

CPUTHRM_ALRT:SMC

TBTTHRM_THRM:SMC

TBTTHRM_ALRT:SMC

TBTTHRM_THRM:SMC

TBTTHRM_ALRT:SMC

SMC_SENSOR_ALERT_L

66

OUT

1

2

U5255

6

2

1

NC

TP_SMC_DEV_SUPPLY_L

74LVC1G32

SOT891

4

CRITICAL

35

SMC_LID_R

DEBUG_BUTTON

PLACE_SIDE=BOTTOM SILK_PART=RESET_BTN

CRITICAL

SW5227

SOX-152HNT

SM

1 2

OUT

43 100 104

49 48

SMC_PME_S4_WAKE_L

SMC_PME_S4_DARK_L

R5256

0

1 2

5%

1/20W

MF

0201

SMC_LID_LEFT

R5255

10K

1 2

5%

1/20W

MF

201

SMC_LID_RIGHT

104

SMC_RESET_L

Specify one of these BOM GROUPs.

BOM GROUP BOM OPTIONS

CPUTHRM:BOTH CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMC CPUTHRM:THRM CPUTHRM_THRM:SMC,CPUTHRM_ALRT:PU CPUTHRM:ALRT CPUTHRM_ALRT:SMC CPUTHRM:NONE CPUTHRM_ALRT:PU

Specify one of these BOM GROUPs.

BOM GROUP BOM OPTIONS

TBTTHRM:BOTH TBTTHRM_THRM:SMC,TBTTHRM_ALRT:SMC TBTTHRM:THRM TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PU TBTTHRM:ALRT TBTTHRM_THRM:PU,TBTTHRM_ALRT:SMC TBTTHRM:NONE TBTTHRM_THRM:PU,TBTTHRM_ALRT:PU

Requires EMC1412-1 or EMC1412-2 instead of EMC1412-A, new APN needs to be created.

MAKE_BASE=TRUE

NOSTUFF

1

R5257

0

5% 1/20W MF 0201

2

SMC_LID

50

OUT

48

OUT

Hall Effect Pads - Left

J5250

AMR-MLB-X502

104 80 66 59 50

SM

8 7 6

1 2 3 45

OMIT_TABLE

HALL_SENSOR_LEFT

PP3V3_G3H

50 100

NOSTUFF

1

C5250

1000PF

10% 16V

2

X7R-1 0201

50

D

Hall Effect Pads - Right

J5260

AMR-MLB-X502

677-04255

49 48

49 48 28

48 36 35

50 48

104 49 43 42

2 CRITICAL

SUBASSY (T&R) PCBA,HES INTERPOSER,X502

SMC_WIFI_PWR_EN

SMC_SENSOR_PWR_EN

SMC_RESET_L

NOSTUFF

10% 16V

0201

1

2

C5270

1000PF

X7R-CERM

GND_SMC_AVSS

SM

8 7 6

1 2 3 45

OMIT_TABLE

48 50

BOM_COST_GROUP=SMC

HALL_SENSOR_RIGHT

PP3V3_G3H

WLAN_UART_RX

WLAN_UART_TX

R5295

R5294

104 80 66 59 50

55 54 53 52 49 48

50

50 100

NOSTUFF

1

C5260

1000PF

10% 16V

2

X7R-1 0201

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

J5250, J5260

PP3V3_S4

49 101

R5273

10K

1 2

R5274

100K

10K

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

1 2

1/20W5% 201MF

SYNC_MASTER=J79_JACK

PAGE_TITLE=SMC Project Support

Apple Inc.

R

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

C

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

B

201MF1/20W5%

2015% 1/20W MF

MF 2015% 1/20W

SYNC_DATE=04/11/2016

A

DRAWING NUMBER SIZE

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

52 OF 145

SHEET

50 OF 119

D

8 7 5 4 2 1

36

345678

2 1

D

LYNX POINT LP

U0500

(MASTER)

SMBUS_PCH_CLK

13

MAKE_BASE=TRUE

SMBUS_PCH_DATA

13

MAKE_BASE=TRUE

PP3V3_S0

51 101

R5300

1K

5%

1/20W

MF

201

SMC SMBus "0" S0 ConnectionsLYNX POINT LP S0 "SMBus 0" Connections

PP3V3_S0

101

1

2

1

R5301

1K

5% 1/20W MF 201

2

SMC

U5000 U5000

(MASTER)

SMBUS_SMC_0_S0_SCL

48

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

48

MAKE_BASE=TRUE

R5350

1K

5%

1/20W

MF

201

1

2

1

R5351

1K

5% 1/20W MF 201

2

Internal DP

J8500

(0x10-0x1F)

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

80 104

SMC Battery Charger

(MASTER)

SMBUS_SMC_5_G3_SCL

48

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

48

MAKE_BASE=TRUE

Banjo

U7800

(Write: 0x68 Read: 0x69)

SMBUS_SMC_5_G3_SCL

74

SMC SMBus "5" G3H Connections

PP3V3_G3H

100

R5380

2.0K

5%

1/20W

MF

201

1

2

1

R5381

2.0K

5% 1/20W MF 201

2

ISL6259 - U7000

(Write: 0x12 Read: 0x13)

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

(Write: 0x16 Read:0x17)

SMBUS_SMC_5_G3_SCL

Battery

J6951

66

65 104

D

C

ACE I2C Interrupt

U5000

(MASTER)

SMBUS_SMC_2_S4_SCL

51 50

SMBUS_SMC_2_S4_SDA

51 50

PP3V3_S4

51 101

LOADISNS

R5372

SMBUS_SMC_2_S4_SCL

51 50

SMBUS_SMC_2_S4_SDA

51 50

1

100K

5%

1/20W

MF

201

2

BYPASS=U5372.1::5MM

SMBUS_2_OE

SMC

1

C5372

0.1UF

10%

6.3V

2

CERM-X5R 0201

LOADISNS

SMC SMBus "2" S4 Connections

PP3V3_S4

51 101

1

U5372

TXS0102DQE

5

2 3

X2SON-COMBO

OE

CRITICAL

A1

LOADISNS

A2

NO_XNET_CONNECTION=1

1K

5%

1/20W

MF

201

1

2

R5370

NO_XNET_CONNECTION=1

PP5V_S4SW_ISNS

1

C5373

0.1UF

10% 10V

2

X5R-CERM 0201

BYPASS=U5372.8::3MM

SMBUS_2_SCL_Q

MAKE_BASE=TRUE

CKPLUS_WAIVE=I2C_PULLUP

GND

4

8

VCCBVCCA

7

B1

6

B2

SMBUS_2_SDA_Q

MAKE_BASE=TRUE

CKPLUS_WAIVE=I2C_PULLUP

1K

5%

1/20W

MF

201

1

2

R5371

LOADISNS

(Write: 0x78 Read: 0x79)

SMBUS_SMC_2_S4_SCL

SMBUS_SMC_2_S4_SDA

55 101

(Write: 0x10 Read: 0x11)

SMBUS_2_SCL_Q

SMBUS_2_SDA_Q

(Write: 0x12 Read: 0x13)

SMBUS_2_SCL_Q

SMBUS_2_SDA_Q

Berkelium

U4200

EADC1

U5700

EADC2

U5710

41

55

SMBUS_SMC_5_G3_SDA

SMC SMBus "3" S0 Connections

PP3V3_S0

101

SMC

U5000

(MASTER)

SMBUS_SMC_3_SCL

48

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

48

MAKE_BASE=TRUE

Trackpad

J4501

(Write: 0x98 Read: 0x99)

43 104

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

R5390

2.0K

5%

1/20W

MF

201

SMBUS_SMC_5_G3_SDA

1

2

1

R5391

2.0K

5% 1/20W MF 201

2

X100 Temp

HPA00330AI: U5820

(Write: 0x92 Read: 0x93)

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

65 104

56

C

TBT & Airflow Left

TMP461: U5850

(Write: 0x90 Read: 0x91)

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

56

TBT & Airflow Right

TMP461: U5860

(Write: 0x96 Read: 0x97)

B

LYNX POINT LP S0 "SMLink 0" Connections

LYNX POINT LP

U0500

(MASTER)

SML_PCH_0_CLK

13

MAKE_BASE=TRUE

SML_PCH_0_DATA

13

MAKE_BASE=TRUE

LYNX POINT LP S0 "SMLink 1" Connections

PP3V3_S0

51 101

R5310

8.2K

5%

1/20W

MF

201

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

56

SMC SMBUS "4" G3H CONNECTIONS

PP3V3_G3H

100

SMC

SMC SMBus "1" S0 Connections

1

2

1

R5311

8.2K

5% 1/20W MF 201

2

101

SMC

U5000

(MASTER)

SMBUS_SMC_1_S0_SCL

48

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

48

MAKE_BASE=TRUE

PP3V3_S0

R5360

2.0K

5%

1/20W

MF

201

SMBUS_SMC_4_G3H_SCL

50

MAKE_BASE=TRUE

SMBUS_SMC_4_G3H_SDA

1

2

1

R5361

2.0K

5% 1/20W MF 201

2

Finstack Left, Right

TMP513A: U5870

(Write: 0xB8 Read: 0xB9)

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

CPU, Mem,

56

50

MAKE_BASE=TRUE

28

94 48

UC400 - ADDR: 0X20

U5000

(MASTER)

SMC_USBC_INT_L

MAKE_BASE=TRUE

Pri ACE

1

R5322

10K

5% 1/20W MF 201

2

1

R5320

2.0K

5% 1/20W MF 201

2

(Write: 0x40 Read: 0x41)

SMBUS_SMC_4_G3H_SCL

94

SMBUS_SMC_4_G3H_SDA

94

1

R5321

2.0K

5% 1/20W MF 201

2

USB-C PORT CONTROLLER XA

U3100 - ADDR: 0X38

(WRITE: 0X70 READ: 0X71)

SMBUS_SMC_4_G3H_SCL

SMBUS_SMC_4_G3H_SDA

SMC_USBC_INT_L

USB-C PORT CONTROLLER XB

U3200 - ADDR: 0X3F

(WRITE: 0X7E READ: 0X7F)

SMBUS_SMC_4_G3H_SCL

SMBUS_SMC_4_G3H_SDA

28

29

28

B

A

LYNX POINT LP

U0500

(Write: 0x88 Read: 0x89)

SMBUS_SMC_1_S0_SCL

13

SMBUS_SMC_1_S0_SDA

13

SMLink 1 is slave port to access PCH.

8 7 5 4 2 1

95

SMC_USBC_INT_L

Sec ACE

UC500 - ADDR: 0X27

(Write: 0x4E Read: 0x4F)

SMBUS_SMC_4_G3H_SCL

94

SMBUS_SMC_4_G3H_SDA

94

96

36

SMC_USBC_INT_L

BOM_COST_GROUP=SMC

SMC_USBC_INT_L

SYNC_MASTER=J79_JACK SYNC_DATE=03/31/2016

PAGE TITLE

30

SMBus Connections

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

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PAGE

53 OF 145

SHEET

51 OF 119

D

A

345678

2 1

D

C

B

100

CPU High Side Current Sense (IC0R)

Gain: 100x, EDP: 10.5 A Rsense: 0.003 (R5400)

PP3V3_S0

Vsense: 31.5 mV, Range: 10 A

53 101

SMC ADC: 00

3

V+

PPBUS_HS_CPU

PPBUS_G3H

CRITICAL

0612

0.003

R5400

NO_XNET_CONNECTION=1

CYN

1W 1%

PLACE_NEAR=U5400.5:10MM

4

54

ISNS_HS_COMPUTING_N CPUHI_IOUT

ISNS_HS_COMPUTING_P

54

123

PLACE_NEAR=U5400.4:10MM

U5400

5

IN-

INA214

SC70

OUT

CRITICAL

4

100x

GND

2

6

1

REFIN+

OTHER 5V High Side Current Sense (IO5R)

Gain: 200x, EDP: 1.22 A Rsense: 0.01 (R5410) or Rsense SHORT

PP3V3_S4SW_SNS

Vsense: 12.2 mV, Range: 1.5 A

52 101

SMC ADC:

6

V+

PPBUS_G3H

PPBUS_HS_OTH5V

OMIT

R5410

0.005

0306-SHORT

1%

1/3W

MF

PLACE_NEAR=U5410.2:3:10MM

123

ISNS_HS_OTHER5V_P

ISNS_HS_OTHER5V_N

4

PLACE_NEAR=U5410.4:5:10MM

2

IN+

3

IN+

4

IN-

5

IN-

U5410

INA210A

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

NC NC

OTHER 3.3V High Side Current Sense (IO3R)

Gain: 200x, EDP: 4.31 A Rsense: 0.003 (R5440) or Rsense SHORT

PP3V3_S4SW_SNS

Vsense: 12.93 mV, Range: 5 A

52 101

SMC ADC:

6

V+

PPBUS_G3H

PPBUS_HS_OTH3V3

OMIT

R5440

0.005

0306-SHORT

1%

1/3W

MF

PLACE_NEAR=U5440.2:3:10MM

123

ISNS_HS_OTHER3V3_P

ISNS_HS_OTHER3V3_N

4

PLACE_NEAR=U5440.4:5:10MM

2

IN+

3

IN+

4

IN-

5

IN-

U5440

INA210A

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

NC NC

LCD Backlight Current Sense (IBLR)

Gain: 100x. EDP: 1 A Rsense: 0.025 (R8400) Vsense: 25 mV, Range: 2.4 A EADC1: CH0

79

IN

79

IN

PLACE_NEAR=R8400.4:5MM

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

PLACE_NEAR=R8400.3:5MM

PP3V3_S0

101

LOADISNS

1

C5450

6

V+

U5450

INA214A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

100x

GND

9

OUT

REF

NC NC

10

8

1 7

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U5450.6::5MM

ISNS_LCDBKLT_IOUT

1

R5455

NC NC

6.04K

1% 1/20W MF 201

2

LOADISNS

PLACE_NEAR=U5450.10:5MM

LOADISNS

R5459

453K

1 2

1/20W

201

BYPASS=U5400.3::5MM

1

C5401

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

R5405

15K

5% 1/20W MF 201

2

PLACE_NEAR=U5400.6:5MM

LOADISNS

BYPASS=U5410.6::5MM

1

C5411

0.1UF

10%

6.3V

2

CERM-X5R 0201

HS_OTHER5V_IOUT

1

R5415

15K

1% 1/20W MF 201

2

LOADISNS

PLACE_NEAR=U5410.10:5MM

LOADISNS

BYPASS=U5440.6::5MM

1

C5441

0.1UF

10%

6.3V

2

CERM-X5R 0201

HS_OTHER3V3_IOUT

1

R5445

15K

1% 1/20W MF 201

2

LOADISNS

PLACE_NEAR=U5440.10:5MM

PLACE_NEAR=U5700.22:5MM

EADC1_LCDBKLT_ISENSE

1% MF

1

C5459

0.22UF

20%

6.3V

2

X5R 0201

LOADISNS

PLACE_NEAR=U5700.22:5MM

(to CPU High Side Threshold Alert circuit)

PLACE_NEAR=U5000.E2:5MM

R5409

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_HI_ISENSE

1

C5409

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.E2:5MM

GND_SMC_AVSS

LOADISNS

PLACE_NEAR=U5000.A4:5MM

R5419

4.53K

1 2

1%

1/20W

MF

201

SMC_OTHER5V_HI_ISENSE

1

C5419

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.A4:5MM

GND_SMC_AVSS

LOADISNS

PLACE_NEAR=U5000.B5:5MM

R5449

4.53K

1 2

1%

1/20W

MF

201

SMC_OTHER3V3_HI_ISENSE

1

C5449

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.B5:5MM

GND_SMC_AVSS

55

OUT

53

OUT

50

OUT

117S0008

50

PBUS Voltage Sense & Enable (VP0R)

Gain: 0.167x Vnominal: 12.6 V, Range: 17.97 V SMC ADC: 01

Enables PBUS VSense divider when in S0.

SMC_SENSOR_PWR_EN

SM

PBUS_S0_VSENSE_IN

100

PPBUS_G3H

50

IN

XW5480

1 2

PLACE_NEAR=R5400.1:10 MM

55 54 53 52 50 49 48

100K

1%

1/20W

MF

201

1

2

R5481

CRITICAL

Q5480

NTUD3169CZ

SOT-963

N-CHANNEL

2

1

5

4

G

P-CHANNEL

PBUSVSENS_EN_L_DIV

6

PBUSVSENS_EN_L

D

R5482

S

3

PBUS_S0_VSENSE

D

S

100K

1%

1/20W

MF

201

1

D

2

1%

1/20W

MF

201

1%

1/20W

MF

201

1

Rthevenin = 4573 Ohms

2

SMC_PBUS_VSENSE

1

2

1

C5489

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.E1:5MM

GND_SMC_AVSS

OUT

50

55 54 53 52 50 49 48

R5488

27.4K

R5489

5.49K

DC In Voltage Sense & Enable (VD0R)

Gain: 0.13x Vnominal: 16.5 V, Range: 22.96 V SMC ADC: 04

Enables DC-In VSense divider when AC present.

50

IN

55 54 53 52 50 49 48

100

SMC_AUX_OK

PPDCIN_G3H

R5491

69.8K

1%

1/20W

MF

201

1

2

1

5

4

Charger (BMON) Current Sense (IPBR) DC-IN (AMON) Current Sense (ID0R)

Charger Gain: 20x, EDP: 7.2 A

PLACE_NEAR=U5000.F2:5MM

R5429

300K

1 2

1%

1/20W

MF

201

C5419,C54492 LOADRC:NO

SMC_BMON_ISENSE

1

C5429

3300PF

10% 10V

2

X7R-CERM 0201

GND_SMC_AVSS

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

PLACE_NEAR=U5000.F2:5MM

1

Rsense: 0.005 (R7060) SMC ADC: 02

66

55 54 53 52 50 49 48

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

CHGR_BMON

IN

CRITICAL

Q5490

DMC31D5UDJ

SOT963

N-CHANNEL

D

G

S

D

G

S

P-CHANNEL

PDCINVSENS_EN_L_DIV GND_SMC_AVSS

50

OUT

LOADRC:NOC5469117S0008

6

DCINVSENS_EN_L

3

DCIN_S5_VSENSE

Charger Gain: 20x, EDP: 4.6 A Rsense: 0.010 (R7020) SMC ADC: 03

66

IN

55 54 53 52 50 49 48

200K

1%

1/20W

MF

201

1

2

R5492

PLACE_NEAR=U5000.B3:5MM

1%

1/20W

MF

201

1

Rthevenin = 4129 Ohms

2

R5498

31.6K

SMC_DCIN_VSENSE

PLACE_NEAR=U5000.B3:5MM

1

C5497

0.022UF

10%

6.3V

2

X6S 0201-1

R5499

4.75K

1%

1/20W

MF

201

1

2

1

C5499

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.B3:5MM

PLACE_NEAR=U5000.F1:5MM

R5439

453K

CHGR_AMON SMC_DCIN_ISENSE

1 2

1%

1/20W

MF

201

1

C5439

2200PF

10% 10V

2

X7R-CERM 0201

PLACE_NEAR=U5000.F1:5MM

GND_SMC_AVSS

OUT

C

50

55 54 53 52 50 49 48

50

55 54 53 52 50 49 48

B

A

GND_EADC1_COM

Trackpad Actuator X239 Current Sense (ITAR)

Gain: 24.9x, EDP: 2.61 A (Transient) Rsense: 0.02 (R5460) Vsense: 52.2 mV, Range: 6 A SMC ADC: 12

100

PPBUS_G3H

PP3V3_S4SW_SNS

52 53 54 55 57 101

PLACE_NEAR=U5460.3:3MM

10%

6.3V

0201

1

2

C5460

0.1UF

CERM-X5R

BYPASS=U5460.5::5MM

LOADISNS

OMIT

R5460

0.005

1/3W

0306-SHORT

1 2 3 4

3 4

U5460

INA139

V+

SOT23-5

LOADISNS

CRITICAL

GND

1%

MF

PPBUS_S4_HS_TPAD

PLACE_NEAR=U5460.4:3MM

ISNS_TPAD_NISNS_TPAD_P

VIN-VIN+

15

OUT

2

ISNS_X239_IOUT_BUF

1

R5461

24.9K

1% 1/20W MF 201

2

LOADISNS

52 53 54 55 57 101

PLACE_NEAR=U5460.1:5MM

Gain: 1000uA/V * 24.9KOhm = 24.9

100

OUTIN

PP3V3_S4SW_SNS

C5462

0.1UF

10%

6.3V

CERM-X5R

0201

1

2

55 54 53

ISNS_X239_IOUT

LOADISNS

CRITICAL

U5462

8

3

V+

2

LOADISNS

V-

BYPASS=U5462.8::5MM

OPA2340

MSOP

1

4

LOADISNS

R5465

10K

1 2

1/20W

1% MF

201

PP3V3_S4SW_SNS

52 53 54 55 57 101

ISNS_X239_INT_NI

LOADISNS

R5468

10K

1 2

1%

1/20W

MF

201

LOADISNS

CRITICAL

U5462

8

5

6

V+

V-

LOADISNS

OPA2340

MSOP

7

4

R5467

10K

1 2

1%

1/20W

MF

201

ISNS_X239_INT_I

PLACE_NEAR=U5000.C1:5MM

ISNS_X239_IOUT_INT

LOADISNS

R5469

4.53K

1 2

1%

1/20W

MF

201

SMC_TPAD_ISENSE

1

C5469

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.C1:5MM

LOADRC:YES

GND_SMC_AVSS

BOM_COST_GROUP=SENSORS

OUT

50

SYNC_DATE=12/07/2015SYNC_MASTER=J79_JACK

PAGE TITLE

A

Power Sensors: High Side

DRAWING NUMBER SIZE

Apple Inc.

R

55 54 53 52 50 49 48

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

54 OF 145

SHEET

52 OF 119

D

8 7 5 4 2 1

36

D

C

PCH 1.0V Current Sense (IS1C)

Gain: 200x, EDP: 3.29 A Rsense: 0.003 (R8004) or Rsense SHORT Vsense: 9.87 mV, Range: 5 A SMC ADC: 11

76

52 53 54 55 57 101

PLACE_NEAR=R8004.3:5MM

ISNS_1V0_P

IN

ISNS_1V0_N

PLACE_NEAR=R8004.4:5MM

PP3V3_S4SW_SNS

2

IN+

3

IN+

4

IN-

5

IN-

6

V+

U5560

INA210A

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

LOADISNS

BYPASS=U5560.6::5MM

1

C5560

0.1UF

10%

6.3V

2

CERM-X5R 0201

P1V0S0_IOUT

1

R5565

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5560.10:5MM

DDR 1.2V S3 (CPU & Memory) Current Sense (IM0C)

Gain: 100x, EDP: 8.21 A Rsense: 0.003 (R7918) or XWTBD Vsense: 24.63 mV, Range: 10 A SMC ADC: 09

75

PP3V3_S4SW_SNS

52 53 54 55 57 101

PLACE_NEAR=R7918.3:5MM

IN

ISNS_CPUDDR_P

ISNS_CPUDDR_N

PLACE_NEAR=R7918.4:5MM

6

V+

U5570

INA214A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

100x

GND

9

OUT

REF

NC NC

10

8

1 7

LOADISNS

BYPASS=U5570.6::5MM

1

C5570

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_DDR_IOUT

1

R5575

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5570.10:5MM

LOADISNS

PLACE_NEAR=U5000.H2:5MM

R5569

4.53K

1 2

1%

1/20W

MF

201

SMC_PCH_ISENSE

1

C5569

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.H2:5MM

LOADRC:YES

GND_SMC_AVSS

LOADISNS

PLACE_NEAR=U5000.A5:5MM

R5579

4.53K

1 2

1%

1/20W

MF

201

SMC_DDR1V2_ISENSE

1

C5579

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.A5:5MM

LOADRC:YES

GND_SMC_AVSS

OUTIN

OUT

50

345678

2 1

CPU Fixed Current Sense (ICAC)

Gain: 275.74x, EDP: 29 A Rsense: 2x of 0.00075 (R7310, R7320), Rsum: 0.000375 Vsense: 10.875 mV, Range: 29.01 A SMC ADC: 06

68

IN

68

IN

68

IN

68

55 54 53 52 50 49 48

IN

CPUCORE_ISNS1_P

PLACE_NEAR=R7210:5MM

LOADISNS

CPUCORE_ISNS2_P CPUVR_ISNS_P

PLACE_NEAR=R7220:5MM

LOADISNS

CPUCORE_ISNS1_N

PLACE_NEAR=R7210:5MM

LOADISNS

CPUCORE_ISNS2_N

PLACE_NEAR=R7220:5MM

LOADISNS

R5545

4.42K

1 2

0.1%

1/20W

MF

0201

R5546

4.42K

1 2

0.1%

1/20W

MF

0201

R5547

4.42K

1 2

0.1%

1/20W

MF

0201

R5548

4.42K

1 2

0.1%

1/20W

MF

0201

CPUVR_ISNS_N

LOADISNS

R5542

383

1 2

1/20W

R5543

383

1 2

1/20W

LOADISNS

1%

MF

201

1%

MF

201

PP3V3_S0

101

CPUVR_ISNS_R_P

CPUVR_ISNS_R_N

1

R5544

715K

0.1% 1/20W MF 0201

2

LOADISNS

NO_XNET_CONNECTION=1

1

3

R5541

1 2

V+

V-

2

715K

0.1%

1/20W

MF

0201

LOADISNS

CRITICAL

U5540

5

ISL28133

SC70-5

4

1

R5540

20K

5%

1/20W

MF

201

2

NOSTUFF

PLACE_NEAR=U5540.4:5MM

LOADISNS

NO_XNET_CONNECTION=1

LOADISNS

BYPASS=U5540.5::5MM

1

C5540

0.1UF

10%

6.3V

2

CERM-X5R 0201

R5549

4.53K

1 2

1%

1/20W

MF

201

LOADISNS

PLACE_NEAR=U5000.B4:5MM

SMC_CPU_ISENSECPUVR_ISUM_IOUT

1

C5549

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.B4:5MM

GND_SMC_AVSS

OUT

50

D

55 54 53 52 50 49 48

BT Current Sense (IBTC)

Gain: 200x, EDP: 0.06 A

PP3V3_S4SW_SNS

52 53 54 55 57 101

Rsense: 0.05 (R5580) Vsense: 3 mV, Range: 0.25 A EADC1: CH5

101 106

55 54 53 52 50 49 48

PP3V3_S4

NO_XNET_CONNECTION=1

R5580

0306-SHORT

OMIT

PP3V3_S4_BT

0.005

1%

1/3W

MF

PLACE_NEAR=U5580.2:3:10MM

123

ISNS_BT_P ISNS_S4_BT_IOUT

ISNS_BT_N

4

PLACE_NEAR=U5580.4:5:10MM

2

IN+

3

IN+

4

IN-

5

IN-

6

V+

U5580

INA210A

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

LOADISNS

BYPASS=U5580.6::5MM

1

C5580

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

R5585

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5580.10:5MM

LOADISNS

R5589

453K

1 2

1%

1/20W

MF

201

PLACE_NEAR=U5700.6:5MM

EADC1_BT_ISENSE

LOADISNS

1

C5589

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5700.6:5MM

GND_EADC1_COM

OUT

55

55 54 53 52

C

B

A

CPU DDR 1.2V S3 (CPU Only) Current Sense (IMCC)

Gain: 200x, EDP: 2 A Rsense: 0.005 (R5510) or Rsense SHORT Vsense: 10 mV, Range: 3 A SMC ADC: 18

100

PP1V2_S3

OMIT

R5510

0306-SHORT

100

PP1V2_S3_CPUDDR

0.005

1%

1/3W

MF

PP3V3_S4SW_SNS

52 53 54 55 57 101

PLACE_NEAR=U5510.2:3:10MM

123

ISNS_CPUVDDQ_P

ISNS_CPUVDDQ_N

4

PLACE_NEAR=U5510.4:5:10MM

6

V+

U5510

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

LOADISNS

BYPASS=U5510.3::5MM

1

C5510

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_CPUDDR_IOUT

1

R5515

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5510.10:5MM

T139 Current Sense (IF3C)

Gain: 200x, EDP: 0.06 A Rsense: 0.05 (R5520) or Rsense SHORT Vsense: 3 mV, Range: 0.25 A EADC1: CH3

101

PP3V3_S5

OMIT

R5520

0306-SHORT

101

PP3V3_S5_T139

0.005

1%

1/3W

MF

PP3V3_S4SW_SNS

52 53 54 55 57 101

PLACE_NEAR=U5520.2:3:10MM

123

ISNS_PP3V3S0_P

ISNS_PP3V3S0_N

4

PLACE_NEAR=U5520.4:5:10MM

6

V+

U5520

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

LOADISNS

BYPASS=U5520.6::5MM

1

C5520

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_PP3V3S0_IOUT

1

R5525

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5520.10:5MM

WLAN Current Sense (IAPC)

Gain: 163.3x, EDP: 1.67 A Rsense: 0.015 (R5530) or Rsense SHORT Vsense: 25.05 mV, Range: 1.67 A EADC1: CH4

36 35

106

PP3V3_S4_WLAN_SW

OMIT

0306-SHORT

PLACE_NEAR=U5530.3:10MM

4

MF

1/3W

1%

0.005

36

R5530

PP3V3_S4_WLAN_SW_R

NO_XNET_CONNECTION=1

123

PLACE_NEAR=U5530.4:10MM

PP5V_S4SW_ISNS

101

ISNS_PP3V3S4_WLAN_R_P

ISNS_PP3V3S4_WLAN_P

ISNS_PP3V3S4_WLAN_N

LOADISNS

R5531

120

1 2

0.1%

1/20W

MF

ISNS_PP3V3S4_WLAN_R_N

0201

LOADISNS

R5532

120

1 2

0.1%

1/20W

MF

0201

CKPLUS_WAIVE=PDIFPR_BADTERM

CKPLUS_WAIVE=NDIFPR_BADTERM

ISNS_WLAN_OP

LOADISNS

D5530

SM-0201

A K

DSF01S30SCAP

4

CRITICAL

LOADISNS

3

NO_XNET_CONNECTION=1

52

U5530

LTC2050HVCS5

TSOT23-5

LOADISNS

PLACE_NEAR=U5000.H1:5MM

R5519

4.53K

1 2

1%

1/20W

MF

201

SMC_CPUDDR_ISENSE

1

2

GND_SMC_AVSS

117S0008

LOADISNS

PLACE_NEAR=U5700.1:5MM

R5529

453K

1 2

1%

1/20W

MF

201

EADC1_PP3V3S0_T139_ISENSE

1

2

GND_EADC1_COM

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=5V

PP5V_S4_WLAN_ISNS_D

Q5530

DMP31D0UFB4

DFN1006H4-3

LOADISNS

1

R5533

100K

5% 1/20W MF 201

2

LOADISNS

G

2

S

D

3

GAIN:163.3x

OUT

C5519

0.22UF

20%

6.3V X5R 0201

PLACE_NEAR=U5000.H1:5MM

LOADRC:YES

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5529

0.22UF

20%

6.3V X5R 0201

PLACE_NEAR=U5700.1:5MM

LOADISNS

BYPASS=U5530.5::5MM

1

C5530

0.1UF

10% 10V

2

X5R-CERM 0201

ISNS_PP3V3S4_WLAN_IOUT

LOADISNS

1

R5534

19.6K

0.1% 1/20W MF 0201

2

50

OUT

55 54 53 52

55

CPU High Side Current (IC0R) Threshold Alert

Gain: 100x Rsense: 0.003 (R5400)

PP3V3_S0

52 101

CPUHYS

Trip Target on CPU High current: 2.5 A Hysteresis Circuit: Vref = 0.737 V Vth = 0.616 V -> 2.054 A on CPU High current

1

R5554

294K

1% 1/20W MF 201

2

Vtl = 0.771 V -> 2.571 A on CPU High current Hysteresis Margin = 0.518 A

CPUHYS

1

R5555

55 54 53 52 50 49 48

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

C5569,C5519RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5549,C5579

LOADRC:NO117S0008 2

LOADRC:NO2

84.5K

1% 1/20W MF 201

2

NOSTUFF

D5557

SM-201

CPUHI_COMP_VREF

NOSTUFF

1

R5557

0

5% 1/20W MF 0201

2

BMON_IOUT_D

A

BYPASS=U5551.5::5MM

CPUHYS

1

C5551

0.1UF

10%

6.3V

2

CERM-X5R 0201

CPUHYS

R5556

12K

1 2

1%

1/20W

MF

201

CPUHI_IOUT_R

CPUHYS

1

R5552

0

5% 1/20W MF 0201

2

3

4

NOSTUFF

1

C5552

0.1UF

10%

6.3V

2

CERM-X5R 0201

CPUHI_COMP_FB

CPUHYS

U5551

5

MAX9119EXK-T SC70-5

1

CRITICAL

2

CPUHYS

U5552

DMN32D2LFB4

DFN1006H4-3

CPUHI_COMP_OUT

SMC_CPUHI_COMP_ALERT_L

SYM_VER_2

1

NOSTUFF

C5553

0.22UF

1 2

20%

6.3V X5R

0201

R5553

255K

1 2

1%

1/20W

MF

201

CPUHYS

3

D

SG

2

OUT

50

B

RB521ZS-30

K

1.8V Current Sense (I18C)

CPUHI_IOUT

IN

52

Gain: 200x, EDP: 0.7 A Rsense: 0.025 (R8024) or Rsense SHORT Vsense: 17.5 mV, Range: 0.6 A SMC ADC: 16

LOADISNS

PLACE_NEAR=U5700.2:5MM

PP3V3_S4SW_SNS

52 53 54 55 57 101

PLACE_NEAR=R8024.3:5MM

76

IN

ISNS_1V8_SUS_P

ISNS_1V8_SUS_N

PLACE_NEAR=R8024.4:5MM

6

V+

U5590

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

LOADISNS

BYPASS=U5590.6::5MM

1

C5590

0.1UF

10%

6.3V

2

CERM-X5R 0201

P1V8SUS_IOUT

1

R5595

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5590.10:5MM

LOADISNS

PLACE_NEAR=U5700.23:5MM

R5599

453K

1 2

1%

1/20W

MF

201

EADC1_P1V8SUS_ISENSE

1

C5599

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5700.23:5MM

LOADISNS

GND_EADC1_COM

OUT

55

55 54 53 52

R5539

453K

1 2

1%

1/20W

MF

201

EADC1_PP3V3S4_WLAN_ISENSE

1

C5539

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5700.2:5MM

LOADISNS

GND_EADC1_COM

55 54 53 52

OUT

55

BOM_COST_GROUP=SENSORS

PAGE TITLE

Power Sensors: Load Side

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=04/03/2016SYNC_MASTER=J79_JACK

DRAWING NUMBER SIZE

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

55 OF 145

SHEET

53 OF 119

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

T139 5V Current Sense (IF5C)

Gain: 200x, EDP: 0.004 A Rsense: 0.05 (R5630) or Rsense SHORT Vsense: 0.2 mV, Range: 0.25 A EADC1: CH6

101 106

101

PP5V_S0

PP5V_S0_T139

OMIT

R5630

0.005

0306-SHORT

1%

1/3W

MF

PLACE_NEAR=U5630.2:3:10MM

123

ISNS_PP5V_T139_P

ISNS_PP5V_T139_N

4

PLACE_NEAR=U5630.4:5:10MM

Thunderbolt TBT Current Left (IULC)

Gain: 200x. EDP: 0.5 A Rsense: 0.025 (R5640) or Rsense SHORT Vsense: 12.5 mV, Range: 0.5 A EADC1: CH7

101

PP3V3_S0

OMIT

R5640

0.005

1/3W

0306-SHORT

101

PP3V3_TBT_X_S0

PLACE_NEAR=U5640.2:3:10MM

123

1%

MF

ISNS_TBT_P

ISNS_TBT_N

4

PLACE_NEAR=U5640.4:5:10MM

52 53 54 55 57 101

LCD Panel Current Sense (ILDC)

Gain: 200x. EDP: 1 A RSENSE: 0.01 (R8520) or Rsense SHORT Vsense: 5 mV, Range: 1.25 A EADC2: CH0

PLACE_NEAR=R8520.3:5MM

ISNS_LCDPANEL_P

80

ISNS_LCDPANEL_N

IN

PLACE_NEAR=R8520.4:5MM

PP3V3_S4SW_SNS

52 53 54 55 57 101

PP3V3_S4SW_SNS

2

IN+

3

IN+

4

IN-

5

IN-

PP3V3_S0

101

INA210A

2

IN+

3

4 5

CRITICAL

IN+

LOADISNS

ININ-

6

V+

U5640

INA210A

UQFN

CRITICAL

LOADISNS

200x

GND

9

2 3

4 5

V+

U5630

UQFN

200x

GND

IN+ IN+

ININ-

6

OUT

REF

NC NC

9

10

OUT

8

REF

1

NC

7

NC

6

V+

U5620

INA210A

UQFN

CRITICAL

LOADISNS

200x

GND

9

LOADISNS

BYPASS=U5630.6::5MM

1

C5630

0.1UF

10%

6.3V

2

CERM-X5R 0201

10

8

1 7

ISNS_PP5V_T139_IOUT EADC1_PP5V_T139_ISENSE

1

R5635

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5630.10:5MM

LOADISNS

BYPASS=U5640.6::5MM

1

C5640

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_TBT_IOUT

1

R5645

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5640.10:5MM

LOADISNS

BYPASS=U5620.6::5MM

1

C5620

0.1UF

10%

6.3V

2

CERM-X5R 0201

10

OUT

8

REF

1

NC NC

NC

7

NC

LOADISNS

PLACE_NEAR=U5700.4:5MM

R5639

453K

1 2

1/20W

LOADISNS

PLACE_NEAR=U5700.5:5MM

R5649

453K

1 2

1%

1/20W

MF

201

1

R5625

51K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5620.10:5MM

1% MF

201

1

C5639

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5700.4:5MM

LOADISNS

GND_EADC1_COM

EADC1_TBT_ISENSE

1

C5649

0.22UF

20%

6.3V

2

X5R 0201

LOADISNS

PLACE_NEAR=U5700.5:5MM

GND_EADC1_COM

LOADISNS

PLACE_NEAR=U5710.22:5MM

R5629

453K

1 2

1%

1/20W

MF

201

EADC2_LCDPANEL_ISENSEISNS_LCDPANEL_IOUT

1

C5629

0.22UF

20%

6.3V

2

X5R 0201

LOADISNS

PLACE_NEAR=U5710.22:5MM

OUT

55

OUT

CPU High Side (IC0R) Peak Detection Support

R5660

0

PP3V3_S0

56 101 106

55

CKPLUS_WAIVE=NdifPr_badTerm CKPLUS_WAIVE=NdifPr_badTerm

PLACE_NEAR=R5400.3:10MM

54 52

55 54 53 52

54 52

IN

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

PLACE_NEAR=R5400.4:10MM

CKPLUS_WAIVE=NdifPr_badTerm CKPLUS_WAIVE=NdifPr_badTerm

1 2

LOADISNS

2 3

4 5

5%

1/20W

MF

201

U5660

INA210A

IN+

CRITICAL

IN+

LOADISNS

ININ-

200x

6

V+

UQFN

GND

9

OUT

REF

NC NC

PP3V3_S0_CPUTHMSNS_R

1

C5660

0.1UF

10%

6.3V

2

CERM-X5R 0201

BYPASS=U5660.6::5MM

LOADISNS

10

8

1 7

ISNS_CPUHIGAIN_OUT

1

R5664

NC NC

15K

5% 1/20W MF 201

2

LOADISNS

PLACE_NEAR=U5660.10:5MM

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

R5665

0

1 2

5%

1/20W

MF

LOADISNS

0201

NO_XNET_CONNECTION=1

XW5660

SM

12

ISNS_CPUHIGAIN_OUT_R

1

C5665

0.22UF

20%

6.3V

2

X5R 0201

NOSTUFF

R5666

0

ISNS_CPUHIGAIN_R_P

PLACE_NEAR=U5660.10:10MM

1

R5662

1K

1% 1/20W MF 201

2

LOADISNS

54 52

IN

ISNS_HS_COMPUTING_P

PLACE_NEAR=U5660.10:10MM

NO_XNET_CONNECTION=1

ISNS_CPUHIGAIN_R_N

PLACE_NEAR=U5660.10:10MM

1

R5661

16K

1% 1/20W MF 201

2

LOADISNS

NO_XNET_CONNECTION=1

54 52

IN

ISNS_HS_COMPUTING_N

PLACE_NEAR=U5660.10:10MM

NO_XNET_CONNECTION=1

In battery discharge scenario negative voltage will be present on IN+/- pins with INA output voltage decreasing from 3.3V with increasing discharge current.

SENSE+ pins of EMC1704 sink 10-20uA current. This deviation has been designed in our Peak Detection circuit. With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV

1 2

5%

1/20W

MF

0201

NOSTUFF

R5668

0

1 2

5%

1/20W

MF

0201

ISNS_CPUHIGAIN_P

R5667

0

1 2

5%

1/20W

MF

0201

ISNS_CPUHIGAIN_N

R5669

0

1 2

5%

1/20W

MF

0201

OUT

56

D

With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV

Battery Discrete Current Sense (IB0L)

Gain: 2940x. EDP: 8 A Rsense: 0.003 (R501//R502) Vsense: 24 mV, Range: 0.28 A EADC2: CH5

104 65

BMON_IOUT

LOADISNS

1

R5675

20K

5% 1/20W MF 201

2

Thunderbolt TBT Current Right (IURC)

55 54 53 52

55 80

OUTIN

Gain: 200x. EDP: 0.5 A Rsense: 0.025 (R5670) or Rsense SHORT Vsense: 12.5 mV, Range: 0.5 A EADC1: CH2

101

PP3V3_S0

PP3V3_TBT_T_S0

OMIT

R5670

0.005

0306-SHORT

1%

1/3W

MF

PLACE_NEAR=U5670.2:3:10MM

123

4

PLACE_NEAR=U5670.4:5:10MM

PP3V3_S4SW_SNS

52 53 54 55 57 101

ISNS_TBT_T_P

ISNS_TBT_T_N

LOADISNS

BYPASS=U5670.6::5MM

1

C5670

6

V+

U5670

0.1UF

10%

6.3V

2

CERM-X5R 0201

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

ISNS_TBT_T_IOUT EADC1_TBT_T_ISENSE

1

R5676

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5670.10:5MM

1 2

LOADISNS

PLACE_NEAR=U5710.6:5MM

R5679

453K

1 2

1%

1/20W

MF

201

LOADISNS

PLACE_NEAR=U5700.24:5MM

EADC2_BMON_DISCRETE_ISENSE

R56A9

453K

1%

1/20W

MF

201

1

C56A9

0.22UF

20%

6.3V

2

X5R 0201

LOADISNS

PLACE_NEAR=U5700.24:5MM

GND_EADC1_COM

1

C5679

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5710.6:5MM

LOADISNS

GND_EADC2_COM

OUT

55

OUT

C

55 54

55 54 53 52

B

A

Trackpad 3V Current Sense (IT3C)

Gain: 200x, EDP: 0.2 A Rsense: 0.05 (R5650) or Rsense SHORT Vsense: 10 mV, Range: 0.25 A EADC2: CH1

101

PP3V3_S4

NO_XNET_CONNECTION=1

PP3V3_S4_TPAD

R5650

0.005

0306-SHORT

OMIT

1%

1/3W

MF

PLACE_NEAR=U5650.2:3:10MM

123

ISNS_PP3V3_TPAD_P ISNS_PP3V3_TPAD_IOUT

ISNS_PP3V3_TPAD_N

4

PLACE_NEAR=U5650.4:5:10MM

Camera Current Sense (ICMC)

Gain: 200x. EDP: 0.82 A Rsense: 0.015 (R5610) or XW5610 Vsense: 12.3 mV, Range: 0.83 A EADC2: CH2

101

PP3V3_S4

NO_XNET_CONNECTION=1

PP3V3_S4_SOC_PMU

OMIT

R5610

0.005

0306-SHORT

1%

1/3W

MF

PLACE_NEAR=U5610.2:3:10MM

123

4

PLACE_NEAR=U5610.4:5:10MM

52 53 54 55 57 101

ISNS_CAMERA_P

ISNS_CAMERA_N

PP3V3_S4SW_SNS

52 53 54 55 57 101

PP3V3_S4SW_SNS

2 3

4 5

2

IN+

3

4 5

CRITICAL

IN+

LOADISNS

ININ-

U5610

INA210A

IN+

CRITICAL

IN+

LOADISNS

ININ-

200x

U5650

INA210A

6

V+

UQFN

GND

9

6

V+

UQFN

OUT

REF

200x

GND

9

OUT

REF

NC NC

10

8

1 7

LOADISNS

BYPASS=U5650.6::5MM

1

C5650

0.1UF

10%

6.3V

2

CERM-X5R 0201

10

8

1 7

1

2

1

R5655

NC NC

LOADISNS

BYPASS=U5610.6::5MM

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5650.10:5MM

C5610

0.1UF

10%

6.3V CERM-X5R 0201

ISNS_CAMERA_IOUT

1

R5615

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5610.10:5MM

GND_EADC2_COM

LOADISNS

PLACE_NEAR=U5710.23:5MM

R5659

453K

1 2

1%

1/20W

MF

201

EADC2_PP3V3_TPAD_ISENSE

1

C5659

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5710.23:5MM

LOADISNS

GND_EADC2_COM

LOADISNS

PLACE_NEAR=U5710.24:5MM

R5619

453K

1 2

1%

1/20W

MF

201

EADC2_CAMERA_ISENSE

1

C5619

0.22UF

20%

6.3V

2

X5R 0201

LOADISNS

PLACE_NEAR=U5710.24:5MM

GND_EADC2_COM

OUT

55 54

55

OUT

55 54

55

2117S0008

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

C5608, C5699

CPU GT Voltage Sense (VCGC)

SMC ADC: 21

PPVCCGT_S0_CPU

8 100

XW5600

SM

1 2

PLACE_NEAR=R7410.2:5 MM

CPUGTVSENSE_IN

PLACE_NEAR=U5000.A7:5MM

R5609

4.53K

1 2

1%

1/20W

MF

201

SMC_CPUGT_VSENSE

1

C5609

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.A7:5MM

GND_SMC_AVSS

CPU Core Voltage Sense (VCAC)

SMC ADC: 20

PPVCC_S0_CPU

8 100 104

CPU Core IMON Current Sense (ICAM)

Gain: 1 A / 34.223 mV, Range: 29 A. SMC ADC: 22

With R7150 (Ri) set to 226 Ohm, R7210 (Rsen) set to 0.75 mOhm, R7160 set to 82.5 kOhm, Num Phases (N) is 2, and Io (ICCmax) is 29A, then 1A of Io gives 34.223mV at the Vimon.

XW5680

SM

1 2

PLACE_NEAR=R7210.2:5 MM

67

CPUVSENSE_IN

PLACE_NEAR=U5000.B7:5MM

IMON_B_CPUCORE SMC_CPU_IMON_ISENSE

PLACE_NEAR=U5000.B8:5MM

R5689

4.53K

1 2

1%

1/20W

MF

201

LOADISNS

R5699

0

1 2

5%

1/20W

MF

0201

SMC_CPU_VSENSE

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

OUT

1

C5689

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.B7:5MM

GND_SMC_AVSS

1

C5699

0.22UF

20%

2

6.3V X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.B8:5MM

GND_SMC_AVSS

BOM_COST_GROUP=SENSORS

50

LOADRC:NO

CPU GT IMON Current Sense (ICGM)

Gain: 1 A / 17.963 mV, Range: 64 A. SMC ADC: 23

55 54 53 52 50 49 48

50

OUT

50

IMON_A_CPUGT

67

PLACE_NEAR=U5000.A8:5MM

With R7154 (Ri) set to 294 Ohm, R7410 (Rsen) set to 0.75 mOhm, R7194 set to 84.5 kOhm, Num Phases (N) is 3, and Io (ICCmax) is 64A, then 1A of Io gives 17.963mV at the Vimon.

55 54 53 52 50 49 48

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

55 54 53 52 50 49 48

LOADISNS

R5608

0

1 2

5%

1/20W

MF

0201

SMC_CPUGT_IMON_ISENSE

1

C5608

0.22UF

20%

2

6.3V X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.A8:5MM

GND_SMC_AVSS

Power Sensors: Extended

Apple Inc.

R

50

OUT

55 54 53 52 50 49 48

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

56 OF 145

SHEET

54 OF 119

B

A

SYNC_DATE=01/08/2016SYNC_MASTER=J79_JACK

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

NAND Current Sense (IHNC)

LOADISNS

PLACE_NEAR=U5000.B1:5MM

R5789

4.53K

ISNS_SSDNAND_IOUT ISNS_PICCOLO_IOUT

57 57

1 2

1%

1/20W

MF

201

SMC_SSDNAND_ISENSE

1

C5789

0.22UF

20%

6.3V

2

X5R 0201

OUT

PLACE_NEAR=U5000.B1:5MM

LOADRC:YES

GND_SMC_AVSS GND_SMC_AVSS

PCH PrimeCore Current Sense (ISCC)

Gain: 200x, EDP: 2.574 A Rsense: 0.005 (R8054) Vsense: 12.87 mV, Range: 3 A SMC ADC: 15

PLACE_NEAR=R8054.4:5MM

76

ISNS_PCHPRIMCORE_P

IN OUT

ISNS_PCHPRIMCORE_N

IN

PLACE_NEAR=R8054.3:5MM

PP3V3_S4SW_SNS

52 53 54 55 57 101

6

V+

U5760

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

KB backlite Current Sense (IKBC)

Gain: 200x, EDP: 300m A Rsense: 0.035 (R5730) Vsense: 10.5 mV, Range: 0.36 A EADC2: CH3

101

PP5V_S0

PP5V_S0_KBD

2

2 LOADRC:NO117S0008

2117S0008 LOADRC:NO

OMIT

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

2 LOADRC:NO117S0008

R5730

0.005

1%

1/3W

0306-SHORT

MF

PLACE_NEAR=U5730.2:3:10MM

123

ISNS_KBBLT_P

ISNS_KBBLT_N

4

PLACE_NEAR=U5730.4:5:10MM

PP3V3_S4SW_SNS

52 53 54 55 57 101

C5769,C5778

C5749,C5779

C5729,C5799

C5709,C5789RES,MTL FLIM,100K,1/16W,0201,SMD,LF

2

IN+

3

4 5

CRITICAL

IN+

LOADISNS

ININ-

PCH PrimeCore Voltage Sense (VSCC)

PP5V_S4SW_ISNS

51 55 101

BYPASS=U5700.12::5MM

52

53

54

53

54

54 53 52

EADC1_LCDBKLT_ISENSE EADC1_P1V8SUS_ISENSE EADC1_TBT_T_ISENSE EADC1_PP3V3S0_T139_ISENSE EADC1_PP3V3S4_WLAN_ISENSE EADC1_BT_ISENSE EADC1_PP5V_T139_ISENSE EADC1_TBT_ISENSE

GND_EADC1_COM

EADC2: CH7

PPVCCPRIMCORE_SUS_PCH

8 12 100

PLACE_NEAR=U0500.V21:5MM

LOADISNS

EADC1

R5700

10

1 2

5%

1/20W

MF

201

BYPASS=U5700.12::5MM

PLACE_NEAR=U5700.6:1MM

PLACE_NEAR=U5700.25:1MM

PP5V_EADC1_AVDD

1

C5702

4.7UF

20% 10V

2

X5R 0402

LOADISNS

XW5700

SM

12

22 23 24

1

2

CH0 CH1 CH2

1

CH3

2

CH4

3

CH5

4

CH6

5

CH7

6

COM

C5701

0.1UF

10% 10V X5R-CERM 0201

LOADISNS

BYPASS=U5700.12::3MM

12

CRITICAL

LOADISNS

GND

9

1011181920

AVDD DVDD

LTC2309

XW5764

SM

12

VSNS_PCHPRIMCORE

PLACE_NEAR=U5710.5:5MM

1

2

13

21

U5700

14

QFN

THRM

BYPASS=U5700.8::3MM

AD0

15

AD1

17

SDA

16

SCL

VREF

REFCOMP

PAD

25

(Write: 0x10 Read: 0x11)

7

8

PICCOLO Current Sense (IHCC)

LOADISNS

PLACE_NEAR=U5000.C2:5MM

R5709

4.53K

50

55 54 53 52 50 49 48 55 54 53 52 50 49 48

LOADISNS

BYPASS=U5760.6::5MM

1

C5760

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_PCHCORE_IOUT

1

R5765

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5760.10:5MM

LOADISNS

OUT

REF

NC NC

10

8

1 7

1 2

1%

1/20W

MF

201

BYPASS=U5730.6::5MM

1

C5730

6

V+

U5730

INA210A

UQFN

200x

GND

9

OUT

REF

NC NC

10

8

1 7

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_KBBLT_IOUT

1

R5735

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

LOADISNS

PLACE_NEAR=U5710.1:5MM

R5739

453K

1 2

1/20W

PLACE_NEAR=U5730.10:5MM

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

LOADRC:NO117S0008

LOADISNS

T151 Current Sense (IIDC)

EADC2: CH4

ISNS_T151_IOUT

57

R5764

453K

1 2

C5703

0.1UF

10% 10V X5R-CERM 0201

LOADISNS

BYPASS=U5700.21::3MM

SMBUS_2_SDA_Q SMBUS_2_SCL_Q

PP2V5_ADC1_VREF

ADC1_REFCOMP

1

C5705

0.1UF

10%

6.3V

2

CERM-X5R 0201

LOADISNS

1

C5706

10UF

20% 10V

2

X5R-CERM 0402-10

LOADISNS

BYPASS=U5700.8::5MM

1%

1/20W

MF

201

51

1

2

EADC2_PCHPRIMCORE_VSENSE

PLACE_NEAR=U5710.5:5MM

1

C5764

0.22UF

20%

6.3V

2

X5R 0201

LOADISNS

GND_EADC2_COM

PP5V_S4SW_ISNS

51 55 101

BYPASS=U5710.12::=5MM

54

55

C5700

2.2UF

20%

6.3V X5R-CERM 0201

LOADISNS

54

55

GND_EADC2_COM

55 54

BYPASS=U5700.7::5MM

SMC_PICCOLO_ISENSE

1

C5709

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.C2:5MM

LOADRC:YES

LOADISNS

PLACE_NEAR=U5000.A5:5MM

R5769

4.53K

1 2

1%

1/20W

MF

201

SMC_PCHPRIMCORE_ISENSE

1

C5769

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.A5:5MM

LOADRC:YES

GND_SMC_AVSS

EADC2_KBBLT_ISENSE

1% MF

201

1

C5739

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5710.1:5MM

LOADISNS

GND_EADC2_COM

LOADISNS

PLACE_NEAR=U5710.2:5MM

R5759

453K

1 2

1/20W

55

55 54

LOADISNS

R5710

10

1 2

5%

1/20W

MF

201

BYPASS=U5710.12::5MM

EADC2_LCDPANEL_ISENSE EADC2_PP3V3_TPAD_ISENSE EADC2_CAMERA_ISENSE EADC2_KBBLT_ISENSE EADC2_T151_ISENSE

EADC2_BMON_DISCRETE_ISENSE

EADC2_PCHPRIMCORE_VSENSE

PLACE_NEAR=U5710.6:1MM

50

OUT

55 54 53 52 50 49 48

55

55 54

EADC2_T151_ISENSE

1% MF

201

1

C5759

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5710.2:5MM

LOADISNS

GND_EADC2_COM

EADC2

PP5V_EADC2_AVDD

1

C5712

4.7UF

20% 10V

2

X5R 0402

LOADISNS

XW5710

SM

PLACE_NEAR=U5710.25:1MM

1

C5711

0.1UF

10% 10V

2

X5R-CERM 0201

LOADISNS

BYPASS=U5710.12::3MM

22

CH0

23

CH1

24

CH2

1

CH3

2

CH4

3

CH5

4

NC

12

CH6

5

CH7

6

COM

CPU GT+GTX Current Sense (ICGC)

Gain: 188.49x, EDP: 64 A Rsense: 3x of 0.00075 (R7410, R7420, R7430), Rsum: 0.00025 Vsense: 16 mV, Range: 63.66 A

70

SMC ADC: 5

IN

CPUGT_ISNS1_P

PLACE_NEAR=R7410.4:5MM

LOADISNS

R5745

4.42K

1 2

0.1%

1/20W

MF

0201

R5746

70

IN

PLACE_NEAR=R7420.4:5MM

LOADISNS

1 2

0.1%

1/20W

MF

0201

CPUGT_ISNS_R_PCPUGT_ISNS2_P

4.42K

R5747

4.42K

70

IN

CPUGT_ISNS3_P

PLACE_NEAR=R7430.4:5MM

LOADISNS

1 2

0.1%

1/20W

MF

0201

R5748

4.42K

70

IN

CPUGT_ISNS1_N

PLACE_NEAR=R7410.3:5MM

LOADISNS

1 2

0.1%

1/20W

MF

0201

R5757

4.42K

1 2

0.1%

1/20W

MF

0201

CPUGT_ISNS_R_N

50

70

IN

CPUGT_ISNS2_N

PLACE_NEAR=R7420.3:5MM

LOADISNS

R5758

4.42K

70

IN

CPUGT_ISNS3_N

PLACE_NEAR=R7430.3:5MM

LOADISNS

1 2

0.1%

1/20W

MF

0201

CPU SA Current Sense (ICSC)

Gain: 200x, EDP: 5.1 A Rsense: 0.002 (R7270) Vsense: 10.2 mV, Range: 7.5 A SMC ADC: 19

LOADISNS

R5760

1 2

1/20W

0201

0

5% MF

LOADISNS

R5761

1 2

1/20W

0201

0

5% MF

PLACE_NEAR=R5760.2:5MM

CPUSA_ISNS_R_P

CPUSA_ISNS_R_N

PLACE_NEAR=R5761.2:5MM

68

PLACE_NEAR=R7270.3:5MM

CPUSA_ISNS_P

IN

CPUSA_ISNS_N

PLACE_NEAR=R7270.4:5MM

LPDDR 1.8V Current Sense (IM1C)

Gain: 200x, EDP: 0.555 A Rsense: 0.025 (R5720) or Rsense SHORT Vsense: 13.875 mV, Range: 0.6 A SMC ADC: 16

PP1V8_S3

PP1V8_S3_MEM

1

C5713

0.1UF

10% 10V

2

X5R-CERM 0201

LOADISNS

BYPASS=U5710.21::3MM

14

AD0

15

AD1

17

SDA

16

SCL

VREF

7

8

PP2V5_ADC2_VREF

ADC2_REFCOMP

1

C5715

0.1UF

10%

6.3V

2

CERM-X5R 0201

LOADISNS

OMIT

R5720

0306-SHORT

EADC2_AD0

R5712

100K

1 2

5%

1/20W

MF

201

SMBUS_2_SDA_Q SMBUS_2_SCL_Q

PP5V_S4SW_ISNS

NOSTUFF

1

C5716

10UF

20% 10V

2

X5R-CERM 0402-10

LOADISNS

BYPASS=U5710.10::5MM

(Write: 0x12 Read: 0x13)

PLACE_NEAR=U5720.2:3:10MM

0.005

1%

1/3W

MF

123

4

ISNS_LPDDR_P

ISNS_LPDDR_N

PLACE_NEAR=U5720.4:5:10MM

51

1

C5710

2.2UF

20%

6.3V

2

X5R-CERM 0201

LOADISNS

BYPASS=U5710.7::5MM

55

55 54

12

13

AVDD DVDD

U5710

LTC2309

CRITICAL

LOADISNS

GND

9

1011181920

100

21

QFN

REFCOMP

THRM

PAD

25

BYPASS=U5710.10::3MM

LOADISNS

R5742

2.32K

1 2

1%

1/20W

MF

201

CPUGT_ISNS_P

R5743

2.32K

1 2

1%

1/20W

MF

201

LOADISNS

CPUGT_ISNS_N

1

R5744

715K

0.1% 1/20W MF 0201

2

LOADISNS

NO_XNET_CONNECTION=1

CPU SA Voltage Sense (VCSC)

SMC ADC: 17

PPVCCSA_S0_CPU

8 100

PP3V3_S4SW_SNS

52 53 54 55 57 101

PP3V3_S4SW_SNS

52 53 54 55 57 101

PP3V3_S4SW_SNS

52 53 54 55 57 101

PLACE_NEAR=R7718.3:5MM

73

51 55 101

ISNS_CPUEDRAM_P

ISNS_CPUEDRAM_N

IN

PLACE_NEAR=R7718.4:5MM

BYPASS=U5740.5::5MM

PP3V3_S0

101

LOADISNS

CRITICAL

U5740

5

ISL28133

1

3

V+

V-

SC70-5

4

2

R5741

715K

1 2

0.1%

1/20W

MF

0201

XW5778

SM

1 2

PLACE_NEAR=R7410.2:5 MM

LOADISNS

NO_XNET_CONNECTION=1

CPUSAVSENSE_IN

PLACE_NEAR=U5000.A7:5MM

LOADISNS

CPUGT_ISUM_IOUT

1

R5740

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5740.4:5MM

LOADISNS

1

C5740

0.1UF

10%

6.3V

2

CERM-X5R 0201

1 2

LOADISNS

R5778

4.53K

1 2

1%

1/20W

MF

201

LOADISNS

PLACE_NEAR=U5000.B4:5MM

R5749

4.53K

1%

1/20W

MF

201

SMC_CPUSA_VSENSE

SMC_CPUGT_ISENSE

1

C5749

0.22UF

20%

6.3V

2

X5R 0201

LOADRC:YES

PLACE_NEAR=U5000.B4:5MM

GND_SMC_AVSS

LOADRC:YES

1

C5778

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

OUT

50

OUT

PLACE_NEAR=U5000.A7:5MM

50

D

55 54 53 52 50 49 48

BYPASS=U5770.6::5MM

1

C5770

6

V+

U5770

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

0.1UF

10%

6.3V

2

CERM-X5R 0201

ISNS_CPUSA_IOUT

1

R5775

NC NC

20K

5% MF

201

2

NOSTUFF

PLACE_NEAR=U5770.10:5MM

LOADISNS

PLACE_NEAR=U5000.A5:5MM

R5779

4.53K

1 2

1%

1/20W

MF

201

SMC_CPUSA_ISENSE

1

C5779

0.22UF

20%

6.3V

21/20W

X5R 0201

PLACE_NEAR=U5000.A5:5MM

LOADRC:YES

GND_SMC_AVSS

C

50

OUTIN

55 54 53 52 50 49 48

BYPASS=U5720.6::5MM

1

C5720

6

V+

U5720

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

0.1UF

10%

6.3V

2

CERM-X5R 0201

LOADISNS

PLACE_NEAR=U5000.H1:5MM

R5729

4.53K

ISNS_LPDDR_IOUT SMC_DDR1V8_ISENSE

1

R5725

NC NC

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5720.10:5MM

1 2

1%

1/20W

MF

201

1

C5729

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.H1:5MM

LOADRC:YES

GND_SMC_AVSS

OUT

50

B

55 54 53 52 50 49 48

CPU EDRAM Current Sense (ICEC)

BYPASS=U5790.6::5MM

6

V+

U5790

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

BOM_COST_GROUP=SENSORS

OUT

REF

NC NC

10

8

1 7

LOADISNS

1

C5790

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

NC NC

2

R5795

20K

5%

1/20W

MF

201

NOSTUFF

PLACE_NEAR=U5790.10:5MM

PAGE TITLE

Power Sensors: Extended 2

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

Gain: 200x, EDP: 4.5 A Rsense: 0.003 (R7718)

Vsense: 13.5 mV, Range: 5 A SMC ADC: 10

LOADISNS

PLACE_NEAR=U5000.A5:5MM

R5799

4.53K

1 2

1%

1/20W

MF

201

Apple Inc.

SMC_CPUEDRAM_ISENSEISNS_CPUEDRAM_IOUT

1

C5799

0.22UF

20%

6.3V

2

X5R 0201

PLACE_NEAR=U5000.A5:5MM

LOADRC:YES

GND_SMC_AVSS

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

OUTIN

051-00515

9.0.0

dvt-fab09-0

57 OF 145

55 OF 119

55 54 53 52 50 49 48

50

D

A

SYNC_DATE=05/10/2016SYNC_MASTER=J79_JACK

8 7 5 4 2 1

36

D

Thermal Sensor A: Thunderbolt Die, Airflow Left

I2C Write: 0xD8, I2C Read: 0xD9

Thermal Diode: TBT Die (TBT1)

Placement Note: The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AC22.

26

27

BI

PP3V3_S0

56 101

TBTTHMSNS_D1_P

TBTTHMSNS_D1_N

TBTTHMSNS_D1_P

MAKE_BASE=TRUE

TBTTHMSNS_D1_N

MAKE_BASE=TRUE

Note: Use GND pin AC22 on U2800 for N leg.

R5850

0

1 2

5%

1/20W

MF

201

NO_XNET_CONNECTION=1 PLACE_NEAR=U5850.2:5MM

C5851

2200PF

X7R-CERM

PLACE_NEAR=U5850.3:5MM

TBTTHRM_SNS

PP3V3_S0_TBTTHMSNS_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

10% 10V

2

0201

2

D+

3

D-

5

A0

10

A1 THERM*

CRITICAL

1

V+

U5850

TMP461

QFN

ALERT*/THERM2*

GND

6

TBTTHRM_SNS

SCL

SDA

BYPASS=U5850.1::5MM

1

C5850

0.1UF

10%

6.3V

2

CERM-X5R 0201

TBTTHRM_SNS

TBTTHRM_THRM:PU

9

SMBUS_SMC_3_SCL

8

SMBUS_SMC_3_SDA

7

TBTTHMSNS_ALERT_L

4

TBTTHMSNS_THM_L

345678

2 1

D

1

R5851

100K

5% 1/20W MF 201

2

1

R5852

100K

5% 1/20W MF 201

2

TBTTHRM_ALRT:PU

51

BI

51

BI

50

OUT

50

OUT

U5850 I2C Address:

TMP461 is 0x90/0x91.

C

Thermal Sensor C: Thunderbolt Die, Air Flow Right

I2C Write: 0xB8, I2C Read: 0xB9

Thermal Diode: TBT Die (TBT2)

Placement Note: The P leg connects to THERMDA pin of the TBT chip, the N leg connect to pin AC22.

92

93

BI

Placement Note: Place U5850 on the BOTTOM side, on the left portion of the board, 1" to the right of USB connector.

R5860

0

PP3V3_S0

56 101

RIO_TBTTHMSNS_D1_P

RIO_TBTTHMSNS_D1_N SMBUS_SMC_3_SDA

RIO_TBTTHMSNS_D1_P

MAKE_BASE=TRUE

RIO_TBTTHMSNS_D1_N

MAKE_BASE=TRUE

NO_XNET_CONNECTION=1 PLACE_NEAR=U5860.2:5MM

PLACE_NEAR=U5860.3:5MM

1 2

5%

1/20W

MF

201

C5861

2200PF

10% 10V

X7R-CERM

0201

TBTTHRM_SNS

PP3V3_S0_TBTTHMSNS_T_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

U5860

2

D+

3

D-

5

A0

10

NC

A1 THERM*

TMP461

QFN

CRITICAL

1

V+

SCL

SDA

ALERT*/THERM2*

9

SMBUS_SMC_3_SCL

8

7

4

Note: Use GND pin AC22 on UB000 for N leg.

GND

6

TBTTHRM_SNS

U5860 I2C Address:

TMP461 is 0x96/0x97.

BYPASS=U5860.1::5MM

1

C5860

0.1UF

10%

6.3V

2

CERM-X5R 0201

TBTTHRM_SNS

TBTTHRM_THRM:PU

TBTTHMSNS_ALERT_T_L

TBTTHMSNS_THM_T_L

1

R5861

100K

5% 1/20W MF 201

2

51

BI

51

BI

1

R5862

100K

5% 1/20W MF 201

2

TBTTHRM_ALRT:PU

51

BI

51

OUT

BI

50

101

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

PP3V3_S0

PLACE_NEAR=U3730::10MM

X100 PROXIMITY

AP_TEMP

6

SDA

1

SCL ALERT

5

V+

U5820

HPA00330AI

SOT563

ADD0

4

3

1

C5820

0.1UF

10%

6.3V

2

CERM-X5R 0201

WIFI_THMSNS_A0

NC

AP_TEMP

1

R5820

10K

5% 1/20W MF 201

2

C

B

A

Thermal Sensor B & CPU High Peak Detection: CPU Proximity, Memory Proximity, Fin Stack Left, Fin Stack Right

I2C Write: 0xB8, I2C Read: 0xB9

R5870

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=U5870.6:5MM

C5871

2200PF

X7R-CERM

PLACE_NEAR=U5870.7:5MM

10% 10V

0201

10% 10V

0201

1

2

1

2

C5872

2200PF

X7R-CERM

C5873

2200PF

X7R-CERM

Thermal Diode: Fin Stack Left (Th2H)

Placement Note: Place Q5871, Airflow thermal indicator, above the X100, on the TOP side.

Thermal Diode: CPU Proximity (TC0P)

Placement Note: Place Q5873 under the CPU, on the BOTTOM side.

Thermal Diode: Memory Proximity (TM0P)

Placement Note: Place Q5872 between two rows of Memory devices, between channel A and B, on the BOTTOM side.

PP3V3_S0

54 101 106

Q5871

BC846BLP

DFN1006H4-3

Q5873

BC846BLP

DFN1006H4-3

Q5872

BC846BLP

DFN1006H4-3

CPUTHMSNS_D1_P

3

CRITICAL

2

CPUTHMSNS_D1_N

CPUTHMSNS_D2_P

3

CRITICAL

2

CPUTHMSNS_D2_N

CPUTHMSNS_D3_P

3

2

CRITICAL

CPUTHMSNS_D3_N

NO_XNET_CONNECTION=1

1

NO_XNET_CONNECTION=1

PLACE_NEAR=U5870.8:5MM

1

PLACE_NEAR=U5870.9:5MM

NO_XNET_CONNECTION=1

1

PLACE_NEAR=U5870.10:5MM

PLACE_NEAR=U5870.11:5MM

54

IN

ISNS_CPUHIGAIN_P ISNS_CPUHIGAIN_N

Placement Note: Place U5860 on the BOTTOM side, on the right portion of the board, 1" to the left of USB connector.

PP3V3_S0_CPUTHMSNS_TI_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

10% 10V

0201

2

6 7

8 9

10 11

1 2

TMP513AISAR

DXP1 DXN1

DXP2

DXN2

DXP3 DXN3

VIN+ VIN-

Thermal Sensor: Fin Stack Right (Th1H)

Placement Note: Place U5870 at corner near right Fan, on the TOP side.

16

CRITICAL

V+

U5870

QFN

FILTER C

14

THRM

PAD

17

GND

A0

ALERT

SDA SCL

GPIO

BYPASS=U5870.16::5MM

1

C5870

0.1UF

10%

6.3V

2

CERM-X5R 0201

15

CPUTHMSNS_FILTER

5

CPUTHMSNS_ADDR_SEL

13

CPUTHMSNS_ALERT_L

3

SMBUS_SMC_1_S0_SDA

4

SMBUS_SMC_1_S0_SCL

12

CPUTHMSNS_THM_L

1

R5873

10K

5% 1/20W MF 201

2

1

R5871

100K

1% 1/20W MF 201

2

1

R5872

100K

5% 1/20W MF 201

2

CPUTHRM_ALRT:PU

50

OUT

51

BI

51

BI

50

OUT

PLACE_NEAR=U5870.15:2.54MM

1

C5874

0.47UF

10%

6.3V

2

CERM-X5R 0201

BOM_COST_GROUP=SENSORS

CRITICAL

GND

2

WRITE ADDRESS: 0X92 READ ADDRESS: 0X93

Placement note:

PLACE U5820 ON BOTTOM NEAR X100

PAGE TITLE

Thermal Sensors

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=09/24/2015SYNC_MASTER=J79_JACK

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

58 OF 145

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B

A

8 7 5 4 2 1

36

EADC Current Sense (IADC)

Gain: 200x, EDP: 200m A Rsense: 0.050 (R5950) or Rsense SHORT Vsense: 10 mV, Range: 0.25 A

EADC2: CH7

345678

2 1

D

101

PP5V_S4SW

NO_XNET_CONNECTION=1

R5950

0.005

0306-SHORT

OMIT

1%

1/3W

MF

123

TP_ISNS_EADCP

TP_ISNS_EADCN

4

PP5V_S4SW_ISNS

NAND Current Sense (IHNC)

Gain: 200x, EDP: 4.25 A Rsense: 0.002 (R9430) Vsense: 8.5 mV, Range: 7.5 A SMC ADC: 14

PLACE_NEAR=R9430.4:5MM

ISNS_SSDNAND_N

89

ISNS_SSDNAND_P

89

ISNS_SSDNAND_N

MAKE_BASE=TRUE

ISNS_SSDNAND_P

MAKE_BASE=TRUE

PLACE_NEAR=R9430.3:5MM

PP3V3_S5

57 78 101

3

V+

U5910

5

IN-

4

IN+ REF

INA210

SC70

CRITICAL

LOADISNS

200x

GND

2

OUT

D

BYPASS=U5910.3::5MM

LOADISNS

1

C5910

0.1UF

10%

6.3V

2

CERM-X5R 0201

6

1

R5915

20K

5% 1/20W MF 201

2

ISNS_SSDNAND_IOUT

OUT

55

C

101

Piccolo Current Sense (IHCC)

Gain: 200x, EDP: 4.06 A Rsense: 0.003 (R5520)

PP3V3_S5

Vsense: 12.18 mV, Range: 5 A SMC ADC: 13

PP3V3_S5_SSD

NO_XNET_CONNECTION=1

OMIT

0306-SHORT

MF

1/3W

1%

0.005

R5920

123

PP3V3_S5_SSD_LB

PLACE_NEAR=U5920.4:10MM

4

ISNS_PICCOLO_N

ISNS_PICCOLO_P

PLACE_NEAR=U5920.5:10MM

57 78 101

3

V+

U5920

5

IN-

4

IN+ REF

INA210

SC70

CRITICAL

LOADISNS

200x

GND

2

OUT

NOSTUFF

PLACE_NEAR=U5910.6:5MM

C

LOADISNS

BYPASS=U5920.3::5MM

1

C5920

0.1UF

10%

6.3V

2

CERM-X5R 0201

6

1

R5925

20K

5% 1/20W MF 201

2

NOSTUFF

PLACE_NEAR=U5920.6:5MM

ISNS_PICCOLO_IOUT

OUT

55

B

101

PP3V3_S4

PP3V3_S4_MESA

SMC Current Sense (ISMC)

Gain: 391.67x, EDP: 0.2 A Rsense: 0.05 (R5940) or Rsense SHORT Vsense: 10 mV, Range: 0.21A EADC2: CH6

T151 Current Sense (IIDC)

Gain: 200x, EDP: 163.8m A Rsense: 0.050 (R5530) or Rsense SHORT

PP3V3_S4SW_SNS

Vsense: 819 mV, Range: 0.25 A EADC2: CH4

NO_XNET_CONNECTION=1

R5930

0.005

0306-SHORT

OMIT

1%

1/3W

MF

PLACE_NEAR=U5930.2:3:10MM

123

4

PLACE_NEAR=U5930.4:5:10MM

ISNS_T151_P

ISNS_T151_N

52 53 54 55 101

LOADISNS

B

6

V+

U5930

BYPASS=U5930.6::5MM

1

C5930

0.1UF

10%

6.3V

2

CERM-X5R 0201

INA210A

2

IN+

3

IN+

4

IN-

5

IN-

UQFN

CRITICAL

LOADISNS

200x

GND

9

OUT

REF

NC NC

10

8

1 7

NC NC

1

R5935

51K

5% 1/20W MF 201

2

NOSTUFF

ISNS_T151_IOUT

OUT

55

PLACE_NEAR=U5930.10:5MM

A

48 49 100

80 100

8 7 5 4 2 1

PP3V3_G3H_SMC_ISNS

0306-SHORT

PP3V3_G3H

NO_XNET_CONNECTION=1

OMIT

MF

1/3W

1%

0.005

R5940

123

TP_ISNS_PP3V3G3H_SMCN

4

SYNC_MASTER=J79_JACK SYNC_DATE=04/14/2016

PAGE TITLE

Power Sensors:Extended 3

DRAWING NUMBER SIZE

TP_ISNS_PP3V3G3H_SMCP

BOM_COST_GROUP=SENSORS

Apple Inc.

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36

051-00515

9.0.0

dvt-fab09-0

59 OF 145

57 OF 119

A

D

345678

2 1

D

FAN CONTROL

PP3V3_S0

58 101

PP3V3_S0

D

58 101

C

48

OUT

IN

SMC_FAN_0_TACH

R6001

100K

1/20W

201

SMC_FAN_0_CTL

5% MF

C

47K

5% MF

201

1

2

48

OUT

SMC_FAN_1_TACH

FAN_LT_TACH

R6051

100K

1/20W

201

FAN_LT_PWM FAN_RT_PWM

104 43 104 43

48

SMC_FAN_1_CTL

IN

1

5% MF

2

R6055

47K

1 2

5%

1/20W

MF

201

1

GS

2

Q6050

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

R6000

1/20W

R6005

47K

1 2

5%

1/20W

MF

201

1

GS

2

Q6000

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

D

3

R6050

47K

1/20W

5% MF

201

1

2

FAN_RT_TACH

104 43 104 43

B

FOR DEBUG FAN POWER

PP5V_S0

NOSTUFF

J6000

TH

1 2

43 101

B

A

998-0470

SYNC_MASTER=J79_JACK SYNC_DATE=08/21/2015

PAGE TITLE

Fans

DRAWING NUMBER SIZE

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=FAN

8 7 5 4 2 1

36

REVISION

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051-00515

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A

D

59

59 16

PP3V3_SUS

101

SPI_MLB_CS_L SPIROM_USE_MLB

U6101

74LVC1G99

2 3 5 6

SOT833

CRITICAL

B C D

8

VCC

GND

4

OE*

SPI ROM

Quad-IO Mode (Mode 0 & 3) supported. SPI Frequency: 50MHz for CPU, 20MHz for SMC.

BYPASS=U6101::3mm

1

C6101

0.1UF

10% 16V

2

X5R-CERM 0201

59 59 59

7

YA

1

SPI_MLBROM_CS_L

PLACE_NEAR=U6100.1:12MM

59

BYPASS=U6100::3mm

C6100

0.1UF

10% 16V

X5R-CERM

0201

SPI_MLB_CLK

SPI_MLB_IO2_WP_L SPI_MLB_IO3_HOLD_L

1

2

6

1

3

7

8

CRITICAL

VCC

U6100

W25Q64FVZPIG

64MBIT

GND

4

WSON

IO2

IO3

THRM_PAD

CLK

OMIT_TABLE

CS* WP*(IO2) HOLD*(IO3)

DI(IO0)

DO(IO1)

9

IO0

IO1

BYPASS=U6100::3mm

CRITICAL

1

C6102

1UF

20% 10V

2

X5R 0201

5

SPI_MLB_IO0_MOSI

2

SPI_MLB_IO1_MISO

59

104 80 66 50

345678

2 1

SPI+SWD SAM Connector

SAMCONN CRITICAL

J6100

DF40PC-12DP-0.4V-51

PP3V3_G3H

100

SPI_ALT_IO0_MOSI

59

SPI_ALT_IO1_MISO

59

SPI_ALT_IO2_WP_L

59

SPI_ALT_IO3_HOLD_L

59

OUT OUT

SMC_RESET_L

16

M-ST-SM

1314

12

34

56

78

910

1112

15

SPI_ALT_CLK SPI_ALT_CS_L

SPIROM_USE_MLB SMC_TMS SMC_TCK

(SWDIO) (SWCLK)

59

BI

D

59 16

49 48

C

NOTE: If HOLD* is asserted ROM will ignore SPI cycles in normal and Dual-IO modes.

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)

in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

SPI Bus Series Termination (Modified per PDG)

PLACE_NEAR=J6100.10:5MM

PLACE_NEAR=J6100.8:5MM

SAMCONN

1

R6133

0

5% 1/20W MF 0201

2

SAMCONN

1

R6132

0

5% 1/20W MF 0201

2

PLACE_NEAR=J6100.6:5MM

PLACE_NEAR=J6100.4:5MM

SAMCONN

1

R6128

0

5% 1/20W MF 0201

2

SAMCONN

1

R6127

0

5% 1/20W MF 0201

2

PLACE_NEAR=J6100.3:5MM

PLACE_NEAR=J6100.5:5MM

SAMCONN

1

R6126

0

5% 1/20W MF 0201

2

SAMCONN

1

R6125

0

5% 1/20W MF 0201

2

SPI_ALT_IO3_HOLD_L SPI_ALT_IO2_WP_L SPI_ALT_IO1_MISO SPI_ALT_IO0_MOSI SPI_ALT_CLK

SPI_ALT_CS_L

59

C

59

Sam Card ROM Slave

B

13

17 13

13

IN

BI

SPI_CS0_R_L

SPI_CLK_R SPI_CLK

PLACE_NEAR=U0500.AV2:50MM

SPI_MOSI_R

(SPI_IO<0>)

BI

SPI_MISO

PLACE_NEAR=U0500.AW3:50MM

(SPI_IO<1>)

BI

SPI_IO<2>

PLACE_NEAR=U0500.AW2:50MM

SPI_IO<3>

PLACE_NEAR=U0500.AU4:50MM

PLACE_NEAR=U0500.AU3:50MM

R6111

22

1 2

5%

1/20W

MF

201

PLACE_NEAR=U0500.AV3:50MM

R6113

22

1 2

5%

1/20W

R6118

22

1 2

5%

1/20W

MF

201

MF

201

R6119

22

1 2

5%

1/20W

MF

201

R6110

22

1 2

5%

1/20W

MF

201

R6112

22

1 2

5%

1/20W

MF

201

SPI_CS0_L

SPI_MOSI

SPI_MISO_R

SPI_IO2_R

SPI_IO3_R

R6121

22

1 2

5%

1/20W

MF

201

R6123

22

1 2

5%

1/20W

MF

201

R6131

22

1 2

5%

1/20W

MF

201

R6120

22

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6100.6:12MM

PLACE_NEAR=U6100.1:12MM

R6122

22

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6100.2:12MM

PLACE_NEAR=U6100.5:12MM

R6130

22

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6100.7:12MM

PLACE_NEAR=U6100.3:12MM

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_IO0_MOSI

SPI_MLB_IO1_MISO

SPI_MLB_IO2_WP_L

SPI_MLB_IO3_HOLD_L

59

B

59

SPI ROM SlaveCPU Master

59

A

SYNC_MASTER=J52_MLB

PAGE TITLE

SPI Debug Connector

DRAWING NUMBER SIZE

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=CPU & CHIPSET

8 7 5 4 2 1

36

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SHEET

SYNC_DATE=05/12/2015

051-00515

D

9.0.0

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59 OF 119

A

D

PLACE_NEAR=U6200:5MM

R6280

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6200:5MM

R6282

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6200:5MM

R6281

0

1 2

5%

1/20W

MF

201

1

C6281

27PF

5%

6.3V

2

NP0-C0G 0201

NOSTUFF

1

C6282

47PF

5% 25V

2

C0G 0201

345678

8409_ASP2_SCLK_RC

8409_ASP2_LRCLK_RC

8409_ASP2_SDOUT_RC

NOSTUFF

1

C6283

47PF

5% 25V

2

C0G 0201

R6210

33

1 2

5%

1/20W

MF

201

R6213

33

1 2

5%

1/20W

MF

201

R6211

33

1 2

5%

1/20W

MF

201

2 1

PLACE_NEAR=U6200:5MM

AUD_ASP2_SCLK

PLACE_NEAR=U6200:5MM

AUD_ASP2_LRCLK

AUD_ASP2_SDIN

PLACE_NEAR=U6200:5MM

AUD_ASP2_SDOUT

OUT

IN

61

D

61

AUDIO JACK CODEC

61

C

B

PCH AUDIO

3-MIC CONNECTOR

APN: 518S0818

J6200

FF14A-6C-R11DL-B-3H

F-RT-SM

7

1

2

3

4

5

6

8

PP1V8_S0

60 62 63 100 104

13

105 13

13

PP1V8_S0

HDA_BIT_CLK

IN

HDA_SYNC

IN

HDA_SDOUT

IN

HDA_SDIN0

OUT

HDA_RST_L

IN

104

DMIC1_DATA

104

DMIC1_CLK

60 62 63 100 104

104

DMIC2_DATA

104

DMIC2_CLK

U6200.B2:A1:3 MM

1

C6203

0.22UF

10% 10V

2

CERM 402

R6203

1 2

R6206

33

1 2

5%

1/20W

MF

201

R6208

33

1 2

5%

1/20W

MF

201

33

5%

1/20W

MF

201

R6205

1 2

5%

1/20W

MF

201

R6207

1 2

5%

1/20W

MF

201

U6200.E2:C3:3 MM

1

C6204

0.1UF

10% 25V

2

X5R 0201

PLACE_NEAR=U6200:5MM

8409_HDA_SDIN0_R

PLACE_NEAR=U6200:5MM

0

8409_DMIC1_DATA

PLACE_NEAR=U6200:5MM

8409_DMIC1_CLK_R

PLACE_NEAR=U6200:5MM

8409_DMIC2_DATA

PLACE_NEAR=U6200:5MM

8409_DMIC2_CLK_R

U6200.C4:C3:3 MM

1

C6201

0.1UF

10% 25V

2

X5R 0201

1

C6205

2.9PF

+/-0.05PF 25V

2

C0G-CERM 0201

B1

BCLK

B3

SYNC

A2

SDO

C1

SDI

A3

RST*

D2

DMIC1_DATA

E1

DMIC1_CLK

C2

DMIC2_DATA

D1

DMIC2_CLK

8409_VA_PLL

A6E2B2

VL_DM

VA_PLL

U6200

CS8409

WLCSP

GND_PLL

GNDL

A5

C3

C4

VL_SP

VL_HD

ASP2_MCLK ASP2_SCLK

ASP2_LRCK/FSYNC

ASP2_SDIN

ASP2_SDOUT

ASP1_MCLK ASP1_SCLK

ASP1_LRCK/FSYNC

ASP1_SDIN

ASP1_SDOUT

SPI_SCLK

MOSI

GPIO0/MISO1

GPIO1/CS1* GPIO2/CS2*

GPIO6/SCL GPIO7/SDA

GPIO3/MISO2

GPIO4 GPIO5

GNDD

A1

U6200.A6:A5:3 MM

1

C6200

1UF

10% 25V

2

X5R 603-1

F3

NC

F2

8409_ASP2_SCLK_R

E4

8409_ASP2_LRCLK_R

E3 F4

8409_ASP2_SDOUT_R

B6

NC

C5

8409_ASP1_SCLK_R

D6

8409_ASP1_LRCLK_R

B5

NC

C6

8409_ASP1_SDOUT_R

E6

NC

B4

NC

E5 D5 F5

8409_SPKR_ID0

D4

8409_I2C_SCL

D3

8409_I2C_SDA

F6

NC

F1

NC

A4

NC

1

R6227

47K

5% 1/20W MF 201

2

IN

PLACE_NEAR=U6200:5MM

1

R6229

820

5% 1/20W MF

62

201

2

104

1

C6288

100PF

5% 25V

2

C0G 0201

R6283

0

1 2

R6284

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6200:5MM

1

R6228

820

5% 1/20W MF 201

2

1

C6289

100PF

5% 25V

2

C0G 0201

ESDESD

5%

1/20W

MF

201

R6285

0

1 2

5%

1/20W

MF

201

PP1V8_S0

PLACE_NEAR=U6200:5MM

1

C6285

47PF

5% 25V

2

C0G 0201

60 62 63 100 104

8409_ASP1_SCLK_RC

8409_ASP1_LRCLK_RC

8409_ASP1_SDOUT_RC

NOSTUFF

1

C6286

47PF

5% 25V

2

C0G 0201

NOSTUFF

1

C6287

2

47PF

5% 25V C0G 0201

R6219

33

1 2

5%

1/20W

MF

201

R6221

33

1 2

5%

1/20W

MF

201

R6223

33

1 2

5%

1/20W

MF

201

R6230

33

1 2

5%

1/20W

MF

201

R6231

33

1 2

5%

1/20W

MF

201

R6232

33

1 2

5%

1/20W

MF

201

R6233

33

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6200:5MM

AUD_ASP1B_SCLK

R6220

33

1 2

5%

1/20W

MF

201

R6222

33

1 2

5%

1/20W

MF

201

R6225

33

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6200:5MM

AUD_ASP1B_LRCLK

PLACE_NEAR=U6200:5MM

AUD_ASP1B_SDOUT

PLACE_NEAR=U6200:5MM

AUD_ASP1A_SCLK

PLACE_NEAR=U6200:5MM

AUD_ASP1A_LRCLK

PLACE_NEAR=U6200:5MM

AUD_ASP1A_SDOUT

AMP_LT_I2C_SCL

PLACE_NEAR=U6200:5MM

AMP_CODEC_RT_I2C_SCL

PLACE_NEAR=U6200:5MM

AMP_LT_I2C_SDA

PLACE_NEAR=U6200:5MM

AMP_CODEC_RT_I2C_SDA

OUT

BI

OUT

62

63

RIGHT SPEAKER AMPS

63

62

LEFT SPEAKER AMPS

62

63 61

C

B

A

R6290

47K

5%

1/20W

MF

201

PP1V8_S0

1

2

60 62 63 100 104

CODEC_INT_L

CODEC_RESET_L

OUT

IN

61

BOM_COST_GROUP=AUDIO

DESIGN: X502/DEV_MLB_U LAST CHANGE: Wed Feb 18 17:12:24 2015

SYNC_MASTER=J79_JCURCIO SYNC_DATE=03/24/2016

PAGE TITLE

HDA Bridge

DRAWING NUMBER SIZE

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

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BRANCH

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PAGE

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60 OF 119

D

A

8 7 5 4 2 1

36

AUDIO JACK CODEC I2C ADDRESS

AD1 ADDRESS

1.8V GND

1.8V

AD0

GNDGND

1.8VGND

1.8V 0x96

0x90 <-0x92 0x94

AUD_PWR_EN

16

345678

L6361

FERR-470-OHM

1 2

0201

2 1

L83_LDO_EN

D

C

B

A

64

IN

MIN_LINE_WIDTH=0.0730 MIN_NECK_WIDTH=0.0850

AUD_HS_MIC_P

CRITICAL

5% 25V C0G

0201

1

2

C6352

27PF

AUD_HS_MIC_N

MIN_LINE_WIDTH=0.0730 MIN_NECK_WIDTH=0.0850

64 61

64

OUT

VOLTAGE=0V

GND_AUDIO_CODEC

61

64

OUT

R/C6550 FILTER TO ADDRESS OUT-OF-BAND

NOISE ISSUE SEEN ON EARLY HEADSETS

AUD_HP_PORT_L

AUD_HP_PORT_R

(SEE RADAR # 6210118)

R6351

2.2K

1/20W

R6352

12

1%

MF

201

CRITICAL

C6351

3300PF

X7R-CERM

0201

2.2K

1/20W

1%

MF

201

12

AUD_HP_PORT_CH_GND

AUD_HP_PORT_US_GND

10% 10V

D

PP1V8_AUDIO

61

GND_AUDIO_CODEC

L6300

FERR-22-OHM-1A-0.055OHM

1 2

0201

L6301

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

BYPASS=U6300.B1:C2:3 MM

1

C6301

2.2UF

20% 10V

2

X5R-CERM 402

CRITICAL

L83_VCP

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

PP3V3_S0

61 101 106

L6360

FERR-22-OHM-1A-0.055OHM

1 2

0201

BYPASS=U6360.A1:B2:3 MM

AUD_3V3_S0

1

2

CRITICAL

C6360

1UF

20% 10V X5R 0201

4

IN

3

EN

NOSTUFF

1

R6360

100K

5% 1/20W MF 201

2

XW6300

SHORT-8L-0.25MM-SM

1 2

U6360

NCP160AMX180

XDFN-COMBO

EPADGND

5

2

NOSTUFF

1

C6390

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

OUT

NOSTUFF

1

C6391

12PF

5% 25V

2

NP0-C0G 0201

1

CRITICAL

1

C6361

1UF

20% 10V

2

X5R 0201

GND_AUDIO_CODEC

VOLTAGE=1.8V

PP1V8_AUDIO

BYPASS=U6360.A2:B2:3 MM

61

FERR-22-OHM-1A-0.055OHM

PP1V8_AUDIO

61

BYPASS=U6300.A3:B3:3 MM

FERR-22-OHM-1A-0.055OHM

PP3V3_S0

61 101 106

1

R6300

1K

5% 1/20W MF 201

2

1

R6301

1K

5% 1/20W MF 201

2

64

64 61

AUD_HP_SENSE_L

IN

AUD_HP_SENSE_R

IN

BI

AUD_HP_PORT_CH_GND

HS_MIC_P

64 61

BI

AUD_HP_PORT_US_GND

HS_MIC_N

1

2

R6350

100K

5% 1/20W MF 201

2

NOSTUFF PLACE_NEAR=U6300:5mm

1

C6320

560PF

2% 25V

2

NPO-C0G 0201

NOSTUFF PLACE_NEAR=U6300:5mm

1

C6322

560PF

2% 25V

2

NPO-C0G 0201

NOSTUFF

PLACE_NEAR=U6300:5mm

1

C6321

560PF

2% 25V

2

NPO-C0G 0201

64

1

R6381

0

5% 1/20W MF 201

2

1 2

0201

C6303

CRITICAL

0.1UF

10% 16V

X7R-CERM

0402

L6302

1 2

0201

BYPASS=U6300.D7:C7:3 MM

CRITICAL

AUD_RING_SENSE

IN

AUD_TIP_SENSE

L83_HSBIAS_FILT

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0700

C6309

4.7UF

1 2

20%

6.3V X5R 402

BYPASS=U6300.F3:E3:3 MM

CRITICAL

PLACE_NEAR=U6300:5mm

L83_HSBIAS_FILT_REF

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0700

1

2

1

2

L83_VL

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

L83_VP

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

C6304

10UF

20% 10V X5R-CERM 0402-7

D7

VP

D5

HPSENSA

E5

HPOUTA

F5

HPSENSB

G5

HPOUTB

F1

HS4

E2

HS_CLAMP2

E1

HSIN+

G2

HS3

F2

HS_CLAMP1

D1

HSIN-

F4

HS4_REF

G4

HS3_REF

G3

RING_SENSE

E4

TIP_SENSE

F3

HSBIAS_FILT

E3

HSBIAS_FILT_REF

NC

A3

VL VA VCP

A7

VD_FILT

B1

CRITICAL

U6300

CS42L83A

WLCSP-SKT

SWIRE_SD/ASP_SDIN

SWIRE_CLK/ASP_SCLK

GNDL

B3

B6

C7

GNDHS GNDAGNDD

C2

G1

D6

+VCP_FILT

-VCP_FILT

GNDCP

VL_SEL

DIGLDO_PDN*

INT*

WAKE*

RESET*

SPDIF_TX

SWIRE_SEL

ASP_LRCK/FSYNC

ASP_SDOUT

AD0 AD1

SDA

SCL FLYP FLYC FLYN

FILT_P

D2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

L83_VCP_FILTP

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

L83_VCP_FILTN

E6 G6

F6

C4

D4

B7

C6

C5

A6

NC

D3

B5

A5

A4

B4

C3 B2

A1 A2 E7 F7 G7

C1

L83_FILT

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

L83_SDOUT_R

AMP_CODEC_RT_I2C_SDA AMP_CODEC_RT_I2C_SCL

GND_AUDIO_CODEC

CODEC_WAKE_L

L83_FLYP L83_FLYC L83_FLYN

1

C6310

10UF

20% 10V

2

X5R 0603

BYPASS=U6300.C1:C2:3 MM

CRITICAL

61

C6302

2.2UF

1 2

20% 10V

X5R-CERM

402

C6305

4.7UF

1 2

20% 10V

X5R-CERM

0402

C6306

4.7UF

1 2

20% 10V

X5R-CERM

0402

R6380

0

1 2

5%

1/20W

MF

201

60

BI

63

IN

BYPASS=U6300.D6:F6:3 MM

CRITICAL

L83_VCP_FILT_GND

CRITICAL BYPASS=U6300.E6:F6:3MM

CRITICAL

BYPASS=U6300.G6:F6:3MM

PLACE_NEAR=U6300:5mm

L83_SDOUT

BYPASS=U6300.E7:F7:3 MM

CRITICAL

63 60

MIN_LINE_WIDTH=0.2000

MIN_NECK_WIDTH=0.0700

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0700

XW6301

SM

1 2

1

2

R6302

47K

5% 1/20W MF 201

C6307

2.2UF

1 2

20% 10V

X5R-CERM

402

C6308

2.2UF

1 2

20% 10V

X5R-CERM

402

PP3V3_S0

R6303

100K

1 2

1%

1/20W

MF

201

NOSTUFF

1

C6380

47PF

5% 25V

2

C0G 0201

CRITICAL

BYPASS=U6300.G7:F7:3 MM

DESIGN: X502/DEV_MLB_U

101

CODEC_INT_L

CODEC_RESET_L

R6306

33

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6300:5mm

OUT

IN

60

AUD_ASP2_LRCLK

AUD_ASP2_SDOUT

AUD_ASP2_SDIN

AUD_ASP2_SCLK

IN

OUT

IN

60

C

B

LAST CHANGE: Wed Feb 18 17:31:01 2015

SYNC_DATE=05/13/2016SYNC_MASTER=J79_JCURCIO

PAGE TITLE

A

AUDIO JACK CODEC

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=AUDIO

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

63 OF 145

61 OF 119

D

2X MONO SPEAKER AMPLIFIERS

APN: 353S4074

GAIN = TBD

PLACE_NEAR=U6400.C4:3MM

PPBUS_G3H

62 63 100

345678

2 1

D

TDM SLOT 1

62 60

IN

60 62 63 100 104

PLACE_NEAR=U6400.D1:3MM

PLACE_NEAR=U6400:5MM

AUD_ASP1A_SCLK

PLACE_NEAR=U6400:5MM

AUD_ASP1A_LRCLK

PLACE_NEAR=U6400:5MM

AUD_ASP1A_SDOUT

PP1V8_S0

C6400

62 60

IN

BI

R6400

1 2

1/20W

R6402

1 2

1/20W

BYPASS=U6400.A1:A2:3 MM

1

1UF

20% 10V

2

X5R

0201

AMP_LT_I2C_SCL AMP_LT_I2C_SDA

0

5% MF

201

0

5% MF

201

R6401

0

1 2

5%

1/20W

MF

201

SPRAMP_5V_TL

1

C6402

2.2UF

20% 10V

2

X5R-CERM 402

PLACE_NEAR=U6400.D1:3MM

1

C6401

0.1UF

10% 16V

2

X7R-CERM 0402

C1 B1

C2

E2

AMP_TL_SCLK

AMP_TL_LRCLK

AMP_TL_SDOUT

D2

E1

SCL SDA

REG_EN

BCLK

FSYNC

SDATA

D1

A1

VREG50/AVDD

VREG18/DVDD

C3

U6400

SSM3515B

WLCSP

PGND

A3

E3

C4

PVDD

AGND

A2

BST+ OUT+ OUT+ OUTOUTBST-

ADDR

1

C6403

0.1UF

10% 16V

2

X7R-CERM 0402

E4 D3 D4 B3 B4 A4

B2

1

C6404

1UF

10% 25V

2

X5R 603-1

SPKRAMP_BSTP_1

SPKRAMP_TL_OUT_P

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000

SPKRAMP_TL_OUT_N

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.1000

SPKRAMP_BSTP_2

SPKRAMP_LT_I2C_ADDR

NO STUFF

1

R6408

0

5% 1/20W MF 201

2

I2C ADDR 0x2A / 0X15

1

C6405

22UF

20% 25V

2

X5R-CERM 0805

C6406

0.22UF

1 2

C6407

0.22UF

1 2

20% 25V X5R 603

L6400

180OHM-3.4A

1 2

0806

L6401

180OHM-3.4A

0806

Speaker ID Uses 2 Center Connector Pins

Confirm at Speaker Connector

104

SPKRCONN_TL_OUT_P

104

SPKRCONN_TL_OUT_N

1

C6408

220PF

5% 25V

2

C0G-CERM 0402

1

C6409

220PF

5% 25V

2

C0G-CERM 0402

104 60

OUT

8409_SPKR_ID0

10 PIN APN: 998-5655

J6410

FF14A-10C-R11DL-B-3H

F-RT-SM1

11

1

2

3

4

5

6

7

8

9

10

12

LEFT TWEETER SPEAKER CONNECTOR

D

C

B

TDM SLOT 2

62 60

IN

PP1V8_S0

60 62 63 100 104

62 60

PLACE_NEAR=U6420:5MM

AUD_ASP1A_SCLK

PLACE_NEAR=U6420:5MM

AUD_ASP1A_LRCLK

PLACE_NEAR=U6420:5MM

AUD_ASP1A_SDOUT

62 60

C6420

1UF

20% 10V X5R

0201

IN

BI

R6420

0

1 2

5%

1/20W

MF

201

R6422

0

1 2

5%

1/20W

MF

201

BYPASS=U6420.A1:A2:3 MM

1

2

1

C6421

0.1UF

10% 16V

2

X7R-CERM 0402

AMP_LT_I2C_SCL AMP_LT_I2C_SDA

AMP_WL_SCLK

R6421

0

1 2

5%

1/20W

MF

201

AMP_WL_LRCLK

AMP_WL_SDOUT

SPRAMP_5V_WL

1

C6422

2.2UF

20% 10V

2

X5R-CERM 402

D1

C1 B1

C2

E2

D2

E1

SCL SDA

REG_EN

BCLK

FSYNC

SDATA

VREG18/DVDD

C3

A1

VREG50/AVDD

C4

PVDD

U6420

SSM3515B

WLCSP

PGND

E3

AGND

A2

PGND

A3

PVDD

PLACE_NEAR=U6400.C4:3MM

1

C6423

0.1UF

10% 16V

2

X7R-CERM 0402

PLACE_NEAR=U6400.C4:3MM

1

C6424

1UF

10% 25V

2

X5R 603-1

SPKRAMP_BSTP_3

BST+ OUT+ OUT+ OUTOUTBST-

ADDR

E4 D3 D4 B3 B4 A4

B2

SPKRAMP_WL_OUT_P

SPKRAMP_WL_OUT_N

SPKRAMP_BSTP_4

SPKRAMP_I2C_ADDR

1

R6423

47K

5% 1/20W MF 201

2

PPBUS_G3H

1

C6425

22UF

20% 25V

2

X5R-CERM 0805

C6426

0.22UF

1 2

C6427

0.22UF

1 2

I2C ADDR 0x28 / 0X14

20% 25V X5R 603

62 63 100

L6420

180OHM-3.4A

1 2

0806

L6421

180OHM-3.4A

0806

104

SPKRCONN_WL_OUT_P

104

SPKRCONN_WL_OUT_N

1

C6428

220PF

5% 25V

2

C0G-CERM 0402

1

C6429

220PF

5% 25V

2

C0G-CERM 0402

10 PIN APN: 998-5655

J6430

FF14A-10C-R11DL-B-3H

F-RT-SM1

11

1

2

3

4

5

6

7

8

9

10

12

LEFT WOOFER SPEAKER CONNECTOR

C

B

A

DESIGN: X502/DEV_MLB_U

62 63 100

PPBUS_G3H

1

C6480

33UF

20% 16V

2

TANT-POLY CASE-B3

1

C6481

33UF

20% 16V

2

TANT-POLY CASE-B3

1

C6482

33UF

20% 16V

2

TANT-POLY CASE-B3

1

C6483

33UF

20% 16V

2

TANT-POLY CASE-B3

1

C6484

33UF

20% 16V

2

TANT-POLY CASE-B3

1

C6485

33UF

20% 16V

2

TANT-POLY CASE-B3

BOM_COST_GROUP=AUDIO

8 7 5 4 2 1

36

LAST CHANGE: Wed Feb 18 17:12:24 2015

SYNC_MASTER=J79_JCURCIO SYNC_DATE=11/18/2015

PAGE TITLE

Left Speaker Amps & Conn

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

64 OF 145

62 OF 119

A

D

2X MONO SPEAKER AMPLIFIERS

APN: 353S4073

GAIN = TBD

345678

2 1

D

C

SPKRAMP_5V_TR

CRITICAL

BYPASS=U6500.A1:A2:3 MM

PP1V8_S0

BI

IN

60 62 63 100 104

CRITICAL

1UF

20% 10V X5R

0201

1

2

C6500

AMP_CODEC_RT_I2C_SCL AMP_CODEC_RT_I2C_SDA

R6500

0

1 2

5%

1/20W

MF

201

R6502

0

1 2

5%

1/20W

MF

201

R6501

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=U6500.D1:3mm

63 61 60

PLACE_NEAR=U6500:5mm

TDM SLOT 3 I2C ADDRESS

PLACE_NEAR=U6500.D1:3mm

CRITICAL

1

C6501

0.1UF

10% 16V

2

X7R-CERM 0402

AMP_TR_SCLK

AMP_TR_LRCLK

AMP_TR_SDOUT

1

C6502

2.2UF

20% 10V

2

X5R-CERM 402

C1

SCL

B1

SDA

C2

REG_EN

E2

BCLK

D2

FSYNC

E1

SDATA

D1

A1

VREG50/AVDD

VREG18/DVDD

U6500

SSM3515B

PGND

A3

PLACE_NEAR=U6500.C4:3mm

C3

C4

PVDD

WLCSP

AGND

PGND

A2

E3

PLACE_NEAR=U6500.C4:3mm

CRITICAL

1

C6503

0.1UF

10% 16V

2

X7R-CERM 0402

E4

BST+

D3

OUT+

D4

OUT+

B3

OUT-

B4

OUT-

A4

BST-

B2

ADDR

U6400_B2

1

R6503

47K

5% 1/20W MF 201

2

PLACE_NEAR=U6500.C4:3mm

CRITICAL

1

C6504

1UF

10% 25V

2

X5R 603-1

RIO_SPKRAMP_BSTP_1

SPKRAMP_TR_OUT_P

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000

SPKRAMP_TR_OUT_N

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.1000

RIO_SPKRAMP_BSTP_2

0x2C / 0X16

PP1V8_S0

CRITICAL

1

C6505

22UF

20% 25V

2

X5R-CERM 0805

C6506

0.22UF

1 2

20% 25V X5R 603

C6507

0.22UF

1 2

20% 25V X5R 603

PPBUS_G3H

BYPASS=U6500.E4:D4:3 MM

PLACE_NEAR=U6500.D4:5mm

62 63 100

FL6500

180OHM-3.4A

1 2

0806

1 2

FL6501

PLACE_NEAR=U6500.B4:5mm

BYPASS=U6500.A4:B4:3 MM

60 62 63 100 104

180OHM-3.4A

CRITICAL

CRITICAL CRITICAL

C6508

220PF

5%

25V

C0G-CERM

0402

D

10-PIN APN: 998-5655

J6500

FF14A-10C-R11DL-B-3H

104

SPKRCONN_TR_OUT_P

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000

DIFFERENTIAL_PAIR=DP_RIO_SPKRAMP_BSTP_

104

SPKRCONN_TR_OUT_N

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000

DIFFERENTIAL_PAIR=DP_RIO_SPKRAMP_BSTP_

1

2

1

C6509

220PF

5% 25V

2

C0G-CERM 0402

NC NC

CRITICAL

F-RT-SM1

11

1

2

3

4

5

6

7

8

9

10

12

RIGHT TWEETER SPEAKER CONNECTOR

C

B

60

IN

AUD_ASP1B_LRCLK

IN

AUD_ASP1B_SDOUT

IN

AUD_ASP1B_SCLK

TDM SLOT 4

PLACE_NEAR=U6550.D1:3mm

63 61 60

PLACE_NEAR=U6550:5mm

60 62 63 100 104

IN

BI

BYPASS=U6550.A1:A2:3 MM

PP1V8_S0

CRITICAL

1UF

20% 10V X5R

0201

1

2

C6550

AMP_CODEC_RT_I2C_SCL AMP_CODEC_RT_I2C_SDA

R6550

0

1 2

5%

1/20W

MF

201

R6552

0

1 2

5%

1/20W

MF

201

R6551

0

1 2

5%

1/20W

MF

201

SPKRAMP_5V_WR

1

2

PLACE_NEAR=U6550.D1:3mm

CRITICAL

1

C6551

0.1UF

10% 16V

2

X7R-CERM 0402

AMP_WR_SCLK

AMP_WR_LRCLK

AMP_WR_SDOUT

CRITICAL

C6552

2.2UF

20% 10V X5R-CERM 402

C1

SCL

B1

SDA

C2

REG_EN

E2

BCLK

D2

FSYNC

E1

SDATA

D1

A1

VREG50/AVDD

VREG18/DVDD

C3

U6550

SSM3515B

WLCSP

PGND

A3

E3

PLACE_NEAR=U6550.C4:3mm

C4

PVDD

AGND

A2

PLACE_NEAR=U6550.C4:3mm

CRITICAL

1

C6553

0.1UF

10% 16V

2

X7R-CERM 0402

E4

BST+

D3

OUT+

D4

OUT+

B3

OUT-

B4

OUT-

A4

BST-

B2

ADDR

PLACE_NEAR=U6550.C4:3mm

CRITICAL

1

C6554

1UF

10% 25V

2

X5R 603-1

CRITICAL

1

C6555

22UF

20% 25V

2

X5R-CERM 0805

C6556

0.22UF

RIO_SPKRAMP_BSTP_3

SPKRAMP_WR_OUT_P

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000

SPKRAMP_WR_OUT_N

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000

C6557

0.22UF

RIO_SPKRAMP_BSTP_4

I2C ADDRESS 0x2E / 0X17

PP1V8_S0

1 2

20% 25V X5R 603

1 2

20% 25V X5R 603

60 62 63 100 104

PPBUS_G3H

BYPASS=U6550.E4:D4:3 MM

PLACE_NEAR=U6550.D4:5mm

62 63 100

FL6502

180OHM-3.4A

1 2

0806

1 2

CRITICAL CRITICAL

FL6503

PLACE_NEAR=U6550.B4:5mm

BYPASS=U6550.A4:B4:3 MM

180OHM-3.4A

C6558

220PF

C0G-CERM

CRITICAL

5%

25V

0402

10-PIN APN: 998-5655

J6550

FF14A-10C-R11DL-B-3H

104

SPKRCONN_WR_OUT_P

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000

DIFFERENTIAL_PAIR=DP1_RIO_SPKRAMP_BSTP_

SPKRCONN_WR_OUT_N

104

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000

DIFFERENTIAL_PAIR=DP1_RIO_SPKRAMP_BSTP_

1

2

1

C6559

220PF

5% 25V

2

C0G-CERM 0402

CRITICAL

F-RT-SM1

11

1

2

3

4

5

6

7

8

9

10

12

RIGHT WOOFER SPEAKER CONNECTOR

B

A

DESIGN: X502/DEV_MLB_U

PPBUS_G3H

62 63 100

CRITICAL

1

C6580

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

1

C6581

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

1

C6582

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

1

C6583

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

1

C6584

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

1

C6585

33UF

20% 16V

2

TANT-POLY CASE-B3

BOM_COST_GROUP=AUDIO

8 7 5 4 2 1

36

LAST CHANGE: Wed Feb 18 17:12:24 2015

SYNC_MASTER=J79_JCURCIO SYNC_DATE=12/03/2015

PAGE TITLE

Right Speaker Amps & Conn

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

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A

D

CODEC OUTPUT SIGNAL PATHS

345678

2 1

D

FUNCTION

TWEETERS

SUB

xxxxxxxxxxxxxxxxxxx

SPDIF OUT

CODEC INPUT SIGNAL PATHS

FUNCTION

DMIC 1

DMIC 2

VOLUME

0X02 (2)HP/HS OUT

0X03 (3)

0X04 (4)

N/A

0X02 (2) 0X10 (16)

0X03 (3)

0X04 (4)

0X0E (14)

CONVERTER

0X09 (9)

PIN COMPLEXCONVERTER

0X12 (18)

0X13 (19)

PIN COMPLEX

0X1C (28)

MUTE CONTROL

N/A

CODEC GPIO0

N/A

VREF

3.3V

OTHER CODEC GPIO LINES

LEFT SPEAKER ID

RIGHT SPEAKER ID GPIO3

DFET CONTROL0X21 (33)

GPIO2

GPIO4

INPUT

OUTPUT

xxxxxxxxxx

HEADSET MIC

0X07 (7)

0X18 (24)

2.7V

HIGH = FG, LOW = MERRY

HIGH = DFETs OPEN

D

C

61

IN

OUT

AUD_HP_PORT_L

AUD_HP_PORT_R

AUD_HP_PORT_US_GND

AUD_HP_PORT_CH_GND

AUD_HP_SENSE_L

AUD_HP_SENSE_R

AUD_TIP_SENSE

CRITICAL

FL6601

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6600

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6603

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6605

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6606

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6607

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6605

FERR-470-OHM

1 2

0201

104 64

104

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.0730 MIN_NECK_WIDTH=0.0850

AUD_CONN_HP_RIGHT

MIN_LINE_WIDTH=0.0730 MIN_NECK_WIDTH=0.0850

AUD_CONN_RING2

MIN_LINE_WIDTH=0.0730 MIN_NECK_WIDTH=0.0850

AUD_CONN_SLEEVE

MIN_LINE_WIDTH=0.0730 MIN_NECK_WIDTH=0.0850

AUD_CONN_HP_SENSE_L

104

AUD_CONN_HP_SENSE_R

AUD_CONN_TIP_SENSE

Audio Jack Flex Connector

APN: 516S00055

(Matching plug APN: 516S1055)

J6600

503304-2040

F-ST-SM

22

21

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

NC

19 20

23

24

AUD_CONN_HP_LEFT

AUD_CONN_HP_RIGHT

AUD_CONN_RING2

AUD_CONN_SLEEVE

C

104 64

B

61

OUT

AUD_HS_MIC_P

AUD_HS_MIC_N

CRITICAL

FL6602

120-OHM-25%-1.3A

1 2

0402

CRITICAL

FL6604

120-OHM-25%-1.3A

1 2

0402

AUD_CONN_SLEEVE_XW

104

MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0920

104

AUD_CONN_RING2_XW

MIN_LINE_WIDTH=0.0920 MIN_NECK_WIDTH=0.0920

B

A

DESIGN: X502/DEV_MLB_U LAST CHANGE: Wed Feb 18 17:12:24 2015

PAGE TITLE

AUDIO JACK CONNECTOR

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=AUDIO

8 7 5 4 2 1

36

REVISION

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PAGE

SHEET

SYNC_DATE=12/18/2015SYNC_MASTER=J79_JCURCIO

051-00515

9.0.0

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A

D

J79 Battery Hotbar Flex Pads

J6950

PWR-MLB-X362

HB-SM

1011

J6951

FF14A-6C-R11DL-B-3H

F-RT-SM

7

345678

2 1

D

13

14

12

1

2

3

4 5

9

8

7

6

C6950

0.1UF

10% 25V X5R 402

PPVBAT_G3H_CONN

1

2

C6960

1UF

10% 25V X5R

603-1

104 66

1

2

1

2

3

4

5

6

8

NC

104

SYS_DETECT_L

1

R6950

10K

5% 1/16W MF-LF 402

2

SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA BMON_IOUT

D6950

RCLAMP3552T

SLP1006N3T

BI

OUT

1

2

104 51

104 54

CRITICAL

3

C

B

100

104 66

FROM PBUS

PPBUS_G3H

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=20V

FROM DCIN

BMU POWER FLEX HOTBAR'd TO THE MLB:

1 J6950PCBA,FLEX,BMU PWR,X362632-00566 CRITICAL

R6907

2.2

R6902

0

1 2

5% 1/16W MF-LF

402

1 2

5%

1/8W

MF-LF

805

PPBUS_G3H_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=8.6V

PPDCIN_G3H_CHGR_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=20V

D6902

BAT30CWFILM

SOT-323

1

3

2

66

PPVIN_G3H_P3V3G3H

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=8.6V

66

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

C

CRITICAL

1

C6921

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

100 104

PP3V3_G3H_REG_R

1

C6915

10UF

20% 10V

2

X5R-CERM 0402-7

VOLTAGE=3.3V

1

C6916

10UF

20% 10V

2

X5R-CERM 0402-7

1

C6917

10UF

20% 10V

2

X5R-CERM 0402-7

B

1

C6905

2.2UF

20% 35V

2

X5R-CERM 0402

1

2

PM_EN_P3V3_G3H

C6906

2.2UF

20% 35V X5R-CERM 0402

NC

U6903

MAX77596

2

SUP

7

MODE

10

EN

6

RESET* BIAS

XW6900

1 2

TDFN

CRITICAL

AGND

PGND

5

4

11

SM

OUT/FB

EPAD

BST

LX

CRITICAL

1

C6920

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE

5G DESENSE

R6915

P3V3G3H_VBST_R

1

C6907

0.1UF

10% 16V

2

X5R-CERM 0201

L6900

10UH-20%-1.4A-0.399OHM

1 2

PIYA25201B-SM

R6910

115K

1 2

0.1%

1

R6911

47K

0.1% 1/20W MF 0201

2

1/20W

MF

0201

C6911

5.6PF

+/-0.1PF

25V C0G

0201

12

P3V3G3H_FB_R

1

R6912

10

5% 1/20W MF 201

2

1

C6912

10UF

20% 10V

2

X5R-CERM 0402-7

0

5%

1/20W

MF

0201

1

2

R6908

1

3

9

8

P3V3G3H_VBST

P3V3G3H_LX

P3V3G3H_FB

P3V3G3H_BIAS

1

C6910

0.33UF

10% 16V

2

CERM-X7R 603

P3V3G3H_FB_RC

0

1 2

5% 1/16W MF-LF

402

1

C6913

10UF

20% 10V

2

X5R-CERM 0402-7

PP3V3_G3H

1

C6914

10UF

20% 10V

2

X5R-CERM 0402-7

A

P3V3G3H_AGND

1

R6913

1.47K

1% 1/20W MF 201

2

BOM_COST_GROUP=PLATFORM POWER

PAGE TITLE

DC-In & Battery Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=12/03/2015SYNC_MASTER=J79_JSHAO

DRAWING NUMBER SIZE

051-00515

REVISION

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9.0.0

BRANCH

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PAGE

69 OF 145

SHEET

65 OF 119

A

8 7 5 4 2 1

36

345678

2 1

D

CRITICAL

1

C7000

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C7001

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C7002

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE5G DESENSE 2.4G DESENSE 5G DESENSE

CRITICAL

1

C7024

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

CRITICAL

1

C7003

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C7025

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

CRITICAL

1

C7026

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

CRITICAL

1

C7027

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

CRITICAL

1

C7006

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C7028

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

2.4G DESENSE5G DESENSE2.4G DESENSE

CRITICAL

1

C7029

6.8UF

20% 35V-0.09OHM

2

POLY-TANT CASE-B1-2-SM

CRITICAL

1

C7008

12PF

5% 25V

2

NP0-C0G 0201

104 65

CRITICAL

1

C7009

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

C7032

2.2UF

20% 35V

2

X5R-CERM 0402

CRITICAL

R7020

0.01

0.5%

0.5W MF

0306

1 2 3 4

1

2

3

13

FROM USB-C SOURCE

104 100

PPDCIN_G3H PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

(AMON)

TBA_CSI_R_NTBA_CSI_R_P

D1

1

C7033

2.2UF

20% 35V

2

X5R-CERM 0402

PLACE_NEAR=Q7030.2:1MM

7

8

9

10

S1/D2

VOLTAGE=20V

1

C7034

2.2UF

20% 35V

2

X5R-CERM 0402

PLACE_NEAR=Q7030.1:3mm

2.7UH-0.0196OHM-13.5A

TBA_PHASE1

IHLP4040BD-PIMA102D-COMBO

5

6

14

S2

CRITICAL

1

C7090

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE 5G DESENSE 2.4G DESENSE 2.4G DESENSE 5G DESENSE 5G DESENSE 2.4G DESENSE 5G DESENSE

1

C7035

2.2UF

20% 35V

2

X5R-CERM 0402

CRITICAL

1

C7091

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C7092

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C7093

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

5G DESENSE

CRITICAL

1

C7094

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C7050

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CRITICAL

1

C7095

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C7051

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CRITICAL

1

C7096

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE

CRITICAL

1

C7097

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C7053

2.2UF

20% 25V

2

X5R 0402-1

CRITICAL

1

C7098

12PF

5% 25V

2

NP0-C0G 0201

1

C7055

2.2UF

20% 25V

2

X5R 0402-1

CRITICAL

1

C7099

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C7054

1000PF

10% 25V

2

X7R 0201

OMIT_TABLE

L7030

1 2

TBA_PHASE2

CRITICAL

F7000

12AMP-32V

1 2

1206

14

S2

104

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

2

3

13

7

8

9

10

5

6

S1/D2

D1

VOLTAGE=13.1V

TO SYSTEM

PPBUS_G3H

D

100

C

B

A

PP7011

PP7012

PP7013

PP7014

PP7015

PP7016

P2MM

SM

PP

P2MM

66 65

50 66

1

R7022

1.00

1% 1/20W MF-LF 0201

2

TBA_CSI_N

12

PLACE_NEAR=U7000.C5:1MM

TBA_COMP

1

C7071

0.12UF

10%

10.0V

2

CERM-X5R 402

1

C7022

0.047UF

10% 50V

2

CER-X7R 0402

NO STUFF

DFN

Q7030

FDMD8800

TBA_GATE_Q1

TBA_VDDA

1

C7075

2.2UF

20% 25V

2

X6S-CERM 0402

B5

P_IN

C5

CSIN

D5

CSIP

A5

MPM_PBUS

D3

AUX_DET

B2

SGATE

C2

AGATE

E4

MPM_DET

F5

VR1_3P3

G5

SDA

H5

SCL

G2

SMC_RST_IN

G3

HPWR_EN*

E5

COMP

G4

CELL

G1

12

A2

VDDA

U7000

ISL9239

WCSP-1

OMIT_TABLE

AGND

E3

G1R

11

TBA_LX1

1

C7030

0.1UF

2

1

R7030

0

5% 1/16W MF-LF 402

2

R7075

4.7

1 2

1/20W

TBA_VDDP

C7077

X5R-CERM

D2

VDDP

PGND

E2

G2 4

TBA_GATE_Q2

10% 25V X7R-CERM-1 0402

TBA_BOOT1_RC

TBA_BOOT1

5%

MF

201

1

10UF

20% 25V

2

0603

LX1

LX2

H1 F1 G1 E1 D1 B1 C1 A1 A3 A4 B4 B3 C3 F2 H4 H3 H2 F4 F3 D4 C4

GATE_Q1

BOOT1

GATE_Q2 GATE_Q3

BOOT2

GATE_Q4

PBUS CSOP CSON

BGATE

VBAT

EN_VR1

SMC_RST*

IRQ* CBC_ON MPM_OK AUX_OK

AMON

BMON

NC

G2

4

TBA_GATE_Q3

TBA_LX2

C7040

0.1UF

10%

X7R-CERM-1

25V

0402

TBA_BOOT2_RC

R7040

5% 1/16W MF-LF

402

TBA_BOOT2

PM_EN_P3V3_G3H

SMC_RST_L

SMC_CHGR_INT_L

SMC_CBC_ON

SMC_AUX_OK

CHGR_AMON CHGR_BMON

0

DFN

Q7040

FDMD8800

G1

G1R

12

11

TBA_GATE_Q4

1

20% 25V

2

X5R

C7064

1000PF

1 2

10% 25V X7R

0201

CRITICAL

SI7137DP

3

S

2 1

C7067

0.1UF

10% 25V X5R

0201

Q7065

SO-8

SYM-VER-2

G

4

TBA_BGATE

1

2

1

2

5

D

C7063

4700PF

10% 25V CER-X5R 0201

10% 25V

0201

1

2

C7068

0.01UF

X5R-CERM

TO/FROM BATTERY

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=13.1V

PLACE_NEAR=Q7065.5:2MM

1

C7060

0.1UF

10% 25V

2

X5R 0201

C

104 65

20% 25V X5R

1

2

C7066

1

2

2.2UF

0402-1

C7069

2.2UF

0402-1

CRITICAL

1

(BMON)

2

(PBUS)

TBA_CSO_R_P

R7061

1.00

1% 1/20W MF-LF

0201

TBA_CSO_P

10% 50V

0402

1

2

C7061

0.047UF

CER-X7R

R7060

1 2 3 4

1

2

0.005

1% 1W MF

0612-5

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=13.1V

TBA_CSO_R_N

1

R7062

1.00

1% 1/20W MF-LF 0201

2

TBA_CSO_N

1

C7062

0.047UF

10% 50V

2

CER-X7R 0402

B

PLACE_NEAR=U7000.A4:1MM

12

OUT

104 80 59 50

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL1152S00198

BOM_COST_GROUP=PLATFORM POWER

DESIGN: X502/MLB LAST CHANGE: Thu Mar 5 18:14:03 2015

PAGE TITLE

PBUS Supply & Battery Charger

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

BRANCH

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PAGE

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66 OF 119

9.0.0

SYNC_DATE=12/03/2015SYNC_MASTER=J79_JSHAO

A

D

OUT

48

50

52

C7020

0.47UF

20%

4V

CERM-X5R-1

201

66 65

66 50

R7090

100K

1 2

5%

1/20W

MF

201

SMC_RESET_L

L7030IND,MLD,2.7UH,19.6MO,12.5A,10.9X10X2.4MM

1.00

1% 1/20W MF-LF

0201

1

2

R7021

TBA_CSI_P

10% 50V

0402

1

2

C7021

0.047UF

CER-X7R

1

R7015

750K

1% 1/20W MF 201

2

SM

1

PP

1

SM

1

PP

SM

1

PP

SM

1

PP

SM

1

PP

TBA_GATE_Q1

TBA_GATE_Q2

TBA_GATE_Q3

TBA_GATE_Q4

66

TBA_LX1

TBA_LX2

66

PM_EN_P3V3_G3H

SMC_CHGR_INT_L

1

P2MM

1

P2MM

SM

PP

SM

PP

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

P2MM

SM

PP

PP7001

PP7002

PP7003

PP7004

PP7005

PP7006

PP7007

PP7008

TBA_AUX_DET

NO STUFF

100

66 65

PP3V3_G3H

C7080

1UF

20% 10V X5R

0201

PPVIN_G3H_P3V3G3H

PLACE_NEAR=U7000.A5:2MM

C7081

2.2UF

20% 35V

X5R-CERM

0402

R7008

10K

5%

1/20W

MF

201

1

2

1

2

C7016

0.01UF

X5R-CERM

1

2

R7009

100K

1/20W

10% 25V

0201

5%

MF

201

1

2

1

2

1

R7016

255K

1% 1/20W MF 201

2

TBA_MPM_DET

51

BI

51

IN

50

IN

104

C7070

0.12UF

CERM-X5R

C7023

0.47UF

20%

4V

CERM-X5R-1

201

PPVIN_G3H_P3V3G3H

65 66

SMBUS_SMC_5_G3_SDA SMBUS_SMC_5_G3_SCL SMC_4FINGERS_RST HPWR_EN_L

1

10%

10.0V 2

402

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

8

68 67

IN

8

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPUCORE_ISUMP

CPUCORE_ISUMN CPUCORE_ISUMN_R

CPUCORE_ISEN1

CPUCORE_ISEN2

68

IN

R7160

93.1K

CPUSA_ISUMP

CPUSA_ISUMN

CPU_VCCSASENSE_P

CPU_VCCSASENSE_N

68

IN

1%

1/20W

MF

201

C7181

220PF

X7R-CERM

R7190

147K

1/20W

C7154

0.01UF

X7R-CERM

0201

12

IMON_B_CPUCORE

C7160

150PF

10% 25V

X7R-CERM

0201

1

10% 25V

2

201

C7182

0.01UF

10% 10V

X7R-CERM

0201

12

1%

MF

201

1

10% 10V

2

12

R7181

1 2

1

2

C7190

68PF

12

5% 25V C0G

0201

C7141

330PF

C7151

220PF

X7R-CERM

C7153

0.01UF

10% 10V

X7R-CERM

0201

C7152

0.01UF

X7R-CERM

R7180

1K

1%

1/20W

MF

201

C7171

R7142

0

1 2

5%

1/20W

MF

201

1

C7142

330PF

10% 16V

2

X7R 0201

67 54

10% 16V X7R

0201

10% 25V

201

10% 10V

0201

422

1%

1/20W

MF

201

1

2

1

2

1

2

1

2

12

SA_ISUMN_R

IMON_C_CPUSA

R7172

1 2

1/20W

201

1

2

330PF

10% 16V X7R

0201

1

2

FB_CORE_R

XW7140

SM

1 2

R7150

249

1/20W

R7151

1K

1 2

1%

1/20W

MF

201

C7161

6800PF

X7R-CERM

0201

C7180

3300PF

1 2

10% 10V

X7R-CERM

0201

67

0

5%

MF

XW7170

1 2

C7172

330PF

10% 16V X7R 0201

R7143

1.58K

1%

1/20W

C7144

MF

201

3300PF

12

FB_B_CORE_R

10% 10V

X7R-CERM

0201

RTN_B_CPUCORE

12

1%

MF

201

CORE_ISUMN_R

C7162

68PF

12

COMP_B_CPUCORE_L

10% 10V

CPUSA_ISUMN_R

C7191

6800PF

10% 10V

X7R-CERM

0201

R7173

FB_SA_R

2.15K

1/20W

C7174

3300PF

12

FB_C_SA_R

10% 10V

X7R-CERM

0201

SM

RTN_C_CPUSA

12

R7144

1K

1%

1/20W

MF

201

67

C7150

3300PF

1 2

10% 10V

X7R-CERM

0201

CPU VCC Core

12

5% 25V C0G

0201

12

COMP_C_CPUSA_L

12

1%

MF

201

COMP_B_CPUCORE

R7161

4.99K

1%

1/20W

MF

201

67

R7174

2.15K

1%

1/20W

MF

201

FB_B_CPUCORE

R7145

560

12

1 2

1%

1/20W

MF

201

PPBUS_HS_CPU

100

12

CPU VCC SA

C7192

150PF

12

10% 25V

X7R-CERM

0201

R7191

4.99K

1%

1/20W

MF

201

FB_C_CPUSA

R7175

560

12

67

1 2

1%

1/20W

MF

201

67

FB_B_CORE_RC

C7143

1000PF

10% 25V X7R

0201

67

68

OUT

68 67

67

68 67

OUT

68

OUT

IN

67

IN

67

67 54

67 67

68

OUT

IN

67

COMP_C_CPUSA

12

67

FB_C_SA_RC

C7173

820PF

10% 25V

X7R-CERM

0201

P2MM

SM

68 67

1

2

68 67

CPUCORE_PWM1

CPUSA_PWM

1

P2MM

1

PP

SM

PP

PP7100

70 67

PP7202

CPUGT_PWM1

CPUGT_PWM2

R7101

10

1 2

5%

1/20W

MF

201

PPVIN_S0_CPUVR_VIN

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=13.1V

1

C7101

0.22UF

10% 25V

2

X7R 0402

41

VIN

42

VCC

PP5V_COREVR_VCC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=5V

1

2

U7100

ISL95828HRTZ

CPUCORE_FCCM

CPUCORE_PWM1 CPUCORE_PWM2 CPUGT_PWM2

CPUCORE_ISUMP CPUCORE_ISUMN_R

CPUCORE_ISEN1 CPUCORE_ISEN2

COMP_B_CPUCORE

FB_B_CPUCORE

RTN_B_CPUCORE

IMON_B_CPUCORE

NTC_B_CPUCORE

CPUSA_FCCM

CPUSA_PWM

CPUSA_ISUMP CPUSA_ISUMN_R

COMP_C_CPUSA

FB_C_CPUSA

RTN_C_CPUSA

IMON_C_CPUSA

PROG1_CPUCOREVR

PROG2_CPUCOREVR PROG3_CPUCOREVR

PROG4_CPUCOREVR PROG5_CPUCOREVR

67

PROG1_CPUCOREVR

FCCM_B

PWM1_B PWM2_B

ISUMP_B ISUMN_B

ISEN1_B ISEN2_B

COMP_B

FB_B

RTN_B

IMON_B

NTC_B

34

FCCM_C

PWM_C

32

ISUMP_C

33

ISUMN_C

29

COMP_C

30

FB_C

31 45

RTN_C

28

IMON_C

40

PROG1

39

PROG2

38

PROG3

37

PROG4

36

PROG5

LLP

THRM_PAD

49

67

PROG2_CPUCOREVR

FCCM_A

PWM1_A PWM2_A PWM3_A

ISUMP_A ISUMN_A

ISEN1_A ISEN2_A ISEN3_A

COMP_A

FB_A

RTN_A

IMON_A

NTC_A

VR_HOT*

VR_READY

VR_ENABLE

ALERT*

SCLK

PSYS

67

PROG3_CPUCOREVR

1

2

1

R7111

78.7K

1% 1/20W MF 201

2

1

R7112

63.4K

1% 1/20W MF 201

2

1

R7113

1.87K

1% 1/20W MF 201

2

1

R7114

182K

1% 1/20W MF 201

2

PROG4_CPUCOREVR

1

2

2411

2512 2613 27

197 208

219 2210 23

164

175

186

142

153

46

4735

48

43

SDA

44

1

R7115

100K

0.1% 1/20W MF 0201-1

CPUGT_FCCM

CPUGT_PWM1

CPUGT_PWM3

CPUGT_ISUMP CPUGT_ISUMN_R

CPUGT_ISEN1 CPUGT_ISEN2 CPUGT_ISEN3

COMP_A_CPUGT

FB_A_CPUGT

RTN_A_CPUGT

IMON_A_CPUGT

NTC_A_CPUGT

CPU_PROCHOT_L_R

CPUVR_PGOOD

CPU_VR_EN_R

CPUVR_VIDSOUT_R

CPUVR_VIDALERT_L_R

CPUVR_VIDSCLK_R

CPUCORE_PSYS

1

C7108

4700PF

10% 10V

2

X7R 201

67

PROG5_CPUCOREVR

R7100

1

1 2

5%

1/20W

MF

201

C7100

1UF

10% 10V CER-X6S 0402

PP5V_S4

67

OUT

R7106

49.9

1 2

1/20W

PP5V_S0

NOSTUFF

1

R7107

12.1K

1% 1/20W MF 201

2

1

R7108

12.1K

1% 1/20W MF 201

2

67

OUT

IN

67 54

1%

MF

201

P2MM

1

P2MM

1

70

77 74

SM

PP

SM

PP

70 67

R7103

1 2

67

PP7103

67

FB_A_CPUGT

PP7104

FB_A_GT_RC

10% 25V

0201

1

2

C7148

680PF

X7R-CERM

101

CPU VCC GT + GTx Merged

67

R7102

100

0

5%

1/20W

MF

201

1

R7110

45.3

1% 1/20W MF 201

2

R7105

0

1 2

5%

1/20W

MF

201

1 2

5%

1/20W

MF

201

PP1V0_S3

R7104

1 2

68 101

NTC_A_CPUGT

67

10

5%

1/20W

MF

201

CPU_PROCHOT_L

1

R7109

100

1% 1/20W MF 201

2

CPU_VIDALERT_L

R7120

13.3K

NTC_B_CPUCORE

1 2

1%

1/20W

MF

201

R7149

453

1%

1/20W

MF

201

CPUGT_ISUMN_R

C7155

3300PF

10% 10V

X7R-CERM

0201

ALL_SYS_PWRGD

CPU_VIDSOUT

CPU_VIDSCLK

R7121

13.3K

1 2

1%

1/20W

MF

201

NTC_B_CPUCORE_R

BOM_COST_GROUP=CPU & CHIPSET

NTC_A_CPUGT_R

R7148

1K

12

1 2

1%

1/20W

MF

201

RTN_A_CPUGT

67

R7154

1 2

12

GT_ISUMN_R

OUT

IN

101

BI

IN

49 48 6

77

8

332

1%

1/20W

MF

201

1

2

R7147

2.67K

1 2

1%

1/20W

MF

201

FB_A_GT_R

R7155

1K

1%

1/20W

MF

201

COMP_A_CPUGT

67

1

R7124

220KOHM-3%

0201

2

R7123

220KOHM-3%

0201

FB_GT_R

R7146

0

C7147

1500PF

XW7141

12

1 2

10% 10V X7R

0201

SM

1

2

1

C7149

0.01UF

10% 10V

2

X7R-CERM 0201

12

C7146

330PF

10% 16V X7R

0201

C7156

220PF

10% 25V X7R-CERM 201

1

C7157

0.01UF

10% 10V

2

X7R-CERM 0201

5%

1/20W

MF

201

1

2

12

1

2

C7145

330PF

10% 16V X7R 0201

1

C7158

0.01UF

10% 10V

2

X7R-CERM 0201

CPU_VCCGTSENSE_P

CPU_VCCGTSENSE_N

CPUGT_ISUMP

CPUGT_ISUMN

CPUGT_ISEN1

CPUGT_ISEN2

CPUGT_ISEN3

1

C7159

0.01UF

10% 10V

2

X7R-CERM 0201

IN

C7193

68PF

1 2

5%

R7193

2.49K

1 2

1%

1/20W

MF

201

25V C0G

0201

COMP_A_CPUGT_L

C7194

6800PF

1 2

10% 10V

X7R-CERM

0201

R7194

95.3K

67 54

IMON_A_CPUGT

C7195

150PF

12

10% 25V

X7R-CERM

0201

SYNC_MASTER=J79_JSHAO SYNC_DATE=03/02/2016

PAGE TITLE

1 2

1%

1/20W

MF

201

CORE & SA IMVP IC

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

71 OF 145

SHEET

67 OF 119

8

D

8

70 67

70

C

70 67

B

A

D

8 7 5 4 2 1

36

D

PPBUS_HS_CPU

68 100

PP5V_S0

67 68 101

R7215

1

1 2

5% 1/16W MF-LF

402

PVCCCORE_PH1_AGND

68

68 67

67

IN

CPU VCC Phase 1

C7217

2.2UF

20% 25V

X6S-CERM

0402

CPUCORE_FCCM

CPUCORE_PWM1

PVCCCORE_PH1_AGND

68

345678

1

C7210

33UF

1

VOLTAGE=5V

PP5V_S0_VCORE1

1

2

3

VCC

29

PVCC

U7210

BOOT

SW SW

GL0 GL1

GH

5

7

16 24

27 3330

6

NC NC

31

8 9

2

1

VIN VIN

FCCM

PWM

NC NC

FDMF5808A

PQFN-COMBO-THICKSTNCL

OMIT_TABLE

CRITICAL

AGND

4

32

PGND

12

XW7210

SM

PHASE

PGND

28

12

C7216

2.2UF

20% 25V

2

X6S-CERM 0402

CPUCORE1_GL0

NC

CPUCORE1_DRVH

CPUCORE_SW1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

CPUCORE_BOOT1

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

R7219

68

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

CPUCORE_PHASE1

CPUCORE_BP1

DIDT=TRUE

C7219

68

0.22UF

5% 1/16W MF-LF

402

10% 25V X7R

0402

CRITICAL

R7210

0.00075

L7210

0.22UH-35A-0.00255OHM

1 2

PILS062D-IHLP2525BD-SM-COMBO

1

R7218

2.2

5% 1/10W MF-LF 603

1

0

2

1

2

NOSTUFF

CPUCORE_SW1_SNUB

DIDT=TRUE

1

C7218

0.001UF

10% 50V

2

X7R-CERM 0402

NOSTUFF

PPVCC_CPU_PH1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7212

1/20W

1K

1%

MF

201

1

2

1% 1W MF

0612-1

1

2

NO_XNET_CONNECTION=1

12 34

CPUCORE_ISNS1_P CPUCORE_ISNS1_N

1

R7211

2.2

1% 1/20W MF 201

2

NO_XNET_CONNECTION=1

R7213

200K

1% 1/20W MF 201

20% 16V

2

TANT-POLY CASE-B3

NO_XNET_CONNECTION=1

CPUCORE_ISUMN

CPUCORE_ISEN1

CPUCORE_ISUMP

1

C7211

33UF

20% 16V

2

TANT-POLY CASE-B3

OUT

53

68 53

1

C7212

33UF

20% 16V

2

TANT-POLY CASE-B3

OUT

67

1

C7213

2.2UF

20% 25V

2

X6S-CERM 0402

68 67

NO_XNET_CONNECTION=1

1

C7214

2.2UF

20% 25V

2

X6S-CERM 0402

R7214

200K

1/20W

68 67

1%

MF

201

12

CPUCORE_ISNS2_N

PLACE_NEAR=U7210.32:2MM

1

C7215

12PF

5% 25V

2

NP0-C0G 0201

68 53

2 1

PPVCC_S0_CPU

100

Vout = 0.55 - 1.5V IccMax = 32A F = 750kHz

CPUCORE1_GL0

68

CPUCORE2_GL0

68

CPUSA_GL0

68

CPUCORE1_DRVH

68

CPUCORE2_DRVH

68

P2MM

1

P2MM

1

P2MM

1

P2MM

1

P2MM

1

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

D

PP7210

PP7220

PP7270

PP7211

PP7221

C

B

PPBUS_HS_CPU

68 100

PP5V_S0

67 68 101

R7225

1

1 2

5% 1/16W MF-LF

402

PVCCCORE_PH2_AGND

68

68 67

67

IN

CPU VCC Phase 2

C7227

2.2UF

20% 25V

X6S-CERM

0402

CPUCORE_FCCM

CPUCORE_PWM2

PVCCCORE_PH2_AGND

68

P2MM

SM

68 67

1

VOLTAGE=5V

PP5V_S0_VCORE2

1

2

3

VCC

29

PVCC

U7220

BOOT

SW SW

GL0 GL1

GH

5

7

16 24

27 3330

6

NC NC

31

8 9

2

1

VIN VIN

FCCM

PWM

NC NC

FDMF5808A

PQFN-COMBO-THICKSTNCL

OMIT_TABLE

CRITICAL

AGND

4

32

PGND

12

XW7220

SM

PHASE

PGND

28

12

1

C7226

2.2UF

20% 25V

2

X6S-CERM 0402

CPUCORE2_GL0

DIDT=TRUE

NC

SWITCH_NODE=TRUE

CPUCORE2_DRVH

DIDT=TRUE SWITCH_NODE=TRUE

CPUCORE_SW2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

CPUCORE_BOOT2

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

R7229

68

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

CPUCORE_PHASE2

CPUCORE_BP2

DIDT=TRUE

68

C7229

0.22UF

5% 1/16W MF-LF

402

10% 25V X7R

0402

CRITICAL

R7220

0.00075

L7220

0.22UH-35A-0.00255OHM

1 2

PILS062D-IHLP2525BD-SM-COMBO

1

R7228

2.2

5% 1/10W MF-LF

1

0

2

1

2

603

2

NOSTUFF

CPUCORE_SW2_SNUB

DIDT=TRUE

1

C7228

0.001UF

10% 50V

2

X7R-CERM 0402

NOSTUFF

PPVCC_CPU_PH2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7222

1K

1%

1/20W

MF

201

1

2

1% 1W MF

0612-1

1

2

NO_XNET_CONNECTION=1

12 34

1

R7221

2.2

1% 1/20W MF 201

2

NO_XNET_CONNECTION=1

R7223

200K

1% 1/20W MF 201

C7220

33UF

20% 16V

2

TANT-POLY CASE-B3

CPUCORE_ISNS2_P CPUCORE_ISNS2_N

NO_XNET_CONNECTION=1

CPUCORE_ISUMN

CPUCORE_ISEN2

CPUCORE_ISUMP

1

C7221

33UF

20% 16V

2

TANT-POLY CASE-B3

OUT

53

68 53

OUT

68 67

67

68 67

1

C7223

2.2UF

20% 25V

2

X6S-CERM 0402

NO_XNET_CONNECTION=1

R7224

200K

1/20W

1%

MF

201

12

CPUCORE_ISNS1_N

1

C7224

2.2UF

20% 25V

2

X6S-CERM 0402

1

C7225

12PF

5% 25V

2

NP0-C0G 0201

68 53

CRITICAL

1

C7230

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE

68 67

CPUCORE_FCCM

CPUSA_FCCM

CPUSA_DRVH

68

1

2

5G DESENSE

CRITICAL

C7231

3.0PF

+/-0.1PF 25V NP0-C0G 0201

2.4G DESENSE 5G DESENSE

1

2

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

CRITICAL

C7232

12PF

5% 25V NP0-C0G 0201

PP7212

PP7272

PP7271

CRITICAL

1

C7233

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

C

B

A

PPBUS_HS_CPU

100

PP5V_S0

67 68 101

R7275

1

1 2

5% 1/16W MF-LF

402

PVCCCSA_AGND

68

68 67

67

IN

CPUSA_FCCM

CPUSA_PWM

CPUSA_DRVH

68 68

CPU VCCSA

C7277

2.2UF

20% 25V

X6S-CERM

0402

PLACE_NEAR=U7220.32:2MM

67

L7270

1

C7272

2.2UF

20% 25V

2

X6S-CERM 0402

1

C7270

33UF

VOLTAGE=5V

PP5V_S0_VCCSA

1

2

VCIN

11

VDRV

U7270

SIC535CD

6

1

12

3

VIN

ZCD_EN*

PWM

NC

MLP4535

PGND

7

XW7270

SM

12

BOOT

PHASE

VSWH

PGND

CGND

13

10

PVCCCSA_AGND

68

GL GL

4

5

8

9 14

1

C7276

2.2UF

20% 25V

2

X6S-CERM 0402

CPUSA_GL0

NC

CPUVR_SWSA

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

CPUSA_BOOTSA

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

DIDT=TRUE SWITCH_NODE=TRUE

CPUSA_BPSA

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

CPUSA_PHASESA

R7279

5% 1/16W MF-LF

402

DIDT=TRUE

C7279

0.22UF

10% 25V X7R

0402

CRITICAL

OMIT_TABLE

L7270

0.47UH-20A-0.00494OHM

1 2

IHLP2020BD-SM

1

R7278

2.2

5% 1/10W MF-LF 603

2

NOSTUFF

PPVCCSA_CPU_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.15V

R7270

0.002

1% 1W

CYN

0612

1 2 3 4

CPUSA_ISNS_P CPUSA_ISNS_N

R7272

0

1 2

5%

1/20W

MF

201

CPUSA_SW_SNUB

1

0

2

1

2

DIDT=TRUE

1

C7278

0.001UF

10% 50V

2

X7R-CERM 0402

NOSTUFF

353S00497 CRITICAL2

152S00241 1

IC,FDMF5808A,DRMOS,IMVP8,50A,PQFN31,5X5 U7210, U7220

IND,MLD,0.47UH,4.94MO,20A,5.4X5.2X2.4MM

20% 16V

2

TANT-POLY CASE-B3

NO_XNET_CONNECTION=1

R7274

1K

1 2

1%

1/20W

MF

201

NO_XNET_CONNECTION=1

CPUSA_ISUMN

CPUSA_ISUMP

1

C7271

33UF

20% 16V

2

TANT-POLY CASE-B3

OUT

55

OUT

1

C7273

2.2UF

20% 25V

2

X6S-CERM 0402

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL

2.4G DESENSE

PLACE_NEAR=U7270.13:2MM

BOM_COST_GROUP=CPU & CHIPSET

1

C7274

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C7280

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C7281

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

5G DESENSE

PPVCCSA_S0_CPU

100

Vout = 0.55 - 1.15V IccMax = 5.1A F = 750kHz

SYNC_MASTER=J79_JSHAO SYNC_DATE=12/03/2015

PAGE TITLE

CORE & SA IMVP POWER BLOCK

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

72 OF 145

SHEET

68 OF 119

D

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

SYNC_MASTER=J79_SILUCHEN SYNC_DATE=04/02/2015

PAGE TITLE

Empty

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

73 OF 145

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A

D

PPBUS_HS_CPU

70 100

PP5V_S0

70 101

R7416

1

1 2

5% 1/16W MF-LF

402

VOLTAGE=5V

PP5V_S0_VGT1

C7417

2.2UF

X6S-CERM

PVCCCGT_PH1_AGND

70

70 67

67

IN

CPUGT_FCCM

CPUGT_PWM1

CPU VCCGT/GTx Phase 1

PLACE_NEAR=U7410.32:2MM

PVCCCGT_PH1_AGND

70

20% 25V

0402

345678

200K

1%

1/20W

MF

201

1

C7414

33UF

20% 16V

2

TANT-POLY CASE-B3

12

NO_XNET_CONNECTION=1

1

C7410

1

29

3

1

2

8

VIN

9

VIN

PQFN-COMBO-THICKSTNCL

2

FCCM

1

PWM

31

NC NC

XW7410

VCC

U7410

FDMF5808A

OMIT_TABLE

CRITICAL

AGND

4

32

SM

12

PVCC

PGND

12

PGND

28

BOOT

PHASE

SW SW

GL0 GL1

GH

5

7

16 24

27 3330

6

C7416

2.2UF

20% 25V

2

X6S-CERM 0402

NC NC

CPUGT_SW1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

CPUGT_BOOT1

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

CPUGT1_DRVH

DIDT=TRUE SWITCH_NODE=TRUE

CPUGT_BP1

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

CPUGT_PHASE1

70

C7419

0.22UF

R7419

0

5% 1/16W MF-LF

402

10% 25V X7R

0402

0.22UH-20%-44A-0.0019OHM

1

2

1

2

1

2

L7410

1 2

PILA082D-SM

R7418

2.2

5% 1/10W MF-LF 603

NOSTUFF

CPUGT_SW1_SNUB

DIDT=TRUE

C7418

0.001UF

10% 50V X7R-CERM 0402

NOSTUFF

NO_XNET_CONNECTION=1

PPVCCGT_CPU_PH1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7412

1/20W

1K

1%

MF

201

R7410

0.00075

1

2

1% 1W MF

0612-1

12 34

1

R7411

2.2

1% 1/20W MF 201

2

NO_XNET_CONNECTION=1

1

R7413

200K

1% 1/20W MF 201

2

NO_XNET_CONNECTION=1

33UF

20% 16V

2

TANT-POLY CASE-B3

CPUGT_ISNS1_P CPUGT_ISNS1_N

CPUGT_ISUMN

CPUGT_ISEN1

CPUGT_ISUMP

1

C7411

33UF

20% 16V

2

TANT-POLY CASE-B3

OUT

55

70 55

1

C7412

33UF

20% 16V

2

TANT-POLY CASE-B3

OUT

70 67

67

70 67

1

C7413

2.2UF

20% 25V

2

X6S-CERM 0402

NO_XNET_CONNECTION=1

R7414

200K

1%

1/20W

MF

201

12

CPUGT_ISNS2_N

R7415

2 1

1

C7415

12PF

5% 25V

2

NP0-C0G 0201

PPVCCGT_S0_CPU

Vout = 0.55 - 1.5V IccMax = 64A F = 750kHz

70 55

CPUGT_ISNS3_N

70 55

100

D

C

PPBUS_HS_CPU

70 100

70 101

PP5V_S0

R7426

1

1 2

5% 1/16W MF-LF

402

VOLTAGE=5V

PP5V_S0_VGT2

C7427

2.2UF

X6S-CERM

PVCCCGT_PH2_AGND

70

70 67

67

IN

CPUGT_FCCM

CPUGT_PWM2

CPU VCCGT/GTx Phase 2

PLACE_NEAR=U7420.32:2MM

70

PVCCCGT_PH2_AGND

20% 25V

0402

CRITICAL

1

C7440

12PF

5% 25V

2

NP0-C0G 0201

PP5V_S0

70 101

1

C7426

2.2UF

29

3

1

2

8

VIN

9

VIN

PQFN-COMBO-THICKSTNCL

2

FCCM

1

PWM

31

NC NC

XW7420

VCC

U7420

FDMF5808A

OMIT_TABLE

CRITICAL

AGND

4

32

SM

12

PVCC

PGND

12

PGND

28

BOOT

PHASE

SW SW

GL0 GL1

GH

5

7

16 24

27 3330

6

20% 25V

2

X6S-CERM 0402

NC NC

NC

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

CPUGT_PHASE2

CPUGT_SW2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

CPUGT_BOOT2

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

SWITCH_NODE=TRUE

CPUGT_BP2

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000

DIDT=TRUE

R7429

5% 1/16W MF-LF

402

C7429

0.22UF

10% 25V X7R

0402

L7420

0.22UH-20%-44A-0.0019OHM

1 2

PILA082D-SM

1

R7428

2.2

5% 1/10W MF-LF

1

0

2

1

2

603

2

NOSTUFF

CPUGT_SW2_SNUB

DIDT=TRUE

1

C7428

0.001UF

10% 50V

2

X7R-CERM 0402

NOSTUFF

NO_XNET_CONNECTION=1

PPVCCGT_CPU_PH2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7422

1K

1%

1/20W

MF

201

R7420

0.00075

1

2

1% 1W MF

0612-1

12 34

1

R7421

2.2

1% 1/20W MF 201

2

NO_XNET_CONNECTION=1

1

R7423

200K

1% 1/20W MF 201

2

NO_XNET_CONNECTION=1

1

C7420

33UF

20% 16V

2

TANT-POLY CASE-B3

CPUGT_ISNS2_P CPUGT_ISNS2_N

CPUGT_ISUMN

CPUGT_ISEN2

CPUGT_ISUMP

1

C7421

33UF

20% 16V

2

TANT-POLY CASE-B3

OUT

55

1

C7490

33UF

20% 16V

2

TANT-POLY CASE-B3

70 55

OUT

70 67

67

70 67

1

C7423

2.2UF

20% 25V

2

X6S-CERM 0402

NO_XNET_CONNECTION=1

R7424

200K

1/20W

1%

MF

201

12

1

C7424

2.2UF

20% 25V

2

X6S-CERM 0402

CPUGT_ISNS1_N

R7425

200K

1/20W

1%

MF

201

12

CPUGT_ISNS3_N

NO_XNET_CONNECTION=1

1

C7425

12PF

5% 25V

2

NP0-C0G 0201

70 55

CRITICAL

1

C7442

12PF

5% 25V

2

NP0-C0G 0201

70 55

5G DESENSE2.4G DESENSE

CRITICAL

1

C7441

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C7443

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

C

B

A

PPBUS_HS_CPU

70 100

R7436

1

70 101

PP5V_S0

PVCCCGT_PH3_AGND

70

1 2

5% 1/16W MF-LF

402

70 67

67

IN

CPU VCCGT/GTx Phase 3

PLACE_NEAR=U7430.32:2MM

353S00497

3 CRITICAL

IC,FDMF808A,DRMOS,IMVP8,50A,PQFN31,5X5

VOLTAGE=5V

PP5V_S0_VGT3

20% 25V

0402

1

2

C7437

2.2UF

X6S-CERM

CPUGT_FCCM

CPUGT_PWM3

70

PVCCCGT_PH3_AGND

U7410, U7420, U7430

NC NC

31

8 9

2

1

70 101

VIN VIN

FCCM

PWM

NC NC

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

PP5V_S0

29

3

VCC

PVCC

U7430

FDMF5808A

PQFN-COMBO-THICKSTNCL

OMIT_TABLE

CRITICAL

AGND

4

32

XW7430

SM

12

70 67

CPUGT_FCCM

PGND

12

PGND

28

BOOT

PHASE

SW SW

GL0 GL1

GH

5

7

16 24

27 3330

6

1

C7436

2.2UF

20% 25V

2

X6S-CERM 0402

CPUGT3_GL0

DIDT=TRUE

NC

SWITCH_NODE=TRUE

CPUGT3_DRVH

DIDT=TRUE SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

CPUGT_PHASE3

P2MM

SM

1

PP

CPUGT_SW3

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

DIDT=TRUE

CPUGT_BOOT3

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000 DIDT=TRUE

SWITCH_NODE=TRUE

70

CPUGT_BP3

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000

DIDT=TRUE

PP7412

C7439

70

CPUGT1_DRVH

70

R7439

5% 1/16W MF-LF

402

0.22UF

10% 25V X7R

0402

L7430

0.22UH-20%-44A-0.0019OHM

1 2

PILA082D-SM

1

R7438

2.2

5% 1/10W MF-LF

1

0

2

1

2

603

2

NOSTUFF

CPUGT_SW_SNUB

DIDT=TRUE

1

C7438

0.001UF

10% 50V

2

X7R-CERM 0402

NOSTUFF

P2MM

SM

1

PP

P2MM

SM

1

PP PP

NO_XNET_CONNECTION=1

PPVCCGT_CPU_PH3

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.5V

NO_XNET_CONNECTION=1

R7432

PP7411

CPUGT3_GL0CPUGT3_DRVH

PP7431

70 70

1K

1%

1/20W

MF

201

R7430

0.00075

1

2

1% 1W MF

0612-1

12 34

1

R7431

2.2

1% 1/20W MF 201

2

NO_XNET_CONNECTION=1

1

R7433

200K

1% 1/20W MF 201

2

1

C7430

33UF

20% 16V

2

TANT-POLY CASE-B3

CPUGT_ISNS3_P CPUGT_ISNS3_N

NO_XNET_CONNECTION=1

P2MM

SM

1

PP7430

1

C7431

33UF

20% 16V

2

TANT-POLY CASE-B3

OUT

CPUGT_ISUMN

CPUGT_ISEN3

CPUGT_ISUMP

55

1

2

70 55

C7491

33UF

20% 16V TANT-POLY CASE-B3

OUT

70 67

1

C7433

2.2UF

20% 25V

2

X6S-CERM 0402

NO_XNET_CONNECTION=1

R7434

200K

1/20W

67

OUT

70 67

BOM_COST_GROUP=CPU & CHIPSET

1%

MF

201

12

1

C7434

2.2UF

20% 25V

2

X6S-CERM 0402

CPUGT_ISNS1_N

R7435

200K

1/20W

1%

MF

201

12

CPUGT_ISNS2_N

NO_XNET_CONNECTION=1

PAGE TITLE

1

C7435

12PF

5% 25V

2

NP0-C0G 0201

70 55

GT & GTX IMVP POWER BLOCK

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

SYNC_DATE=09/25/2015SYNC_MASTER=J79_JSHAO

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

74 OF 145

SHEET

70 OF 119

B

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8 7 5 4 2 1

36

345678

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SYNC_MASTER=J79_SILUCHEN SYNC_DATE=03/27/2015

PAGE TITLE

Empty

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

75 OF 145

71 OF 119

A

D

345678

2 1

D

C

B

72 101 104

C7606

2.2UF

X6S-CERM

1

C7608

2.2UF

20% 25V

2

X6S-CERM 0402

1

2

5VS4_VFB1_RR

1

2

1

2

PPBUS_HS_OTH5V

100

C7600

33UF

TANT-POLY

CASE-B3

PP5V_S4

VOUT = 5V

1.58A MAX OUTPUT F = 500 KHZ

1

20% 25V

2

0402

1

C7605

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

P5VS4_VFB1_R

R7677

200

1% 1/20W MF 201

R7678

41.2K

0.1% 1/16W MF 0402

Change R7677 to 200 Ohm 1% and R7678 to 41.2K 0.1% in Proto-2.

R7679

10K

0.1% 1/16W MF 0402

1

20% 16V

2

C7607

150UF

20%

6.3V

TANT-POLY

CASE-B1S-1

XW7675

XW7671

5V S4 - V5

5.14V Norm

1

C7601

2.2UF

20% 25V

2

X6S-CERM 0402

OMIT_TABLE

L7600

1

2

1

2

PLACE_NEAR=C7607.1:3MM

2

SM

1

PLACE_NEAR=L7600.1:3MM

2

SM

1

2.2UH-20%-4.5A-0.043OHM

IHLP1616BZ-PIMA042T-COMBO

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

P5VS4_VSW

NO STUFF

1

R7674

1

5% 1/10W MF-LF 603

2

P5VS4_SNUBR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

SWITCH_NODE=TRUE

PLACE_NEAR=L7600.2:3MM

2

XW7670

SM

1

P5VS4_CSP1_R

1

C7602

2.2UF

20% 25V

2

X6S-CERM 0402

DIDT=TRUE

1

6 7 8

NO STUFF

C7674

0.0033UF

10% 50V

CERM

402

U7600

CSD58879Q3D

Q3D

VIN

VSW

PGND

9

1

2

3

TG

4

TGR

5

BG

R7672

4.87K

1%

1/20W

MF

201

1

C7603

12PF

5% 25V

2

NP0-C0G 0201

1

2

PPBUS_HS_OTH3V3

100

P5VS4_TG

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 GATE_NODE=TRUE DIDT=TRUE

P5VS4_VBST_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

C7609

0.1UF

10% 25V

2

X6S-CERM 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

C7673

0.1UF

1 2

10%

6.3V X7R

0201

R7673

698

1 2

1%

1/20W

MF

201

SKIP_5V3V3:AUDIBLE

R7609

0

5%

1/20W

MF

201

C7678

270PF

X7R-CERM

0201-1

10% 25V X6S

0402

1

2

C7650

1.0UF

SKIP_5V3V3:INAUDIBLE

R7650

R7651

1

R7665

1

2

1

5% 1/20W MF 201

2

SWITCH_NODE=TRUE DIDT=TRUE

GATE_NODE=TRUE DIDT=TRUE

SWITCH_NODE=TRUE DIDT=TRUE

GATE_NODE=TRUE DIDT=TRUE

77 74

NO STUFF

1

R7676

10K

1% 1/20W MF 201

2

1

10% 16V

2

1

0

5%

1/20W

MF

0201

2

P5VP3V3_SKIPSEL

P5VS4_VBST

P5VS4_DRVH

P5VS4_SW

P5VS4_DRVL

P5VS4_CSP1 P5VS4_CSN1

P5VS4_VFB1 P5VS4_COMP1

77

IN

P5VS4_EN P5VS4_PGOOD

P5VS4_COMP1_R

1

C7679

4700PF

10% 10V

2

X7R 201

(P5VP3V3_VREF2)

GND_5V3V3_AGND

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0V

PP5V_S4

72 101 104

1

0

5%

1/20W

MF

0201

2

R7675

3.92K

1/20W

1% MF

201

2

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

31

VBST1 VBST2

1

DRVH1 DRVH2

32

SW1 SW2

30

DRVL1

7

CSP1

8

CSN1 CSN2

11

MODE

9

10

COMP1 COMP2

4

EN1 EN2

5

PGOOD1 PGOOD2

1

2

XW7650

PLACE_NEAR=U7650.28:1MM

23

VIN

CRITICAL

U7650

GND

28

2

SM

1

29

VREG5

QFN

22

VREG3

TPS51980A

THRM_PAD

33

P5VP3V3_VREG3

P5VP3V3_VREF2

13

VREF2

12

EN

DRVL2

CSP2

RF

VFB2VFB1

26

24

25

27

18 17

3 16 15

21 20

DIDT=TRUE

DIDT=TRUE GATE_NODE=TRUE

10% 10V

402

1

2

C7652

0.22UF

CERM

P5VS5_EN

P3V3S5_VBST

SWITCH_NODE=TRUE

P3V3S5_DRVH

GATE_NODE=TRUEDIDT=TRUE

P3V3S5_SW

P3V3S5_DRVL

P3V3S5_CSP2 P3V3S5_CSN2

P3V3S5_RF P3V3S5_VFB2 P3V3S5_COMP2

P3V3S5_EN S5_PWRGD

1

R7695

3.92K

1% 1/20W MF 201

2

P3V3S5_COMP2_R

(P5VP3V3_VREF2)

1

2

1

C7653

2.2UF

20% 10V

2

X5R-CERM 402

IN

OUTOUT

NO STUFF

R7696

C7699

2700PF

10% 10V

X7R-CERM

201

PP5V_S5

VOUT = 5V

CRITICAL

100MA MAX OUTPUT

C7651

10UF

20% 10V X5R-CERM 0402-7

77

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520DIDT=TRUE SWITCH_NODE=TRUE

77

77 74

1

10K

1%

1/20W

MF

201

2

1

2

R7685

1

1 2

5%

1/20W

MF

201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

R7669

0

2

R7655

1

C7698

330PF

10% 16V

2

X7R 0201

5% 1/20W MF 201

200K

1/20W

101

P3V3S5_TG

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE GATE_NODE=TRUE

P3V3S5_VBST_R

C7671

0.1UF

X6S-CERM

0201

R7686

1 2

1/20W

201

C7693

0.1UF

1 2

1

6.3V

1% MF

201

2

0201

R7693

1.58K

1 2

1/20W

201

3.3V DSW - V6

1

5%

25V

2

0201

1.0UH-20%-14A-0.0107OHM

U7660

CSD58873Q3D

Q3D

VSW

PGND

9

DIDT=TRUE

10% 25V

0

5% MF

10% X7R

1% MF

1

2

P3V3S5_DRVL_R

DIDT=TRUE GATE_NODE=TRUE

1

R7692

3.83K

1% 1/20W MF 201

2

P3V3S5_CSP2_R

C7682

12PF

NP0-C0G

3

TG

4

TGR

5

BG

1

C7660

33UF

20% 16V

2

TANT-POLY CASE-B3

1

VIN

6 7 8

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

P3V3S5_VSW

R7694

P3V3S5_SNUBR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

NO STUFF

1

C7694

0.001UF

10% 50V

2

X7R-CERM 0402

L7660

PIMB062D-SM

NO STUFF

1

10

5% 1/10W MF-LF

603

2

XW7690

C7664

2.2UF

X6S-CERM

1

C7661

33UF

20% 16V

2

TANT-POLY CASE-B3

1

2

PLACE_NEAR=L7660.1:3MM

2

PLACE_NEAR=L7660.2:3MM

XW7691

2

SM

1

SM

1

20% 25V

2

0402

1

C7662

33UF

20% 16V

2

TANT-POLY CASE-B3

1

C7665

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

CASE-B1S-1

PLACE_NEAR=C7665.1:3MM

2

XW7695

SM

1

P3V3S5_VFB2_R

R7697

P3V3S5_VFB2_RR

R7698

R7699

C7663

2.2UF

20% 25V

X6S-CERM

0402

C7666

150UF

20%

6.3V

TANT-POLY

1

402

1%

1/20W

MF

201

2

1

23.2K

0.1%

1/16W

MF

0402

2

1

10K

0.1%

1/16W

MF

0402

2

1

2

1

C7675

33UF

20% 16V

2

TANT-POLY CASE-B3

PP3V3_S5

VOUT = 3.3V

8.47A MAX OUTPUT F = 500 KHZ

1

C7667

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

1

C7668

150UF

2

C7669

2.2UF

20% 25V

X6S-CERM

0402

6.3V

TANT-POLY

CASE-B1S-1

1

2

1

20%

2

C7670

2.2UF

X6S-CERM

20% 25V

0402

1

2

101

C7672

150UF

20%

6.3V TANT-POLY CASE-B1S-1

C7676

150UF

TANT-POLY

CASE-B1S-1

NO STUFF

1

2

20%

6.3V

D

1

2

C

B

A

CRITICAL

1

C7610

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE 5G DESENSE 2.4G DESENSE 5G DESENSE

CRITICAL

1

C7611

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

2.4G DESENSE

CRITICAL

1

C7612

12PF

5% 25V

2

NP0-C0G 0201

5G DESENSE

CRITICAL

1

C7613

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C7614

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C7615

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

152S00182

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1 CRITICAL

IND,PWR,2.2UH,20%,4.5A,43MOHM,4X4MM

L7600

CRITICAL

1

C7683

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE

BOM_COST_GROUP=PLATFORM POWER

CRITICAL

1

C7684

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C7685

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE 5G DESENSE5G DESENSE 5G DESENSE2.4G DESENSE

SYNC_MASTER=J79_JSHAO SYNC_DATE=03/23/2016

PAGE TITLE

CRITICAL

1

C7686

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C7687

12PF

5% 25V

2

NP0-C0G 0201

Power - 5V 3.3V Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CRITICAL

1

C7688

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

76 OF 145

SHEET

72 OF 119

A

8 7 5 4 2 1

36

PPBUS_HS_CPU

100

1V EDRAM & EOPIO

345678

2 1

D

C

C7715

0.1UF

10%

6.3V X7R

0201

BYPASS=U7700.6::1mm

PPVCCEDRAM_S0_REG_F

73

C7709

33UF

20% 16V

TANT-POLY

CASE-B3

1

C7700

33UF

2

TANT-POLY

CASE-B3

20% 16V

1

2

1

C7701

2.2UF

20% 25V

2

X6S-CERM 0402

1

C7704

2.2UF

20% 25V

2

X6S-CERM 0402

D

PVCCEDRAM_BOOT_RC

BYPASS=U7700.2::1mm

PP5V_S0

73 101

C7702

10UF

BYPASS=U7700.12::1mm

X5R-CERM

0402-1

12 15

17 16

6

8

19 18

20% 10V

1

2

C7703

10UF

X5R-CERM

0402-1

Scrub S3 & S5 pins connections!

PVCCEDRAM_S3_EN

ALL_SYS_PWRGD

73

PVCCEDRAM_VREF

MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600

1

2

1

R7711

30.9K

0.1%

0.05W MF 0201

2

PLACE_NEAR=U7700.8:5mm

MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600

PVCCEDRAM_REFIN

PVCCEDRAM_MODE PVCCEDRAM_TRIP

PVCCEDRAM_VREF_R

1

R7719

3.09K

1% 1/20W MF 201

2

1

R7712

48.7K

0.1% 1/20W MF 0201

2

PLACE_NEAR=U7700.8:5mm

1

C7716

0.01UF

10% 10V

2

X7R-CERM 0201

1

R7715

1K

1% 1/20W MF 201

2

PLACE_NEAR=U7700.17:3mm

1

R7713

33K

1% 1/20W MF 201

2

PLACE_NEAR=U7700.19:3mm

1

R7714

35.7K

1% 1/20W MF 201

2

PLACE_NEAR=U7700.18:3mm

20% 10V

V5IN

S3 S5

VREF

REFIN

MODE TRIP

1

2

VLDOIN

U7700

TPS51916

CRITICAL

PGND GND

7

10

2

QFN

VTT THRM

GND PAD

4

VBST DRVH

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

21

2

XW7700

SM

1

PVCCEDRAM_VBST

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

DIDT=TRUE

14 13

11 20 9

PVCCEDRAM_VTT

3 1

5

PVCCEDRAM_DRVH

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

GATE_NODE=TRUE DIDT=TRUE

PVCCEDRAM_VTTREF

C7740

0.22UF

20% 10V

CERM-X5R

0201

MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600

DIDT=TRUE

2.2

5%

1/20W

MF

201

1

2

R7730

DIDT=TRUEGATE_NODE=TRUE

PVCCEDRAM_LL

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0700

SWITCH_NODE=TRUE DIDT=TRUE

1 2

1

2

R7731

1

1 2

5%

1/20W

MF

201

R7732

1

5%

1/20W

MF

201

1

C7730

0.1UF

10% 25V

2

X6S-CERM 0201

GATE_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

P1VEDRAM_DRVH_R

GATE_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

P1VEDRAM_DRVL_RPVCCEDRAM_DRVL

Q7700

CSD58873Q3D

3

TG

4

TGR

5

BG

Q3D

9

VIN

VSW

PGND

VOLTAGE=1.00V MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

PPVCCEDRAM_S0_REG_F

OMIT

1

L7700

VOLTAGE=1.00V

6 7 8

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

PPVCCEDRAM_PHASE

NOSTUFF

1

R7710

2.2

5% 1/10W MF-LF 603

2

1UH-20%-11A-0.0127OHM

IHLP2020BD-PIHA052D-COMBO

1 2

55

PPVCCEDRAM_S0_REG_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.00V

ISNS_CPUEDRAM_P

OUT

ISNS_CPUEDRAM_N

OUT

R7718

0.005

1%

1/3W

MF

0306-SHORT

12 34

Vout = 1.05V

5.2A MAX OUTPUT F = 500 KHZ

73

PVCCEDRAM_LL_SNUB

DIDT=TRUE

NOSTUFF

C7710

0.001UF

10% 50V

X7R-CERM

0402

PLACE_NEAR=C7707.1:1mm

1

C7705

10UF

2

20%

4V

X6S

0402

1

C7706

10UF

2

0402

20%

4V

X6S

1

2

1

C7707

220UF

20% 2V

23

ELEC SM-COMBO

1

C7708

220UF

20% 2V

23

ELEC SM-COMBO

1

C7711

220UF

20% 2V

23

ELEC SM-COMBO

1

C7714

220UF

20% 2V

23

ELEC SM-COMBO

1

C7712

270UF

20% 2V

2

TANT CASE-B

2

XW7710

SM

1

C

B

BYPASS=U7700.8::1mm

PVCCEDRAM_AGND

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0V

6

IN

NC_CPU_MSM_L

MAKE_BASE=TRUE

Calculated OCP: min=6.34A, typ=12.07A, max=22.35A

102

PLACE_NEAR=U7700.21:1mm

PM_PCH_SYS_PWROK

THE FOLLOWING SHORTCUTS ARE USED:

- OPC (EDRAM) IS POWERED FROM ONE VR.

- LOAD SWITCHES ARE USED TO MEET THE TURN-ON TIMING.

- MSM# IS NOT USED.

P1VOPC_SNS

MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600

73

R7741

10

1 2

5%

1/20W

MF

201

P1VOPC_SNS_R

MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600

104 73 48 14

77 74 48

PM_PCH_SYS_PWROK

MAKE_BASE=TRUE

ALL_SYS_PWRGD

MAKE_BASE=TRUE

PM_PCH_SYS_PWROK

ALL_SYS_PWRGD

73

B

A

PP1V0_S3

101

10% 10V

0201

NC

1

2

C7790

0.1UF

X5R-CERM

6

IN

ZVM is CMOS DC Output: V_OL Max = Vcc * 0.1V V_OH Min = Vcc * 0.9V Vcc referred to in these specs refers to VccST/IO

CPU_ZVM_L

LEVEL SHIFT

6

VCC

U7790

74AUP1G07GF

SOT891

2

1

GND

(OD)

3

PPVCCEDRAM_S0_REG_F

73

PP5V_S0

PP3V3_S0

101

PM_SLP_S3_L

NOSTUFF

1

R7791

100K

5% 1/20W MF 201

2

4

YA

5

NCNC

NC

SLG5AP031 EN: V_IL Max = 1V V_IH Min = 2V

1

R7792

100K

5% 1/20W MF 201

2

PM_OPC_ZVM_L

73

73 101

C7760

104 92 80 77 74 48 26 19 14

0.1UF

X5R-CERM

PM_OPC_ZVM_L

73

SWEOPIO_CNFG

1

2

1

10% 16V

2

0201

R7760

2.2M

5% 1/20W MF 201

2

3

1

VCC

U7760

SLG5AP031

EN

CNFG

TDFN

GND

4

THRM

PAD

9

S

DONE

5

D

7

SWEOPIO_G

G

6

8

NC

G

5

D

Q7761

FDMC7570S

POWER33

S

1 2 3

5

D

4

G

S

1 2 3

Q7760

FDMC7570S

POWER33

4

PPVCCEDRAM_S0_CPU

CRITICAL

1

C7762

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE

5G DESENSE

CRITICAL

1

C7763

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

BOM_COST_GROUP=CPU & CHIPSET

1

C7761

20UF

20%

2.5V

2

X6S-CERM 0402-1

104 73 48 14

PAGE TITLE

PM_PCH_SYS_PWROK

100

Power - EOPIO EDRAM Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

PP3V3_S0

74 101

1

R7790

10K

1% 1/20W MF 201

2

SYNC_DATE=04/12/2016SYNC_MASTER=J79_JSHAO

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

77 OF 145

SHEET

73 OF 119

A

8 7 5 4 2 1

36

345678

2 1

D

C

74 77

GND

77 49 48

R7820

1M

1%

1/20W

MF

NOSTUFF

201

R7821

0

5%

1/20W

MF

201

77 74

BANJO - PMIC Control

77 74

GND

74 77

CKPLUS_WAIVE=PWRTERM2GND

L1

ECVCC

(OD)

OMIT_TABLE

U7800

P650839A0D

PBGA

(8 OF 10)

IN

77 74

1

2

SMC_PM_G2_EN

PP3V3_PMICLDO

PPBUS_PMIC

74

GND

74 77

PMIC_VDCSNS

1

2

PP3V3_PMICLDO

74 77

D11

ACOK

H2

PWRBTNIN

E5

VINPP

F1 G1

BAT2

E2

ACIN

G3

VDCSNS

H9

NVDC*

(LDO3V = 3S)

CRITICAL

(OD)

(PP)

(OD)

DS3_VREN

1HZ

SYS_PWROK

PCH_PWROKBAT1

ALL_SYS_PWRGD

RSMRST_L_PWRGD

PMIC_INT*

EC_RST*

EC_ONOFF*

PCH_PWRBTN*

(OD)

DPWROK

ACSWON*

BAT1SWON* BAT2SWON*

VCCST_PWRGD

K13

K11

H11

E11

G11

J11

D12

J3

K4

K2

K12

J2

F2 G2

E4

NC

GND

PM_PCH_PWROK

ALL_SYS_PWRGD

PM_RSMRST_L

SMC_PMIC_INT_L

GND

CPU_VCCST_PWRGD

(Pull up on Chipset Page)

OUT

74 77

14

77

PMIC_SHUTDOWN_L

74

104 74 48 19 14

74 14

77 74 73 48

77 74

49 48

104 92 80 77 74 73 48 26 19 14

104 77 48 43 19 14

104 92 80 77 74 73 48 26 19 14

77 74 72

77 76

104 77 14

77 74 67

104 74 48 19 14

77

IN

77 74

IN

77 74

IN

PM_SLP_S0_L

PP3V3_SUS

101

PP1V8_S3

100

PP3V3_PMICLDO S5_PWRGD

PP3V3_S0

73 74 101

PP1V8_S0

100

P5VS4_PGOOD PM_SLP_S3_L

P1V8SUS_PGOOD PM_SLP_S4_L

PP3V3_PMICLDO

PM_SLP_SUS_L PM_SLP_S3_L

CPUVR_PGOOD

PM_SLP_S0_L

PP3V3_PMICLDO

PLACE_NEAR=U7800.D1:2MM

C7839

2.2UF

X6S-CERM

GND

74 77

D9

E7 K9 K8 E6 F4 E8

J10

F5

B12 C11 C12 J13 F10 J12 B10 L11

L6

1

10% 10V

2

0402

OMIT_TABLE

SHUTDOWN*

STANDBY*

VSA VSB VSC VSD VSE VSF VSG VSH

ENA ENB ENC END ENE ENF ENG ENH

ENLVA

L8

D1

VDDPG

U7800

P650839A0D

PBGA

(1 OF 10)

CRITICAL

PP3V3_S5

VDDLV

(PP) (PP)

(PP) (PP) (PP) (PP) (OD)

(OD) (OD)

PLACE_NEAR=U7800.L8:2MM

1

C7840

1UF

20% 10V

2

X6S-CERM 0201

GND

PGA PGB PGC PGD PGE PGF PGG PGH

LVA

LVB

C8C7

D6 C5 C6 H3 C4 H4 F3 M6

L12 L10

RESET*

NC

NC_PMIC_PGC NC_PMIC_PGD NC_PMIC_PGE NC_PMIC_PGF NC_PMIC_PGG

74 101

74 77

P3V3SUS_PGOOD

P1V8S3_EN

PVCCIO_EN

PM_SLP_S0S3_L

PM_PCH_PWROK

102

OUT

74

77 74 67

74 77

77

78

74

74 14

77 72

74 101

P5VS4_PGOOD

S5_PWRGD

72 74 77

PP3V3_PMICLDO

PMIC_SHUTDOWN_L

PP3V3_S0

73 74 101

CPUVR_PGOOD

PP3V3_SUS

101

PM_RSMRST_L

PP3V3_S5

1

2

1

2

1

2

1

R7801

100K

5% 1/20W MF 201

2

R7860

100K

5% 1/20W MF 201

R7861

100K

5% 1/20W MF 201

R7810

4.7K

5% 1/20W MF 201

1

R7802

100K

5% 1/20W MF 201

2

D

C

B

77 74

PP3V3_PMICLDO

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

PMIC_SLAVEADDR

74

PMIC_EN3V3SW

P5VS4_PGOOD

77

PP5V_S4

77

R7837

100K

1 2

5%

1/20W

MF

201

51

BI

IN

PP3V3_PMICLDO

74 77

R7866

0

77 74 76 75 74

PP3V3_PMICLDO

1UF

20% 10V

0201

1

2

C7830

X6S-CERM

C7841

1UF

20% 10V

X6S-CERM

0201

VOLTAGE=5V

1

2

M13

VDDIO1

D3

VDD5_VPROGOTP

E1

VDDIO0

U7800

P650839A0D

PBGA

(7 OF 10)

H1

SDA

J1

SCLK

L3

SLAVEADDR

K3

EN3V3SW

M5

EN5VSW

N5

VIN5VSW

OMIT_TABLE

CRITICAL

TEMP_ALERT*

VOUT3V3SW

LDO3V

VREF1V25

LDO5V

L2

M7

PP3V3_PMICLDO

N8

B1

PP1V25_PMICVREF

N7

PP5V_PMICLDO

1 2

5%

1/20W

MF

201

1

C7831

1UF

20% 10V

2

X6S-CERM 0201

76 75 74

PP5V_PMICLDO

77 74

74

PP3V0_G3H

100

GND

74 77

B13

J4

PP3V0_G3H

100

C13

V3P3A_RTC

OMIT_TABLE

VBATTBKUP

VCOMP

F6F7F8G5G6G7G8H5H6H7H8J5J6J7J8K6K7

U7800

P650839A0D

PBGA

(10 OF 10)

CRITICAL

AGND

PLACE_NEAR=U7800.C13:2MM

1

C7880

1UF

20% 10V

2

X6S-CERM 0201

GND

(OD)

TRIP*

NC0 NC1 NC2 NC3

H10

A1 A13 N1 N13

NC NC NC NC

74 77

GND

74 77

74 14

77 74 73 48

74 75

100

PP3V3_S0

73 74 101

PM_PCH_PWROKPP5V_PMICLDO_R

ALL_SYS_PWRGD

PP3V3_S5

74 101

PVCCIO_EN

PPBUS_G3H

R7865

0

1 2

5%

1/20W

MF

201

1

R7804

10K

5% 1/20W MF 201

2

PPBUS_PMIC

VOLTAGE=13.1V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

R7805

10K

5% 1/20W MF 201

2

1

R7807

100K

5% 1/20W MF 201

2

74

B

A

PLACE_NEAR=U7800.M8:2MM

C7837

1.0UF

10% 25V X6S

0402

74

PLACE_NEAR=U7800.N6:2MM

10% 25V X6S

0402

1

2

1

C7838

1.0UF

2

PP3V3_PMICLDO

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

PPBUS_PMIC

GND

74 77

M8

VINLDO3

N6

VIN

AGND2

AGND3

L13

AGND4

D13

76

PLACE_NEAR=U7800.N7:2MM

1

C7836

10UF

20%

6.3V

2

CERM-X6S 0402

75 74

PP1V25_PMICVREF

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.25V

PLACE_NEAR=U7800.N7:2MM

1

C7835

10UF

20%

6.3V

2

CERM-X6S 0402

74

PLACE_NEAR=U7800.B1:2MM

1

C7834

0.47UF

10% 10V

2

X7R 0402

PLACE_NEAR=U7800.N8:2MM

1

C7833

10UF

20%

6.3V

2

CERM-X6S 0402

104 92 80 77 74 73 48 26 19 14

PM_SLP_S3_L

AGND1

C1

K1

77 74

PP5V_PMICLDO

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0700 VOLTAGE=5V

PMIC_SLAVEADDR

74

1

R7808

100K

5% 1/20W MF 201

2

PM_SLP_S0S3_L

74

PVCCIO_EN

74 75

PVCCIO_EN

74

R7864

0

1 2

5%

1/20W

MF

201

NOSTUFF

PP3V3_PMICLDO

PM_SLP_S0S3_L

MAKE_BASE=TRUE

PVCCIO_EN

MAKE_BASE=TRUE

BOM_COST_GROUP=PLATFORM POWER

77 74

SYNC_DATE=09/09/2015SYNC_MASTER=J79_JSHAO

PAGE TITLE

A

PMIC-1 & Power Control

77

75

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

78 OF 145

SHEET

74 OF 119

8 7 5 4 2 1

36

345678

2 1

D

1.2V VDDQ - V10 (Banjo#1 VR4)

Calculated OCP: min=9.83A, typ=18.18A, max=32.64A

PP5V_PMICLDO

P1V2S3_ILIM

GND

IN

PM_MEMVTT_EN

IN

PVCCIO_EN

OUT

PM_SLP_S4_L

IN

R7900

11K

1/20W

Check R7901

1

1%

MF

201

2

R7901

100K

1/20W

201

76 74

77

7

74

77

1

5%

MF

2

OMIT_TABLE

U7800

P650839A0D

PBGA

(5 OF 10)

VREGVR4

D2

ILIMVR4

D4

DDRID

E3

DDR_VTT_CTRL

B5

PGVR4

C2 D5

ENVR4

CRITICAL

(OD)

PGNDVR4

A4

VBSTVR4

DRVHVR4

SWVR4

DRVLVR4

FBVR4+ FBVR4-

B3B4

A2 A3 A5

C3

P1V2_VBST

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

P1V2_DRVH P1V2_SW P1V2_DRVL

P1V2S3_FB_P P1V2S3_FB_N

100

R7902

0

1 2

5%

1/20W

MF

201

MIN_LINE_WIDTH=0.0900 GATE_NODE=TRUEDIDT=TRUEMIN_NECK_WIDTH=0.0520

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 SWITCH_NODE=TRUEDIDT=TRUE

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUE

1

2

P1V2_VBST_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

R7903

0

5% 1/20W MF 201

DIDT=TRUE

1

R7904

10

5% 1/20W MF 201

2

C7904

0.1UF

1 2

20% 16V

X6S-CERM

0201

P1V2S3_FB_R_P

PPBUS_HS_CPU

P1V2_DRVH_R

DIDT=TRUE GATE_NODE=TRUE

R7905

1

1 2

5%

1/20W

MF

201

R7906

0

1 2

5% 1/16W MF-LF

402

P1V2_DRVL_R

DIDT=TRUE GATE_NODE=TRUE

U7900

CSD58873Q3D

3

TG

4

TGR

5

BG

Q3D

9

VIN

VSW

PGND

1

DIDT=TRUE

6 7 8

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900

P1V2_PHASE

NOSTUFF

R7917

P1V2_SW_SNUB

DIDT=TRUE

C7917

0.001UF

NOSTUFF

X7R-CERM

C7900

33UF

20% 16V

TANT-POLY

CASE-B3

1

2.2

5% 1/10W MF-LF

603

2

1

10% 50V

2

0402

CRITICAL

1

C7901

33UF

2

TANT-POLY

CASE-B3

0.56UH-20%-19A-0.0065OHM

1 2

PILA062D-SM-COMBO

1

20% 16V

2

L7900

1

C7902

2.2UF

20% 25V

2

X6S-CERM 0402

PP1V2_S3_REG_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.2V

53

ISNS_CPUDDR_P

OUT

ISNS_CPUDDR_N

OUT

XW7904

1 2

1

C7903

2.2UF

20% 25V

2

X6S-CERM 0402

OMIT

R7918

0.005

1%

1/3W

MF

0306-SHORT

1 2 3 4

SM

1

C7905

270UF

20% 2V

2

TANT CASE-B

C7906

270UF

20%

2V

TANT

CASE-B

5G DESENSE

20%

2V

ELEC

1

2 3

C7908

220UF

SM-COMBO

1

2

C7907

220UF

20% 2V

23

ELEC SM-COMBO

1

C7921

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

2.4G DESENSE

1

C7913

10UF

20% 4V

2

X6S 0402

C7914

10UF

20% X6S

0402

CRITICAL

1

2

1

4V

2

C7922

12PF

5% 25V NP0-C0G 0201

PP1V2_S3

Vout = 1.2V IccMax = 8.21A

F = 600kHz

D

78 100

C

PP1V2_S3

100

C7935

10UF

20%

4V

X6S

0402

P1V2S3_FB_R_N

1 2

XW7903

SM

C

0.6V VTT - V13 (Banjo#1 LDO1)

OMIT_TABLE

U7800

1

C7930

10UF

2

20%

4V

X6S

0402

1

2

XW7931

SM

1 2

PMIC_VINLDO1S

A6

VINLDO1_0

B6

VINLDO1_1

F9

VINLDO1S

P650839A0D

PBGA

(9 OF 10)

CRITICAL

VOUTLDO1_0 VOUTLDO1_1

A8 B8

XW7930

SM

1

C7931

15UF

20% 2V

2

X6S

1 2

0402

1

C7932

15UF

20% 2V

2

X6S 0402

1

C7933

15UF

20% 2V

2

X6S 0402

1

C7934

15UF

20% 2V

2

X6S 0402

1

C7936

15UF

20% 2V

2

X6S 0402

1

C7937

15UF

20% 2V

2

X6S 0402

PP0V6_S0_DDRVTT

Vout = 0.6V IccMax = 0.512A

100

B

A

0.95V VCCIO - V6 (Banjo#1 VR3)

OMIT_TABLE

U7800

P650839A0D

XW7964

SM

PPBUS_HS_CPU

75 100

1 2

PVCCIO_ILIM_LS

7.5K

1%

1/20W

MF

201

1

77

OUT

74

2

IN

PVCCIO_PGOOD PVCCIO_EN PVCCIO_FB_N

R7961

Calculated OCP: min=3.95A, typ=7.38A, max=13.3A

VINVR3

D10

ILIMVR3HS

C9

ILIMVR3LS

B9

PGVR3

E9 D7

ENVR3

PBGA

(4 OF 10)

CRITICAL

PGNDVR3

A10

VBSTVR3

DRVHVR3

SWVR3

DRVLVR3

FBVR3+ FBVR3-

B11G9

PVCCIO_VBSTPMIC_VINVR3

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

A12

PVCCIO_DRVH

A11

PVCCIO_SW

A9

PVCCIO_DRVL

C10

PVCCIO_FB_P

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUEDIDT=TRUE

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUEDIDT=TRUE

R7962

0

5%

1/20W

MF

201

PGNDLDO1_1

PGNDLDO1_0

A7

B7

FBLDO1

D8

PVTT_FB

R7930

10

1 2

5%

1/20W

MF

201

PVTT_FB_R

CRITICAL

1

C7940

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE

CRITICAL

1

C7941

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

5G DESENSE

B

PPBUS_HS_CPU

75 100

1

C7961

2.2UF

20% 25V

2

X6S-CERM 0402

L7960

1UH-20%-11A-0.0127OHM

1 2

IHLP2020BD-PIHA052D-COMBO

C7969

0.001UF

NOSTUFF

10% 50V

X7R-CERM

0402

20% 16V

1

2

2.2

5% 1/10W MF-LF

603

1

2

C7960

PVCCIO_VBST_R

MIN_LINE_WIDTH=0.0900

1

R7964

0

5% 1/20W MF 201

2

10

5%

1/20W

MF

201

1

2

1

2

R7963

MIN_NECK_WIDTH=0.0520 DIDT=TRUE

1

C7963

0.1UF

20% 16V

2

X6S-CERM 0201

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

U7960

CSD58889Q3D

3

TG

4

TGR

5

BG

8

IN

8

IN

Q3D

9

VIN

VSW

PGND

1

DIDT=TRUE MIN_NECK_WIDTH=0.2000

6

MIN_LINE_WIDTH=0.6000

7 8

PVCCIO_PHASE

NOSTUFF

33UF

TANT-POLY

CASE-B3

R7969

PVCCIO_SW_SNUB

DIDT=TRUE

1

2

1

2

C7962

2.2UF

20% 25V X6S-CERM 0402

C7964

10UF

20%

4V

X6S

0402

CRITICAL

1

C7970

12PF

5% 25V

2

NP0-C0G 0201

5G DESENSE2.4G DESENSE

PPVCCIO_S0_CPU

20%

4V

X6S

0402

1

2

1

C7966

220UF

20% 2V

23

ELEC SM-COMBO

1

C7967

220UF

20% 2V

23

ELEC SM-COMBO

Vout = 0.95V IccMax = 3.1A

1

C7965

10UF

2

CRITICAL

1

C7971

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

100

F = 500kHz

SYNC_DATE=12/03/2015SYNC_MASTER=J79_JSHAO

PAGE TITLE

A

PMIC-1 1.2V 0.6V VCCIO

DRAWING NUMBER SIZE

BOM_COST_GROUP=PLATFORM POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

79 OF 145

SHEET

75 OF 119

D

8 7 5 4 2 1

36

345678

2 1

D

1V - V11 (Banjo#1 VR1)

76 75 74

Calculated OCP: min=3.98A, typ=7.42A, max=13.66A

PP5V_PMICLDO

C8016

1%

1/20W

MF

201

1

77

77 78

2

R8000

6.04K

1UF

20% 10V

X6S-CERM

0201

OUT

IN

1

2

P1VSUS_ILIM

P1VSUS_PGOOD P1V0PCH_PGOOD

OMIT_TABLE

U7800

P650839A0D

PBGA

(2 OF 10)

VREGVR1

CRITICAL

L9

ILIMVR1

M9

PGVR1

M12 J9

ENVR1

PGNDVR1

N10

VBSTVR1

DRVHVR1

SWVR1

DRVLVR1

FBVR1+ FBVR1-

M11M10

N12 N11 N9

K10

P1VS4_VBST

MIN_NECK_WIDTH=0.0520

P1VS4_DRVH P1VS4_SW P1VS4_DRVL

P1VS4_FB_P P1VS4_FB_N

DIDT=TRUEMIN_LINE_WIDTH=0.0900

1

R8002

0

5% 1/20W MF 201

2

P1VS4_VBST_R

1

R8001

0

5% 1/20W MF 201

2

1

R8003

10

5% 1/20W MF 201

2

MIN_NECK_WIDTH=0.0520MIN_LINE_WIDTH=0.0900 DIDT=TRUE

1

C8003

0.1UF

20% 16V

2

X6S-CERM 0201

GATE_NODE=TRUEDIDT=TRUEMIN_NECK_WIDTH=0.0520MIN_LINE_WIDTH=0.0900

DIDT=TRUEMIN_NECK_WIDTH=0.0520MIN_LINE_WIDTH=0.0900 SWITCH_NODE=TRUE

GATE_NODE=TRUEMIN_NECK_WIDTH=0.0520MIN_LINE_WIDTH=0.0900 DIDT=TRUE

P1VS4_FB_R_P P1VS4_FB_R_N

100

PPBUS_G3H

U8000

CSD58889Q3D

3

TG

4

TGR

5

BG

Q3D

9

VIN

VSW

PGND

C8000

2.2UF

20% 25V

X6S-CERM

0402

PP1V0_SUS

1

C8002

33UF

20% 16V

2

TANT-POLY CASE-B3

CRITICAL

1

C8010

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C8011

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CRITICAL

1

C8017

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C8018

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

20% 25V

0402

1

2

1

C8001

2.2UF

2

X6S-CERM

101

D

1

OMIT

R8004

0.005

DIDT=TRUE

6 7 8

MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.6000

NOSTUFF

R8009

2.2

1/10W MF-LF

5%

603

1UH-20%-11A-0.0127OHM

IHLP2020BD-PIHA052D-COMBO

1

2

P1VS4_SW_SNUB

DIDT=TRUE

NOSTUFF

L8000

1 2

10% 50V

0402

1

2

C8009

0.001UF

X7R-CERM

PP1V_PCH_REG_RP1VS4_PHASE

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.0V

53

ISNS_1V0_P

OUT

ISNS_1V0_N

OUT

XW8003

SM

1 2

1%

1/3W

MF

0306-SHORT

1 2 3 4

C8004

10UF

20%

4V

X6S

0402

20%

4V

X6S

0402

1

2

1

C8005

10UF

2

5G DESENSE2.4G DESENSE 2.4G DESENSE 5G DESENSE

1

C8006

220UF

20% 2V

23

ELEC SM-COMBO

1

C8007

220UF

20% 2V

23

ELEC SM-COMBO

Vout = 1.0V IccMax = 3.29A F = 500kHz

C

PP3V3_S5

101

C8024

2.2UF

20% 25V

X6S-CERM

0402

XW8004

SM

PP1V8_SUS

CRITICAL

1.8V - V8 (Banjo#1 VR2)

OMIT_TABLE

U7800

P650839A0D

PBGA

(3 OF 10)

F12 F13

VINVR2_0 VINVR2_1

SWVR2_0 SWVR2_1

CRITICAL

76 75 74

1

C8020

2.2UF

2

X6S-CERM

20% 25V

0402

1

2

1

C8021

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

PP5V_PMICLDO

1

C8025

1UF

20% 10V

2

X6S-CERM 0201

77 74

77

OUT

IN

P1V8SUS_PGOOD PM_SLP_SUS_L

E13

VREGVR2

E12

PGVR2

F11 E10

ENVR2

PGNDVR2_0

PGNDVR2_1

G12

G13

FBVR2+ FBVR2-

H12

P1V8SUS_SW

H13

G10

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE SWITCH_NODE=TRUE

P1V8SUS_FB_P P1V8SUS_FB_N

R8020

100

5%

1/20W

MF

201

NOSTUFF

1

2

R8029

1

R8021

10

5% 1/20W MF 201

2

0.47UH-20%-4.0A-28MOHM

1

2.2

5% 1/10W MF-LF

603

2

P1V8SUS_FB_R_P

L8020

1 2

PIFE25201B-SM

DIDT=TRUE

P1V8S3_SW_SNUB

C8029

0.001UF

NOSTUFF

10% 50V

X7R-CERM

0402

XW8021

1 2

PP1V8_SUS_REG_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V

53

1

2

SM

ISNS_1V8_SUS_P

OUT

ISNS_1V8_SUS_N

OUT

P1V8SUS_FB_RC

OMIT

R8024

0.005

1%

1/3W

MF

0306-SHORT

1 2 3 4

R8025

100

5%

1/20W

MF

201

2.4G DESENSE

1

C8022

100UF

20%

6.3V

2

TANT-POLY CASE-A3-LLP

1

C8023

100UF

20%

6.3V

2

TANT-POLY CASE-A3-LLP

Vout = 1.8V IccMax = 0.7A F = 2MHz

2

1

C8030

12PF

5% 25V

2

NP0-C0G 0201

5G DESENSE

1

C8026

20UF

20%

6.3V

2

CERM-X5R 0402

CRITICAL

1

C8031

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

100

1

C8027

20UF

20%

6.3V

2

CERM-X5R 0402

C

B

A

1.0V PCH CORE - V11 (Banjo#1 VR5)

0.7V LPM

XW8054

SM

PPBUS_G3H

76 100

P1V0PCH_ILIM_LS

1%

1/20W

MF

201

1

77

OUT

77

2

IN

R8007

7.68K

Calculated OCP: min=3.98A, typ=7.42A, max=13.4A

1 2

PMIC_VINVR5

P1V0PCH_PGOOD

P3V3SUS_PGOOD

VINVR5

K5

ILIMVR5HS

L5

ILIMVR5LS

M4

PGVR5

M2

ENVR5

OMIT_TABLE

U7800

P650839A0D

PBGA

(6 OF 10)

CRITICAL

PGNDVR5

N3

VBSTVR5

DRVHVR5

SWVR5

DRVLVR5

FBVR5+ FBVR5-

M3L7

P1V0PCH_VBST

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

M1

P1V0PCH_DRVH

N2

P1V0PCH_SW

N4

P1V0PCH_DRVL

G4

P1V0PCH_FB_P

L4

P1V0PCH_FB_N

R8051

0

1 2

5%

1/20W

MF

201

1

R8052

0

5% 1/20W MF 201

2

P1V0PCH_VBST_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

1

R8053

10

5% 1/20W MF 201

2

P1V0PCH_FB_R_P P1V0PCH_FB_R_N

PPBUS_G3H

76 100

C8053

0.1UF

1 2

20% 16V

X6S-CERM

0201

GATE_NODE=TRUEDIDT=TRUEMIN_NECK_WIDTH=0.0520MIN_LINE_WIDTH=0.0900

SWITCH_NODE=TRUEDIDT=TRUEMIN_NECK_WIDTH=0.0520MIN_LINE_WIDTH=0.0900

GATE_NODE=TRUEDIDT=TRUEMIN_NECK_WIDTH=0.0520MIN_LINE_WIDTH=0.0900

U8050

CSD58889Q3D

3

TG

4

TGR

5

BG

Q3D

9

VIN

VSW

PGND

C8028

0.01UF

X5R-CERM

P1V8SUS_FB_R_N

1

C8014

2.2UF

20% 25V

2

X6S-CERM 0402

20% 16V

1

2

C8013

33UF

TANT-POLY

CASE-B3

1

C8015

2.2UF

20% 25V

2

X6S-CERM 0402

L8050

DIDT=TRUE

6 7 8

MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.6000

P1V0PCH_PHASE

NOSTUFF

R8059

2.2

5% 1/10W MF-LF

603

1

2

P1V0PCH_SW_SNUB

DIDT=TRUE

1UH-20%-11A-0.0127OHM

IHLP2020BD-PIHA052D-COMBO

1 2

C8059

0.001UF

NOSTUFF

X7R-CERM

10% 50V

0402

1

2

P1V0PCH_REG_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.85V

55

ISNS_PCHPRIMCORE_P

OUT

ISNS_PCHPRIMCORE_N

OUT

1 2

XW8020

SM

OMIT

R8054

0.005

1%

1/3W

MF

0306-SHORT

XW8053

SM

1 2

XW8052

SM

1

10% 25V

2

0201

12 34

20%

4V

X6S

0402

1

2

C8055

10UF

20%

4V

X6S

0402

C8054

10UF

BOM_COST_GROUP=PLATFORM POWER

B

CRITICAL

1

C8060

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE

5G DESENSE

PPVCCPRIMCORE_SUS_PCH

1

2

1

C8056

220UF

20% 2V

23

ELEC SM-COMBO

PAGE TITLE

1

C8057

220UF

20% 2V

23

ELEC SM-COMBO

CRITICAL

1

C8061

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

Vout = 1.0V

IccMax = 2.58A

F = 500kHz

100

SYNC_DATE=12/03/2015SYNC_MASTER=J79_JSHAO

A

PMIC-1 1V 1.8V VCCPCH

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

80 OF 145

SHEET

76 OF 119

D

8 7 5 4 2 1

36

345678

2 1

KEEP THESE RAILS ON WHEN USING XDP

PP3V3_SUS

17 77 101

D

C

74 49 48

SUS Enables

104 74 14

104 48 19 14

104 77 74 48 43 19 14

104 92 80 74 73 48 26 19 14

S5 Enables

R8110

SMC_PM_G2_EN

MAKE_BASE=TRUE

PM_SLP_SUS_L

MAKE_BASE=TRUE

1 2

S4 Enables

PM_SLP_S5_L

MAKE_BASE=TRUE

S3 Enables

PM_SLP_S4_L

MAKE_BASE=TRUE

S0 Enables

PM_SLP_S3_L

MAKE_BASE=TRUE

0

5%

1/20W

MF

201

PMIC_EN_P3V3S5

PM_SLP_SUS_L PM_SLP_SUS_L

PM_SLP_S5_L PM_SLP_S5_L PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L PM_SLP_S3_L PM_SLP_S3_L

76

78

77

78

77

75

77

78

74

101

74 72

77 76

74 77

74

74 77

74 73 48

PP3V3_PMICLDO

MAKE_BASE=TRUE

PP5V_S4

P5VS4_PGOOD

MAKE_BASE=TRUE

P1V0PCH_PGOOD

MAKE_BASE=TRUE

GND

MAKE_BASE=TRUE

P3V3SUS_PGOOD

MAKE_BASE=TRUE

GND

MAKE_BASE=TRUE

ALL_SYS_PWRGD

MAKE_BASE=TRUE

S5_PWRGD

72 74

PP3V3_PMICLDO

PP5V_S4

P5VS4_PGOOD

P1V0PCH_PGOOD

GND

P3V3SUS_PGOOD

GND

ALL_SYS_PWRGD

S5_PWRGD

MAKE_BASE=TRUE

74

76 78

75

76

74

67

48

I14

I17

I19

I28

I29

74 67

CPUVR_PGOOD

75

PVCCIO_PGOOD

P1VSUS_PGOOD

76

76 74

P1V8SUS_PGOOD

77 76

P1V0PCH_PGOOD

P2MM

SM

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

P2MM

SM

1

PP

PP8100

PP8101

PP8102

PP8106

PP8107

77 17

104 77 74 48 43 19 14

77 17

77 74

IN

XDP_PRESENT_L

PM_SLP_S4_L

PP3V3_SUS

17 77 101

IN

XDP_PRESENT_L

PM_SLP_S0S3_L

XDP:YES

C8192

0.1UF

10% 10V

X5R-CERM

0201

XDP:NO

R8193

0

1 2

5%

1/20W

MF

201

XDP:YES

C8194

0.1UF

10% 10V

X5R-CERM

0201

XDP:NO

R8195

0

1 2

5%

1/20W

MF

201

1

2

(INV)

1

2

(INV)

XDP:YES

U8192

165

3

74AUP1T97GM

SOT886

4

P1V0S3_EN

XDP:YES

2

1

R8192

100K

5% 1/20W MF 201

2

XDP:YES

(S4# OR XDP)

78

OUT

D

U8194

1

5

6

3

2

74AUP1T97GM

SOT886

4

P1VS0SW_EN_RC

XDP:YES

1

R8194

100K

5% 1/20W MF 201

2

(S3# AND S0# OR XDP)

77

OUT

C

77

77 74

IN

S0i Enables

P1VS0SW_EN_RC

MAKE_BASE=TRUE

IN

PM_SLP_S0S3_L

MAKE_BASE=TRUE

P1VS0SW_EN_RC

PM_SLP_S0S3_L

OUT

78

48 17 14

PM_RSMRST_L

MAKE_BASE=TRUE

GND

74 77

MAKE_BASE=TRUE

SSD_PWR_REQ

77

MAKE_BASE=TRUE

PM_RSMRST_L

SSD_PWR_REQ

74

IN

PP3V3_G3H

100

10% 10V

0201

1

2

U8190

6

2

1

NC

74LVC1G32

SOT891

4

35

PM_EN_PVXS5

MAKE_BASE=TRUE

PM_EN_PVXS5

77

C8190

0.1UF

88 84

PMIC_EN_P3V3S5

77

SSD_PWR_REQ

IN

X5R-CERM

B

A

77

PM_EN_PVXS5

R8165

100

5%

1/20W

MF

201

NO STUFF

P3V3S5_EN_RD

NC

1

R8190

100K

5% 1/20W MF 201

2

B

R8160

0

77

R8162

0

1 2

5%

1

2

1/20W

MF

201

D8164

SM-201

RB521ZS-30

NO STUFF

P3V3S5_EN

AK

1

C8155

1UF

10% 25V

2

X6S-CERM 0402

OUT

NO STUFF

72

77

PM_SLP_S5_L

R8164

100

1/20W

201

NO STUFF

P5VS4_EN_RD

1

5%

MF

2

R8163

0

1 2

5%

1/20W

MF

201

D8163

SM-201

AK

RB521ZS-30

NO STUFF

P5VS4_EN

1

C8154

1UF

10% 25V

2

X6S-CERM 0402

NO STUFF

OUT

72

77

PM_SLP_S3_L

R8167

100

1/20W

201

NO STUFF

P5VS0_EN_RD

5%

MF

1

2

R8166

0

1 2

5%

1/20W

MF

201

D8165

SM-201

AK

RB521ZS-30

NO STUFF

P5VS0_EN

1

C8156

1UF

10% 25V

2

X6S-CERM 0402

NO STUFF

OUT

78

BOM_COST_GROUP=PLATFORM POWER

PM_EN_PVXS5

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

1 2

5%

1/20W

MF

201

P5VS5_EN

OUT

72

PMIC-1 Aliases & TPs

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

81 OF 145

SHEET

77 OF 119

SYNC_DATE=07/17/2015SYNC_MASTER=J79_SILUCHEN

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

77

PP3V3_S5

57 101

78 50

3.3V SUS Switch

PP3V3_S5

101

77

IN

PM_SLP_SUS_L

C8200

1.0UF

20%

6.3V X5R

0201-1

1

2

SLG5AP1569V

2

VIN

1

ON

3.3V S4 Switch

PP3V3_S5

101

R8209

0

PM_SLP_S5_L

IN

1 2

5%

1/20W

MF

201

P3V3S4_EN_R

C8209

0.1UF

10% 16V

X5R-CERM

0201

NOSTUFF

1

C8204

4700PF

2

3.3V S0 Switch

PP3V3_S5

101

C8205

P3V3S0_RAMP

C8206

4700PF

10% 10V X7R 201

1

2

77

PM_SLP_S3_L

IN

5V S0 Switch (Cumulus vs Kona)

PP5V_S4

101

P5VS4_FET_RAMP

CUMULUS_IPD

C8207

4700PF

10% 10V X7R 201

77

1

2

IN

P5VS0_EN

3.3V Sensor Switch

U8210

TPS22934

DSBGA

LOADISNS

VIN

ON

VOUT

CRITICAL

GND

B1

IN

SMC_SENSOR_PWR_EN

LOADISNS

C8210

1.0UF

6.3V

0201-1

20%

X5R

A2

B2

1

2

U8200

STDFN

CRITICAL

GND

4

C8203

P3V3S4_RAMP

1

10% 10V

2

X7R 201

1

1UF

10% 10V

2

X5R 402

CUMULUS_IPD

7 3

2 5

A1

PP3V3_S4SW_SNS_FET_R

VOUT

1UF

10% 10V X5R 402

3

Part

Type

R(on) @ 3.3V

Current

1

2

1

VDD

U8203

SLG5AP1445V

7 3

CAP

2 5

ON S

1

VDD

TDFN8

CRITICAL

GND

8

U8205

SLG5AP1445V

7 3

CAP

2 5

ON S

TDFN8

CRITICAL

GND

8

CUMULUS_IPD

1

VDD

U8209

SLG5AP1453V

CAP

ON S

VOLTAGE=3.3V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

TDFN

D

CRITICAL

GND

8

U8210

Part TPS22934

Type

R(on) @ 3.6V

Current

EDP: 416mA

PP3V3_SUS

U8200

SLG5AP1569V

Load Switch

36.4 mOhm Typ 46 mOhm Max

1A Max

D

Part

Type

R(on) @ 4A

Current

1

C8208

0.1UF

10% 16V

2

X5R-CERM 0201

EDP: 16mA

2.4G DESENSE

LOADISNS

R8210

0

1 2

5% 1/16W MF-LF

402

Load Switch

63 mOhm Typ 77 mOhm Max

1A Max

101

PP3V3_S4

EDP: 0.04 A

Part

Type

R(on) @ 4A

Current

U8205

SLG5AP1445V

Load Switch

7.8 mOhm Typ TBD mOhm Max

4A Max

PP5V_S0

101

CRITICAL

1

C8216

12PF

5% 25V

2

NP0-C0G 0201

PP3V3_S4SW_SNS

101

U8203

SLG5AP1445V

Load Switch

7.8 mOhm Typ TBD mOhm Max

4A Max

PP3V3_S0

EDP: 0.04 A

Part

Type

R(on)

Current

CRITICAL

1

C8217

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

5G DESENSE

PP3V3_S5

101

1

C8289

100PF

5% 25V

2

C0G 0201

101

S3_STATE:YES

C8215

4700PF

10% 10V X7R 201

101

C8219

4700PF

U8209

SLG5AP1443V

Load Switch

17 mOhm Typ 19 mOhm Max

2.5A

C8222

4700PF

101

P1V0SUSFUSE_RAMP

76

IN

77

1

10% 10V

2

X7R 201

P1V0PCH_PGOOD

PP3V3_S5

77

IN

PP3V3_S5

101

1

2

77

74

PP3V3_S5

1

2

10% 10V X7R 201

PP3V3_SUS

101

VCCPLLOC:S0G

1.0V SUS FUSE Switch

1

C8288

0.1UF

10% 16V

2

X5R-CERM 0201

1.8V S4 LDO

1UF

10% 10V X5R 402

1

2

1

3

C8211

PM_SLP_S5_L

1.8V S3 Switch

S3_STATE:YES

1UF

10% 10V X5R 402

1

2

7 3

CAP

2 5

ON S

IN

C8214

P1V8S3_RAMP

P1V8S3_EN

1.8V S0 Switch

1UF

10% 10V X5R 402

1

2

7 3

2 5

77

P1V8S0_RAMP

IN

C8218

PM_SLP_S3_L

1.2V S0 SW Switch

VCCPLLOC:S0G

1UF

10% 10V X5R 402

1

2

SLG5AP1453V

7 3

CAP

2 5

ON S

D

S

C8221

P1V2S0SW_RAMP

IN

PM_SLP_S0S3_L

1

VDD

U8288

SLG5AP1635V

7 3

CAP

2 5

ON

STDFN

GND

8

U8212

NCP703SN18TG

TSOP5

GND

2

S3_STATE:YES

1

VDD

OUTIN

NC1EN

U8215

SLG5AP1453V

TDFN

GND

8

1

VDD

D

U8218

SLG5AP1453V

CAP

ON S

TDFN

GND

8

VCCPLLOC:S0G

1

VDD

U8220

TDFN

GND

8

PP1V0_SUS

D

R8288

1/20W

PP1V0_SUSFUSE

VOLTAGE=1.0V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

5

4

D

1

0

5%

MF

201

2

EDP: TBD

1.0V SUS SW Switch

PP3V3_SUS

101

PP1V0_SUS

101

NC

PP1V8_S4

EDP: 0.020 A

1

C8212

1UF

10% 10V

2

X5R 402

100

14

IN

NOSTUFF

R8280

PCH_HSIO_PWR_EN

10K

5%

1/20W

MF

201

1

2

NOSTUFF

C8280

1UF

U8215

Part

Type

R(on) @ 5.3A HSIO has turn-on requirement of

Current

PP1V8_SUS

S3_STATE:NO

R8281

0

5%

1/20W

MF

201

PP1V8_S3

Part

Type

R(on) @ 5.3A

Current

PP1V8_SUS

PP1V8_S0

Part

Type

R(on) @ 5.3A

Current

SLG5AP1453V

Load Switch

7.8 mOhm Typ

9.6 mOhm Max

5.3A Max

PMEG3010EB/S500

1

2

PMEG3010EB/S500

EDP: 0.550 A

U8218

SLG5AP1453V

Load Switch

7.8 mOhm Typ

9.6 mOhm Max

5.3A Max

EDP: 0.140 A

U8220

SLG5AP1453V

Load Switch

7.8 mOhm Typ

9.6 mOhm Max

5.3A Max

D8215

SOD523

AK

D8216

SOD523

AK

100

PP1V2_S3

100

75 100

<0.1V/uS ramp rate and <65uS from EN to 95% (1.05V)

1.0V S3 Switch

PP3V3_S5

101

P1V0S3_RAMP

S3_STATE:YES

1

C8284

100PF

5% 25V

2

C0G 0201

77

IN

P1V0S3_EN

1.0V S0 SW Switch

PP3V3_S5

101

1

C8286

0.1UF

10% 16V

2

X5R-CERM 0201

P1V0S0SW_RAMP

1

C8287

100PF

5% 25V

2

C0G 0201

77

IN

P1VS0SW_EN_RC

(CURRENTLY DE-FEATURED)

9 5

ON

1

10% 10V

2

X5R 402

S3_STATE:YES

1

C8283

0.1UF

10% 16V

2

X5R-CERM 0201

7 3

CAP

2 5

ON

5V Sensor Switch

PP1V2_S3

PP1V2_S0SW

101

NOSTUFF

12 8

R8220

1

VCCPLLOC:S3

0

5%

1/20W

MF

201

2

EDP: 0.260 A

Part

Type

R(on) @ 25C

Current

Ton Total

R(discharge)

U8288

SLG5AP1635V

Load Switch

20 mOhm Typ 28 mOhm Max

2.5A Max

39us max @ 1V

100

LOADISNS

C8223

1000PF

10% 25V X7R

0201

300 Ohm Max

PP5V_S4

101

P5V_S4SW_SNS_FET_RAMP

78 50

1

2

SMC_SENSOR_PWR_EN

IN

1

VDD

U8213

SLG5AP1443V

7 3

CAP

2 5

ON S

TDFN

CRITICAL

LOADISNS

GND

8

NOSTUFF

1

VDD

U8280

SLG5AP1646V

TDFN

CRITICAL

GND

8

1

VDD

2

D

3

D

S

7

S

S3_STATE:YES

U8283

SLG5AP1635V

7 3

CAP

2 5

ON

1

VDD

STDFN

GND

8

U8286

SLG5AP1635V

STDFN

GND

8

LOADISNS

C8213

1.0UF

0201-1

D

20%

6.3V X5R

PP5V_S4SW

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

D

S

Part

Type

R(on) @ 25C

Current 2.5A Max

Ton Total

1

2

D

S

Part

Type

R(on) @ 25C

Ton Total

PP1V0_S3

PP1V0_S0SW

101

Apple Inc.

R

2

XW8280

SM

1

PP1V0_SUSSW

EDP: 2.653A

U8280

Part

Type

R(on) @ 4V Vgs

Current 6A Max

PP1V0_SUS

PP1V0_S3

U8283

39us max @ 1V

SLG5AP1646V

Load Switch

8.5 mOhm Typ

9.8 mOhm Max

R8282

1/20W

EDP: 0.240 A

SLG5AP1635V

Load Switch

20 mOhm Typ 28 mOhm Max

2.5A MaxCurrent

EDP: 0.04 A

5%

MF

201

1

S3_STATE:NO

0

2

U8286

SLG5AP1635V

Load Switch

20 mOhm Typ 28 mOhm Max

39us max @ 1V

U8213

Part

Type

R(on)

Current

BOM_COST_GROUP=PLATFORM POWER

SLG5AP1443V

Load Switch

17 mOhm Typ 19 mOhm Max

2.5A

Power FETs

DRAWING NUMBER SIZE

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

82 OF 145

SHEET

78 OF 119

101

9.0.0

101

D

C

B

SYNC_DATE=03/14/2016SYNC_MASTER=J79_JSHAO

A

D

8 7 5 4 2 1

36

Page Notes

345678

2 1

D

C

Power aliases required by this page:

- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)

- =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT)

PPBUS_G3H

100

740S0159

CRITICAL

F8400

3AMP-32V

1 2

79

0603

PPVIN_S0SW_LCDBKLT_F

52

ISNS_LCDBKLT_P

OUT

ISNS_LCDBKLT_N

OUT

R8400

0.025

1% 1W MF

0612-1

107S00034

12 34

79

PPVIN_S0SW_LCDBKLT_R

1

2

PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW

5

IN

EDP_BKLT_EN

C8400

1000PF

10% 16V X7R-1 0201

R8442

1 2

GND_BKLT_SGND

79

1

R8401

80.6K

1% 1/16W MF-LF 402

2

1

R8402

63.4K

1% 1/16W MF-LF 402

2

1

2

0

5%

1/20W

MF

0201

CRITICAL

Q8400

FDC638APZ_SBMS001

SSOT6-HF

4

3

6 5 2 1

LCDBKLT_EN_L

PP5V_S0

79 101

R8444

PLACE_NEAR=U8400.5:5MM

GND_BKLT_SGND

79

C8440

R8440

1M

5% 1/20W MF 201

BKLT_SD

79

BKLT_SENSE_OUT

BKLT_EN_R

NO STUFF

1

C8442

33PF

5% 25V

2

NPO-C0G 0201

0

5% 1/16W MF-LF

402

1UF

10% 10V X5R 402

NOSTUFF

1

C8401

0.001UF

10% 50V

2

CERM 402

1

2

1

2

79

PPVIN_S0SW_LCDBKLT

MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=12.9V MAKE_BASE=TRUE

1

R8445

0

5% 1/16W MF-LF 402

2

79

PP5V_S0_BKLT_A

79

PP5V_S0_BKLT_D

1

C8441

PLACE_NEAR=U8400.18:5MM

1UF

10% 10V

2

X5R 402

U8400

LP8548B1SQ_-04

11

SD

9

VSENSE_N

10

VSENSE_P

19

SENSE_OUT

17

EN

12

PWM_KEYB

15

SCL

(IPU)

16

(IPU)

SDA

CRITICAL

18

5

VDDA

VDDD

LLP

ISET_KEYB

SW SW FB GD

KEYB1 KEYB2

SW2 FB2

1

C8410

4.7UF

10% 25V

2

X6S-CERM 0603

PLACE_NEAR=L8410.1:5MM

DIDT=TRUE

SWITCH_NODE=TRUE

VOLTAGE=55V MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=2.0000

2

LCDBKLT_SW

1 21

LCDBKLT_FB

4

LCDBKLT_FET_DRV

20

NC

13

NC

14

NC

6

NC

8

NC

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=5V

GATE_NODE=TRUE

DIDT=TRUE

15UH-20%-1.9A-0.24OHM

1

C8411

4.7UF

10% 25V

2

X6S-CERM 0603

PLACEMENT_NOTE:

SANDWICH C8210 AND C8211

PLACE_NEAR=L8410.1:5MM

79

LCDBKLT_FET_DRV_R

PLACE_NEAR=L8410.1:5MM

1

R8433

10

1% 1/16W MF-LF 402

2

PLACE_NEAR=Q8401.5:3MM

CRITICAL

L8410

1 2

PIME062D-SM

152S00253

1

C8412

0.1UF

10% 25V

2

X5R 402

4

PLACE_NEAR=L8410.2:3MM

371S0704 or 371S00077 (Combo)

SOD123-COMBO

PMEG10020ELR-DFLS2100

79

PPVIN_SW_LCDBKLT_SW

5

CRITICAL

Q8401

SI7812DN

PWRPK-1212-8

1 2 3

PLACE_NEAR=U8400.1:3MM

CRITICAL

D8410

A K

2

XW8410

PLACE_NEAR=D8410::2MM

SM

1

PLACE_NEAR=D8410.K:5MM

1

C8460

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

1

C8465

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

1

C8470

2.2UF

10% 100V

2

X5R 1206

1

R8431

LCDBKLT_TB_XWR

18.2K

1% 1/16W MF-LF 402

2

1

R8432

150K

1% 1/16W MF-LF 402

2

PLACE_NEAR=D8410.K:5MM

1

C8461

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

1

C8466

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

1

C8471

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

1

2

PLACE_NEAR=D8410.K:5MM

1

2

PLACE_NEAR=D8410.K:5MM

1

2

NOSTUFF

1

C8430

100PF

5% 100V

2

C0G-CERM 0603

C8462

2.2UF

10% 100V X5R 1206

C8467

2.2UF

10% 100V X5R 1206

C8472

2.2UF

10% 100V X5R 1206

PLACE_NEAR=D8410.K:5MM

1

C8463

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

1

C8468

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

1

C8473

2.2UF

10% 100V

2

X5R 1206

PLACE_NEAR=D8410.K:5MM

1

2

PLACE_NEAR=D8410.K:5MM

1

2

PLACE_NEAR=D8410.K:5MM

J79 DISPLAY

Vout = 46V Typ, 55V Max

Iout = 0.12A Typ, 0.15A Max

Fs = 625kHz Typ (+/- 7%)

PPVOUT_S0_LCDBKLT

C8464

2.2UF

10% 100V X5R 1206

C8469

2.2UF

10% 100V X5R 1206

PLACE_NEAR=D8410.K:5MM

1

C8474

12PF

5% 100V

2

C0G 0201

1

C8475

12PF

5% 100V

2

C0G 0201

104 80 79

D

C

B

PP5V_S0

79 101

1

R8452

1.8K

5% 1/20W MF 201

2

102

IN

102

BI

I2C ID DEDICATED.ONLY CONNECTS TO JERRY

I2C_BKLT_SCL

I2C_BKLT_SDA

BKLT_PWM_KEYB

1

R8447

10K

5% 1/20W MF 201

2

1

R8453

1.8K

5% 1/20W MF

2

201

PLACE_NEAR=U8400.15:10MM

R8450

1 2

R8451

0

1 2

5%

1/20W

MF

PLACE_NEAR=U8400.16:10MM

0201

1/20W

0201

0

5% MF

BKLT_SCL

BKLT_SDA

GND_SW

GND_SW2

7

23

24

XW8400

SM

1 2

GNDD

3

THRM

GNDA

22

PAD

25

GND_BKLT_SGND

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=0V

B

79

A

LINE WIDTHS

79

LCDBKLT_FET_DRV_R

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=5V

GATE_NODE=TRUE

DIDT=TRUE

PP5V_S0_BKLT_A

MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=5V

PP5V_S0_BKLT_D

MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=5V

BKLT_SD

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000

79

PPVIN_S0SW_LCDBKLT_F

MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT_R

MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=12.9V

PPVIN_S0SW_LCDBKLT

MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=12.9V

8 7 5 4 2 1

LCD BKLT LINE WIDTHSPBUS LINE WIDTHS

79

PPVIN_SW_LCDBKLT_SW

MIN_LINE_WIDTH=2.0000 MIN_NECK_WIDTH=0.2000 VOLTAGE=55V

SWITCH_NODE=TRUE

DIDT=TRUE

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1500 VOLTAGE=55V

79

SYNC_MASTER=J79_RUENJOU SYNC_DATE=09/09/2015

PAGE TITLE

LCD Backlight Driver

104 80 79

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=DISPLAY

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

36

051-00515

9.0.0

dvt-fab09-0

84 OF 145

79 OF 119

A

D

PP5V_S0

101

LCD PANEL INTERFACE (eDP) + Camera (MIPI)

345678

2 1

D

R8517

330

1 2

201

5% 1/20W

MF

R8515

150K

1 2

5%

1/20W

MF

201

PANEL_P5V_EN_D

LCD_PWR_SLEW

PANEL_P5V_EN

D8517

SC2

A K

DSF01S30SCAP

1

C8515

0.1UF

10% 10V

2

X5R-CERM 0201

R8518

330

1 2

2015%

1/20W

MF

CRITICAL

SLG5AP1443V

7 3

CAP

2 5

ON S

1

C8509

2200PF

10% 10V

2

X7R-CERM 0201

R8516

200K

1 2

1%

1/20W

MF

201

PANEL_P3V3_EN_D

1

VDD

U8500

TDFN

GND

8

PANEL_P3V3_EN

D8518

DSF01S30SCAP

D

SC2

AK

1

C8511

0.1UF

10% 10V

2

X5R-CERM 0201

1

C8516

0.47UF

10%

6.3V

2

CERM-X5R 0201

1

C8512

10UF

20% 10V

2

X5R-CERM 0402-7

LCD_PWR_SLEW_3V3

VOLTAGE=5V

PP5V_S0SW_LCD

PP3V3_S5

101

CRITICAL

SLG5AP1443V

7 3

CAP

2 5

ON S

1

C8513

2200PF

10% 10V

2

X7R-CERM 0201

1

VDD

U8501

TDFN

GND

8

D

106 104 80

OMIT

R8520

0.005

D

VOLTAGE=3.3V

PP3V3_S0SW_LCD_R

1

2

C8510

1.0UF

20% X5R

6.3V

0201-1

ISNS_LCDPANEL_P

54

ISNS_LCDPANEL_N

54

1/3W

0306-SHORT

1 2 3 4

NO_XNET_CONNECTION=1

1%

MF

PP3V3_S0SW_LCD

MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900 VOLTAGE=3.3V

106 104 80

BKLT_PWM_TCON2MLB

48 104

BKLT_PWM_MLB2TCON

5 104

MAKE_BASE=TRUE

BKLT_PWM_TCON2MLB

MAKE_BASE=TRUE

BKLT_PWM_MLB2TCON

Move to CSA 20

80

Move to CSA 92

80

J8500

20759-042E-02

F-ST-SM

C

104 80 66 59 50

IN

U8510 BYPASS

SMC_RESET_L

NO_STUFF

R8590

0

1 2

5% 1/20W

MF

0201

NO_STUFF

R8591

0

1 2

5%

MF 0201

NO_STUFF

1/20W

R8592

0

1 2

5%

MF 0201

1/20W

PANEL_FET_EN_DLYEDP_PANEL_PWR_EN

BUF_EDP_PANEL_PWR_EN

BUF_SMC_RESET_L

PANEL_FET_EN_DLY

80

57 100

PP3V3_G3H

CRITICAL

1

VDD

BUF_SMC_RESET_L DFR_DISP_PWR_EN DFR_DISP_SMC_RST_L

OUT

80 48

42

SLG4AP4998

80 5

IN

104 92 77 74 73 48 26 19 14

104 80 66 59 50

80 80 5

104 80

80 48

IN

EDP_PANEL_PWR_EN

PM_SLP_S3_L

SMC_RESET_L

2

EDP_PANEL_PWR_EN

PM_SLP_S3_L

12 9

SMC_RESET_INPUT_L

STQFN

PANEL_FET_EN_DLY

PANEL_PWR_EN_CONN

SMC_RESET_OUTPUT_L

X604_DISP_PWR_EN

X604_DISP_SMC_RST_L

U8510

GND

7

NC0 NC1

3

84

6

10

5

NC_U8510_5

11

NC_U8510_11

BUF_EDP_PANEL_PWR_EN

NO_TEST=1 NO_TEST=1

104 80

104 80 79

104 80

104 80 104 80

104 80

105 104 38

106 104 80

PPVOUT_S0_LCDBKLT

GND_VOID=TRUE

EDP_INT_AUX_N EDP_INT_AUX_P BUF_EDP_PANEL_PWR_EN

GND_VOID=TRUE GND_VOID=TRUE

EDP_INT_ML_N<0> EDP_INT_ML_P<0>

GND_VOID=TRUE GND_VOID=TRUE

EDP_INT_ML_N<1> EDP_INT_ML_P<1>

GND_VOID=TRUE GND_VOID=TRUE

EDP_INT_ML_N<2> EDP_INT_ML_P<2>

GND_VOID=TRUE GND_VOID=TRUE

EDP_INT_ML_N<3> EDP_INT_ML_P<3>

GND_VOID=TRUE GND_VOID=TRUE

MIPI_DATA_CONN_N MIPI_DATA_CONN_P

GND_VOID=TRUE GND_VOID=TRUE

MIPI_CLK_CONN_N MIPI_CLK_CONN_P

GND_VOID=TRUE

PP5V_S0SW_LCD

43 44

PWR

SIGNAL

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

PWR

45 46

PP3V3_S0SW_LCD

DP_INT_HPD

LCD_IRQ_L

BKLT_PWM_TCON2MLB BKLT_PWM_MLB2TCON

I2C_BKLT_SDA I2C_BKLT_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL

I2C_ALS_SDA I2C_ALS_SCL I2C_CAM_SCL I2C_CAM_SDA

PP5V_S0_ALSCAM_F

106 104 80

C

104 80 5

104 16

80

104 102

51 104

104 42

104 38 37

106 104 38

B

104 80 5

DP_INT_HPD

101

104 80

PP3V3_S0

NO_STUFF

EDP_INT_AUX_N

EDP_INT_AUX_P

NO_XNET_CONNECTION=1

1

R8503

1M

5% 1/20W MF 201

2

GND

47 48

49 50

51 52

MAKE_BASE=TRUE

5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

5

IN

EDP_INT_ML_P<0>

EDP_INT_ML_N<0>

EDP_INT_ML_P<1>

EDP_INT_ML_N<1>

EDP_INT_ML_P<2>

EDP_INT_ML_N<2>

EDP_INT_ML_P<3>

EDP_INT_ML_P<0>

MAKE_BASE=TRUE

EDP_INT_ML_N<0>

MAKE_BASE=TRUE

EDP_INT_ML_P<1>

MAKE_BASE=TRUE

EDP_INT_ML_N<1>

MAKE_BASE=TRUE

EDP_INT_ML_P<2>

MAKE_BASE=TRUE

EDP_INT_ML_N<2>

MAKE_BASE=TRUE

EDP_INT_ML_P<3>

104 80

PPVOUT_S0_LCDBKLT

104 80

10%

100V 0603

1

2

104 80

C8500

1000PF

X7R-CERM

104 80 79

53 54

55 56

57 58

59 60

61 62

63 64

65 66

67 68

SIGNAL_MODEL=EDP

B

A

NO_XNET_CONNECTION=1

R8501

100K

5%

1/20W

MF

201

1

NO_STUFF

2

1

R8502

1M

5% 1/20W MF 201

2

LCD Panel HPD & AUX strapping

8 7 5 4 2 1

MAKE_BASE=TRUE

5

IN

5

BI

5

BI

EDP_INT_ML_N<3>

EDP_INT_AUX_P

EDP_INT_AUX_N

EDP_INT_ML_N<3>

MAKE_BASE=TRUE

EDP_INT_AUX_P

MAKE_BASE=TRUE

EDP_INT_AUX_N

104 80

SYNC_MASTER=J79_RUENJOU SYNC_DATE=09/12/2015

PAGE TITLE

A

eDP Display Connector

DRAWING NUMBER SIZE

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

85 OF 145

SHEET

80 OF 119

BOM_COST_GROUP=DISPLAY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

36

D

345678

2 1

D

C

B

A

CONFIG

00 - 2 01 - 4

LANDING1

R8601

NOSTUFF NOSTUFF ASSEMBLE

10 - 8 ASSEMBLE

11 - RESERVED ASSEMBLE

OPERATION MODE (ODT, CLK FREQ, ETC)

CONFIG

000 - TEABERRY 001 - XB58 GS 010 - RESERVED 011 - RESERVED 100 - RESERVED 101 - RESERVED 110 - RESERVED 111 - RESERVED

1

C8657

0.01UF

10% 10V

2

X7R-CERM 0201

1

C8650

0.01UF

10% 10V

2

X7R-CERM 0201

131S00077

117S0002

OP_MODE2

NOSTUFF NOSTUFF NOSTUFF NOSTUFF ASSEMBLE ASSEMBLE ASSEMBLE ASSEMBLE

1 CRITICAL

NAND LANDINGS

LANDING0

R8660

NOSTUFF

ASSEMBLE

OP_MODE1

NOSTUFF

NOSTUFF ASSEMBLE ASSEMBLE

NOSTUFF

ASSEMBLE ASSEMBLE

1

C8658

0.01UF

10% 10V

2

X7R-CERM 0201

1

C8652

0.01UF

10% 10V

2

X7R-CERM 0201

S3XCLK:INT

1

2

NOSTUFF ASSEMBLE NOSTUFF ASSEMBLE NOSTUFF ASSEMBLE NOSTUFF ASSEMBLE

1

C8659

0.01UF

10% 10V

2

X7R-CERM 0201

1

C8654

0.01UF

10% 10V

2

X7R-CERM 0201

PLACE_NEAR=U8600.AJ18:2.0MM

Y8600

1.60X1.20MM-SM

24MHZ-30PPM-60OHM

1 3

S3XCLK:INT

S3X_XTALO

PLACE_NEAR=Y8600.1:1.0MM

C8600

9.5PF

+/-0.1PF 50V CER-C0G 0201

2 4

Buffered SSD_RESET_L to Mitigate EPO Issue

104 88 87 86 85 84 82 81 19

91 88 84

OP_MODE0

R8680R8615R8614

S3X_XTALI

NC

PLACE_NEAR=U8600.AK18:2.0MM

1

2

OMIT_TABLE

IN

000 - MLC SD/TOS 1Y/1Z(W/ HARD RESET)

001 - MLC SD/TOS 1Y/1Z (W/O HARD RESET)

PP1V8_SSD_COLD

1

C8660

0.01UF

10% 10V

2

X7R-CERM 0201

1

C8656

0.01UF

10% 10V

2

X7R-CERM 0201

PLACE_NEAR=U8600.AJ18:2.0MM

1

R8600

S3XCLK:INT

R8602

1K

1 2

1%

1/20W

MF

201

PLACE_NEAR=Y8600.3:1.0MM

S3XCLK:INT

1M

1% 1/20W MF 201

2

C8601

9.5PF

+/-0.1PF 50V CER-C0G 0201

C8601CAP,9.5PF,50V,0201

C8601RES,MF,0 OHM,1/20W,0201

PP1V8_SSD_COLD

SSD_RESET_LB_L

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

1

C8602

0.1UF

10%

6.3V

2

CERM-X5R 0201

NC

NAND CONFIGURATION

CONFIG

ROMBOOT2

R8617

NOSTUFF NOSTUFF

010 - RESERVED

NOSTUFF

011 - MLC HYNIX 3D-V2 NOSTUFF

100 - RESERVED 101 - RESERVED 110 - RESERVED 111 - RESERVED

ASSEMBLE ASSEMBLE ASSEMBLE ASSEMBLE

PRODUCT CAPACITY

CONFIG

000 - 32GB 001 - 64GB NOSTUFF 010 - 128GB 011 - 256GB 100 - 512GB 101 - 1024GB 110 - 2048GB 111 - RESERVED

104 88 87 86 85 84 82 81 19

ANI01_VREF

ANI23_VREF

ANI45_VREF

ANI67_VREF

86

87

S3X_XTALO_R

1

R8605

34.8

1% 1/20W MF 201

2

CRITICAL1

1

R8606

34.8

1% 1/20W MF 201

2

S3XCLK:INT

S3XCLK:EXT

U8601

74AUP1G08GF

6

SOT891

VCC

2

A Y

1

B

5

NC

GND

3

4

ERN_L

CAPACITY2

NOSTUFF

NOSTUFF NOSTUFF ASSEMBLE ASSEMBLE ASSEMBLE ASSEMBLE

104 88 87 86 85 84 82 81 19

ANI47_ZQ ANI03_ZQ

R8603

3.01K

1 2

1%

1/20W

MF

201

81

PP1V8_SSD_COLD

ROMBOOT1

R8618

NOSTUFF

NOSTUFF ASSEMBLE ASSEMBLE

NOSTUFF

ASSEMBLE ASSEMBLE

CAPACITY1

NOSTUFF

NOSTUFF ASSEMBLE ASSEMBLE

NOSTUFF

ASSEMBLE ASSEMBLE

102

NC_S3X_DT0 NC_S3X_DT1

102

88

IN

ROMBOOT0

R8616

NOSTUFF ASSEMBLE NOSTUFF ASSEMBLE NOSTUFF ASSEMBLE NOSTUFF ASSEMBLE

CAPACITY0

R8662R8663R8664

NOSTUFF ASSEMBLE NOSTUFF ASSEMBLE NOSTUFF ASSEMBLE NOSTUFF ASSEMBLE

1

R8615

10K

5% 1/20W MF 201

2

S3X_PCIE_REF

S3X_GPIO0 NC_S3X_GPIO1 S3X_PFN

NC

F18 G18

AK18 AJ18

T26 T25

T5 T6

H17

AD11 AD10 AE11

DTO0 DTO1

XI0 XO0

ANI03_ZQ_PD

ANI03_ZQ_PU ANI47_ZQ_PD ANI47_ZQ_PU

REXT

GPIO0 GPIO1 GPIO2

OMIT_TABLE

U8600

S3X

BGA-H1P35

SYM 3 OF 7

DDR_PHY_DATA_VREF

REFCLK_P REFCLK_M

PCIE_TX0_P PCIE_TX0_M

PCIE_TX1_P PCIE_TX1_M

PCIE_TX2_P PCIE_TX2_M

PCIE_TX3_P PCIE_TX3_M

PCIE_RX0_P PCIE_RX0_M

PCIE_RX1_P PCIE_RX1_M

PCIE_RX2_P PCIE_RX2_M

PCIE_RX3_P PCIE_RX3_M

DDR_ATO

BOOT_FROM_LPSR

CLK_IN

CLK_IN_SEL

PCIE_ATB0

PCIE_ATB1

PCIE_CLKREQ*

JTAG_TRST*

RESET*

HOLD_RESET

PERST*

JTAG_SEL JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

I2C_SCL

I2C_SDA

PMIC_CTRL0 PMIC_CTRL1 PMIC_CTRL2

PMIC_EXT_CLK_DIS

PMIC_LOW_PWR

RET_LPSR_CLEAR

SPI_CLK

SPI_CS* SPI_MISO SPI_MOSI

SPI_NOR_CLK SPI_NOR_CS*

SPI_NOR_SIO0

SPI_NOR_SO1

SPI_NOR_SO2

SPI_NOR_SO3 SPI_NOR_RFN

UART0_RX UART0_TX UART1_RX UART1_TX

RETEN_EN

DDR_PHY_ZQ

DDR_VREFI_ALIVE

DDR_VREFI_ZQ

DDR_VREFO

DDR_ZQ DDR_CKE0 DDR_CKE1

A19 A18

A17 A16

A15 A14

A13 A12

A11 A10

C17 C16

C15 C14

C13 C12

C11 C10

J21

AF17

AG18 AD17

G16 G17

F12

AE18 AF18 AH18 E12

AG20 AH19 AH17 AD20 AF19

E8 F8

AF20 AE20 AG17 AH20 AD21

AE17

F11 G12 E11 G10 E9 G11 H10 C8 F10 G9 E10

B8 A8 B7 A7

H18

AD12 G21 B23 J20 AH16 B26 C20 C21

PCIE_CLK100M_SSD_LB_P PCIE_CLK100M_SSD_LB_N

PCIE_SSD_D2R_C_P<0> PCIE_SSD_D2R_C_N<0>

PCIE_SSD_D2R_C_P<1> PCIE_SSD_D2R_C_N<1>

PCIE_SSD_D2R_C_P<2> PCIE_SSD_D2R_C_N<2>

PCIE_SSD_D2R_C_P<3> PCIE_SSD_D2R_C_N<3>

PCIE_SSD_R2D_LB_P<0> PCIE_SSD_R2D_LB_N<0>

PCIE_SSD_R2D_P<1> PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<2> PCIE_SSD_R2D_N<2>

PCIE_SSD_R2D_P<3> PCIE_SSD_R2D_N<3>

NC_S3X_DDR_ATO

S3X_COLD_BOOT_L

S3X_EXT_SE_24MHZ_CLK_IN S3X_CLK_IN_SEL

NC_S3X_PCIE_ATB0 NC_S3X_PCIE_ATB1

S3X_PCIE_CLKREQ_L

S3X_JTAG_TRST_L

S3X_RESET_L S3X_HOLD_RESET

84

S3X_PERST_L

S3X_JTAG_SEL S3X_JTAG_TCK S3X_JTAG_TDI S3X_JTAG_TDO S3X_JTAG_TMS

S3X_I2C_SCL S3X_I2C_SDA

S3X_PMIC_CTRL0 S3X_PMIC_CTRL1 NC_S3X_PMIC_CTRL_2 S3X_PMIC_EXT_CLK_DIS S3X_PMIC_LOW_PWR

S3X_RET_LPSR_CLEAR

S3X_SPI_CLK SSD_BOOT_LB_L S3X_SPI_MISO S3X_SPI_MOSI S3X_BOOTSTRAP0 NC_S3X_BOOTSTRAP1 ERN_L S3X_BOOTSTRAP3 S3X_BOOTSTRAP4 S3X_BOOTSTRAP5 NC_S3X_BOOTSTRAP6

S3X_SMC_OOB_UART_R2D

88

S3X_SMC_OOB_UART_D2R S3X_DEBUG_UART_R2D S3X_DEBUG_UART_D2R

S3X_RET_EN_L

S3X_DDR_PHY_DATA_VREF S3X_DDR_PHY_ZQ S3X_DDR_VREFI_ALIVE S3X_DDR_VREFI_ZQ S3X_DDR_VREFO S3X_DDR_ZQ S3X_DDR_CKE0

S3X_DDR_CKE1

NOSTUFF

1

R8610

1K

5% 1/20W MF 201

2

PLACE_NEAR=U8600.B26:3.0MM

NOSTUFF

1

R8611

1K

2

5% 1/20W MF 201

102

IN

102

R8624

104 84

IN

94

IN

OUT

BI

OUT

88

102

88

102

81

102

IN

1

R8607

240

1% 1/20W MF 201

2

91

105 91

81

84

IN

84

IN

84

IN

84

IN

84

IN

84

IN

104 88 87 86 85 84 82 81 19

84

IN

84

IN

88

1/20W

104 84

104 94 84

10K

5%

MF

201

88 85

104 84

IN

1 2

104 84

BI

104 88 87 86 85 84 82 81 19

105 15

91

1

R8604

2

1

R8612

2

NAND_CFG0

1

R8616

10K

5% 1/20W MF 201

2

IN

1

C8621

1000PF

2

BYPASS=U8600.AH16::3.0MM BYPASS=U8600.J20::3.0MM BYPASS=U8600.B23::3.0MM BYPASS=U8600.AD12::3.0MM

88

91 88 84

88

OUT

1

2

88

C8620

1000PF

10% 16V X7R-1 0201

GND_VOID=TRUE

C8610

OUT

PCIE_SSD_D2R_LB_P<0>

GND_VOID=TRUE

C8611

OUT

PCIE_SSD_D2R_LB_N<0>

GND_VOID=TRUE

C8613

OUT

PCIE_SSD_D2R_P<1>

GND_VOID=TRUE

C8612

OUT

PCIE_SSD_D2R_N<1>

GND_VOID=TRUE

C8614

OUT

PCIE_SSD_D2R_P<2>

GND_VOID=TRUE

C8615

OUT

PCIE_SSD_D2R_N<2>

GND_VOID=TRUE

C8617

OUT

PCIE_SSD_D2R_P<3>

GND_VOID=TRUE

C8616

OUT

100K

0.1% 1/20W MF 0201-1

BI

10K

5% 1/20W MF 201

PP1V8_SSD_COLD

1

2

PCIE_SSD_D2R_N<3>

PP1V8_SSD_COLD

1

R8676

10K

5% 1/20W MF 201

2

88

IN

NAND_CFG2

R8617

10K

5% 1/20W MF 201

1

R8677

10K

2

S3XCLK:INT

88

NAND_CFG1

1

R8618

10K

5% 1/20W MF 201

2

5% 1/20W MF 201

IN

88

1

R8660

10K

5% 1/20W MF 201

2

R8629

10K

1 2

88

10% 16V X7R-1 0201

5%

1/20W

MF

201

1

C8622

1000PF

10% 16V

2

X7R-1 0201

1

C8623

1000PF

10% 16V

2

X7R-1 0201

BOM_COST_GROUP=SSD

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

GND_VOID=TRUE

PCIE_SSD_D2R_C_P<0>

GND_VOID=TRUE

PCIE_SSD_D2R_C_N<0>

GND_VOID=TRUE

PCIE_SSD_D2R_C_P<1>

GND_VOID=TRUE

PCIE_SSD_D2R_C_N<1>

GND_VOID=TRUE

PCIE_SSD_D2R_C_P<2>

GND_VOID=TRUE

PCIE_SSD_D2R_C_N<2>

GND_VOID=TRUE

PCIE_SSD_D2R_C_P<3>

GND_VOID=TRUE

PCIE_SSD_D2R_C_N<3>

S3XCLK:EXT

1

R8674

1K

5% 1/20W MF 201

2

1

R8609

1K

5% 1/20W MF 201

2

1

2

CAPACITY0

1

R8662

10K

5% 1/20W MF 201

2

PLACE_NEAR=U8600.G21:3.0MM

1

R8608

240

1% 1/20W MF

PACK_TYPE=201

2

SYNC_MASTER=J79_RUENJOU SYNC_DATE=08/20/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

S3XCLK:EXT

R8698

33

1 2

PLACE_NEAR=U1900.16:2.0MM

MF1/20W

SYSCLK_CLK24M_SSD

5%

201

R8699

0

5% 1/20W MF 201

S3XCLK:INT

CAPACITY1

1

R8663

10K

5% 1/20W MF 201

2

CAPACITY2

1

R8664

10K

5% 1/20W MF 201

2

S3X CORE PCIE

Apple Inc.

R

81

2016-08-3000069392729 ENGINEERING RELEASED

18

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

86 OF 145

SHEET

81 OF 119

D

C

B

A

8 7 5 4 2 1

36

D

C

B

A

104 88 87 86 85 84 82 81 19

BYPASS=U8600.K17::1.5MM BYPASS=U8600.J14::1.5MM

1

C8766

0.1UF

10%

6.3V

2

X7R 0201

104 88 87 86 85 84 82 81 19

C8770

1UF

20%

4V CERM 0402

1

234

C8772

1UF

20%

4V CERM 0402

1

234

1

C8700

0.1UF

10%

6.3V

2

X7R 0201

1

C8704

1.0UF

20%

6.3V

2

X5R 0201-1

1

C8701

0.1UF

10%

6.3V

2

X7R 0201

1

C8705

1.0UF

20%

6.3V

2

X5R 0201-1

1

C8784

0.1UF

10%

6.3V

2

X7R 0201

BYPASS=U8600.A21::1.5MM BYPASS=U8600.A25::1.5MM

1

C8718

0.1UF

10%

6.3V

2

X7R 0201

1

C8702

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8706

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

C8716

0.1UF

10%

6.3V

2

X7R 0201

88

C8771

1UF

20%

4V CERM 0402

1

234

C8773

1UF

20%

4V CERM 0402

1

234

PP1V8_SSD_COLD

PP0V9_SSD_FIXED

1

C8717

0.1UF

10%

6.3V

2

X7R 0201

PP1V8_SSD_COLD

1

C8703

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8707

4.7UF

20%

6.3V

2

X6S 0402

PP1V2_SSD_HOT

88 82

H15

J13 J15 J12 J14

J17 J16 H16

K13 K15 K12 K14

K17 K16

AB12 AB16

K19

AB30 AB29 AB28

J30

AC25

V26 W25 Y26 M26 P26 R27

J23 AB20 AB22 AB24 AC21 AC23

K26

N25 AA27

H22

H24

H26

J27

J28

J29

L27

N27 AB27

U27

W27

H5

J1 AB1 AB2 AB3

J7

J9 J11 K10 AB4 AB7

J2

J3

J4 AB9

K5

AB11

L4

M5

N4

N6

P5

R4

U4

V5

W4

W6 AC6 AC8

Y5

AC10

AA4

A21 A25

BGA-H1P35

PCI_AVDD_H

PCI_VDD_1 PCI_VDD_1 PCI_VDD_1 PCI_VDD_1

PCI_VDD_2 PCI_VDD_2 PCI_VDD_2

PCI_VDD_CLK_1 PCI_VDD_CLK_1 PCI_VDD_CLK_1 PCI_VDD_CLK_1

PCI_VDD_CLK_2 PCI_VDD_CLK_2

VDDIO18_DDR_PLL_D VDDIO18_DDR_PLL_D

VDDIO18_DDR_PLLAC

VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03 VDDIO_03

VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47 VDDIO_47

VDDCA VDDCA

SYM 4 OF 7

U8600

S3X

VDDRQ12_AC_AON

VDD12_DDRAC_CK

VDD1 VDD1 VDD1 VDD1 VDD1 VDD1

VDDRQ12_AC VDDRQ12_AC VDDRQ12_AC

VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2

VDD_03 VDD_03 VDD_03 VDD_03 VDD_03 VDD_03 VDD_03 VDD_03 VDD_03

VDD_47 VDD_47 VDD_47 VDD_47 VDD_47 VDD_47 VDD_47 VDD_47 VDD_47

VDD_PLL4 VDD_PLL5 VDD_PLL6 VDD_PLL7 VDD_PLL8

VDD_PLL9 VDD_PLL10 VDD_PLL11 VDD_PLL_C

VDD18_EFUSE0 VDD18_EFUSE1 VDD18_EFUSE2 VDD18_EFUSE3

VDD18_XTAL

VDDA18_PLL4 VDDA18_PLL5 VDDA18_PLL6 VDDA18_PLL7 VDDA18_PLL8

VDDA18_PLL9 VDDA18_PLL10 VDDA18_PLL11 VDDA18_PLL_C

VDDA18_TS

VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12 VDDRQ12

A28 AJ3 AJ28 AK15 AK16 B21

G19 H20 J19

K18

B19 A23 A27 AJ8 AJ15 AJ16 AJ23 AK3 AK28

J25 L25 R25 AA25 U25 L24 AB25 R24 W24

R7 L7 W7 AB6 J6 L6 R6 U6 AA6

Y25 V25 K25 P25 K6 P6 Y6 V6 W18

AA7 AA8 AA9 AA10 AB19

Y23 V24 K23 P24 K8 P7 Y8 V7 W17 Y19

AB13 AC12 AC14 AD13 AE14 AF13 AF15 AG14 AH13 AH15 AB15 AC16 AD15 AE16 AG16 AK13 AK4 AK6 AK8 AK10 AK12 AK14 AK17 AK19 AK21 AK23 AK25 AK27

K20

88

PP1V8_SSD_HOT

PP1V2_SSD_COLD

PP1V2_SSD_HOT

88 82

PP0V9_SSD_REG

VOLTAGE=0.9V

PP0V9_PLL_C_DVDD03 PP0V9_SSD_REG

CKPLUS_WAIVE=PWRTERM2GND

PP1V8_SSD_COLD

PP1V8_PLL_C_AVDD

VOLTAGE=1.8V

PP1V2_SSD_COLD

S3X_VDDR12_CK_PLANE

82

C8715

1.0UF

1 2

6.3V

1

C8710

0.1UF

10%

6.3V

2

X7R 0201

88 82

1

C8720

0.1UF

10%

6.3V

2

X7R 0201

88

PP1V2_SSD_COLD

82

104 88 82

1

C8734

0.1UF

10%

6.3V

2

X7R 0201

BYPASS=U8600.G19::1.5MM BYPASS=U8600.H20::1.5MM BYPASS=U8600.J19::1.5MM

1

C8711

0.1UF

10%

6.3V

2

X7R 0201

1

C8721

0.1UF

10%

6.3V

2

X7R 0201

1

C8735

2

0.1UF

10%

6.3V X7R 0201

1

C8712

0.1UF

10%

6.3V

2

X7R 0201

1

C8722

0.1UF

10%

6.3V

2

X7R 0201

1

C8760

0.1UF

2

10%

6.3V X7R 0201

1

C8713

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8723

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8761

2

L8700

22NH-100MA

VOLTAGE=0.9V

PP0V9_PLL_DVDD47 PP0V9_SSD_REG

1 2

0201

L8701

VOLTAGE=0.9V

PP0V9_PLL_DVDD811

22NH-100MA

1 2

0201

PP0V9_SSD_REG

L8702

22NH-100MA

1 2

0201

R8700

25.5

1 2

1%

1/20W

MF

201

1

C8788

10UF

20% 4V

2

X6S 0402

1

C8732

1.0UF

20%

6.3V

2

X5R 0201-1

1

C8708

0.1UF

10%

6.3V X7R 0201

BYPASS=U8600.AK4::1.5MM

C8782

0.22UF

20%

6.3V X6S-CERM 0201

C8726

0.1UF

10%

6.3V

2

X7R 0201

1

2

1

C8733

2.2UF

20%

6.3V

2

X5R-CERM 0201

C8783

0.1UF

10%

6.3V X7R 0201

20%

X5R

0201-1

PP1V8_PLL_AVDD47

82

PP1V8_PLL_AVDD811

1

C8787

10UF

20% 4V

2

X6S 0402

1

C8730

0.1UF

10%

6.3V

2

X7R 0201

1

C8709

0.1UF

10%

6.3V

2

X7R 0201

BYPASS=U8600.K20::1.5MM

1

2

1

2

1

2

1

C8781

0.1UF

10%

6.3V

2

X7R 0201

BYPASS=U8600.W17::1.5MM BYPASS=U8600.W17::1.5MM

C8786

10UF

20% 4V X6S 0402

C8731

0.22UF

20%

6.3V X6S-CERM 0201

C8785

0.1UF

10%

6.3V X7R 0201

1

2

1

2

1

C8714

1.0UF

20%

6.3V

2

X5R 0201-1

1

C8724

1.0UF

20%

6.3V

2

X5R 0201-1

1

C8762

2

104 88 82

0.1UF

10%

6.3V X7R 0201

0.1UF

10%

6.3V X7R 0201

PP1V8_SSD_COLD

R8701

25.5

1 2

R8702

25.5

1 2

1%

1/20W

MF

201

1

C8798

0.1UF

10%

6.3V

2

X7R 0201

S3X_VSSA18_PLL_C

BYPASS=U8600.AE16::1.5MM BYPASS=U8600.AG14::1.5MM

1

C8736

0.1UF

10%

6.3V

2

X7R 0201

1

C8727

0.1UF

10%

6.3V

2

X7R 0201

1

C8780

0.1UF

10%

6.3V

2

X7R 0201

1

C8725

2.2UF

20%

6.3V

2

X5R-CERM 0201

1

C8763

0.1UF

10%

6.3V

2

X7R 0201

PP1V8_SSD_COLD

1%

1/20W

MF

201

PP1V8_SSD_COLD

83

1

C8737

0.1UF

10%

6.3V

2

X7R 0201

1

C8789

0.1UF

10%

6.3V

2

X7R 0201

BOMOPTION=OMIT_TABLE

L8704

22NH-100MA

1 2

0201

104 88 82

1

C8764

0.1UF

10%

6.3V

2

X7R 0201

104 88 87 86 85 84 82 81 19

88

PP1V2_SSD_COLD

82

PP0V9_SSD_REG

104 88 87 86 85 84 82 81 19

83

S3X_VSSA18_PLL4

83

S3X_VSSA18_PLL5

83

S3X_VSSA18_PLL6

83

S3X_VSSA18_PLL7

83

S3X_VSSA18_PLL8

83

S3X_VSSA18_PLL9

83

S3X_VSSA18_PLL10

83

S3X_VSSA18_PLL11

BYPASS=L8704.2::1.0MM

C8765

0.1UF

1 2

10%

6.3V X7R 0201

AA11 AA13 AA15 AA17 AA19 AA21 AA23

K22

L9 L11 L13 L15 L17 L19 L21 L23

M8 M10 M12 M14 M16 M18 M20 M22

N9 N11 N13 N15 N17 N19 N21 N23

P8 P10 P12 P14 P16 P18 P20 P22

R9 R11 R13 R15 R17

117S0002 1 CRITICAL

VOLTAGE=1.8V

PP1V8_PLL_AVDD47

82

1

C8790

0.1UF

10%

6.3V

2

X7R 0201

PP1V8_PLL_AVDD811

82

1

2

VOLTAGE=1.8V

C8794

0.1UF

10%

6.3V X7R 0201

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

1

C8791

0.1UF

10%

6.3V

2

X7R 0201

1

C8795

0.1UF

10%

6.3V

2

X7R 0201

345678

U8600

S3X

BGA-H1P35

SYM 5 OF 7

1

C8792

0.1UF

10%

6.3V

2

X7R 0201

1

C8796

0.1UF

10%

6.3V

2

X7R 0201

OMIT_TABLE

R19

VDD

R21

VDD

R23

VDD

T8

VDD

T10

VDD

T12

VDD

T14

VDD

T16

VDD

T18

VDD

T20

VDD

T22

VDD

U9

VDD

U11

VDD

U13

VDD

U15

VDD

U17

VDD

U19

VDD

U21

VDD

U23

VDD

V8

VDD

V10

VDD

V12

VDD

V16

VDD

V18

VDD

V20

VDD

V22

VDD

W9

VDD

W11

VDD

W13

VDD

W15

VDD

W19

VDD

W21

VDD

W23

VDD

Y10

VDD

Y12

VDD

Y14

VDD

Y16

VDD

Y18

VDD

Y20

VDD

Y22

VDD

VDD_S

BYPASS=U8600.Y24::1.5MM BYPASS=U8600.U24::1.5MM BYPASS=U8600.K24::1.5MM BYPASS=U8600.N24::1.5MM

1

C8793

0.1UF

10%

6.3V

2

X7R 0201

BYPASS=U8600.K7::1.5MM BYPASS=U8600.N7::1.5MM BYPASS=U8600.Y7::1.5MM BYPASS=U8600.U7::1.5MM

1

C8797

0.1UF

10%

6.3V

2

X7R 0201

BYPASS=U8600.K20::1.5MM

V14

S3X_VDDR12_CK_PLANE

1

C8719

0.1UF

10%

6.3V

2

X7R 0201

NC_S3X_VDD_S

BOM_COST_GROUP=SSD

82

2 1

1

C8740

0.1UF

10%

6.3V

2

X7R 0201

1

C8745

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8750

4.7UF

20%

6.3V

2

X6S 0402

1

C8754

10UF

20% 4V

2

X6S 0402

C8758

1

102

L8704RES,MF,0 OHM,1/20W,0201

PAGE TITLE

1UF

20%

4V CERM 0402

234

1

C8741

0.1UF

10%

6.3V

2

X7R 0201

1

C8746

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8751

4.7UF

20%

6.3V

2

X6S 0402

1

C8755

10UF

20% 4V

2

X6S 0402

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

C8759

1UF

20%

4V CERM 0402

1

234

1

C8742

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8747

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8752

4.7UF

20%

6.3V

2

X6S 0402

1

C8756

10UF

20% 4V

2

X6S 0402

1

C8743

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8748

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8757

10UF

20% 4V

2

X6S 0402

S3X POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

C8744

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8749

0.22UF

20%

6.3V

2

X6S-CERM 0201

1

C8753

4.7UF

20%

6.3V

2

X6S 0402

SYNC_DATE=06/18/2015SYNC_MASTER=J79_RIO

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

87 OF 145

SHEET

82 OF 119

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

82

S3X_VSSA18_PLL4

82

S3X_VSSA18_PLL5

82

S3X_VSSA18_PLL6

82

S3X_VSSA18_PLL7

82

S3X_VSSA18_PLL8

82

S3X_VSSA18_PLL9

82

S3X_VSSA18_PLL10

82

S3X_VSSA18_PLL11

82

S3X_VSSA18_PLL_C

Y24 U24 K24 N24

K7 N7 Y7 U7

V17

A1 A2

A9 A20 A29 A30 AA5

AA12 AA14 AA16 AA18 AA20 AA22 AA24 AA26

AB5 AB8

AB10 AB14 AB17 AB18 AB21 AB23 AB26

AC3 AC4 AC5 AC7 AC9

AC11 AC13 AC15 AC17 AC18 AC19 AC20 AC22 AC24 AC26 AC27 AC28

AD4 AD5 AD6 AD7 AD8 AD9

AD14 AD16 AD18 AD19 AD24 AD25 AD26 AD27

AE3 AE4 AE5 AE6 AE7 AE8 AE9

AE10 AE12 AE13 AE15 AE19 AE21 AE22 AE23 AE25 AE26 AE27 AE28

AF3 AF4 AF5 AF7 AF8 AF9

AF11 AF12 AF14 AF16 AF27 AF28

AG3 AG4

AG13 AG15

VSS_PLL4 VSS_PLL5 VSS_PLL6 VSS_PLL7 VSS_PLL8 VSS_PLL9 VSS_PLL10 VSS_PLL11 VSS_PLL_C

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

OMIT_TABLE

U8600

S3X

BGA-H1P35

SYM 6 OF 7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AG19 AG21 AG23 AG25 AG27 AG28 AH4 AH14 AH27 AJ1 AJ2 AJ4 AJ6 AJ10 AJ12 AJ13 AJ14 AJ17 AJ19 AJ21 AJ25 AJ27 AJ29 AJ30 AK1 AK2 AK29 AK30 B1 B2 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B27 B28 B29 B30 C5 C7 C9 C18 C22 C23 C24 C25 C26 C27 D3 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D27 D28 E3 E13 E14 E15 E16 E17 E18 E27 E28 F3 F5 F7 F9 F13 F14 F15 F16 F17 F19 F20 F22 F24 F25 F26 F27 F28 G4 G13 G14 G15 G20 G22

G23 G24 G25 G26 G27

H3 H4 H6 H7

H8 H11 H12 H13 H14 H19 H21 H23 H25 H27 H28

J5

J8 J10 J18 J22 J24 J26

K4

K9 K11 K21 K27

L3

L5

L8 L10 L12 L14 L16 L18 L20 L22 L26 L28

M3

M4

M6

M7

M9 M11 M13 M15 M17 M19 M21 M23 M24 M25 M27 M28

N3

N5

N8 N10 N12 N14 N16 N18 N20 N22 N26 N28

P4

P9 P11

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

OMIT_TABLE

U8600

S3X

BGA-H1P35

SYM 7 OF 7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS_S

P13 P15 P17 P19 P21 P23 P27 R3 R5 R8 R10 R12 R14 R16 R18 R20 R22 R26 R28 T3 T4 T7 T9 T11 T13 T15 T17 T19 T21 T23 T24 T27 T28 U5 U8 U10 U12 U14 U16 U18 U20 U22 U26 V3 V4 V9 V11 V13

V19 V21 V23 V27 V28 W3 W5 W8 W10 W12 W14 W16 W20 W22 W26 W28 Y3 Y4 Y9 Y11 Y13 Y15 Y17 Y21 Y27 Y28

V15

NC_S3X_VSS_S

102

BOM_COST_GROUP=SSD

SYNC_MASTER=J79_RIO

PAGE TITLE

PAGE_TITLE=S3X GND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=06/18/2015

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

88 OF 145

SHEET

83 OF 119

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

104 81

104 94 81

104 81

104 88

87 86 85 84 82 81 19

104 88

JTAG (DEBUG 1)

S3X_JTAG_TDI

S3X_JTAG_TMS

S3X_JTAG_TCK

S3X_JTAG_SEL

SSD_DBG_UART_R2D

PP1V8_SSD_COLD

S3X_DBG

J8992

DF40PB-20DS-0.4V

NC

F-ST-SM

22

21

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

23

24

S3X_JTAG_TDO

S3X_JTAG_TRST_L SSD_BOOT_LB_L

S3X_HOLD_RESET

SSD_DBG_UART_D2R

SSD_RESET_LB_L

PP1V8_SSD_COLD

104 81

81

GND_VOID=TRUE

C8910

91

PCIE_SSD_R2D_LB_C_P<0>

GND_VOID=TRUE

C8911

91

PCIE_SSD_R2D_LB_C_N<0>

GND_VOID=TRUE

C8913

105 15

PCIE_SSD_R2D_C_P<1>

GND_VOID=TRUE

C8912

105 15

104 81

91 88 81

PCIE_SSD_R2D_C_N<1>

GND_VOID=TRUE

C8914

GND_VOID=TRUE

C8915

104 88 19

91 88 81

104 88 87 86 85 84 82 81 19

101

88 101

PP3V3_S4

PP3V3_S5_SSD

R8901

R8902

1/20W

100K

1 2

2011/20W MF5%

100K

1 2

201MF5%

3

STORAGE_EN

PD_L

104 91

105 15 81

105 15

PCIE_SSD_R2D_C_N<2> PCIE_SSD_R2D_N<2>

GND_VOID=TRUE

C8917

PCIE_SSD_R2D_C_P<3>

GND_VOID=TRUE

C8916

PCIE_SSD_R2D_C_N<3>

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

0.22UF

1 2

GND_VOID=TRUE

PCIE_SSD_R2D_LB_P<0>

GND_VOID=TRUE

PCIE_SSD_R2D_LB_N<0>

GND_VOID=TRUE

PCIE_SSD_R2D_P<1>

GND_VOID=TRUE

PCIE_SSD_R2D_N<1>

GND_VOID=TRUE

PCIE_SSD_R2D_P<2>PCIE_SSD_R2D_C_P<2>

GND_VOID=TRUE

PCIE_SSD_R2D_P<3>

GND_VOID=TRUE

PCIE_SSD_R2D_N<3>

81

81 105 15

81

81 88

D

C

D

Q8901

91

P2MM

SM

77 88

SSD_PWR_REQ

1

PP

PP8901

SSD_PWR_EN_LB_L

1

R8903

100K

5% 1/20W MF 201

2

G

1

S

2

DMN32D2LFB4

DFN1006H4-3

SYM_VER_1

C

B

A

PAGE TITLE

Connector

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

89 OF 145

84 OF 119

SYNC_DATE=09/09/2015SYNC_MASTER=J79_RUENJOU

A

D

345678

U9010: Top side under S3X

2 1

DEVICE 2-WIRE ADDRESS ADD0 PIN CONNECTION 1001000 GND 1001001 V+ 1001010 SDA 1001011 SCL

D

104 88 87 86 84 82 81 19

88 85 81

BI

PP1V8_SSD_COLD

1

R9010

4.7K

5% 1/20W MF 201

2

1

R9011

4.7K

5% 1/20W MF 201

2

S3X_I2C_SDA S3X_I2C_SCL

5

V+

U9010

HPA00330AI

6

1

SOT563

SDA

SCL ALERT

GND

2

5

V+

U9011

HPA00330AI

6

1

SOT563

SDA

SCL ALERT

ADD0

4

S3X_I2C_SDA

3

4

S3X_I2C_SCL

3

NC

BYPASS=U9011.5::3.0MM

1

C9010

0.01UF

10% 10V

2

X5R-CERM

88 85 81

BYPASS=U9010.5::3.0MM

88 85 81

0201

U9011: Bottom side under Piccolo

1

C9011

0.01UF

10% 10V

2

X5R-CERM 0201

1

C9012

0.01UF

10% 10V

2

X5R-CERM 0201

BYPASS=U9012.5::3.0MM

BYPASS=U9013.5::3.0MM

1

C9013

0.01UF

10% 10V

2

X5R-CERM 0201

D

C

GND

2

5

V+

U9012

HPA00330AI

6

1

SOT563

SDA

SCL ALERT

GND

2

5

V+

U9013

HPA00330AI

6

1

SOT563

SDA

SCL ALERT

ADD0

4

3

4

3

C

U9012: Bottom side near north NAND

NC

U9013: Top side near south NAND

NC

B

GND

2

B

A

SYNC_MASTER=J79_RUENJOU

PAGE TITLE

NAND VR, I2C ROM, TEMP SENSORS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=09/12/2015

051-00515

9.0.0

dvt-fab09-0

90 OF 145

85 OF 119

A

D

C

B

86 81

OMIT_TABLE

NC NC

AC29 AD30 AD29 AD28 AG30 AG29 AH30 AH29

AG22 AD23 AF21 AD22 AF22 AF23 AJ20 AK20

AH23 AK22 AH28 AJ22

AH22 AH21

AF30 AF29

AE30 AE29

AC30

H29 G28 G29 G30 D29 D30 C29 C30

B22 C19 D22 E22 F21 D19 D21 E21

E20 A22 C28 D20

E19 B20

E29 E30

F29 F30

H30

ANI0_IO0 ANI0_IO1 ANI0_IO2 ANI0_IO3 ANI0_IO4 ANI0_IO5 ANI0_IO6 ANI0_IO7

ANI0_NCE(0) ANI0_NCE(1) ANI0_NCE(2) ANI0_NCE(3) ANI0_NCE(4) ANI0_NCE(5) ANI0_NCE(6) ANI0_NCE(7)

ANI0_ALE ANI0_CLE ANI0_NWE ANI0_RNB

ANI0_PPM_IN ANI0_PPM_OUT

ANI0_NRE_P ANI0_NRE_N

ANI0_DQS_P ANI0_DQS_N

ANI0_VREF

ANI2_IO0 ANI2_IO1 ANI2_IO2 ANI2_IO3

ANI2_IO4 ANI2_IO5 ANI2_IO6

U8600

S3X

BGA-H1P35

SYM 1 OF 7

ANI1_IO0 ANI1_IO1 ANI1_IO2 ANI1_IO3 ANI1_IO4 ANI1_IO5 ANI1_IO6 ANI1_IO7

ANI1_NCE(0) ANI1_NCE(1) ANI1_NCE(2) ANI1_NCE(3) ANI1_NCE(4) ANI1_NCE(5) ANI1_NCE(6) ANI1_NCE(7)

ANI1_ALE ANI1_CLE ANI1_NWE ANI1_RNB

ANI1_PPM_IN

ANI1_PPM_OUT

ANI1_NRE_P ANI1_NRE_N

ANI1_DQS_P ANI1_DQS_N

ANI1_VREF

ANI3_IO0

ANI3_IO1

ANI3_IO2

ANI3_IO3

ANI3_IO4

ANI3_IO5 ANI3_IO6 ANI3_IO7ANI2_IO7

ANI2_NCE(0) ANI2_NCE(1) ANI2_NCE(2) ANI2_NCE(3) ANI2_NCE(4) ANI2_NCE(5) ANI2_NCE(6) ANI2_NCE(7)

ANI2_ALE ANI2_CLE ANI2_NWE ANI2_RNB

ANI2_PPM_IN

ANI3_NCE(0) ANI3_NCE(1) ANI3_NCE(2) ANI3_NCE(3) ANI3_NCE(4) ANI3_NCE(5) ANI3_NCE(6) ANI3_NCE(7)

ANI3_ALE ANI3_CLE ANI3_NWE ANI3_RNB

ANI3_PPM_IN

ANI2_PPM_OUT ANI3_PPM_OUT

ANI2_NRE_P ANI2_NRE_N

ANI2_DQS_P ANI2_DQS_N

ANI2_VREF

ANI3_NRE_P ANI3_NRE_N

ANI3_DQS_P ANI3_DQS_N

ANI3_VREF

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

OUT

86

OUT

86

OUT

86

OUT

102

OUT

102

OUT

102

OUT

102

OUT

86

86 86

86

OUT

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

OUT

86

OUT

86

OUT

86

OUT

102

OUT

102

OUT

102

OUT

102

OUT

86

OUT OUT

ANI0_IO<0> ANI0_IO<1> ANI0_IO<2> ANI0_IO<3> ANI0_IO<4> ANI0_IO<5> ANI0_IO<6> ANI0_IO<7>

ANI0_NCE<0> ANI0_NCE<1> ANI0_NCE<2> ANI0_NCE<3> NC_ANI0_NCE4 NC_ANI0_NCE5 NC_ANI0_NCE6 NC_ANI0_NCE7

ANI0_ALE ANI0_CLE ANI0_NWE ANI0_RNB

ANI0_NRE_P ANI0_NRE_N

ANI0_DQS_P ANI0_DQS_N

ANI01_VREF

ANI2_IO<0> ANI2_IO<1> ANI2_IO<2> ANI2_IO<3> ANI2_IO<4> ANI2_IO<5> ANI2_IO<6> ANI2_IO<7>

ANI2_NCE<0> ANI2_NCE<1> ANI2_NCE<2> ANI2_NCE<3> NC_ANI2_NCE4 NC_ANI2_NCE5 NC_ANI2_NCE6

ANI2_ALE ANI2_CLE ANI2_NWE ANI2_RNB

ANI2_NRE_P ANI2_NRE_N

ANI2_DQS_P ANI2_DQS_N

ANI23_VREF

T29 U30 U29 U28 Y30 Y29 AA30 AA29

AJ24 AG26 AH26 AF24 AF26 AK24 AE24 AH24

AK26 AG24 AA28 AJ26

AF25 AH25

W30 W29

V30 V29

T30

R29 P28 P29 P30 L29 L30 K29 K30

A26 D24 A24 D25 D23 E24 D26 B25

E25 E26 K28 B24

F23 E23

M29 M30

N29 N30

R30

ANI1_IO<0> ANI1_IO<1> ANI1_IO<2> ANI1_IO<3> ANI1_IO<4> ANI1_IO<5> ANI1_IO<6> ANI1_IO<7>

ANI1_NCE<0> ANI1_NCE<1> ANI1_NCE<2> ANI1_NCE<3> NC_ANI1_NCE4 NC_ANI1_NCE5 NC_ANI1_NCE6 NC_ANI1_NCE7

ANI1_ALE ANI1_CLE ANI1_NWE NC_ANI1_RNB

NC NC

ANI1_NRE_P ANI1_NRE_N

ANI1_DQS_P ANI1_DQS_N

ANI01_VREF

ANI3_IO<0> ANI3_IO<1> ANI3_IO<2> ANI3_IO<3> ANI3_IO<4> ANI3_IO<5> ANI3_IO<6> ANI3_IO<7>

ANI3_NCE<0> ANI3_NCE<1> ANI3_NCE<2> ANI3_NCE<3> NC_ANI3_NCE4 NC_ANI3_NCE5 NC_ANI3_NCE6 NC_ANI3_NCE7NC_ANI2_NCE7

ANI3_ALE ANI3_CLE ANI3_NWE NC_ANI3_RNB

NC NC

ANI3_NRE_P ANI3_NRE_N

ANI3_DQS_P ANI3_DQS_N

ANI23_VREF

OUT

86

102

86

OUT

86

102

86

BI

86

102

86

102

345678

2 1

NAND INTERFACE 2/3 TOP

PP1V8_SSD_COLD

20%

6.3V X5R

1

2

C9124

1.0UF

0201-1

C9125

0.22UF

20%

6.3V

X6S-CERM

0201

10%

6.3V

0201

1

C9133

0.1UF

2

CERM-X5R

1

C9126

0.1UF

2

CERM-X5R

10%

6.3V

0201

1

C9134

0.1UF

2

CERM-X5R

10%

6.3V

0201

1

2

C9127

12PF

5%

25V

NP0-C0G

0201

104 88 87 86 85 84 82 81 19

PP3V3_2V7_NAND_VCC

1

C9122

1.0UF

20%

6.3V

2

X5R 0201-1

1

C9123

0.22UF

20%

6.3V

2

X6S-CERM 0201

25V

0201

1

C9120

0.1UF

2

CERM-X5R

10%

6.3V

0201

1

2

C9121

0.22UF

20%

6.3V

X6S-CERM

0201

1

2

1

2

C9128

3.0PF

+/-0.1PF

NP0-C0G

D

OA8

OC0

OD0

OF8

OB0

OC8

OD8

OE0

VCC

OMIT_TABLE

U9120

GND

D4

K4

OA0

NC NC NC NC

N3

IO0-0

N5

IO1-0

M2

IO2-0

M6

IO3-0

L5

IO4-0

K6

IO5-0

K2

IO6-0

J3

IO7-0

A3

IO0-1

A5

IO1-1

B2

IO2-1

B6

IO3-1

C5

IO4-1

D6

IO5-1

D2

IO6-1

E3

IO7-1

G7

NC_G7

G1

NC_G1

G0

NC_G0

G5

NC_G5

G3

ZQ

104 88 87 86 85 84 82 81 19

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86

BI

86 81

86

BI

ANI2_IO<0> ANI2_IO<1> ANI2_IO<2> ANI2_IO<3> ANI2_IO<4> ANI2_IO<5> ANI2_IO<6> ANI2_IO<7>

ANI3_IO<0> ANI3_IO<1> ANI3_IO<2> ANI3_IO<3> ANI3_IO<4> ANI3_IO<5> ANI3_IO<6> ANI3_IO<7>

NAND INTERFACE 0/1 TOP

PP1V8_SSD_COLD

101 88 87 86

10%

6.3V

0201

86

1

2

BI

C9100

0.1UF

CERM-X5R

86 81

PP3V3_2V7_NAND_VCC

20%

6.3V

0201

1

2

C9101

0.22UF

X6S-CERM

ANI0_IO<0> ANI0_IO<1> ANI0_IO<2> ANI0_IO<3> ANI0_IO<4> ANI0_IO<5> ANI0_IO<6> ANI0_IO<7>

ANI1_IO<0> ANI1_IO<1> ANI1_IO<2> ANI1_IO<3> ANI1_IO<4> ANI1_IO<5> ANI1_IO<6> ANI1_IO<7>

1

C9102

1.0UF

20%

6.3V

2

X5R 0201-1

NC NC NC NC

N3 N5 M2 M6 L5 K6 K2 J3

A3 A5 B2 B6 C5 D6 D2 E3

G7 G1 G0 G5

1

2

IO0-0 IO1-0 IO2-0 IO3-0 IO4-0 IO5-0 IO6-0 IO7-0

IO0-1 IO1-1 IO2-1 IO3-1 IO4-1 IO5-1 IO6-1 IO7-1

NC_G7 NC_G1

NC_G0

NC_G5

C9103

1.0UF

20%

6.3V X5R 0201-1

OA8

OC0

VCC

OD0

OF8

OB0

OMIT_TABLE

U9100

LGA

NAND-15NM-64GB-2.8V

20%

6.3V X5R

1

C9105

0.22UF

2

X6S-CERM

OC8

OD8

C9104

1.0UF

0201-1

OE0

VCCQ

RE0

WP*

RE1

N1 L7 J7 N7

J5 H4

M4 L3

H6 F6

A1 C7 E7 A7

E5 F4

B4 C3

CE0* CLE0 ALE0 WE0*

RE0*

DQS0

DQS0*

R/B*

1Z-64GB-2P-MLC-DDP

CE1* CLE1 ALE1 WE1*

RE1*

DQS1

DQS1*

ANI0_NCE<0> ANI0_CLE ANI0_ALE ANI0_NWE

ANI0_NRE_N ANI0_NRE_P

ANI0_DQS_P ANI0_DQS_N

88

87 86

NAND_WP_L

ANI1_NCE<0> ANI1_CLE ANI1_ALE ANI1_NWE

ANI1_NRE_N ANI1_NRE_P

ANI1_DQS_P ANI1_DQS_N

20%

6.3V

0201

86

ANI0_RNB

10%

6.3V

0201

86

IN

1

C9113

0.1UF

2

86

CERM-X5R

1

R9100

10K

5% 1/20W MF 201

2

1

C9106

0.1UF

2

CERM-X5R

10%

6.3V

0201

1

C9114

0.1UF

2

CERM-X5R

NOSTUFF

1

R9101

1K

5% 1/20W MF 201

2

104 88 87 86 85 84 82 81 19

1

10%

6.3V

2

0201

NAND_ZQ_U9120

PP1V8_SSD_COLD

R9192

300

1 2

1%

1/20W

MF

201

VCCQ

RE0

WP*

RE1

N1 L7 J7 N7

J5 H4

M4 L3

H6 F6

A1 C7 E7 A7

E5 F4

B4 C3

G8

L1 C1 J1 E1 H2 F2

CE0*

LGA

CLE0 ALE0 WE0*

RE0*

DQS0

DQS0*

R/B*

1Z-64GB-2P-MLC-DDP

NAND-15NM-64GB-2.8V

CE1* CLE1 ALE1 WE1*

RE1*

DQS1

DQS1*

VREF

CE2* CE3* CE4* CE5* CE6* CE7*

OB8

OE8

OF0

ANI2_NCE<0> ANI2_CLE ANI2_ALE ANI2_NWE

ANI2_NRE_N ANI2_NRE_P

ANI2_DQS_P ANI2_DQS_N

86

ANI2_RNB

NAND_WP_L

ANI3_NCE<0> ANI3_CLE ANI3_ALE ANI3_NWE

ANI3_NRE_N ANI3_NRE_P

ANI3_DQS_P ANI3_DQS_N

ANI23_VREF

ANI2_NCE<1> ANI3_NCE<1> ANI2_NCE<2> ANI3_NCE<2> ANI2_NCE<3> ANI3_NCE<3>

86

IN

86

86 81

PP1V8_SSD_COLD

1

R9102

10K

5% 1/20W MF 201

2

88 87 86

104 88 87 82 81 19 86 85 84

C

B

A

101 88 87 86

PP3V3_2V7_NAND_VCC

1

C9187

20UF

20%

6.3V

2

CERM-X5R 0402

1

2

NAND_ZQ_U9100

C9188

20UF

20%

6.3V CERM-X5R 0402

R9190

1 2

1

C9189

20UF

20%

6.3V

2

CERM-X5R 0402

300

1%

1/20W

MF

201

G3

1

C9191

20UF

20%

6.3V

2

CERM-X5R 0402

ZQ

D4

K4

GND

OA0

OB8

OE8

OF0

VREF

CE2* CE3* CE4* CE5* CE6* CE7*

G8

L1 C1 J1 E1 H2 F2

ANI01_VREF

ANI0_NCE<1> ANI1_NCE<1> ANI0_NCE<2> ANI1_NCE<2> ANI0_NCE<3> ANI1_NCE<3>

IN

86

86 81

SYNC_DATE=09/25/2015SYNC_MASTER=J79_RUENJOU

PAGE TITLE

A

ANI[3:0]

DRAWING NUMBER SIZE

BOM_COST_GROUP=SSD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

91 OF 145

SHEET

86 OF 119

D

8 7 5 4 2 1

36

D

C

B

87 81

87

102

87

102

OUT

BI

OUT

BI

OUT

87

ANI4_IO<0> ANI4_IO<1> ANI4_IO<2> ANI4_IO<3> ANI4_IO<4> ANI4_IO<5> ANI4_IO<6> ANI4_IO<7>

ANI4_NCE<0> ANI4_NCE<1> ANI4_NCE<2> ANI4_NCE<3> NC_ANI4_NCE4 NC_ANI4_NCE5 NC_ANI4_NCE6 NC_ANI4_NCE7

ANI4_ALE ANI4_CLE ANI4_NWE ANI4_RNB

ANI4_NRE_P ANI4_NRE_N

ANI4_DQS_P ANI4_DQS_N

ANI45_VREF

ANI6_IO<0> ANI6_IO<1> ANI6_IO<2> ANI6_IO<3> ANI6_IO<4> ANI6_IO<5> ANI6_IO<6> ANI6_IO<7>

ANI6_NCE<0> ANI6_NCE<1> ANI6_NCE<2> ANI6_NCE<3> NC_ANI6_NCE4 NC_ANI6_NCE5 NC_ANI6_NCE6 NC_ANI6_NCE7

ANI6_ALE ANI6_CLE ANI6_NWE ANI6_RNB

ANI6_NRE_P ANI6_NRE_N

ANI6_DQS_P ANI6_DQS_N

ANI67_VREF

NC NC

H2 G3 G2 G1 D2 D1 C2 C1

G6 E7 E6 G7 D8 A6 H9 G8

D7 F6 C3 D6

B6 C6

E2 E1

F2 F1

H1

AC2 AD1 AD2 AD3 AG1 AG2 AH1 AH2

AK11 AJ11 AH10

AH9 AH12 AH11

AG9 AG11

AJ9

AK9

AH3 AG12

AG10 AF10

AF1

AF2

AE1

AE2

AC1

OMIT_TABLE

ANI4_IO0 ANI4_IO1 ANI4_IO2 ANI4_IO3 ANI4_IO4 ANI4_IO5 ANI4_IO6 ANI4_IO7

ANI4_NCE(0) ANI4_NCE(1) ANI4_NCE(2) ANI4_NCE(3) ANI4_NCE(4) ANI4_NCE(5) ANI4_NCE(6) ANI4_NCE(7)

ANI4_ALE ANI4_CLE ANI4_NWE ANI4_RNB

ANI4_PPM_IN ANI4_PPM_OUT

ANI4_NRE_P

U8600

S3X

BGA-H1P35

SYM 2 OF 7

ANI5_IO0 ANI5_IO1 ANI5_IO2 ANI5_IO3 ANI5_IO4 ANI5_IO5 ANI5_IO6 ANI5_IO7

ANI5_NCE(0) ANI5_NCE(1) ANI5_NCE(2) ANI5_NCE(3) ANI5_NCE(4) ANI5_NCE(5) ANI5_NCE(6) ANI5_NCE(7)

ANI5_ALE ANI5_CLE ANI5_NWE ANI5_RNB

ANI5_PPM_IN

ANI5_PPM_OUT

ANI5_NRE_P

ANI4_NRE_N ANI5_NRE_N

ANI4_DQS_P ANI4_DQS_N

ANI5_DQS_P ANI5_DQS_N

ANI4_VREF ANI5_VREF

ANI6_IO0 ANI6_IO1 ANI6_IO2 ANI6_IO3 ANI6_IO4 ANI6_IO5 ANI6_IO6 ANI6_IO7

ANI6_NCE(0) ANI6_NCE(1) ANI6_NCE(2) ANI6_NCE(3) ANI6_NCE(4) ANI6_NCE(5) ANI6_NCE(6) ANI6_NCE(7)

ANI6_ALE ANI6_CLE ANI6_NWE ANI6_RNB

ANI6_PPM_IN ANI6_PPM_OUT

ANI6_NRE_P ANI6_NRE_N

ANI6_DQS_P ANI6_DQS_N

ANI6_VREF

ANI7_IO0 ANI7_IO1 ANI7_IO2 ANI7_IO3 ANI7_IO4 ANI7_IO5 ANI7_IO6 ANI7_IO7

ANI7_NCE(0) ANI7_NCE(1) ANI7_NCE(2) ANI7_NCE(3) ANI7_NCE(4) ANI7_NCE(5) ANI7_NCE(6) ANI7_NCE(7)

ANI7_ALE ANI7_CLE ANI7_NWE ANI7_RNB

ANI7_PPM_IN

ANI7_PPM_OUT

ANI7_NRE_P ANI7_NRE_N

ANI7_DQS_P ANI7_DQS_N

ANI7_VREF

R2 P3 P2 P1 L2 L1 K2 K1

B3 D4 E4 B4 A4 D5 B5 A5

F4 A3 K3 C4

G5 E5

M2 M1

N2 N1

R1

T2 U1 U2 U3 Y1 Y2 AA1 AA2

AK5 AK7 AJ7 AJ5 AH5 AH7 AG7 AG5

AG6 AH6 AA3 AF6

AG8 AH8

W1 W2

V1 V2

T1

NC NC

ANI5_IO<0> ANI5_IO<1> ANI5_IO<2> ANI5_IO<3> ANI5_IO<4> ANI5_IO<5> ANI5_IO<6> ANI5_IO<7>

ANI5_NCE<0> ANI5_NCE<1> ANI5_NCE<2> ANI5_NCE<3> NC_ANI5_NCE4 NC_ANI5_NCE5 NC_ANI5_NCE6 NC_ANI5_NCE7

ANI5_ALE ANI5_CLE ANI5_NWE NC_ANI5_RNB

ANI5_NRE_P ANI5_NRE_N

ANI5_DQS_P ANI5_DQS_N

ANI45_VREF

ANI7_IO<0> ANI7_IO<1> ANI7_IO<2> ANI7_IO<3> ANI7_IO<4> ANI7_IO<5> ANI7_IO<6> ANI7_IO<7>

ANI7_NCE<0> ANI7_NCE<1> ANI7_NCE<2> ANI7_NCE<3> NC_ANI7_NCE4 NC_ANI7_NCE5 NC_ANI7_NCE6 NC_ANI7_NCE7

ANI7_ALE ANI7_CLE ANI7_NWE NC_ANI7_RNB

ANI7_NRE_P ANI7_NRE_N

ANI7_DQS_P ANI7_DQS_N

ANI67_VREF

87

OUT

BI

87

102

87

102

345678

2 1

NAND INTERFACE 6/7

10%

104 88 87 86 85 84 82 81 19

1

C9220

0.1UF

2

CERM-X5R

10%

6.3V

0201

1

C9221

0.1UF

2

CERM-X5R

10%

6.3V

0201

1

2

C9227

12PF

5%

25V

NP0-C0G

0201

PP3V3_2V7_NAND_VCC

1

2

C9228

3.0PF

+/-0.1PF

NP0-C0G

25V

0201

1

C9212

0.1UF

2

CERM-X5R

10%

6.3V

0201

1

C9211

0.22UF

2

X6S-CERM

20%

6.3V

0201

1

2

1

C9215

1.0UF

20%

6.3V

2

X5R 0201-1

1

C9216

1.0UF

20%

6.3V

2

X5R 0201-1

PP1V8_SSD_COLD

20%

6.3V X5R

1

2

C9217

1.0UF

0201-1

C9218

0.22UF

20%

6.3V

X6S-CERM

0201

1

C9219

0.1UF

2

6.3V

CERM-X5R

0201

D

OA8

OC0

OD0

OF8

OB0

OC8

OD8

OE0

VCC

OMIT_TABLE

U9220

GND

D4

K4

OA0

NC NC NC NC

N3

IO0-0

N5

IO1-0

M2

IO2-0

M6

IO3-0

L5

IO4-0

K6

IO5-0

K2

IO6-0

J3

IO7-0

A3

IO0-1

A5

IO1-1

B2

IO2-1

B6

IO3-1

C5

IO4-1

D6

IO5-1

D2

IO6-1

E3

IO7-1

G7

NC_G7

G1

NC_G1

G0

NC_G0

G5

NC_G5

G3

ZQ

88 87 86 85 84 82 81

87

BI

87

BI

87

BI

87

BI

87

BI

87

BI

87

BI

87

BI

87

BI

87

BI

87

BI

87

BI

87

BI

87

87 81

NAND INTERFACE 4/5

87

BI

PP1V8_SSD_COLD

101 88 87 86

10%

6.3V

0201

1

2

C9200

0.1UF

CERM-X5R

87 81

PP3V3_2V7_NAND_VCC

C9201

0.22UF

20%

6.3V

X6S-CERM

0201

87

BI

ANI4_IO<0> ANI4_IO<1> ANI4_IO<2> ANI4_IO<3> ANI4_IO<4> ANI4_IO<5> ANI4_IO<6> ANI4_IO<7>

ANI5_IO<0> ANI5_IO<1> ANI5_IO<2> ANI5_IO<3> ANI5_IO<4> ANI5_IO<5> ANI5_IO<6> ANI5_IO<7>

20%

6.3V X5R

CE0* CLE0 ALE0 WE0*

RE0

RE0*

DQS0

DQS0*

R/B*

WP*

CE1* CLE1 ALE1 WE1*

RE1

RE1*

DQS1

DQS1*

1

C9205

0.22UF

2

N1 L7 J7 N7

J5 H4

M4 L3

H6 F6

A1 C7 E7 A7

E5 F4

B4 C3

X6S-CERM

ANI4_NCE<0> ANI4_CLE ANI4_ALE ANI4_NWE

ANI4_NRE_N ANI4_NRE_P

ANI4_DQS_P ANI4_DQS_N

87

NAND_WP_L

ANI5_NCE<0> ANI5_CLE ANI5_ALE ANI5_NWE

ANI5_NRE_N ANI5_NRE_P

ANI5_DQS_P ANI5_DQS_N

C9204

1.0UF

0201-1

N3 N5 M2 M6 L5 K6 K2 J3

A3 A5 B2 B6 C5 D6 D2 E3

G7 G1 G0 G5

1

C9203

1.0UF

20%

6.3V

2

X5R 0201-1

IO0-0 IO1-0 IO2-0 IO3-0 IO4-0 IO5-0 IO6-0 IO7-0

IO0-1 IO1-1 IO2-1 IO3-1 IO4-1 IO5-1 IO6-1 IO7-1

NC_G7 NC_G1

NC_G0

NC_G5

OA8

OC0

OD0

OF8

VCC

OMIT_TABLE

OB0

OC8

OD8

OE0

VCCQ

U9200

LGA

1Z-64GB-2P-MLC-DDP

NAND-15NM-64GB-2.8V

1

2

1

C9202

1.0UF

20%

6.3V

2

X5R 0201-1

NC NC NC NC

1

20%

6.3V

2

0201

ANI4_RNB

C9206

0.1UF

CERM-X5R

10%

6.3V

0201

87

IN

1

C9213

0.1UF

2

87

CERM-X5R

PP1V8_SSD_COLD

1

R9200

10K

5% 1/20W MF 201

2

87

10%

6.3V

0201

1

2

NAND_ZQ_U9220

88 87 86

C9214

0.1UF

10%

6.3V

CERM-X5R

0201

ANI6_IO<0> ANI6_IO<1> ANI6_IO<2> ANI6_IO<3> ANI6_IO<4> ANI6_IO<5> ANI6_IO<6> ANI6_IO<7>

ANI7_IO<0> ANI7_IO<1> ANI7_IO<2> ANI7_IO<3> ANI7_IO<4> ANI7_IO<5> ANI7_IO<6> ANI7_IO<7>

104 88 87 86 85 84 82 81 19

1

2

1 2

19 104

R9292

300

1%

1/20W

MF

201

VCCQ

RE0

WP*

RE1

N1 L7 J7 N7

J5 H4

M4 L3

H6 F6

A1 C7 E7 A7

E5 F4

B4 C3

G8

L1 C1 J1 E1 H2 F2

CE0*

LGA

CLE0 ALE0 WE0*

RE0*

DQS0

DQS0*

R/B*

1Z-64GB-2P-MLC-DDP

NAND-15NM-64GB-2.8V

CE1* CLE1 ALE1 WE1*

RE1*

DQS1

DQS1*

VREF

CE2* CE3* CE4* CE5* CE6* CE7*

OB8

OE8

OF0

ANI6_NCE<0> ANI6_CLE ANI6_ALE ANI6_NWE

ANI6_NRE_N ANI6_NRE_P

ANI6_DQS_P ANI6_DQS_N

87

ANI6_RNB

NAND_WP_L

ANI7_NCE<0> ANI7_CLE ANI7_ALE ANI7_NWE

ANI7_NRE_N ANI7_NRE_P

ANI7_DQS_P ANI7_DQS_N

ANI67_VREF

ANI6_NCE<1> ANI7_NCE<1> ANI6_NCE<2> ANI7_NCE<2> ANI6_NCE<3> ANI7_NCE<3>

87

IN

87

PP1V8_SSD_COLD

1

R9201

10K

5% 1/20W MF 201

2

88 87 86

87 81

104 88 87 82 81 19 86 85 84

C

B

A

NAND_ZQ_U9200

R9290

300

1 2

1%

1/20W

MF

201

G3

ZQ

D4

K4

GND

OA0

OB8

OE8

OF0

VREF

CE2* CE3* CE4* CE5* CE6* CE7*

G8

L1 C1 J1 E1 H2 F2

ANI45_VREF

ANI4_NCE<1> ANI5_NCE<1> ANI4_NCE<2> ANI5_NCE<2> ANI4_NCE<3> ANI5_NCE<3>

IN

87

87 81

SYNC_DATE=09/25/2015SYNC_MASTER=J79_RUENJOU

PAGE TITLE

A

ANI[7:4]

DRAWING NUMBER SIZE

BOM_COST_GROUP=SSD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

92 OF 145

SHEET

87 OF 119

D

8 7 5 4 2 1

36

345678

2 1

D

C

PP3V3_S5_SSD

84 88

101

1

C9300

0.1UF

20% 16V

2

X6S-CERM 0201

PP3V3_S5_SSD

84 88 101

PP3V3_S5_SSD

84 88 101

1

C9320

10UF

20%

6.3V

2

CERM-X6S 0402

1

C9301

4.7UF

20%

6.3V

2

X6S 0402

1

C9321

2

10UF

20%

6.3V CERM-X6S 0402

1

C9302

4.7UF

20%

6.3V

2

X6S 0402

1

C9313

0.1UF

20% 16V

2

X6S-CERM 0201

1

C9329

0.1UF

20% 16V

2

X6S-CERM 0201

M1

VDD_BUCK1

M2

VDD_BUCK1

H1

VDD_BUCK5

L6

VDD_BUCK0_01

M6

VDD_BUCK0_01

U9300

D2331

WLCSP

SYM 2 OF 8

OMIT_TABLE

U9300

D2331

WLCSP

SYM 1 OF 8

OMIT_TABLE

BUCK1_FB_DIS

BUCK1_LX0

BUCK5_FB_DIS

BUCK5_LX0

VSS(VSS_BUCK1_5)

BUCK0_FB_DIS

BUCK0_LX0 BUCK0_LX0

BUCK0_LX1 BUCK0_LX1

VSS(VSS_BUCK0) VSS(VSS_BUCK0) VSS(VSS_BUCK0)

K3

VOLTAGE=0.9V

L1

P0V9_FIXED_SW

SWITCH_NODE=TRUE

J3

VR_P1V8_HOT_FB

J1

P1V8_HOT_SW

DIDT=TRUE

K1

J4

L5 M5

L7 M7

L8 M4 M8

SWITCH_NODE=TRUE

VOLTAGE=0.9V

P0V9_REG_SW0

DIDT=TRUE

SWITCH_NODE=TRUE

P0V9_REG_SW1

DIDT=TRUE

SWITCH_NODE=TRUE

VOLTAGE=0.9V

VR_P0V9_FIXED_FB

L9300

1UH-20%-2.2A-0.072OHM

1 2

DIDT=TRUE

VOLTAGE=1.8V

0806

L9310

1UH-20%-1.01A-0.202OHM

1 2

PSB12101T-SM

VR_P0V9_REG_FB

L9320

1UH-20%-3.8A-0.035OHM

1 2

PIFE32251B-SM

104 82

L9321

1UH-20%-3.8A-0.035OHM

1 2

PIFE32251B-SM

82

PP0V9_SSD_FIXED

VOLTAGE=0.9V

PP1V8_SSD_HOT

VOLTAGE=1.8V

PP0V9_SSD_REG

VOLTAGE=0.9V

1

C9328

1000PF

10% 25V

2

X7R 0201

1

R9300

0

5% 1/20W MF 201

2

1

R9310

0

5% 1/20W MF 201

2

1

C9310

20UF

20%

6.3V

2

CERM-X5R 0402

1

R9320

0

5% 1/20W MF 201

2

1

C9322

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9303

20UF

20%

6.3V

2

CERM-X5R 0402

1

C9311

4.7UF

20%

6.3V

2

X6S 0402

C9317

12PF

5%

25V

NP0-C0G

0201

1

C9323

22UF

20% 10V

2

X5R-CERM 0603-1

PICCOLO I2C INTERFACE ADDRESSES WRITE:78H

1

C9307

12PF

5% 25V

2

NP0-C0G 0201

1

C9304

2.2UF

20% 10V

2

CER-X6S 0402

1

C9312

1000PF

10% 25V

2

X7R 0201

25V

0201

1

2

1

2

C9318

3.0PF

+/-0.1PF

NP0-C0G

1

C9324

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9308

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C9305

2.2UF

20% 10V

2

CER-X6S 0402

1

C9325

22UF

20% 10V

2

X5R-CERM 0603-1

84 88 101

81

SSD_DBG_UART_R2D_R

19

1

C9326

12PF

5% 25V

2

NP0-C0G 0201

READ:79H

1

R9357

100K

5% 1/20W MF 201

2

1

2

PP3V3_S5_SSD

NOSTUFF

1

R9373

10K

5% 1/20W MF 201

2

IN

104 84

50

R9377

1/20W

101 88 87 86

1

C9327

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

R9358

100K

5% 1/20W MF 201

81

IN

1

1K

1% MF

201

2

PP3V3_2V7_NAND_VCC

81

S3X_PMIC_LOW_PWR

81

S3X_PMIC_EXT_CLK_DIS

81

BI

85 81

IN

85 81

S3X_DEBUG_UART_D2R

S3X_SMC_OOB_UART_D2R

SSD_DBG_UART_R2D

SMC_OOB1_R2D_L

89 88

88

BI

P2V7NAND_PGOOD PICCOLO_POK2

89 88

S3X_PMIC_CTRL0 S3X_PMIC_CTRL1

S3X_RET_LPSR_CLEAR

S3X_PCIE_CLKREQ_L

1

R9376

1K

1% 1/20W MF 201

2

P2V7NAND_PGOOD

S3X_I2C_SCL S3X_I2C_SDA

G5 G7

H6 H8

D8 C8

E7

PMIC_LOW_POWER

C6

PMIC_EXT_CLK_DIS

C4

PMIC_CTRL0/DEBUG

C5

PMIC_CTRL1

E8

RET_LPSR_CLEAR

PCIE_CLKREQ_L_1.8V

F5

I2C_SCL

F6

I2C_SDA

LS1P8_IN1 LS1P8_IN2

LS3P3_IN1 LS3P3_IN2

POK1 POK2

84 88 101

U9300

D2331

WLCSP

SYM 6 OF 8

OMIT_TABLE

PP3V3_S5_SSD

PICCOLO_POK2

88

U9300

D2331

WLCSP

SYM 4 OF 8

OMIT_TABLE

LS1P8_OUT1 LS1P8_OUT2

LS3P3_OUT1 LS3P3_OUT2

PFN PERST* RESET*

BOOT_FROM_LPSR

LPDDR3_RET*

G6

S3X_DEBUG_UART_R2D

G8

H5

SSD_DBG_UART_D2R_R

H7

SMC_OOB_UART_D2R_R

D7

VEN1 VEN2

1

R9375

20K

5% 1/20W MF 201

2

PICCOLO_VEN1

C7

NC_PICCOLO_VEN2

C3 J2 D3 G4

C2K2

S3X_SMC_OOB_UART_R2D

S3X_PFN

S3X_PERST_L S3X_RESET_L

S3X_COLD_BOOT_L

S3X_RET_EN_L

PP1V8_SSD_COLD

NOSTUFF

1

R9371

10K

5% 1/20W MF 201

2

89

105

OUT

R9378

1 2

1/20W

MF

100

OUT

1

R9372

10K

5% 1/20W MF 201

2

81

SSD_DBG_UART_D2R

201

5%

81

R9379

1 2

5%MF

100

201

1/20W

SMC_OOB1_D2R_L

D

104 84 19

50

OUT

C

104 88 87 86 85 84 82 81 19

B

A

PP3V3_S5_SSD

84 88 101

1

C9330

0.1UF

20% 16V

2

X6S-CERM 0201

PPVIN_2V7NAND_LB

89 91

R9350

1.3M

1/20W

0201

1

C9362

220PF

10% 25V

2

X7R-CERM 201

1

C9331

4.7UF

20%

6.3V

2

X6S 0402

PP3V3_S5_SSD

84 88 101

1

C9333

0.1UF

20% 16V

2

X6S-CERM 0201

PP3V3_S5_SSD

84 88 101

1

C9350

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

IUVD VDIVIDER:

3S - 215K 2S - 348K

1

1% MF

2

1

R9351

215K

1% 1/20W MF 201

2

1

C9332

4.7UF

20%

6.3V

2

X6S 0402

1

C9347

2

1

C9351

0.1UF

20% 16V

2

X6S-CERM 0201

R9351

1

R9355

10K

1% 1/20W MF 201

2

10UF

20%

6.3V CERM-X6S 0402

88 87 86

88 82

1

C9348

10UF

20%

6.3V

2

CERM-X6S 0402

104 88 87 86 85 84 82 81 19

1

C9352

0.1UF

20% 16V

2

X6S-CERM 0201

PP3V3_2V7_NAND_VCC

101

88

PICCOLO_IUVD

1

C9353

0.1UF

10%

6.3V

2

X7R 0201

PICCOLO_VPP_OTP

PP1V2_SSD_HOT

U9300

D2331

WLCSP

A2

VDD_BUCK3 BUCK3_FB_DIS

A6

VDD_BUCK4_01

B6

VDD_BUCK4_01

PP1V8_SSD_COLD

SYM 3 OF 8

OMIT_TABLE

J5E1H4

D5

B2

VPUMP

VCORE_D

VCORE_A

V_BUF_1.8V

BUCK3_LX0 BUCK3_LX0

VSS(VSS_BUCK3_4) VSS(VSS_BUCK3_4)

BUCK4_FB_DIS

BUCK4_LX0 BUCK4_LX0

BUCK4_LX1 BUCK4_LX1

VSS(VSS_BUCK4) VSS(VSS_BUCK4)

PICCOLO_VPUMP

U9300

D2331

WLCSP

SYM 7 OF 8

VSENSE1

F3

VSENSE2

E2

IUVD

VPP_OTP

A1

1.2V_COLD_IN

B1

1.2V_COLD_IN

OMIT_TABLE

1.2V_COLD_OUT

VREF IREF

VCC_DIS

VDD_RTC

D2

A3 B3

A4 B4

E5

A5 B5

A7 B7

A8 B8

G2F1 F2

VR_P1V2_HOT_FB

P1V2_HOT_SW

DIDT=TRUE

SWITCH_NODE=TRUE

VR_P1V8_COLD_FB

P1V8_COLD_SW0

DIDT=TRUE

SWITCH_NODE=TRUE

P1V8_COLD_SW1

DIDT=TRUE

SWITCH_NODE=TRUE

VOLTAGE=1.8V

1

C9354

0.01UF

10% 25V

2

X7R 402

PICCOLO_VREF PICCOLO_IREF

PP3V3_2V7_NAND_VCC

G1E6

C1

PICCOLO_VDD_RTC

82

PP1V2_SSD_COLD

1

C9356

22UF

20% 10V

2

X5R-CERM 0603-1

R9330

0

1 2

5%

1/20W

MF

201

VOLTAGE=1.2V

R9340

0

1 2

5%

1/20W

MF

201

VOLTAGE=1.8V

VOLTAGE=1.2V

NOSTUFF

1

C9357

22UF

20% 10V

2

X5R-CERM 0603-1

L9330

1UH-20%-2.2A-0.072OHM

1 2

0806

L9340

1.0UH-20%-2.7A-55MOHM

1 2

PIFE25201B-SM

104 88 87 86 85

L9341

1.0UH-20%-2.7A-55MOHM

1 2

PIFE25201B-SM

101 88 87 86

1

C9358

1000PF

10% 25V

2

X7R 0201

1

C9377

12PF

5% 25V

2

NP0-C0G 0201

88 82

PP1V2_SSD_HOT

VOLTAGE=1.2V

84 82 81 19

PP1V8_SSD_COLD

VOLTAGE=1.8V

1

C9378

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

C9334

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9340

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9344

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9363

12PF

5% 25V

2

NP0-C0G 0201

PLACE_NEAR=U9300.F2:1.0MM

1

C9359

0.1UF

10%

6.3V

2

X7R 0201

1

2

1

C9341

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9345

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9364

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

R9360

200K

1% 1/20W MF 201

2

C9335

22UF

20% 10V X5R-CERM 0603-1

1

2

1

C9342

22UF

20% 10V

2

X5R-CERM 0603-1

1

C9346

0.01UF

2

1

C9365

12PF

5% 25V

2

NP0-C0G 0201

1

C9361

0.1UF

2

C9336

1000PF

10% 25V X7R 0201

10% 10V X5R-CERM 0201

10%

6.3V X7R 0201

1

C9343

22UF

20% 10V

2

X5R-CERM 0603-1

1

2

1

2

1

C9337

12PF

5% 25V

2

NP0-C0G 0201

C9367

12PF

5% 25V NP0-C0G 0201

C9366

3.0PF

+/-0.1PF 25V NP0-C0G 0201

**NEED PID GPIO OPTION TABLE**

PP3V3_S5_SSD

84 88 101

1

C9338

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

R9380

10K

5% 1/20W MF 201

2

1

R9386

0

5% 1/20W MF 201

2

PICCOLO_PID0 PICCOLO_PID1

LPSR_EN_LB_L

PICCOLO_NOR_CS_L

1

C9368

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

R9383

10K

5% 1/20W MF 201

2

91

91 84 81

88 84

91

91 88

IN

SSD_PCIE_CLKREQ_LB_L

BI

IN

88

STORAGE_LB_EN

SSD_RESET_LB_L

PD_L

U9300

D2331

WLCSP

D4 E4 F4 F8 K4 G3

VSS VSS VSS VSS VSS VSS

SYM 8 OF 8

OMIT_TABLE

BOM_COST_GROUP=SSD

VSS VSS VSS VSS VSS

D1 H3 K5 L3 H2

PID0

F7

PID1

K8

LPSR_EN*

K7

NOR_CS*

L2

STORAGE_EN

L4

STORAGE_RST*

K6

PD*

M3

PCIE_CLKREQ*

89 88

P2V7NAND_PGOOD

PICCOLO_POK2

88

91 84 81

SSD_BOOT_LB_L

PP3V3_S5_SSD

84 88 101

1

R9384

10K

5% 1/20W

U9300

D2331

WLCSP

SYM 5 OF 8

OMIT_TABLE

PGOOD

WP*

STORAGE_LATCH

24_CLK_REQ

E3J7

PICCOLO_PGOOD

D6

PICCOLO_WP_L

J8

J6

1

R9385

0

5% 1/20W MF 201

2

NAND_WP_L

SSD_PWR_REQ

2

MF 201

OUT

NC_PICCOLO_24M_CLK_REQ

P2MM

SM

88

P2MM

SM

1

PP

P2MM

SM

1

PP

SYNC_MASTER=J79_RUENJOU SYNC_DATE=09/24/2015

PAGE TITLE

PP9305

PP9306

88 84

91 88

88

PICCOLO_IUVD

PD_L

LPSR_EN_LB_L

PICCOLO_NOR_CS_L

1

P2MM

1

P2MM

1

P2MM

1

PP

SM

PP

SM

PP

SM

PP

PP9301

PP9302

PP9303

PP9304

PICCOLO PMIC

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

051-00515

REVISION

9.0.0

BRANCH

dvt-fab09-0

PAGE

93 OF 145

SHEET

88 OF 119

B

87 86

84 77

102

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

PP3V3_2V7_NAND_VCC

89 101

2

XW9430

SM

1

2

XW9431

SM

1

P2V7NAND_RFB_PP2V7NAND_RFB_N

1

R9431

10K

0.1% 1/20W MF 0201-1

2

NO_XNET_CONNECTION=1

88

IN

10K

0.1%

1/20W

MF

1

2

R9403

0201-1

NO_XNET_CONNECTION=1

Change R3505 and R3531 to 0.1% when available

C9423

0.01UF

X7R-CERM

0201

1

C9426

10PF

5% 50V

2

C0G 0201

1

R9404

10K

0.1% 1/20W MF 0201-1

2

1

R9402

10K

0.1% 1/20W MF 0201-1

2

1

C9415

10PF

5% 50V

2

C0G 0201

PICCOLO_VEN1

1

10% 10V

2

R9420

0

5%

1/20W

MF

201

1

R9417

191K

0.1% 1/20W MF 0201

2

1

R9418

95.3K

0.1% 1/20W MF 0201

2

1

2

P2V7NAND_SET_R

R9400

16.9K

1 2

1%

1/20W

MF

201

12

C9417

22PF

5% 50V C0G 0201

PP2V7_NAND_VCC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=2.7V

1

C9422

1UF

10% 16V

2

X6S-CERM 0402

P2V7NAND_EN

P2V7NAND_SENSE_DIV

P2V7NAND_SREF

P2V7NAND_PGOOD_R

89

P2V7NAND_RTN_DIV

P2V7NAND_FSEL

100K

1%

1/20W

MF

201

1

2

R9413

PP5V_S4_P2V7NAND_LB

P2V7NAND_VO

P2V7NAND_OCSET

P2V7NAND_SET0

P2V7NAND_SET1

R9401

EN

10

FB

7

SREF

12

VO

11

OCSET

14

PGOOD

4

RTN

13

FSEL

8

SET0

9

SET1

6

VID0

5

VID1

1

10

5%

1/20W

MF

201

2

19

U9400

ISL95870AH

UTQFN

CRITICAL

3

1

R9406

2.2

5% 1/16W MF-LF 402

2

20

PVCCVCC

PGNDGND

2

PP2V7_NAND_PVCC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=2.7V

1

C9421

2.2UF

20% 10V

2

CER-X6S 0402

P2V7NAND_VBST

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

BOOT

UGATE

PHASE

LGATE

1815

17

16

1

P2V7NAND_DRVH_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUE DIDT=TRUE

P2V7NAND_LL

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 SWITCH_NODE=TRUE

DIDT=TRUE

P2V7NAND_DRVL_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUE DIDT=TRUE

91 88 91

R9409

2.2

5%

1/20W

MF

201

PPVIN_2V7NAND_LB

P2V7NAND_BOOT_RC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

1

2

C9416

0.1UF

10% 16V

2

X7R-CERM 0402

R9414

0

5%

1/20W

MF

201

R9415

0

12

5%

1/20W

MF

201

12

P2V7NAND_DRVH

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUE DIDT=TRUE

3

4

5

P2V7NAND_DRVL

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUE DIDT=TRUE

Q9401

CSD58873Q3D

Q3D

TG

TGR

BG

NOSTUFF

1

C9435

0.001UF

10% 50V

2

CERM 402

VSW

PGND

9

C9403

33UF

20%

CASE-B3

1

VIN

6 7 8

16V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 SWITCH_NODE=TRUE DIDT=TRUE

TANT-POLY

1

2

C9402

TANT-POLY

CASE-B3

2.2UH-20%-12A-0.0245OHM

P2V7NAND_SW

NOSTUFF

2.2

5% 1/10W MF-LF

603

1

2

R9435

P2V7NAND_SNUB

DIDT=TRUE

SWITCH_NODE=TRUE

1

33UF

20% 16V

2

152S00270

L9400

1 2

PIMB062D-SM

NO_XNET_CONNECTION=1

1

C9400

2.2UF

20% 25V

2

X6S-CERM 0402

1

C9401

2.2UF

20% 25V

2

X6S-CERM 0402

NO_XNET_CONNECTION=1

P2V7NAND_R

MIN_LINE_WIDTH=0.1160 MIN_NECK_WIDTH=0.0600

R9421

2

2.49K

1/20W 1%

201

1

MF

C9470

0.01UF

NO_XNET_CONNECTION=1

R9430

0.003

1 2 3 4

12

10% 10V

X7R-CERM

0201

1%

1/2W

MF

0306

1

C9404

1000PF

10% 25V

2

X7R 0201

2

R9472

2.49K

201

1

NOSTUFF

200

5% 1/16W MF-LF

402

1

2

57

R9410

ISNS_SSDNAND_P

ISNS_SSDNAND_N

1/20W 1%

MF

C9405

2.2UF

20% 10V

CER-X6S

0402

VOUT = 3.3V FREQ = 500 KHZ

MAX OCP = 8.51A Nom OCP = 7.06A

MIN OCP = 5.16A

20% 10V

0402

1

2

1

C9408

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

C9410

1000PF

1

2

NOSTUFF

1

C9409

150UF

20%

6.3V

2

POLY-TANT CASE-BL-SM

C9406

2.2UF

CER-X6S

PP3V3_2V7_NAND_VCC

1

10% 25V

2

X7R

0201

1

C9407

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

89 101

D

C

B

P2V7NAND_AGND

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000

R9411

0

5%

1/20W

MF

201

XW9400

SM

1 2

PLACE_NEAR=U9400.3:1MM

12

P2V7NAND_PGOOD_RP2V7NAND_PGOOD

CRITICAL

1

C9430

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE 5G DESENSE

89 88

CRITICAL

1

C9431

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

2.4G DESENSE 5G DESENSE

CRITICAL

1

C9432

12PF

5% 25V

2

NP0-C0G 0201

CRITICAL

1

C9433

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

B

A

PAGE TITLE

SSD NAND VR

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

94 OF 145

89 OF 119

D

A

SYNC_DATE=12/18/2015SYNC_MASTER=J79_JSHAO

345678

2 1

D

C

B

A

SYNC_MASTER=J14 SYNC_DATE=10/23/2012

PAGE TITLE

Empty

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

95 OF 145

90 OF 119

A

D

345678

2 1

D

C

PCH Side

PPBUS_G3H

100

PP5V_S4

101

104 14

104 13

104 84

104 19 16

102

105 15

15

102 104

SSD_BOOT_L SSD_PWR_EN_L STORAGE_EN

SSD_RESET_L SSD_CLKREQ_L

PCIE_SSD_D2R_P<0> PCIE_SSD_D2R_N<0>

PCIE_SSD_R2D_C_P<0> PCIE_SSD_R2D_C_N<0>

PCIE_CLK100M_SSD_P PCIE_CLK100M_SSD_N

SSD_SR_EN_L

LIFEBOAT

J9600

20759-042E-02

F-ST-SM

43 44

PWR

SIGNAL

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

GND_VOID=TRUE

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

GND_VOID=TRUE

SSD Side

PPVIN_2V7NAND_LB

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=13.1V

PP5V_S4_P2V7NAND_LB SSD_BOOT_LB_L SSD_PWR_EN_LB_L STORAGE_LB_EN

SSD_RESET_LB_L SSD_PCIE_CLKREQ_LB_L

PCIE_SSD_D2R_LB_P<0> PCIE_SSD_D2R_LB_N<0>

PCIE_SSD_R2D_LB_C_P<0> PCIE_SSD_R2D_LB_C_N<0>

PCIE_CLK100M_SSD_LB_P PCIE_CLK100M_SSD_LB_N

LPSR_EN_LB_L

D

89 88

89

84

88

81

84

88

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=5V

88 84 81

105 81

C

B

101

PP3V3_S5

PWR

45 46

GND

47 48

49 50

51 52

53 54

55 56

57 58

59 60

61 62

63 64

65 66

67 68

PP3V3_S5_SSD_LB

SIGNAL_MODEL=LIFEBOAT

101

B

A

PAGE TITLE

LIFEBOAT

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=SSD

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=09/09/2015SYNC_MASTER=J79_RUENJOU

051-00515

9.0.0

dvt-fab09-0

96 OF 145

91 OF 119

A

D

345678

2 1

D

C

B

A

1

RB090

3.3K

5% 1/20W MF 201

2

TBT_T_SPI_CLK

94

TBT_T_SPI_CS_L

94

TBT_T_ROM_WP_L

92

TBT_T_ROM_HOLD_L

34

IN

34

IN

34

IN

34

IN

34

IN

34

IN

34

IN

34

IN

34

BI

34

BI

34

IN

34

IN

34

IN

34

IN

34

IN

34

IN

34

IN

34

IN

34

BI

34

BI

100K

1 2

100K

1 2

1M

1 2

1M

1 2

1M

1 2

1M

1 2

DP_T_SNK0_ML_C_P<0>

DP_T_SNK0_ML_C_N<0>

DP_T_SNK0_ML_C_P<1>

DP_T_SNK0_ML_C_N<1>

DP_T_SNK0_ML_C_P<2>

DP_T_SNK0_ML_C_N<2>

DP_T_SNK0_ML_C_P<3>

DP_T_SNK0_ML_C_N<3>

DP_T_SNK0_AUXCH_C_P

DP_T_SNK0_AUXCH_C_N

DP_T_SNK1_ML_C_P<0>

DP_T_SNK1_ML_C_N<0>

DP_T_SNK1_ML_C_P<1>

DP_T_SNK1_ML_C_N<1>

DP_T_SNK1_ML_C_P<2>

DP_T_SNK1_ML_C_N<2>

DP_T_SNK1_ML_C_P<3>

DP_T_SNK1_ML_C_N<3>

DP_T_SNK1_AUXCH_C_P

DP_T_SNK1_AUXCH_C_N

1/20W 201MF

5%

1/20W 201

5% MF

RB091

RB062

MF1/20W5% 201

RB072

1/20W

MF5% 201

RB060

RB061

RB070

MF5%

RB071

1

3.3K

5%

1/20W

MF

201

2

DP_TA_HPD

DP_TB_HPD

TBT_TA_LSTX

TBT_TA_LSRX

TBT_TB_LSTX

2011/20W

TBT_TB_LSRX

2011/20W MF5%

RB093

3.3K

5% 1/20W MF 201

6

CLK

1

CS*

3

WP*(IO2)

7

HOLD*(IO3)

SNK0 AC Coupling

CB020

CB021

CB022

CB023

CB024

CB025

CB026

CB027

CB028

CB029

SNK1 AC Coupling

CB030

CB031

CB032

CB033

CB034

CB035

CB036

CB037

CB038

CB039

PP3V3_UPC_TA_LDO

8

VCC

UB090

8MBIT-3.0V

W25Q80DVUXIE

USON

OMIT_TABLE

CRITICAL

GND EPAD

4

0.1UF

96 92

95 92

96 92

DI(IO0) DO(IO1)

9

1 2

95 94 92

3.3K

5%

1/20W

MF

201

5 2

1

2

TBT_T_SPI_MOSI TBT_T_SPI_MISO

RB092

DP_T_SNK0_ML_P<0>

16V10% 0201

X5R-CERM

DP_T_SNK0_ML_N<0>

020110%

16V

X5R-CERM

DP_T_SNK0_ML_P<1>

10%

16V 0201

X5R-CERM

DP_T_SNK0_ML_N<1>

16V 0201

10% X5R-CERM

DP_T_SNK0_ML_P<2>

10% 16V X5R-CERM

0201

DP_T_SNK0_ML_N<2>

X5R-CERM

020116V10%

DP_T_SNK0_ML_P<3>

10% 16V 0201 X5R-CERM

DP_T_SNK0_ML_N<3>

16V 020110%

X5R-CERM

DP_T_SNK0_AUXCH_P

16V10%

X5R-CERM

0201

DP_T_SNK0_AUXCH_N

X5R-CERM

020116V10%

DP_T_SNK1_ML_P<0>

X5R-CERM

020116V10%

DP_T_SNK1_ML_N<0>

X5R-CERM

020110% 16V

DP_T_SNK1_ML_P<1>

16V 020110%

X5R-CERM

DP_T_SNK1_ML_N<1>

X5R-CERM

020116V10%

DP_T_SNK1_ML_P<2>

16V

10% 0201 X5R-CERM

DP_T_SNK1_ML_N<2>

X5R-CERM

020116V10%

DP_T_SNK1_ML_P<3>

X5R-CERM

020116V10%

DP_T_SNK1_ML_N<3>

X5R-CERM

020116V10%

DP_T_SNK1_AUXCH_P

X5R-CERM

020116V10%

DP_T_SNK1_AUXCH_N

16V10% 0201

X5R-CERM

1

CB090

1UF

10%

6.3V

2

CERM 402

94

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

92

GND_VOID=TRUE

95

PLACE_NEAR=UB000.H6:2MM PLACE_NEAR=UB000.J6:2MM

GND_VOID=TRUE

DP_TA_AUXCH_P

BI

DP_TA_AUXCH_N

BI

GND_VOID=TRUE

10K PU ON CLOCKS PAGE

94 34

OUT

RB030

100K

1/20W

94 34

OUT

RB031

100K

5%

1/20W

MF

201

1 2

TF

1

2

1/20W

RB055

12

0201

PLACE_NEAR=UB000.H19:2MM

16V

10%

X5R-CERM

10%

16V

X5R-CERM

12

RB054

499

1%

1/20W

MF

1

5% MF

201

2

CB010

0.1UF

CB011

0.1UF

1

2

201

94

IN

94

IN

94

IN

94

IN

94

IN

94

IN

94

IN

94

IN

PCIE_CLK100M_TBT_T_P

IN

PCIE_CLK100M_TBT_T_N

IN

TBT_T_CLKREQ_L

OUT

94

IN

94

BI

94

IN

94

BI

MF1%

1/20W

14K

105 15

19

12 201

RB050

94 28 26

4.75K

0.5% 0201

TBT_TA_USB2_RBIAS

97

94

95 92

95 94 92

56

OUT

IN

OUT

IN

DP_TA_AUXCH_C_P DP_TA_AUXCH_C_N

BI

OUT

IN

RIO_TBTTHMSNS_D1_P

PCIE_TBT_T_R2D_P<0> PCIE_TBT_T_R2D_N<0>

PCIE_TBT_T_R2D_P<1> PCIE_TBT_T_R2D_N<1>

NC_PCIE_TBT_T_R2D_P<2> NC_PCIE_TBT_T_R2D_N<2>

NC_PCIE_TBT_T_R2D_P<3> NC_PCIE_TBT_T_R2D_N<3>

DP_T_SNK0_ML_P<0>

92

DP_T_SNK0_ML_N<0>

92

DP_T_SNK0_ML_P<1>

92

DP_T_SNK0_ML_N<1>

92

DP_T_SNK0_ML_P<2>

92

DP_T_SNK0_ML_N<2>

92

DP_T_SNK0_ML_P<3>

92

DP_T_SNK0_ML_N<3>

92

DP_T_SNK0_AUXCH_P

92

DP_T_SNK0_AUXCH_N

92

DP_T_SNK0_HPD

DP_T_SNK0_DDC_CLK DP_T_SNK0_DDC_DATA

DP_T_SNK1_ML_P<0>

92

DP_T_SNK1_ML_N<0>

92

DP_T_SNK1_ML_P<1>

92

DP_T_SNK1_ML_N<1>

92

DP_T_SNK1_ML_P<2>

92

DP_T_SNK1_ML_N<2>

92

DP_T_SNK1_ML_P<3>

92

DP_T_SNK1_ML_N<3>

92

DP_T_SNK1_AUXCH_P

92

DP_T_SNK1_AUXCH_N

92

DP_T_SNK1_HPD

DP_T_SNK1_DDC_CLK DP_T_SNK1_DDC_DATA

DP_T_SNK_RBIAS

PLACE_NEAR=UB000.Y18:2MM

94 26

94 28

94 26

IN

OUT

JTAG_TBT_TDI JTAG_TBT_T_TMS JTAG_TBT_TCK JTAG_ISP_TDO

TBT_T_RBIAS TBT_T_RSENSE

USBC_TA_D2R_P<2> USBC_TA_D2R_N<2>

USBC_TA_R2D_C_P<2> USBC_TA_R2D_C_N<2>

USBC_TA_R2D_C_P<1> USBC_TA_R2D_C_N<1>

USBC_TA_D2R_P<1> USBC_TA_D2R_N<1>

USB_UPC_TA_P USB_UPC_TA_N

TBT_TA_LSTX TBT_TA_LSRX DP_TA_HPD

USE NEAREST GND BALL

(AC22) FOR THERM_D_N

NC

Y23 Y22

T23 T22

PCIE_RX0_P PCIE_RX0_N

PCIE_RX1_P PCIE_RX1_N

UB000

TBT-AR-4C-CNTRL

SYM 1 OF 2

FCBGA

OMIT_TABLE

PCIE_TX0_P PCIE_TX0_N

PCIE_TX1_P PCIE_TX1_N

CRITICAL

M23

PCIE_RX2_P

M22

PCIE_RX2_N

H23

PCIE_RX3_P

H22

PCIE_RX3_N

V19

PCIE_REFCLK_100_IN_P

T19

PCIE_REFCLK_100_IN_N

AC5 N16

PCIE_CLKREQ*

AB7

DPSNK0_ML0_P

AC7

DPSNK0_ML0_N

AB9

DPSNK0_ML1_P

AC9

DPSNK0_ML1_N

AB11 AC11

AB13 AC13

AB15 AC15

AB17 AC17

AB19 AC19

AB21 AC21

AC23 AB23

DPSNK0_ML2_P DPSNK0_ML2_N

DPSNK0_ML3_P DPSNK0_ML3_N

Y11

DPSNK0_AUX_P

W11

DPSNK0_AUX_N

AA2

DPSNK0_HPD

Y5

DPSNK0_DDC_CLK

R4

DPSNK0_DDC_DATA

DPSNK1_ML0_P DPSNK1_ML0_N

DPSNK1_ML1_P DPSNK1_ML1_N

DPSNK1_ML2_P DPSNK1_ML2_N

DPSNK1_ML3_P DPSNK1_ML3_N

Y12

DPSNK1_AUX_P

W12

DPSNK1_AUX_N

Y6

DPSNK1_HPD

Y8

DPSNK1_DDC_CLK

N4

DPSNK1_DDC_DATA

Y18

DPSNK_RBIAS

Y4

TDI

V4

TMS

T4

TCK

W4

TDO

H6

RBIAS

J6

RSENSE

A15

PA_RX1_P

B15

PA_RX1_N

A17

PA_TX1_P

B17

PA_TX1_N

A19

PA_TX0_P

B19

PA_TX0_N

B21

PA_RX0_P

A21

PA_RX0_N

Y15

PA_DPSRC_AUX_P

W15

PA_DPSRC_AUX_N

E20

PA_USB2_D_P

D20

PA_USB2_D_N

A5

PA_LSTX

A4

PA_LSRX

M4

PA_DPSRC_HPD

H19

PA_USB2_RBIAS

THERMDA THERMDA

V18

PCIE_ATEST

AC1

TEST_EDM

L15

FUSE_VQPS_64

N15

FUSE_VQPS_128

C23

MONDC_CIO_0

C22

MONDC_CIO_1

SINK PORT 0

SINK PORT 1

PORT A

PCIE GEN3

SOURCE PORT 0

MISC

PORT B POC GPIO LC GPIO

TBT PORTS

DEBUG

PCIE_TX2_P PCIE_TX2_N

PCIE_TX3_P PCIE_TX3_N

PERST*

PCIE_RBIAS

DPSRC_ML0_P DPSRC_ML0_N

DPSRC_ML1_P DPSRC_ML1_N

DPSRC_ML2_P DPSRC_ML2_N

DPSRC_ML3_P DPSRC_ML3_N

DPSRC_AUX_P DPSRC_AUX_N

DPSRC_HPD

DPSRC_RBIAS

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7

GPIO_8 POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4 POC_GPIO_5 POC_GPIO_6

TEST_EN

TEST_PWR_GOOD

RESET*

XTAL_25_IN

XTAL_25_OUT

EE_DI EE_DO

EE_CS*

EE_CLK

PB_RX1_P PB_RX1_N

PB_TX1_P PB_TX1_N

PB_TX0_P PB_TX0_N

PB_RX0_P PB_RX0_N

PB_DPSRC_AUX_P PB_DPSRC_AUX_N

PB_USB2_D_P PB_USB2_D_N

PB_LSTX PB_LSRX

PB_DPSRC_HPD

PB_USB2_RBIAS

MONDC_SVR

ATEST_P ATEST_N

USB2_ATEST

MONDC_DPSNK_0 MONDC_DPSNK_1

MONDC_DPSRC

V23 V22

P23 P22

K23 K22

F23 F22

L4

PCIE_TBT_T_D2R_C_P<0> PCIE_TBT_T_D2R_C_N<0>

PCIE_TBT_T_D2R_C_P<1> PCIE_TBT_T_D2R_C_N<1>

NC_PCIE_TBT_T_D2R_C_P<2> NC_PCIE_TBT_T_D2R_C_N<2>

NC_PCIE_TBT_T_D2R_C_P<3> NC_PCIE_TBT_T_D2R_C_N<3>

TBT_T_PCI_RESET_L

TBT_T_PCIE_BIAS

R2 R1

N2 N1

L2 L1

J2 J1

W19 Y19

G1

N6

U1 U2 V1 V2 W1 W2 Y1 Y2 AA1 J4 E2 D4 H4 F2 D2 F1

E1

AB5

F4

D22 D23

AB3 AC4 AC3 AB4

B7 A7

A9 B9

A11 B11

A13 B13

Y16 W16

E19 D19

B4 B5 G2

F19

D6

A23 B23

E18

W13 W18

AB2

NC_DP_T_SRC_ML_P<0> NC_DP_T_SRC_ML_N<0>

NC_DP_T_SRC_ML_P<1> NC_DP_T_SRC_ML_N<1>

NC_DP_T_SRC_ML_P<2> NC_DP_T_SRC_ML_N<2>

NC_DP_T_SRC_ML_P<3> NC_DP_T_SRC_ML_N<3>

NC_DP_T_SRC_AUX_P NC_DP_T_SRC_AUX_N

DP_T_SRC_HPD

94

DP_T_SRC_RBIAS

I2C_TBT_T_SDA I2C_TBT_T_SCL

TBT_T_ROM_WP_L

92

TBT_T_TMU_CLK_OUT SMC_PME_S4_DARK_L TBT_T_CIO_PLUG_EVENT_L DDI2_MUX_SEL DDI1_MUX_SEL TBT_T_TMU_CLK_IN I2C_TBT_TA_INT_L I2C_TBT_TB_INT_L TBT_T_USB_PWR_EN TBT_T_FORCE_PWR PM_BATLOW_L PM_SLP_S3_L TBT_T_CIO_PWR_EN

TBT_T_TEST_EN

TBT_T_TEST_PWR_GOOD

USBC_T_RESET_L

TBT_T_XTAL25M_IN TBT_T_XTAL25M_OUT

UPC_T_SPI_MOSI UPC_T_SPI_MISO UPC_T_SPI_CS_L UPC_T_SPI_CLK

USBC_TB_D2R_P<2> USBC_TB_D2R_N<2>

USBC_TB_R2D_C_P<2> USBC_TB_R2D_C_N<2>

USBC_TB_R2D_C_P<1> USBC_TB_R2D_C_N<1>

USBC_TB_D2R_P<1> USBC_TB_D2R_N<1>

DP_TB_AUXCH_C_P DP_TB_AUXCH_C_N

USB_UPC_TB_P USB_UPC_TB_N

TBT_TB_LSTX TBT_TB_LSRX DP_TB_HPD

BI

OUT

IN

TBT_TB_USB2_RBIAS

PLACE_NEAR=UB000.F19:2MM

1

RB053

NC NC

NC

499

1% 1/20W MF 201

2

BOM_COST_GROUP=TBT

OUT

28 94

IN

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

IN

94

98 94

94

To SPI Flash

97

IN

97

IN

97

OUT

97

OUT

97

OUT

97

OUT

97

IN

97

IN

96 92

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

94

OUT

94 19

PLACE_NEAR= UB000.N6:2MM

RB052

1/20W

1 2

1%

94

34

BI

34

28

IN

94

IN

94

IN

MF

14K

28 26

96 95 94

PU at PCH

96 95

1

RB029

100

5% 1/20W MF 201

2

CB012

0.1UF

CB013

0.1UF

DRAWING

SYNC_MASTER=J79_GREG SYNC_DATE=07/28/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

PLACE_NEAR=UB000.N16:2MM

RB051

3.01K

1 2

1%

1/20W

MF

201

PP3V3_S5_TBT_T_SW

1

RB036

2.2K

5% 1/20W MF 201

2

94

IN

104 80 77 74 73 48 26 19 14

1

RB025

100

5% 1/20W MF 201

2

GND_VOID=TRUE

1 2

DP_TB_AUXCH_P

0201

16V10%

X5R-CERM

DP_TB_AUXCH_N

0201

16V10%

X5R-CERM

GND_VOID=TRUE

LAST_MODIFIED=Tue Aug 30 11:06:29 2016

USB-C HIGH SPEED 1

Apple Inc.

R

PP3V3_S5_TBT_T_SW

92 98

96

1

RB035

2.2K

5% 1/20W MF 201

2

BI

1

RB034

2.2K

5% 1/20W MF 201

2

1

RB037

2.2K

5% 1/20W MF 201

2

IN

not used

1

RB027

100K

5% 1/20W MF 201

2

BI

94

BI

92 98

94

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

110 OF 145

SHEET

92 OF 119

D

C

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

1

CB130

1.0UF

20%

6.3V

2

X5R 0201-1

1

CB131

1.0UF

20%

6.3V

2

X5R 0201-1

1

CB184

1.0UF

20%

6.3V

2

X5R 0201-1

CB145

1.0UF

20%

6.3V X5R

0201-1

1

CB132

1.0UF

20%

6.3V

2

X5R 0201-1

1

2

1

CB133

2

1

CB164

1.0UF

20%

6.3V

2

X5R 0201-1

1

CB185

1.0UF

20%

6.3V

2

X5R 0201-1

CB146

1.0UF

20%

6.3V X5R

0201-1

1.0UF

20%

6.3V X5R 0201-1

1

2

SOURCED BY INTERNAL SWITCH

1

CB134

2

1

CB165

1.0UF

20%

6.3V

2

X5R 0201-1

SOURCED BY INTERNAL SWITCH

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

CB147

1.0UF

20%

6.3V X5R

0201-1

1.0UF

20%

6.3V X5R 0201-1

VOLTAGE=3.3V

1

2

1

CB135

2

1

CB166

1.0UF

20%

6.3V

2

X5R 0201-1

PP0V9_TBT_T_DP

1

CB136

1.0UF

20%

6.3V X5R 0201-1

SOURCED BY INTERNAL SWITCH

1.0UF

20%

6.3V

2

X5R 0201-1

1

CB167

1.0UF

20%

6.3V

2

X5R 0201-1

94

PP0V9_TBT_T_PCIE

94

PP0V9_TBT_T_USB

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=0.9V

PP0V9_TBT_T_CIO

94

PP3V3_TBT_T_ANA_PCIE

PP3V3_TBT_T_ANA_USB2

1

CB120

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

CB121

1.0UF

20%

6.3V

2

X5R 0201-1

SOURCED BY

INTERNAL SWITCH

L8

VCC0P9_DP

L11

VCC0P9_DP

L12

VCC0P9_DP

M8

VCC0P9_DP

T11

VCC0P9_DP

T12

VCC0P9_DP

L6

VCC0P9_ANA_DPSRC

M6

VCC0P9_ANA_DPSRC

V11

VCC0P9_ANA_DPSNK

V12

VCC0P9_ANA_DPSNK

V13

VCC0P9_ANA_DPSNK

M13

VCC0P9_PCIE

M15

VCC0P9_PCIE

M16

VCC0P9_PCIE

L19

VCC0P9_ANA_PCIE_1

N19

VCC0P9_ANA_PCIE_1

L18

VCC0P9_ANA_PCIE_2

M18

VCC0P9_ANA_PCIE_2

N18

VCC0P9_ANA_PCIE_2

R15

VCC0P9_USB

R16

VCC0P9_USB

R8

VCC0P9_CIO

R9

VCC0P9_CIO

R11

VCC0P9_CIO

R12

VCC0P9_CIO

L16

VCC3P3_ANA_PCIE

J16

VCC3P3_ANA_USB2

A6

VSS_ANA

A8

VSS_ANA

A10

VSS_ANA

A12 A14

VSS_ANA

A16

VSS_ANA

A18

VSS_ANA

A20

VSS_ANA

A22

VSS_ANA

B6

VSS_ANA

B8

VSS_ANA

B10

VSS_ANA

B12

VSS_ANA

B14

VSS_ANA

B16

VSS_ANA

B18

VSS_ANA

B20

VSS_ANA

B22

VSS_ANA

D8

VSS_ANA

D9

VSS_ANA

D11

VSS_ANA

D12

VSS_ANA

D13

VSS_ANA

D15

VSS_ANA

D16

VSS_ANA

D18

VSS_ANA

E8

VSS_ANA

E9

VSS_ANA

E11

VSS_ANA

E15

VSS_ANA

E16

VSS_ANA

E22

VSS_ANA

E23

VSS_ANA

F9

VSS_ANA

F20

VSS_ANA

F16

VSS_ANA

G22

VSS_ANA

G23

VSS_ANA

H1

VSS_ANA

H2

VSS_ANA

H12

VSS_ANA

H13

VSS_ANA

H15

VSS_ANA

H16

VSS_ANA

H20

VSS_ANA

J5

VSS_ANA

J19

VSS_ANA

J20

VSS_ANA

J18

VSS_ANA

J22

VSS_ANA

J23

VSS_ANA

K1

VSS_ANA

K2

VSS_ANA

L5

VSS_ANA

L20

VSS_ANA

L22

VSS_ANA

L23

VSS_ANA

M1

VSS_ANA

M2

VSS_ANA

M5

VSS_ANA

M19

VSS_ANA

M20

VSS_ANA

N5

VSS_ANA

N20

VSS_ANA

N22

VSS_ANA

N23

VSS_ANA

P1

VSS_ANA

P2

VSS_ANA

R5

VSS_ANA

R18

VSS_ANA

R19

VSS_ANA

R20

VSS_ANA

R22

VSS_ANA

UB000

TBT-AR-4C-CNTRL

SYM 2 OF 2

FCBGA

OMIT_TABLE

CRITICAL

VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA VCC0P9_SVR_ANA

VCC0P9_SVR_SENSE

VCC

VCC0P9_LVR_SENSE

GND

VCC3P3_LC

VCC3P3_SX

VCC3P3_S0

VCC3P3A

VCC3P3_SVR VCC3P3_SVR VCC3P3_SVR

VCC0P9_SVR VCC0P9_SVR

SVR_IND SVR_IND SVR_IND

SVR_VSS SVR_VSS

SVR_VSS

VCC0P9_LVR VCC0P9_LVR VCC0P9_LVR

VSS_ANA VSS_ANA VSS_ANA VSS_ANAVSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA VSS_ANA

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

R6

F8

R13

H9

A2 A3 B3

L9 M9 E12 E13 F11 F12 F13 F15 J9

C1 C2 D1

A1 B1 B2

F18 H18 J11 H11

R23 T1 T2 T5 T20 U23 U22 V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2 M11

PP3V3_TBT_T_LC

PP3V3_S5_TBT_T_SW

1

CB191

1.0UF

20%

6.3V

2

X5R 0201-1

1

CB175

10UF

20%

6.3V

2

CERM-X5R 0402-4

BYPASS=UB000.A2:A1:3MM

1

CB176

2

PP0V9_TBT_T_SVR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

DIDT=TRUE SWITCH_NODE=TRUE

0.68UH-20%-6.1A-0.020OHM

VR0V9_IND_TBT_T

PP0V9_TBT_T_LVR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.9V

CB192

1.0UF

0201-1

1

20%

6.3V 2

X5R

Add XW or alias on support page

XW

XWB100

SM

1 2

PLACE_NEAR=UB000.AC22:2MM

NO_XNET_CONNECTION=1

PP3V3_TBT_T_F

VOLTAGE=3.3V MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

CB177

10UF

20%

6.3V CERM-X5R 0402-4

10UF

20%

6.3V

2

CERM-X5R 0402-4

LB150

1 2

1210

SOURCED BY INTERNAL SWITCH

20%

6.3V X5R

1

2

CB193

1.0UF

0201-1

94

RIO_TBTTHMSNS_D1_N

CB154

10UF

20%

6.3V

CERM-X5R

0402-4

1

CB178

10UF

20%

6.3V

2

CERM-X5R 0402-4

1

2

OUT

CB190

1.0UF

0201-1

1

2

CB155

10UF

CERM-X5R

0402-4

2x 10uF outside BGA area

1

20%

6.3V 2

X5R

1

2

CB150

47UF

20%

6.3V CER-X5R 0603

1

20%

6.3V 2

CB194

47UF

CER-X5R

CB117

12PF

5% 25V NP0-C0G 0201

20%

6.3V

0603

1

CB151

47UF

20%

6.3V

2

CER-X5R 0603

1

2

P0V9_TBT_T_SVR_AGND

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0V

56

BOM_COST_GROUP=TBT

CB195

47UF

CER-X5R

1

CB110

1.0UF

20%

6.3V

2

X5R 0201-1

20%

6.3V

0603

1

2

1

2

1

2

1 2

0603

LB190

1.0UH-20%-2.1A-0.128OHM

CRITICAL

CB111

1.0UF

20%

6.3V X5R 0201-1

CB152

47UF

20%

6.3V CER-X5R 0603

FROM USB-C PORT CONTROLLER (UPC)

1

CB181

1.0UF

20%

6.3V

2

X5R 0201-1

PP3V3_TBT_T_S0

1

CB112

1.0UF

20%

6.3V

2

X5R 0201-1

INTERNAL SWITCHING VR OUTPUT

1

CB113

1.0UF

20%

6.3V

2

X5R 0201-1

SYNC_MASTER=J79_GREG SYNC_DATE=08/28/2015

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

94

94 98

94 101

1

CB114

1.0UF

20%

6.3V

2

X5R 0201-1

ISOLATE GND OF SVR_IND CAPS

AND GND OF VCC3P3_SVR CAPS

FROM SYSTEM GND IN LAYOUT

(SEE INTEL LAYOUT GUIDELINES)

1

CB180

2

1

CB115

1.0UF

20%

6.3V

2

X5R 0201-1

0.1UF

10% 16V X5R-CERM 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

CB116

1.0UF

20%

6.3V

2

X5R 0201-1

USB-C HIGH SPEED 2

DRAWING NUMBER SIZE

Apple Inc.

R

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

111 OF 145

SHEET

93 OF 119

SOURCED BY INTERNAL SWITCH

9.0.0

D

C

B

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

TMU CLKs

TBT_T_TMU_CLK_OUT

92

MAKE_BASE=TRUE

TBT_T_TMU_CLK_OUT

Ridge 0.9V SVR XW

P0V9_TBT_T_SVR_AGND

93

DP SRC OPTIONS

IF DP SRC NOT USED

NC_DP_T_SRC_ML_P<0>

92

NC_DP_T_SRC_ML_P<1>

92

NC_DP_T_SRC_ML_P<2>

92

NC_DP_T_SRC_ML_P<3>

92

NC_DP_T_SRC_ML_N<0>

92

NC_DP_T_SRC_ML_N<1>

92

NC_DP_T_SRC_ML_N<2>

92

NC_DP_T_SRC_ML_N<3>

92

NC_DP_T_SRC_AUX_P

92

NC_DP_T_SRC_AUX_N

92

AR xtal

92

IN

OUT

TBT_T_XTAL25M_OUT

NOSTUFF

1

RB206

1M

5% 1/20W MF 201

2

TBT_T_XTAL25M_IN

25MHZ-25PPM-20PF-50OHM

T RIDGE DEBUG CONN

USBC_DBG

RB225

15

1 2

5%

1/20W

MF

201

PLACE_NEAR=UB000.V2:5mm

TBT_X_TMU_CLK_IN

RB224

5% MF1/20W 201

NO_XNET_CONNECTION=1

XWB200

SHORT-L6-SM

1 2

DP_T_SRC_HPD

92

NC_DP_T_SRC_ML_P<0> NC_DP_T_SRC_ML_P<1> NC_DP_T_SRC_ML_P<2> NC_DP_T_SRC_ML_P<3> NC_DP_T_SRC_ML_N<0> NC_DP_T_SRC_ML_N<1> NC_DP_T_SRC_ML_N<2> NC_DP_T_SRC_ML_N<3>

NC_DP_T_SRC_AUX_P NC_DP_T_SRC_AUX_N

RB207

0

1 2

1/20W5%MF

CRITICAL

YB200

2.00X1.60-SM

TBT_T_XTAL25M_OUT_R

201

2 4

JB201

505070-1220

M-ST-SM

13 14

Place on bottom

MAKE_BASE=TRUE

100K

1 2

RB240

1M

1 2

5%

1/20W

MF

201

1

2

1 3

2

1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1

MAKE_BASE=TRUE

NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1

MAKE_BASE=TRUE NO_TEST=1 MAKE_BASE=TRUE NO_TEST=1

CB202

20PF

5% 25V C0G 0201

0201 C0G 25V 5%

20PF

CB203

26

ACE A/B RPD STRAPPING

MAKE_BASE=TRUE

USBC_TA_CC1

95

USBC_TA_CC2

95

USBC_TB_CC1

96

USBC_TB_CC2

96

USBC_TA_CC1

MAKE_BASE=TRUE

USBC_TA_CC2

MAKE_BASE=TRUE

USBC_TB_CC1

MAKE_BASE=TRUE

USBC_TB_CC2

ACE FET DCIN Bypass Caps

PPDCIN_G3H

100 29 30 95 96

10% 35V

0201

1

2

CB211

0.1UF

10% 35V

CER-X5R

0201

10% 35V

0201

1

2

CB213

0.1UF

CER-X5R

1

CB212

0.1UF

2

CER-X5R

ACE PDs

UPC_TA_DBG3

95

UPC_TA_DBG4

95

UPC_TB_DBG3

96

UPC_TB_DBG4

96

UPC_TA_DBG1

95

UPC_TA_DBG2

95

99 94

UPC_T_5V_EN

FUSES FOR UPC

PP20V_USBC_TA_VBUS

94 95

PP20V_USBC_TB_VBUS

94 96

RB260

1/20W

RB261

RB262

1/20W MF5% 201

RB263

RB264

1/20W 201MF

5%

RB265

RB232

MF 2015%

MF5% 1/20W 201

MF1/20W5% 201

100K

1 2

100K

1 2

100K

1 2

100K

1 2

2015% MF1/20W

100K

1 2

100K

1 2

201MF5% 1/20W

100K

1 2

0603

FB200

6AMP-32V-0.0095OHM

1 2

0603

FB201

6AMP-32V-0.0095OHM

1 2

T ACEs DEBUG CONN

JB200

USBC_DBG

505070-1220

M-ST-SM

13 14

CB214

0.1UF

10% 35V

CER-X5R

0201

ACE Debug Support

UPC_TA_DBG_UART_TX

104 97 95

104 97 96

1

2

CRITICAL

PLACE_NEAR=QB300:5MM

PP20V_USBC_TA_VBUS_F

CRITICAL

PLACE_NEAR=QB400:5MM

PP20V_USBC_TB_VBUS_F

Place on bottom

95

UPC_TA_DBG_UART_RX

95

UPC_TB_DBG_UART_TX

96

UPC_TB_DBG_UART_RX

96

OMIT

RB289

NOSTUFF

NONE NONE NONE

402

OMIT

RB288

NOSTUFF

NONE NONE NONE

402

95

96

GND ALIASES

GND

95

GND

96

1

2

95

96

GND

GND GND GND GND

NC/NO TEST

1

NO_TEST=1

96

IN

2

NC_UPC_TB_I2C_ADDR

96

95

96

95

96

95

GND GND GND

GND

AR/ACE SPI BUS SERIES R'S

TBT_T_SPI_CLK

92

TBT_T_SPI_CS_L

92

TBT_T_SPI_MOSI

92

TBT_T_SPI_MISO

92

ROM

RB290 RB280 RB281 RB282 RB283 RB284 RB285 RB286 RB287

100

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

15

1 2

TBT_T_SPI_CLK_DBG

MF1/20W5%

201

UPC_TA_SPI_CLK

1/20W

5% 201MF

UPC_TA_SPI_CS_L

2011/20W5% MF

UPC_TA_SPI_MOSI

1/20W 201MF5%

UPC_TA_SPI_MISO

5% 1/20W MF 201

UPC_T_SPI_CLK

2011/20W5%

MF

UPC_T_SPI_CS_L

5% 1/20W 201MF

UPC_T_SPI_MOSI

MF5%

2011/20W

UPC_T_SPI_MISO

5% MF 2011/20W

IN

OUT

IN

OUT

94

95

Ace

92 28

AR

92 28

D

SIGNAL ALIASES

TBT to ACE

U3100

(Write: 0x70 Read: 0x71)

I2C_TBT_T_SCL I2C_TBT_T_SDA I2C_TBT_TA_INT_L

Sec ACE

U3200

(Write: 0x7E Read: 0x7F)

I2C_TBT_T_SCL I2C_TBT_T_SDA I2C_TBT_TB_INT_L

D2R

20%6.3V0201

20%X5R 6.3V0201

CB250

12

0.22UF

CB251

12

0.22UF

CB252

12

0.22UF

GND_VOID=TRUE

PCIE_TBT_T_D2R_P<0>

GND_VOID=TRUE

PCIE_TBT_T_D2R_N<0>

GND_VOID=TRUE

PCIE_TBT_T_D2R_P<1>

GND_VOID=TRUE

95

96

OUT

C

105 15

15

TBT_T_CIO_PWR_EN

92 95 96

TBT_T_USB_PWR_EN

92 95 96

PM_BATLOW_L

92

UPC_T_5V_EN

95

UPC_T_5V_EN

96

JTAG_ISP_TDO

26 28 92

TBT_POC_RESET

94 95 96

TBT_T_CIO_PLUG_EVENT_L

16

XDP_USB_EXTC_OC_L

95

XDP_USB_EXTD_OC_L

96

JTAG_TBT_T_TMS

13 28

S3X_JTAG_TCK

96

S3X_JTAG_TMS

96

NC_USBC_TB_RESET_L

96

15

95

15

95

15

96

15

96

USB_UPC_PCH_TA_N

USB_UPC_PCH_TA_P

USB_UPC_PCH_TB_N

USB_UPC_PCH_TB_P

MAKE_BASE=TRUE

TBT_T_CIO_PWR_EN

MAKE_BASE=TRUE

TBT_T_USB_PWR_EN

MAKE_BASE=TRUE

PM_BATLOW_L

MAKE_BASE=TRUE

UPC_T_5V_EN

MAKE_BASE=TRUE

JTAG_ISP_TDO

MAKE_BASE=TRUE

TBT_POC_RESET

MAKE_BASE=TRUE

TBT_T_CIO_PLUG_EVENT_L

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTD_OC_L

MAKE_BASE=TRUE

JTAG_TBT_T_TMS

MAKE_BASE=TRUE

S3X_JTAG_TCK

MAKE_BASE=TRUE

S3X_JTAG_TMS

MAKE_BASE=TRUE

NC_USBC_TB_RESET_L

MAKE_BASE=TRUE

USB_UPC_PCH_TA_N

MAKE_BASE=TRUE

USB_UPC_PCH_TA_P

MAKE_BASE=TRUE

USB_UPC_PCH_TB_N

MAKE_BASE=TRUE

USB_UPC_PCH_TB_P

28 5

17 5

102

94 16

48 28 14

99 94

28 16

94 92

92 28

104 84 81

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

Alpine Ridge U2800

TBT Pri ACE

(MASTER)

I2C_TBT_T_SCL

92 94

I2C_TBT_T_SDA

92 94

I2C_TBT_TA_INT_L

92 94

I2C_TBT_TB_INT_L

92 94

Ridge PCIE Caps

92

PCIE_TBT_T_D2R_C_P<0>

IN

PCIE_TBT_T_D2R_C_N<0>

IN

PCIE_TBT_T_D2R_C_P<1>

IN

0201

X5R 20%6.3V

X5R

B

94 92

92 34

95 92

94 95 96

93

TBT_T_CIO_PLUG_EVENT_L DP_T_SNK0_HPD DP_T_SNK1_HPD DP_TA_HPD TBT_POC_RESET PP3V3_TBT_T_LC

1 2

3 4

5 6

7 8

9 10

11 12

15

RIDGE JTAG ISOLATION

92 26

Ridge PWR ENs

JTAG_TBT_TCK

JTAG_TBT_TDI

RB246

100K

94 16

TBT_T_CIO_PWR_EN

TBT_T_USB_PWR_EN

1

RB245

5%

1/20W

MF

201

2

201 1/20W

100K

5% 1/20W MF 201

2

MF201

16

RB243

RB244

TBT_T_PCI_RESET_L USBC_T_RESET_L PP3V3_S5_TBT_T_SW PP0V9_TBT_T_PCIE PP0V9_TBT_T_USB PP0V9_TBT_T_CIO

PLACE_NEAR=U0500.J1:10mm

TBT_DBG

15

1 2

15

1 2

XDP_JTAG_ISP_TCK

1/20W MF 2015%

XDP_JTAG_ISP_TDI

5% 1/20W

TBT_DBG

PLACE_NEAR=U0500.J2:10mm

5 13 14 16 19 101

100K

5%MF

5%1/20W

12

100K

19 92

98 92

93 98

93

201MF

PP3V3_S0

RB271

RB272

17

94 92

94

51 48 28

94

96 95

95

96

94

95

96

94

I2C_TBT_TB_INT_L I2C_UPC_T_SCL2

I2C_UPC_T_SDA2 SMC_USBC_INT_L TBT_T_SPI_CLK_DBG UPC_TA_UART_TX

1 2

3 4

5 6

7 8

9 10

11 12

15

16

I2C_TBT_TA_INT_L I2C_TBT_T_SDA I2C_TBT_T_SCL TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN UPC_TA_UART_RX

T ACE-SMC I2C SERIES R'S

PLACE_NEAR=U5000:5mm

I2C_UPC_T_SDA2

MAKE_BASE=TRUE

I2C_UPC_T_SDA2

I2C_UPC_T_SCL2

MAKE_BASE=TRUE

I2C_UPC_T_SCL2

RB241

RB242

1/20W

201MF1/20W5%

201MF5%

33

1 2

SMBUS_SMC_4_G3H_SDA

PLACE_NEAR=U5000:5mm

33

1 2

SMBUS_SMC_4_G3H_SCL

CB253

94 92

94 16

96 95

51

PP3V3_UPC_TA_LDO

92

PP3V3_UPC_TA_LDO

95

PP3V3_UPC_TA_LDO

95

PP3V3_UPC_TB_LDO

96

PP3V3_UPC_TB_LDO

96

PP20V_USBC_TA_VBUS

94 95

PP20V_USBC_TB_VBUS

94 96

PP5V_S4_T_USBC

95

PP5V_S4_T_USBC

96

PP5V_S4_T_USBC

99

PP3V3_TBT_T_S0

93 101

POWER ALIASES

MAKE_BASE=TRUE

PP3V3_UPC_TA_LDO

MAKE_BASE=TRUE

PP3V3_UPC_TB_LDO

MAKE_BASE=TRUE

PP20V_USBC_TA_VBUS

MAKE_BASE=TRUE

PP20V_USBC_TB_VBUS

MAKE_BASE=TRUE

PP5V_S4_T_USBC

MAKE_BASE=TRUE

PP3V3_TBT_T_S0

95

96

97

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=5V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

92

105

15

PCIE_TBT_T_D2R_C_N<1>

IN

MAKE_BASE=TRUE

0201 20%6.3VX5R

NC_PCIE_TBT_T_D2R_C_P<2>

NO_TEST=1

MAKE_BASE=TRUE

NC_PCIE_TBT_T_D2R_C_N<2>

NO_TEST=1

MAKE_BASE=TRUE

NC_PCIE_TBT_T_D2R_C_P<3>

NO_TEST=1

MAKE_BASE=TRUE

NC_PCIE_TBT_T_D2R_C_N<3>

NO_TEST=1

GND_VOID=TRUE

PCIE_TBT_T_R2D_C_P<0>

IN

105

PCIE_TBT_T_R2D_C_N<0>

PCIE_TBT_T_R2D_C_P<1>

PCIE_TBT_T_R2D_C_N<1>

MAKE_BASE=TRUE

NC_PCIE_TBT_T_R2D_P<2>

NO_TEST=1

MAKE_BASE=TRUE

NC_PCIE_TBT_T_R2D_N<2>

NO_TEST=1

MAKE_BASE=TRUE

NC_PCIE_TBT_T_R2D_P<3>

NO_TEST=1

MAKE_BASE=TRUE

NC_PCIE_TBT_T_R2D_N<3>

NO_TEST=1

0201 X5R 6.3V 20%

GND_VOID=TRUE

0201

GND_VOID=TRUE

0201

6.3VX5R0201

X5R 20%6.3V

20%X5R 6.3V

20%

12

0.22UF

R2D

12

0.22UF

12

0.22UF

12

0.22UF

12

0.22UF

CB240

CB241

CB242

CB243

PCIE_TBT_T_D2R_N<1>

NC_PCIE_TBT_T_D2R_C_P<2>

NC_PCIE_TBT_T_D2R_C_N<2>

NC_PCIE_TBT_T_D2R_C_P<3>

NC_PCIE_TBT_T_D2R_C_N<3>

PCIE_TBT_T_R2D_P<0>

PCIE_TBT_T_R2D_N<0>

PCIE_TBT_T_R2D_P<1>

PCIE_TBT_T_R2D_N<1>

NC_PCIE_TBT_T_R2D_P<2>

NC_PCIE_TBT_T_R2D_N<2>

NC_PCIE_TBT_T_R2D_P<3>

NC_PCIE_TBT_T_R2D_N<3>

OUT

92

OUT

15

B

92

A

Ridge PDs

DP_T_SNK0_DDC_CLK

92

MAKE_BASE=TRUE

RB267

1/20W 201MF5%

DP_T_SNK0_DDC_CLK

DP_T_SNK0_DDC_DATA

92

MAKE_BASE=TRUE

RB268

1/20W5% 201MF

DP_T_SNK0_DDC_DATA

DP_T_SNK1_DDC_CLK

92

MAKE_BASE=TRUE

RB269

1/20W 2015% MF

DP_T_SNK1_DDC_CLK

DP_T_SNK1_DDC_DATA

92

MAKE_BASE=TRUE

RB270

MF1/20W5%

DP_T_SNK1_DDC_DATA

8 7 5 4 2 1

100K

1 2

100K

1 2

100K

1 2

100K

1 2

201

USB2 AR PDs

USB_UPC_TA_P

92

USB_UPC_TA_N

92

USB_UPC_TB_P

92

USB_UPC_TB_N

92

RB220

5% MF1/20W

RB221

5% 1/20W MF

RB222

1/20W MF5%

RB223

1/20W5% MF

0

1 2

201

0

1 2

201

0

1 2

201

0

1 2

201

PAGE TITLE

USB-C Support

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

BOM_COST_GROUP=TBT

36

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

112 OF 145

94 OF 119

D

A

SYNC_DATE=07/05/2016SYNC_MASTER=J79_GREG

D

PRIMARY ACE USB-C PORT CONTROLLER (UPC)

QB300

FDPC4044

PWR-CLIP-33

345678

2 1

D

C

PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES

CAP FOR PP_5V0 ON VR PAGE

PP20V_USBC_TA_VBUS

94

PP3V3_UPC_TA_LDO

94

PP3V3_G3H

100

GND

28 29 30 96

PP5V_S4_T_USBC

94

FUSE

Add on support page

1

CB300

10UF

20%

6.3V

2

CERM-X5R 0402-1

PP20V_USBC_TA_VBUS_F

94

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=20V

1

CB301

1UF

10% 35V

2

X5R 0402

A11

B11

C11

D11

PP_5V0

A6A7A8

PP_HV

B7

H10

PP_HV

PP_CABLE

H11

VBUS

J10

VBUS

S2 5

J11

VBUS

G2 4

K11B1H1

VBUS

VIN_3V3

NC

VDDIO

LDO_3V3

2

3

NC

H2

VOUT_3V3

G1

S1

1

8

UPC_TA_GATE1

UPC_TA_GATE2

K1

A2G1E1

LDO_BMC

LDO_1V8D

LDO_1V8A

PP1V8_UPC_TA_LDOD

PP1V1_UPC_TA_LDO_BMC

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.1V

PPDCIN_G3H

MAX 100uF TOTAL ON RAIL

PP1V8_UPC_TA_LDOA

MIN_LINE_WIDTH=0.0900

MIN_NECK_WIDTH=0.0520

VOLTAGE=1.8V

1

CB304

2.2UF

20% 4V

2

X5R-CERM 0201

1

CB305

1.0UF

20%

6.3V

2

X5R 0201-1

29 30 94 96 100

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

PP3V3_UPC_TA_LDO

P3V3_TBT_T_SX_EN_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=1.8V

1

CB306

0.47UF

10%

6.3V

2

CERM-X5R 0201

98

94

1

CB308

10UF

20%

6.3V

2

CERM-X5R 0402-1

C

B

GND

1M

1 2

1M

1 2

1M

RB309

1/20W5%

RB308

1/20W5%

RB305

1/20W MF5%

94

I2C_UPC_TA_DBG_CTL_SCL

201MF

I2C_UPC_TA_DBG_CTL_SDA

MF 201

UPC_TA_UART_RX

201

95

TBT_POC_RESET USBC_T_RESET_L_R

UPC_TA_DBG_UART_TX

UPC_TA_DBG_UART_RX

TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN

DP_TA_HPD

GND

UPC_T_5V_EN

SMC_PME_S4_DARK_L

XDP_USB_EXTC_OC_L

GND

UPC_TA_R_OSC

TESTPOINTS MUST BE

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

96 30 29 28

GND I2C_ADDR PRIMARY ONLY

96 94

98

94

96 94 92

94 92

94

IN

OUT

IN

OUT

IN

CRITICAL

RB303

96 95 94

NEED 0.1%

REAR PORT:

CONNECT UPC SPI TO ROM

FRONT PORT:

GROUND UPC SPI

1

15K

0.1% 1/20W TF-LF

0201

2

TO SMC

94

51

94

BI

OUT

BI

OUT

IN

OUT

I2C_UPC_TA_DBG_CTL_SCL

95

I2C_UPC_TA_DBG_CTL_SDA

95

I2C_TBT_T_SDA I2C_TBT_T_SCL I2C_TBT_TA_INT_L

I2C_UPC_T_SDA2

I2C_UPC_T_SCL2

SMC_USBC_INT_L

UPC_TA_SPI_CLK UPC_TA_SPI_MOSI UPC_TA_SPI_MISO UPC_TA_SPI_CS_L

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

PRIMARY ONLY

UB300

CD3215A

BGA

HV FET/SENSE

TYPE-C

CRITICAL OMIT_TABLE

SS

SENSEP SENSEN

HV_GATE1 HV_GATE2

C_CC1 C_CC2

RPD_G1 RPD_G2

C_USB_TP C_USB_TN

C_USB_BP C_USB_BN

C_SBU1 C_SBU2

NC

H7

B10 A10

B9 A9

L9

USBC_TA_CC1

L10

USBC_TA_CC2

K9

USBC_TA_CC1

K10

USBC_TA_CC2

K6

USBC_TA_USB_TOP_P

L6

USBC_TA_USB_TOP_N

K7

USBC_TA_USB_BOT_P

L7

USBC_TA_USB_BOT_N

K8

USBC_TA_SBU1

L8

USBC_TA_SBU2

L11

GROUND

NC or GND to dissipate heat

UPC_TA_SS

1

CB309

0.47UF

10%

6.3V

2

CERM-X5R 0201

BI

94

97

1

CB314

220PF

10% 16V

2

CER-X7R 0201

1

CB313

220PF

10% 16V

2

CER-X7R 0201

BI

104

94 104

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.2000

97 94

97

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.2000

B

A

94

BI

LB300

90-OHM-0.1A

EXCX4CE

SYM_VER-1

USB_UPC_PCH_TA_P

USB_UPC_PCH_TA_N

PP3V3_UPC_TA_LDO

94

PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_TA_LDO

NO_XNET_CONNECTION=1

1

2 3

92

BI

4

PLACE_NEAR=UB300.L5:5mm

PLACE_NEAR=UB300.K5:5mm

1

RB310

100K

5% 1/20W MF 201

2

96 95 94

96 94

92

94

TP_UPC_TA_SWD_DATA

TP_UPC_TA_SWD_CLK

IN

OUT

IN

OUT

UPC_TA_UART_RX UPC_TA_UART_TX

TBT_TA_LSTX TBT_TA_LSRX

USB_UPC_TA_F_P USB_UPC_TA_F_N

DP_TA_AUXCH_P DP_TA_AUXCH_N

BI

UPC_TA_DBG1

UPC_TA_DBG2

UPC_TA_DBG3 UPC_TA_DBG4

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

A1D6E5E6E7F5G5H4H5G8H8L1B8D8E8F6F7F8G6

GND

G7

PAGE TITLE

SYNC_DATE=02/28/2016SYNC_MASTER=J79_GREG

A

1

RB311

NO_XNET_CONNECTION=1

8 7 5 4 2 1

100K

5% 1/20W MF 201

2

GND

PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION

94

BOM_COST_GROUP=USB-C

36

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

USB-C PORT CONTROLLER A

DRAWING NUMBER SIZE

Apple Inc.

R

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

113 OF 145

95 OF 119

D

SECONDARY ACE USB-C PORT CONTROLLER (UPC)

QB400

FDPC4044

PWR-CLIP-33

PP20V_USBC_TB_VBUS

94

FUSE

Add on support page

PP20V_USBC_TB_VBUS_F

94

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=20V

S2 5

G2 4

345678

2 1

D

G1

S1

2

3

NCNC

1

8

PPDCIN_G3H

29 30 94 95 100

MAX 100uF TOTAL ON RAIL

C

B

PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES

GND

1M

1 2

1M

1 2

1M

1 2

RB409

5% 201MF

1/20W

RB408

1/20W 201MF5%

RB405

1/20W MF 201

5%

94

I2C_UPC_TB_DBG_CTL_SCL

I2C_UPC_TB_DBG_CTL_SDA

UPC_TA_UART_TX

96

PP3V3_UPC_TB_LDO

94

1

CB401

1UF

10% 35V

2

X5R 0402

UPC_TB_GATE1

UPC_TB_GATE2

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=3.3V

PP3V3_UPC_TB_LDO

P3V3_TBT_T_SX_EN_R

94

98

PP1V8_UPC_TB_LDOA

PP3V3_G3H

100

GND

28 29 30 95

PP5V_S4_T_USBC

94

CAP FOR PP_5V0 ON VR PAGE

TBT_POC_RESET NC_USBC_TB_RESET_L

UPC_TB_DBG_UART_TX

94

UPC_TB_DBG_UART_RX

94

TBT_T_CIO_PWR_EN TBT_T_USB_PWR_EN

92

94

OUT

IN

DP_TB_HPD

GND

UPC_T_5V_EN

SMC_PME_S4_DARK_L

XDP_USB_EXTD_OC_L

GND

NC_UPC_TB_I2C_ADDR

TESTPOINTS MUST BE

PRESENT FOR GPIO0, GPIO1

(EVEN IN PRODUCTION)

95 94 92

95 94

IN

94

OUT

IN

95 30 29 28

UPC_TB_R_OSC

CRITICAL

15K

0.1% 1/20W TF-LF

0201

1

2

TO SMC

RB403

96 95 94

REAR PORT:

CONNECT UPC SPI TO ROM GROUND UPC SPI

NEED 0.1%

I2C_UPC_TB_DBG_CTL_SCL

96

I2C_UPC_TB_DBG_CTL_SDA

96

94

51

94

BI

OUT

BI

OUT

IN

OUT

I2C_TBT_T_SDA I2C_TBT_T_SCL I2C_TBT_TB_INT_L

I2C_UPC_T_SDA2 I2C_UPC_T_SCL2 SMC_USBC_INT_L

GND GND GND GND

1

CB400

10UF

20%

6.3V

2

CERM-X5R 0402-1

E11

MRESET

F11

RESET*

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

F10

BUSPOWERZ

F1

I2C_ADDR

G2

R_OSC

E4

DEBUG_CTL1

D5

DEBUG_CTL2

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1*

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2*

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

A11

B11

PP_5V0

C11

D11

PP_5V0

A6A7A8

PP_HV

B7

PP_HV

H10

H11

J10

VBUS

PP_CABLE

UB400

CD3215A

BGA

J11

K11B1H1

VBUS

HV FET/SENSE

TYPE-C

VDDIO

VIN_3V3

CRITICAL OMIT_TABLE

K1

H2

LDO_3V3

VOUT_3V3

A2G1E1

LDO_BMC

LDO_1V8D

LDO_1V8A

SS

SENSEP SENSEN

HV_GATE1 HV_GATE2

C_CC1 C_CC2

RPD_G1 RPD_G2

C_USB_TP C_USB_TN

C_USB_BP C_USB_BN

C_SBU1 C_SBU2

NC

H7

B10 A10

B9 A9

L9

USBC_TB_CC1

L10

USBC_TB_CC2

K9

USBC_TB_CC1

K10

USBC_TB_CC2

K6

USBC_TB_USB_TOP_P

L6

USBC_TB_USB_TOP_N

K7

USBC_TB_USB_BOT_P

L7

USBC_TB_USB_BOT_N

K8

USBC_TB_SBU1

L8

USBC_TB_SBU2

GROUND

L11

PP1V1_UPC_TB_LDO_BMC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.1V

UPC_TB_SS

NC or GND to dissipate heatFRONT PORT:

PP1V8_UPC_TB_LDOD

1

CB404

2.2UF

2

1

CB409

0.47UF

10%

6.3V

2

CERM-X5R 0201

BI

94

97

1

2

20% 4V X5R-CERM 0201

CB414

220PF

10% 16V CER-X7R 0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V

1

CB405

1.0UF

20%

6.3V

2

X5R 0201-1

MIN_LINE_WIDTH=0.0900

BI

1

CB413

220PF

10% 16V

2

CER-X7R 0201

104 97 94

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.0900

104 97 94

MIN_NECK_WIDTH=0.2000

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

1

CB406

0.47UF

10%

6.3V

2

CERM-X5R 0201

1

CB408

10UF

20%

6.3V

2

CERM-X5R 0402-1

C

B

94

BI

USB_UPC_PCH_TB_P

USB_UPC_PCH_TB_N

PU to PP3V3_S4 if convenient for layout. Otherwise PU to PP3V3_UPC_TB_LDO

NO_XNET_CONNECTION=1

1

2 3

94

LB400

90-OHM-0.1A

EXCX4CE

SYM_VER-1

4

PLACE_NEAR=UB400.L5:5mm

PLACE_NEAR=UB400.K5:5mm

PP3V3_UPC_TB_LDO

1

RB410

2

92

BI

92

BI

100K

5% 1/20W MF 201

96 95 94

95 94

92

94

TP_UPC_TB_SWD_DATA TP_UPC_TB_SWD_CLK

IN

OUT

IN

OUT

UPC_TA_UART_TX

UPC_TA_UART_RX

TBT_TB_LSTX

TBT_TB_LSRX

USB_UPC_TB_F_P USB_UPC_TB_F_N

DP_TB_AUXCH_P DP_TB_AUXCH_N

BI

S3X_JTAG_TCK S3X_JTAG_TMS

UPC_TB_DBG3 UPC_TB_DBG4

F4

SWD_DATA

G4

SWD_CLK

F2

UART_RX

E2

UART_TX

L4

LSX_R2P

K4

LSX_P2R

L5

USB_RP_P

K5

USB_RP_N

J1

AUX_P

J2

AUX_N

L2

DEBUG1

K2

DEBUG2

L3

DEBUG3

K3

DEBUG4

PORT MUX DIGITAL CORE I/O AND CONTROL

GND

A1D6E5E6E7F5G5H4H5G8H8L1B8D8E8F6F7F8G6

GND

G7

A

100K

5%

1/20W

MF

201

1

2

GND

PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION

94

RB411

NO_XNET_CONNECTION=1

BOM_COST_GROUP=USB-C

8 7 5 4 2 1

36

SYNC_MASTER=J79_GREG SYNC_DATE=02/28/2016

PAGE TITLE

USB-C PORT CONTROLLER B

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

REVISION

BRANCH

PAGE

SHEET

051-00515

9.0.0

dvt-fab09-0

114 OF 145

96 OF 119

A

D

345678

2 1

D

C

B

CC1

TBT_R2D0

TBT_D2R0

SBU2

USB2 BOT

SBU1

TBT_R2D1

TBT_D2R1

CC2

94

NSR20F40NX_G

104 96 94

104 95 94

VOLTAGE=20V

BI

92

IN

92

IN

92

OUT

92

OUT

96

BI

96

BI

96

BI

95

BI

95

BI

95

BI

92

IN

92

IN

92

OUT

92

OUT

BI

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

PP20V_USBC_TA_VBUS

CRITICAL

DB500

DSN2

VOLTAGE=20V

94

MIN_LINE_WIDTH=0.0900

USBC_TB_CC1

USBC_TB_R2D_C_N<1>

USBC_TB_R2D_C_P<1> USBC_TB_D2R_N<1> USBC_TB_D2R_P<1> USBC_TB_SBU2 USBC_TB_USB_BOT_N USBC_TB_USB_BOT_P

GND_VOID=TRUE

USBC_TA_USB_BOT_N USBC_TA_USB_BOT_P

USBC_TA_SBU1

USBC_TA_R2D_C_P<2>

USBC_TA_R2D_C_N<2>

USBC_TA_D2R_P<2> USBC_TA_D2R_N<2>

USBC_TA_CC2

2

1

5.5V-6.2PF

0201-THICKSTNCL

1

2

OMIT_TABLE

K

A

DZB501

CB504

1UF

10% 25V X5R 402

2

ESD8011

DB554

1

X3DFN2-THICKSTNCL

GND_VOID=TRUE

CB573

GND_VOID=TRUE

CB572

GND_VOID=TRUE

ESD8011

DB527

X3DFN2-THICKSTNCL

K

1610

ESDA25P35-1U1M

DB501

A

CRITICAL

DB570

DSN2

NSR20F40NX_G

GND_VOID=TRUE

CB591

GND_VOID=TRUE

CB590

GND_VOID=TRUE

2

1

2

1

DB549

1 2

2

1

XWB500

SM

1 2

ESD8011

X3DFN2-THICKSTNCL

10%

ESD8011

DB526

12

K

OMIT_TABLE

CB554

1UF

10%

A

GND_VOID=TRUE

0.22UF

6.3V

GND_VOID=TRUE

0.22UF

6.3V 0201

10% X5R-CERM

2

DZB550

0.22UF

X3DFN2-THICKSTNCL

1

5.5V-6.2PF

0201-THICKSTNCL

GND_VOID=TRUE

6.3V 0201

DB525

X5R-CERM

GND_VOID=TRUE

ESD8011

X3DFN2-THICKSTNCL

VOLTAGE=20V

PP20V_USBC_TA_VBUS_CONN

25V X5R 402

2

1

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

K

1

1610

ESDA25P35-1U1M

DB502

2

020110% X5R-CERM

GND_VOID=TRUE

ESD8011

DB553

USBC_TA_R2D_P<2>

020110% 6.3V

USBC_TA_R2D_N<2>

2

ESD8011

1

DB524

A

GND_VOID=TRUE

2

1

X3DFN2-THICKSTNCL

1

DZB503

X3DFN2-THICKSTNCL

0201-THICKSTNCL

BYPASS=JB500.59::2MM

XWB550

SM

12

USBC_TB_R2D_N<1>

USBC_TB_R2D_P<1>

GND_VOID=TRUE

ESD8011

DB552

X3DFN2-THICKSTNCL

GND_VOID=TRUE

2

ESD8011

5.5V-6.2PF

1

DB512

CRITICAL

1

CB500

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=JB500.59::2MM

CRITICAL

1

CB506

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=JB500.59::2MM

ESD8011

DB551

X3DFN2-THICKSTNCL

GND_VOID=TRUE

2

1

X3DFN2-THICKSTNCL

CRITICAL

1

2

CRITICAL

1

2

GND_VOID=TRUE

2

ESD8011

1

2

1

DB528

BYPASS=JB500.59::2MM

DB550

X3DFN2-THICKSTNCL

ESD8011

X3DFN2-THICKSTNCL

PLACE VBUS CAP NEAR EACH VBUS PIN

CRITICAL

CB501

0.01UF

10% 25V X5R-CERM 0201

1

CB502

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

CB507

0.01UF

10% 25V X5R-CERM 0201

BYPASS=JB500.59::2MM

1

CB508

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=JB500.59::2MM

VOLTAGE=20V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520MIN_NECK_WIDTH=0.0520

PP20V_USBC_TB_VBUS_CONNPP20V_USBC_TB_VBUS

2

5.5V-6.2PF

DZB552

0201-THICKSTNCL

1

BYPASS=JB500.59::2MM

CRITICAL

1

CB503

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=JB500.59::2MM

CRITICAL

1

CB509

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=JB500.59::2MM

CRITICAL

1

CB512

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

CB505

0.01UF

10% 25V

2

X5R-CERM 0201

20759-056E-02

GND_VOID=TRUE GND_VOID=TRUE

JB500

F-ST-SM

57 58

PWR

SIGNAL

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

PWR

59 60

GND

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

TP_USBC_PP20V_TB

GND_VOID=TRUE GND_VOID=TRUE

TP_USBC_PP20V_TA

BYPASS=JB500.58::2MM

104

OUT

5.5V-6.2PF

DZB551

0201-THICKSTNCL

OUT

DZB500

104

2

1

5.5V-6.2PF

0201-THICKSTNCL

BYPASS=JB500.58::2MM

CRITICAL

1

CB550

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=JB500.58::2MM

1

2

CRITICAL

1

2

1

2

1

GND_VOID=TRUE

ESD8011

DB521

DB555

GND_VOID=TRUE

2

1

X3DFN2-THICKSTNCL

CB556

0.01UF

10% 25V X5R-CERM 0201

CB560

3.0PF

+/-0.1PF 25V NP0-C0G 0201

GND_VOID=TRUE

2

ESD8011

1

X3DFN2-THICKSTNCL

2

1

ESD8011

DB520

1

2

BYPASS=JB500.58::2MM

1

2

X3DFN2-THICKSTNCL

PP20V_USBC_TA_VBUS_CONN

PLACE VBUS CAP NEAR EACH VBUS PIN

BYPASS=JB500.58::2MM

CRITICAL

CB551

0.01UF

10% 25V X5R-CERM 0201

CRITICAL

CB557

0.01UF

10% 25V X5R-CERM 0201

CB566

3.0PF

+/-0.1PF 25V NP0-C0G 0201

CRITICAL

1

CB552

0.01UF

10% 25V

2

X5R-CERM 0201

CRITICAL

1

CB558

0.01UF

10% 25V

2

X5R-CERM 0201

1

CB561

12PF

5% 25V

2

NP0-C0G 0201

USBC_TB_R2D_N<2>

USBC_TB_R2D_P<2>

GND_VOID=TRUE

2

ESD8011

DB556

X3DFN2-THICKSTNCL

ESD8011

DB558

1

X3DFN2-THICKSTNCL

USBC_TA_R2D_P<1>

USBC_TA_R2D_N<1>

GND_VOID=TRUE

2

ESD8011

DB504

1

X3DFN2-THICKSTNCL

104 97

1

DB529

BYPASS=JB500.58::2MM

CRITICAL

1

CB553

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=JB500.58::2MM

CRITICAL

1

CB559

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=JB500.58::2MM

1

CB563

12PF

5% 25V

2

NP0-C0G 0201

BYPASS=JB500.58::2MM

CB592

GND_VOID=TRUE

CB593

GND_VOID=TRUE

2

ESD8011

1

DB560

GND_VOID=TRUE

ESD8011

DB559

X3DFN2-THICKSTNCL

CB570

GND_VOID=TRUE GND_VOID=TRUE

CB571

GND_VOID=TRUE

2

ESD8011

X3DFN2-THICKSTNCL

ESD8011

DB523

1

X3DFN2-THICKSTNCL

CRITICAL

1

CB562

0.01UF

10% 25V

2

X5R-CERM 0201

BYPASS=JB500.58::2MM

1

CB564

12PF

5% 25V

2

NP0-C0G 0201

1 2

GND_VOID=TRUE

2

1

X3DFN2-THICKSTNCL

1 2

2

1

CB565

12PF

2

GND_VOID=TRUEGND_VOID=TRUE

0.22UF

GND_VOID=TRUE

0.22UF

DB557

GND_VOID=TRUE

0.22UF

10% 6.3V X5R-CERM 0201

ESD8011

DB522

X3DFN2-THICKSTNCL

CRITICAL

1

CB555

0.01UF

10% 25V

2

X5R-CERM 0201

5% 25V NP0-C0G 0201

2

ESD8011

X3DFN2-THICKSTNCL

1

5.5V-6.2PF

DZB553

0201-THICKSTNCL

USBC_TA_SBU2

USBC_TA_USB_TOP_P USBC_TA_USB_TOP_N

USBC_TA_D2R_P<1> USBC_TA_D2R_N<1>

2

5.5V-6.2PF

DZB502

1

0201-THICKSTNCL

USBC_TB_CC2

USBC_TB_R2D_C_N<2>

0201X5R-CERM6.3V10%

USBC_TB_R2D_C_P<2>

0201X5R-CERM6.3V10%

USBC_TB_USB_TOP_P USBC_TB_USB_TOP_N USBC_TB_D2R_N<2> USBC_TB_D2R_P<2>

USBC_TB_SBU1

USBC_TA_R2D_C_P<1>

0201X5R-CERM6.3V10%

USBC_TA_R2D_C_N<1>

USBC_TA_CC1

OUT

BI

IN

BI

OUT

IN

BI

92

96

95

92

95

92

104

104 96 94

CC2

TBT_R2D1

USB2 TOP

TBT_D2R1

SBU1

SBU2

TBT_R2D0

USB2 BOT

TBT_D2R0

95 94

CC1

D

C

B

A

1

CB510

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CB516

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

1

CB511

12PF

5% 25V

2

NP0-C0G 0201

1

CB513

12PF

5% 25V

2

NP0-C0G 0201

1

CB514

12PF

5% 25V

2

NP0-C0G 0201

1

CB515

12PF

5% 25V

2

NP0-C0G 0201

2

CAP,CER,X5R,1UF,10%,25V,0402

BOM_COST_GROUP=USB-C

CB504, CB554

SYNC_MASTER=J79_GREG SYNC_DATE=07/05/2016

PAGE TITLE

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

CRITICAL138S0683 NOSTUFF

LAST CHANGE: Wed Apr 1 22:57:37 2015

USB-C CONNECTOR A

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

051-00515

REVISION

BRANCH

dvt-fab09-0

PAGE

115 OF 145

SHEET

97 OF 119

A

D

9.0.0

8 7 5 4 2 1

36

345678

2 1

D

C

95

96

IN

P3V3_TBT_T_SX_EN_R

MAKE_BASE=TRUE

P3V3_TBT_T_SX_EN_R

RB601

0

1 2

1/20W

1

RB605

100K

5% 1/20W MF 201

2

5%

MF

201

P3V3_TBT_T_SX_EN

95

IN

TBT T "POC" Power-up Reset

1

USBC_T_RESET_L_R

NOSTUFF

RB600

0

1 2

5%

402

1/16WMF-LF

CRITICAL

UB600

SLG5AP1449V

STDFN

ON

GND

4

2

D

3

S

1

RB602

100K

1% 1/20W MF 201

2

MAKE_BASE=TRUE

PP3V3_S5

USBC_T_RESET_L_R

TBTTPOCRST_SNS

CRITICAL

TPS3895ADRY

1

3

SENSE

6

VCC

UB601

USON

SENSE_OUTENABLE

MAKE_BASE=TRUE

101

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V

PP3V3_S5_TBT_T_SW

Output

Delay

Vth

4

USBC_T_RESET_L

5

CT

TBTTPOCRST_CT

93 94

92

UB601

Push-pull

440us +/- 20us

2.508V nominal

OUT

D

C

94 92

B

1

RB603

24.9K

1% 1/20W MF 201

2

GND

2

NOSTUFF

RB604

0

1 2

5%

1/20W

MF

201

CB600

100PF

5% 25V C0G

0201

1

2

B

A

DESIGN: j130/dev_mlb_u LAST CHANGE: Wed Apr 1 22:57:37 2015

PAGE TITLE

USB-C CONNECTOR B

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

BOM_COST_GROUP=USB-C

8 7 5 4 2 1

36

.

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2016SYNC_MASTER=J79_GREG

051-00515

9.0.0

dvt-fab09-0

116 OF 145

98 OF 119

A

D

345678

2 1

D

PP5V_S4_T_USBC

94 99

XWB701

P5VUSBC_T_RTN_DIV_R

SM

RB703

27.4K

0.1%

1/20W

MF

0201

NO_XNET_CONNECTION=1

PP5V_S4

101

RB701

2

XWB702

SM

1

P5VUSBC_T_SENSE_DIV_R

1

2

1

RB731

27.4K

0.1% 1/20W MF 0201

2

NO_XNET_CONNECTION=1

1

RB717

191K

0.1% 1/20W MF 0201

2

1

CB717

22PF

5% 50V

2

C0G 0201

PP5V_USBC_T_VCC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

VOLTAGE=5V

1

CB722

2.2UF

10% 10V

2

X6S-CERM 0402

94

UPC_T_5V_EN

IN

102

P5VUSBC_T_SENSE_DIV

P5VUSBC_T_SREF

P5VUSBC_T_VO

P5VUSBC_T_OCSET

NC_P5VUSBC_T_PGOOD

P5VUSBC_T_RTN_DIV

P5VUSBC_T_FSEL

10

7

12

11

14

13

4

EN

FB

SREF

VO

OCSET

PGOOD

RTN

FSEL

1

2.2

5%

1/20W

MF

201

2

19

UB700

ISL95870AH

UTQFN

CRITICAL

1

2

20

PVCCVCC

RB706

2.2

5% 1/20W MF 201

BOOT

UGATE

PHASE

LGATE

VOLTAGE=5V

PP5V_USBC_T_PVCC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520

1

2

1815

17

16

1

CB721

10UF

20% 10V X5R-CERM 0402-7

P5VUSBC_T_VBST

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

P5VUSBC_T_DRVH_R

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUE DIDT=TRUE

P5VUSBC_T_LL

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 SWITCH_NODE=TRUE

DIDT=TRUE

P5VUSBC_T_DRVL

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUE DIDT=TRUE

PPBUS_G3H

33 100

RB709

2.2

5%

1/20W

MF

201

P5VUSBC_T_BOOT_RC

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 DIDT=TRUE

1

2

CB716

0.1UF

10% 16V

2

X7R-CERM 0402

RB739

0

12

5%

1/20W

MF

P5VUSBC_T_DRVH

0201

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 GATE_NODE=TRUE DIDT=TRUE

CB704

33UF

20% 16V

TANT-POLY

CASE-B3

QB701

FDPC1012S

1

HSG

2

SW

3 4

1

2

LLP

CB703

33UF

20% 16V

TANT-POLY

CASE-B3

V+

8

V+

9

LSG

7

1

CB700

2.2UF

20% 25V

2

X5R-CERM 0402-1

20% 16V

1

2

1

CB702

33UF

2

TANT-POLY

CASE-B3

LB700

1.5UH-20%-12.5A-0.017OHM

1 2

PIMB062D-SM

P5VUSBC_T_R

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

1

CB701

2.2UF

20% 25V

2

X5R-CERM 0402-1

P5VUSBC_T_POS

CRITICAL

RB730

0.002

1%

1/2W

MF

0306

PP5V_S4_T_USBC

CRITICAL

1

CB710

12PF

5% 25V

2

NP0-C0G 0201

2.4G DESENSE

12 34

20% 25V

1

2

1

CB709

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

CB705

2.2UF

20% 25V

X5R-CERM

0402-1

1

CB706

2.2UF

2

X5R-CERM

0402-1

5G DESENSE

1

2

CRITICAL

1

CB711

3.0PF

+/-0.1PF 25V

2

NP0-C0G 0201

CB708

150UF

20%

6.3V TANT-POLY CASE-B1S-1

94 99

1

CB707

150UF

20%

6.3V

2

TANT-POLY CASE-B1S-1

D

C

1

CB726

10PF

5% 50V

2

C0G 0201

1

RB704

10K

0.1% 1/20W MF 0201-1

2

1

RB702

10K

0.1% 1/20W

0201-1

2

CB723

1

CB715

10PF

5% 50V

2MF

C0G 0201

0.1UF

10% 16V

X5R-CERM

0201

1

2

1

RB718

95.3K

0.1% 1/20W MF 0201

2

P5VUSBC_T_SET_R

NOSTUFF

RB713

5%

1/20W

MF

201

1

0

2

P5VUSBC_T_SET0

P5VUSBC_T_SET1

RB700

11K

1 2

1%

1/20W

MF

201

P5VUSBC_T_AGND

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

8

SET0

9

SET1

6

VID0

5

VID1

3

XWB700

SM

1 2

PLACE_NEAR=UB700.2:1mm

GND

5

GND

6

GND

10

P5VUSBC_T_NEG

Vout = 5.036V

1%

1/20W

MF

201

1

Freq = 500 kHz

CB770

2

2200PF

12

10% 25V

CER-X7R

0201

1

RB772

2.55K

1% 1/20W MF 201

2

Max OCP = 13.05A Nom OCP = 10.84A

Min OCP = 7.94A

C

RB721

2.55K

PGNDGND

2

B

A

PAGE TITLE

TBT 5V REGULATOR

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

BOM_COST_GROUP=USB-C

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=12/18/2015SYNC_MASTER=J79_JSHAO

051-00515

9.0.0

dvt-fab09-0

117 OF 145

99 OF 119

A

D

345678

2 1

D

C

52

66

PPBUS_G3H

PPBUS_HS_CPU

52

PPBUS_HS_OTH5V

PPBUS_HS_OTH3V3

PPBUS_S4_HS_TPAD

PBUS Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=13.1V MAKE_BASE=TRUE

PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H

PPBUS_HS_CPU

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=13.1V MAKE_BASE=TRUE

PPBUS_HS_CPU PPBUS_HS_CPU PPBUS_HS_CPU PPBUS_HS_CPU PPBUS_HS_CPU PPBUS_HS_CPU PPBUS_HS_CPU

PPBUS_HS_OTH5V

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=13.1V MAKE_BASE=TRUE

PPBUS_HS_OTH5V

PPBUS_HS_OTH3V3

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=13.1V MAKE_BASE=TRUE

PPBUS_HS_OTH3V3

PPBUS_S4_HS_TPAD

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=13.1V MAKE_BASE=TRUE

PPBUS_S4_HS_TPAD

52

79

52

74

65

76

33 99

76

68

70

75

73

75

67

72

43

62 63

91

IMVP Rails

68

70

PPVCC_S0_CPU

PPVCCSA_S0_CPU

PPVCCGT_S0_CPU

CPU VCCIO Rails

PPVCCIO_S0_CPU

75

CPU EDRAM Rails

73

PPVCCEDRAM_S0_CPU

PCH Prime Core Rails

PPVCC_S0_CPU

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.5V MAKE_BASE=TRUE

PPVCC_S0_CPU PPVCC_S0_CPU

PPVCCSA_S0_CPU

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.5V MAKE_BASE=TRUE

PPVCCSA_S0_CPU PPVCCSA_S0_CPU

PPVCCGT_S0_CPU

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.5V MAKE_BASE=TRUE

PPVCCGT_S0_CPU PPVCCGT_S0_CPU PPVCCGT_S0_CPU PPVCCGT_S0_CPU

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.95V MAKE_BASE=TRUE

PPVCCIO_S0_CPU PPVCCIO_S0_CPU

PPVCCEDRAM_S0_CPU

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.05V MAKE_BASE=TRUE

PPVCCEDRAM_S0_CPU PPVCCEDRAM_S0_CPU PPVCCEDRAM_S0_CPU PPVCCEDRAM_S0_CPU PPVCCEDRAM_S0_CPU PPVCCEDRAM_S0_CPU PPVCCEDRAM_S0_CPU

8 54 104

10

8 55

10

8 54

11

8

11

5 8

10

8

10

0V6 Rails

75

PP0V6_S0_DDRVTT

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=0.6V MAKE_BASE=TRUE

PP0V6_S0_DDRVTT PP0V6_S0_DDRVTT

25

D

PP0V6_S3_MEM_VREFDQ_A

20

PP0V6_S3_MEM_VREFCA_A

20 100

PP0V6_S3_MEM_VREFDQ_B

20

PP0V6_S3_MEM_VREFCA_A

20 100

PP0V6_S3_MEM_VREFDQ_A

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFCA_A

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFDQ_B

MAKE_BASE=TRUE

VOLTAGE=0.6V

PP0V6_S3_MEM_VREFCA_A

MAKE_BASE=TRUE

VOLTAGE=0.6V

22 21

24 23

23 24

1V8 Rails

76

8

78

PP1V8_SUS

PP1V8_S4

PP1V8_SUS

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_SUS PP1V8_SUS

PP1V8_SUS PP1V8_SUS PP1V8_SUS PP1V8_SUS PP1V8_SUS

PP1V8_S4

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V MAKE_BASE=TRUE

PP1V8_S4 PP1V8_S4

8 14 19

8 12

78

8

12

38 42

18 19 35

C

B

A

PP3V3_G3H

65 104

PP3V3_G3H_SMC_ISNS

48 49 57

PP3V0_G3H

74

PPDCIN_G3H

29 30 94 95 96

PPDCIN_G3H

52

3V3 G3H Rails

RTC Rails

MAKE_BASE=TRUE

PPDCIN_G3H

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=20V

PP3V3_G3H

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H

PP3V3_G3H

PP3V3_G3H PP3V3_G3H PP3V3_G3H

PP3V3_G3H PP3V3_G3H PP3V3_G3H PP3V3_G3H

PP3V3_G3H

PP3V3_G3H PP3V3_G3H PP3V3_G3H

PP3V3_G3H_SMC_ISNS

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V0_G3H

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.0V MAKE_BASE=TRUE

PP3V0_G3H

104 66

59

57 80

50 100

66

43 50 104

51

49

18

51

29

30

106

77

95

96

50 100

8 12 14 15

74

PPVCCPRIMCORE_SUS_PCH

76

1V2 Rails

75 78

53

78

PP1V2_S3

PP1V2_S3_CPUDDR

PP1V2_S0SW

PPVCCPRIMCORE_SUS_PCH

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.0V MAKE_BASE=TRUE

PPVCCPRIMCORE_SUS_PCH

PP1V2_S3

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.2V MAKE_BASE=TRUE

PP1V2_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3 PP1V2_S3

PP1V2_S3_CPUDDR

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.2V MAKE_BASE=TRUE

PP1V2_S3_CPUDDR PP1V2_S3_CPUDDR PP1V2_S3_CPUDDR PP1V2_S3_CPUDDR

PP1V2_S0SW

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.2V MAKE_BASE=TRUE

PP1V2_S0SW

8 12 55

21 22 23 24

75

20

21 22 23 24

53

78

8

10

8 10

78

55

PP1V8_S3

PP1V8_S3_MEM

PP1V8_S0

PP1V8_S3

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_S3 PP1V8_S3

PP1V8_S3_MEM

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_S3_MEM

PP1V8_S0

MIN_LINE_WIDTH=0.0900 MIN_NECK_WIDTH=0.0520 VOLTAGE=3.3V MAKE_BASE=TRUE

PP1V8_S0 PP1V8_S0

PP1V8_S0

PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0

PP1V8_S0

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

55

74

21 22 23 24

106

12

60 62 63 104

19 106

37 38 42

74

18

37 42

37

19

Power Aliases - 1

Apple Inc.

R

SYNC_DATE=06/17/2015SYNC_MASTER=J79_ALFRED

DRAWING NUMBER SIZE

051-00515

REVISION

D

9.0.0

BRANCH

dvt-fab09-0

PAGE

120 OF 145

SHEET

100 OF 119

B

A

8 7 5 4 2 1

36