Apple MacBook Pro Retina 15 A1398 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

2 1

REV ECN

DESCRIPTION OF REVISION

CK APPD

DATE

2012-05-09

SCHEM,MLB,KEPLER,2PHASE,D2

FSB, 5/9/2012

苹果笔记本维修交流群群号：３２５７４２６３４

Date

SyncPage

03/05/2012

01/13/2012

03/16/2012

01/13/2012

03/05/2012

01/13/2012

03/05/2012

01/13/2012

03/05/2012

01/13/2012

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

91 92 93 94 95 96 97 98 99

(.csa)

102

PCH Constraints 1

103

PCH Constraints 2

105

Thunderbolt Constraints

106

SMC Constraints

107

GPU (Kepler) CONSTRAINTS

108

Project Specific Constraints

109

PCB Rule Definitions

130

DEBUG SENSORS AND ADC

132

SMC12 SENSORS EXTENDED

Contents

D2_KEPLER

D2_CLEAN

D2_KEPLER

D2_SEAN

D2_KEPLER

Date

SyncPage

01/13/2012

03/15/2012

01/13/2012

03/05/2012

01/13/2012

D

C

B

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

(.csa)

54

High Side and CPU/AXG Current Sensing

55

Thermal Sensors

56

Fan Connectors

57

KEYBOARD/TRACKPAD (1 OF 2)

58

KEYBOARD/TRACKPAD (2 OF 2)

59

DIGITAL ACCELEROMETER & GYRO

61

SPI ROM

62

AUDIO: CODEC/REGULATOR

63

AUDIO: HEADPHONE FILTER

64

AUDIO: IV SENSE

65

AUDIO: IV SENSE FILTER

66

AUDIO: SPEAKER AMP

67

AUDIO: JACK

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

System Agent Supply

72

5V / 3.3V Power Supply

73

1V5R1V35V DDR3 SUPPLY

74

CPU IMVP7 & AXG VCore Regulator

75

CPU IMVP7 & AXG VCore Output

76

CPU VCCIO (1V0R1V05 S0) POWER SUPPLY

77

Misc Power Supplies

78

Power FETs

79

Power Control 1/ENABLE

80

KEPLER PCI-E

81

KEPLER CORE/FB POWER

82

KEPLER FRAME BUFFER I/F

83

1V05 GPU / 1V35 FB POWER SUPPLY

84

GDDR5 Frame Buffer A

85

GDDR5 Frame Buffer B

86

KEPLER EDP/DP/GPIO

87

KEPLER GPIOS,CLK & STRAPS

88

KEPLER PEX PWR/GNDS

89

GFX IMVP VCore Regulator

90

eDP Display Connector

91

eDP Mux

92

eDP Muxed Graphics Support

94

Thunderbolt Connector A

96

Thunderbolt Connector B

97

LCD Backlight Driver (LP8545)

98

PCH VCCIO (1.05V) POWER SUPPLY

99

Power Sequencing EG/PCH S0

100

CPU Constraints

101

Memory Constraints

Contents

D2_SEAN

D2_KEPLER

D2_CARA

D2_KEPLER

D2_SEAN

D2_KEPLER

D2_SEAN

D2_KEPLER

D2_SEAN

D2_KEPLER

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

42 43 44 45

(.csa)

1

1 2 3 4 5 6 7 8 9

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

Revision History

5

BOM Configuration

6

BOM Variants

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU DMI/PEG/FDI/RSVD

11

CPU CLOCK/MISC/JTAG

12

CPU DDR3 INTERFACES

13

CPU POWER

14

CPU POWER AND GND

16

CPU DECOUPLING-I

17

CPU DECOUPLING-II

18

PCH SATA/PCIe/CLK/LPC/SPI

19

PCH DMI/FDI/PM/Graphics

20

PCH PCI/USB/TP/RSVD

21

PCH GPIO/MISC/NCTF

22

PCH POWER

23

PCH GROUNDS

24

PCH DECOUPLING

25

CPU & PCH XDP

26

Chipset Support

27

USB HUB & MUX

28

CPU Memory S3 Support

29

DDR3 SDRAM Bank A (1 OF 2)

30

DDR3 SDRAM Bank A (2 OF 2)

31

DDR3 SDRAM Bank B (1 OF 2)

32

DDR3 SDRAM Bank B (2 OF 2)

33

DDR3 Termination

34

DDR3/FRAMEBUF VREF MARGINING

35

X29/ALS/CAMERA CONNECTOR

36

Thunderbolt Host (1 of 2)

37

Thunderbolt Host (2 of 2)

38

Thunderbolt Power Support

44

RIO CONNECTOR

45

SSD CONNECTOR

46

USB 3.0 CONNECTORS

49

SMC41

50

SMC Support

51

LPC+SPI Debug Connector

52

SMBus Connections

53

Voltage & Load Side Current Sensing

Contents

D2_KEPLER

D2_SEAN

D2_KEPLER

D2_CLEAN

D2_KEPLER

D2_CLEAN

D2_KEPLER

D2_SEAN

D

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

C

B

TABLE_TABLEOFCONTENTS_ITEM

Date

SyncPage

01/13/2012

03/05/2012

01/13/2012

03/19/2012

01/13/2012

03/19/2012

01/13/2012

03/05/2012

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

A

Schematic / PCB #’s

PART NUMBER

051-9589

820-3332

DRAWING

TITLE=MLB ABBREV=ABBREV

LAST_MODIFIED=Wed May 9 13:50:52 2012

QTY

1

DESCRIPTION

SCHEM,MLB,KEPLER_2PHASE,D2

PCBF,MLB,KEPLER_2PHASE,D2

REFERENCE DES

SCH1

PCB

CRITICAL

BOM OPTION

苹果笔记本维修交流群群号：３２５７４２６３４

SIZE

A

D

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

3

SCHEM,MLB,KEPLER,2PHASE,D2

Apple Inc.

R

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

SHEET

1245678

4.18.0

1 OF 132

1 OF 99

8 7 6 5 4 3

12

2 DIMMS

RTC

PG 16

J2500,J2550

XDP CONN

J2900

J3100

DIMM

PG 26,28

苹果笔记本维修交流群群号：３２５７４２６３４

PG 23

J6950

DC/BATT

PG 63

U6100

U4900

POWER SUPPLY

D

U8000

AMD WHISTLER

GRAPHICS

PG 73

INTEL CPU

2.X GHZ

IVY BRIDGE

PG 9

DDR3-1067/1333MHZ

D

GPIO

PG 19

FDI

PG 17

DMI

PG 17

SPI

CLOCK

U2700

CK5G05

PG 24

J4501

SATA

ODD

CONN

PG 41

J4500

SATA

C

HDD

CONN

PG 41

CLK

BUFFER

PG 16

SATA2.0/3(GB/S)

4 5

SATA

SATA2.0/3(GB/S)

PG 16

SATA2.0/3(GB/S)

2 3

SATA3.0/6(GB/S)

10

SATA3.0/6(GB/S)

INTEL

PANTHER-POINT

MOBILE

U1800

Misc

PG 19

SPI

PG 16

J5100

LPC

PG 16

PWR

DP OUT

U9320

DP MUX

XP25-5G

PG 83

J9400

MINI DP PORT

PG 84

U9370

B

DDC MUX

PG 83

RGB OUT

HDMI OUT

DVI OUT

LVDS OUT

TMDS OUT

PG 18

PCI

PG 18

JTAG

PG 16

PEG

PG 16

PCI-E

(UP TO 16 LINES)

PG 16

CTRL

PG 17

PG 18

USB

(UP TO 14 DEVICES)

SMB

PG 16

HDA

PG 16

10 11 1312 98654 73210

LCD PANEL

Boot ROM

PG 55

LPC + SPI CONN Port80,serial

PG 46

U3600

USB

HUB 2

PG 33

U3700

USB

HUB 1

PG 34

DIMM

PG 26,28

Ser

BSBB,0

Prt

U4900

J3402

J4501

J4610

(RESERVATION)

J5713

TRACKPAD/KEYBOARD

J3401

J4600

CAMERA

IR

EXTERNAL B

EXTERNAL C

BLUETOOTH

EXTERNAL A

SMC

PG 44

Fan

ADC

PG 31

PG 41

PG 33

PG 53

PG 31

PG 34

TEMP SENSOR

PG 44

POWER SENSE

PG 44

J5650,5660

FAN CONN AND CONTROL

PG 51

SMBUS

CONNECTION

PG 47

C

B

U9600

GMUX

PG 86

U4100

A

J3401

FW643

PG 38

AirPort

J4310PG 31

FIREWIRE

CONN

PG 40

U3900

J4000

GB

E-NET

BCM57765

PG 36

E-NET

CONN

PG 37

J3500

SDCARD READER

CONN

PG 37

6 3

LINE TIN

FILTER

PG 57

U6201

J6700,J6750

AUDIO CODEC

PG 56

HEADPHONE

FILTER

PG 58

AUDIO

CONN

PG 60

U6610,6620,6630

SPEATKER

AMP

PG 59

SPEATKER

PG 63

苹果笔记本维修交流群群号：３２５７４２６３４

SYNC_MASTER=D2_KEPLER

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

2 OF 132

SHEET

2 OF 99

124578

SIZE

A

D

苹果笔记本维修交流群群号：３２５７４２６３４

D

C

B

A

J6900

AC

ADAPTER

IN

J6950

3S2P

(9 TO 12.6V)

GMUX

U9600

XP25-5

(PAGE 86)

SMC

U4900

(PAGE 44)

PANTHER-POINT

MOBILE

SLP_S5#(E4)

U1800

SLP_S4#(H7)

SLP_S3#(P12)

(PAGE 16~21)

8 7 6 5 4 3

D6990

PP1V0_S0GPU_REG

R5413

PP1V5_GPU_REG

A

SMC_GPU_1V8_ISENSE

EN1

EN2

TPS51125

(PAGE 65)

PGOOD

PPVOUT_S0_LCDBKLT

P1V5CPU_EN

VIN

VREG5

VOUT1

5V

(L/H)

VOUT2

3.3V

(R/H)

U7201

P5V3V3_PGOOD

PPBUS_G3H

PP5V_S3_GFXIMVP6_VDD

DDRREG_EN

DDRVTT_EN

PP5V_S3

PP3V3_S5

SMC_PBUS_VSENSE

GPUVCORE_EN

SMC_CPU_HI_ISENSE

VIN

ON

SLG5AP020

U7801

V

PP5V_S3_DDRREG

S5

S3

PP1V5_S3

G

PP3V3_S5

Q7870

Q7810

Q7830

P1V8_S0_EN

Q5315

VDD

GPU VCORE

ISL6263C

U8900

VR_ON

(PAGE 82)

R5388/U5388

A

VIN

1.5V

0.75V

TPS51116

U7300

(PAGE 66)

P1V5S0FET_GATE

PP3V3_S0GPU

P3V3GPU_EN

PP3V3_S3

P3V3S3_EN

PP3V3_S0_FET

P3V3S0_EN

P1V2ENET_EN

ENABLE

3.425V G3HOT

VIN

VOUT

PGOOD

CPUIMVP7_VR_ON

VLDOIN

VOUT1

VOUT2

PGOOD

Q7801

PP1V5_S3RS0

(PAGE 39)

ISL8014A

EN

U7720

(PAGE 70)

EN

U7760

(PAGE 70)

PM6640

U6990

(PAGE 62)

U5410

SMC_GPU_ISENSE

GPUVCORE_PGOOD

VIN

VR_ON

PPDDR_S3_REG

PPVTT_S0_DDR_LDO

DDRREG_PGOOD

P1V8FB_EN

TPS22924

U4201

EN

FW_PWR_EN

VIN

VOUT

PGOOD

VIN

ISL8014A

VOUT

PGOOD

PP3V42_G3H

A

CPU VCORE

ISL95831

U7400

(PAGE 67)

Q7860

PP3V3_FW_FWPHY

PP1V8_S0

P1V8S0_PGOOD

PP1V2_ENET

P1V2ENET_PGOOD

SMC_GPU_VSENSE

V

PPVCORE_GPU

VOUT

PGOOD

A

SMC_CPU_ISENSE

CPUIMVP7_AXG_PGOOD

R7350

SMC_DDR_ISENSE

A

PP5V_S0

P5VS0_EN

PP1V8_S0

VIN

ON

G

SLG5AP020

U7880

Q7922

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

Q7850

SMC_CPU_DDR_VSENSE

PP3V3_S0

Q7880

P1V8GPUIFPXFET_GATE

PP3V3_ENET

PP3V3_S0

PP1V5_S0

PP1V05_S0

PP1V2_S0

P1V2S0_EN

NCP303LSN

SMC_CPU_VSENSE

V

U5440

VIN

SMC PWRGD

U5000

(PAGE 45)

PP5V_S0_CPUVTTS0

PPVCORE_S0_CPU

V

EN

PM_ALL_GPU_PGOOD

PP1V8_GPUIFPX

PP3V3_S0

P60

DELAY

RC

DCIN(16.5V)

PB16B

PB17A

PB17B

PB18A

PL32A

SMC_PM_G2_EN

D2 POWER SYSTEM ARCHITECTURE

PP18V5_DCIN_CONN

F6905 6A FUSE

PPVBATT_G3H_CONN

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL4_EN

PM_ALL_GPU_PGOOD

R7978

PM_SLP_S3_L_R

P1V8S0_EN

P1V2S0_EN

CPUVTTS0_EN

P1V5CPU_EN

RC

DELAY

PM_SLP_S5_L

RC

DELAY

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

P5VS3_EN

DDRREG_EN

P3V3S3_EN

R7020

SMC_DCIN_ISENSE

SMC_RESET_L

P1V1GPU_EN

P3V3GPU_EN

GPUVCORE_EN

P3V3S5_EN

A

VIN

Q7055

CHGR_BGATE

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

U7000

ISL6259HRTZ

PBUS SUPPLY/

BATTERY CHARGER

(PAGE 64)

R6990

VOUT

PPVBAT_G3H_CHGR_R

P1V0GPU_EN

P1V5FB_EN

BKLT_PLT_RST_L

&&

LCD_BKLT_NO

SMC_ADAPTER_EN&&PM_SLP_S3_L

PPVBAT_G3H

R7050

SMC_BATT_ISENSE

Q9806

BKLT_EN

Q4260

VIN

EN1

1.003V(L/H)

EN2

1.503V(R/H)

ISL6236

U9500

(PAGE 85)

ENA

PPBUS_G3H

F7040

8A FUSE

A

www.qdzbwx.com

VOUT1

VOUT2

P1V0GPU_PGOOD

POK1

P1V5FB_PGOOD

POK2

P5VS3_EN

P3V3S5_EN

VIN

LP8550

U9701

VOUT

(PAGE 87)

PFWBOOST

6 3

CPUVTTS0_EN

PP1V5_S3

4.5V

MAX8840

U6200

S0PGOOD_PWROK

VOUT

P1V8S0_PGOOD

P5V3V3_PGOOD

V2MON

U7971

ISL88042IRTJJZ

V3MON

V4MON

(PAGE 72)

TRST = 200mS

SMC_RESET_L

VIN

1.05V

ISL95870

U7600

EN

(PAGE 70)

PP4V5_AUDIO_ANALOG

U7980

PP3V3_S0_PWRCTL

VCC

RST*

SMC AVREF SUPPLY

VIN

REF3333

(PAGE 45)

VOUT

PGOOD

RSMRST_PWRGD

SMC_ONOFF_L

VOUT

R7640

CPUVTTS0_PGOOD

PM_PCH_PWRGD

U2850

ALL_SYS_PWRGD

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

12

PP3V3_S5_AVREF_SMC

PPCPUVTT_S0

A

SMC_CPU_FSB_ISENSE

PANTHER_POINT

PS_PWRGD

U1800

(PAGE 16~21)

SM_DRAMPWROK

CPU

U1000

VCCCPUPWRGD

(PAGE 9~14)

SMC

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

H8S2117

U4900

(PAGE 45)

(P64)

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

P17(BTN_OUT)

苹果笔记本维修交流群群号：３２５７４２６３４

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

Power Block Diagram

R

PP3V3_S5_SMC

SMC_TPAD_RST_L

SMC_ONOFF_L

TPS22924

U4202

(PAGE 39)

EN

PM_PWRBTN_L

PWRBTN#

SYS_RERST#

RSMRST#

ACPRESENT

PLT_RERST_L

PLTRST#

CPU_PWRGD

PROCPWRGD

PM_MEM_PWRGD

DRAMPWROK

RESET*

SMC_ADAPTER_EN

PM_RSMRST_L

CPUIMVP_VR_ON

PM_SYSRST_L

SYSRST(PA2)

PM_PWRBTN_L

SMC_RESET_L

RES*

Apple Inc.

FW_PWR_EN

U5001

PP1V0_FW_FWPHY

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

3 OF 132

SHEET

124578

4.18.0

3 OF 99

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

Revision History

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

4 OF 132

SHEET

4 OF 99

124578

8 7 6 5 4 3

BOM Variants (continued on CSA 6)

BOM NUMBER

085-3726

085-4776

607-9546

685-0016

685-0017

639-3378

D

639-3379

639-3380

639-3381

639-3384

639-3385

639-3386

639-3387

639-2821

639-2825

639-2817

639-2815

639-2979

639-2980

639-2981

639-2982

639-3618

639-3619

639-3561

C

639-3620

639-3627

639-3562

639-3628

639-3629

PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2

PBUS PAIR,SANYO POSCAP,SHORT MYLAR,D2

PCBA,2.3G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY3V

PCBA,2.3G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY3W

PCBA,2.3G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY3Y

PCBA,2.3G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY40

PCBA,2.3G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY43

PCBA,2.3G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY44

PCBA,2.3G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY45

PCBA,2.3G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY4C

PCBA,2.6G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DRF1

PCBA,2.6G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DRF4

PCBA,2.6G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DRDN

PCBA,2.6G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DRDW

PCBA,2.6G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DT9H

PCBA,2.6G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DT9D

PCBA,2.6G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DT9F

PCBA,2.6G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DT9G

PCBA,2.7G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HN

PCBA,2.7G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,F0HR

PCBA,2.7G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DYW4

PCBA,2.7G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HV

PCBA,2.7G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HM

PCBA,2.7G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DYW5

PCBA,2.7G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,F0HY

PCBA,2.7G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HT

BOM NAME

D2,MLB,KEPLER,DEV

D2,MLB,KEPLER,FSB DEV

D2,MLB,KEPLER_2PHASE,COMMON

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3V,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY3W,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3Y,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY40,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY43,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY44,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY45,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY4C,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF1,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRF4,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDN,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDW,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9H,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9D,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9F,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9G,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HN,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HR,DEVEL_BOM,RAM_2G_HYNIX_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYW4,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HV,DEVEL_BOM,RAM_2G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HM,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:DYW5,DEVEL_BOM,RAM_4G_HYNIX_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HY,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HT,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BOM OPTIONS

D2_DEVEL:ENG

D2_DEVEL:FSB

D2_COMMON,POSCAP_MYLAR_PAIR

PBUS_CAP:KEMET

PBUS_CAP:SANYO

BOM Groups

BOM GROUP

D2_COMMON

D2_COMMON1

D2_COMMON2

D2_PVB

D2_PROGPARTS

D2_DEVEL:ENG

D2_DEVEL:FSB

IVB_PPT_XDP

ALTERNATE,COMMON,D2_COMMON1,D2_COMMON2,D2_PROGPARTS,D2_PVB

CPUMEM_S0,SMC_DEBUG_YES,DPMUX:HOCO,TBTRTR:PRQ,TBTBST:Y,TBTHV:P15V,HUB_2NONREM,USBHUB2512B,SPEAKERID,SMC_PACKAGE:PROD,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,P1V5S0:LDO

EDP:YES,MIKEY,PPCPUVCCIO:IVB,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,KBD_BL:SANDWICH,CAPS:INT,BTPWR:S4,XDP,XDP_CPU:BPM,GPU:2P,TPAD_5V:LDO_S5

SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG

ALTERNATE,IVB_PPT_XDP,S0PGOOD_ISL,DPMUX_DEBUG,DDRVREF_DAC,VREF:ENG_M3,SENSOR_NONPROD:Y,D_BKL:DEV

BOM OPTIONS

VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N

ALTERNATE,IVB_PPT_XDP

XDP_CONN,XDP_PCH

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Module Parts

B

PART NUMBER

337S4266

337S4267

337S4268

337S4269

337S4256

338S1113

333S0622

333S0623

333S0628

333S0625

333S0624

333S0629 CRITICAL

333S0630

333S0631

128S0264

128S0257

725-1614

A

725-1648

725-1568

725-1569 CRITICAL

725-1621 CRITICAL

806-2897

QTY

1

32

4

30

1

2

1

946-3819

825-7841

1

DESCRIPTION

IVB,S R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA

IVB,S R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA

IVB,S R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA

PANTHER POINT,C1,SLJ8C,PRQ,BD82HM77

IC,GPU,NV GK107-GTX-PS-A2

IC,TBT,CR-4C,B1,PRQ,CIO,228 12X12 FC-CSP

IC,SDRAM,DDR3-1600,256MX8,78FBGA,HYNIX,C-DIE,38NM

IC,SDRAM,DDR3-1600,256MX8,78FBGA,SAMSUNG

IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

IC,SDRAM,GDDR5,64MX32,A-DIE,HYNIX

IC,SDRAM,GDDR5,64MX32,D-DIE,SAMSUNG

CAP,TANT,POLY,68UF,20%,16V,50MOHM,D2E

CAP,TANT,POLY,68UF,20%,16V,50MOHM,D,LF

INSULATOR,SHORT,REAR,MLB,D2

INSULATOR,TALL,REAR,MLB,D2

INSULATOR,CPU,D2

INSULATOR,GPU,D2

INSULATOR,PCH,D2

CAN,COVER,2,J5

TEXT,LABEL,MLB,D2

D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

LBL,PART CONFIG,BOARDS,D2

REFERENCE DES

U1000

U1800

U8000

U3600

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270

U8400,U8450,U8500,U8550

C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821

REAR_INSULATOR

CPU_INSULATOR

GPU_INSULATOR

PCH_INSULATOR

CAN_COVER1,CAN_COVER2

TEXT_LABEL

EDGE_BOND

CONFIG_LABEL

CRITICAL

CRITICAL825-7697

CRITICAL

BOM OPTION

CPU_IVY:2_3GHZ

CPU_IVY:2_6GHZ

CPU_IVY:2_7GHZ

TBTRTR:PRQ

2G_HYNIX_1600

2G_SAMSUNG_1600

2G_ELPIDA_1600

4G_HYNIX_1600

4G_SAMSUNG_1600

4G_ELPIDA_1600

FB_2G_HYNIX_A_DIE

FB_2G_SAMSUNG

PBUS_CAP:SANYO

PBUS_CAP:KEMET

PBUS_CAP:SANYO

PBUS_CAP:KEMET

PD Parts

Bar Code Labels / EEEE #’s (continued on CSA 6)

PART NUMBER

QTY

1

825-7563 CRITICAL

825-7563

825-7563 CRITICAL

825-7563

1

825-7563

1

825-7563

1

DESCRIPTION

LABEL,MLB/LIO,MBA

REFERENCE DES

[EEEE:DY3V]

[EEEE:DY3W]

[EEEE:DY3Y]

[EEEE:DY40]

[EEEE:DY43]

[EEEE:DY44]

[EEEE:DY45]

[EEEE:DY4C]

[EEEE:DRF1]

[EEEE:DRF4]

[EEEE:DRDN]

[EEEE:DRDW]

[EEEE:DT9H]

[EEEE:DT9D]

[EEEE:DT9F]

[EEEE:DT9G]

[EEEE:F0HN]

[EEEE:F0HR]

[EEEE:DYW4]

[EEEE:F0HV]

[EEEE:F0HM]

[EEEE:DYW5]

[EEEE:F0HY]

[EEEE:F0HT]

CRITICAL

CRITICAL825-7563

CRITICAL

CRITICAL825-7563

CRITICAL

CRITICAL825-7563

CRITICAL

Programmables

341S3584 CRITICAL

337S2983

341S3597

335S0865

335S0852

341S3565

337S4313

1

IC,TRKPD/KYBD CNTRLR,DVB,D2

IC,TP PSOC,QFN,BLANK

IC,EEPROM,CACTUS RIDGE (8.1) FSB,D2

EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN

IC,GPU ROM,D2,BLANK

IC,EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2

IC,MCU,H8S/2113,9X9MM,TLP-145V

U5701

U3690

U8701

U9100

CRITICAL

DRAM VREF Configs

BOM GROUP

VREF:PROD

VREF:ENG_M3

VREF:ENG_LDO

VREFDQ:M1_M3,VREFCA:LDO_DAC

VREFDQ:M1_DAC,VREFCA:LDO_DAC

BOM OPTIONS

VREFDQ:M1_M3,VREFCA:LDO

DRAM SPD Straps

BOM GROUP

RAM_4G_HYNIX_1600_S

RAM_1G_SAMSUNG_1600

RAM_4G_SAMSUNG_1600_S

RAM_1G_HYNIX_1600

RAM_4G_ELPIDA_1600_S

RAM_2G_SAMSUNG_1600

RAM_2G_SAMSUNG_1333

RAM_2G_HYNIX_1600

RAM_4G_SAMSUNG_1600

RAM_4G_HYNIX_1600

RAM_2G_ELPIDA_1600_S

RAM_2G_ELPIDA_1600

RAM_4G_ELPIDA_1600

RAM_2G_SAMSUNG_1600_S

RAM_2G_HYNIX_1600_S

2G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

2G_HYNIX_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

4G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

4G_HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

2G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

BOM OPTIONS

RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

DEVELOPMENT/BASE BOM

PART NUMBER

085-3726

685-0016

QTY

1

D2 MLB KEPLER FSB DEVEL BOM

D2 MLB KEPLER 2PHASE BASE BOM

PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2

DESCRIPTION

D2 MLB KEPLER DEVEL BOM

REFERENCE DES

DEVEL

DEVEL_FSB

CRITICAL

CRITICAL085-4776

BASE CRITICAL607-9546 BASE_BOM

POSCAP_MYLAR

CRITICAL

SMC

341S3308

341S3309

1

IC,SMC,DEVELOPMENT-FSB,A3,D2

IC,SMC,PVB,A3,2.2F36,D2

U4900

CRITICAL

EFI ROM

341S3595

1

IC,EFI,ROM,FSB, D2

U6100

CRITICAL

BOM OPTION

EEEE:DY3V

EEEE:DY3W

EEEE:DY3Y

EEEE:DY40

EEEE:DY43

EEEE:DY44

EEEE:DY45

EEEE:DY4C

EEEE:DRF1

EEEE:DRF4

EEEE:DRDN

EEEE:DRDW

EEEE:DT9H

EEEE:DT9D

EEEE:DT9F

EEEE:DT9G

EEEE:F0HN

EEEE:F0HR

EEEE:DYW4

EEEE:F0HV

EEEE:F0HM

EEEE:DYW5

EEEE:F0HY

EEEE:F0HT

TPAD_PSOC:PROG

TPAD_PSOC:BLANK

TBTROM:PROG

TBTROM:BLANK

GPUROM:BLANK

DPMUXMCU:PROG

DPMUXMCU:BLANK

BOM OPTION

DEVEL_BOM

DEVEL_FSB_BOM

POSCAP_MYLAR_PAIR

SMC_PROG:FSB

SMC_PROG:PVB

BOOTROM_PROG:FSB

Alternate Parts

PART NUMBER

128S0257

353S3527

353S3526 353S3528

376S0855

376S0855 376S0613

376S1076

376S0977

376S1053

128S0311

138S0739 138S0706

197S0434 197S0343

197S0435 197S0343

197S0432

197S0453 197S0181

376S0975

371S0709

371S0713

377S0126 377S0066

377S0147

152S0461

376S1080 376S0820

107S0232

197S0466 197S0464

341S3564

ALTERNATE FOR PART NUMBER

BOM OPTION

128S0264

353S3528

376S0613

VREFDQ:M1_M3

376S0634

376S0796376S0903

376S0859

376S0604

128S0329

197S0431

197S0181197S0452

685-0016685-0017

376S1081

371S0652

371S0558

377S0066

152S1645

155S0583155S0667

107S0129

341S3565

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

SYNC_MASTER=D2_KEPLER

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

REF DES

ALL

6 3

12

COMMENTS:

Kemet alt to Sanyo

Pericom eDP MUX

TI eDP MUX

Diodes alt to Toshiba

Diodes alt to On Semi

Fairchild alt to Siliconix

Diodes alt to Toshiba

Diodes alt to Fairchild

NEC alt to Sanyo

Samsung alt to Murata

Epson Alt to TXC

NDK Alt to TXC

NDK Alt to Epson

Epson Alt to TXC

NDK Alt to TXC

Sanyo POSCAP/Mylar alt to Kemet

Toshiba alt to diodes

NXP alt to infineon

DDS alt to ST

New Semtech package

On Semi alt to Semtech

Cyntec alt to Vishay

Diodes alt to On Semi

Panasonic alt to TDK

Cyntec alt to TFT

Epson alt to NDK

Avnet eDP MUX alt to Renesas

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

5 OF 132

SHEET

5 OF 99

124578

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

C

B

A

SIZE

D

8 7 6 5 4 3

12

BOM Variants (continued from CSA 5)

BOM NUMBER

639-3382

639-3383

639-3445

639-3446

639-2818

D

639-2820

639-2823

639-2819

639-3632

639-3633

639-3630

639-3631

PCBA,2.3G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DY41

PCBA,2.3G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DY42

PCBA,2.3G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DYJ5

PCBA,2.3G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DYJ6

PCBA,2.6G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRF0

PCBA,2.6G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDP

PCBA,2.6G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRDT

PCBA,2.6G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDQ

PCBA,2.7G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0JD

PCBA,2.7G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0J3

PCBA,2.7G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0J4

PCBA,2.7G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0JC

BOM NAME

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY41,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY42,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYJ5,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DYJ6,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF0,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDP,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDT,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDQ,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0JD,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0J3,DEVEL_BOM,RAM_2G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0J4,DEVEL_BOM,RAM_4G_ELPIDA_1600

BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0JC,DEVEL_BOM,RAM_4G_ELPIDA_1600

BOM OPTIONS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

C

Bar Code Labels / EEEE #’s (continued from CSA 5)

PART NUMBER

825-7563

825-7563 CRITICAL

825-7563

QTY

1

DESCRIPTION

LABEL,MLB/LIO,MBA

REFERENCE DES

[EEEE:DY41]

[EEEE:DY42]

[EEEE:DYJ5]

[EEEE:DYJ6]

[EEEE:DRF0]

[EEEE:DRDP]

[EEEE:DRDT]

[EEEE:DRDQ]

[EEEE:F0JD]

[EEEE:F0J3]

[EEEE:F0J4]

[EEEE:F0JC]

CRITICAL

CRITICAL825-7563

CRITICAL

CRITICAL825-7563

CRITICAL

BOM OPTION

EEEE:DY41

EEEE:DY42

EEEE:DYJ5

EEEE:DYJ6

EEEE:DRF0

EEEE:DRDP

EEEE:DRDT

EEEE:DRDQ

EEEE:F0JD

EEEE:F0J3

EEEE:F0J4

EEEE:F0JC

Elipda DQ’d Keeping for PRQ

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

BOM Variants

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

6 OF 132

SHEET

6 OF 99

124578

8 7 6 5 4 3

ICT Test Points

CPU NO_TESTs

Thunderbolt NO_TESTs

PCH ALIASES

TRUE

TP_CLINK_CLK TP_CLINK_DATA TP_CLINK_RESET_L

NO_TEST

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC NO_TESTs

NO_TEST

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

GPU NO_TESTs

NO_TEST

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

NO_TEST

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_TP_CPU_RSVD<65..62> NC_TP_CPU_RSVD<58..45> NC_TP_CPU_RSVD<43..32> NC_TP_CPU_RSVD<27..26> NC_TP_CPU_RSVD<24..15> NC_TP_CPU_RSVD<2..1> NC_TP_CPU_RSVD_NCTF<8..5>

NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_DATA NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_DATA NC_PCH_LVDS_VBG

NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3 NC_PCI_AD<31..0> NC_PCI_C_BE_L<3..0> NC_PCI_GNT3_L NC_PCI_GNT2_L NC_PCI_GNT1_L NC_PCI_GNT0_L NC_PCI_PAR NC_PCI_RESET_L NC_PCI_PME_L NC_PCI_CLK33M_OUT3 NC_PCH_NV_RCOMP NC_NV_DQ<15..0> NC_NV_DQS<1..0> NC_NV_CE_L<3..0> NC_NV_ALE NC_NV_CLE NC_NV_RB_L NC_NV_WR_RE_L<1..0> NC_NV_WE_CK_L<1..0> NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_B_D2RN NC_SATA_B_D2RP NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP NC_SATA_F_D2RN NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP NC_SMC_P41

NC_DVPDATA<21..4> NC_DVPCNTL_M<1..0> NC_DVPDATA<2..0> NC_DVPDATA<2..0>

NC_TBT_XTAL25OUT NC_TBT_PCIE_RESET0_L NC_TBT_PCIE_RESET1_L NC_TBT_PCIE_RESET2_L NC_TBT_PCIE_RESET3_L NC_DP_TBTSRC_ML_CP<3..0> NC_DP_TBTSRC_ML_CN<3..0> NC_DP_TBTSRC_AUXCH_CP NC_DP_TBTSRC_AUXCH_CN

TP_LPC_DREQ0_L

NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L

NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP

NO_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TP_HDMI_CEC

TP_DP_IG_C_HPD TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_MLP<3..0>

18

TP_DP_IG_C_MLN<3..0>

18

TP_DP_IG_C_AUXP TP_DP_IG_C_AUXN

TP_DP_IG_D_HPD

18

TP_DP_IG_D_CTRL_CLK

18

TP_DP_IG_D_CTRL_DATA

18

TP_DP_IG_D_MLP<3..0>

18

TP_DP_IG_D_MLN<3..0>

18

TP_DP_IG_D_AUXP

18

TP_DP_IG_D_AUXN

18

TP_SDVO_TVCLKINN

18

TP_SDVO_TVCLKINP

18

TP_SDVO_STALLN

18

TP_SDVO_STALLP

18

TP_SDVO_INTN

18

TP_SDVO_INTP

TP_GPU_BUFRST_L TP_GPU_GSTATE<0> TP_GPU_GSTATE<1> TP_GPU_MIOA_D<9..0> TP_GPU_MIOA_DE

TP_LVDS_EG_BKL_PWM LVDS_IG_B_CLK_N

18

LVDS_IG_B_CLK_P

18

LVDS_IG_BKL_PWM

18

7

17

SMC_BS_ALRT_L

PCH_VSS_NCTF<1>

TRUE

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<7>

TRUE

PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<12>

TRUE

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

NC NO_TESTs

NC_SMC_FAN_3_TACH NC_SMC_FAN_3_CTL NC_SMC_FAN_2_TACH NC_SMC_FAN_2_CTL NC_FW2_TPBP NC_FW2_TPBN NC_FW2_TPBIAS NC_FW2_TPAP NC_FW2_TPAN NC_FW0_TPBP NC_FW0_TPBN NC_FW0_TPAP NC_ESTARLDO_EN NC_ALS_GAIN NC_USB_HUB_PRTPWR2 NC_USB_HUB_PRTPWR3 NC_USB_HUB_PRTPWR4 NC_USB_HUB_OCS2 NC_USB_HUB_OCS3 NC_USB_HUB_OCS4 NC_SMC_XOSC1 NC_SMC_ODD_DETECT NC_SMC_SYS_LED NC_SMC_HIB_L NC_SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SCL NC_SMC_T25_EN_L NC_SMC_T25_ISENSE NC_ISNS_P1V5R1V35_CPUDDRP NC_ISNS_P1V5R1V35_CPUDDRN NC_ISNS_LCDBKLTP NC_ISNS_LCDBKLTN NC_ISNS_LCD_PANELP NC_ISNS_LCD_PANELN NC_ISNS_AIRPORTP NC_ISNS_AIRPORTN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_HPD NC_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_DATA NC_DP_IG_C_MLP<3..0> NC_DP_IG_C_MLN<3..0> NC_DP_IG_C_AUXP NC_DP_IG_C_AUXN

NC_DP_IG_D_HPD NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA NC_DP_IG_D_MLP<3..0> NC_DP_IG_D_MLN<3..0> NC_DP_IG_D_AUXP NC_DP_IG_D_AUXN

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE

Functional / ICT Test

Apple Inc.

R

NO_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

I1759

I1760 I1761

I1763

I1762

I1764 I1766

I1765

I1768 I1767

I1769

I1770 I1771

I1773 I1772

I1774

I1775 I1776

I1777

I1779 I1778

I1780

I1781 I1782

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

FUNC_TEST

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

J6950 - battery

PPVBAT_G3H_CONN SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA SYS_DETECT_L GND

J9000 - eDP

DP_INT_AUX_N DP_INT_AUX_P DP_INT_ML_N<0> DP_INT_ML_N<1> DP_INT_ML_N<2> DP_INT_ML_N<3> DP_INT_ML_P<0> DP_INT_ML_P<1> DP_INT_ML_P<2> DP_INT_ML_P<3> LCD_FSS LCD_HPD_CONN LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 PP5VR3V3_SW_LCD PPVOUT_S0_LCDBKLT GND

NO_TEST=TRUE

TBT_A_D2R_C_P<1..0>

TRUE

TBT_A_D2R_C_N<1..0>

TRUE

TBT_A_D2R_P<1..0>

TRUE

TBT_A_D2R_N<1..0>

TRUE

TBT_A_R2D_C_P<1..0>

TRUE

TBT_A_R2D_C_N<1..0>

TRUE

TBT_A_R2D_P<1..0>

TRUE

TBT_A_R2D_N<1..0>

TRUE

TBT_B_D2R_C_P<1..0>

TRUE

TBT_B_D2R_C_N<1..0>

TRUE

TBT_B_D2R_P<1..0>

TRUE

TBT_B_D2R_N<1..0>

TRUE

TBT_B_R2D_C_P<1..0>

TRUE

TBT_B_R2D_C_N<1..0>

TRUE

TBT_B_R2D_P<1..0>

TRUE

TBT_B_R2D_N<1..0>

TRUE

DP_TBTSNK0_ML_C_P<3..0>

TRUE

DP_TBTSNK0_ML_C_N<3..0>

TRUE

DP_TBTSNK0_ML_P<3..0>

TRUE

DP_TBTSNK0_ML_N<3..0>

TRUE

DP_TBTSNK0_AUXCH_C_P

TRUE

DP_TBTSNK0_AUXCH_C_N

TRUE

DP_TBTSNK0_AUXCH_P

TRUE

DP_TBTSNK0_AUXCH_N

TRUE

DP_TBTSNK1_ML_C_P<3..0>

TRUE

DP_TBTSNK1_ML_C_N<3..0>

TRUE

DP_TBTSNK1_ML_P<3..0>

TRUE

DP_TBTSNK1_ML_N<3..0>

TRUE

DP_TBTSNK1_AUXCH_C_P

TRUE

DP_TBTSNK1_AUXCH_C_N

TRUE

DP_TBTSNK1_AUXCH_P

TRUE

DP_TBTSNK1_AUXCH_N

TRUE

NC_PCIE_5_D2RN NC_PCIE_5_D2RP NC_PCIE_5_R2D_CN NC_PCIE_5_R2D_CP

NC_PCIE_6_D2RN NC_PCIE_6_D2RP NC_PCIE_6_R2D_CN NC_PCIE_6_R2D_CP

NC_PCIE_7_D2RN NC_PCIE_7_D2RP NC_PCIE_7_R2D_CN NC_PCIE_7_R2D_CP

NC_PCIE_8_D2RN NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN NC_PCIE_8_R2D_CP

NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN NC_PCIE_PE5_R2D_CP

NC_PCIE_PE6_D2RN NC_PCIE_PE6_D2RP NC_PCIE_PE6_R2D_CN NC_PCIE_PE6_R2D_CP

NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN NC_PCIE_PE7_R2D_CP

NC_PCIE_PE8_D2RN NC_PCIE_PE8_D2RP NC_PCIE_PE8_R2D_CN NC_PCIE_PE8_R2D_CP

8X

60 61

41 44

60

8X GND

81 95

81 82

81

81 86

81

3X

81 86 99

16X GND

TP_CPU_RSVD<65..62> TP_CPU_RSVD<58..45> TP_CPU_RSVD<43..32> TP_CPU_RSVD<27..26> TP_CPU_RSVD<24..15> TP_CPU_RSVD<2..1> TP_CPU_RSVD_NCTF<8..5>

TP_CRT_IG_BLUE

18

TP_CRT_IG_GREEN

18

TP_CRT_IG_RED

18

TP_CRT_IG_DDC_CLK

18

TP_CRT_IG_DDC_DATA

18

TP_CRT_IG_HSYNC

18

TP_CRT_IG_VSYNC

18

TP_LVDS_IG_CTRL_CLK

18

TP_LVDS_IG_CTRL_DATA

18

TP_PCH_LVDS_VBG

18

TP_HDA_SDIN1

17

TP_HDA_SDIN2

17

TP_HDA_SDIN3

17

TP_PCI_AD<31..0> TP_PCI_C_BE_L<3..0> TP_PCI_GNT3_L TP_PCI_GNT2_L TP_PCI_GNT1_L TP_PCI_GNT0_L

84 93

TP_PCI_PAR

84 93

TP_PCI_RESET_L

7

35 84 93

TP_PCI_PME_L

19

7

35 84 93

TP_PCI_CLK33M_OUT3

19

7

35 84 93

TP_PCH_NV_RCOMP

35 84 93

TP_NV_DQ<15..0>

84 93

TP_NV_DQS<1..0>

84 93

TP_NV_CE_L<3..0>

85 93

TP_NV_ALE

85 93

TP_NV_CLE

35 85 93

TP_NV_RB_L

35 85 93

TP_NV_WR_RE_L<1..0>

7

35 85 93

TP_NV_WE_CK_L<1..0>

35 85 93

TP_PCIE_CLK100M_PE4N

17

85 93

TP_PCIE_CLK100M_PE4P

17

85 93

TP_PCIE_CLK100M_PE5N

35 77 95

TP_PCIE_CLK100M_PE5P

35 77 95

TP_PCIE_CLK100M_PE6N

35 95

TP_PCIE_CLK100M_PE6P

35 95

TP_PCIE_CLK100M_PE7N

35 83 95

TP_PCIE_CLK100M_PE7P

35 83 95

TP_PSOC_P1_3

49

35 95

TP_SATA_B_D2RN

35 95

TP_SATA_B_D2RP

35 77 95

TP_SATA_B_R2D_CN

35 77 95

TP_SATA_B_R2D_CP

35 95

TP_SATA_D_D2RN

17

35 95

TP_SATA_D_D2RP

17

35 83 95

TP_SATA_D_R2D_CN

17

35 83 95

TP_SATA_D_R2D_CP

17

35 95

TP_SATA_E_D2RN

17

35 95

TP_SATA_E_D2RP

17

TP_SATA_E_R2D_CN

17

TP_SATA_E_R2D_CP

17

TP_SATA_F_D2RN

17

TP_SATA_F_D2RP

17

TP_SATA_F_R2D_CN

17

TP_SATA_F_R2D_CP

17

TP_SMC_P41

TP_DVPDATA<21..4> TP_DVPCNTL_M<1..0> TP_DVPCNTL<2..0>

7

TP_DVPCNTL<2..0>

7

TP_TBT_XTAL25OUT

35

TP_TBT_PCIE_RESET0_L

35

TP_TBT_PCIE_RESET1_L

35

TP_TBT_PCIE_RESET2_L

35

TP_TBT_PCIE_RESET3_L

35

TP_DP_TBTSRC_ML_CP<3..0>

35

TP_DP_TBTSRC_ML_CN<3..0>

35

TP_DP_TBTSRC_AUXCH_CP

35

TP_DP_TBTSRC_AUXCH_CN

35

NC_LPC_DREQ0_L

MAKE_BASE=TRUE

17

TP_PCIE_CLK100M_PEBN

17

TP_PCIE_CLK100M_PEBP

17

J6701 - audio flex

AUD_HP_PORT_L

TRUE

AUD_HP_PORT_R

TRUE

AUD_SPDIF_OUT_JACK

TRUE

AUD_TIPDET_INV

TRUE

AUD_TYPEDET

TRUE

CH_HS_GND

TRUE

CH_HS_MIC

TRUE

PP3V3_S0

TRUE

US_HS_GND

TRUE

US_HS_MIC

TRUE

GND

TRUE

J6801 - 3-mic

CON_DMIC_CLK

TRUE

CON_DMIC_PWR

TRUE

CON_DMIC_SDA1

TRUE

CON_DMIC_SDA2

TRUE

GND

TRUE

J6802 - L speaker

SPKRCONN_L_ID

TRUE

SPKRCONN_L_OUT_N

TRUE

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_SL_OUT_N

TRUE

SPKRCONN_SL_OUT_P

TRUE

GND

TRUE

J6803 - R speaker

SPKRCONN_R_ID

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_SR_OUT_N

TRUE

SPKRCONN_SR_OUT_P

TRUE

GND

TRUE

J6900 - DC PWR

ADAPTER_SENSE

TRUE

PP18V5_DCIN_FUSE

TRUE

TDM_ONEWIRE_MPM

TRUE

GND

TRUE

POWER RAILS

PM_SLP_S3_L

TRUE

PP0V75_S0_DDRVTT

TRUE

PP1V05_S0

TRUE

PP1V8_S0

TRUE

PP3V3_S0

TRUE

PP3V3_S0GPU

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V42_G3H

TRUE

PP5V_S0

TRUE

PP5V_S3

TRUE

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PPDCIN_G3H

TRUE

PPVCORE_GPU

TRUE

PPVCORE_S0_CPU

TRUE

PPVTTDDR_S3

TRUE

TP_PCIE_5_D2RN

17

TP_PCIE_5_D2RP

17

TP_PCIE_5_R2D_CN

17

TP_PCIE_5_R2D_CP

17

TP_PCIE_6_D2RN

17

TP_PCIE_6_D2RP

17

TP_PCIE_6_R2D_CN

17

TP_PCIE_6_R2D_CP

17

TP_PCIE_7_D2RN

17

TP_PCIE_7_D2RP

17

TP_PCIE_7_R2D_CN

17

TP_PCIE_7_R2D_CP

17

TP_PCIE_8_D2RN

17

TP_PCIE_8_D2RP

17

TP_PCIE_8_R2D_CN

17

TP_PCIE_8_R2D_CP

17

TP_PCIE_PE5_D2RN TP_PCIE_PE5_D2RP TP_PCIE_PE5_R2D_CN TP_PCIE_PE5_R2D_CP

TP_PCIE_PE6_D2RN TP_PCIE_PE6_D2RP TP_PCIE_PE6_R2D_CN TP_PCIE_PE6_R2D_CP

TP_PCIE_PE7_D2RN TP_PCIE_PE7_D2RP TP_PCIE_PE7_R2D_CN TP_PCIE_PE7_R2D_CP

TP_PCIE_PE8_D2RN TP_PCIE_PE8_D2RP TP_PCIE_PE8_R2D_CN TP_PCIE_PE8_R2D_CP

53 54 58

53 58

59

58 59

4X

58

7 8

4X

58

2X GND

59

57 59 96

59

57 59 96

60

2X

60

2X GND

7

18 27 38 41 70

8

96

7 8

8

7 8

8

96

41 42

7 8

8

7 8

8

NC NO_TESTs

58

96

58

60

I1756

I1758 I1757

I1731

I1733 I1735

I1734

I1736 I1738

I1737 I1740

I1739

I1741

I1743

I1742

I1745 I1744

I1746 I1748

I1747

I1750 I1749

I1751

I1753 I1752

I1755

I1754

FUNC_TEST

Functional Test Points

FUNC_TEST

I1596 I1597

I1599 I1600

I1601

I1602 I1603

I1604

D

C

B

A

I1605 I1606

I1608

I1609 I1607

I1611

I1610

I1613

I1614 I1612

I1615

I1616

I1618

I1619 I1617

I1621

I1620 I1623

I1624

I1622 I1625

I1626 I1628

I1629

I1627 I1631

I1630

I1633 I1634

I1632

I1635

I1636

I1638

I1639 I1637

I1641

I1640 I1643

I1644

I1642 I1645

I1646 I1648

I1649

I1647 I1651

I1650

I1785

I1653 I1654

I1680

I1683

I1793

I1684

I1682 I1795

I1728

I1730

I1729

J3501 - airport

AP_CLKREQ_Q_L

TRUE

AP_RESET_CONN_L

TRUE

PCIE_AP_D2R_PI_N

TRUE

PCIE_AP_D2R_PI_P

TRUE

PCIE_AP_R2D_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

PCIE_WAKE_L

TRUE

PP3V3_S3RS4_BT_F

TRUE

PP3V3_WLAN

TRUE

USB_BT_CONN_N

TRUE

USB_BT_CONN_P

TRUE

WIFI_EVENT_L

TRUE

GND

TRUE

J3502 - ALS camera

PP5V_S3_ALSCAMERA_F

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

USB_CAMERA_CONN_N

TRUE

USB_CAMERA_CONN_P

TRUE

GND

TRUE

J4400 - rio coax

HDMI_EG_CLK_C_N

TRUE

HDMI_EG_CLK_C_P

TRUE

HDMI_EG_DATA_C_N<0>

TRUE

HDMI_EG_DATA_C_N<1>

TRUE

HDMI_EG_DATA_C_N<2>

TRUE

HDMI_EG_DATA_C_P<0>

TRUE

HDMI_EG_DATA_C_P<1>

TRUE

HDMI_EG_DATA_C_P<2>

TRUE

PCIE_CLK100M_ENET_N

TRUE

PCIE_CLK100M_ENET_P

TRUE

PCIE_ENET_D2R_N

TRUE

PCIE_ENET_D2R_P

TRUE

PCIE_ENET_R2D_C_N

TRUE

PCIE_ENET_R2D_C_P

TRUE

USB3_EXTB_RX_N

TRUE

USB3_EXTB_RX_P

TRUE

USB3_EXTB_TX_C_N

TRUE

USB3_EXTB_TX_C_P

TRUE

USB_EXTB_N

TRUE

USB_EXTB_P

TRUE

GND

TRUE

J4410 - rio flex

ENET_CLKREQ_L

TRUE

ENET_RESET_L

TRUE

HDMI_EG_DDC_CLK

TRUE

HDMI_EG_DDC_DATA

TRUE

HDMI_HPD_L

TRUE

I2C_DPMUX_A_SCL

TRUE

I2C_DPMUX_A_SDA

TRUE

PM_SLP_S3_L

TRUE

PM_SLP_S4_L

TRUE

PP1V5_S0_RIO

TRUE

PP3V3_S3

TRUE

PP3V3_S4

TRUE

PP5V_S4

TRUE

SDCONN_STATE_CHANGE_RIO

TRUE

SD_PWR_EN

TRUE

USB_EXTB_OC_L

TRUE

GND

TRUE

J5050 - hall effect

PP3V42_G3H

TRUE

SMC_LID_R

TRUE

GND

TRUE

J5650 - left fan

FAN_LT_PWM

TRUE

FAN_LT_TACH

TRUE

PP5V_S0

TRUE

GND

TRUE

J5660 - right fan

FAN_RT_PWM

TRUE

FAN_RT_TACH

TRUE

PP5V_S0

TRUE

GND

TRUE

J5815 - kbd backlight

KBDLED_ANODE1

TRUE

KBDLED_ANODE2

TRUE

SMC_KBDLED_PRESENT_L

TRUE

GND

TRUE

34

34 92

34 96

18 34

34

34 42

34 91

34 41 42

4X GND

34

7

41 44 94

7

41 44 94

34 91

38 77 95

17 38 92

19 38 91

38 97

26 38 91

19X GND

17 38

25

38 77

38 42 82

44

7

18 27 38 41 70

18 27 34 38 40 41 70

8

3X P3V3_S3

7 8

5X P5V_S4

8

25 38

9

38

24 38

10X GND

7 8

42

48

3X P5V_S0

7 8

5X GND

48

3X P5V_S0 5X GND

2X

50

2X

50

4X GND

I1685

I1686 I1687

I1689

I1688 I1691

I1690 I1692

I1694

I1693 I1695

I1799

I1800 I1697

I1797

I1798 I1817

I1818

I1652 I1655

I1656 I1658

I1659

I1657 I1661

I1660

I1663 I1664

I1662

I1665 I1666

I1668 I1669

I1667

I1671 I1670

I1673

I1674 I1672

I1675

I1676 I1678

I1679 I1677

I1681

I1802

I1803 I1696

I1698

I1699 I1700

I1702

I1701 I1703

I1704 I1705

I1707

I1706 I1708

I1709

I1710 I1712

I1711

I1713 I1715

I1714 I1717

I1716

I1718 I1720

I1719

I1722 I1721

I1723

FUNC_TEST

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

TRUE

TRUE TRUE

J5100 - lpc + spi

LPCPLUS_GPIO LPCPLUS_RESET_L LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_CLK33M_LPCPLUS LPC_FRAME_L LPC_PWRDWN_L LPC_SERIRQ PM_CLKRUN_L PP5V_S0 SMC_RESET_L SMC_ROMBOOT SMC_RX_L SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_TX_L SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L SPI_ALT_MISO SPI_ALT_MOSI TP_SMC_MD1 TP_SMC_TRST_L GND

J5700 - ipd flex

Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_F_CS_L PICKB_L PP3V3_S4 PP5V_S5 PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SDA

GND

J5713 - keyboard

PP3V3_S4 PP3V42_G3H WS_CONTROL_KBD WS_KBD1 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD2 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD_ONOFF_L WS_LEFT_OPTION_KBD WS_LEFT_SHIFT_KBD GND

20 43

25 43

17 41 43 82 92

25 43 92

17 41 43 82 92

18 25 41 43

17 41 43

18 41 43

7 8

41 42 43 61

42 43

41 42 43

20 43 52

43

2X GND

49

7 8

49

7

41 44 94

7

41 44 94

2X GND

7 8

49

2X GND

PLACEABLE BEAD-PROBES FOR TBT

7

35 85 93

7

35 85 93

7

35 84 93

7

35 84 93

TBT_B_R2D_C_P<1> TBT_B_R2D_C_P<0> TBT_A_R2D_C_P<1> TBT_A_D2R_P<1> TBT_A_D2R_N<1>

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

1

TP

BEAD-PROBE

SM

SIGNAL_MODEL=EMPTY

BP0733

SIGNAL_MODEL=EMPTY

BP0734

SIGNAL_MODEL=EMPTY

BP0735

SIGNAL_MODEL=EMPTY

BP0731

SIGNAL_MODEL=EMPTY

BP0732

6 3

12

26

41

42

41

42

8

69 98

99

81 98

99

NC_HDMI_CEC

NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP

NC_SDVO_STALLN NC_SDVO_STALLP

NC_SDVO_INTN NC_SDVO_INTP

NC_GPU_BUFRST_L NC_GPU_GSTATE<0> NC_GPU_GSTATE<1> NC_GPU_MIOA_D<9..0> NC_GPU_MIOA_DE

NC_LVDS_EG_BKL_PWM NC_LVDS_IG_B_CLKN NC_LVDS_IG_B_CLKP NC_LVDS_IG_BKL_PWM

NC_SMC_BS_ALRT_L

PCH_VSS_NCTF<15> PCH_VSS_NCTF<17> PCH_VSS_NCTF<19> PCH_VSS_NCTF<19> PCH_VSS_NCTF<21> PCH_VSS_NCTF<25> PCH_VSS_NCTF<27> PCH_VSS_NCTF<29>

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

7 OF 132

SHEET

7 OF 99

124578

D

C

B

7

A

SIZE

D

C

B

A

=PPBUS_G3H

60 61

G3H Rails

=PPVIN_S5_HS_COMPUTING_ISNS

46

=PPVIN_S5_HS_GPU_ISNS

46

=PPVIN_S5_HS_OTHER_ISNS

=PP18V5_DCIN_CONN

60

=PP18V5_DCIN_ISOL

60

=PP3V42_G3H_REG

60

=PP3V42_G3H_AUDIO

58

=PP3V42_G3H_TDM

60

=PP3V42_S3_HALL

42

For PCH RTC Power

=PPVRTC_G3_OUT

25

5V Rails

=PP5V_S5_LDO

63

=PP5V_SUS_FET

69

=PP5V_S4_REG

63

=PP5V_S3_FET

69

=PP5V_S0_FET

69

=PP5V_S0_P1V5_LDO

68

=PP3V3_S4_FET

69

=PP3V3_S4_TBT_R

36

=PP3V3_S4_RIO

38

=PP3V3_SUS_FET

69

=PP3V3_SUS_ROM

52

=PP3V3_SUS_PCH_VCC_SPI

21 23

8 7 6 5 4 3

3.3V Rails

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PPBUS_S0_LCDBKLT =PPVIN_S5_HS_OTHER_ISNS_R

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PPVIN_S5_HS_GPU_ISNS_R =PPVIN_SW_TBTBST =PPBUS_S0_VSENSE =PPBUS_G3H_T25_R

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_S0_CPUIMVP =PPVIN_S3_DDRREG =PPVIN_S0_CPUVCCIOS0 =PPVIN_S0_CPUAXG =PPVIN_S0_VCCSAS0 =PPVIN_S0_PCHVCCIOS0

PPVIN_S5_HS_GPU_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_S0_GFXIMVP

=PPVIN_S0GPU_P1V5P1V0

PPVIN_S5_HS_OTHER_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

=PPVIN_S5_P5VP3V3 PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

=PPDCIN_S5_CHGR PPDCIN_G3H_ISOL

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

=PPDCIN_S5_CHGR_ISOL =PPDCIN_S5_VSENSE

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3_S5_LPCPLUS =PP3V3_S5_SMC =PP3V42_G3H_CHGR =PP3V42_G3H_ONEWIREPROT =PP3V42_G3H_PWRCTL =PP3V42_G3H_SMBUS_SMC_5 =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD =PPVIN_S5_SMCVREF =PPVBAT_G3_SYSCLK

PPVRTC_G3H

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

=PPVRTC_G3_PCH

PP5V_S5

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.1 MM

=PP5V_S5_P1V5S3RS0FET =PP5V_S5_P5VSUSFET =PP5V_S5_TPAD

PP5V_SUS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP5V_SUS_PCH

PP5V_S4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

=PP5V_S4_RIO =PP5V_S4_P5VS0FET =PP5V_S4_P5VS3FET =PP5V_S0_LCD

=PP5V_S3_LTUSB =PP5V_S4_ISNS =PP5V_S4_TPAD =PP5V_S4_AUDIO

PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

=PP5V_S3_ISNS =PP5V_S3_ALSCAMERA =PP5V_S3_DDRREG =PP5V_S3_DEBUG_ADC_AVDD =PP5V_S3_DEBUG_ADC_DVDD

=PP5V_S3_DEBUG_ISNS =PP5V_S3_MEMRESET PP5V_S0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

=PP5V_S0GPU_P1V0P1V35_GPU =PP5V_S0_AUDIO_XW =PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN_LT

=PP5V_S0_FAN_RT

=PP5V_S0_GFXIMVP

=PP5V_S0_KBDLED

=PP5V_S0_LPCPLUS =PP5V_S0_PCH =PP5V_S0_PCHVCCIOS0

=PP5V_S0_RMC =PP5V_S0_VCCSAS0 =PP5V_S0_VMON

PP3V3_S4

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1 MM

=PP3V3_S4_TPAD

=PP3V3_S4_SMC =PP3V3_S4_BT PP3V3_SUS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_SUS_PCH_VCCSUS =PP3V3_SUS_PCH_VCCSUS_GPIO =PP3V3_SUS_PCH_GPIO =PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_SUS_CNTRL =PP3V3_SUS_SMC

MAKE_BASE=TRUE VOLTAGE=3.3V

VOLTAGE=12.8V MAKE_BASE=TRUE

VOLTAGE=18.5V MAKE_BASE=TRUE

VOLTAGE=3.42V MAKE_BASE=TRUE

VOLTAGE=5V MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

VOLTAGE=12.8V MAKE_BASE=TRUE

7

61

45

7

86

46

9

37

45

65 66

64

67

66

62

87

80

74

63

7

43

41 42 78

61 70

60

70

44

40

49

42

25

17 18 21

7

69

49

23

38

69

81

40

49

53 59

99

34

64

98

27

7

74

9

86

65 66

67

48

80

50

43

23 25

87

98

62

70

7

25 42

34

68

21 23

17 18 19 20

21 23

70

42

49

=PP3V3_S5_REG

63

=PP3V3_S3_FET

69

=PP3V3_S0_FET

69

TBT RAILS

=PP3V3_TBTLC_FET

37

=PP1V05_TBTLC_FET

37

=PP1V05_TBTCIO_FET

37

=PP15V_TBT_REG

9

37

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3_GPU_P3V3GPUFET =PP3V3_GPU_MISC_P3V3GPUMISCFET =PP3V3_S0_P3V3S0FET =PP3V3_S3_P3V3S3FET

=PP3V3_S4_DPAPWRSW

=PP3V3_S4_DPBPWRSW =PP3V3_S4_P3V3S4FET =PP3V3_S5_CPU_VCCDDR =PP3V3_S5_P1V2P1V8 =PP3V3_S5_P1V5S0 =PP3V3_S5_P3V3SUSFET =PP3V3_S5_PCH

=PP3V3_S5_PCHPWRGD =PP3V3_S5_PCH_GPIO =PP3V3_S5_PCH_VCCDSW =PP3V3_S5_PWRCTL

=PP3V3_S5_SMCBATLOW =PP3V3_S5_SYSCLK

=PP3V3_S5_VMON =PP3V3_S5_XDP =PP3V3_S4_TBTAPWRSW =PP3V3_S4_TBTBPWRSW

PP3V3_S3

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

=PP3V3_S3_BT =PP3V3_S3_DPMUX_UC =PP3V3_S3_ISNS =PP3V3_S3_MEMRESET =PP3V3_S3_PCH_GPIO =PP3V3_S3_RIO =PP3V3_S3_SMBUS_SMC_2_S3 =PP3V3_S3_SMBUS_SMC_3 =PP3V3_S3_TPAD =PP3V3_S3_USBMUX =PP3V3_S3_USB_HUB =PP3V3_S3_USB_RESET =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_GYRO =PP3V3_S3_SMS =PP3V3_S3_SDBUF

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 mm

=PP3V3_S0_AUDIO =PP3V3_S0_AUDIO_DIG =PP3V3_S0_BKL_VDDIO =PP3V3_S0_CPUTHMSNS =PP3V3_S0_CPU_VCCIO_SEL =PP3V3_S0_DPMUX =PP3V3_S0_DPMUXI2C =PP3V3_S0_DPMUX_UC =PP3V3_S0_FAN_LT =PP3V3_S0_FAN_RT =PP3V3_S0_GPUTHMSNS =PP3V3_S0_HS_ISNS

=PP3V3_S0_IMVPISNS =PP3V3_S0_ISNS =PP3V3_S0_LCD

=PP3V3_S0_P1V8GPUFET =PP3V3_S0_P3V3TBTFET =PP3V3_S0_PCH =PP3V3_S0_PCH_GPIO =PP3V3_S0_PCH_VCC3_3_CLK =PP3V3_S0_PCH_VCC3_3_GPIO =PP3V3_S0_PCH_VCC3_3_HVCMOS =PP3V3_S0_PCH_VCC3_3_PCI =PP3V3_S0_PCH_VCC3_3_SATA =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PWRCTL =PP3V3_S0_RSTBUF

=PP3V3_S0_SATAMUX =PP3V3_S0_SB_PM =PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_1_S0

=PP3V3_S0_SSD

=PP3V3_S0_SYSCLK

=PP3V3_S0_TBTI2C =PP3V3_S0_TBTPWRCTL =PP3V3_S0_TPAD =PP3V3_S0_VMON =PP3V3_S0_X29THMSNS =PP3V3_S0_XDP =PP3V3_S0_DDR3THMSNS =PP3V3_S0_SPKRTHMSNS

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM

=PP3V3_TBT_PCH_GPIO =PPVDDIO_TBT_CLK =PP3V3_TBTLC_RTR

PP1V05_TBTLC

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP15V_TBT

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

=PP1V05_TBTLC_RTR

=PP1V05_TBTCIO_RTR

=PPHV_SW_TBTAPWRSW =PPHV_SW_TBTBPWRSW

VOLTAGE=3.3V MAKE_BASE=TRUE

VOLTAGE=1.05V MAKE_BASE=TRUE

VOLTAGE=15V MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.15 MM MAKE_BASE=TRUE

70

24

84

85

84

85

7

96

69

27

68

69

18

70

20

21 23

70

42

25

7

34

82

99

27

19 25

38

44

26

33

34

51

25

7

96

59

53 58

86

47

13

82 83

44

35 78 82

48

47

46

45 98 99

81

37

17 23

17 18 19 20 25 37

23

21 23

23

70 88

25

39

25 70

44

39

25

37

50

70

47

24

20

25

35 36 37

37

36

=PP1V8_S0_REG

68

4A max supply

=PP1V8_S0_CPU_VCCPLL_R

13 15

=PPDDR_S3_REG

64

=PPVIN_S3_MEM_ISNS

45

=PP1V5_S3RS0_FET_ISNS

69

=PP1V5_S0_REG

68

=PP1V5_S0_RIO_LDO

68

=PPVTT_S3_DDR_BUF

33 64

=PPVTT_S0_DDR_LDO

64

=PP1V05_SUS_LDO

68

=PPCPUVCCIO_S0_REG

67

=PPPCHVCCIO_S0_REG

87

=PP1V05_S0_P1V05TBTFET

37 99

1.8V/1.5V/1.2V/1.05V Rails

Defined here since TBT page does not know PBUS voltage

=PPBUS_SW_BKL

99

SMC_T25_EN_L

41

I1679

Backlight Rails

PP1V8_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V8R1V5_S0_PCH_VCCVRM =PP1V8_S0_AUDIO =PP1V8_S0_CPU_VCCPLL =PP1V8_S0_GPUFET

=PP1V8_S0_PCH_VCCTX_LVDS

=PP1V8_S0_PCH_VCC_DFTERM =PPVDDIO_S0_SBCLK =PP1V8_S0_P1V5_LDO

PP1V8_S0_CPU_VCCPLL_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP1V5R1V35_S3

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3_MEMRESET =PPDDR_S3_MEMVREF =PPVIN_S3_P1V5S3RS0_FET =PPVIN_S0_DDRREG_LDO =PPVIN_S3_MEM_ISNS_R

PP1V5R1V35_MEM

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5R1V35_S3_MEM_A =PP1V5R1V35_S3_MEM_B

PP1V5_S3RS0_CPUDDR

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3RS0_VMON =PP1V5_S3_CPU_VCCDDR

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S0_AUDIO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

PP1V5_S0_RIO

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP1V5_S0_RIO

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_SUS_PCH_JTAG PP1V05_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_CPU_VCCIO

=PPVCCIO_S0_XDP =PPVCCIO_S0_CPUIMVP =PPVCCIO_S0_SMC =PP1V05_S0_VMON =PP1V05_S0_RMC

PP1V05_PCHVCCIO_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MAKE_BASE=TRUE =PP1V05_S0_PCH_VCCIO_PLLPCIE =PP1V05_S0_PCH_VCCADPLL =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE =PP1V05_S0_PCH_VCCIO_SATA =PP1V05_S0_PCH_VCCIO_CLK =PP1V05_S0_PCH_VCCIO_USB =PP1V05_S0_PCH_VCC_CORE =PP1V05_S0_PCH_VCCASW =PP1V05_S0_PCH_VCCIO_CLK =PP1V05_S0_PCH_VCCDIFFCLK =PP1V05_S0_PCH =PP1V05_S0_PCH_VCCSSC =PP1V05_S0_PCH_V_PROC_IO =PP1V05_S0_PCH_VCCIO_PLLUSB =PP1V05_S0_PCH_VCC_DMI =PP1V05_S0_PCH_VCCIO_PLLFDI =PP1V05_S0_PCH_VCCDMI_FDI =PP1V05_S0_P1V05TBTFET_R

PPVIN_SW_TBTBST

VOLTAGE=12.8V

VOLTAGE=1.5V MAKE_BASE=TRUE

37

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM

PPBUS_S0_LCDBKLT_PWR

NC_SMC_T25_EN_L

PP1V05_S0_P1V05TBTFET

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

6 3

VOLTAGE=1.8V MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=12.6V

MAKE_BASE=TRUE

VOLTAGE=1.05V MAKE_BASE=TRUE

7

21

15

23

20 21 23

25

68

27

33

69

64

45

28 29

30 31

96

70

11 14 16 27

53

21 23 25

7

38

7

32

27

24

7

10 11 13 14 15

24

65

42

70

98

21

23

21 23

18

17 21 23

8

21 23

8

21 23

17 21 23

17 23

21 23

21

21 23

21

99

=PP3V3_S0GPU_FET

69 88

=PP3V3_S0GPU_MISC_FET

69

74

=PP1V05_S0GPU_REG

74

45

=PPVCORE_S0_CPU_REG

66

=PPVCORE_S0_AXG_REG

45 66

=PP1V5_S3_CPU_VCCDQ

13 16

=PP1V05_S0_CPU_VCCPQE

13 15

=PPVCCSA_S0_REG

62 99

86

7

TP_P1V8GPU_EN

=PP1V5R1V35_GPU_REG

=PP1V8_GPU_FET

88

=PPVCORE_GPU_REG

GND

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.085MM VOLTAGE=0V

MAKE_BASE=TRUE

"GPU" Rails

PP3V3_S0GPU

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_GPU_IFPX_PLLVDD =PP3V3_S0_GFX3V3BIAS =PP3V3_GPU_VDD33

PP3V3_S0GPU_MISC

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_GPU_MISC

=P1V8GPU_EN

PP1V5R1V35_S0GPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V35_GPU_FBVDDQ =PP1V35_GPU_S0_FB

TP_GPU_PGOOD2

MAKE_BASE=TRUE

PP1V0_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP1V0_GPU_DPLL =PP1V0_GPU_DP_AB =PP1V0_GPU_DP_CD =PP1V05_GPU_IFPCD_IOVDD =PP1V05_GPU_IFPEF_IOVDD =PP1V05_GPU_PEX_IOVDD =PP1V05_GPU_PEX_PLLVDD

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PPVCORE_GPU

=PPVCORE_S0_GFX_REG

=LVDS_VCCA

Chipset "VCore" Rails

SYNC_MASTER=D2_KEPLER

PAGE TITLE

21

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

=PPVCORE_S0_CPU

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PPVCORE_S0_CPU_VCCAXG

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_CPU_VCCPQE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCCSA_S0_REG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PPVCCSA_S0_CPU

Power Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

88

MAKE_BASE=TRUE VOLTAGE=1.5V

VOLTAGE=1.05V MAKE_BASE=TRUE

12

VOLTAGE=1.05V MAKE_BASE=TRUE

VOLTAGE=1.0V MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=1.25V

MAKE_BASE=TRUE VOLTAGE=1.05V

VOLTAGE=0.9V MAKE_BASE=TRUE

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

7

77

80

71 77 78 79

77

SYNC_DATE=01/13/2012

051-9589

4.18.0

8 OF 132

8 OF 99

124578

72 75 76

73

77

73 79

77 79

7

72 79

80

7

13 15 45 98

13 14 16

13 16

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

ZT0915

2.8R2.3

ZT0950

TH-NSP

SL-2.3X3.9-2.9X4.5

ZT0974

TH-NSP

D

C

SL-1.1X0.45-1.4x0.75

ZT0975

TH-NSP

SL-1.1X0.45-1.4x0.75

SH0920

STDOFF-4.5OD2.15H-SM

1

STDOFF-4.5OD2.15H-SM-1

SH0921

1

STDOFF-4.5OD2.15H-SM

STDOFF-4.9OD2.38H-SM-2

1

SH0950

SM

SHLD-J5-USB

B

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0931

SM

1

SH0934

SM

1

2.8OD1.2ID-1.35H-SM

A

SH0942

2.8OD1.2ID-1.35H-SM

1

Frame Holes

1

GND_BATT_CHGND

1

GND_CHASSIS_FAN

1

GND_CHASSIS_MLBCAN5

1

GND_CHASSIS_MLBCAN6

THERMAL MODULE STANDOFFS

SH0922

1

SH0946

1

SH0952

SM

SHLD-J5-CAN-FENCE-MDP-2

POGO PINS

SH0940

1

ZT0970

TH-NSP

GND_CHASSIS_MLBCAN1

GND_CHASSIS_MLBCAN2

GND_CHASSIS_MLBCAN3

GND

MAKE_BASE=TRUE

SH0927

1

SH0929

STDOFF-4.5OD2.15H-SM

1

SH0930

STDOFF-4.5OD2.15H-SM

1

STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2

SH0945

1

GND_CHASSIS_MLBCAN4

SH0926

STDOFF-4.5OD2.15H-SMSTDOFF-4.5OD2.15H-SM

1

SH0928

STDOFF-4.5OD2.15H-SM

1

SL-1.1X0.45-1.4x0.75

ZT0971

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0972

TH-NSP

1

SL-1.1X0.45-1.4x0.75

ZT0973

TH-NSP

1

SL-1.1X0.45-1.4x0.75

SH0925

STDOFF-4.5OD1.8H-SM

1

SH0923

STDOFF-4.5OD1.8H-SM

1

SH0924

STDOFF-4.5OD1.9H-SM

1

APN 806-2247

BR0901

1

SH0951

SM

MLB-MTG-BRKT-J5

TH

1

SHLD-J5-CAN-FENCE-MDP-1

POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0932

SM

1

SH0935

SM

1

SH0941

2.8OD1.2ID-1.35H-SM

1

SH0933

SM

1

SH0936

SM

1

SH0944

2.8OD1.2ID-1.35H-SM

1

Digital Ground

SH0943

2.8OD1.2ID-1.35H-SM

1

20

MLB_RAMCFG0

6 3

TBT_LSOE<3>

TBT_LSOE<2>

82

LVDS_IG_BKL_ON

18

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

18

MAKE_BASE=TRUE

17

82

PCIE_EXCARD_D2R_N

17

PCIE_EXCARD_D2R_P

17

PCIE_EXCARD_R2D_C_N

17

PCIE_EXCARD_R2D_C_P

17

PCIE_CLK100M_EXCARD_N

17 92

PCIE_CLK100M_EXCARD_P

17 92

17

POGO-2.3OD-5.5H-SM-LOW-FORCE

TP_PCH_CLKOUT_DPN

TP_PCH_CLKOUT_DPP

38

ZT0990

2.1SM2.0MM-CIR 2.1SM2.0MM-CIR

SMT-PAD-NSP

1

SH0937

SM

1

2.8OD1.2ID-1.35H-SM

MLB_RAMCFG3

20

MLB_RAMCFG2

R0910

1/20W

20

RAMCFG1:L

1

1K

5% MF

201

2

R0911

1/20W

1

1K

5% MF

201

2

MLB_RAMCFG1

RAMCFG0:L

T29 / GMUX JTAG Signals

EG_RESET_L

MAKE_BASE=TRUE

PEX_CLKREQ_L

MAKE_BASE=TRUE

PEG_CLKREQ_L

MAKE_BASE=TRUE

DP_TBTSNK0_HPD_IG

MAKE_BASE=TRUE

DP_TBTSNK1_HPD_IG

MAKE_BASE=TRUE

TP_PCH_GPIO64_CLKOUTFLEX0 TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

SD_PWR_EN_PCH

MAKE_BASE=TRUE

SD_PWR_EN

7

MAKE_BASE=TRUE

TP_FW_PWR_EN

MAKE_BASE=TRUE

SMT GND TEST PONTS

SH0960

1

SH0961

1

RAMCFG2:L

R0912

1/20W

1

1K

5% MF

201

2

TBT_LSEO_LSOE3

MAKE_BASE=TRUE

TBT_LSEO_LSOE2

MAKE_BASE=TRUE

NO_TEST=TRUE

TBT_LSEO<3>

TBT_LSEO<2>

GMUX ALIASES

GPU_RESET_L

IG_BKLT_EN

IG_LCD_PWR_EN

EG_CLKREQ_IN_L

EG_CLKREQ_OUT_L

DPA_IG_HPD

DPB_IG_HPD

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

ENET_LOW_PWR_PCH

ENET_LOW_PWR

FW_PWR_EN

ZT0991

SMT-PAD-NSP SMT-PAD-NSP

1

RAMCFG3:L

1

R0913

1K

5%

1/20W

MF

201

2

NC_PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P

NC_PCIE_CLK100M_EXCARD_N

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_P

TRUE MAKE_BASE=TRUE

DPLL_REF_CLKN

DPLL_REF_CLKP

NC_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCH_GPIO66_CLKOUTFLEX2

NC_PCH_GPIO67_CLKOUTFLEX3

ZT0992

2.1SM2.0MM-CIR

1

ZT0993

2.1SM2.0MM-CIR

SMT-PAD-NSP

1

8

71 78

82

78 82

82

18 82

11 89

20 24 25

25

=PP5V_S0_AUDIO_XW

CPU_VID<0..6>

MAKE_BASE=TRUE

MEMVTT_EN

27

MAKE_BASE=TRUE

NC_PEG_D2R_P<15..14>

MAKE_BASE=TRUE

NC_PEG_D2R_N<15..14>

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15..14>

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15..14>

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3..0>

35 92

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3..0>

35 92

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3..0>

35 92

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

35 92

MAKE_BASE=TRUE

PEG_D2R_P<7..0>

71 88 89

MAKE_BASE=TRUE

PEG_D2R_N<7..0>

71 88 89

MAKE_BASE=TRUE

PEG_R2D_C_P<7..0>

71 89

MAKE_BASE=TRUE

PEG_R2D_C_N<7..0>

71 89

MAKE_BASE=TRUE

TBT_D2R_P<3..2>

TBT_D2R_N<3..2>

TBT_R2D_C_P<3..2>

TBT_R2D_C_N<3..2>

DPMUX_UC_BOOT_TX

82

DPMUX_UC_BOOT_RX

82

PCIE_SSD_D2R_P<1..0>

39 92

MAKE_BASE=TRUE

PCIE_SSD_D2R_N<1..0>

39 92

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_P<1..0>

39 92

MAKE_BASE=TRUE

PCIE_SSD_R2D_C_N<1..0>

39 92

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_P

MAKE_BASE=TRUE

TP_PCIE_CLK100M_FW_N

MAKE_BASE=TRUE

NC_PCH_FDI_DATA_N<7..0>

MAKE_BASE=TRUE

NC_PCH_FDI_DATA_P<7..0>

MAKE_BASE=TRUE

NC_PCH_FDI_FSYNC<1..0>

MAKE_BASE=TRUE

NC_PCH_FDI_LSYNC<1..0>

MAKE_BASE=TRUE

NC_CPU_FDI_DATA_N<7..0>

MAKE_BASE=TRUE

NC_CPU_FDI_DATA_P<7..0>

MAKE_BASE=TRUE

NC_CPU_FDI_FSYNC<1..0>

MAKE_BASE=TRUE

NC_CPU_FDI_LSYNC<1..0>

MAKE_BASE=TRUE

USB_BT_P

34 91

MAKE_BASE=TRUE

USB_BT_N

34 91

MAKE_BASE=TRUE

USB_TPAD_P

49 91

MAKE_BASE=TRUE

USB_TPAD_N

49 91

MAKE_BASE=TRUE

USB_SMC_P

41 91

MAKE_BASE=TRUE

USB_SMC_N

41 91

MAKE_BASE=TRUE

PU_USBHUB_DN4P

MAKE_BASE=TRUE

PU_USBHUB_DN4N

MAKE_BASE=TRUE

XW0902

SM

1 2

XW0903

SM

1 2

CPU signals

Unused PEG signals

NO_TEST=TRUE

T29 Signals Through PEG

GPU signals

UNUSED TBT PORTS

DPMUX TX & RX

SSD PCIE SIGNALS

UNUSED FDI SIGNALS

NO_TEST=TRUE

USB SIGNALS

PP5V_S0_AUDIO_AMP_L

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

PP5V_S0_AUDIO_AMP_R

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

CPUIMVP_VID<0..6>

=DDRVTT_EN

=PEG_D2R_P<15..14>

=PEG_D2R_N<15..14>

=PEG_R2D_C_P<15..14>

=PEG_R2D_C_N<15..14>

=PEG_D2R_P<11..8>

=PEG_D2R_N<11..8>

=PEG_R2D_C_P<11..8>

=PEG_R2D_C_N<11..8>

=PEG_D2R_P<7..0>

=PEG_D2R_N<7..0>

=PEG_R2D_C_P<7..0>

=PEG_R2D_C_N<7..0>

NC_TBT_D2RP<3..2>

MAKE_BASE=TRUE

NC_TBT_D2RN<3..2>

MAKE_BASE=TRUE

NC_TBT_R2D_CP<3..2>

MAKE_BASE=TRUE

NC_TBT_R2D_CN<3..2>

MAKE_BASE=TRUE

DPMUX_UC_TX

MAKE_BASE=TRUE

DPMUX_UC_RX

MAKE_BASE=TRUE

=PEG_D2R_P<13..12>

=PEG_D2R_N<13..12>

=PEG_R2D_C_P<13..12>

=PEG_R2D_C_N<13..12>

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

=FDI_DATA_N<7..0>

=FDI_DATA_P<7..0>

=FDI_FSYNC<1..0>

=FDI_LSYNC<1..0>

FDI_DATA_N<7..0>

FDI_DATA_P<7..0>

FDI_FSYNC<1..0>

FDI_LSYNC<1..0>

USBHUB_DN1_P

USBHUB_DN1_N

USBHUB_DN2_P

USBHUB_DN2_N

USBHUB_DN3_P

USBHUB_DN3_N

USBHUB_DN4_P

USBHUB_DN4_N

NO_TEST=TRUE

57

27 64

10

82

10

18

10 89

26

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

10

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

10

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

10

MAKE_BASE=TRUE

10

17 92

NC_USB3_EXTD_TX_P

MAKE_BASE=TRUE

NC_USB3_EXTD_TX_N

MAKE_BASE=TRUE

NC_USB3_EXTD_RX_P

MAKE_BASE=TRUE

NC_USB3_EXTD_RX_N

MAKE_BASE=TRUE

NC_USB_EXTD_EHCI_P

MAKE_BASE=TRUE

NC_USB_EXTD_EHCI_N

MAKE_BASE=TRUE

NC_USB3_EXTC_TX_P

MAKE_BASE=TRUE

NC_USB3_EXTC_TX_N

MAKE_BASE=TRUE

NC_USB3_EXTC_RX_P

MAKE_BASE=TRUE

NC_USB3_EXTC_RX_N

MAKE_BASE=TRUE

NC_USB_EXTC_P

MAKE_BASE=TRUE

NC_USB_EXTC_N

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_CLK_N

MAKE_BASE=TRUE

NC_LVDS_IG_A_CLK_P

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_N<2..0>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_P<2..0>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_N<2..0>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_P<2..0>

MAKE_BASE=TRUE

NC_LVDS_IG_DDC_CLK

MAKE_BASE=TRUE

NC_LVDS_IG_DDC_DATA

MAKE_BASE=TRUE

NC_PCIE_FW_D2RN

MAKE_BASE=TRUE

NC_PCIE_FW_D2RP

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CN

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CP

MAKE_BASE=TRUE

NC_SATA_ODD_D2R_N

MAKE_BASE=TRUE

NC_SATA_ODD_D2R_P

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_C_N

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_C_P

MAKE_BASE=TRUE

NC_DP_IG_MLP<3..0>

MAKE_BASE=TRUE

NC_DP_IG_MLN<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

TBTBST:N

=PPVIN_SW_TBTBST

8

37

UNUSED USB SIGNALS

NO_TEST=TRUE

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

I1187

I1188

I1189

I1190

I1192

I1191

USB3_EXTD_TX_P

USB3_EXTD_TX_N

USB3_EXTD_RX_P

USB3_EXTD_RX_N

USB_EXTD_EHCI_P

USB_EXTD_EHCI_N

USB3_EXTC_TX_P

USB3_EXTC_TX_N

USB3_EXTC_RX_P

USB3_EXTC_RX_N

USB_EXTC_P

USB_EXTC_N

Apple Inc.

R

CPU_VTTSELECT

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<2..0>

LVDS_IG_A_DATA_P<2..0>

LVDS_IG_B_DATA_N<2..0>

LVDS_IG_B_DATA_P<2..0>

LVDS_IG_DDC_CLK

LVDS_IG_DDC_DATA

PCIE_FW_D2R_N

PCIE_FW_D2R_P

PCIE_FW_R2D_C_N

PCIE_FW_R2D_C_P

SATA_ODD_D2R_N

SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

TP_DP_IG_B_MLP<3..0>

TP_DP_IG_B_MLN<3..0>

R0950

0

1 2

1/8W

MF-LF

5%

805

=PP15V_TBT_REG

19

19 91

Signal Aliases

18

8

37

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

9 OF 132

SHEET

9 OF 99

124578

18 91

18

18 91

18

17

17 91

SIZE

D

C

B

A

D

8 7 6 5 4 3

=PP1V05_S0_CPU_VCCIO

1

OMIT_TABLE

AC10

AA10

N10

R10

R8

U10

N8 T9

R6

U8

N4 R4

P1

U6

N2

R2 P3

T5

V7

W8

AA8

U4

W2

V1 Y5

W6

W10

Y9

U2 W4

V3

AA6

AC8

AA2

AD9

AB3

AB7

AG2

AF1 AE6

AG6

AG4

AF3 AF7

AG8

AE4

AE2

AB1

AC2

AE8

DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3*

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3*

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

FDI0_TX0* FDI0_TX1* FDI0_TX2* FDI0_TX3*

FDI1_TX0* FDI1_TX1* FDI1_TX2* FDI1_TX3*

FDI0_TX0 FDI0_TX1 FDI0_TX2 FDI0_TX3

FDI1_TX0 FDI1_TX1 FDI1_TX2 FDI1_TX3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI1_LSYNC FDI0_LSYNC

EDP_TX0* EDP_TX1* EDP_TX2* EDP_TX3*

EDP_TX0 EDP_TX1 EDP_TX2 EDP_TX3

EDP_AUX EDP_AUX*

EDP_ICOMPO EDP_COMPIO

EDP_HPD*

DMI_S2N_N<0>

18 89

IN

DMI_S2N_N<1>

18 89

IN

DMI_S2N_N<2>

18 89

IN

DMI_S2N_N<3>

18 89

IN

DMI_S2N_P<0>

18 89

IN

DMI_S2N_P<1>

18 89

IN

DMI_S2N_P<2>

18 89

D

C

=PP1V05_S0_CPU_VCCIO

8

10 11 13 14 15

1

OMIT_TABLE

B

82

1

R1031

1K

5% 1/16W MF-LF

402

2

DP_INT_IG_HPD

IN

R1030

24.9

1% 1/16W MF-LF 402

2

PLACE_NEAR=U1000.AB1:12.7mm

IN

DMI_S2N_P<3>

18 89

IN

DMI_N2S_N<0>

18 89

OUT

DMI_N2S_N<1>

18 89

OUT

DMI_N2S_N<2>

18 89

OUT

DMI_N2S_N<3>

18 89

OUT

DMI_N2S_P<0>

18 89

OUT

DMI_N2S_P<1>

18 89

OUT

DMI_N2S_P<2>

18 89

OUT

DMI_N2S_P<3>

18 89

OUT

FDI_DATA_N<0>

9

89

OUT

FDI_DATA_N<1>

9

89

OUT

FDI_DATA_N<2>

9

89

OUT

FDI_DATA_N<3>

9

89

OUT

FDI_DATA_N<4>

9

89

OUT

FDI_DATA_N<5>

9

89

OUT

FDI_DATA_N<6>

9

89

OUT

FDI_DATA_N<7>

9

89

OUT

FDI_DATA_P<0>

9

89

OUT

FDI_DATA_P<1>

9

89

OUT

FDI_DATA_P<2>

9

89

OUT

FDI_DATA_P<3>

9

89

OUT

FDI_DATA_P<4>

9

89

OUT

FDI_DATA_P<5>

9

89

OUT

FDI_DATA_P<6>

9

89

OUT

FDI_DATA_P<7>

9

89

OUT

FDI_FSYNC<0>

9

89

IN

FDI_FSYNC<1>

9

89

IN

FDI_INT

18 89

IN

FDI_LSYNC<1>

9

89

IN

FDI_LSYNC<0>

9

89

IN

DP_INT_IG_ML_N<0>

82 89

OUT

DP_INT_IG_ML_N<1>

82 89

OUT

DP_INT_IG_ML_N<2>

82 89

OUT

DP_INT_IG_ML_N<3>

82 89

OUT

DP_INT_IG_ML_P<0>

82 89

OUT

DP_INT_IG_ML_P<1>

82 89

OUT

DP_INT_IG_ML_P<2>

82 89

OUT

DP_INT_IG_ML_P<3>

82 89

OUT

DP_INT_IG_AUX_P

82 89

BI

DP_INT_IG_AUX_N

82 89

BI

CPU_EDP_COMP

89

DP_INT_IG_HPD_L

D

3

Q1031

1

2N7002TXG

G

SOT-523-3

EDP:YES

S

2

U1000

IVY-BRIDGE

BGA

(1 OF 11)

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

DMI

PEG_RX10* PEG_RX11* PEG_RX12* PEG_RX13* PEG_RX14* PEG_RX15*

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15*

EMBEDDED DISPLAY PORT

PEG_RX0* PEG_RX1* PEG_RX2* PEG_RX3* PEG_RX4* PEG_RX5* PEG_RX6* PEG_RX7* PEG_RX8* PEG_RX9*

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX0* PEG_TX1* PEG_TX2* PEG_TX3* PEG_TX4* PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8* PEG_TX9*

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

G2

H1

F3

F23

H23 H21

H19

J20 G18

K17 F15

H15

H13 H11

J12

E8 G10

J8

F7

G22 K23

K21

F19 K19

H17

K15 G14

J16

K13 F11

K11 F9

H9

H7 G6

A22 B23

C18

D21 B19

E20 A14

D17

B15 E16

D13

A10 B11

D9

B7 E12

C22

D23

A18 B21

D19

F21 C14

B17

D15 F17

B13 C10

D11

B9 D7

F13

89

CPU_PEG_COMP

=PEG_D2R_N<0>

=PEG_D2R_N<1> =PEG_D2R_N<2>

=PEG_D2R_N<3> =PEG_D2R_N<4>

=PEG_D2R_N<5>

=PEG_D2R_N<6> =PEG_D2R_N<7>

=PEG_D2R_N<8>

=PEG_D2R_N<9> =PEG_D2R_N<10>

=PEG_D2R_N<11>

=PEG_D2R_N<12> =PEG_D2R_N<13>

=PEG_D2R_N<14> =PEG_D2R_N<15>

=PEG_D2R_P<0> =PEG_D2R_P<1>

=PEG_D2R_P<2>

=PEG_D2R_P<3> =PEG_D2R_P<4>

=PEG_D2R_P<5>

=PEG_D2R_P<6> =PEG_D2R_P<7>

=PEG_D2R_P<8> =PEG_D2R_P<9>

=PEG_D2R_P<10>

=PEG_D2R_P<11> =PEG_D2R_P<12>

=PEG_D2R_P<13>

=PEG_D2R_P<14> =PEG_D2R_P<15>

=PEG_R2D_C_N<0> =PEG_R2D_C_N<1>

=PEG_R2D_C_N<2> =PEG_R2D_C_N<3>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<5> =PEG_R2D_C_N<6>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<8> =PEG_R2D_C_N<9>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<11> =PEG_R2D_C_N<12>

=PEG_R2D_C_N<13> =PEG_R2D_C_N<14>

=PEG_R2D_C_N<15>

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<2> =PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_P<7> =PEG_R2D_C_P<8>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<10> =PEG_R2D_C_P<11>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<13> =PEG_R2D_C_P<14>

=PEG_R2D_C_P<15>

R1010

24.9

1% 1/16W MF-LF 402

2

9

IN

9

IN

9

SIGNAL_MODEL=EMPTY

IN

1

TP

BEAD-PROBE

SM

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

SIGNAL_MODEL=EMPTY

IN

1

TP

BEAD-PROBE

SM

9

IN

1

TP

BEAD-PROBE

SM

9

IN

9

SIGNAL_MODEL=EMPTY

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

8

10 11 13 14 15

BP1004

BP1011 BP1012

NOTE:

Intel is investigating processor driven VREF_DQ generation. This connection is to support the same.

10 24 89

24 89

10 24 89

24 89

PPCPU_MEM_VREFDQ_B

33 89

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PPCPU_MEM_VREFDQ_A

33 89

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

CPU_CFG<0>

CPU_CFG<1> CPU_CFG<2>

CPU_CFG<3> CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

CPU_CFG<8>

CPU_CFG<9> CPU_CFG<10>

CPU_CFG<11>

CPU_CFG<12> CPU_CFG<13>

CPU_CFG<14> CPU_CFG<15>

CPU_CFG<16>

CPU_CFG<17>

B57

(IPU)

D57

(IPU)

B55

(IPU)

A54

(IPU)

A58

(IPU)

D55

(IPU)

C56

(IPU)

E54

(IPU)

J54

(IPU)

G56

(IPU)

CFG

F55

(IPU)

K55

(IPU)

F57

(IPU)

E58

(IPU)

H57

(IPU)

H55

(IPU)

D53

(IPU)

K57

(IPU)

G64

NC

BJ42

NC

BJ34

NC

BJ22

NC

BH43

NC

BH35

NC

BH25

NC

BH23

NC

BH21

NC

BH19

NC

BG62

NC

BG34

NC

BG26

NC

BG22

NC

BG4

(DDR_VREF1)

BF63

NC

BF43

NC

BF41

BF35 BF25

BF23

BF21 BF19

BE32

BE16

BD33

BD29

BD19 BD15

BD13

BC42 BC30

BC14

RSVD

BF3

(DDR_VREF0)

BE6

NC NC NC NC NC NC

NC NC NC NC NC NC NC NC NC NC NC

U1000

IVY-BRIDGE

BGA

(5 OF 11)

RESERVED

OMIT_TABLE

(THERMDA)

(THERMDC)

RSVD

BB57

BB43 BB25

BB17

BB15 BB13

BA48

BA16 AY45

AY41 AY17

AY15

AY13 AW50

AW46

AW42 AW14

AJ10

AJ6 AH5

AD5 AC6

AC4

AA4 P7

N6

M9 M5

L10

L6 L4

L2 K49

K47

K9 K7

K5

J50 J4

J2

H49 H47

H5 G52

G48

G4 F5

D49

D25 D3

C52

C24 C4

B53 B25

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

12

D

C

B

CPU_CFG<7>

10 24 89

CPU_CFG<6>

10 24 89

CPU_CFG<5>

10 24 89

CPU_CFG<4>

10 24 89

CPU_CFG<2>

10 24 89

A

CPU_CFG<4> should be pulled down to enable EDP

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

NOSTUFF

R1042

EDP:YES

1

R1044

1K

5%

1/16W

MF-LF

402

2

1

R1045

1K

5%

1/16W MF-LF

402

2

R1046

NOSTUFF

1

R1047

1K

5%

1/16W

MF-LF

402

2

CPU_CFG<16>

10 24 89

CPU_CFG<3>

10 24 89

CPU_CFG<1>

10 24 89

CPU_CFG<0>

10 24 89

NOSTUFF

These can be Placed close to J2500 and Only for debug access

R1040

NOSTUFF

1

1K

5% 1/16W MF-LF

402

2

R1041

NOSTUFF

1

R1043

1K

5% 1/16W MF-LF

402

1K

5% 1/16W MF-LF

402

2

PART NUMBER

116S0066

116S0090

NOSTUFF

1

2

R1049

1

1K

5% 1/16W MF-LF

402

2

QTY

1

DESCRIPTION

RES,MTL FILM,1/16W,1K,0402,SMD,LF

RES,MTL FILM,1/16W,10K,0402,SMD,LF

REFERENCE DES

R1031

CRITICAL

BOM OPTION

EDP:YES

EDP:NO

6 3

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

10 OF 132

SHEET

10 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PP1V05_S0_CPU_VCCIO

8

10 11 13 14 15

=PP1V05_S0_CPU_VCCIO

8

10 11 13 14 15

1

R1101

68

5%

1/16W

MF-LF

402

2

CPU_PROC_SEL_L

20 89

R1103

C

8

10 11 13 14 15

CPU_PROCHOT_L

41 42 65 89

BI

=PP1V05_S0_CPU_VCCIO

CPU_RESET_L

24 25

IN

=PP1V5_S3_CPU_VCCDDR

8

11 14 16 27

PLACE_NEAR=R1121.2:1mm

R1126

1/16W MF-LF

1

75

1%

402

2

R1120

PM_MEM_PWRGD

18 27 89

B

R1120 and R1121 are Intel recommended values

IN

=PP1V5_S3_CPU_VCCDDR

8

11 14 16 27

PLACE_NEAR=U1000.BJ44:2.54mm

R1130

1/16W MF-LF

1

1K

1%

402

2

56

12

5% 1/16W MF-LF

402

1

200

1% 1/16W MF-LF

402

R1121

2

130

1% 1/16W MF-LF

PLACE_NEAR=U1000.AY25:51.562mm

402

R1125

43.2

12

1% 1/16W MF-LF

402

12

PLACE_NEAR=U1000.BJ46:12.7mm

41 89

20 42 89

PLT_RESET_LS1V1_L

18 89

20 24 89

27

OUT

1

R1112

140

1% 1/16W MF-LF 402

2

PLACE_NEAR=U1000.BG46:12.7mm

OUT

BI

OUT

IN

PM_MEM_PWRGD_R

=MEM_RESET_L

CPU_DDR_VREF

1

R1113

25.5

1% 1/16W MF-LF 402

2

CPU_CATERR_L

CPU_PECI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

PM_SYNC

CPU_PWRGD

1

2

R1114

200

1% 1/16W MF-LF 402

NOSTUFF

1

R1100

1K

5%

1/20W

MF

201

2

89

CPU_SM_RCOMP<0>

CPU_SM_RCOMP<1>

89

CPU_SM_RCOMP<2>

89

PLACE_NEAR=U1000.BF45:12.7mm

1

2

R1104

51

5% 1/16W MF-LF 402

NOSTUFF

1

R1102

1K

5% 1/20W MF 201

2

NC

1

R1111

10K

5%

PLACE_NEAR=U1800.AY11:157mm

1/16W MF-LF 402

2

OMIT_TABLE

B59

PROC_DETECT*

AH9

PROC_SELECT*

H53

CATERR*

F53

PECI

H51

PROCHOT*

F51

THERMTRIP*

K51

RESET*

K53

PM_SYNC

C60

UNCOREPWRGOOD

AY25

SM_DRAMPWROK

BE24

SM_DRAMRST*

BJ44

SM_VREF

BJ46

SM_RCOMP0

BG46

SM_RCOMP1

BF45

SM_RCOMP2

U1000

IVY-BRIDGE

BGA

(2 OF 11)

THERMAL

PWR MGMT

DDR3 MISC

DPLL_REF_CLK

DPLL_REF_CLK*

CLOCKS

(IPU)

(IPD)

(IPU)

JTAG & BPM

(IPU)

BCLK_ITP

BCLK_ITP*

BCLK

BCLK*

PRDY* PREQ*

TRST*

DBR*

BPM0* BPM1* BPM2* BPM3* BPM4* BPM5* BPM6* BPM7*

TCK TMS

TDI TDO

AJ4 AJ2

K63 K65

D5

C6

J62

H65

J58

H59

H63

K61 K59

H61

C62

D61 E62

F63

D59 F61

F59 G60

DPLL_REF_CLKP

DPLL_REF_CLKN

ITPCPU_CLK100M_P

ITPCPU_CLK100M_N

DMI_CLK100M_CPU_P

DMI_CLK100M_CPU_N

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

XDP_CPU_TMS XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3> XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<6> XDP_BPM_L<7>

9

89

IN

9

89

IN

17 89

IN

17 89

IN

17 89

IN

17 89

IN

24 89

OUT

24 89

IN

24 89

IN

24 89

IN

24 89

IN

24 89

IN

24 89

OUT

24 25 89

OUT

24 89

BI

24 89

BI

24 89

BI

24 89

BI

24 89

BI

24 89

BI

24 89

BI

24 89

BI

D

C

B

1

R1131

1K

PLACE_NEAR=U1000.BJ44:2.54mm

1% 1/16W MF-LF

402

PLACE_NEAR=U1000.BJ44:2.54mm

A

1

C1130

0.1UF

10%

16V

2

X7R-CERM

2

0402

SIZE

A

D

6 3

PAGE TITLE

CPU CLOCK/MISC/JTAG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

11 OF 132

SHEET

11 OF 99

124578

8 7 6 5 4 3

12

SA_CLK0

SA_CKE0

SA_CLK1

SA_CKE1

SA_CS0* SA_CS1*

SA_ODT0 SA_ODT1

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

BB31

BA32

BC18

AW34

AY33

BD17

BD41

BD45

BB41

BC46

AN8

AU6

BC6 BD9

BC50 BB55

BD59

AU60

AN6

AU8 BD5

BC10

BB51 BD55

BD61 AV61

BD27 BA28

BB27

AW26 BB23

BA24

AY21 BD21

BC22 BB21

AW38

AW22 BA20

BB45

BE20 AW18

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<1> MEM_A_DQS_N<2>

MEM_A_DQS_N<3>

MEM_A_DQS_N<4> MEM_A_DQS_N<5>

MEM_A_DQS_N<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1>

MEM_A_DQS_P<2>

MEM_A_DQS_P<3> MEM_A_DQS_P<4>

MEM_A_DQS_P<5>

MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_A<0> MEM_A_A<1>

MEM_A_A<2> MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5> MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8> MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11> MEM_A_A<12>

MEM_A_A<13> MEM_A_A<14>

MEM_A_A<15>

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

28 32 90

29 32 90

28 32 90

29 32 90

28 32 90

29 32 90

28 29 90

28 29 32 90

BF11 BJ10

BH11

BG10 BJ14

BG14

BF17 BJ18

BF13

BH13 BH17

BG18 BH49

BF47

BH53 BG50

BF49

BH47 BF53

BJ50

BF55 BH55

BJ58 BH59

BJ54

BG54 BG58

BF59

BA64 BC62

AU62

AW64 BA62

BC64 AU64

AW62

AR64 AT65

AL64

AM65 AR62

AT63

AL62 AM63

BJ38

BD37

AY29

BH39

BG38 BF39

AL4

AK3 AP3

AR2

AL2 AK1

AP1

AR4 AV3

AU4 BA4

BB1

AV1 AU2

BA2

BB3 BC2

BF7

BC4 BH7

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS* SB_RAS* SB_WE*

U1000

IVY-BRIDGE

BGA

(4 OF 11)

OMIT_TABLE

MEMORY CHANNEL B

SB_CLK0*

SB_CLK1*

SB_DQS0* SB_DQS1* SB_DQS2* SB_DQS3* SB_DQS4* SB_DQS5* SB_DQS6* SB_DQS7*

MEM_B_DQ<0>

30 31 90

BI

MEM_B_DQ<1>

30 31 90

BI

MEM_B_DQ<2>

30 31 90

BI

MEM_B_DQ<3>

30 31 90

BI

MEM_B_DQ<4>

30 31 90

BI

MEM_B_DQ<5>

30 31 90

BI

MEM_B_DQ<6>

30 31 90

BI

MEM_B_DQ<7>

30 31 90

BI

MEM_B_DQ<8>

30 31 90

BI

MEM_B_DQ<9>

30 31 90

BI

MEM_B_DQ<10>

30 31 90

BI

MEM_B_DQ<11>

30 31 90

BI

MEM_B_DQ<12>

30 31 90

BI

MEM_B_DQ<13>

30 31 90

BI

MEM_B_DQ<14>

30 31 90

BI

MEM_B_DQ<15>

30 31 90

BI

MEM_B_DQ<16>

30 31 90

BI

MEM_B_DQ<17>

30 31 90

BI

MEM_B_DQ<18>

30 31 90

BI

MEM_B_DQ<19>

30 31 90

BI

MEM_B_DQ<20>

30 31 90

BI

MEM_B_DQ<21>

30 31 90

BI

MEM_B_DQ<22>

30 31 90

BI

MEM_B_DQ<23>

30 31 90

BI

MEM_B_DQ<24>

30 31 90

BI

MEM_B_DQ<25>

30 31 90

BI

MEM_B_DQ<26>

30 31 90

BI

MEM_B_DQ<27>

30 31 90

BI

MEM_B_DQ<28>

30 31 90

BI

MEM_B_DQ<29>

30 31 90

BI

MEM_B_DQ<30>

30 31 90

BI

MEM_B_DQ<31>

30 31 90

BI

MEM_B_DQ<32>

30 31 90

BI

MEM_B_DQ<33>

30 31 90

BI

MEM_B_DQ<34>

30 31 90

BI

MEM_B_DQ<35>

30 31 90

BI

MEM_B_DQ<36>

30 31 90

BI

MEM_B_DQ<37>

30 31 90

BI

MEM_B_DQ<38>

30 31 90

BI

MEM_B_DQ<39>

30 31 90

BI

MEM_B_DQ<40>

30 31 90

BI

MEM_B_DQ<41>

30 31 90

BI

MEM_B_DQ<42>

30 31 90

BI

MEM_B_DQ<43>

30 31 90

BI

MEM_B_DQ<44>

30 31 90

BI

MEM_B_DQ<45>

30 31 90

BI

MEM_B_DQ<46>

30 31 90

BI

MEM_B_DQ<47>

30 31 90

BI

MEM_B_DQ<48>

30 31 90

BI

MEM_B_DQ<49>

30 31 90

BI

MEM_B_DQ<50>

30 31 90

BI

MEM_B_DQ<51>

30 31 90

BI

MEM_B_DQ<52>

30 31 90

BI

MEM_B_DQ<53>

30 31 90

BI

MEM_B_DQ<54>

30 31 90

BI

MEM_B_DQ<55>

30 31 90

BI

MEM_B_DQ<56>

30 31 90

BI

MEM_B_DQ<57>

30 31 90

BI

MEM_B_DQ<58>

30 31 90

BI

MEM_B_DQ<59>

30 31 90

BI

MEM_B_DQ<60>

30 31 90

BI

MEM_B_DQ<61>

30 31 90

BI

MEM_B_DQ<62>

30 31 90

BI

MEM_B_DQ<63>

30 31 90

BI

MEM_B_BA<0>

30 31 32 90

OUT

MEM_B_BA<1>

30 31 32 90

OUT

MEM_B_BA<2>

30 31 32 90

OUT

MEM_B_CAS_L

30 31 32 90

OUT

MEM_B_RAS_L

30 31 32 90

OUT

MEM_B_WE_L

30 31 32 90

OUT

AL10

AN10

AR10

AW12

AV11

BB11 BA12

BA10 BD11

BE12 BB49

AY49

BE52 BD51

BD49

BE48 BA52

AY51

BC54 AY53

AW54 AY55

BD53

BB53 BE56

BA56

BD57 BF61

BA60

BB61 BE60

BD63 BB59

BC58

AW58 AY59

AL60

AP61 AW60

AY57

AN60 AR60

BA36

BC38

BB19

BE44

BE36 BA44

AL6

AL8 AP7

AM5

AK7

AM9

AR8 AV7

AY5

AT5 AR6

AW6

AT9 BA6

BA8

BG6 AY9

AW8 BB7

BC8

BE4

BE8

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS* SA_RAS* SA_WE*

U1000

IVY-BRIDGE

BGA

(3 OF 11)

OMIT_TABLE

MEMORY CHANNEL A

SA_CLK0*

SA_CLK1*

SA_DQS0* SA_DQS1* SA_DQS2* SA_DQS3* SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7*

MEM_A_DQ<0>

28 29 90

BI

MEM_A_DQ<1>

28 29 90

BI

MEM_A_DQ<2>

28 29 90

BI

MEM_A_DQ<3>

28 29 90

BI

MEM_A_DQ<4>

28 29 90

D

C

B

BI

MEM_A_DQ<5>

28 29 90

BI

MEM_A_DQ<6>

28 29 90

BI

MEM_A_DQ<7>

28 29 90

BI

MEM_A_DQ<8>

28 29 90

BI

MEM_A_DQ<9>

28 29 90

BI

MEM_A_DQ<10>

28 29 90

BI

MEM_A_DQ<11>

28 29 90

BI

MEM_A_DQ<12>

28 29 90

BI

MEM_A_DQ<13>

28 29 90

BI

MEM_A_DQ<14>

28 29 90

BI

MEM_A_DQ<15>

28 29 90

BI

MEM_A_DQ<16>

28 29 90

BI

MEM_A_DQ<17>

28 29 90

BI

MEM_A_DQ<18>

28 29 90

BI

MEM_A_DQ<19>

28 29 90

BI

MEM_A_DQ<20>

28 29 90

BI

MEM_A_DQ<21>

28 29 90

BI

MEM_A_DQ<22>

28 29 90

BI

MEM_A_DQ<23>

28 29 90

BI

MEM_A_DQ<24>

28 29 90

BI

MEM_A_DQ<25>

28 29 90

BI

MEM_A_DQ<26>

28 29 90

BI

MEM_A_DQ<27>

28 29 90

BI

MEM_A_DQ<28>

28 29 90

BI

MEM_A_DQ<29>

28 29 90

BI

MEM_A_DQ<30>

28 29 90

BI

MEM_A_DQ<31>

28 29 90

BI

MEM_A_DQ<32>

28 29 90

BI

MEM_A_DQ<33>

28 29 90

BI

MEM_A_DQ<34>

28 29 90

BI

MEM_A_DQ<35>

28 29 90

BI

MEM_A_DQ<36>

28 29 90

BI

MEM_A_DQ<37>

28 29 90

BI

MEM_A_DQ<38>

28 29 90

BI

MEM_A_DQ<39>

28 29 90

BI

MEM_A_DQ<40>

28 29 90

BI

MEM_A_DQ<41>

28 29 90

BI

MEM_A_DQ<42>

28 29 90

BI

MEM_A_DQ<43>

28 29 90

BI

MEM_A_DQ<44>

28 29 90

BI

MEM_A_DQ<45>

28 29 90

BI

MEM_A_DQ<46>

28 29 90

BI

MEM_A_DQ<47>

28 29 90

BI

MEM_A_DQ<48>

28 29 90

BI

MEM_A_DQ<49>

28 29 90

BI

MEM_A_DQ<50>

28 29 90

BI

MEM_A_DQ<51>

28 29 90

BI

MEM_A_DQ<52>

28 29 90

BI

MEM_A_DQ<53>

28 29 90

BI

MEM_A_DQ<54>

28 29 90

BI

MEM_A_DQ<55>

28 29 90

BI

MEM_A_DQ<56>

28 29 90

BI

MEM_A_DQ<57>

28 29 90

BI

MEM_A_DQ<58>

28 29 90

BI

MEM_A_DQ<59>

28 29 90

BI

MEM_A_DQ<60>

28 29 90

BI

MEM_A_DQ<61>

28 29 90

BI

MEM_A_DQ<62>

28 29 90

BI

MEM_A_DQ<63>

28 29 90

BI

MEM_A_BA<0>

28 29 32 90

OUT

MEM_A_BA<1>

28 29 32 90

OUT

MEM_A_BA<2>

28 29 32 90

OUT

MEM_A_CAS_L

28 29 32 90

OUT

MEM_A_RAS_L

28 29 32 90

OUT

MEM_A_WE_L

28 29 32 90

OUT

SB_CLK0

SB_CKE0

SB_CLK1

SB_CKE1

SB_CS0* SB_CS1*

SB_ODT0 SB_ODT1

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BF33

BH33

BD25

BF37

BH37

BJ26

BE40

BH41

BG42

BH45

AN4

AW2

BH9 BF15

BF51 BH57

AY63

AN62

AN2

AW4 BF9

BH15

BH51 BF57

AY65 AN64

BF31 BH31

BB37

BC34 BF27

BB33

BH27 BG30

BH29 BF29

AY37

BJ30 AW30

BA40

BB29 BE28

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_DQS_N<0>

MEM_B_DQS_N<1> MEM_B_DQS_N<2>

MEM_B_DQS_N<3>

MEM_B_DQS_N<4> MEM_B_DQS_N<5>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MEM_B_DQS_P<3> MEM_B_DQS_P<4>

MEM_B_DQS_P<5>

MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_A<0> MEM_B_A<1>

MEM_B_A<2> MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5> MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8> MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11> MEM_B_A<12>

MEM_B_A<13> MEM_B_A<14>

MEM_B_A<15>

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

30 32 90

31 32 90

30 32 90

31 32 90

30 32 90

31 32 90

30 31 90

30 31 32 90

D

C

B

A

PAGE TITLE

CPU DDR3 INTERFACES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

12 OF 132

SHEET

12 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

PLACE_NEAR=U1000.B47:50.8mm

B

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.A46:50.8mm

PLACE_SIDE=BOTTOM

D

=PP3V3_S0_CPU_VCCIO_SEL

For Future Compatibility

1

R1320

10K

5% 1/16W MF-LF

=PPVCCSA_S0_CPU

8

=PP1V05_S0_CPU_VCCIO

PLACE_NEAR=R1310.1:2.54mm

1

R1300

75

1% 1/16W MF-LF 402

8

13 15 45 98

8

10 11 13 14 15

PLACE_SIDE=BOTTOM

2

402 1/16W

NOSTUFF

1 2

1/16W402

0

1 2

0

1 2

8

13 14

16

R1364

49.9

1%

1/20W

MF

201

R1365

49.9

1%

1/20W

MF

201

CPU_VIDSOUT

65 89

BI

CPU_VIDSCLK

65 89

OUT

CPU_VIDALERT_L

65 89

IN

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCIO

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AW10:50.8mm

NOSTUFF

1

R1360

100

5% 1/16W MF-LF

402

2

65 89

OUT

65 89

OUT

65 89

OUT

65 89

OUT

67 89

OUT

67 89

OUT

1

R1361

100

5% 1/16W MF-LF

402

2

1

R1362

100

1% 1/16W MF-LF 402

R1363

100

1% 1/16W MF-LF 402

R1366

100

1%

NOSTUFF

1/16W MF-LF 402

2

PLACE_NEAR=U1000.F49:50.8mm

PLACE_NEAR=U1000.E50:50.8mm

PLACE_SIDE=BOTTOM

1

R1367

100

1% 1/16W MF-LF 402

2

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AU10:50.8mm

NOSTUFF

R1312

R1311

R1310

43

1

2

1

2

1

2

1

2

8

10 11 13 14 15

=PP1V05_S0_CPU_VCCIO

1

R1302

130

1% 1/16W MF-LF 402

2

MF-LF5%

5%402 1/16W MF-LF

5% MF-LF

PLACE_NEAR=U1000.B51:38mm

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU_VCCAXG=PPVCORE_S0_CPU_VCCAXG

PLACE_SIDE=BOTTOM

NOSTUFF

R1370

49.9

1% 1/20W MF 201

62 89

OUT

R1371

PLACE_SIDE=BOTTOM

49.9

1%

NOSTUFF

1/20W MF 201

PLACE_NEAR=U1000.A50:2.54mm

CPU_VIDSOUT_R

CPU_VIDSCLK_R

CPU_VIDALERT_L_R

=PPVCCSA_S0_CPU

1

R1368

100

1% 1/16W MF-LF 402

2

8

13 15 45 98

8

13 14 16

8 16

8

10 11 13 14 15

13

62 89

OUT

62 89

OUT

13 16

CPU_VCCSA_VID<0> CPU_VCCSA_VID<1>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

TP_CPU_VDDQSENSEP

TP_CPU_VDDQSENSEN

CPU_VCCSASENSE

TP_CPU_DIE_SENSE

CPU_VCC_VALSENSE_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_AXG_VALSENSE_N

R1314

VCCDQ

VCCPLL

VCCPQE

AJ8

AV23

AT23 AP23

AL23

AK65

AK63

AK61

AV21

AT21 AP21

AL21

BJ60

BJ6 BH61

BH5

BE64 BE2

BD65

BD1 F65

F1 E64

E2

B61 B5

A60

A6

A4

A62 A64

B3 B63

B65

BF1 BF65

BG2

BG64 BH1

BH3

BH63 BH65

BJ2 BJ4

BJ62

BJ64 C2

C64

D1 D65

CPU_VCCIO_SEL

TP_DC_TEST_A4

TP_DC_TEST_A62 DC_TEST_B63_A64

DC_TEST_B3_C2

DC_TEST_B65_C64

TP_DC_TEST_BF1

TP_DC_TEST_BF65 DC_TEST_BH1_BG2

DC_TEST_BG64_BH65

DC_TEST_BH3_BJ2

DC_TEST_BJ64_BH63

TP_DC_TEST_BJ4 TP_DC_TEST_BJ62

TP_DC_TEST_D1

TP_DC_TEST_D65

W17

W15 W12

U17 U15

U12

T16 T14

T11

N18

VCCSA

N16

N14

M17 M15

M12 M11

L18

L14

A50

VIDSOUT

D51

VIDSCLK

B51

VIDALERT*

AE10

VCCSA_VID0

AG10

VCCSA_VID1

B47

VCC_SENSE

A46

VSS_SENSE

F49

VAXG_SENSE

E50

VSSAXG_SENSE

AW10

VCCIO_SENSE

AU10

VSS_SENSE_VCCIO

AY19

VDDQ_SENSE

AW20

VSS_SENSE_VDDQ

K3

VCCSA_SENSE

F47

VCC_DIE_SENSE

D47

VCC_VAL_SENSE

C48

VSS_VAL_SENSE

B49

VAXG_VAL_SENSE

A48

VSSAXG_VAL_SENSE

1

R1313

10K

5% 1/16W MF-LF

402

5% 1/16W MF-LF 402

2

U1000

IVY-BRIDGE

BGA

(9 OF 11)

OMIT_TABLE

VCCIO_SEL

VSS_NCTF

DC_TEST_A4 DC_TEST_A62 DC_TEST_A64

DC_TEST_B3 DC_TEST_B63 DC_TEST_B65 DC_TEST_BF1

DC_TEST_BF65

DC_TEST_BG2

DC_TEST_BG64

DC_TEST_BH1 DC_TEST_BH3

DC_TEST_BH63 DC_TEST_BH65

DC_TEST_BJ2 DC_TEST_BJ4

DC_TEST_BJ62 DC_TEST_BJ64

DC_TEST_C2 DC_TEST_C64

DC_TEST_D1 DC_TEST_D65

402

2

=PP1V5_S3_CPU_VCCDQ

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

8

16

8

15

8

15

8

13 15 45 98

=PPVCORE_S0_CPU

R46 R42

R40

R36 R34

R29

R27 G38 R23

R21 N45

N43

N39 N37

N33

N30 N26

N24

N20 M46

M42 M40

M36

M34 M29

M27

M23 M21

L44

VCC VCC

L40 L38

L34 L32

L28

L26 L22

K45

K43 K41

K37

K35 K31

K29 K25

J44

J40 J38

J34

J32 J28

J26

H45 H43

H41 H37

U1000

IVY-BRIDGE

BGA

(6 OF 11)

CORE POWER

OMIT_TABLE

=PPVCORE_S0_CPU

H35 H31

H29

H25 G44

G40

G34

G32 G28

G26

F45 F43

F41

F37 F35

F31

F29 F25

E44 E40

E38

E34 E32

E28

E26 D45

D43

D41 D37

D35 D31

D29

C44 C40

C38

C34 C32

C28

C26 B45

B43 B41

B37

B35 B31

B29

A44 A40

A38

A34 A32

A28 A26

8

13 15 45 98

C

B

NOTE: Intel validation sense lines per doc 439028 rev1.0

HR_PPDG sections 6.2.1 and 6.3.1.

A

SYNC_MASTER=D2_KEPLER

PAGE TITLE

CPU POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

13 OF 132

SHEET

13 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

BJ56

BJ52 BJ48

BJ40

BJ32 BJ24

BJ20

BJ16

D

C

B

BJ12

BG60 BG56

BG52 BG48

BG44

BG36 BG28

BG24

BG20 BG16

BG12

BE62 BE58

BE54

BE50 BE46

BE42

BE38 BE34

BE30

BE26 BE22

BE18 BE14

BE10

BD35

BC60 BC56

BC52

BC48 BC44

BC40 BC36

BC32

BC28 BC26

BC24

BC20 BC16

BC12

BB65 BB63

BB47 BB39

BA58

BA54

BA50 BA46

BA42

BA38 BA34

BA30 BA26

BA22

BA18 BA14

AY61

AY11

AW56

AW52 AW48

AW44

AW40 AW36

AW32

AW28 AW24

BJ8

BG8 BF5

BD7

BD3

BB9

BB5

AY7

AY3

AY1

U1000

IVY-BRIDGE

BGA

(10 OF 11)

OMIT_TABLE

AW16

AV65 AV63

AV59

AV57 AV50

AV44

AV38 AV31

AV25

AV19 AV9

AV5 AU54

AU47

AU41 AU35

AU28

AU22 AU16

AU14

AT61 AT57

AT50 AT44

AT38

AT31 AT25

AT19

AT11 AT7

AT3

AT1 AR54

AR47 AR41

AR35

AR28 AR22

AP65

AP63 AP57

AP50

AP44

VSSVSS

AP38

AP31 AP25

AP19

AP17 AP15

AP12

AP11 AP9

AP5

AN54 AN47

AN41 AN35

AN28

AN22 AM61

AM7

AM3 AM1

AL57

AL50 AL44

AL38 AL31

AL25

AL19 AK16

AK14

AK11 AK9

AK5

AJ64 AJ62

AJ60 AJ57

AH7

AH3 AH1

AG57

AG17 AG15

AG12

AF65 AF63

AF61

AF11

AE57 AD16

AD14

AC64

AC62

AC60 AC57

AB11

AA57

AA17 AA15

AA12

U1000

IVY-BRIDGE

BGA

(11 OF 11)

AF9

AF5

AD7 AD3

AD1

AB9 AB5

Y65

Y63

Y61

Y7

Y3

Y1 W57

V16

V14 V11

V9

V5

U64

U62 U60

U57

T7

T3

T1

R57 R50

R44 R38

R31

R25 R19

R17

R15 R12

P65

P63 P61

P11

P9

P5

N54 N47

N41

N35 N28

N22

M57 M50

M44 M38

M31

M25 M19

M7

M3

M1

L64

L62 L60

L58 L54

L50

L46 L42

L36

L30 L24

OMIT_TABLE

A

6 3

L20

L16 L12

L8

K39 K33

K27

K1 J64

J60

J56 J52

J48 J46

J42

J36 J30

J24

J22 J18

J14

J10 J6

H39 H33

H27

H3 G62

G58

G54 G50

G46

G42 G36

G30 G24

G20

G16 G12

G8

VSSVSS

F39 F33

F27

E60 E56

E52 E48

E46

E42 E36

E30

E24 E22

E18

E14 E10

E6 E4

D63

D39 D33

D27

C58 C54

C50

C46 C42

C36 C30

C20

C16 C12

C8

B39 B33

B27

A56 A52

A42 A36

A30

A24 A20

A16

A12 A8

=PPVCORE_S0_CPU_VCCAXG

8

13 16

AH65

AH63 AH61

AH58

AH56 AG64

AG62

AG60 AF58

AF56

AE64 AE62

AE60 AD65

AD63

AD61 AD58

AD56

AB65 AB63

AB61

AB58 AB56

AA64 AA62

AA60

=PP1V5_S3_CPU_VCCDDR

VDDQ

BJ36

BJ28 BG40

BG32

BD47 BD43

BD39

BD31 BD23

BB35

AY47 AY43

AY39 AY35

AY31

AY27 AY23

AV46

AV42 AV40

AV36

AV34 AV29

AV27 AU45

AU43

AU39 AU37

AU33

AU30 AU26

AU24

AT46 AT42

AT40 AT36

AT34

AT29 AT27

AR45

AR43 AR39

AR37

AR33 AR30

AR26 AR24

AP46

AP42 AP40

AP36

AP34 AP29

AP27

AN45 AN43

AN39 AN37

AN33

AN30 AN26

AN24

AL46 AL42

AL40

AL36 AL34

AL29 AL27

U1000

IVY-BRIDGE

BGA

(8 OF 11)

OMIT_TABLE

Y58 Y56

W64

W62 W60

V65

V63

VAXG

V61

V58 V56

T65

T63 T61

T58

T56 R64

R62

R60 R55

R53 R48

N64

N62 N60

N58

N56 N52

N49

M65 M63

M61 M59

M55

M53 M48

L56

L52 L48

GRAPHIC CORE POWER

IO POWER DDR3

8

11 16 27

=PP1V05_S0_CPU_VCCIO =PP1V05_S0_CPU_VCCIO

8

10 11 13 14 15

AV55 AV53

AV48

AV17 AV15

AV12 AU58

AU56

AU52 AU49

AU20

AU18 AT55

AT53

AT48 AT17

AT15 AT12

AR58

AR56 AR52

AR49

AR20 AR18

AR16

AR14 AP55

AP53 AP48

AN58

AN56 AN52

AN49

U1000

IVY-BRIDGE

BGA

(7 OF11) IO POWER

OMIT_TABLE

AN20 AN18

AN16

AN14 AM11

AL55 AL53

AL48

AL17 AL15

AL12

AK58 AK56

AJ17

AJ15 AJ12

AH16

VCCIOVCCIO

AH14

AH11

AF16 AF14

AE17

AE15 AE12

AD11

AC17 AC15

AC12 AB16

AB14

Y16 Y14

Y11

8

10 11 13 14 15

PAGE TITLE

CPU POWER AND GND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

14 OF 132

SHEET

14 OF 99

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

12

CPU VCORE DECOUPLING

Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF) Apple Implementation: 8x 270uF 6mOhm, 0x 470uF 4mOhm , 16x 22uF 0402, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0402 (NOSTUFF)

=PPVCORE_S0_CPU

8

13 45 98

D

PLACEMENT_NOTE (C1600-C16C7):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1600

1UF

2

10% 10V X6S-CERM 0402

1

C1601

2

1UF

10% 10V X6S-CERM 0402

1

2

C1602

1UF

10% 10V X6S-CERM 0402

1

2

C1603

1UF

10% 10V X6S-CERM 0402

1

C1604

2

1UF

10% 10V X6S-CERM 0402

1

C1605

1UF

10% 10V

2

X6S-CERM 0402

1

2

C1606

1UF

10% 10V X6S-CERM 0402

1

C1607

1UF

2

10% 10V X6S-CERM 0402

1

C1608

2

1UF

10% 10V X6S-CERM 0402

1

C1609

1UF

10% 10V

2

X6S-CERM 0402

1

C1610

1UF

2

10% 10V X6S-CERM 0402

1

C1611

2

1UF

10% 10V X6S-CERM 0402

1

C1612

2

1UF

10% 10V X6S-CERM 0402

1

2

C1613

1UF

10% 10V X6S-CERM 0402

1

2

C1614

1UF

10% 10V X6S-CERM 0402

1

C1615

1UF

10% 10V

2

X6S-CERM 0402

1

C1616

1UF

10% 10V

2

X6S-CERM 0402

1

C1617

1UF

10% 10V

2

X6S-CERM 0402

1

C1618

2

1UF

10% 10V X6S-CERM 0402

1

C1619

2

1UF

10% 10V X6S-CERM 0402

D

NOSTUFF

1

C16A0

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C16C0

1UF

20% 4V

2

CERM-X6S 0201

PLACEMENT_NOTE (C1620-C1623): Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side. Place near U1000 on bottom side

Place near U1000 on bottom side

1

C1620

10UF

20% 4V

2

X6S 0402

C

PLACEMENT_NOTE (C1624-C16D5):

Place near inductors on bottom side.

CRITICAL

1

C1624

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16A1

2

NOSTUFF

1

C16C1

2

1

2

1

2

1UF

20% 4V CERM-X6S 0201

1UF

20% 4V CERM-X6S 0201

C1621

10UF

20% 4V X6S 0402

CRITICAL

C1625

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A2

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C16C2

1UF

20% 4V

2

CERM-X6S 0201

1

C1622

2

CRITICAL

1

C1626

2

10UF

20% 4V X6S 0402

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A3

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C16C3

1UF

20% 4V

2

CERM-X6S 0201

1

C1623

2

CRITICAL

1

C1627

2

10UF

20%

4V

X6S

0402

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A4

2

NOSTUFF

1

C16C4

2

1UF

20% 4V CERM-X6S 0201

1UF

20% 4V CERM-X6S 0201

NOSTUFF CRITICAL

1

C1628

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16A5

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF

1

C16C5

1UF

20% 4V

2

CERM-X6S 0201

CRITICAL

1

C1629

20UF

20% 2V

2

X6T-CERM 0402

1

2

1

2

NOSTUFF

C16A6

1UF

20% 4V CERM-X6S 0201

NOSTUFF

C16C6

1UF

20% 4V CERM-X6S 0201

CRITICAL

1

C1630

2

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A7

1UF

2

NOSTUFF

1

C16C7

1UF

2

20% 4V CERM-X6S 0201

1

2

CRITICAL

C1631

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A8

2

1UF

20% 4V CERM-X6S 0201

1

2

NOSTUFF CRITICAL

C1632

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16A9

1UF

20% 4V

2

CERM-X6S 0201

NOSTUFF CRITICAL

1

C1633

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B0

1UF

2

20% 4V CERM-X6S 0201

CRITICAL

1

C1634

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B1

2

1UF

20% 4V CERM-X6S 0201

CRITICAL

1

C1635

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B2

2

1UF

20% 4V CERM-X6S 0201

NOSTUFF CRITICAL

1

C1690

20UF

20% 2V

2

X6T-CERM 0402

CRITICAL

1

C1636

20UF

20% 2V

2

X6T-CERM 0402

1

2

NOSTUFF

C16B3

1UF

20% 4V CERM-X6S 0201

NOSTUFF CRITICAL

1

C1691

20UF

20% 2V

2

X6T-CERM 0402

CRITICAL

1

C1637

20UF

20% 2V

2

X6T-CERM 0402

1

2

NOSTUFF

C16B4

1UF

20% 4V CERM-X6S 0201

NOSTUFF CRITICAL

1

C1698

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF CRITICAL

1

C1638

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B5

1UF

20% 4V

2

CERM-X6S 0201

CRITICAL

1

C1693

20UF

20% 2V

2

X6T-CERM 0402

CRITICAL

1

C1639

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B6

1UF

20% 4V

2

CERM-X6S 0201

CRITICAL

1

C1694

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D0

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B7

2

1UF

20% 4V CERM-X6S 0201

CRITICAL

1

C1695

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D1

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16B8

2

1UF

20% 4V CERM-X6S 0201

1

C1696

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D2

20UF

2

20% 2V X6T-CERM 0402

NOSTUFF

1

C16B9

1UF

20% 4V

2

CERM-X6S 0201

CRITICAL

NOSTUFF CRITICAL

1

C1699

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D3

20UF

20% 2V

2

X6T-CERM 0402

NOSTUFF

1

C16D4

2

20UF

20% 2V X6T-CERM 0402

NOSTUFF

1

C16D5

20UF

20% 2V

2

X6T-CERM 0402

C

PLACEMENT_NOTE (C1640-C1645):

CRITICAL

1

C1640

270UF

20% 2V

2

TANT CASE-B2-SM

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402 Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

PLACEMENT_NOTE (C1646-C1671):

Place on bottom side of U1000

Place on bottom side of U100.

=PP1V05_S0_CPU_VCCIO

8

10 11 13

B

14

Place on bottom side of U1000

1

C1646

1UF

10% 10V

2

X6S-CERM 0402

1

C1659

1UF

10% 10V

2

X6S-CERM 0402

1

C1647

2

1

C1660

2

CRITICAL

1

C1641

270UF

20% 2V

2

TANT CASE-B2-SM

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

1

2

1

2

CRITICAL

1

C1642

270UF

20% 2V

2

TANT CASE-B2-SM

C1648

1UF

10% 10V X6S-CERM 0402

C1661

1UF

10% 10V X6S-CERM 0402

1

2

1

C1662

2

1

2

C1649

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

CRITICAL

C1643

270UF

20% 2V TANT CASE-B2-SM

1

C1650

2

1

C1663

2

1

2

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

CRITICAL

C1644

270UF

20% 2V TANT CASE-B2-SM

1

C1651

1UF

10% 10V

2

X6S-CERM 0402

1

C1664

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1645

270UF

20% 2V

2

TANT CASE-B2-SM

1

2

1

C1665

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1688

270UF

20% 2V

2

TANT CASE-B2-SM

C1652

1UF

10% 10V X6S-CERM 0402

1

2

1

C1666

1UF

2

1

2

C1653

1UF

10% 10V X6S-CERM 0402

CRITICAL

C1689

270UF

20% 2V TANT CASE-B2-SM

1

C1654

2

1

C1667

2

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

1

C1655

1UF

10% 10V

2

X6S-CERM 0402

1

C1668

1UF

10% 10V

2

X6S-CERM 0402

1

2

1

C1669

1UF

2

C1656

1UF

10% 10V X6S-CERM 0402

1

2

1

C1670

2

C1657

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

1

2

1

C1671

2

C1658

1UF

10% 10V X6S-CERM 0402

1UF

10% 10V X6S-CERM 0402

=PP1V8_S0_CPU_VCCPLL

8

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

CPU VCCPLL DECOUPLING

R1600

0

1 2

5% 1/16W MF-LF

402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

1

2

C1685

1UF

10% 10V X6S-CERM 0402

1

C1686

1UF

10% 10V

2

X6S-CERM 0402

CPU VCCPLL Low pass filter

=PP1V8_S0_CPU_VCCPLL_R

PLACE_NEAR=U1000.AK61:5MM CRITICAL

1

C1687

220UF

20%

(Z = 1.2mm, place on short side behind CPU)

2.5V

2

TANT B16

8

13

B

PLACEMENT_NOTE (C1672-C1681):

Place near U1000 on bottom side

1

C1672

10UF

20% 4V

2

X6S-CERM 0603

1

C1673

2

10UF

20% 4V X6S-CERM 0603

1

C1674

10UF

20% 4V

2

X6S-CERM 0603

1

C1675

2

10UF

20% 4V X6S-CERM 0603

1

C1676

10UF

20% 4V

2

X6S-CERM 0603

1

C1677

10UF

4V

2

20%

X6S-CERM 0603

1

C1678

2

10UF

20% 4V X6S-CERM 0603

1

C1679

2

10UF

20% 4V X6S-CERM 0603

1

C1680

10UF

20% 4V

2

X6S-CERM 0603

1

2

C1681

10UF

20% 4V X6S-CERM 0603

CRITICAL

1

C1682

330UF-6MOHM

20%

2.0V

23

A

POLY-TANT D15T-ECGLT-COMBO D15T-ECGLT-COMBO

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1601

0.010

1 2

1/4W

0603

1%

MF

=PP1V05_S0_CPU_VCCPQE

CRITICAL

1

C1683

330UF-6MOHM

20%

2.0V

23

POLY-TANT

1

C1684

1UF

10% 10V

2

X6S-CERM 0402

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

8

13

6 3

SYNC_MASTER=D2_SEAN

PAGE TITLE

CPU DECOUPLING-I

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

16 OF 132

SHEET

15 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

VAXG DECOUPLING

INTEL RECOMMENDATION: 2X 470UF 4MOHM, 2X 470UF 4MOHM (NOSTUFF), 6X 22UF 0805, 2X 22UF 0805 (NOSTUFF), 6X 10UF 0603, 2X 10UF 0603 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF) APPLE IMPLEMENTATION: 0X 470UF 4MOHM, 3X 330UF 9MOHM , 6X 22UF 0603, 2X 22UF 0603 (NOSTUFF), 6X 10UF 0402, 2X 10UF 0402 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)

=PPVCORE_S0_CPU_VCCAXG

8

13 14

D

PLACEMENT_NOTE (C1700-C1708):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1700

2

1UF

10% 10V X6S-CERM 0402

1

C1701

2

1UF

10% 10V X6S-CERM 0402

1

2

PLACEMENT_NOTE (C1718-C1723):

Place close to U1000 on bottom side

1

C1718

2

10UF

20% 4V X6S 0402

1

C1719

2

10UF

20% 4V X6S 0402

1

C1720

2

10UF

20% 4V X6S 0402

PLACEMENT_NOTE (C1726-C1731):

Place near inductors on bottom side.

1

C1726

2

22UF

20% 4V X6S 0603

1

C1727

2

22UF

20% 4V X6S 0603

1

2

PLACEMENT_NOTE (C1734-C1735):

C1702

1UF

10% 10V X6S-CERM 0402

C1728

22UF

20% 4V X6S 0603

1

2

1

C1721

10UF

2

1

2

C1703

1UF

10% 10V X6S-CERM 0402

20% 4V X6S 0402

C1729

22UF

20% 4V X6S 0603

1

C1704

2

1

C1722

2

1

2

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S 0402

C1730

22UF

20% 4V X6S 0603

1

C1705

2

1

C1723

2

1

2

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S 0402

C1731

22UF

20% 4V X6S 0603

1

2

1

C1724

2

C1706

1UF

10% 10V X6S-CERM 0402

NOSTUFF

10UF

20% 4V X6S 0402

NOSTUFF

1

C1732

22UF

20% 4V

2

X6S 0603

1

2

1

2

C1707

1UF

10% 10V X6S-CERM 0402

NOSTUFF

C1725

10UF

20% 4V X6S 0402

NOSTUFF

1

C1733

22UF

20% 4V

2

X6S 0603

1

C1708

2

1UF

10% 10V X6S-CERM 0402

NOSTUFF

1

C1709

1UF

2

10% 10V X6S-CERM 0402

NOSTUFF

1

C1710

1UF

10% 10V

2

X6S-CERM 0402

NOSTUFF

1

C1711

1UF

2

10% 10V X6S-CERM 0402

1

2

NOSTUFF

C1712

1UF

10% 10V X6S-CERM 0402

1

2

NOSTUFF

C1713

1UF

10% 10V X6S-CERM 0402

NOSTUFF

1

C1714

1UF

2

10% 10V X6S-CERM 0402

NOSTUFF

1

C1715

1UF

2

10% 10V X6S-CERM 0402

1

2

NOSTUFF

C1716

1UF

10% 10V X6S-CERM 0402

NOSTUFF

1

C1717

2

1UF

10% 10V X6S-CERM 0402

D

C

CRITICAL

1

C1734

330UF-6MOHM

20%

2.0V

23

POLY-TANT D15T

CRITICAL

1

C1735

330UF-6MOHM

20%

2.0V

23

POLY-TANT D15T

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402 Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

=PP1V5_S3_CPU_VCCDDR

8

11 14 27

B

PLACEMENT_NOTE (C1738-C1747):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1738

1UF

10% 10V

2

X6S-CERM 0402

Place close to U1000 on bottom side

1

C1748

10UF

20% 4V

2

X6S-CERM 0603

1

C1739

1UF

10% 10V

2

X6S-CERM 0402

1

C1749

10UF

20% 4V

2

X6S-CERM 0603

1

2

1

C1750

2

Place near inductors on bottom side

C1756

1

330UF-0.006OHM

20% 2V POLY

2

CASE-D2-SM

C1740

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S-CERM 0603

CRITICAL

1

C1737

330UF-6MOHM

20%

2.0V

23

POLY-TANT D15T

1

C1741

1UF

10% 10V

2

X6S-CERM 0402

1

C1751

10UF

20% 4V

2

X6S-CERM 0603

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

1

C1742

1UF

10% 10V

2

X6S-CERM 0402

1

C1752

10UF

20% 4V

2

X6S-CERM 0603

1

C1743

1UF

10% 10V

2

X6S-CERM 0402

1

C1753

10UF

20% 4V

2

X6S-CERM 0603

1

2

1

C1754

2

C1744

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S-CERM 0603

1

2

1

C1755

2

C1745

1UF

10% 10V X6S-CERM 0402

10UF

20% 4V X6S-CERM 0603

1

C1746

1UF

10% 10V

2

X6S-CERM 0402

1

C1747

2

1UF

10% 10V X6S-CERM 0402

=PPVCCSA_S0_CPU

8

13

CPU VCCSA DECOUPLING

Intel recommendation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402 Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

PLACEMENT_NOTE (C1758-C1762):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1758

1UF

10% 10V

2

X6S-CERM 0402

1

C1763

10UF

20% 4V

2

X6S-CERM 0603

CRITICAL

1

C1768

330UF-6MOHM

20%

2.0V

23

POLY-TANT D15T-ECGLT-COMBO

1

2

1

2

C1759

1UF

10% 10V X6S-CERM 0402

C1764

10UF

20% 4V X6S-CERM 0603

1

2

1

C1765

10UF

20% 4V

2

X6S-CERM 0603

C1760

1UF

10% 10V X6S-CERM 0402

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

1

2

1

C1766

10UF

20% 4V

2

X6S-CERM 0603

C1761

1UF

10% 10V X6S-CERM 0402

1

C1762

1UF

10% 10V

2

X6S-CERM 0402

1

C1767

10UF

20% 4V

2

X6S-CERM 0603

C

B

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1700

0.010

1 2

1/4W

0603

1%

MF

=PP1V5_S3_CPU_VCCDQ

1

2

C1757

1UF

10% 10V X6S-CERM 0402

8

13

A

6 3

SYNC_MASTER=D2_SEAN

PAGE TITLE

CPU DECOUPLING-II

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=03/05/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

17 OF 132

SHEET

16 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

SYSCLK_CLK32K_RTC

25 91

IN

RTC_RESET_L

17

PCH_SRTCRST_L

17

PCH_INTRUDER_L

17

PCH_INTVRMEN_L

D

VSel strap not functional (VCCVRM = 1.8V)

C

17

HDA_BIT_CLK_R

17 92

HDA_SYNC_R

17 92

PCH_SPKR

17

HDA_RST_R_L

17 92

HDA_SDIN0

53 92

IN

TP_HDA_SDIN1

7

TP_HDA_SDIN2

7

TP_HDA_SDIN3

7

HDA_SDOUT_R

17 25 92

JTAG_ISP_TMS

20

OUT

ENET_MEDIA_SENSE_RDIV

17

IN

XDP_PCH_TCK

24

IN

XDP_PCH_TMS

24

IN

XDP_PCH_TDI

24

IN

XDP_PCH_TDO

24

OUT

SPI_CLK_R

43 92

OUT

SPI_CS0_R_L

43 92

OUT

TP_SPI_CS1_L

SPI_MOSI_R

43 92

OUT

SPI_MISO

43 92

IN

=PPVRTC_G3_PCH

1

330K

1/20W

1

R1801

1M

5%

5% 1/20W

MF

201

2

R1800

B

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

R1877 R1878

R1834 R1833

R1842 R1869 R1844 R1845 R1847

GPU:1P

R1814 R1815

R1843 R1846 R1848 R1853 R1854 R1855

R1879

A

A20

OMIT_TABLE

RTCX1

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34 G34

C34

A34

A36

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201 201

MF

201

MF MF

201

MF

201

MF

201

MF

201

MF

RTCX2

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

(IPD-PLTRST#)

HDA_RST*

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0*

SPI_CS1*

SPI_MOSI

SPI_MISO

17

PCH_SPKR PCH_SATALED_L

DP_AUXCH_ISOL SATARDRVR_EN

FW_CLKREQ_L AP_CLKREQ_L EXCARD_CLKREQ_L JTAG_DPMUXUC_TRST_L ENET_CLKREQ_L PEG_CLKREQ_L TBT_CLKREQ_L

SSD_CLKREQ_L PEGCLKRQA_L_GPIO47

SMBUS_PCH_ALERT_L USB_EXTB_SEL_XHCI USB_EXTD_SEL_XHCI

ENET_MEDIA_SENSE_RDIV

NC

8

18 21

1

20K

5%

MF

201

2

1

2

8

18 19 20

8

18 19 20 25 37

5% MF

5%

5% 5%

5%

5% 5%

5%

5% MF 5%

5%

5% 5%

5%

5% 5%

5%

1

R1803

20K

5% 1/20W MF 201

2

RTC_RESET_L PCH_SRTCRST_L PCH_INTRUDER_L PCH_INTVRMEN_L

1

C1803

1UF

10% 10V

2

X5R 402

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

1/20W 1/20W

1/20W

R1802

1/20W

C1802

1UF

10% 10V X5R 402

4.7K

1 2

4.7K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

2 1

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V. If HDA = S0, must also ensure that signal cannot be high in S3.

PANTHERPOINT

(IPD-BOOT)

(IPD) (IPD) (IPD) (IPD)

(IPD-BOOT)

(IPD)

(IPU)

(IPD-BOOT)

(IPU)

U1800

MOBILE

FCBGA

(1 OF 10)

RTC

IHDA

JTAG

SPI

FWH4/LFRAME*

(IPU)

LDRQ1*/GPIO23

(IPU)

LPC

SATA

SATA3RCOMPO

SATA0GP/GPIO21 SATA1GP/GPIO19

(IPU)

LPC_AD_R<0>

17

LPC_AD_R<1>

17

LPC_AD_R<2>

17

LPC_AD_R<3>

17

LPC_FRAME_R_L

17

HDA_BIT_CLK_R

17 92

HDA_SYNC_R

17 92

HDA_RST_R_L

17 92

HDA_SDOUT_R

17 25 92

17

24 25

24

17

17 34

17

7

9

17 37

17 39

17

17 26

17

LDRQ0*

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATALED*

C38 A38

B37

C37

D36

E36

K36

V5

AM3 AM1

AP7

AP5

AM10 AM8

AP11 AP10

AD7

AD5

AH5 AH4

AB8

AB10

AF3 AF1

Y7

Y5 AD3

AD1

Y3

Y1 AB3

AB1

Y11

Y10

AB12

AB13 AH1

P3

V14 P1

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

(IPU)

SATAICOMPO SATAICOMPI

SATA3COMPI SATA3RBIAS

PLACE_NEAR=U1800.N34:1.27mm

PLACE_NEAR=U1800.L34:1.27mm

PLACE_NEAR=U1800.K34:1.27mm

PLACE_NEAR=U1800.A36:1.27mm

17 38

17

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

LPC_FRAME_R_L

TP_LPC_DREQ0_L TBT_PWR_EN_PCH

LPC_SERIRQ

SATA_HDD_D2R_N SATA_HDD_D2R_P SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P

SATA_ODD_D2R_N SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

TP_SATA_C_D2RN TP_SATA_C_D2RP TP_SATA_C_R2D_CN TP_SATA_C_R2D_CP

TP_SATA_D_D2RN TP_SATA_D_D2RP TP_SATA_D_R2D_CN TP_SATA_D_R2D_CP

TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN TP_SATA_E_R2D_CP

TP_SATA_F_D2RN TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP

PCH_SATAICOMP

91

PCH_SATA3COMP

91

PCH_SATA3RBIAS

PCH_SATALED_L

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

33

R1860 R1861 R1862 R1863 R1864

R1810 R1811 R1812 R1813

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

17

7

25

OUT

39 91

IN

39 91

IN

39 91

OUT

39 91

OUT

9

91

IN

9

91

IN

9

91

OUT

9

91

OUT

7

17

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

ITPCPU_CLK100M_N

11 89

ITPCPU_CLK100M_P

11 89

=PP3V3_S0_PCH

1

R1820

10K

5% 1/20W MF 201

2

7

41 43

BI

=PP1V05_S0_PCH_VCCIO_SATA

PLACE_NEAR=U1800.Y11:2.54mm

1

R1830

37.4

1% 1/20W MF 201

2

=PP1V05_S0_PCH

1

R1831

49.9

1% 1/20W MF 201

2

PLACE_NEAR=U1800.AB12:2.54mm

PLACE_NEAR=U1800.AH1:2.54mm

1

R1832

750

1%

24

OUT OUT

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

1/20W

24

MF 201

2

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

8

NO STUFF

R1841

0

1 2

5%

1/20W

MF

201

23

8

21 23

8

23

7

41 43 82 92

BI

7

41 43 82 92

BI

7

41 43 82 92

BI

7

41 43 82 92

BI

7

41 43 82 92

OUT

53 92

OUT

53 92

OUT

53 92

OUT

53 92

OUT

NO STUFF

R1840

0

1 2

5%

1/20W

MF

201

7

38 92

IN

7

38 92

IN

7

38 92

OUT

7

38 92

OUT

34 92

IN

34 92

IN

34 92

OUT

34 92

OUT

9

IN

9

IN

9

OUT

9

OUT

9

IN

9

IN

9

OUT

9

OUT

7

38 92

OUT

7

38 92

OUT

17 39

IN

9

92

9

92

17

34 92

OUT

34 92

OUT

17 34

IN

9

92

OUT

9

92

OUT

17

IN

7

17

OUT

39 92

OUT

39 92

OUT

7

17 38

IN

7

17

71 92

OUT

71 92

OUT

9

17

IN

35 92

OUT

35 92

OUT

17 37

IN

24 89

PCIE_ENET_D2R_N PCIE_ENET_D2R_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_P

PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

PCIE_FW_D2R_N PCIE_FW_D2R_P PCIE_FW_R2D_C_N PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P

TP_PCIE_5_D2RN TP_PCIE_5_D2RP TP_PCIE_5_R2D_CN TP_PCIE_5_R2D_CP

TP_PCIE_6_D2RN TP_PCIE_6_D2RP TP_PCIE_6_R2D_CN TP_PCIE_6_R2D_CP

TP_PCIE_7_D2RN TP_PCIE_7_D2RP TP_PCIE_7_R2D_CN TP_PCIE_7_R2D_CP

TP_PCIE_8_D2RN TP_PCIE_8_D2RP TP_PCIE_8_R2D_CN TP_PCIE_8_R2D_CP

PCIE_CLK100M_ENET_N PCIE_CLK100M_ENET_P

SSD_CLKREQ_L

PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P

FW_CLKREQ_L

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

AP_CLKREQ_L

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

EXCARD_CLKREQ_L

TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P

JTAG_DPMUXUC_TRST_L

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

ENET_CLKREQ_L

TP_PCIE_CLK100M_PEBN TP_PCIE_CLK100M_PEBP

PEGCLKRQB_L_GPIO56

PEG_CLK100M_N PEG_CLK100M_P

PEG_CLKREQ_L

PCIE_CLK100M_TBT_N PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

ITPXDP_CLK100M_N ITPXDP_CLK100M_P

25 91

Unused clock terminations for FCIM Mode

10K 10K

10K

10K 10K

R1880

10K

GPU:2P

1 2

PCH_CLK96M_DOT_P

17 92

PCH_CLK96M_DOT_N

17 92

PCH_CLK100M_SATA_P

17 92

PCH_CLK100M_SATA_N

5%

1/20W

PEGCLKRQB_L_GPIO56PEGCLKRQB_L_GPIO56

201

MF

17 17

17 92

PCIE_CLK100M_PCH_P

17 92

PCIE_CLK100M_PCH_N

17 92

PCH_CLK14P3M_REFCLK

17 92

PCH_CLKIN_GNDP1

17

PCH_CLKIN_GNDN1

17

R1891 R1892

R1893 R1894

R1895 R1896

R1897

R1870 R1871

6 3

BG34 BJ34

AV32

AU32

BE34 BF34

BB32 AY32

BG36

BJ36

AV34 AU34

BF36

BE36

AY34 BB34

BG37

BH37 AY36

BB36

BJ38

BG38 AU36

AV36

BG40 BJ40

AY40

BB40

BE38 BC38

AW38

AY38

Y40

Y39

J2

AB49 AB47

M1

AA48 AA47

V10

Y37

Y36

A8

Y43

Y45

L12

V45

V46

L14

AB42

AB40

E6

V40

V42

T13

V38 V37

K12

AK14 AK13

SYSCLK_CLK25M_SB

IN

1 2 1 2

1 2

1 2 1 2

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

Controlled by PCIECLKRQ5#

PCIECLKRQ0*/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1*/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4*/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

(IPU-RSMRST#)

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ*/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE7N CLKOUT_PCIE7P

PCIECLKRQ7*/GPIO46

(IPU-RSMRST#)

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

1/20W

5%

1/20W

MF

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(2 OF 10)

SMBUS

SML1ALERT*/PCHHOT*/GPIO74

PCI-E*

C-LINK

CLOCKS

FLEX

CLOCKS

R1872

604

1 2

1% 1/16W MF-LF

402

201

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

(IPU/IPD)

CL_CLK1

CL_DATA1

CL_RST1*

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

(IPD-PWROK)

CLKOUTFLEX1/GPIO65

(IPD-PWROK)

CLKOUTFLEX2/GPIO66

(IPD-PWROK)

CLKOUTFLEX3/GPIO67

(IPD-PWROK)

SYSCLK_CLK25M_SB_R

1.8V -> 1.1V

1

R1873

1K

1% 1/20W MF 201

2

SYNC_MASTER=D2_KEPLER

PAGE TITLE

E12

H14 C9

A12

C8

G12

C13

E14 M16

M7

T11

P10

M10

AB37 AB38

AV22

AU22

AM12 AM13

BF18

BE18

BJ30 BG30

G24

E24

AK7 AK5

K45

H45

33MHz clocks must be matched within 5"

V47

V49

Y47

K43

F47

H47

K49

SMBUS_PCH_ALERT_L

SMBUS_PCH_CLK SMBUS_PCH_DATA

USB_EXTB_SEL_XHCI

SML_PCH_0_CLK SML_PCH_0_DATA

USB_EXTD_SEL_XHCI

SML_PCH_1_CLK SML_PCH_1_DATA

TP_CLINK_CLK

TP_CLINK_DATA

TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47

TP_PCIE_CLK100M_PEGAN TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPN TP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

PCH_CLKIN_GNDN1 PCH_CLKIN_GNDP1

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_SB_R

NC

=PP1V05_S0_PCH_VCCDIFFCLK

8

21 23

PLACE_NEAR=U1800.Y47:2.54mm

PCH_XCLK_RCOMP

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

17 91

PCH SATA/PCIe/CLK/LPC/SPI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

17

44 92

OUT

44 92

BI

17 26

OUT

44 92

OUT

44 92

BI

17

OUT

44 92

OUT

44 92

BI

7

17

11 89

OUT

11 89

OUT

9

OUT

9

OUT

17 92

IN

17 92

IN

17

17 92

IN

17 92

IN

17 92

IN

17 92

IN

17 92

IN

25 92

IN

17 91

1

R1890

90.9

1%

1/20W

MF

201

2

9

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

18 OF 132

SHEET

17 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

B

R1905

10K

1/20W

=PP3V3_SUS_PCH_GPIO =PP1V05_S0_PCH_VCCIO_PCIE

PLACE_NEAR=U1800.BJ24:12.7mm

1

R1900

49.9

5%

1% 1/20W

MF

MF 201

201

2

PLACE_NEAR=U1800.BH21:2.54mm

1

R1920

750

1% 1/20W MF 201

2

DMI_N2S_N<0>

10 89

IN

DMI_N2S_N<1>

10 89

IN

DMI_N2S_N<2>

10 89

IN

DMI_N2S_N<3>

10 89

IN

DMI_N2S_P<0>

10 89

IN

DMI_N2S_P<1>

10 89

IN

DMI_N2S_P<2>

10 89

IN

DMI_N2S_P<3>

10 89

IN

DMI_S2N_N<0>

10 89

OUT

DMI_S2N_N<1>

10 89

OUT

DMI_S2N_N<2>

10 89

OUT

DMI_S2N_N<3>

10 89

OUT

DMI_S2N_P<0>

10 89

OUT

DMI_S2N_P<1>

10 89

OUT

DMI_S2N_P<2>

10 89

OUT

DMI_S2N_P<3>

10 89

OUT

PCH_DMI_COMP

PCH_DMI2RBIAS

PCH_SUSACK_L

18

PM_SYSRST_L

25 41

IN

PM_PCH_SYS_PWROK

24 41 70

IN

PM_PCH_PWROK

25 70

IN

PM_PCH_APWROK

70

IN

PM_MEM_PWRGD

11 27 89

OUT

PM_RSMRST_L

70

IN

PCH_SUSWARN_L

18

PM_PWRBTN_L

18 24 41

IN

SMC_ADAPTER_EN

41 42 70

IN

PM_BATLOW_L

42

IN

PCH_RI_L

=PP3V3_SUS_PCH_GPIO

8

17 18 19 20

PCH_SUSWARN_L

18

8

R1983

10K

1/20W

17 18 19 20

1

5% MF

201

2

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK*

K3 B9

SYS_RESET*

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST*

K16

SUSWARN*/SUSPWRDNACK/GPIO30

E20

PWRBTN*

H20

ACPRESENT/GPIO31

(IPD-DeepS4/S5)

E10

BATLOW*/GPIO72

A10

RI*

R1986

0

12

PCH_SUSACK_L

5%

1/20W

MF

201

U1800

PANTHERPOINT

MOBILE

FCBGA

(3 OF 10)

DMI

(IPU)

MANAGEMENT

SYSTEM POWER

(IPU)

18

OMIT_TABLE

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0 FDI_FSYNC1

FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

PMSYNCH

SLP_LAN*/GPIO29

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12 BC10

AV14 BB10

A18

E22

N3

G8

N14

D10

H4

F4

G10 G16

AP14

K14

=FDI_DATA_N<0> =FDI_DATA_N<1> =FDI_DATA_N<2> =FDI_DATA_N<3> =FDI_DATA_N<4> =FDI_DATA_N<5> =FDI_DATA_N<6> =FDI_DATA_N<7>

=FDI_DATA_P<0> =FDI_DATA_P<1> =FDI_DATA_P<2> =FDI_DATA_P<3> =FDI_DATA_P<4> =FDI_DATA_P<5> =FDI_DATA_P<6> =FDI_DATA_P<7>

FDI_INT =FDI_FSYNC<0>

=FDI_FSYNC<1> =FDI_LSYNC<0>

=FDI_LSYNC<1>

PCH_DSWVRMEN PM_DSW_PWRGD PCIE_WAKE_L PM_CLKRUN_L LPC_PWRDWN_L PM_CLK32K_SUSCLK_R PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L TP_PM_SLP_A_L PM_SLP_SUS_L PM_SYNC MEM_VDD_SEL_1V5_L

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

10 89

OUT

9

OUT

9

OUT

9

OUT

9

OUT

7

IN

7

BI

7

OUT

42

OUT

18 41 70

OUT

7

OUT

7

OUT

18 70

OUT

11 89

OUT

18 64

OUT

18 34

18 41 43

25 41 43

18 27 34 38 40 41 70

18 27 38 41 70

PLACE_NEAR=U1800.AF37:2.54mm

=PPVRTC_G3_PCH

1

R1915

390K

5% 1/20W MF 201

2

41

IN

1

R1909

100K

5% 1/20W MF 201

2

R1950

2.37K

1/20W

8

17 21

OMIT_TABLE

LVDS_IG_BKL_ON

9

18

OUT

LVDS_IG_PANEL_PWR

9

18

OUT

LVDS_IG_BKL_PWM

7

OUT

LVDS_IG_DDC_CLK

9

OUT

LVDS_IG_DDC_DATA

9

OUT

TP_LVDS_IG_CTRL_CLK

7

TP_LVDS_IG_CTRL_DATA

7

PCH_LVDS_IBG TP_PCH_LVDS_VBG

1

1% MF

201

2

7

LVDS_IG_A_CLK_N

9

91

OUT

LVDS_IG_A_CLK_P

9

91

OUT

LVDS_IG_A_DATA_N<0>

9

91

OUT

LVDS_IG_A_DATA_N<1>

9

91

OUT

LVDS_IG_A_DATA_N<2>

9

91

OUT

LVDS_IG_A_DATA_N<3>

9

91

OUT

LVDS_IG_A_DATA_P<0>

9

91

OUT

LVDS_IG_A_DATA_P<1>

9

91

OUT

LVDS_IG_A_DATA_P<2>

9

91

OUT

LVDS_IG_A_DATA_P<3>

9

91

OUT

LVDS_IG_B_CLK_N

7

OUT

LVDS_IG_B_CLK_P

7

OUT

LVDS_IG_B_DATA_N<0>

9

91

OUT

LVDS_IG_B_DATA_N<1>

9

91

OUT

LVDS_IG_B_DATA_N<2>

9

91

OUT

LVDS_IG_B_DATA_N<3>

9

OUT

LVDS_IG_B_DATA_P<0>

9

91

OUT

LVDS_IG_B_DATA_P<1>

9

91

OUT

LVDS_IG_B_DATA_P<2>

9

91

OUT

LVDS_IG_B_DATA_P<3>

9

OUT

TP_CRT_IG_BLUE

7

TP_CRT_IG_GREEN

7

TP_CRT_IG_RED

7

TP_CRT_IG_DDC_CLK

7

TP_CRT_IG_DDC_DATA

7

TP_CRT_IG_HSYNC

7

TP_CRT_IG_VSYNC

7

PCH_DAC_IREF

PLACE_NEAR=U1800.T43:2.54mm

1

R1951

1K

5% 1/20W MF 201

2

J47 M45

P45

T40 K47

T45 P39

AF37 AF36

AE48 AE47

AK39 AK40

AN48 AM47 AK47 AJ48

AN47 AM49 AK49 AJ47

AF40 AF39

AH45 AH47 AF49 AF45

AH43 AH49 AF47 AF43

N48 P49 T49

T39 M40

M47 M49

T43 T42

L_BKLTEN L_VDD_EN

L_BKLTCTL

L_DDC_CLK L_DDC_DATA

(IPD-PLTRST#) L_CTRL_CLK L_CTRL_DATA

LVD_IBG LVD_VBG

LVD_VREFH LVD_VREFL

LVDSA_CLK* LVDSA_CLK

LVDSA_DATA0* LVDSA_DATA1* LVDSA_DATA2* LVDSA_DATA3*

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK* LVDSB_CLK

LVDSB_DATA0* LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3*

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

U1800

PANTHERPOINT

MOBILE

FCBGA

(4 OF 10)

LVDS

DIGITAL DISPLAY INTERFACE

CRT

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

(IPD-PLTRST#)

DDPB_AUXN DDPB_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPC_AUXN DDPC_AUXP

DDPD_CTRLCLK

DDPD_CTRLDATA

(IPD-PLTRST#)

DDPD_AUXN DDPD_AUXP

(IPD) (IPD)

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

TP_SDVO_TVCLKINN TP_SDVO_TVCLKINP

TP_SDVO_STALLN TP_SDVO_STALLP

TP_SDVO_INTN TP_SDVO_INTP

DPA_IG_DDC_CLK DPA_IG_DDC_DATA

DPA_IG_AUX_CH_N DPA_IG_AUX_CH_P DPA_IG_HPD

TP_DP_IG_B_MLN<0> TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1> TP_DP_IG_B_MLN<2> TP_DP_IG_B_MLP<2> TP_DP_IG_B_MLN<3> TP_DP_IG_B_MLP<3>

DPB_IG_DDC_CLK DPB_IG_DDC_DATA

DPB_IG_AUX_CH_N DPB_IG_AUX_CH_P DPB_IG_HPD

TP_DP_IG_C_MLN<0> TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1> TP_DP_IG_C_MLP<1> TP_DP_IG_C_MLN<2> TP_DP_IG_C_MLP<2> TP_DP_IG_C_MLN<3> TP_DP_IG_C_MLP<3>

TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXN TP_DP_IG_D_AUXP TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0> TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1> TP_DP_IG_D_MLP<1> TP_DP_IG_D_MLN<2> TP_DP_IG_D_MLP<2> TP_DP_IG_D_MLN<3> TP_DP_IG_D_MLP<3>

7

83

83 95

9

83

83 95

9

7

D

82

C

B

=PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO =PP3V3_S5_PCH

R1985 R1991

A

R1982 R1925

R1924 R1921 R1922 R1923

R1981 R1984

8.2K 10K

100K 100K 100K 100K

100K 100K

1 2

2 1 2 1 2 1 2 1

2 1 2 1

8

17 18 19 20

8

17 19 20 25 37

8

5%1K1/20W

1/20W

5%

1/20W

5%1K1/20W

5%

1/20W 1/20W 1/20W 1/20W

5%

1/20W

5% MF

1/20W

MF

MF MF5% MF5% MF

MF5%

PM_PWRBTN_L

201

PM_CLKRUN_L

201

MEM_VDD_SEL_1V5_L

201

PCIE_WAKE_L

201

MAKE_BASE=TRUE

PM_SLP_S3_L

201

PM_SLP_S4_L

201

PM_SLP_S5_L

201

PM_SLP_SUS_L

201

LVDS_IG_BKL_ON

201

LVDS_IG_PANEL_PWR

201

18 24 41

7

18 41 43

18 64

7

18 34

7

18 27 38 41 70

7

18 27 34 38 40 41 70

18 41 70

18 70

9

18

9

18

NOSTUFF

R1999

0

5%

1/20W

MF

201

12

=TBT_WAKE_L

35 42

IN

6 3

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCH DMI/FDI/PM/Graphics

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-9589

4.18.0

19 OF 132

18 OF 99

SIZE

A

D

8 7 6 5 4 3

12

BG26

NC NC NC NC NC NC NC NC NC NC

D

TP_PCH_TP23

NC NC NC NC NC NC NC NC NC NC

NC NC

NC

USB3_EXTA_RX_N

40 91

IN

USB3_EXTB_RX_N

7

38 91

IN

USB3_EXTC_RX_N

9

91

IN

USB3_EXTD_RX_N

9

C

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

R2010 R2011 R2012 R2013

B

R2054

=PP3V3_SUS_PCH_GPIO =PP3V3_S3_PCH_GPIO =PP3V3_S0_PCH_GPIO

R2016 R2017 R2018

R2030

R2014 R2031

A

R2033

R2069 R2060

R2061 R2062 R2068

R2067

10K 10K 10K

10K

10K 10K

10K

10K 10K 10K 10K

10K

1 2

NO STUFF

1 2

NO STUFF

1 2

1 2 1 2

2 1

8

17 18 20 25

8

25

8

17 18 19 20 25 37

JTAG_GMUX_TMS

MF

5%

1/20W 1/20W

5%

1/20W

5%

1/20W

Redundant to pull-up on audio page

5%

1/20W

5%

1/20W

Redundant to pull-up on audio page

5%

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

201

BLC_I2C_MUX_SEL

201

MF5%

USE_HDD_OOB_L

MF

201

BLC_GPIO

MF

201

AUD_IP_PERIPHERAL_DET

MF

201

TBT_PWR_REQ_L

MF

201

AUD_I2C_INT_L

MF

201

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

201

MF

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

MF

201

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

201

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

MF

201

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

201

MF

AP_PWR_EN

MF

201

10K 10K 10K 10K

10K

1 2

1 2 1 2

NO STUFF

2 1

19

19 59

19 35

19 58

24 34 70

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

19 24

IN

40 91

IN

7

38 91

IN

9

91

IN

9

IN

40 91

OUT

38 91

OUT

9

91

OUT

9

OUT

40 91

OUT

38 91

OUT

9

91

OUT

9

OUT

MF

201

MF

201

MF

201

MF

201

19

OUT

19

OUT

19

OUT

MF

201

19

IN

19 59

IN

19 35

IN

19 58

IN

7

25 27

OUT

25 92

OUT

25

OUT

7

25

OUT

USB3_EXTA_RX_P USB3_EXTB_RX_P USB3_EXTC_RX_P USB3_EXTD_RX_P

USB3_EXTA_TX_N USB3_EXTB_TX_N USB3_EXTC_TX_N USB3_EXTD_TX_N

USB3_EXTA_TX_P USB3_EXTB_TX_P USB3_EXTC_TX_P USB3_EXTD_TX_P

PCI_INTA_L PCI_INTB_L PCI_INTC_L PCI_INTD_L

JTAG_GMUX_TMS BLC_I2C_MUX_SEL USE_HDD_OOB_L

TP_PCH_STRP_BBS1 TP_PCH_STRP_ESI_L PCH_STRP_TOPBLK_SWP_L

BLC_GPIO AUD_IP_PERIPHERAL_DET TBT_PWR_REQ_L AUD_I2C_INT_L

TP_PCI_PME_L

PLT_RESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R TP_PCI_CLK33M_OUT2 TP_PCI_CLK33M_OUT3 PCH_CLK33M_PCIOUT

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3RN1

BC30

USB3RN2

BE32

USB3RN3

BJ32

USB3RN4

BC28

USB3RP1

BE30

USB3RP2

BF32

USB3RP3

BG32

USB3RP4

AV26

USB3TN1

BB26

USB3TN2

AU28

USB3TN3

AY30

USB3TN4

AU26

USB3TP1

AY26

USB3TP2

AV28

USB3TP3

AW30

USB3TP4

K40

PIRQA*

K38

PIRQB*

H38

PIRQC*

G38

PIRQD*

C46

REQ1*/GPIO50

C44

REQ2*/GPIO52

E40

REQ3*/GPIO54

D47

GNT1*/GPIO51

E42

GNT2*/GPIO53

F46

GNT3*/GPIO55

(IPU-PCIERST#)

G42

PIRQE*/GPIO2

G40

PIRQF*/GPIO3

C42

PIRQG*/GPIO4

D44

PIRQH*/GPIO5

K10

(IPU)

PME*

C6

PLTRST*

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

(IPD)

19 24 19 24

U1800

PANTHERPOINT

MOBILE

FCBGA

(5 OF 10)

USB

PCI

USBRBIAS*

OC0*/GPIO59 OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

6 3

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25

RSVD26 RSVD27

RSVD28 RSVD29

USBP0N USBP0P

USBP1N USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBP10N USBP10P

USBP11N USBP11P

USBP12N USBP12P

USBP13N USBP13P

(IPD)

USBRBIAS

AY7 AV7

AU3

BG4

AT10 BC8

AU2

AT4 AT3

AT1

AY3 AT5

AV3

AV1 BB1

BA3

BB5 BB3

BB7 BE8

BD4

BF6

AV5 AV10

AT8

AY5

BA2

AT12 BF3

C24 A24

C25

B25

C26

A26

K28

H28

E28

D28

C28 A28

C29

B29

N28 M28

L30

K30

G30

E30

C30 A30

L32

K32

G32 E32

C32

A32

C33

B33

A14

K20 B17

C16

L16 A16

D14

C14

NC NC NC NC

NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC

NC

USB_EXTA_N USB_EXTA_P

USB_EXTB_XHCI_N USB_EXTB_XHCI_P

USB_EXTC_N USB_EXTC_P

USB_EXTD_XHCI_N USB_EXTD_XHCI_P

TP_USB_4N TP_USB_4P

TP_USB_SDN TP_USB_SDP

TP_USB_WLANN TP_USB_WLANP

USB_HUB_UP_N USB_HUB_UP_P

USB_CAMERA_N USB_CAMERA_P

USB_EXTB_EHCI_N USB_EXTB_EHCI_P

USB_EXTD_EHCI_N USB_EXTD_EHCI_P

TP_USB_BT_HSN TP_USB_BT_HSP

TP_USB_12N TP_USB_12P

TP_USB_13N TP_USB_13P

PCH_USB_RBIAS

91

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L XDP_DB2_PCH_GPIO10_AP_PWR_EN XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

1K

R2020 R2021

1 2

1K

1 2

BI BI

5%

40 91

26 91

9

26 91

91

Ext A (XHCI/EHCI)

Ext B (XHCI)

Ext C (XHCI/EHCI)

Ext D (XHCI) (Mobiles: Trackpad?)

Unused

RSVD: SD

RSVD: WiFi

26 91

34 91

26 91

9

USB Hub (All LS/FS Devices)

Camera

Ext B (EHCI)

Ext D (EHCI)

RSVD: BT (HS)

Unused

IN IN IN IN IN IN

OUT

IN

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

MF

1/20W

201

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

201

MF5%

19 24

24

19 24

PLACE_NEAR=U1800.B33:2.54mm

1

R2070

22.6

1% 1/20W MF 201

2

19 24 19 24

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

PCH PCI/USB/TP/RSVD

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-9589

4.18.0

20 OF 132

19 OF 99

SIZE

D

C

B

A

D

OMIT_TABLE

8 7 6 5 4 3

BOM GROUP

RAMCFG_SLOT

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

12

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

Systems with chip-down memory should add pull-downs on another page and set straps per software.

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

RAMCFG3:H

R2172

D

XDP_FC1_PCH_GPIO0

20 24

IN

FW_PME_L

20

IN

DPMUX_UC_IRQ

20 82

IN

SMC_RUNTIME_SCI_L

20 41

IN

TP_PCH_GPIO8

WOL_EN

20

OUT

XDP_FC0_PCH_GPIO15

24

IN

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

24

OUT

LPCPLUS_GPIO

7

20 43

BI

ODD_PWR_EN_L

20

OUT

TBT_GO2SX_BIDIR

20 35

SMC_WAKE_SCI_L

20 41

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

24

0

37

OUT

TBT_SW_RESET_L

R2180

1 2

C

OUT

TBT_SW_RESET_R_L

20

1/20W

5%

201

MF

XDP_DC1_PCH_GPIO35_MXM_GOOD

24

OUT

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

20 24

OUT

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

24

OUT

JTAG_ISP_TDO

20

IN

JTAG_ISP_TDI

20

OUT

FW_PWR_EN_PCH

20 25

OUT

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

24

OUT

SPIROM_USE_MLB

7

20 43 52

BI

(TBT_CIO_PLUG_EVENT_ISOL)

T7

BMBUSY*/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

(IPU-RSMRST#)

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

(IPU)

SATA4GP/GPIO16

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

(IPU-DeepS4/S5)

GPIO28

(IPU-RSMRST#)

STP_PCI*/GPIO34

GPIO35

SATA2GP/GPIO36

(IPD-PLTRST#)

SATA3GP/GPIO37

(IPD-PLTRST#)

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49/TEMP_ALERT*

GPIO57

VSS_NCTF_0 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13

BD49

BE49

BF49

U2

D40

T5

E8

E16

P8

K1

K4

V8

M5

N2

M3

V13

V3

D6

A4

A44

A45 A46

A5 A6

B3

B47 BD1

BE1

BF1

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(6 OF 10)

NCTF

(IPD-PLTRST#?)

CPU/MISC

GPIO

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

A20GATE

PECI

(IPD)

RCIN*

PROCPWRGD

THRMTRIP*

INIT3_3V*

(IPU)

DF_TVS

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11 AH10

AK10

P37

BG2 BG48

BH3

BH47 BJ4

BJ44

BJ45 BJ46

BJ5 BJ6

C2

C48 D1

D49

E1 E49

F1

F49

42

NC

MLB_RAMCFG3

9

MLB_RAMCFG2

9

MLB_RAMCFG1

9

MLB_RAMCFG0

9

PCH_A20GATE

PCH_PECI

PCH_RCIN_L

PCH_PROCPWRGD

PM_THRMTRIP_L_R

PCH_INIT3V3_L

PCH_DF_TVS

NO STUFF

R2130

1/20W

20

1

1K

This has internal pull up and should not pulled low.

5%

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

MF

201

2

RAMCFG2:H RAMCFG1:H

1

R2173

10K

5%

5% 1/20W

MF

201

2

NO STUFF

43

390

0

1 2

R2170

R2140

R2156

R2174

CPU_PECI

1/20W

5%

201

MF

CPU_PWRGD

1/20W

5%

201

MF

PM_THRMTRIP_L

1/20W

5%

201

MF

1/20W

10K

RAMCFG0:H

1

R2175

10K

5%

5% 1/20W

MF

201

2

11 42 89

BI

11 24 89

OUT

11 42 89

ININ

R2178

1K

1/20W

201

=PP1V8_S0_PCH_VCC_DFTERM

1

R2179

2.2K

5% 1/20W MF 201

2

12

CPU_PROC_SEL_L

5%

DF_TVS:DMI & FDI Term Voltage

MF

Set to Vss when Low Set to Vcc when High

11 89

8

21 23

D

C

SIZE

B

A

D

B

JTAG Isolation due to glitch in and out of sleep

NOTE: TCK from PCH is Push-Pull CMOS NOTE: TMS/TDI from PCH is Open Drain NOTE: TDO from CR is Push-Pull CMOS

=PP3V3_S5_PCH_GPIO =PP3V3_SUS_PCH_GPIO =PP3V3_S0_PCH_GPIO

Stuff R2160 or R2574, not both

R2160 R2185 R2196 R2190

R2197 R2184

R2150 R2155

A

R2194 R2192 R2193

R2191 R2111

R2195 R2112 R2198

R2116

10K 10K 10K

100K

10K 10K

100K

10K

20K

100K

10K 10K

10K

NO STUFF

1 2

1 2 1 2

NO STUFF

1 2 1 2

1 2

1 2 1 2

1 2

2 1 2 1 2 1 2 1

2 1

8

17 18 19

8

17 18 19 20 25 37

1/20W

5%

1/20W

5%

1/20W

5%

Must stuff R2197 when R2180 NO STUFFed.

5%

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5% MF

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

XDP_FC1_PCH_GPIO0

MF5%

201

FW_PME_L

201

MF

SMC_RUNTIME_SCI_L

201

MF

LPCPLUS_GPIO

MF

201

TBT_SW_RESET_R_L

201

MF

FW_PWR_EN_PCH

201

MF

PCH_A20GATE

MF5%

201

PCH_RCIN_L

201

WOL_EN

201

MF

TBT_GO2SX_BIDIR

201

MF

SPIROM_USE_MLB

201

MF5%

SMC_WAKE_SCI_L

MF

201

DPMUX_UC_IRQ

201

AUD_IPHS_SWITCH_EN_PCH

201

MF

ODD_PWR_EN_L

201

MF

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

201

MF

ENET_LOW_PWR_PCH

201

MF

20 24

20

20 41

7

20 43

20

20 25

20

20 35

7

20 43 52

20 41

20 82

24 25

20

20 24

9

24 25

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

JTAG_ISP_TMS

17

IN

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

JTAG_ISP_TDI

20

IN

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

20

OUT

1

R2186

2

1

R2188

10K

5% 1/20W MF 201

2

1

R2199

10K

2

10K

5% 1/20W MF 201

CRITICAL

Q2160

SSM6N15AFE

SOT563

D

6

CRITICAL

Q2160

SSM6N15AFE

SOT563

D

3

CRITICAL

Q2162

SSM3K15FV

SOD-VESM-HF

D

3

=PP3V3_TBT_PCH_GPIO

2

S G

1

5

S G

4

=PP3V3_TBT_PCH_GPIO

1

GS

2

1

R2163

10K

5% 1/20W MF 201

2

JTAG_TBT_TMS

=PP3V3_TBT_PCH_GPIO

1

R2161

10K

5% 1/20W MF 201

2

JTAG_TBT_TDI

1

R2162

10K

5% 1/20W MF 201

2

JTAG_TBT_TDOJTAG_ISP_TDO

8

20

TBT_PWR_EN goes high for JTAG Programming

24

IN

35

OUT

8

20

35

OUT

8

20

35

IN

R2113

10K

1/20W

1

5%

MF

201

2

TBT_PWR_EN

25 35

IN

JTAG_ISP_TCK TBT_CIO_PLUG_EVENT

IN

1

2

6 3

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 37

R2166

10K

5% 1/20W MF 201

CRITICAL

1

A1

2

B1

5

A2

6

B2

8

VCC

U2100

SOT833

08

74LVC2G08GT

GND

4

1

C2113

0.1UF

10% 16V

2

X5R-CERM 0201

7

Y1

Y2

JTAG_TBT_TCK

3

TBT_CIO_PLUG_EVENT_ISOL Connects to PCH through current limiting 1K resistor R2574

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCH GPIO/MISC/NCTF

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

35

OUT

24 35

OUT

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

21 OF 132

SHEET

20 OF 99

124578

8 7 6 5 4 3

12

D

OMIT_TABLE

AD49

VCCACLK pin left as NC per DG

=PP3V3_S5_PCH_VCCDSW

8

23

NC

TP_PPVOUT_PCH_DCPSUSBYP PP3V3_S0_PCH_VCC3_3_CLK_F

23

VCCAPLLDMI2 pin left as NC per DG

=PP1V05_S0_PCH_VCCIO_CLK

8

21 23

AL24 left as NC per DG

=PP1V05_S0_PCH_VCCASW

8

21 23

NC

C

PLACE_NEAR=U1800.N16:2.54mm

C2210

B

C2222

PCH output, for decoupling only

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

0.1UF

20% 10V

2

CERM

402

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

0.1UF

PLACE_NEAR=U1800.V16:2.54mm

20% 10V

2

CERM

402

PPVOUT_G3_PCH_DCPRTC =PP1V8R1V5_S0_PCH_VCCVRM

8

21

PP1V05_S0_PCH_VCCADPLLA_F

23

PP1V05_S0_PCH_VCCADPLLB_F

23

=PP1V05_S0_PCH_VCCIO_CLK

8

21 23

=PP1V05_S0_PCH_VCCDIFFCLK

8

17 23

55mA Max, 5mA Idle

=PP1V05_S0_PCH_VCCSSC

8

23

PPVOUT_S0_PCH_DCPSST

=PP1V05_S0_PCH_V_PROC_IO

8

23

=PPVRTC_G3_PCH

8

17 18

C2231

PLACE_NEAR=U1800.A22:2.54mm

NC-ed per DG

1

1UF

10%

6.3V

2

CERM

402

NC NC

1

C2232

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U1800.A22:2.54mm

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3_5_CLK

BH23

VCCAPLLDMI2

AL29

VCCIO_14_PLLCLK

AL24

DCPSUS_3_CLK

AA19

VCCASW_1_CLK

AA21

VCCASW_2_CLK

AA24

VCCASW_3_CLK

AA26

VCCASW_4_CLK

AA27

VCCASW_5_CLK

AA29

VCCASW_6_CLK

AA31

VCCASW_7_CLK

AC26

VCCASW_8_CLK

AC27

VCCASW_9_CLK

AC29

VCCASW_10_CLK

AC31

VCCASW_11_CLK

AD29

VCCASW_12_CLK

AD31

VCCASW_13_CLK

W21

VCCASW_14_CLK

W23

VCCASW_15_CLK

W24

VCCASW_16_CLK

W26

VCCASW_17_CLK

W29

VCCASW_18_CLK

W31

VCCASW_19_CLK

W33

VCCASW_20_CLK

N16

DCPRTC

Y49

VCCVRM_4_CLK

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO_7_CLK

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS_1_CLK

V19

DCPSUS_2_CLK

BJ8

V_PROC_IO

A22

VCCRTC

1

C2233

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U1800.A22:2.54mm

U1800

PANTHERPOINT

MOBILE

FCBGA

(8 OF 10)

VCCSUS3_3_10_USB

USB

VCCSUS3_3_2_GPIO VCCSUS3_3_3_GPIO VCCSUS3_3_4_GPIO VCCSUS3_3_5_GPIO

CLK/MISC

PCI/GPIO/

VCCIO_6_PLLSATA3

SATAMISC

CPURTC

HDA

VCCIO_29_USB VCCIO_30_USB VCCIO_31_USB VCCIO_32_USB VCCIO_33_USB

VCCSUS3_3_7_USB VCCSUS3_3_8_USB VCCSUS3_3_9_USB

VCCSUS3_3_6_USB

VCCIO_34_PLLUSB

V5REF_SUS

DCPSUS_4_USB

VCCSUS3_3_1_USB

V5REF

VCC3_3_1_GPIO VCC3_3_8_GPIO

LPC

VCC3_3_4_GPIO

VCC3_3_2_SATA

VCCIO_5_PLLSATA

VCCIO_12_SATA3 VCCIO_13_SATA3

VCCAPLLSATA

VCCVRM_1_SATA

VCCIO_2_SATA VCCIO_3_SATA VCCIO_4_SATA

VCCASW_22_MISC VCCASW_23_MISC VCCASW_21_MISC

VCCSUSHDA

N26

=PP1V05_S0_PCH_VCCIO_USB

P26 P28 T27 T29

T23

=PP3V3_SUS_PCH_VCCSUS_USB

T24 V23 V24 P24

T26

=PP1V05_S0_PCH_VCCIO_PLLUSB

M26

=PP5V_SUS_PCH_V5REFSUS

AN23

AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14

AK1

AF11

AC16 AC17 AD17

T21 V21 T19

P32

NC-ed per DG

NC

=PP3V3_SUS_PCH_VCCSUS

=PP5V_S0_PCH_V5REF =PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCC3_3_SATA =PP1V05_S0_PCH_VCCIO_SATA

VCCAPLLSATA pin left as NC per DG

NC

=PP1V8R1V5_S0_PCH_VCCVRM =PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCASW

=PP3V3R1V5_S0_PCH_VCCSUSHDA

10 mA Max, 1mA Idle

8

23

8

23

8

23

8

23

8

23

8

23

8

23

8

17 21 23

8

21

8

17 21 23

8

21 23

8

23 25

=PP1V05_S0_PCH_VCC_CORE

8

23

1.44 A Max, 474mA Idle

=PP1V05_S0_PCH_VCCIO_PLLPCIE

8

TP_1V05_S0_PCH_VCCAPLLEXP =PP1V05_S0_PCH_VCCIO

8

23

=PP3V3_S0_PCH_VCC3_3_PCI

8

23

=PP1V8R1V5_S0_PCH_VCCVRM

8

21

VCCAFDIPLL pin left as NC per DG

=PP1V05_S0_PCH_VCCIO_PLLFDI

8

=PP1V05_S0_PCH_VCCDMI_FDI

8

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO_28_PLLPCIE

BJ22

VCCAPLLEXP

AN16

VCCIO_15_FDI

AN17

VCCIO_16_FDI

AN21

VCCIO_17_PCIE

AN26

VCCIO_18_PCIE

AN27

VCCIO_19_PCIE

AP21

VCCIO_20_PCIE

AP23

VCCIO_21_PCIE

AP24

VCCIO_22_PCIE

AP26

VCCIO_23_PCIE

AT24

VCCIO_24_PCIE

AN33

VCCIO_25_DP

AN34

VCCIO_26_DP

BH29

VCC3_3_3_PCIE

AP16

VCCVRM_2_FDI

BG6

NC

VCCAFDIPLL

AP17

VCCIO_27_PLLFDI

AU20

VCCDMI_2_FDI

OMIT_TABLE

U1800

PANTHERPOINT

MOBILE

FCBGA

(7 OF 10)

VCC CORE

LVDS

VCC3_3_6_HVCMOS

VCC3_3_7_HVCMOS

HVCMOS

VCCIO

DMI CRT

FDI

DFT/SPI

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

VCCVRM_3_DMI

VCCDMI_1_DMI

VCCCLKDMI

VCCDFTERM VCCDFTERM VCCDFTERM VCCDFTERM

VCCSPI

U48

PP3V3_S0_PCH_VCCA_DAC_F

U47

CKPLUS_WAIVE=PwrTerm2Gnd

AK36

=LVDS_VCCA

AK37

PP1V8_S0_PCH_VCCTX_LVDS_F

AM37 AM38 AP36 AP37

=PP3V3_S0_PCH_VCC3_3_HVCMOS

V33

V34

AT16

=PP1V8R1V5_S0_PCH_VCCVRM

AT20

=PP1V05_S0_PCH_VCC_DMI

AB36

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V8_S0_PCH_VCC_DFTERM

AG16 AG17 AJ16 AJ17

V1

=PP3V3_SUS_PCH_VCC_SPI

23

8

23

8

23

8

21

8

23

8

20 23

8

23

D

C

B

A

PAGE TITLE

PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

6 3

SYNC_DATE=03/19/2012SYNC_MASTER=D2_CLEAN

DRAWING NUMBER

051-9589

REVISION

BRANCH

PAGE

22 OF 132

SHEET

124578

4.18.0

21 OF 99

SIZE

A

D

8 7 6 5 4 3

B7

D3

D8

F3

VSS

PANTHERPOINT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

OMIT_TABLE

U1800

MOBILE

FCBGA

(10 OF 10)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS

VSS VSS VSS

VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8

BG29 N24 AJ3 AD47

B43 BE10 BG41

G14 H16

T36

BG22

BG24 C22

AP13

M14 AP3 AP1 BE16 BC16 BG28 BJ28

SYNC_MASTER=D2_KEPLER

PAGE TITLE

PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

H5

AA17

AA2

AA3 AA33 AA34 AB11 AB14 AB39

AB4

D

C

B

AB43

AC19

AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD40 AD42 AD43 AD45 AD46

AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38

AF42 AF46

AG19

AG31 AG48 AH11

AH36 AH39 AH40 AH42 AH46

AJ19 AJ21 AJ24 AJ33 AJ34 AK12

AB5

AB7

AC2

AD4

AD8

AE2

AE3

AF4

AF5

AF7

AF8

AG2

AH3

AH7

AK3

VSS

PANTHERPOINT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U1800

MOBILE

FCBGA

(9 OF 10)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV11 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AY12 AY22 AY28

A

OMIT_TABLE

AY42 AY46

BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38

BB46 BC14 BC18

BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46

BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28

BF30 BF38 BF40

BG17 BG21 BG33 BG44

BH11 BH15 BH17 BH19

BH27 BH31 BH33 BH35 BH39 BH43

AY4

AY8 B11 B15 B19 B23 B27 B31

B35

B39

F45

BB4

BC2

BD5

BD3

BF8

BG8

H10

BH7

D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42

E18 E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34

6 3

12

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

23 OF 132

SHEET

22 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

8

21

8

D

PLACE_NEAR=U1800.M26:2.54mm

8

C

8

B

8

A

8

17

=PP3V3_SUS_PCH_VCCSUS =PP5V_SUS_PCH

1 mA S0-S5

C2438

R2404

1/16W MF-LF

0.1UF

20% 10V

CERM

402

2

10

NC NC

5%

402

1

2

=PP1V8_S0_PCH_VCCTX_LVDS

PLACE_NEAR=U1800.AM37:2.54mm

=PP3V3_S0_PCH_VCCADAC

PLACE_NEAR=U1800.U48:2.54mm

=PP3V3_S0_PCH_VCC3_3_CLK

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

PCH V5REF_SUS Filter & Follower (PCH Reference for 5V Tolerance on USB)

4

D2400

NC

BAT54DW-X-G

SOT-363

3

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_SUS_PCH_V5REFSUS

NO STUFF

L2407

0.1UH

1 2

0805

NO STUFF

C2400

22UF

X5R-CERM-1

PLACE_NEAR=U1800.AM37:2.54mm

PLACE_NEAR=U1800.U48:2.54mm

10UH-0.58A-0.35OHM

PLACE_NEAR=U1800.AM37:2.54mm

R2450

0

1 2

5%

1/20W

MF

201

C2450

10UF

PLACE_NEAR=U1800.U48:2.54mm

R2451

1

1 2

5% 1/16W MF-LF

402

R2490

0

1 2

R2491

1 2

MIN_LINE_WIDTH=0.4 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=1.05V

MF-LF

402

0

MIN_LINE_WIDTH=0.4 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=1.05V

MF-LF

402

CRITICAL

L2406

1 2

1098AS-SM

<1 mA S0-S5

21

NOSTUFF

1

C2406

0.01UF

20%

6.3V 603

20%

6.3V X5R 603

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=3.3V

10% 16V

2

X7R-CERM 0402

1

C2451

0.1UF

10% 16V

2

X7R-CERM 0402

PP1V05_S0_PCH_VCCADPLLA_R

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

PP1V05_S0_PCH_VCCADPLLB_R

(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)

PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.05V

PLACE_NEAR=U1800.P34:2.54mm

NO STUFF

1

C2408

0.01UF

10% 16V

2

X7R-CERM 0402

PP3V3_S0_PCH_VCCA_DAC_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

1

C2455

0.01UF

10% 16V

2

X7R-CERM 0402

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.T38:2.54mm

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.BD47:2.54MM

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.BF47:2.54MM

PLACE_NEAR=U1800.AB36:2.54mm

1

2

CRITICAL

L2451

1 2

0603

C2453

10UF

CRITICAL

L2490

1 2

0603

CRITICAL

C2491

220UF

CRITICAL

L2491

1 2

0603

CRITICAL

C2493

220UF

R2415

0

1 2

5% 1/16W MF-LF

402

C2411

10UF

=PP3V3_S0_PCH

17

8

=PP5V_S0_PCH

8

25

1 mA

PP1V8_S0_PCH_VCCTX_LVDS_F

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.8V

R2401

0

5% 1/20W MF 201

PLACE_NEAR=U1800.AM37:2.54MM

1

20%

6.3V 2

X5R 603

1

20%

2.5V

2

TANT

B16

1

20%

2.5V

2

TANT

B16

1

20%

6.3V 2

X5R 603

R2405

100

1/16W MF-LF

C2439

1UF

10% 10V X5R 402

21

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=3.3V

1

C2454

1UF

10% 10V

2

X5R 402

PCH VCCADPLLA Filter (PCH DPLLA PWR)

PP1V05_S0_PCH_VCCADPLLA_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

NO STUFF

1

C2492

1UF

10%

6.3V

2

CERM 402

PCH VCCADPLLB Filter (PCH DPLLB PWR)

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

NO STUFF

1

C2494

1UF

10%

6.3V

2

CERM 402

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.05V

2

5%

402

1

2

PCH V5REF Filter & Follower (PCH Reference for 5V Tolerance on PCI)

1

52

D2400

NC

BAT54DW-X-G

SOT-363

6

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S0_PCH_V5REF

21

68 mA

21

69 mA

21

<1 mA

21

=PP3V3_S5_PCH_VCCDSW

8

21

=PP3V3_SUS_PCH_VCC_SPI

8

21

=PP3V3_SUS_PCH_VCCSUS_GPIO

8

21

PCH VCCSUS3_3 BYPASS (PCH SUSPEND USB 3.3V PWR)

=PP3V3_SUS_PCH_VCCSUS_USB

8

21

PLACE_NEAR=U1800.P24:2.54mm

C2499

0.1UF

PLACE_NEAR=U1800.T16:2.54mm

C2442

PLACE_NEAR=U1800.V1:2.54mm

C2476

PLACE_NEAR=U1800.P22:2.54mm

1

C2484

0.1UF

10% 16V

2

X7R-CERM 0402

PLACE_NEAR=U1800.V24:2.54mm

PCH VCCSUSHDA BYPASS

=PP3V3R1V5_S0_PCH_VCCSUSHDA

8

21 25

PLACE_NEAR=U1800.P32:2.54mm

=PP1V8_S0_PCH_VCC_DFTERM

8

20 21

PLACE_NEAR=U1800.AJ16:2.54mm

=PP1V05_S0_PCH_V_PROC_IO

8

21

C2416

PLACE_NEAR=U1800.BJ8:2.54mm

=PP1V05_S0_PCH_VCC_DMI

8

21

PLACE_NEAR=U1800.BJ8:2.54mm

PLACE_NEAR=U1800.AT20:2.54mm

20% 10V

CERM

402

1UF

10%

6.3V CERM

402

1UF

10%

6.3V CERM

402

4.7UF

6.3V

20% X5R

402

1

2

1

2

1

2

1

2

C2413

0.1UF

10% 16V X7R-CERM 0402

1

2

C2441

0.1UF

C2440

0.1UF

1

C2417

0.1UF

10% 16V

2

X7R-CERM 0402

C2419

CERM

1UF

6.3V CERM

=PP3V3_S0_PCH_VCC3_3_GPIO

8

21

PLACE_NEAR=U1800.T34:2.54mm

=PP3V3_S0_PCH_VCC3_3_HVCMOS

8

21

=PP3V3_S0_PCH_VCC3_3_PCI

8

21

=PP3V3_S0_PCH_VCC3_3_SATA

8

21

1

20% 10V

2

402

1

20% 10V

2

402

1

C2430

0.1UF

10% 16V

2

X7R-CERM 0402

1

10%

2

402

6 3

1

C2486

0.1UF

10% 25V

2

X5R 402

PLACE_NEAR=U1800.AA16:2.54mm

C2424

0.1UF

PLACE_NEAR=U1800.V33:2.54mm

PLACE_NEAR=U1800.BH29:2.54mm

PLACE_NEAR=U1800.AJ2:2.54mm

X7R-CERM

C2421

0.1UF

X7R-CERM

C2423

0.1UF

X7R-CERM

=PP1V05_S0_PCH_VCCIO

8

21

PLACE_NEAR=U1800.AN27:2.54mm

=PP1V05_S0_PCH_VCCASW

8

21

PLACE_NEAR=U1800.AC27:2.54mm

PCH VCCCORE BYPASS (PCH 1.05V CORE PWR)

=PP1V05_S0_PCH_VCC_CORE

8

21

1

C2485

0.1UF

10% 25V

2

X5R 402

1

10% 16V

2

0402

1

10% 16V

2

0402

1

10% 16V

2

0402

C2401

10UF

PLACE_NEAR=U1800.AN27:2.54mm

PCH VCCIO BYPASS

PCH VCC3_3 BYPASS (PCH PCI 3.3V PWR)

PLACE_NEAR=U1800.AN27:2.54mm

C2420

22UF

X5R-CERM-1

PLACE_NEAR=U1800.AC27:2.54mm

PLACE_NEAR=U1800.AG26:2.54mm

PLACE_NEAR=U1800.AD21:2.54mm

SYNC_MASTER=D2_CLEAN

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

=PP1V05_S0_PCH_VCCSSC

8

21

=PP1V05_S0_PCH_VCCDIFFCLK

8

17 21

=PP1V05_S0_PCH_VCCIO_CLK

8

21

=PP1V05_S0_PCH_VCCIO_SATA

8

17 21

PLACE_NEAR=U1800.AH13:2.54mm

PCH VCCIO BYPASS (PCH USB 1.05V PWR)

=PP1V05_S0_PCH_VCCIO_USB

8

21

1

C2429

6.3V

20% X5R

603

20%

603

1UF

10%

6.3V

2

CERM 402

PLACE_NEAR=U1800.AN27:2.54mm

1

C2428

22UF

20%

6.3V

2

X5R-CERM-1

603

PLACE_NEAR=U1800.AC27:2.54mm

C2460

10UF

20%

6.3V X5R 603

PLACE_NEAR=U1800.AG24:2.54mm

PCH DECOUPLING

Apple Inc.

R

PLACE_NEAR=U1800.AG33:2.54mm

PLACE_NEAR=U1800.AF34:2.54mm

PLACE_NEAR=U1800.AF17:2.54mm

1UF

10%

6.3V CERM 402

1UF

10%

6.3V CERM 402

1UF

10%

6.3V CERM 402

1UF

6.3V CERM

1

10%

2

402

1

2

1

2

1

2

C2444

PLACE_NEAR=U1800.AC17:2.54mm

PLACE_NEAR=U1800.P28:2.54mm

1

C2414

2

PLACE_NEAR=U1800.AN27:2.54mm

1

C2426

2

PLACE_NEAR=U1800.AC27:2.54mm

1

C2481

2

PLACE_NEAR=U1800.AJ27:2.54mm

1

C2475

1UF

10%

6.3V

2

CERM

402

1

C2434

1UF

10%

6.3V

2

CERM

402

1

C2469

1UF

10%

6.3V

2

CERM

402

1

C2452

1UF

10%

6.3V 2

CERM

402

1

C2446

1UF

10%

6.3V 2

CERM

402

1

C2407

1UF

10%

6.3V CERM 402

C2456

1UF

10%

6.3V CERM 402

C2482

1UF

10%

6.3V CERM 402

C2463

1UF

10%

6.3V

2

CERM 402

1

C2496

1UF

10%

6.3V

2

CERM 402

1

C2483

1UF

10%

6.3V

2

CERM 402

SYNC_DATE=03/19/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

24 OF 132

SHEET

23 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

=PPVCCIO_S0_XDP

8

24

=PP3V3_S0_XDP

8

XDP_CPU_PREQ_L

11 89

BI

XDP_CPU_PRDY_L

11 89

D

(R2560-R2563)

XDP_CPU:BPM

0

11 89

IN

11 89

IN

11 89

IN

11 89

IN

10 89

IN

10 89

IN

10 89

IN

10 89

IN

11 20 89

IN

18 24 41

OUT

10 24 89

OUT

18 41 70

OUT

XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>

CPU_PWRGD

PM_PWRBTN_L

CPU_CFG<0>

PM_PCH_SYS_PWROK

R2560 R2561 R2562 R2563

R2564 R2565 R2566 R2567

PLACE_NEAR=U1000.C60:2.54mm

PLACE_NEAR=U4900.P17:2.54mm

PLACE_NEAR=U1000.B57:2.54mm

R2500

R2502

R2501

R2504

1 2

0

1 2

0

1 2

0

1 2

(R2564-R2567)

XDP_CPU:CFG

0

1 2

0

1 2

0

1 2

0

1 2

XDP

1K

1 2

XDP

0

1 2

XDP

1K

1 2

XDP

330

1 2

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

1/20W

5%

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

201

MF

C

(R2520-R2537)

XDP SIGNALS

R2584

R2585

R2520 R2521 R2522 R2523

R2524 R2525 R2526 R2527 R2528

R2529 R2530

R2531 R2532 R2533 R2534 R2535

R2536 R2537

1K

0

XDP_DA0_USB_EXTA_OC_L

24

OUT

XDP_DA1_USB_EXTB_OC_L

24

OUT

XDP_DA2_USB_EXTC_OC_L

24

OUT

XDP_DA3_USB_EXTD_OC_L

24

OUT

XDP_DB0_USB_EXTB_OC_EHCI_L

24

OUT

XDP_DB1_USB_EXTD_OC_EHCI_L

24

OUT

XDP_DB2_AP_PWR_EN

24

IN

XDP_DB3_SDCONN_STATE_CHANGE

24

OUT

XDP_FC0

24

OUT

XDP_FC1

24

OUT

XDP_DC0_ISOLATE_CPU_MEM_L

24

IN

XDP_DC1_MXM_GOOD

24

IN

XDP_DC2_DP_AUXCH_ISOL

24

IN

XDP_DC3_SATARDRVR_EN

24

IN

XDP_DD0_DP_GPU_TBT_SEL

24

IN

XDP_DD1_JTAG_ISP_TCK

24

IN

XDP_DD2_AUD_IPHS_SWITCH_EN

24

IN

XDP_DD3_ENET_LOW_PWR

24

IN

B

PCH/XDP Signal Isolation Notes:

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3 doc id 404081. Initially, stuffing both 33 and 0 ohms and validate whether it is functional in that state, else add BOM options.

- For isolated GPIOs:

- ’Output’ non-XDP signals require pulls.

- ’Output’ PCH/XDP signals require pulls.

R252x, R253x, R257x and R259x should be placed where signal path needs to split between route from PCH to J2550 and path to non-XDP signal destination.

ALL_SYS_PWRGD

41 70

IN

PM_PWRBTN_L

18 24 41

OUT

PLACE_NEAR=J2550.39:2.54mm

PLACE_NEAR=U4900.P17:2.54mm

33 33 33 33

33 33 33 33 33

33

33 33 33 33 33 33

33 33

XDP

1 2

XDP

1 2

XDP

1 2 1 2

1 2

1 2 1 2

1 2

1 2 1 2

1 2

1 2 1 2

1 2

5%

1/20W

5%

5% 5%

5% MF

5%

5% MF

5%

5% 5%

5%

5% 5%

1/20W

MF

1/20W

MF

1/20W

MF MF

1/20W

MF

1/20W

MF

1/20W

MF

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

1/20W

MF

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

1/20W

MF

1/20W

MF

201

MF

201

MF

A

PCH SIGNALS

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

201

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

201

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

201

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

201

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

201

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

201

201 201

201

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

201

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

201

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

201

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

201

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

201

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

201

24 44

17 24

IN

XDP_BPM_L<0>

11 89

IN

XDP_BPM_L<1>

11 89

IN

XDP_BPM_L<2>

11 89

IN

XDP_BPM_L<3>

11 89

IN

CPU_CFG<10>

10 89

IN

CPU_CFG<11>

10 89

IN

XDP_OBSDATA_B<0> XDP_OBSDATA_B<1>

XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>

XDP_CPU_PWRGD

89

XDP_CPU_PWRBTN_L

XDP_CPU_CFG<0> XDP_VR_READY

=SMBUS_XDP_SDA

24 44

BI

=SMBUS_XDP_SCL

24 44

IN

XDP_CPU_TCK

11 24 89

OUT

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_FC0_PCH_GPIO15

XDP_FC1_PCH_GPIO0

XDP_DC1_PCH_GPIO35_MXM_GOOD

TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>

XDP_DA0_USB_EXTA_OC_L

24

XDP_DA1_USB_EXTB_OC_L

24

XDP_DA2_USB_EXTC_OC_L

24

XDP_DA3_USB_EXTD_OC_L

24

TP_XDP_PCH_OBSFN_B<0> TP_XDP_PCH_OBSFN_B<1>

XDP_DB0_USB_EXTB_OC_EHCI_L

24

XDP_DB1_USB_EXTD_OC_EHCI_L

24

XDP_DB2_AP_PWR_EN

24

XDP_DB3_SDCONN_STATE_CHANGE

24

XDP_PCH_S5_PWRGD XDP_PCH_PWRBTN_L

TP_XDPPCH_HOOK2 TP_XDPPCH_HOOK3

=SMBUS_XDP_SDA

BI

=SMBUS_XDP_SCL

IN

XDP_PCH_TCK

OUT

NO STUFF

R2540

1/16W MF-LF

1

1K

5%

402

2

IN IN IN IN

IN IN

OUT

IN IN

IN

OUT OUT OUT OUT OUT OUT

OUT OUT

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2 HOOK3

TCK1 TCK0

C2500

19 24

X7R-CERM

19 24

19

NOTE: This is not the standard XDP pinout.

19 24

Use with 921-0133 Adapter Flex to

19 24

support chipset debug.

20

20 24

20

17 24

20

20 24

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2 HOOK3

TCK1 TCK0

C2580

X7R-CERM

CPU Micro2-XDP

CRITICAL XDP_CONN

J2500

DF40RC-60DP-0.4V

M-ST-SM

62

2

4

6

10

20

30

40

SDA SCL

50

NC

60

998-2516

0.1UF

0402

XDP

1

10% 16V

2

PCH Micro2-XDP

CRITICAL XDP_CONN

J2550

DF40RC-60DP-0.4V

M-ST-SM

62

2 4

6

10

20

30

40

SDA SCL

0.1UF

0402

XDP

1

10% 16V

2

50

NC

60

998-2516

NOTE: This is not the standard XDP pinout. Use with 921-0133 Adapter Flex to support chipset debug.

61

1

3

5 78

9 1112

1314

1516 1718

19

2122 2324

2526

2728 29

3132 3334

3536

3738 39

4142

4344 4546

4748

49 5152

5354 5556

5758

59

6364

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page TDO TRSTn TDI TMS XDP_PRESENT#

XDP

1

C2501

0.1UF

10% 16V

2

X7R-CERM 0402

=PP3V3_S5_XDP

61

1 3

5 78

9

1112 1314

1516

1718 19

2122

2324 2526

2728 29

3132

3334 3536

3738

39 4142

4344

4546 4748

49 5152

5354

5556 5758

59

6364

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page TDO TRSTn TDI TMS XDP_PRESENT#

XDP

1

C2581

0.1UF

10% 16V

2

X7R-CERM 0402

CPU_CFG<16> CPU_CFG<17>

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

XDP_CPU_CLK100M_P

89

XDP_CPU_CLK100M_N

89

XDP_CPURST_L XDP_DBRESET_L

XDP_CPU_TDO XDP_CPU_TRST_L XDP_CPU_TDI XDP_CPU_TMS

PCH SIGNALS

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

19 24

OUT

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

19 24

OUT

XDP_DB2_PCH_GPIO10_AP_PWR_EN

19 24

IN

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

19 24

OUT

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

17 24

IN

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

20 24

OUT

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

17 24

IN

XDP_FC1_PCH_GPIO0

OUT

8

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

20 24

OUT

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

20 24

OUT

XDP_FC0 XDP_FC1

XDP_DC0_ISOLATE_CPU_MEM_L XDP_DC1_MXM_GOOD

XDP_DC2_DP_AUXCH_ISOL XDP_DC3_SATARDRVR_EN

TP_XDP_PCH_OBSFN_D<0> TP_XDP_PCH_OBSFN_D<1>

XDP_DD0_DP_GPU_TBT_SEL XDP_DD1_JTAG_ISP_TCK

XDP_DD2_AUD_IPHS_SWITCH_EN XDP_DD3_ENET_LOW_PWR

TP_XDP_PCH_HOOK4 TP_XDP_PCH_HOOK5

XDPPCH_PLTRST_L XDP_DBRESET_L

XDP_PCH_TDO TP_XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS

IN IN

OUT

IN OUT OUT OUT

10 89

10 24 89

10 89

11 24 25 89

11 24 89

R2515

R2516

R2505

24

IN

OUT

IN

OUT OUT

25

11 24 25 89

17 24

XDP_CPU_TDO

11 24 89

XDP_CPU_TDI

11 24 89

XDP_CPU_TMS

11 24 89

XDP_CPU_TCK

11 24 89

XDP_CPU_TRST_L

11 24 89

XDP

0

1K

R2574

PLACE_NEAR=R1841.1:2.54mm

1 2

5%

XDP

PLACE_NEAR=R1840.1:2.54mm

1 2

5%

XDP

PLACE_NEAR=U1000.G3:2.54mm

1 2

5%

R2590 R2591 R2596 R2597

R2573

R2570 R2572

0

1K

R2575 R2576 R2577

XDP_PCH_TDO

17 24

XDP_PCH_TDI

17 24

XDP_PCH_TMS

17 24

XDP_PCH_TCK

17 24

ITPXDP_CLK100M_P

1/20W

MF

ITPXDP_CLK100M_N

1/20W

MF

CPU_RESET_L

1/20W

MF

1 2

5%01/20W

1 2

5% MF

1 2

5% MF0201

1 2

5%

1 2

5%

1 2

5%

1 2

0

1 2

0

1 2

0

1 2

201

1K series R on PCH Support Page

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

R2510

R2511

R2512

R2513

R2514

1/20W

5%

5% 5%

51

17 89

IN

17 89

IN

11 25

IN

Non-XDP Signals

201

MF 1/20W

1/20W

201

MF

201

MF

201

MF

MF5%

201

201MF5%

1/20W

MF

AUD_IPHS_SWITCH_EN_PCH

1/20W

MF

1/20W

MF

R2550

R2551

R2552

R2556

51

CPU & PCH XDP

Apple Inc.

R

6 3

=PPVCCIO_S0_XDP

8

24

XDP

PLACE_NEAR=J2500.52:2.54mm

2 1

XDP

2 1

XDP

2 1

XDP

2 1

XDP

2 1

SDCONN_STATE_CHANGE

1/20W

5%

PLACE_NEAR=U1000.K61:2.54mm

1/20W

5%

PLACE_NEAR=U1000.H59:2.54mm

1/20W

5%

PLACE_NEAR=U1000.J58:2.54mm

1/20W

5%

PLACE_NEAR=U1000.H63:2.54mm

1/20W

5%

USB_EXTA_OC_L USB_EXTB_OC_L

AP_PWR_EN

SATARDRVR_EN

ISOLATE_CPU_MEM_L

DP_AUXCH_ISOL

TBT_CIO_PLUG_EVENT_ISOL

JTAG_ISP_TCK

201

ENET_LOW_PWR_PCH

201

=PP1V05_SUS_PCH_JTAG

8

XDP

PLACE_NEAR=J2550.52:2.54mm

2 1

XDP

2 1

XDP

2 1

XDP

2 1

1/20W

5%

PLACE_NEAR=U1800.K5:2.54mm

1/20W

5%

PLACE_NEAR=U1800.H7:2.54mm

1/20W

5%

PLACE_NEAR=U1800.J3:2.54mm

1/20W

5%

201

MF

201

MF

201

MF

201

MF

201

MF

40

IN

7

38

IN

19 34 70

OUT

25

IN

17

OUT

27

OUT

17 25

OUT

20 20 24

IN

20 20 24

OUTOUT

20 25

OUT

9

20 25

OUT

201

MF

201

MF

201

MF

201

MF

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

25 OF 132

SHEET

24 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

GPIO Glitch Prevention

=PP3V3_S3_PCH_GPIO

8

19 25

CRITICAL

ENET_LOW_PWR_PCH

20 24

IN

PM_PCH_PWROK

18 25 70

IN

FW_PWR_EN_PCH

20

IN

D

=PP3V3_S3_PCH_GPIO

8

19 25

CRITICAL

TBT_PWR_EN_PCH

17

IN

LPC_PWRDWN_L

7

18 41 43

IN

AUD_IPHS_SWITCH_EN_PCH

20 24 39

IN

PM_PCH_PWROK

18 25 70

IN

U2650

1

A1

2

B1

5

A2

6

B2

U2652

1

A1

2

B1

5

A2

6

B2

8

VCC

SOT833

08

74LVC2G08GT

GND

4

8

VCC

SOT833

08

GND

74LVC2G08GT

4

C

1

C2650

0.1UF

20% 10V

2

CERM 402

7

Y1

Y2

Y1

Y2

ENET_LOW_PWR

3

FW_PWR_EN

1

C2652

0.1UF

20% 10V

2

CERM 402

7

TBT_PWR_EN

3

AUD_IPHS_SWITCH_EN

9 9

OUT

24

OUT

11 24 89

IN

SDCONN_STATE_CHANGE

9

OUT

20 35

OUT

58

OUT

SSM6N15FEAPE

SDCONN_STATE_CHANGE_SMC

42

OUT

PCH Reset Button

=PP3V3_S0_SB_PM

8

70

1

R2695

4.7K

XDP

R2696

XDP_DBRESET_L

1 2

5% 1/16W MF-LF

402

SDCONN_STATE_CHANGE ISOLATION

5

4

Y

U2630

470K

1/20W

3

1

5% MF

201

2

5

SDCONN_STATE_CHANGE_INV

S G

4

=PP3V3_S4_SMC

8

25 42

Q2640

SOT563

D

3

R2640

5% 1/16W MF-LF 402

2

0

OMIT

1

R2697

0

5% 1/16W MF-LF 402

2

SILK_PART=SYS RESET

CRITICAL

TC7SZ08AFEAPE

SOT665

2

A

1

SDCONN_STATE_CHANGE_RIO

B

SSM6N15FEAPE

PM_SYSRST_L

=PP3V3_S3_SDBUF

1

C2630

0.1UF

10%

6.3V

2

X5R 201

Q2640

SOT563

R2641

D

6

470K

1/20W

18 41

OUT

8

1

5% MF

201

2

S G

1

=PP3V3_S4_SMC

7

38

IN

8

25 42

=PP3V3_S0_RSTBUF

8

25

Platform Reset Connections

19 27

IN

PLT_RESET_L

MAKE_BASE=TRUE

C2680

0.1UF

20% 10V

CERM

402

Unbuffered

Buffered

1

U2680

2

1

2

CRITICAL

5

MC74VHC1G08

SC70-HF

3

4

MAKE_BASE=TRUE

1

2

PLT_RST_BUF_L

R2680

100K

5% 1/16W MF-LF 402

R2681

33

1 2

5% 1/16W MF-LF

402

R2671

0

1 2

5% 1/16W MF-LF

402

R2687

0

1 2

5% 1/16W MF-LF

402

R2686

0

1 2

5% 1/16W MF-LF

402

R2688

0

1 2

5% 1/16W MF-LF

402

LPC_RESET_L LPCPLUS_RESET_L

1/16W MF-LF

XDP

1/16W MF-LF

33

402

1K

402

MAKE_BASE=TRUE

SMC_LRESET_L

5%

PCA9557D_RESET_L

XDPPCH_PLTRST_L

5%

DPMUX_LRESET_L

0

SSD_RESET_L

5%

=ENET_RESET_L ENET_RESET_L

MAKE_BASE=TRUE

R2683

1 2

R2689

1 2

R2685

1 2

=TBT_RESET_L

Series R on Pg38, R3803

AP_RESET_L

R2693

0

1 2

5% 1/16W MF-LF

402

BKLT_PLT_RST_L

92

OUT

7

43

OUT

41

OUT

33

OUT

24

OUT

82

OUT

38

OUT

7

37

OUT

34

OUT

86

OUT

D

C

LPC 33MHz Clock Series Termination

LPC_CLK33M_SMC_R

19 92

IN

LPC_CLK33M_LPCPLUS_R

19

IN

LPC_CLK33M_DPMUX_UC_R

MAKE_BASE=TRUE

TP_PCI_CLK33M_OUT2

19

IN

PCH_CLK33M_PCIOUT

19

IN

B

System RTC Power Source & 32kHz / 25MHz Clock Generator

VDDIO_25M_A: SB power rail for XTAL circuit. VDDIO_25M_B: Ethernet power rail for XTAL circuit. VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

PLACE_NEAR=U1800.N52

PLACE_NEAR=U1800.P46

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

GreenClk 25MHz Power

Ethernet XTAL Power (Unused on 15" MBP) SB XTAL Power TBT XTAL Power

A

=PP3V3_S0_SYSCLK

8

=PPVDDIO_S0_SBCLK

8

=PPVDDIO_TBT_CLK

8

C2605

12PF

12

5%

50V

C0G-CERM

0402

C2606

12PF

1 2

5%

50V

C0G-CERM

0402

R2655

22

1 2

5%

1/20W

MF

R2656

PLACE_NEAR=U1800.P53

PLACE_NEAR=U1800.P48

201

R2657

22

1 2

5%

1/20W

MF

201

22

1 2

5%

1/20W

MF

201

R2659

22

1 2

5%

1/20W

MF

201

NO STUFF

R2607

1 2

NO STUFF

C2624

0.1UF

CERM

1

20% 10V

2

402

C2622

0.1UF

CERM

1

C2620

20% 10V

2

402

SYSCLK_CLK25M_X2

CRITICAL

13

Y2605

NC

24

SM-3.2X2.5MM

NC

25.000MHZ-12PF-20PPM

NOTE: 30 PPM crystal required

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

LPC_CLK33M_DPMUX_UC

PCH_CLK33M_PCIIN

8

0

5% 1/16W MF-LF

402

0.1UF

CERM

20% 10V

402

1

2

R2605

0

1 2

5% 1/16W MF-LF

402

1

2

SYSCLK_25M_B_GND

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

R2608

0

5% 1/16W MF-LF 402

SYSCLK_CLK25M_X1

=PPVBAT_G3_SYSCLK Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

=PP3V3_S5_SYSCLK Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5 No bypass necessary

OUT

C2602

1UF

10% 10V X5R

402-1

SYSCLK_CLK25M_X2_R

NO STUFF

1

R2606

1M

5% 1/16W MF-LF 402

2

6 3

41 92

7

82

17 92

43 92

1

2

5

VDD_25M

SLG3NB148A

CRITICAL

11

VDDIO_25M_A

CKPLUS_WAIVE=PwrTerm2Gnd

6

VDDIO_25M_B

14

VDDIO_25M_C

3

X2

4

X1

2

+V3.3A

U2600

TQFN

VDD_RTC_OUT

GND

71016

32KHZ_A

25MHZ_A 25MHZ_B 25MHZ_C

THRM

PAD

17

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 37

DP_AUXCH_ISOL

17 24

IN

13

VBAT and +V3.3A are internally ORed to

+3.42V

create VDD_RTC_OUT. +V3.3A should be first

available ~3.3V power to reduce VBAT draw.

12

SYSCLK_CLK32K_RTC

9

SYSCLK_CLK25M_SB

8

TP_SYSCLK_CLK25M_ENET

15

SYSCLK_CLK25M_TBT =PPVRTC_G3_OUT

1

For SB RTC Power

1

C2610

1UF

10%

6.3V

2

CERM 402

DP_AUXIO_EN INVERSION

R2630

10K

1 2

5%

1/20W

MF

201

D

Q2630

SOD-VESM-HF

SSM3K15FV

1

G S

NO STUFF

1

R2631

10K

5% 1/20W MF 201

2

8

3

2

OUT

DP_AUXIO_EN

C2639

0.1UF

10% 16V

X5R-CERM

0201

17 91

35 91

=PP3V3_S0_RSTBUF

8

25

Buffered CPU reset

CRITICAL

5

U2690

74LVC1G07

SC70

84 85

OUT

1

2

C2690

0.1UF

CERM

20% 10V

402

2

1

2

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

=PP3V3R1V5_S0_PCH_VCCSUSHDA

8

21 23

SPI_DESCRIPTOR_OVERRIDE_L

41 42

IN

NC

3

1

NC

SSM6N37FEAPE

4

PLT_RST_CPU_BUF_L

MAKE_BASE=TRUE

1

R2690

100K

5% 1/16W MF-LF 402

2

Q2620

SSM6N37FEAPE

SOT563

D

3

Q2620

SOT563

2

VTT pullup on CPU page

8

23

5

SPI_DESCRIPTOR_OVERRIDE_LS5V

S G

SPI_DESCRIPTOR_OVERRIDE

4

6

D

SG

1

SYNC_MASTER=D2_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

CPU_RESET_L

=PP5V_S0_PCH

1

R2620

100K

5% 1/20W MF 201

2

1

R2621

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

IPD = 9-50k

SYNC_DATE=01/13/2012

Chipset Support

Apple Inc.

R

OUT

17 92

OUT

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

26 OF 132

SHEET

25 OF 99

11 24

SIZE

B

A

D

124578

8 7 6 5 4 3

12

USBHUB2514B

USBHUB2513B

USBHUB2512B

NOSTUFF

1

R2723

10K

5% 1/16W MF-LF 402

2

49 96

BI

TO TP/KB

49 96

BI

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

TABLE_5_HEAD

TABLE_5_ITEM

8

26

C

B

BOM GROUP

HUB_ALLREM

HUB_1NONREM

USB MUX FOR LS/FS INTERNAL DEVICES

R2701

100

1 2

5% 1/16W MF-LF

402

1

R2706

10K

5% 1/16W MF-LF 402

2

1

C2702

0.1UF

10% 16V

2

X7R-CERM 0402

C2706

0.1UF

X7R-CERM

BYPASS=U2700.36::2MM

1

C2703

0.1UF

2

BYPASS=U2700.15::2MM

1

C2708

10% 16V

2

0402

0.1UF

X7R-CERM

USB_HUB_TEST

USB_HUB_RESET_L

26

USB_HUB_XTAL1 USB_HUB_XTAL2

USB_HUB_NONREM0

USB_HUB_NONREM1

USB_HUB_CFG_SEL0

USB_HUB_CFG_SEL1

1

R2707

10K

5% 1/16W MF-LF 402

2

10% 16V X7R-CERM 0402

10% 16V

0402

1

2

5

1015232936

VDD33

SYM VER 1

U2700

USB2513B

11

TEST

26

RESET*

33

XTALIN/CLKIN

32

XTALOUT

28

SUSP_IND/LOCAL_PWR/NON_REM0

22

SDA/SMBDATA/NON_REM1

24

SCL/SMBCLK/CFG_SEL0

25

HS_IND/CFG_SEL1

QFN

OMIT

CKPLUS_WAIVE=NdifPr_badTerm

THRM_PAD

PPUSB_HUB2_VDD1V8

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8PLL

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

14

34

CRFILT

PLLFILT

USBDM_DN1/PRT_DIS_M1 USBDP_DN1/PRT_DIS_P1

USBDM_DN2/PRT_DIS_M2 USBDP_DN2/PRT_DIS_P2

USBDM_DN3/PRT_DIS_M3 USBDP_DN3/PRT_DIS_P3

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2* PRTPWR3/BC_EN3*

37

IPU IPU IPU IPU

OCS1* OCS2* OSC3*

RBIAS

VBUS_DET

USBDM_UP USBDP_UP

1

C2711

0.1UF

10% 16V

2

X7R-CERM 0402

1

USBHUB_DN1_N

2

USBHUB_DN1_P

3

USBHUB_DN2_N

4

USBHUB_DN2_P

6

USBHUB_DN3_N

7

USBHUB_DN3_P

8

USBHUB_DN4_N

NC

9

USBHUB_DN4_P

NC

12

TP_USB_HUB_PRTPWR1

16

NC_USB_HUB_PRTPWR2

18

NC_USB_HUB_PRTPWR3

20

NC_USB_HUB_PRTPWR4

NC

13

TP_USB_HUB_OCS1

17

NC_USB_HUB_OCS2

19

NC_USB_HUB_OCS3

21

NC_USB_HUB_OCS4

NC

35

USB_HUB_RBIAS

27

USB_HUB_VBUS_DET

30

USB_HUB_UP_N

31

USB_HUB_UP_P

PCH PORT 7 (EHCI1)

1

2

=PP3V3_S3_USB_HUB

26

D

C

8

1/16W MF-LF

10K

HUB_NONREM0_1

1

R2703

10K

5%

1/16W MF-LF 402

402

2

HUB_NONREM0_0

1

R2705

10K

5%

1/16W MF-LF 402

402

2

HUB_NONREM1_1

R2702

HUB_NONREM1_0

R2704

15" MBP USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION MBP OG USES 197S0284 FOR Y2700 TO SAVE COST

B

BYPASS=U27000.5::5MM

BYPASS=U2700.23::5MM

CRITICAL

1

C2709

18PF

5%

50V

2

C0G-CERM

0402

=PP3V3_S3_USB_RESET

8

C2700

4.7UF

20%

6.3V X5R 603

BYPASS=U2700.10::2MM

C2704

4.7UF

20%

6.3V X5R 603

CRITICAL

Y2700

SM-2

24.000MHZ-16PF

1 3

2 4

NC

R2700

1M

1 2

5% 1/16W MF-LF

402

CRITICAL

1

2

1

2

1

R2712

10K

5% 1/16W MF-LF 402

2

USB_HUB_RESET_L

C2701

1

0.1UF

10% 16V

2

X7R-CERM

0402

BYPASS=U2700.29::2MM

1

C2705

0.1UF

10% 16V

2

X7R-CERM

0402

BYPASS=U2700.5::2MM

BYPASS=U2650.23::2MM

CRITICAL

1

C2710

18PF

5% 50V

2

C0G-CERM 0402

26

HUB_2NONREM HUB_3NONREM

NON_REM 1 : NON_REM 0 STRAP PIN CFG 0 : 0 ALL PORTS ARE REMOVABLE

0 : 1 PORT 1 IS NON REMOVABLE 1 : 0 PORT 1&2 ARE NON REMOVABLE

CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H

1

C2714

1UF

10% 16V

2

X5R 402

BLUETOOTH FOR 15" MBP & MBP OG

TRACKPAD/KEYBOARD FOR 15" MBP & MBP OG

SMC DEBUG PORT FOR 15" MBP, IR for MBP OG

NC FOR 15" MBP, SMC DEBUG PORT FOR MBP OG

=PP3V3_S3_USB_HUB

1

R2708

10K

5% 1/16W MF-LF 402

2

C2712

1UF

10% 16V X5R 402

BI BI

9

26

9

26

BI BI

7

19 91

9

26

1

C2713

0.1UF

10% 16V

2

X7R-CERM 0402

CRITICAL

1

R2709

12K

1% 1/16W MF 402

2

1 : 1 PORT 1&2&3 ARE NON REMOVABLE

15" MBP ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B MBP OG ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B

26

8

26

TO CONNECT TP/KB TO PCH XHCI NOSTUFF R5701 & R5702, STUFF R2720 & R2721

USB_EXTD_XHCI_N

19 91

BI

26

TO PCH XHCI

USB_EXTD_XHCI_P

19 91

BI

HUB_NONREM1_0,HUB_NONREM0_0 HUB_NONREM1_0,HUB_NONREM0_1 HUB_NONREM1_1,HUB_NONREM0_0 HUB_NONREM1_1,HUB_NONREM0_1

PART#

338S0824

338S0923

338S0983

USBHUB_DN3_N

9

USBHUB_DN3_P

9

USBHUB_DN4_N

9

USBHUB_DN4_P

9

USBHUB_DN2_N

9

USBHUB_DN2_P

9

BOM OPTIONS

BOM TABLE

DESCRIPTION

QTY

1

USB HUB 2514B

USB HUB 2513B

1

USB HUB 2512B

1

NOSTUFF

1

R2716

10K

5% 1/16W MF-LF 402

2

NOSTUFF

R2721

27

1 2

5% 1/16W MF-LF

402

NOSTUFF

1

R2717

10K

5% 1/16W MF-LF 402

2

1 2

REFERENCE DESIGNATOR(S)

NOSTUFF

R2720

27

5% 1/16W MF-LF

402

NOSTUFF

1

R2718

10K

5% 1/16W MF-LF 402

2

U2700

NOSTUFF

1

R2719

10K

5% 1/16W MF-LF 402

2

CRITICAL BOM OPTION

CRITICAL

NOSTUFF

1

R2722

10K

5% 1/16W MF-LF 402

2

USB_TPAD_R_N

USB_TPAD_R_P

=PP3V3_S3_USB_HUB

1

C2715

0.1UF

10% 16V

2

X7R-CERM

BYPASS=U2700.26::2MM

A

0402

USB XHCI/EHCI2 PORT MUX FOR EXT B

=PP3V3_S3_USBMUX

8

1

PCH PORT 9 (EHCI2)

PCH PORT 1 (XHCI)

C2760

0.1UF

20% 10V

2

CERM

19

BI

91 19 91

BI

19

BI

91 19 91

BI

USB_EXTB_EHCI_P USB_EXTB_EHCI_N

USB_EXTB_XHCI_P USB_EXTB_XHCI_N

402

5 4

7 6

8

6 3

M+ M-

U2760

PI3USB102ZLE D+ D-

9

VCC

TQFN

CRITICAL

GND

3

1

Y+

2

Y-

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

10

SELOE*

SEL=0 CHOOSE USB EHCI2 PORT SEL=1 CHOOSE USB XHCI PORT

USB_EXTB_P USB_EXTB_N

USB_EXTB_SEL_XHCI

7

38 91

BI

7

38 91

BI

17

IN

TO CONNECTOR

PCH GPIO60

SYNC_MASTER=D2_KEPLER

PAGE TITLE

USB HUB & MUX

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

27 OF 132

SHEET

26 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

12

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

D

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

PM_SLP_S4_L

7

18 34 38 40 41 70

IN

=PP3V3_S3_MEMRESET

8

C

ISOLATE_CPU_MEM_L

24

IN IN

=PP5V_S3_MEMRESET

8

27

CPUMEM_S0

B

NOSTUFF

C2817

0.047UF

10%

6.3V X5R 201

=MEM_RESET_L

11

IN

R2815

100K

1/16W MF-LF

402

1

2

1

5%

2

CRITICAL

CPUMEM_S0

Q2815

SSM6N15FEAPE

SOT563

D

6

MEMRESET_ISOL_LS5V_L

33

CPU_MEM_RESET_L

MAKE_BASE=TRUE

2

S G

1

CPUMEM_S0

R2801

CRITICAL

CPUMEM_S0

Q2800

SSM6N15FEAPE

SOT563

CPUMEM_S0

R2802

CRITICAL

CPUMEM_S0

Q2800

SSM6N15FEAPE

SOT563

CRITICAL

CPUMEM_S0

Q2815

SSM6N15FEAPE

5

S G

4

100K

1/16W MF-LF

5

100K

1/16W MF-LF

2

5%

402

5%

402

SOT563

1

2

3

D

SG

4

1

2

6

D

SG

1

D

3

CRITICAL

CPUMEM_S0

Q2805

SSM6N15FEAPE

P1V5CPU_EN_L

CRITICAL

CPUMEM_S0

Q2810

SSM6N15FEAPE

MEMVTT_EN_L

=PP1V5_S3_MEMRESET

CPUMEM_S0

1

R2816

1K

5% 1/16W MF-LF 402

2

SOT563

2

3

4

2

3

4

D

S G

D

S G

1

2

CPUMEM_S0

C2816

0.1UF

10% 16V X7R-CERM 0402

CPUMEM_S0

1

R2805

10K

5% 1/16W MF-LF 402

2

P1V5CPU_EN

6

D

SG

1

CRITICAL

CPUMEM_S0

Q2805

SSM6N15FEAPE

SOT563

5

PM_SLP_S3_L

CPUMEM_S0

1

R2810

10K

5% 1/16W MF-LF 402

2

MEMVTT_EN

6

D

SG

1

CRITICAL

CPUMEM_S0

Q2810

SSM6N15FEAPE

SOT563

5

PLT_RESET_L

8

MEM_RESET_L

69

OUT

7

18 38 41 70

9

OUT

19 25

IN

28 29 30 31

OUT

CPUMEM_S3

R2817

0

1 2

5% 1/16W MF-LF

402

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN 0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

1 0 1 1 1 1 1 1 1 2 0 0 1 1 1 1 0 1

to

A

3 0 0 0 1 X 1 0 0

S3

4 0 0 1 1 X 1 0 1 5 0 1 1 1 0 (*) 1 1 1

to

6 0 1 1 1 1 1 1 1 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

6 3

PART NUMBER

=PP1V5_S3_CPU_VCCDDR

8

11 14 16

OMIT_TABLE

114S0365

114S0376

QTY

DESCRIPTION

1

RES,MTL FILM,1/16W,33.2K,1,0402,SMD,LF

RES,MTL FILM,1/16W,43.2K,1,0402,SMD,LF

REFERENCE DES

1V5 S0 "PGOOD" for CPU

=PP3V3_S5_CPU_VCCDDR

8

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

1

R2822

10K

R2820

27.4K

1/16W MF-LF

R2821

33.2K

1/16W MF-LF

1

1%

402

2

1

1%

402

2

P1V5_S0_DIV

C2820

4700PF

10% 100V CERM

402

5% 1/16W MF-LF 402

2

PM_MEM_PWRGD_L

3

CRITICAL

Q2820

5

DMB53D0UV

SOT-563

1

2

4

CRITICAL

G

2

MEMVTT Clamp

Ensures CKE signals are held low in S3

=PPVTT_S0_VTTCLAMP

8

=PP5V_S3_MEMRESET

8

27

SSM6N15FEAPE

=DDRVTT_EN

9

64

IN

CPUMEM_S0

R2851

CRITICAL

CPUMEM_S0

Q2850

SOT563

5

100K

1/16W MF-LF

1

5%

402

2

D

SG

CRITICAL

CPUMEM_S0

SSM6N15FEAPE

VTTCLAMP_EN

NO STUFF

3

C2851

0.001UF

4

Q2850

SOT563

20% 50V

CERM

402

2

1

2

R2821

D

SG

6

1

PM_MEM_PWRGD

6 D

Q2820

DMB53D0UV

SOT-563

S 1

CPUMEM_S0

R2850

VTTCLAMP_L

CRITICAL

1

10

5% 1/10W MF-LF

603

2

SYNC_MASTER=D2_KEPLER

PAGE TITLE

BOM OPTION

PPDDR:1V5

PPDDR:1V35

11 18 89

OUT

75mA max load @ 0.75V 60mW max power

CPU Memory S3 Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

28 OF 132

SHEET

27 OF 99

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

=PP1V5R1V35_S3_MEM_A

1

C2907

0.47UF

20%

4V

CERM-X5R-1

32 90

MEM_A_A<0>

12 28

29

90

MEM_A_A<1>

12 28

D

29 32

MEM_A_A<2>

32 90

MEM_A_A<3>

12 28

90

29

29 32

MEM_A_A<4>

12 28 32 90

MEM_A_A<5>

12 28

29

90

MEM_A_A<6>

12 28 29 32

MEM_A_A<7>

32 90

MEM_A_A<8>

12 28

29

90

MEM_A_A<9>

12 28 29 32

MEM_A_A<10>

12 28 29 32

32

90

MEM_A_A<11>

12 28

29

32 90

90

MEM_A_A<12>

12 28

29

90

MEM_A_A<13>

12 28 29 32

MEM_A_A<14>

12 28 29 32

90

MEM_A_A<15>

12 28 29 32

90

MEM_A_BA<0>

12 28 29 32

MEM_A_BA<1>

12 28 29 32

90

MEM_A_BA<2>

12 28 29 32

90

MEM_A_RAS_L

12 28 29 32

MEM_A_CAS_L

90

MEM_A_WE_L

12 28 29 32

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<0>

2

C

R2900

240

1% 1/20W MF 201

1

2

201

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A3

A10D8G9G3K2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

B2

28 29 33 89

K10M2M10

VDD

OMIT_TABLE

U2900

DDR3-1333

FBGA

(SYM VER 2)

VSS

J2L2N2F3A9D9F9

J10

B10C2E3

L10

N10

VDDQ

8

28 29

B3D2B9

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

=PP1V5R1V35_S3_MEM_A

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5>

12 28 29 32 90

MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<1>

2

R2910

240

1% 1/20W MF 201

1

C2917

1

C2908

0.47UF 0.47UF

20%

4V

CERM-X5R-1

H2

201

NC

H10

NC

N1

NC

N11

VREFDQ

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<0>

DQ0

C8

MEM_A_DQ<6>

DQ1

C3

MEM_A_DQ<7>

DQ2

C9

MEM_A_DQ<5>

DQ3

E4

MEM_A_DQ<3>

E9

MEM_A_DQ<1>

D3

MEM_A_DQ<2>

E8

MEM_A_DQ<4>

C4

MEM_A_DQS_P<0>

DQS

D4

MEM_A_DQS_N<0>

DQS*

B8 A8

NC

H3

MEM_A_CS_L<0>

CS*

G10

MEM_A_CKE<0>

CKE

F8

MEM_A_CLK_P<0>

CK

G8

MEM_A_CLK_N<0>

CK*

A1

NC NC

A4

NC

A11

NC

F2

NC

F10

NC

C10

D10

C2909

0.47UF

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90

12 29 90

12 28 32 90

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U2910

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

N10

VDDQ

8

28 29

E10J9E2

NF/TDQS*

B3D2B9

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

=PP1V5R1V35_S3_MEM_A

1

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<2>

2

R2920

240

1% 1/20W MF 201

1

C2927

0.47UF

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A10D8G9G3K2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

B2

201

1

C2918

0.47UF

20%

4V

CERM-X5R-1

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<14>

DQ0

C8

MEM_A_DQ<9>

DQ1

C3

MEM_A_DQ<10>

DQ2

C9

MEM_A_DQ<15>

DQ3

E4

MEM_A_DQ<11>

E9

MEM_A_DQ<13>

D3

MEM_A_DQ<8>

E8

MEM_A_DQ<12>

C4

MEM_A_DQS_P<1>

DQS

D4

MEM_A_DQS_N<1>

B8 A8

NC NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

CK

G8

MEM_A_CLK_N<0>

A1 A4

NC

A11

NC

F2

NC

F10

NC

C2919

20% 4V

2

CERM-X5R-1 201201

90

27 28 29 30 31

12 28 29 32 90

12 29 90

12 28 32 90

D10

28 29 33 89

K10M2M10

VDD

OMIT_TABLE OMIT_TABLE

U2920

DDR3-1333

FBGA

(SYM VER 2)

VSS

J2L2N2F3A9D9F9

J10

B10C2E3

L10

N10

VDDQ

8

28 29

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C2928

0.47UF

CERM-X5R-1

NC

1

20%

4V

2

H2

201

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<22>

C8

MEM_A_DQ<21>

C3

MEM_A_DQ<16>

C9

MEM_A_DQ<17>

E4

MEM_A_DQ<18>

E9

MEM_A_DQ<23>

D3

MEM_A_DQ<20>

E8

MEM_A_DQ<19>

C4

MEM_A_DQS_P<2>

D4

MEM_A_DQS_N<2>

B8 A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C2929

0.47UF

20% 4V

2

CERM-X5R-1 201

90

12 28 29 32 90

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32 27 28 29 30 31

MEM_A_A<2> MEM_A_A<3>

12 29 90

MEM_A_A<4>

12 29 90

MEM_A_A<5>

12 29 90

MEM_A_A<6>

12 29 90

MEM_A_A<7>

12 29 90

MEM_A_A<8>

12 29 90

MEM_A_A<9>

12 29 90

MEM_A_A<10>

12 29 90

MEM_A_A<11>

12 29 90

MEM_A_A<12>

12 29 90

MEM_A_A<13>

12

28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<0>

12 28 32 90

MEM_A_BA<1>

12 28 32 90

MEM_A_BA<2>

12 28 32 90

MEM_A_RAS_L

12 28 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<3>

2

R2930

240

1% 1/20W MF 201

1

C2937

0.47UF

CERM-X5R-1

=PP1V5R1V35_S3_MEM_A

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

K10M2M10

B10C2E3

VDD

U2930

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

8

VDDQ

28 29

E10J9E2

NF/TDQS*

B3D2B9

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

DQ0 DQ1 DQ2 DQ3

DQS

CK

C2938

0.47UF

20%

CERM-X5R-1

H2

201

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<31>

C8

MEM_A_DQ<24>

C3

MEM_A_DQ<27>

C9

MEM_A_DQ<28>

E4

MEM_A_DQ<30>

E9

MEM_A_DQ<25>

D3

MEM_A_DQ<26>

E8

MEM_A_DQ<29>

C4

MEM_A_DQS_P<3>

D4

MEM_A_DQS_N<3>

B8 A8

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

12

1

C2939

0.47UF

4V

20% 4V

2

CERM-X5R-1 201

D

27 28 29 30 31

12 29 90

12 28 32 90

C

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

=PP1V5R1V35_S3_MEM_A

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A10D8G9G3K2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

B2

201

C2947

CERM-X5R-1

90

MEM_A_A<0>

12 28 29 32

MEM_A_A<1>

90

MEM_A_A<2>

12 28 29 32

MEM_A_A<3>

12 28 29 32

90

MEM_A_A<4>

12 28 29 32

90

MEM_A_A<5>

12 28 29 32

MEM_A_A<6>

90

MEM_A_A<7>

12 28 29 32

MEM_A_A<8>

12 28 29 32

90

MEM_A_A<9>

12 28 29 32

B

90

MEM_A_A<10>

12 28 29 32

MEM_A_A<11>

32 90

MEM_A_A<12>

12 28

90

29

29 32

MEM_A_A<13>

12 28 32 90

MEM_A_A<14>

12 28

29

90

MEM_A_A<15>

12 28 29 32 90 29 32

MEM_A_BA<0>

12 28 32 90

MEM_A_BA<1>

12 28

29

90

MEM_A_BA<2>

12 28 29 32

90

MEM_A_RAS_L

12 28 29 32

MEM_A_CAS_L

90

MEM_A_WE_L

12 28 29 32

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<4>

2

R2940

240

1% 1/20W MF 201

1

28 29 33 89

K10M2M10

VDD

OMIT_TABLE

U2940

DDR3-1333

FBGA

(SYM VER 2)

VSS

J2L2N2F3A9D9F9

J10

B10C2E3

L10

N10

VDDQ

8

28 29

B3D2B9

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

VREFCA

D10

1

C2948

0.47UF

4V

CERM-X5R-1

NC

2

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<32>

C8

MEM_A_DQ<33>

C3

MEM_A_DQ<34>

C9

MEM_A_DQ<35>

E4

MEM_A_DQ<36>

E9

MEM_A_DQ<37>

D3

MEM_A_DQ<38>

E8

MEM_A_DQ<39>

C4

MEM_A_DQS_P<4>

D4

MEM_A_DQS_N<4>

B8 A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C2949

0.47UF

20%20% 4V

2

CERM-X5R-1 201

90

12 28 29 32 90

12 28 29 32 27 28 29 30 31

12 29 90

12

28 29 32 90

12 28 29 32 90

MEM_A_BA<0>

12 28 32 90

MEM_A_BA<1>

12 28 32 90

MEM_A_BA<2>

12 28 32 90

MEM_A_RAS_L

12 28 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

2

R2950

240

1% 1/20W MF 201

1

C2957

0.47UF

CERM-X5R-1

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_A_ZQ<5>

=PP1V5R1V35_S3_MEM_A

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U2950

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

N10

VDDQ

8

28 29

E10J9E2

NF/TDQS*

B3D2B9

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C2958

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C2959

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47>

MEM_A_DQS_P<5> MEM_A_DQS_N<5>

NC

MEM_A_CS_L<0> MEM_A_CKE<0>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

90

12 28 29 32 90

12 28 29 32 27 28 29 30 31

12 29 90

12

28 29 32 90

12 28 29 32 90

12 28 32 90

12 28 29 32 90

12 28 32 90

2

R2960

1

240

1% 1/20W MF 201

C2967

0.47UF

20%

CERM-X5R-1

201

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEM_A_ODT<0> MEM_A_ZQ<6>

=PP1V5R1V35_S3_MEM_A

1

4V

2

A3

A10D8G9G3K2

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

B2

J2L2N2F3A9D9F9

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

8

28 29

1

C2968

0.47UF

20%

K10M2M10

B10C2E3

E10J9E2

FBGA

VDDQ

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS* CKE

DQ0 DQ1 DQ2 DQ3

DQS

VDD

OMIT_TABLE OMIT_TABLE

U2960

DDR3-1333

(SYM VER 2)

CK*

NC

VSS

J10

L10

N10

VSSQ

B3D2B9

C10

CERM-X5R-1

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<48>

C8

MEM_A_DQ<49>

C3

MEM_A_DQ<50>

C9

MEM_A_DQ<51>

E4

MEM_A_DQ<52>

E9

MEM_A_DQ<53>

D3

MEM_A_DQ<54>

E8

MEM_A_DQ<55>

C4

MEM_A_DQS_P<6>

D4

MEM_A_DQS_N<6>

B8 A8

NC

H3

MEM_A_CS_L<0>

G10

MEM_A_CKE<0>

F8

MEM_A_CLK_P<0>

CK

G8

MEM_A_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

4V

201

C2969

0.47UF

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90

12 29 90

12 28 32 90

C2977

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5>

12 28 29 32 90

MEM_A_A<6>

12 28 29 32 90

MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<0>

12 28 32 90

MEM_A_ZQ<7>

2

R2970

240

1% 1/20W MF 201

1

0.47UF

=PP1V5R1V35_S3_MEM_A

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

VDD

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

8

28 29

K10M2M10

B10C2E3

E10J9E2

VDDQ

U2970

DDR3-1333

FBGA

(SYM VER 2)

VSS

B3D2B9

L10

N10

J10

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS* CKE

CK*

NC

VSSQ

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C2978

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C2979

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQS_P<7> MEM_A_DQS_N<7>

NC

MEM_A_CS_L<0> MEM_A_CKE<0>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

27 28 29 30 31

12 29 90

B

12 29 90

12 28 32 90

=PP1V5R1V35_S3_MEM_A

8

28 29

A

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2910

20% 10V

2

402

1

C2950

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C2911

2.2UF

C2951

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C2920

2.2UF

X5R-CERM

C2960

2.2UF

X5R-CERM

1

C2921

20% 10V

2

X5R-CERM

402

1

C2961

20% 10V

2

X5R-CERM

402

1

C2900

2.2UF

X5R-CERM X5R-CERM

C2940

2.2UF

X5R-CERM

C2901

20% 10V

2

402

1

C2941

20% 10V

2

402

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2.2UF

1

20% 10V

2

402

1

20% 10V

2

402

C2930

2.2UF

X5R-CERM

C2970

2.2UF

X5R-CERM

1

C2931

2.2UF

X5R-CERM

C2971

2.2UF

X5R-CERM

20% 10V

402

20% 10V

402

20% 10V

2

402

1

20% 10V

2

402

1

C2903

0.1UF

10%

6.3V

2

1

2

X5R 201

1

C2943

0.1UF

10%

6.3V

2

X5R 201

1

C2904

0.1UF

10%

6.3V

2

X5R 201

1

C2944

0.1UF

10%

6.3V

2

X5R 201

1

C2905

0.1UF

10%

6.3V

2

X5R 201

1

C2945

0.1UF

10%

6.3V

2

X5R 201

6 3

1

C2913

0.1UF

10%

6.3V

2

X5R 201

1

C2953

0.1UF

10%

6.3V

2

X5R 201

1

C2914

0.1UF

10%

6.3V

2

X5R 201

1

C2954

0.1UF

10%

6.3V

2

X5R 201

1

C2915

0.1UF

10%

6.3V

2

X5R 201

1

C2955

0.1UF

10%

6.3V

2

X5R 201

1

C2923

0.1UF

10%

6.3V

2

X5R 201

1

C2963

0.1UF

10%

6.3V

2

X5R 201

1

C2924

0.1UF

10%

6.3V

2

X5R 201

1

C2964

0.1UF

10%

6.3V

2

X5R 201

1

C2925

0.1UF

10%

6.3V

2

X5R 201

1

C2965

0.1UF

10%

6.3V

2

X5R 201

1

C2933

0.1UF

10%

6.3V

2

X5R 201

1

C2973

0.1UF

10%

6.3V

2

X5R 201

1

C2934

0.1UF

10%

6.3V

2

X5R 201

1

C2974

0.1UF

10%

6.3V

2

X5R 201

1

C2935

0.1UF

10%

6.3V

2

X5R 201

1

C2975

0.1UF

10%

6.3V

2

X5R 201

SYNC_MASTER=D2_KEPLER

PAGE TITLE

DDR3 SDRAM Bank A (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

SYNC_DATE=01/13/2012

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

29 OF 132

SHEET

28 OF 99

124578

SIZE

A

D

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

=PP1V5R1V35_S3_MEM_A

8

28 29

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

8

28 29

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

=PP1V5R1V35_S3_MEM_A

8

28 29

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

=PP1V5R1V35_S3_MEM_A

12

8

28 29

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_A

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3000

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

VDDQ

B3D2B9

8

28 29

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

VREFCA

D10

1

C3008

0.47UF

20%

4V

CERM-X5R-1

NC

2

H2

201

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<6>

C8

MEM_A_DQ<0>

C3

MEM_A_DQ<5>

C9

MEM_A_DQ<7>

E4

MEM_A_DQ<4>

E9

MEM_A_DQ<2>

D3

MEM_A_DQ<1>

E8

MEM_A_DQ<3>

C4

MEM_A_DQS_P<0>

D4

MEM_A_DQS_N<0>

B8 A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3009

0.47UF

20% 4V

2

CERM-X5R-1 201

C3017

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

90

27 28 29 30 31

MEM_A_A<2>

12 28 29 32 90

MEM_A_A<4>

12 28 90

MEM_A_A<3>

12 28 90

MEM_A_A<6>

12 28 90

MEM_A_A<5>

12 28 90

MEM_A_A<8>

12 28 90

MEM_A_A<7>

12 28 90

MEM_A_A<9>

12 28 90

MEM_A_A<10>

12 28 90

MEM_A_A<11>

12 28 90

MEM_A_A<12>

90

12 28

MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1>

12 28 29 32 90

MEM_A_BA<0>

12 29 32 90

MEM_A_BA<2>

12 29 32 90

MEM_A_RAS_L

12 28 29 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<9>

2

R3010

240

1% 1/20W MF 201 201

1

C3007

CERM-X5R-1

90

MEM_A_A<0>

12 28 29 32

90 12 28 29 32

12 28 29 32

90

90 12 28 29 32

90

12 28

29 32

90

12 28

29 32

12 28

29 32

90

90 12 28 29 32

90

12 28

29 32

90

12 28

29 32

90

12 28

29 32

12 28

29 32

90

29 32

12 28

32 90

12 28

29

90

12 28

29 32

32 90

12 28

29

90

12 28

29 32

12 28

29 32

90

12 29

32 90

2

1

MEM_A_A<1> MEM_A_A<2> MEM_A_A<4> MEM_A_A<3> MEM_A_A<6> MEM_A_A<5> MEM_A_A<8> MEM_A_A<7> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_A_BA<1> MEM_A_BA<0> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEM_A_ODT<1> MEM_A_ZQ<8>

R3000

240

1% 1/20W MF 201

D

C

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_A

1

C3018

0.47UF

20%

K10M2M10

B10C2E3

E10J9E2

FBGA

VDDQ

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS* CKE

DQ0 DQ1 DQ2 DQ3

DQS

VDD

OMIT_TABLE OMIT_TABLE

U3010

DDR3-1333

(SYM VER 2)

CK*

NC

VSS

L10

J10

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

N10

8

B3D2B9

28 29

VSSQ

C10

4V

CERM-X5R-1

H2

201

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<9>

C8

MEM_A_DQ<14>

C3

MEM_A_DQ<15>

C9

MEM_A_DQ<10>

E4

MEM_A_DQ<12>

E9

MEM_A_DQ<8>

D3

MEM_A_DQ<13>

E8

MEM_A_DQ<11>

C4

MEM_A_DQS_P<1>

D4

MEM_A_DQS_N<1>

B8 A8

NC NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

CK

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

C3019

0.47UF

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90 12 28 29 32 90

12 28 90

12 29 32 90

C3027

0.47UF

20%

4V

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<2> MEM_A_A<4> MEM_A_A<3> MEM_A_A<6> MEM_A_A<5> MEM_A_A<8> MEM_A_A<7> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1> MEM_A_BA<0> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<10>

2

R3020

240

1% 1/20W MF

1

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

VDD

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_A

K10M2M10

B10C2E3

E10J9E2

VDDQ

U3020

DDR3-1333

FBGA

(SYM VER 2)

VSS

B3D2B9

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_APP0V75_S3_MEM_VREFDQ_A

28 29 33 89 28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

8

28 29

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

NF/TDQS*

CS* CKE

CK*

NC

VSSQ

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3028

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3029

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<23> MEM_A_DQ<18>

MEM_A_DQS_P<2> MEM_A_DQS_N<2>

NC

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

90

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32 27 28 29 30 31

MEM_A_A<4>

12 28 90

MEM_A_A<3>

12 28 90

MEM_A_A<6>

12 28 90

MEM_A_A<5>

12 28 90

MEM_A_A<8>

12 28 90

MEM_A_A<7>

12 28 90

MEM_A_A<9>

12 28 90

MEM_A_A<10>

12 28 90

MEM_A_A<11>

12 28 90

MEM_A_A<12>

12 28 90

MEM_A_A<13>

12

28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1>

12 29 32 90

MEM_A_BA<0>

12 29 32 90

MEM_A_BA<2>

12 29 32 90

MEM_A_RAS_L

12 29 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<11>

2

R3030

240

1% 1/20W MF 201

1

C3037

0.47UF

CERM-X5R-1

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_A

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3030

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_A

28 29 33 89

PP0V75_S3_MEM_VREFCA_A

28 29 33 89

VDDQ

8

28 29

E10J9E2

DM/TDQS

NF/TDQS*

VSSQ

B3D2B9

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

NC

CS* CKE

CK*

C10

DQ0 DQ1 DQ2 DQ3

DQS

CK

C3038

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11

VREFCA

N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

D10

1

C3039

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<24> MEM_A_DQ<31> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<29> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<30>

MEM_A_DQS_P<3> MEM_A_DQS_N<3>

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

D

27 28 29 30 31

12 28 90

12 29 32 90

C

C3047

CERM-X5R-1

90

MEM_A_A<0>

12 28 29 32

MEM_A_A<1>

90

MEM_A_A<2>

12 28 29 32

MEM_A_A<4>

12 28 29 32

90

MEM_A_A<3>

12 28 29 32

90

MEM_A_A<6>

12 28 29 32

MEM_A_A<5>

90

MEM_A_A<8>

12 28 29 32

MEM_A_A<7>

12 28 29 32

90

MEM_A_A<9>

12 28 29 32

B

90

MEM_A_A<10>

12 28 29 32

MEM_A_A<11>

32 90

MEM_A_A<12>

12 28

90

29

29 32

MEM_A_A<13>

12 28 32 90

MEM_A_A<14>

12 28

29

90

MEM_A_A<15>

12 28 29 32 90 29 32

MEM_A_BA<1>

12 28 32 90

MEM_A_BA<0>

12 28

29

90

MEM_A_BA<2>

12 28 29 32

32 90

MEM_A_RAS_L

12 28

29

90

MEM_A_CAS_L

12 28 29 32

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<12>

2

R3040

240

1% 1/20W

201

1

0.47UF

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

=PP1V5R1V35_S3_MEM_A

K10M2M10

VDD

OMIT_TABLE

U3040

DDR3-1333

(SYM VER 2)

VSS

8

FBGA

28 29

J10

B10C2E3

L10

N10

VDDQ

E10J9E2

RESET*

DM/TDQS

NF/TDQS*

VSSQ

B3D2B9

VREFDQ

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3048

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3049

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36>

MEM_A_DQS_P<4> MEM_A_DQS_N<4>

NC

MEM_A_CS_L<1> MEM_A_CKE<1>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90

12 28 90

12 28

12 29 32 90

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<4>

12 28 29 32 90

MEM_A_A<3> MEM_A_A<6> MEM_A_A<5> MEM_A_A<8> MEM_A_A<7>

12 28 29 32 90

MEM_A_A<9>

12 28 29 32 90

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12>

90

MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1> MEM_A_BA<0>

12 28 29 32 90

MEM_A_BA<2> MEM_A_RAS_L

12 28 29 32 90

MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<13>

2

R3050

240

1% 1/20W MFMF 201

1

C3057

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3050

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

C3058

0.47UF

CERM-X5R-1

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<41>

C8

MEM_A_DQ<40>

C3

MEM_A_DQ<43>

C9

MEM_A_DQ<42>

E4

MEM_A_DQ<47>

E9

MEM_A_DQ<46>

D3

MEM_A_DQ<45>

E8

MEM_A_DQ<44>

C4

MEM_A_DQS_P<5>

D4

MEM_A_DQS_N<5>

B8 A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

20%

201

1

C3059

0.47UF

20%

4V

2

CERM-X5R-1 201

27 28 29 30

12 28 29 32 90

31 12 28

90 12 28

90

12 28 90

12 28

12 29 32 90

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32 90

MEM_A_A<2> MEM_A_A<4> MEM_A_A<3> MEM_A_A<6>

12 28 29 32 90

MEM_A_A<5> MEM_A_A<8>

12 28 29 32 90

MEM_A_A<7> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12>

90

MEM_A_A<13>

12 28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1> MEM_A_BA<0> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<14>

2

R3060

240

1% 1/20W

201

1

C3067

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3060

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3068

0.47UF

CERM-X5R-1

NC

20%

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<49>

C8

MEM_A_DQ<48>

C3

MEM_A_DQ<51>

C9

MEM_A_DQ<50>

E4

MEM_A_DQ<55>

E9

MEM_A_DQ<54>

D3

MEM_A_DQ<53>

E8

MEM_A_DQ<52>

C4

MEM_A_DQS_P<6>

D4

MEM_A_DQS_N<6>

B8 A8

NC

H3

MEM_A_CS_L<1>

G10

MEM_A_CKE<1>

F8

MEM_A_CLK_P<1>

G8

MEM_A_CLK_N<1>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3069

0.47UF

4V

20% 4V

2

CERM-X5R-1 201

90

27 28 29 30 31

12 28 29 32 90

12 28 90

12 29 32 90

CERM-X5R-1

MEM_A_A<0>

12 28 29 32 90

MEM_A_A<1>

12 28 29 32

MEM_A_A<2> MEM_A_A<4> MEM_A_A<3> MEM_A_A<6> MEM_A_A<5> MEM_A_A<8> MEM_A_A<7> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

12

28 29 32 90

MEM_A_A<14>

12 28 29 32 90

MEM_A_A<15>

12 28 29 32 90

MEM_A_BA<1> MEM_A_BA<0> MEM_A_BA<2>

MEM_A_RAS_L MEM_A_CAS_L

12 28 29 32 90

MEM_A_WE_L

12 28 29 32 90

MEM_A_ODT<1>

12 29 32 90

MEM_A_ZQ<15>

2

R3070

240

1% 1/20W MFMF 201

1

A

C3000

2.2UF

X5R-CERM

C3040

2.2UF

X5R-CERM

1

C3001

20% 10V

2

402

1

C3041

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C3010

20% 10V

2

402

1

C3050

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3011

2.2UF

X5R-CERM

C3051

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3020

2.2UF

X5R-CERM

C3060

2.2UF

X5R-CERM

1

C3021

20% 10V

2

402

1

C3061

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3030

2.2UF

X5R-CERM

C3070

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3031

2.2UF

X5R-CERM

C3071

2.2UF

X5R-CERM

1

C3003

2

1

2

0.1UF 0.1UF

10%

6.3V

2

X5R 201

1

C3043

0.1UF

10%

6.3V

2

X5R 201

20% 10V

402

20% 10V

402

1

C3004

10%

6.3V

2

X5R 201

1

C3044

0.1UF

10%

6.3V

2

X5R 201

1

C3005

0.1UF

10%

6.3V

2

X5R 201

1

C3045

0.1UF

10%

6.3V

2

X5R 201

1

C3013

0.1UF

10%

6.3V

2

X5R 201

1

C3053

0.1UF

10%

6.3V

2

X5R 201

1

C3014

0.1UF

10%

6.3V

2

X5R 201

1

C3054

0.1UF

10%

6.3V

2

X5R 201

1

C3015

0.1UF

10%

6.3V

2

X5R 201

1

C3055

0.1UF

10%

6.3V

2

X5R 201

1

C3023

0.1UF

10%

6.3V

2

X5R 201

1

C3063

0.1UF

10%

6.3V

2

X5R 201

1

C3024

0.1UF

10%

6.3V

2

X5R 201

1

C3064

0.1UF

10%

6.3V

2

X5R 201

1

C3025

0.1UF

10%

6.3V

2

X5R 201

1

C3065

0.1UF

10%

6.3V

2

X5R 201

1

C3033

0.1UF

10%

6.3V

2

X5R 201

1

C3073

0.1UF

10%

6.3V

2

X5R 201

1

C3034

0.1UF

10%

6.3V

2

X5R 201

1

C3074

0.1UF

10%

6.3V

2

X5R 201

1

C3035

0.1UF

10%

6.3V

2

X5R 201

1

C3075

0.1UF

10%

6.3V

2

X5R 201

6 3

C3077

0.47UF

1

20%

4V

2

A3

201

A10D8G9G3K2

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

B2

J2L2N2F3A9D9F9

SYNC_MASTER=D2_KEPLER

PAGE TITLE

K10M2M10

VDD

OMIT_TABLE

U3070

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

C3078

0.47UF

20%

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_A_DQ<57>

DQ0

C8

MEM_A_DQ<56>

DQ1

C3

MEM_A_DQ<59>

DQ2

C9

MEM_A_DQ<58>

DQ3

E4

MEM_A_DQ<63>

E9

MEM_A_DQ<62>

D3

MEM_A_DQ<61>

E8

MEM_A_DQ<60>

C4

MEM_A_DQS_P<7>

DQS

D4

MEM_A_DQS_N<7>

DQS*

B8 A8

NC

H3

MEM_A_CS_L<1>

CS*

G10

MEM_A_CKE<1>

CKE

F8

MEM_A_CLK_P<1>

CK

G8

MEM_A_CLK_N<1>

CK*

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C10

D10

SYNC_DATE=01/13/2012

DDR3 SDRAM Bank A (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

4V

2

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

30 OF 132

SHEET

29 OF 99

1

C3079

0.47UF

20% 4V

2

CERM-X5R-1 201

27 28 29 30 31

12 28 90

B

12 28 90

12 29 32 90

A

SIZE

D

124578

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

8

30 31

=PP1V5R1V35_S3_MEM_B

30 31 33 89

8

30 31

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

8

30 31

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

=PP1V5R1V35_S3_MEM_B

12

8

30 31

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3100

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

VDDQ

B3D2B9

8

30 31

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

VREFCA

D10

1

C3108

0.47UF

20%

4V

CERM-X5R-1

NC

2

H2

201

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<6>

C8

MEM_B_DQ<1>

C3

MEM_B_DQ<3>

C9

MEM_B_DQ<5>

E4

MEM_B_DQ<2>

E9

MEM_B_DQ<4>

D3

MEM_B_DQ<7>

E8

MEM_B_DQ<0>

C4

MEM_B_DQS_P<0>

D4

MEM_B_DQS_N<0>

B8 A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3109

0.47UF

20% 4V

2

CERM-X5R-1 201

C3117

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 31 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

32 90

MEM_B_A<11>

12 30

31

90

MEM_B_A<12>

12 30 31 32

MEM_B_A<13>

12 30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<1>

2

R3110

240

1% 1/20W MF MF

1

C3107

CERM-X5R-1

32 90

MEM_B_A<0>

12 30

31

90

MEM_B_A<1>

12 30 31 32

D

C

MEM_B_A<2>

32 90

MEM_B_A<3>

12 30

90

31

31 32

MEM_B_A<4>

12 30 32 90

MEM_B_A<5>

12 30

31

90

MEM_B_A<6>

12 30 31 32

MEM_B_A<7>

32 90

MEM_B_A<8>

12 30

31

90

MEM_B_A<9>

12 30 31 32

MEM_B_A<10>

90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32

90

MEM_B_A<13>

12 30 31 32

90

MEM_B_A<14>

12 30 31 32

MEM_B_A<15>

12 30 31 32 90 90

MEM_B_BA<0>

12 30 31 32

MEM_B_BA<1>

12 30 31 32

90

MEM_B_BA<2>

12 30 31 32

90

MEM_B_RAS_L

12 30 31 32

MEM_B_CAS_L

90

MEM_B_WE_L MEM_B_WE_L

12 30 31 32

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<0>

2

R3100

240

1% 1/20W MF 201 201

1

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3110

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

N10

VDDQ

8

E10J9E2

NF/TDQS*

B3D2B9

30 31

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

1

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 30 31 32 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30 90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13> MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<2>

2

R3120

240

1% 1/20W

201

1

C3127

0.47UF

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3120

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

N10

VDDQ

B3D2B9

8

30 31

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3128

0.47UF

CERM-X5R-1

NC

1

20%

4V

2

H2

201

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<18>

C8

MEM_B_DQ<20>

C3

MEM_B_DQ<19>

C9

MEM_B_DQ<16>

E4

MEM_B_DQ<23>

E9

MEM_B_DQ<21>

D3

MEM_B_DQ<22>

E8

MEM_B_DQ<17>

C4

MEM_B_DQS_P<2>

D4

MEM_B_DQS_N<2>

B8 A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3129

0.47UF

20% 4V

2

CERM-X5R-1 201

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 31 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30

31 32 90

90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13>

12 30 31 32 90

MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 32 90

MEM_B_RAS_L

12 30 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<3>

2

R3130

240

1% 1/20W MF 201

1

CERM-X5R-1

1

C3118

0.47UF

20%

4V

CERM-X5R-1

H2

201

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<14>

DQ0

C8

MEM_B_DQ<9>

DQ1

C3

MEM_B_DQ<11>

DQ2

C9

MEM_B_DQ<13>

DQ3

E4

MEM_B_DQ<10>

E9

MEM_B_DQ<12>

D3

MEM_B_DQ<15>

E8

MEM_B_DQ<8>

C4

MEM_B_DQS_P<1>

DQS

D4

MEM_B_DQS_N<1>

B8 A8

NC NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

CK

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C3119

0.47UF

20% 4V

2

CERM-X5R-1 201

31 32 90

12 30 31 32 90

D10

C3137

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

J2L2N2F3A9D9F9

B2

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

B10C2E3

VDD

OMIT_TABLE

U3130

DDR3-1333

FBGA

(SYM VER 2)

VSS

L10

N10

J10

PP0V75_S3_MEM_VREFDQ_B

30 31 33 89

PP0V75_S3_MEM_VREFCA_B

30 31 33 89

VDDQ

8

E10J9E2

NF/TDQS*

B3D2B9

30 31

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

DM/TDQS

CS* CKE

CK*

NC

VSSQ

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3138

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3139

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_B_DQ<27> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<28> MEM_B_DQ<31> MEM_B_DQ<24>

MEM_B_DQS_P<3> MEM_B_DQS_N<3>

MEM_B_CS_L<0> MEM_B_CKE<0>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

D

27 28 29 30 31

12 31 90

12 30 32 90

C

C3147

CERM-X5R-1

32 90

MEM_B_A<0>

12 30

31

90

MEM_B_A<1>

12 30 31 32

MEM_B_A<2>

32 90

MEM_B_A<3>

12 30

90

31

31 32

MEM_B_A<4>

12 30 32 90

MEM_B_A<5>

12 30

31

90

MEM_B_A<6>

12 30 31 32

MEM_B_A<7>

32 90

MEM_B_A<8>

12 30

31

90

MEM_B_A<9>

12 30 31 32

B

90 12 30 31 32

12 30 31 32

90

90 12 30 31 32

90

12 30

31 32

12 30

31 32

90

12 30

31 32

12 30

31 32

90

90 12 30 31 32

90

12 30

31 32

90

12 30

31 32

12 30

32 90

2

1

MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

MEM_B_BA<0> MEM_B_BA<1> MEM_B_BA<2>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_ODT<0> MEM_B_ZQ<4>

R3140

240

1% 1/20W

201

1

0.47UF

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

=PP1V5R1V35_S3_MEM_B

K10M2M10

VDD

OMIT_TABLE

U3140

DDR3-1333

(SYM VER 2)

VSS

8

FBGA

30 31

J10

B10C2E3

L10

N10

VDDQ

E10J9E2

RESET*

DM/TDQS

NF/TDQS*

VSSQ

B3D2B9

VREFDQ

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3148

0.47UF

CERM-X5R-1

H2 H10

N1

NC

N11 N3

B4 C8 C3 C9 E4 E9 D3 E8

C4 D4

B8 A8

H3 G10

F8 G8

A1 A4 A11 F2 F10

1

C3149

0.47UF

20%

4V

201

NC NC

MEM_RESET_L

MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39>

MEM_B_DQS_P<4> MEM_B_DQS_N<4>

NC

MEM_B_CS_L<0> MEM_B_CKE<0>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

NC NC NC NC NC

20% 4V

2

CERM-X5R-1 201

12 31 90

31 32 90

12 30 31 32 90

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3> MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 30 31 32 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30 90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13> MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<5>

2

R3150

240

1% 1/20W MFMF 201

1

C3157

0.47UF

1

20%

4V

2

A3

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3150

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

VREFDQ

DQ0 DQ1 DQ2 DQ3

DQS

DQS*

CS* CKE

CK

CK*

NC

C10

C3158

0.47UF

CERM-X5R-1

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<40>

C8

MEM_B_DQ<41>

C3

MEM_B_DQ<42>

C9

MEM_B_DQ<43>

E4

MEM_B_DQ<44>

E9

MEM_B_DQ<45>

D3

MEM_B_DQ<46>

E8

MEM_B_DQ<47>

C4

MEM_B_DQS_P<5>

D4

MEM_B_DQS_N<5>

B8 A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

D10

20%

201

1

C3159

0.47UF

4V

20% 4V

2

CERM-X5R-1 201

31 32 90

12 30 31 32 90

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 30 31 32 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30 90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13> MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<6>

2

R3160

240

1% 1/20W MF 201

1

C3167

0.47UF

1

20%

4V

2

A3

K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 J8

J3 K9 J4

F4 G4 H4

G2

H9

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC* A13 A14

A15

BA0 BA1 BA2

RAS* CAS* WE*

ODT

ZQ

A2

A10D8G9G3K2

B2

J2L2N2F3A9D9F9

201

K10M2M10

VDD

OMIT_TABLE

U3160

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

DQS*

CS* CKE

CK*

NC

C10

VREFCA

DQ0 DQ1 DQ2 DQ3

DQS

CK

D10

C3168

0.47UF

CERM-X5R-1

NC

20%

201

H2

NC

H10

NC

N1

NC

N11

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<48>

C8

MEM_B_DQ<49>

C3

MEM_B_DQ<50>

C9

MEM_B_DQ<51>

E4

MEM_B_DQ<52>

E9

MEM_B_DQ<53>

D3

MEM_B_DQ<54>

E8

MEM_B_DQ<55>

C4

MEM_B_DQS_P<6>

D4

MEM_B_DQS_N<6>

B8 A8

NC

H3

MEM_B_CS_L<0>

G10

MEM_B_CKE<0>

F8

MEM_B_CLK_P<0>

G8

MEM_B_CLK_N<0>

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

1

C3169

0.47UF

4V

20% 4V

2

CERM-X5R-1 201

31 32 90

12 30 31 32 90

CERM-X5R-1

MEM_B_A<0>

12 30 31 32 90

MEM_B_A<1>

12 30 31 32 90

MEM_B_A<2>

12 30 31 32 90

MEM_B_A<3>

12 30 31 32 90

MEM_B_A<4>

12 30 31 32 90

MEM_B_A<5>

12 30 31 32 90

MEM_B_A<6>

12 30 31 32 90

MEM_B_A<7>

12 30 31 32 90

MEM_B_A<8>

12 30 31 32 90

MEM_B_A<9>

12 30 31 32 90

MEM_B_A<10>

12 30 90

MEM_B_A<11>

12 30 31 32

MEM_B_A<12>

12 30 31 32 90

MEM_B_A<13> MEM_B_A<14>

12 30 31 32 90

MEM_B_A<15>

12 30 31 32 90

MEM_B_BA<0>

12 30 31 32 90

MEM_B_BA<1>

12 30 31 32 90

MEM_B_BA<2>

12 30 31 32

12 30 32 90

90

MEM_B_RAS_L

12 30 31 32 90

MEM_B_CAS_L

12 30 31 32 90

MEM_B_WE_L

12 30 31 32 90

MEM_B_ODT<0>

12 30 32 90

MEM_B_ZQ<7>

2

R3170

240

1% 1/20W MF 201

1

A

C3100

2.2UF

X5R-CERM

C3140

2.2UF

X5R-CERM

1

C3101

20% 10V

2

402

1

C3141

20% 10V

2

402

1

2.2UF

20% 10V

2

X5R-CERM

402

1

2.2UF

20% 20% 10V

2

X5R-CERM

402

C3110

2.2UF

X5R-CERM

C3150

2.2UF

X5R-CERM

1

20% 10V

2

402

1

10V

2

402

C3111

2.2UF

X5R-CERM

C3151

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3120

2.2UF

X5R-CERM

C3160

2.2UF

X5R-CERM

1

C3121

20% 10V

2

402

1

C3161

20% 10V

2

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3130

2.2UF

X5R-CERM

C3170

2.2UF

X5R-CERM

1

20% 10V

2

402

1

20% 10V

2

402

C3131

2.2UF

X5R-CERM

C3171

2.2UF

X5R-CERM

1

C3103

20% 10V

402

20% 10V

402

0.1UF

10%

2

1

2

6.3V 6.3V

2

X5R 201

1

C3143

0.1UF

10%

6.3V

2

X5R 201

1

C3104

0.1UF

10%

2

X5R 201

1

C3144

0.1UF

10%

6.3V

2

X5R 201

1

C3105

0.1UF

10%

6.3V

2

X5R 201

1

C3145

0.1UF

10%

6.3V

2

X5R 201

1

C3113

0.1UF

10%

6.3V

2

X5R 201

1

C3153

0.1UF

10%

6.3V

2

X5R 201

1

C3114

0.1UF

10%

6.3V

2

X5R 201

1

C3154

0.1UF

10%

6.3V

2

X5R 201

1

C3115

0.1UF

10%

6.3V

2

X5R 201

1

C3155

0.1UF

10%

6.3V

2

X5R 201

1

C3123

0.1UF

10%

6.3V

2

X5R 201

1

C3163

0.1UF

10%

6.3V

2

X5R 201

1

C3124

0.1UF

10%

6.3V

2

X5R 201

1

C3164

0.1UF

10%

6.3V

2

X5R 201

1

C3125

0.1UF

10%

6.3V

2

X5R 201

1

C3165

0.1UF

10%

6.3V

2

X5R 201

1

C3133

0.1UF

10%

6.3V

2

X5R 201

1

C3173

0.1UF

10%

6.3V

2

X5R 201

1

C3134

0.1UF

10%

6.3V

2

X5R 201

1

C3174

0.1UF 0.1UF

10%

6.3V

2

X5R 201

1

2

1

2

C3135

0.1UF

10%

6.3V X5R 201

C3175

10%

6.3V X5R 201

6 3

C3177

0.47UF

1

20%

4V

2

A3

201

A10D8G9G3K2

K4

A0

L8

A1

L4

A2

K3

A3

L9

A4

L3

A5

M9

A6

M3

A7

N9

A8

M4

A9

H8

A10/AP

M8

A11

K8

A12/BC*

N4

A13

N8

A14

J8

A15

J3

BA0

K9

BA1

J4

BA2

F4

RAS*

G4

CAS*

H4

WE*

G2

ODT

H9

ZQ

A2

B2

J2L2N2F3A9D9F9

SYNC_MASTER=D2_KEPLER

PAGE TITLE

K10M2M10

VDD

OMIT_TABLE

U3170

DDR3-1333

(SYM VER 2)

VSS

FBGA

J10

B10C2E3

L10

N10

VDDQ

B3D2B9

E10J9E2

VREFDQ

RESET*

NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7

DM/TDQS

NF/TDQS*

VSSQ

C3178

0.47UF

20%

CERM-X5R-1

201

H2

NC

H10

NC

N1

NC

N11

VREFCA

NC

N3

MEM_RESET_L

B4

MEM_B_DQ<56>

DQ0

C8

MEM_B_DQ<57>

DQ1

C3

MEM_B_DQ<58>

DQ2

C9

MEM_B_DQ<59>

DQ3

E4

MEM_B_DQ<60>

E9

MEM_B_DQ<61>

D3

MEM_B_DQ<62>

E8

MEM_B_DQ<63>

C4

MEM_B_DQS_P<7>

DQS

D4

MEM_B_DQS_N<7>

DQS*

B8 A8

NC

H3

MEM_B_CS_L<0>

CS*

G10

MEM_B_CKE<0>

CKE

F8

MEM_B_CLK_P<0>

CK

G8

MEM_B_CLK_N<0>

CK*

A1

NC

A4

NC

A11

NC

F2

NC

F10

NC

C10

D10

SYNC_DATE=01/13/2012

DDR3 SDRAM Bank B (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

1

4V

2

DRAWING NUMBER

051-9589

REVISION

4.18.0

BRANCH

PAGE

31 OF 132

SHEET

30 OF 99

1

C3179

0.47UF

20% 4V

2

CERM-X5R-1 201

27 28 29 30 31

12 31 90

B

12 31 90

12 30 32 90

A

SIZE

D

124578

Apple MacBook Pro Retina 15 A1398 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual