Apple Macbook Pro 15 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

3456

ECNREV

DESCRIPTION OF REVISION

12

CK APPD

DATE

2010-10-12

SCHEM,FLYING_DUTCHMAN,MLB,K91F

REV B RELEASE, 01/31/11

91 92 93 94 95 96 97 98

99 100 101

(.csa)

101

Memory Constraints

102

PCH Constraints 1

103

PCH Constraints 2

104

Ethernet/FW Constraints

105

T29 Constraints

106

SMC Constraints

107

GPU (Whistler) CONSTRAINTS

108

Project Specific Constraints

109

PCB Rule Definitions

130

DEBUG SENSORS AND ADC

132

Power Supplies BIST

K18_MLB

K92_MLB

K91_ERIC

T29_REF

K18_MLB

K92_MLB

K18_MLB

K91_DINESH

Date

MASTER

06/30/2009

MASTER

05/28/2009

04/27/2010

06/21/2010

08/03/2010

06/15/2010

08/03/2010

06/15/2010

08/19/2010

10/19/2010

07/06/2010

10/20/2010

07/06/2010

04/30/2010

07/06/2010

10/17/2010

10/08/2010

07/06/2010

06/23/2010

05/10/2010

06/23/2010

04/27/2010

10/08/2010

10/12/2010

10/11/2010

05/26/2010

04/27/2010

06/10/2010

11/08/2010

10/08/2010

04/27/2010

07/12/2010

(.csa)

46

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

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50

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51

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52

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53

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54

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55

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56

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57

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58

TABLE_TABLEOFCONTENTS_ITEM

59

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60

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61

TABLE_TABLEOFCONTENTS_ITEM

62

TABLE_TABLEOFCONTENTS_ITEM

63

TABLE_TABLEOFCONTENTS_ITEM

64

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65

TABLE_TABLEOFCONTENTS_ITEM

66

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67

TABLE_TABLEOFCONTENTS_ITEM

68

TABLE_TABLEOFCONTENTS_ITEM

69

TABLE_TABLEOFCONTENTS_ITEM

70

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71

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72

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75

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76

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77

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78

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79

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80

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81

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82

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83

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84

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85

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86

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87

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88

TABLE_TABLEOFCONTENTS_ITEM

89

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90

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51

LPC+SPI Debug Connector

52

SMBus Connections

53

Voltage & Load Side Current Sensing

54

High Side and CPU/AXG Current Sensing

55

Thermal Sensors

56

Fan Connectors

57

WELLSPRING 1

58

WELLSPRING 2

59

Digital Accelerometer

61

SPI ROM

62

AUDIO: CODEC/REGULATOR

63

AUDIO: LINE INPUT FILTER

65

AUDIO: HEADPHONE FILTER

66

AUDIO: SPEAKER AMP

67

AUDIO: JACKS

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

System Agent Supply

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

74

CPU IMVP7 & AXG VCore Regulator

75

CPU IMVP7 & AXG VCore Output

76

CPU VCCIO (1.05V) Power Supply

77

Misc Power Supplies

78

Power FETs

79

Power Control 1/ENABLE

80

Whistler PCI-E

81

Whistler CORE/FB POWER

82

Whistler FRAME BUFFER I/F

84

GDDR5 Frame Buffer A

85

GDDR5 Frame Buffer B

86

Whistler LVDS/DP/GPIO

87

Whistler GPIOs & STRAPs

88

Whistler DP PWR/GNDs

89

GPU (Whistler) CORE SUPPLY

90

LVDS Display Connector

92

Muxed Graphics Support

93

DisplayPort/T29 A MUXing

94

DisplayPort/T29 A Connector

95

1V0 GPU / 1V5 FB Power Supply

96

Graphics MUX (GMUX)

97

LCD Backlight Driver

99

Power Sequencing EG/PCH S0

100

CPU Constraints

Sync

K18_MLB

K91_DINESH

K18_MLB

K91_ERIC

K91_DINESH

K91_BEN

K91_AUDIO

K91_ERIC

K91_CHANG

K91_ERIC

K91_MARY

K92_SUMA

K92_MLB

K92_SUMA

K91_ERIC

K18_MLB

K92_MLB

T29_REF

K91_ERIC

K91_MARY

K90I_KIRAN

K91_MARY

K92_MLB

Date

04/27/2010

08/16/2010

10/29/2010

09/22/2010

04/27/2010

10/08/2010

07/14/2010

08/06/2010

06/08/2010

09/30/2010

07/12/2010

09/30/2010

09/21/2010

10/08/2010

07/20/2010

10/08/2010

09/22/2010

10/08/2010

11/01/2010

10/14/2010

07/22/2010

06/15/2010

08/03/2010

08/19/2010

12/01/2010

11/23/2010

06/15/2010

12/21/2010

04/27/2010

11/21/2010

10/16/2010

10/08/2010

08/03/2010

06/25/2010

08/03/2010

08/09/2010

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

Page SyncContents

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

(.csa)

1

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

Revision History

5

BOM Configuration

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU DMI/PEG/FDI/RSVD

11

CPU CLOCK/MISC/JTAG

12

CPU DDR3 INTERFACES

13

CPU POWER

14

CPU POWER AND GND

16

CPU DECOUPLING-I

17

CPU DECOUPLING-II

18

PCH SATA/PCIE/CLK/LPC/SPI

19

PCH DMI/FDI/GRAPHICS

20

PCH PCI/FLASHCACHE/USB

21

PCH MISC

22

PCH POWER

23

PCH GROUNDS

24

PCH DECOUPLING

25

CPU & PCH XDP

26

USB HUBS

28

Chipset Support

29

DDR3 SO-DIMM Connector A

30

DDR3 Byte/Bit Swaps

31

DDR3 SO-DIMM Connector B

32

CPU Memory S3 Support

33

FSB/DDR3/FRAMEBUF Vref Margining

34

X19/ALS/CAMERA CONNECTOR

35

SD READER CONNECTOR

36

T29 Host (1 of 2)

37

T29 Host (2 of 2)

38

T29 Power Support

39

ETHERNET PHY (CAESAR IV)

40

Ethernet Connector

41

FireWire LLC/PHY (FW643)

42

FireWire Port & PHY Power

43

FireWire Connector

45

SATA/IR/SIL Connectors

46

External USB Connectors

48

Front Flex Support

49

SMC

50

SMC Support

ContentsPage

Sync ContentsPage

MASTER

K17_REF

MASTER

K17_REF

K18_MLB

K92_SUMA

K92_MLB

K92_SUMA

K92_MLB

K92_SUMA

K92_MLB

K91_MLB

K92_MLB

K91_MLB

K92_MLB

K91_MLB

K91_ERIC

K92_MLB

K92_SUMA

K18_MLB

K91_MARY

K91_ERIC

T29_REF

K91_ERIC

K91_TRINHNI

K18_MLB

T27_REF

K91_ERIC

K18_MLB

K91_BEN

D

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

C

B

TABLE_TABLEOFCONTENTS_ITEM

Date

04/27/2010

08/09/2010

08/03/2010

10/16/2010

04/27/2010

08/09/2010

04/27/2010

08/06/2010

08/18/2010

D

C

B

A

ALIASES RESOLVED

Schematic / PCB #’s

PART NUMBER

051-8620

820-2915

DRAWING

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Mon Jan 31 12:49:37 2011

QTY

1

8 7 6 5 4 2 1

DESCRIPTION

SCHEM,MLB,K91

PCBF,MLB,K91

REFERENCE DES

SCH

PCB

CRITICAL

BOM OPTION

SIZE

A

D

DRAWING TITLE

SCHEM,MLB,K91

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

1 OF 132

SHEET

1 OF 101

3

345678

2 1

2 DIMMS

RTC

PG 16

J2500,J2550

XDP CONN

J3100

J2900

DIMM

PG 26,28

PG 23

U6100

J6950

U4900

DC/BATT

PG 63

D

POWER SUPPLY

U8000

GRAPHICS

AMD WHISTLER

PG 73

INTEL CPU

2.X GHZ

SANDY BRIDGE

PG 9

DDR3-1067/1333MHZ

D

GPIO

PG 19

FDI

PG 17

DMI

PG 17

SPI

CLOCK

U2700

CK5G05

PG 24

J4501

SATA

ODD

CONN

PG 41

J4500

SATA

C

HDD

CONN

PG 41

CLK

BUFFER

PG 16

SATA2.0/3(GB/S)

4 5

SATA

SATA2.0/3(GB/S)

PG 16

SATA2.0/3(GB/S)

2 3

SATA3.0/6(GB/S)

10

SATA3.0/6(GB/S)

INTEL

COUGAR-POINT

MOBILE

U1800

Misc

PG 19

SPI

PG 16

LPC

PG 16

J5100

LPC + SPI CONN Port80,serial

PWR

DP OUT

U9320

DP MUX

XP25-5G

PG 83

J9400

MINI DP PORT

PG 84

U9370

B

DDC MUX

PG 83

RGB OUT

HDMI OUT

DVI OUT

LVDS OUT

TMDS OUT

PG 18

PCI

PG 18

JTAG

PG 16

PEG

PG 16

PCI-E

(UP TO 16 LINES)

PG 16

CTRL

PG 17

1011 1312 98 654 73210

PG 18

USB

(UP TO 14 DEVICES)

SMB

PG 16

HDA

PG 16

LCD PANEL

Boot ROM

PG 55

PG 46

U3600

USB

HUB 2

PG 33

U3700

USB

HUB 1

PG 34

DIMM

PG 26,28

Ser Prt

U4900

J3402

CAMERA

J4501

IR

J4610

EXTERNAL B

EXTERNAL C

(RESERVATION)

J5713

TRACKPAD/KEYBOARD

J3401

BLUETOOTH

J4600

EXTERNAL A

ADC

BSBB,0

SMC

PG 44

PG 31

PG 41

PG 33

PG 53

PG 31

PG 34

Fan

CONNECTION

TEMP SENSOR

PG 44

POWER SENSE

PG 44

J5650,5660

FAN CONN AND CONTROL

PG 51

SMBUS

PG 47

C

B

U9600

GMUX

PG 86

U4100

A

J3401

FW643

PG 38

AirPort

J4310PG 31

FIREWIRE

CONN

PG 40

U3900

BCM57765

J4000

GB

E-NET

PG 36

E-NET

CONN

PG 37

J3500

SDCARD READER

CONN

PG 37

8 7 5 4 2 1

LINE TIN

FILTER

PG 57

U6201

J6700,J6750

AUDIO CODEC

PG 56

HEADPHONE

FILTER

PG 58

AUDIO

CONN

PG 60

U6610,6620,6630

SPEATKER

AMP

PG 59

SPEATKER

PG 63

SIZE

A

D

SYNC_MASTER=K17_REF

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=06/30/2009

DRAWING NUMBER

REVISION

BRANCH

PAGE

2 OF 132

SHEET

2 OF 101

36

345678

2 1

D

C

B

A

J6900

AC

ADAPTER

IN

J6950

3S2P

(9 TO 12.6V)

GMUX

U9600

XP25-5

(PAGE 86)

SMC

U4900

P60

(PAGE 44)

COUGAR-POINT

MOBILE

SLP_S5#(E4)

U1800

SLP_S4#(H7)

SLP_S3#(P12)

(PAGE 16~21)

DELAY

8 7 5 4 2 1

DCIN(16.5V)

PPVBATT_G3H_CONN

EG_RAIL1_EN

PB16B

EG_RAIL2_EN

PB17A

EG_RAIL3_EN

PB17B

EG_RAIL4_EN

PB18A

PL32A

SMC_PM_G2_EN

P1V8S0_EN

RC

P1V2S0_EN

RC

CPUVTTS0_EN

RC

P1V5CPU_EN

RC

K91 POWER SYSTEM ARCHITECTURE

F6905 6A FUSE

SMC_DCIN_ISENSE

PM_ALL_GPU_PGOOD

RC

DELAY

PM_SLP_S5_L

RC

P5VS3_EN

DELAY

RC

DDRREG_EN

DELAY

P3V3S3_EN

PM_SLP_S4_L

PM_SLP_S3_L

R7978

PM_SLP_S3_L_R

PP18V5_DCIN_CONN

R7020

A

SMC_RESET_L

CHGR_BGATE

P1V1GPU_EN

P3V3GPU_EN

GPUVCORE_EN

P3V3S5_EN

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

U7000

VIN

ISL6259HRTZ

PBUS SUPPLY/

BATTERY CHARGER

(PAGE 64)

Q7055

R6990

VOUT

SMC_BATT_ISENSE

PPVBAT_G3H_CHGR_R

P1V0GPU_EN

P1V5FB_EN

Q9806

BKLT_PLT_RST_L

&&

LCD_BKLT_NO

BKLT_EN

Q4260

SMC_ADAPTER_EN&&PM_SLP_S3_L

PPVBAT_G3H

R7050

EN1

1.003V(L/H)

EN2

1.503V(R/H)

ISL6236

U9500

(PAGE 85)

ENA

A

VIN

P5VS3_EN

P3V3S5_EN

LP8550

U9701

(PAGE 87)

PFWBOOST

VOUT1

VOUT2

POK1

POK2

VIN

PPBUS_G3H

F7040

8A FUSE

PP1V0_S0GPU_REG

R5413

A

P1V0GPU_PGOOD

P1V5FB_PGOOD

PPVOUT_S0_LCDBKLT

VOUT

D6990

PPBUS_G3H

PP1V5_GPU_REG

SMC_GPU_1V8_ISENSE

P1V5CPU_EN

VIN

VREG5

EN1

EN2

PGOOD

VOUT1

5V

(L/H)

VOUT2

3.3V

(R/H)

TPS51125

U7201

(PAGE 65)

P5V3V3_PGOOD

SMC_PBUS_VSENSE

V

PP5V_S3_GFXIMVP6_VDD

GPUVCORE_EN

SMC_CPU_HI_ISENSE

PP5V_S3_DDRREG

DDRREG_EN

DDRVTT_EN

PP1V5_S3

VIN

ON

PP5V_S3

PP3V3_S5

SLG5AP020

U7801

G

Q5315

VDD

VR_ON

S5

S3

(PAGE 66)

P1V5S0FET_GATE

PP3V3_S5

Q7870

P3V3GPU_EN

Q7810

P3V3S3_EN

Q7830

P3V3S0_EN

P1V8_S0_EN

P1V2ENET_EN

VIN

GPU VCORE

ISL6263C

U8900

(PAGE 82)

R5388/U5388

A

CPUIMVP7_VR_ON

VIN

VLDOIN

1.5V

VOUT1

0.75V

VOUT2

TPS51116

U7300

Q7801

PP3V3_S0GPU

PP3V3_S3

PP3V3_S0_FET

EN

ENABLE

3.425V G3HOT

PM6640

U6990

(PAGE 62)

VOUT

SMC_GPU_ISENSE

PGOOD

GPUVCORE_PGOOD

PPVTT_S0_DDR_LDO

DDRREG_PGOOD

PGOOD

PP1V5_S3RS0

TPS22924

U4201

(PAGE 39)

EN

VIN

ISL8014A

U7720

(PAGE 70)

VIN

ISL8014A

EN

U7760

(PAGE 70)

A

U5410

CPU VCORE

VIN

ISL95831

U7400

VR_ON

(PAGE 67)

PPDDR_S3_REG

Q7860

P1V8FB_EN

PP3V3_FW_FWPHY

FW_PWR_EN

PP1V8_S0

VOUT

P1V8S0_PGOOD

PGOOD

PP1V2_ENET

VOUT

P1V2ENET_PGOOD

PGOOD

PP3V42_G3H

SMC_GPU_VSENSE

V

PPVCORE_GPU

VOUT

PGOOD

A

SMC_CPU_ISENSE

CPUIMVP7_AXG_PGOOD

R7350

SMC_DDR_ISENSE

A

PP3V3_S0

PP5V_S0

P5VS0_EN

PP1V8_S0

VIN

ON

G

SLG5AP020

U7880

P1V8GPUIFPXFET_GATE

Q7922

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

PP3V3_ENET

Q7850

PP1V2_S0

P1V2S0_EN

V

U5440

SMC_CPU_DDR_VSENSE

Q7880

PP3V3_S0

PP1V5_S0

PP1V05_S0

SMC PWRGD

NCP303LSN

U5000

(PAGE 45)

PP5V_S0_CPUVTTS0

CPUVTTS0_EN

SMC_CPU_VSENSE

PPVCORE_S0_CPU

V

PP1V5_S3

4.5V

VIN

MAX8840

VOUT

U6200

EN

PM_ALL_GPU_PGOOD

PP1V8_GPUIFPX

S0PGOOD_PWROK

PP3V3_S0

V2MON

ISL88042IRTJJZ

V3MON

V4MON

TRST = 200mS

36

SMC_RESET_L

VIN

1.05V

ISL95870

U7600

EN

(PAGE 70)

PP4V5_AUDIO_ANALOG

U7980

PP3V3_S0_PWRCTL

P1V8S0_PGOOD

P5V3V3_PGOOD

VCC

U7971

RST*

(PAGE 72)

SMC AVREF SUPPLY

VIN

REF3333

(PAGE 45)

VOUT

CPUVTTS0_PGOOD

PGOOD

PM_PCH_PWRGD

U2850

ALL_SYS_PWRGD

RSMRST_PWRGD

SMC_ONOFF_L

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

VOUT

PP3V3_S5_AVREF_SMC

R7640

PPCPUVTT_S0

A

SMC_CPU_FSB_ISENSE

COUGAR_POINT

PS_PWRGD

U1800

(PAGE 16~21)

CPU

U1000

(PAGE 9~14)

SMC_TPAD_RST_L

SMC_ONOFF_L

PWRBTN#

SYS_RERST#

RSMRST#

ACPRESENT

PLTRST#

PROCPWRGD

DRAMPWROK

SM_DRAMPWROK

VCCCPUPWRGD

RESET*

SMC

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

SYNC_MASTER=K17_REF

PAGE TITLE

(P64)

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

H8S2117

U4900

(PAGE 45)

SYSRST(PA2)

P17(BTN_OUT)

RES*

Power Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

PP3V3_S5_SMC

U5001

TPS22924

U4202

(PAGE 39)

EN

FW_PWR_EN

PM_PWRBTN_L

PLT_RERST_L

CPU_PWRGD

PM_MEM_PWRGD

SMC_ADAPTER_EN

PM_RSMRST_L

CPUIMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

PP1V0_FW_FWPHY

SYNC_DATE=06/30/2009

DRAWING NUMBER

REVISION

BRANCH

PAGE

3 OF 132

SHEET

3 OF 101

SIZE

D

C

B

A

D

345678

2 1

D

C

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=MASTER

PAGE TITLE

Revision History

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

REVISION

BRANCH

PAGE

4 OF 132

SHEET

4 OF 101

345678

2 1

BOM Variants

BOM NUMBER

639-1468

639-1972

639-1971

639-1469

639-1970

D

639-1956

639-1470

639-1974

639-1976

639-1471

639-1973

639-1954

639-1573

639-1945

639-1953

639-1574

639-1959

639-1960

085-1901

K91 BOM GROUPS

BOM GROUP

K91_COMMON

C

B

A

K91_COMMON1

K91_COMMON2

K91_PVT

K91_PROGPARTS

K91_PROGPARTS1

K91_DEVEL:ENG

K91_DEVEL:PVT

SNB_CPT_XDP

Module Parts

PART NUMBER

337S4031

337S4032

337S4033

337S4029 CRITICAL

337S3936

337S3979 CRITICAL

338S0945

343S0534

343S0494

333S0543

333S0564

333S0571

333S0543

333S0564 CRITICAL

353S3055

725-1479

516S0806

516-0246

516S0805

516-0245

516S0805

516-0246

ETHERNET ROM

335S0663

341S2685

341S2973

341S3026

341S3096 CRITICAL

8 7 5 4 2 1

BOM NAME

PCBA,MLB,K91F,DG64

PCBA,MLB,K91F,DL83

PCBA,MLB,K91F,DL82

PCBA,MLB,K91F,DG65

PCBA,MLB,K91F,DL86

PCBA,MLB,K91F,DL7W

PCBA,MLB,K91F,DG66

PCBA,MLB,K91F,DL87

PCBA,MLB,K91F,DL88

PCBA,MLB,K91F,DG67

PCBA,MLB,K91F,DL81

PCBA,MLB,K91F,DL7T

PCBA,MLB,K91,DHMV

PCBA,MLB,K91,DL7Q

PCBA,MLB,K91,DL7R

PCBA,MLB,K91,DHMW

PCBA,MLB,K91,DL80

PCBA,MLB,K91,DL7Y

K91/K91F DEVELOPMENT BOM

ALTERNATE,COMMON,K91_COMMON1,K91_COMMON2,K91_PROGPARTS,K91_PROGPARTS1,UVGLUE_K91_K91F,K91_PVT

SNB_CPT_XDP,BMON:ENG,GMUX_JTAG_CONN,VREFMRGN,LPCPLUS_CONN:YES,LPCPLUS_R:YES,BKLT:ENG,S0PGOOD_ISL,CPURIPPLE_ENG,IMVPISNS_ENG,ISNS_ON:YES,DEBUG_ADC,DIGI_MIC

QTY

1

4

2

1

DESCRIPTION

IC,CPU,SNB,SR030,PRQ,D2,2.0,45W,4+2,1.20,6M,BGA

IC,CPU,SNB,SR00W,PRQ,D2,2.2,45W,4+2,1.30,6M,BGA

IC,CPU,SNB,SR00U,PRQ,D2,2.3,45W,4+2,1.30,8M,BGA

IC,PCH,COUGARPOINT,SLH9D,PRQ,BD82HM65

IC,GPU,AMD,WHISTLER,962FCBGA,40NM,ES

IC,GPU,AMD,SEYMOUR,M2 LP,ES1,962BGA

IC,ASSP,LIGHTRIDGE,S LHAJ,PRQ,FCBGA,15X15MM

IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN8X8,B0

IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN8X8,A0

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

IC,SGRAM,GDDR5,32MX32.1.25GHz,E-DIE,HF

IC,SDRAM,GDDR5,32MX32,1.25GHz,A-DIE1.35V

IC,SGRAM,GDDR5,64MX32,3.6GBPS,C-DIE,HF

IC,SGRAM,GDDR5,64MX32,3.6GBPS,M-DIE,HF

IC,SGRAM,GDDR5,32MX32.1.25GHz,E-DIE,HF

IC,SDRAM,GDDR5,32MX32,1.25GHz,A-DIE1.35V

IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN

MLB LOCTITE UV EB CPU,PCH,T29,GPU,K91

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN

CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX

CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,MOLEX

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX

CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN

IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC

IC,ENET,1MBITFLASH,CIV REV01,K74/K75,K40

IC,ENET,1MBITFLASH,CIV REV01,K60/K62

IC,ENET,1MBITFLASH,CIV REV01,K90i/K91/K92

IC,ENET ROM,1MBIT,DVT,PVT,K90i/K91x

BOM OPTIONS

K91_COMMON,SODIMM:FOXCONN,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DG64

K91_COMMON,SODIMM:HYBRID,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DL83

K91_COMMON,SODIMM:MOLEX,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DL82

K91_COMMON,SODIMM:FOXCONN,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DG65

K91_COMMON,SODIMM:HYBRID,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DL86

K91_COMMON,SODIMM:MOLEX,CPU:2_2GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DL7W

K91_COMMON,SODIMM:FOXCONN,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DG66

K91_COMMON,SODIMM:HYBRID,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DL87

K91_COMMON,SODIMM:MOLEX,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_HYNIX,VRAM_DVP1,VRAM_DVP0,EEEE:DL88

K91_COMMON,SODIMM:FOXCONN,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DG67

K91_COMMON,SODIMM:HYBRID,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DL81

K91_COMMON,SODIMM:MOLEX,CPU:2_3GHZ,GPU:WHISTLER,FB_1G_SAMSUNG,VRAM_DVP0,EEEE:DL7T

K91_COMMON,SODIMM:FOXCONN,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_HYNIX,EEEE:DHMV

K91_COMMON,SODIMM:HYBRID,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_HYNIX,EEEE:DL7Q

K91_COMMON,SODIMM:MOLEX,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_HYNIX,EEEE:DL7R

K91_COMMON,SODIMM:FOXCONN,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_SAMSUNG,EEEE:DHMW

K91_COMMON,SODIMM:HYBRID,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_SAMSUNG,EEEE:DL80

K91_COMMON,SODIMM:MOLEX,CPU:2_0GHZ,GPU:SEYMOUR,FB_256_SAMSUNG,EEEE:DL7Y

K91_DEVEL:ENG

BOM OPTIONS

CPUMEM_S0,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_2NONREM,USBHUB_2513B

GPUVID_1P11V,KB_BL,T29:YES,ENET_SD:B0,T29BST:Y,SDRV_PD,SDRVI2C:MCU,T29_DP_HPD:ALL_OR

BMON:PROD,VREFMRGN_NOT,XDP,XDP_CPU_BPM,BKLT:PROD,ISNS_ON:NO,LPCPLUS_R:YES

GMUX_PROG,IR_PROG,TPAD_PROG:PVT,ENETROM_PROG:PVT,T29ROM:PROG,T29MCU:PROG

SMC_PROG:PVT,BOOTROM_PROG:PVT

SNB_CPT_XDP,LPCPLUS_CONN:YES,LPCPLUS_R:YES

XDP,XDP_CONN,XDP_CPU_BPM,XDP_PCH

REFERENCE DES

U1000

U1800

U8000

U3600

U3900

U4100

U8400,U8450,U8500,U8550

U8500,U8550

U9390

UV_GLUE_K91_K91F

J3100

J2900

J3100

J2900

J3100

J2900

U3990

CRITICAL

CRITICAL338S0753

CRITICAL

CRITICAL333S0572

CRITICAL

BOM OPTION

CPU:2_0GHZ

CPU:2_2GHZ

CPU:2_3GHZ

GPU:WHISTLER

GPU:SEYMOUR

T29:YES

ENET_SD:B0

ENET_SD:A0

FB_512_SAMSUNG

FB_512_HYNIX

FB_1G_SAMSUNG

FB_1G_HYNIX

FB_256_SAMSUNG

FB_256_HYNIX

UVGLUE_K91_K91F

SODIMM:FOXCONN

SODIMM:MOLEX

SODIMM:HYBRID

ENETROM_BLANK

ENETROM_PROG:A0_SD

ENETROM_PROG:B0_SD

ENETROM_PROG:EVT

ENETROM_PROG:PVT

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

|

Alternate Parts

(Alternate)

PART NUMBER

157S0058

152S0896

155S0457

353S2805 353S2603

128S0264 128S0257

128S0303 128S0282

353S3085 353S1658

376S0972 376S0612

376S0855 376S0613

138S0676

138S0652

152S0685

353S2592

335S0550

138S0671 138S0673

EFI ROM

335S0740

341S2934 CRITICAL

341S2991

341S2894 CRITICAL

341S2895

341S2896

PSOC

341S2902

341S2940

341S3001

341S3024

341S3099

(Primary)

ALTERNATE FOR PART NUMBER

157S0055

152S0518

155S0329

138S0691

138S0648

138S0638138S0681

152S0796

376S0859376S0977

353S3199

335S0777

371S0652371S0679

1

BOM OPTION

REF DES

ALL

64 MBIT SPI SERIAL DUAL I/O FLASH

IC,EFI,ROM,PROTO0, K90/K90I/K91/K91F/K92

IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92

IC,EFI,ROM,PROTO2, K90/K90I/K91/K91F/K92

IC,EFI,ROM,EVT, K90/K90I/K91/K91F/K92

IC,EFI,ROM,DVT, K90/K90I/K91/K91F/K92

IC,EFI,ROM,PVT, K90/K90I/K91/K91F/K92

IC,TP PSOC,K9x,PROTO0

IC,TP PSOC,K9x,PROTO1

IC,TP PSOC,K9x,PROTO2

IC,TP PSOC,K9x,EVT

IC,TP PSOC,K9x,DVT,PVT

COMMENTS:

Delta alt to TDK Magnetics

MAG LAYERS ALT TO CYNTEC

MAG LAYERS ALT TO MURATA

Fairchild wafer option

Sanyo alt to Kemet

Panasonic alt to Sanyo

ST Micro alt to LT

ROHM alt to Toshiba N-FET

Diodes alt to Toshiba dual N-FET

Murata alt to Samsung cap

Samsung / Murata alt for Taiyo Yuden

Taiyo Yuden alt for Samsung

Dale/Vishay/TDK alt for Cyntec

Diodes alt for Rohm

U6201 AUDIO CODEC OLD REV IS ALTERNATE FOR NEW REV

add 4K byte as alternative to 2K

NXP alternate for pin diodes

Taiyo Yuden alt for Murata 10 uF caps

Bar Code Labels

PART NUMBER

826-4393

QTY

1

826-4393

1

826-4393

826-4393 CRITICAL

826-4393

1

826-4393

826-4393 CRITICAL

826-4393

1

826-4393

826-4393 CRITICAL

826-4393

1

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM

/ EEEE #’s

REFERENCE DES

[EEEE_DDKG]

[EEEE_DG63]

[EEEE_DG64]

[EEEE_DG65]

[EEEE_DG66]

[EEEE_DG67]

[EEEE_DHMV]

[EEEE_DHMW]

[EEEE_DL81]

[EEEE_DL82]

[EEEE_DL83]

[EEEE_DL84]

[EEEE_DL85]

[EEEE_DL86]

[EEEE_DL87]

[EEEE_DL88]

[EEEE_DL89]

[EEEE_DL7Q]

[EEEE_DL7R]

[EEEE_DL7T]

[EEEE_DL7V]

[EEEE_DL7W]

[EEEE_DL7Y]

[EEEE_DL80]

CRITICAL

CRITICAL826-4393

CRITICAL

CRITICAL826-4393

CRITICAL

CRITICAL826-4393

CRITICAL

CRITICAL826-4393

CRITICAL

BOM OPTION

EEEE:DDKG

EEEE:DG63

EEEE:DG64

EEEE:DG65

EEEE:DG66

EEEE:DG67

EEEE:DHMV

EEEE:DHMW

EEEE:DL81

EEEE:DL82

EEEE:DL83

EEEE:DL84

EEEE:DL85

EEEE:DL86

EEEE:DL87

EEEE:DL88

EEEE:DL89

EEEE:DL7Q

EEEE:DL7R

EEEE:DL7T

EEEE:DL7V

EEEE:DL7W

EEEE:DL7Y

EEEE:DL80

D

C

Programmables - All Builds

TABLE_ALT_HEAD

TABLE_ALT_ITEM

U6100

U5701

341S2830 CRITICAL

335S0777 CRITICAL

341S3128

341S2957

1

IC,CPLD,LATTICE,GMUX,K91/K91F

IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA

IR,ENCORE II,CY7C63833-LFXC

IC,T29 EEPROM,PVT,K9x

IC,EEPROM,SERIAL,8KB,SOIC

IC,PROGRMD,LPC1112A,T29 PORT MCU,PVT,HVQFN25

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

IC,GPU ROM,K91/F,K92,PROG

IC,GPU ROM,K91/F,K92,BLANK

U9600

U4800

U3690

U9330

U8701

SMC

338S0895

341S2935

341S2994

341S2864

341S2867

CRITICAL

CRITICAL341S2893

CRITICAL

1

BOOTROM_BLANK

BOOTROM_PROG:PROTO0

BOOTROM_PROG:PROTO1

BOOTROM_PROG:PROTO2

BOOTROM_PROG:EVT

BOOTROM_PROG:DVT

BOOTROM_PROG:PVT

TPAD_PROG:PROTO0

TPAD_PROG:PROTO1

TPAD_PROG:PROTO2

TPAD_PROG:EVT

TPAD_PROG:PVT

IC,SMC,HS8/2117,9MMX9MM,TLP

IC,SMC,DEVELOPMENT-PROTO0,K91

IC,SMC,DEVELOPMENT-PROTO1,K91

IC,SMC,DEVELOPMENT-PROTO2,K91

IC,SMC,DEVELOPMENT-EVT,K91

IC,SMC,DEVELOPMENT-DVT,K91

IC,SMC,DEVELOPMENT-PVT,K91

SYNC_MASTER=K17_REF

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

U4900

BOM Configuration

Apple Inc.

R

CRITICAL336S0042

CRITICAL341S2384

CRITICAL341S3129

CRITICAL

CRITICAL337S3997

CRITICAL

CRITICAL335S0724

CRITICAL

CRITICAL341S2854

CRITICAL

CRITICAL341S2861

CRITICAL

GMUX_PROG

GMUX_BLANK

IR_PROG

T29ROM:PROG

T29ROM:BLANK

T29MCU:PROG

T29MCU:BLANK

GPUROM:PROG

GPUROM:BLANK

SMC_BLANK

SMC_PROG:PROTO0

SMC_PROG:PROTO1

SMC_PROG:PROTO2

SMC_PROG:EVT

SMC_PROG:DVT

SMC_PROG:PVT

SYNC_DATE=05/28/2009

DRAWING NUMBER

REVISION

BRANCH

PAGE

5 OF 132

SHEET

5 OF 101

SIZE

B

A

D

36

345678

J5713 (KEY BOARD CONN)

Functional Test Points

J5650 (LEFT FAN CONN)

FUNC_TEST

TRUE

TRUE TRUE

PP5V_S0

FAN_LT_PWM FAN_LT_TACH

J5660 (RIGHT FAN CONN)

D

I1493

TRUE TRUE TRUE TRUE

PP5V_S0 FAN_RT_PWM FAN_RT_TACH GND

J6780 (MIC CONN)

I557

I558

I559

TRUE TRUE

BI_MIC_SHIELD BI_MIC_P

BI_MIC_N

TRUE

J6781 & J6782 (SPEAKERS CONN)

SPKRCONN_L_OUT_P

TRUE

I989

I990

I992

I991

I994

I993

C

TRUE

I995

TRUE

I996

TRUE

I997

TRUE

I998

TRUE

I1000

TRUE

I1001

TRUE

I1002

TRUE

I1004

TRUE

I1003

TRUE

I1005

TRUE

I1007

TRUE

I1006

TRUE

I1009

TRUE

I1008

TRUE

I1010

TRUE

I1011

TRUE

I1012

TRUE

I1014

TRUE

I1013

TRUE

I1015

TRUE

I1016

TRUE

I1017

TRUE

I1018

TRUE

B

A

I1019

TRUE

I1020

TRUE

I1022

TRUE

I1021

TRUE

I1024

TRUE

I1026

TRUE

I1025

TRUE

I1028

TRUE

I1027

TRUE

I1029

TRUE

I1494

TRUE

I1495

TRUE

I1032

TRUE

I1031

TRUE

I1033

TRUE

I1035

TRUE

I1034

TRUE

J5815 (KBD BACKLIGHT CONN)

TRUE

I1145

TRUE

I1146

TRUE

FUNC_TEST

TRUE

SPKRCONN_L_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_S_OUT_P

TRUE

SPKRCONN_S_OUT_N

TRUE

J9000 (LVDS CONN)

PP3V3_SW_LCD PP3V3_S0 PPVOUT_S0_LCDBKLT LVDS_DDC_CLK LVDS_DDC_DATA LVDS_CONN_A_DATA_P<0> LVDS_CONN_A_DATA_N<0> LVDS_CONN_A_DATA_P<1> LVDS_CONN_A_DATA_N<1> LVDS_CONN_A_DATA_P<2> LVDS_CONN_A_DATA_N<2> LVDS_CONN_A_CLK_F_P LVDS_CONN_A_CLK_F_N LVDS_CONN_B_DATA_P<0> LVDS_CONN_B_DATA_N<0> LVDS_CONN_B_DATA_P<1> LVDS_CONN_B_DATA_N<1> LVDS_CONN_B_DATA_P<2> LVDS_CONN_B_DATA_N<2> LVDS_CONN_B_CLK_F_P LVDS_CONN_B_CLK_F_N LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6

GND

J4500 (SATA ODD CONN)

PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N

TRUE

GND

J4501 (SATA HDD CONN)

PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_N SATA_HDD_D2R_C_P

GND

KBDLED_ANODE SMC_KDBLED_PRESENT_L

GND

TRUE

6 TPs

101 67 68 69 71 6 7 8

22 41 46 51 53 64 72 86 88

51

2 TPs

101 6 7 8

22 41 46 51 53 64 67 68 69 71 72 86 88

51

60 61

59 60 98

82 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83

8

2 TP needed

82 88

100

82 83

82 83 97

82 97

82 83 97

82 97

82 88

4 TPs

41

41 44

41

41 92

3 TPs

41 92

5 TPs

41

41 92

53

GND

3 TPs per Fan

5 TPs per Fan

J3401 & J3402 (AIRPORT/BT/CAMERA CONN)

TRUE

I1038

TRUE

I1039

TRUE

I1040

TRUE

I1042

TRUE

I1043

TRUE

I1044

TRUE

I1051

TRUE

I1050

TRUE

I1053

TRUE

I1052

TRUE

I1054

TRUE

I1056

TRUE

I1055

TRUE

I1058

TRUE

I1496

TRUE

I1057

TRUE

I1059

TRUE

I1061

TRUE

I1060

TRUE

I1063

TRUE

I1062

TRUE

I1064

TRUE

I1066

TRUE

I1065

TRUE

I1497

TRUE

I1498

J6950 (BAT CONN)

TRUE

I1510

J5800 (IPD FLEX CONN)

TRUE

I1509

TRUE

I1086

TRUE

I1508

TRUE

I1273

TRUE

I1089

TRUE

I1088

TRUE

I1090

TRUE

I1464

TRUE

I1098

TRUE

I1097

TRUE

I1095

TRUE

I1096

TRUE

I1092

TRUE

I1093

TRUE

I1094

TRUE

I1099

TRUE

I1100

TRUE

I1101

J6900 (DC POWER CONN)

TRUE

I1131

TRUE

I1132

TRUE

J6950 (MAIN BATT CONN)

TRUE

I1134

TRUE

I1136

TRUE

I1135

TRUE

I1137

TRUE

J6995 (BAT LED CONN)

TRUE

I1140

TRUE

I1142

TRUE

I1141

TRUE

I1143

TRUE

USB PORTS

PP5V_S3_RTUSB_A_F USB2_LT1_N USB2_LT1_P

GND

PP5V_S3_RTUSB_B_F USB_LT2_N USB_LT2_P

GND

PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N AP_CLKREQ_Q_L PCIE_WAKE_L WIFI_EVENT_L AP_RESET_CONN_L PP3V3_WLAN PP5V_S3_ALSCAMERA_F SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL USB_CAMERA_CONN_P USB_CAMERA_CONN_N CONN_USB2_BT_P CONN_USB2_BT_N SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA

SYS_DETECT_L

PP18V5_S4 Z2_HOST_INTN Z2_MOSI Z2_CS_L Z2_DEBUG3 Z2_MISO Z2_BOOST_EN Z2_SCLK Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_F_CS_L PICKB_L PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

ADAPTER_SENSE PP18V5_DCIN_FUSE

GND

PPVBAT_G3H_CONN SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA NC_SMC_BS_ALRT_L

GND

PP3V42_G3H SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL SMC_BIL_BUTTON_L

GND

42

42 98

42

42 98

16 31 93

31 93

31 98

31

17 25 31 84

31 44 45

31

31 45

31

6

31 44 47 53 54 96

6

31 44 47 53 54 96

31 92

98

31 44 47 50 79 96

62

53

52 53

53

52 53

6

31 44 47 53 54 96

6

31 44 47 53 54 96

62

62 63

6

44 47 62 63 96

6

44 47 62 63 96

6

6 7

25 42 44 45 46 47 52

62 63 72

6

44 47 62 63 96

6

44 47 62 63 96

44 45 62

I1103

I1102

I1104

I1105

I1107

I1106

I1108

I1109

I1110

I1111

I1112

I1113

I1114

I1115

I1117

I1116

I1118

I1119

I1120

I1122

I1121

I1123

I1124

I1125

I1127

I1126

I1128

I1129

I1130

I1150

I1149

I1151

I1152

PP3V3_S3

TRUE

PP3V42_G3H

TRUE

WS_KBD1

TRUE

WS_KBD2

TRUE

WS_KBD3

TRUE

WS_KBD4

TRUE

WS_KBD5

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD10

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

WS_KBD13

TRUE

WS_KBD14

TRUE

WS_KBD15_CAP

TRUE

WS_KBD16_NUM

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD19

TRUE

WS_KBD20

TRUE

WS_KBD21

TRUE

WS_KBD22

TRUE

WS_KBD23

TRUE

WS_KBD_ONOFF_L

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_CONTROL_KBD

TRUE

J6950 (BIL CABLE CONN)

PP5V_S3_IR_R

TRUE

SMC_LID_R

TRUE

IR_RX_OUT

TRUE

SYS_LED_ANODE

TRUE

POWER RAILS

FUNC_TEST

TRUE

I640

TRUE

I602

TRUE

I603

TRUE

I604

TRUE

I605

TRUE

I607

TRUE

I606

TRUE

I610

TRUE

I612

TRUE

I611

TRUE

I613

TRUE

I600

TRUE

I625

TRUE

I624

TRUE

I623

TRUE

I620

TRUE

I621

TRUE

I618

TRUE

I617

TRUE

I615

TRUE

I616

TRUE

I614

TRUE

I627

TRUE

I626

TRUE

I639

TRUE

I638

TRUE

I637

TRUE

I636

TRUE

I709

TRUE

I714

TRUE

I1156

TRUE

I1160

TRUE

I1161

TRUE

I1610

TRUE

I1611

TRUE

I1613

TRUE

I1612

TRUE

I1614

TRUE

I1615

TRUE

I1592

TRUE

I1591

TRUE

I1593

TRUE

I1594

TRUE

I1595

TRUE

I1596

TRUE

I1617

TRUE

I1616

TRUE

I1618

TRUE

I1619

TRUE

I1620

TRUE

I1622

TRUE

I1621

GND

PM_SLP_S3_L PP0V75_S0_DDRVTT

PP18V5_S3 PP1V05_S0 PP1V05_S0GPU PP1V05_S5 PP1V0_FW_FWPHY PP1V2_ENET PP1V2_S0 PP1V5_S3

PP1V5_S3RS0

PP1V8R1V55_S0GPU_ISNS

PP1V8R1V55_S0GPU_ISNS_R

PP1V8_GPUIFPX PP1V8_S0

PP3V3_ENET

PP3V3_FW_FWPHY

PP3V3_S0

PP3V3_S0GPU

PP3V3_S3 PP3V3_S5

PP3V3_S5_AVREF_SMC PP3V42_G3H PP5V_S0

PP5V_S3

PP5V_S5 PPBUS_G3H PPDCIN_G3H

PPVCORE_GPU PPVCORE_S0_CPU PPVCORE_S0_GFX

PPVP_FW PPVTTDDR_S3

TP_FW643_NAND_TREE TP_FW643_OCR10_CTL TP_FW643_SCIFCLK TP_FW643_SCIFDAIN TP_FW643_SCIFDOUT TP_FW643_SCIFMC TP_FW643_SDA TP_FW643_SE TP_FW643_SM TP_FW643_CE TP_FW643_FW620_L TP_FW643_JASI_EN

DMI_S2N_N<1> DMI_S2N_P<1> FDI_DATA_N<1> FDI_DATA_P<1> FDI_FSYNC<1..0> FDI_LSYNC<1..0> FDI_INT

31 32 47 48 6 7 8 24 25 29 30 49 53 54 71

6 7 45 46 47 52

52

62 63 72

52

41

62

41 43

41 45

NC NO_TESTs

NO_TEST

8 7 5 4 2 1

72 87

18 19

25 42 44

17 29 44

44 67 69 17 20 22 7 9 13 14 16 23 35 39 72

7

38 39

7

36 70

7

70 87

7

26 28 29

66 71 98

7

71

71 87 7

14 17 20 22 25 70 89 98 79 82 83 53 56 60 45 47 48 32 35 36 20 22 23 6 7 17 18 19 25 26 28 39 40 41 49 50 51 61 71 72 84 87 88

46 47

25 42 44

6 72 86 88

7 53 64 67 6 7 8 41 46 51 68 69 71 101

7

53 65 71 63 88

7 8 48 49 62

7

48 62 63

7

48 74 81

7

12 14 48 68

7

39 40

7

30 66

66 7 28 29

10 12

101

12 16

35 39

101

38

72

26

100

22

90 9 17

90 17 9

90 9 17

9 17 90

FUNC_TEST

TRUE

I720

TRUE

I722

TRUE

I724

TRUE

I723

TRUE

I725

TRUE

I726

TRUE

I727

TRUE

I729

TRUE

I728

TRUE

I730

TRUE

I732

TRUE

I731

TRUE

I734

TRUE

I733

TRUE

I735

TRUE TRUE

I737

TRUE

I739

TRUE

I738

TRUE

I740

TRUE

I741

TRUE

I742

TRUE

I743

TRUE

I744

TRUE

I751

TRUE

I752

TRUE

I760

TRUE

I756

TRUE

I1292

TRUE

I1288

NO_TEST=TRUE

TRUE

I1477

TRUE

I1478

TRUE

I1479

TRUE

I1480

TRUE

I1481

TRUE

I1483

TRUE

I1482

TRUE

I1484

TRUE

I1486

TRUE

I1485

TRUE

I1488

TRUE

I1487

TRUE

I1489

TRUE

I1491

TRUE

I1490

TRUE

I1492

TRUE

I1563

TRUE

I1562

TRUE

I1564

TRUE

I1566

TRUE

I1565

TRUE

I1567

TRUE

I1569

TRUE

I1568

TRUE

I1570

TRUE

I1571

TRUE

I1572

TRUE

I1573

TRUE

I1574

TRUE

I1575

TRUE

I1576

TRUE

I1577

44

TRUE

I1578

45

TRUE

45

I1579

52 62

TRUE

63

I1580

72

TRUE

I1581

TRUE

I1583

TRUE

I1582

TRUE

I1584

TRUE

I1585

TRUE

I1587

TRUE

I1588

TRUE

I1589

TRUE

I1586

TRUE

I1590

TRUE

I1598

TRUE

I1600

TRUE

I1601

TRUE

I1602

TRUE

I1599

TRUE

I1603

TRUE

I1605

TRUE

I1604

TRUE

I1606

TRUE

I1607

TRUE

I1631

TRUE

I1630

TRUE

I1624

TRUE

I1623

TRUE

I1625

TRUE

I1626

TRUE

I1627

TRUE

I1629

TRUE

I1628

BKLT_EN TP_ISSP_SCLK_P1_1

TP_ISSP_SDATA_P1_0 LCD_BKLT_PWM

LPCPLUS_GPIO LPCPLUS_RESET_L LPC_AD<0..3> LPC_CLK33M_LPCPLUS LPC_FRAME_L

LPC_PWRDWN_L

LPC_SERIRQ PM_CLKRUN_L PM_SYSRST_L SMC_MD1

SMC_NMI

SMC_ONOFF_L

SMC_RESET_L SMC_RX_L

SMC_TCK SMC_TDI

SMC_TDO SMC_TMS SMC_TRST_L

SMC_TX_L

SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L

SPI_ALT_MISO SPI_ALT_MOSI SYS_LED_ANODE_R

T29_D2R_P<1..0> T29_D2R_N<1..0> T29_D2R_C_P<1..0> T29_D2R_C_N<1..0> T29_R2D_C_P<1..0> T29_R2D_C_N<1..0> T29_R2D_P<1..0> T29_R2D_N<1..0> T29DPA_ML_P<3..0>

T29DPA_ML_N<3..0> DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N

DP_T29SNK0_ML_C_P<3..0> DP_T29SNK0_ML_C_N<3..0> DP_T29SNK0_ML_P<3..0> DP_T29SNK0_ML_N<3..0>

DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N

DP_T29SNK1_ML_C_P<3..0> DP_T29SNK1_ML_C_N<3..0> DP_T29SNK1_ML_P<3..0> DP_T29SNK1_ML_N<3..0> TP_DP_T29SRC_AUXCH_CN TP_DP_T29SRC_AUXCH_CP TP_DP_T29SRC_ML_CP<3..0> TP_DP_T29SRC_ML_CN<3..0> DP_SDRVA_ML_C_P<0> DP_SDRVA_ML_C_N<0> DP_SDRVA_ML_C_P<2> DP_SDRVA_ML_C_N<2> DP_SDRVA_ML_P<0> DP_SDRVA_ML_N<0> DP_SDRVA_ML_P<2> DP_SDRVA_ML_N<2> TP_T29_PCIE_RESET0_L TP_T29_PCIE_RESET1_L TP_T29_PCIE_RESET2_L TP_T29_PCIE_RESET3_L T29DPA_D2R1_AUXCH_N T29DPA_D2R1_AUXCH_P T29_D2R1_BIAS

TP_FW643_VAUX_ENABLE TP_FW643_VBUF TP_FW643_TCK TP_FW643_TDO TP_FW643_TMS TP_SMC_P10 TP_P7_7 TP_PSOC_SCL TP_PSOC_SDA TP_SMC_P24

DC_TEST_BH1_BG2 DC_TEST_BH3_BJ2 TP_USB_HUB1_OCS1 TP_USB_HUB1_PRTPWR1 TP_USB_HUB2_OCS1 TP_USB_HUB2_PRTPWR1 TP_DC_TEST_A62 TP_DC_TEST_D65 TP_SMC_PF5

8

52

8

52

87 88

19 46

25 46 87 93

16 44 46 87 93

25 46 93

16 44 46 87 93

17 44 46

16 44 46

17 44 46

17 25 44

44 46

44 45 52

44 45 46 63

42 44 45 46

44 45 46

44 46

42 44 45 46

19 46 55

46 52

46

41

33 84 95

84 85 95

33 84 95

84 95

84 85 95

33 95

33 78 95

33 95

33 78 95

33 95

33

84 95

33

85 95

38

44 45

52

44 45

12

24

12

44 45

ICT Test Points

CPU NO_TESTs

NO_TEST

TP_CPU_RSVD<65..62>

TP_CPU_RSVD<58..45>

TP_CPU_RSVD<43..32>

TP_CPU_RSVD<27..26>

TP_CPU_RSVD<24..15>

TP_CPU_RSVD<2..1>

TP_CPU_RSVD_NCTF<8..5>

NC NO_TESTs

NO_TEST

NC_CRT_IG_BLUE

6

17

NC_CRT_IG_GREEN

6

17

NC_CRT_IG_RED

6

17

NC_CRT_IG_DDC_CLK

6

17

NC_CRT_IG_DDC_DATA

6

17

NC_CRT_IG_HSYNC

6

17

NC_CRT_IG_VSYNC

6

17

NC_LVDS_IG_CTRL_CLK

6

18

NC_LVDS_IG_CTRL_DATA NC_LVDS_IG_CTRL_DATA

6

18

NC_PCH_LVDS_VBG

6

18

NC_HDA_SDIN1

6 16

NC_HDA_SDIN2

6

16

NC_HDA_SDIN3

6

16

TP_AUD_GPIO_2

TRUE

I1632

I1634

I1633

I1636

I1635

I1637

33 78 95

I1638

33 78 95

I1639

I1641

I1640

I1642

I1644

I1643

I1645

33 78 95

6 18

NC_PCI_CLK33M_OUT3

6

18

NC_PCIE_CLK100M_PE4N

6

NC_PCIE_CLK100M_PE4P

6

NC_PCIE_CLK100M_PE5N

6

16

33

NC_PCIE_CLK100M_PE5P

6

16

33

NC_PCIE_CLK100M_PE6N

6

19

NC_PCIE_CLK100M_PE6P

6

19

NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7N

6

19

NC_PCIE_CLK100M_PE7P

6

19

NC_PSOC_P1_3

6

52

NC_SATA_B_D2RN

6

NC_SATA_B_D2RP

6

NC_SATA_B_R2D_CN

6

NC_SATA_B_R2D_CP

6

NC_SATA_D_D2RN

6

16

NC_SATA_D_D2RP

6

16

NC_SATA_D_R2D_CN

6

16

NC_SATA_D_R2D_CP

6

16

NC_SATA_E_D2RN

6

16

NC_SATA_E_D2RP

6

16

NC_SATA_E_R2D_CN

6

16

NC_SATA_E_R2D_CP

6

16

NC_SATA_F_D2RN

6

16

NC_SATA_F_D2RP

6

16

NC_SATA_F_R2D_CN

6

16

NC_SATA_F_R2D_CP

6

16

TP_SMC_P41

44 45

TP_AUD_GPIO_1

TRUE

TP_AUD_LO1_L_N

TRUE

TP_AUD_LO1_L_P

TRUE

TP_BKL_FAULT

TRUE

TP_SPI_DESCRIPTOR_OVERRIDE_L

TRUE

TP_XDPPCH_HOOK2

TRUE

TP_XDPPCH_HOOK3

TRUE

TP_GMUX_PL6B

TRUE

PM_RSMRST_L

TRUE

CPUIMVP_BOOT1

TRUE

CPUIMVP_BOOT2

TRUE

CPUIMVP_UGATE2

TRUE

TP_1V05_S0_PCH_VCCAPLLEXP

TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC NO_TESTs

NO_TEST

56

88

44

23

87

17 72

67 68

TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

PCH ALIASES

NC_LPC_DREQ0_L

6

16

MAKE_BASE=TRUE

16

NC_CLINK_DATA

6

NC_CLINK_RESET_L

6

NC_PCIE_CLK100M_PEBN

6

NC_PCIE_CLK100M_PEBP

6

NC_CLINK_CLK

6

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

NC_TP_CPU_RSVD<65..62>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<58..45>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<43..32>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<27..26>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<24..15>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD<2..1>

TRUE

MAKE_BASE=TRUE

NC_TP_CPU_RSVD_NCTF<8..5>

TRUE

MAKE_BASE=TRUE

NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED

NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_DATA

NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC

NC_LVDS_IG_CTRL_CLK

NC_PCH_LVDS_VBG

NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3

67 68

20

NC_PCI_PME_LNC_PCI_PME_L NC_PCI_CLK33M_OUT3

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_B_D2RN NC_SATA_B_D2RP NC_SATA_B_R2D_CN NC_SATA_B_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP NC_SATA_F_D2RN NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP

NC_SMC_P41

NC_LPC_DREQ0_L

NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP

NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L

36

6

38

6

38

6

17

NC_DP_IG_C_HPD

6

17

6

17

NC_DP_IG_C_CTRL_CLK

6

17

6

17

NC_DP_IG_C_CTRL_DATA

6

17

6

16

6

16

6

16

6

52

6

16

6

16

6

16

6

16

6

16

6

16

6

6 16

TP_DP_IG_C_MLP<3..0>

17

TP_DP_IG_C_MLN<3..0>

6

17

NC_DP_IG_C_AUXP

6

17

NC_DP_IG_C_AUXN

6

17

NC_DP_IG_D_HPD

17

6

17

NC_DP_IG_D_CTRL_CLK

6

17

NC_DP_IG_D_CTRL_DATA

6

17

18

TP_DP_IG_D_MLP<3..0>

18

TP_DP_IG_D_MLN<3..0>

18

NC_DP_IG_D_AUXP

6

17

NC_DP_IG_D_AUXN

6

17

NC_SDVO_TVCLKINN

6

17

NC_SDVO_TVCLKINP

6

17

NC_SDVO_STALLN

6

17

NC_SDVO_STALLP

6

17

NC_SDVO_INTN

6

17

NC_SDVO_INTP

6

17

6

8

18

8

18

8

18

6

I1513

6

18

I1514

6

I1515

18

I1516

6

I1517

6

I1518

I1519

I1520

I1529

I1530

19 6

I1536

I1535

I1534

I1533

I1537

I1539

I1558 I1559

I1540

16

I1541

16

I1542

I1543

I1544

16

I1545

16

I1560 I1561

I1436

16

I1437

16

I1438

I1439

I1440

I1441

I1442

I1443

6

16

6

16

6

16

6

16

6

16

2 1

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

R

NC NO_TESTs

NC_SMC_FAN_3_TACH NC_SMC_FAN_3_CTL NC_SMC_FAN_2_TACH NC_SMC_FAN_2_CTL NC_FW2_TPBP NC_FW2_TPBN NC_FW2_TPBIAS NC_FW2_TPAP NC_FW2_TPAN NC_FW0_TPBP NC_FW0_TPBN NC_FW0_TPAP NC_ESTARLDO_EN NC_ALS_GAIN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

11 26 91

I1524

11 26 91

I1523

I1522

91 11

I1521

26

11 26

I1525

91

11 26 91

I1526

26

I1527

11 26 27

I1528

91 27 11

I1531

26

27 91

11

I1532

26

91

75 76 97

97

75

76 75 76

97

75 76 97

97

75

76

75

76

97 75 76 97

11 26 91

11 28 91

Apple Inc.

NO_TEST

I1297

I761

I762

I763

I764

I765

I767

I766

I769

I768

I770

I772

I771

I774

NC_FW643_AVREG NC_FW643_TDI

NC_GPU_BUFRST_L TP_GPU_GSTATE<0> NC_GPU_GSTATE<1> TP_GPU_MIOA_D<9..0> NC_GPU_MIOA_DE

NC_LVDS_EG_BKL_PWM TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP TP_LVDS_IG_BKL_PWM

NC_SMC_BS_ALRT_L

MEM_A_BA<2..0>

TRUE

MEM_A_CKE<1..0>

TRUE

MEM_A_CLK_N<1..0>

TRUE

MEM_A_CLK_P<1..0>

TRUE

MEM_A_CS_L<1..0>

TRUE

MEM_A_ODT<1..0>

TRUE

MEM_A_SA<1..0>

TRUE

MEM_A_DQ<63..0>

TRUE

MEM_A_DQS_N<7..0>

TRUE

MEM_A_DQS_P<7..0>

TRUE

FB_A0_DQ<31..0>

TRUE

FB_A0_A<8..0>

TRUE

FB_A0_ABI_L

TRUE

FB_A0_EDC<3..0>

TRUE

FB_A0_WCLK_N<1..0>

TRUE

FB_A0_WCLK_P<1..0>

TRUE

FB_A0_DBI_L<3..0>

TRUE

FB_A1_DQ<31..0>

TRUE

FB_A1_A<8..0>

TRUE

FB_A1_ABI_L

TRUE

FB_A1_EDC<3..0>

TRUE

FB_A1_WCLK_N<1..0>

TRUE

FB_A1_WCLK_P<1..0>

TRUE

FB_A1_DBI_L<3..0>

TRUE

MEM_A_A<15..0>

TRUE

MEM_A_CAS_L

TRUE

MEM_A_RAS_L

TRUE

MEM_A_WE_L

TRUE

MEM_B_A<15..0>

TRUE

MEM_B_CAS_L

TRUE

MEM_B_RAS_L

TRUE

MEM_B_WE_L

TRUE

SYNC_MASTER=K18_MLB

PAGE TITLE

Functional / ICT Test

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

NC_FW643_AVREG NC_FW643_TDI

NC_DP_IG_C_HPD NC_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_MLP<3..0> NC_DP_IG_C_MLN<3..0> NC_DP_IG_C_AUXP NC_DP_IG_C_AUXN

NC_DP_IG_D_HPD NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA

NC_DP_IG_D_MLP<3..0> NC_DP_IG_D_MLN<3..0> NC_DP_IG_D_AUXP NC_DP_IG_D_AUXN

NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP

NC_SDVO_STALLN NC_SDVO_STALLP

NC_SDVO_INTN NC_SDVO_INTP

NC_GPU_BUFRST_L NC_GPU_GSTATE<0> NC_GPU_GSTATE<1> NC_GPU_MIOA_D<9..0> NC_GPU_MIOA_DE

NC_LVDS_EG_BKL_PWM NC_LVDS_IG_B_CLKN NC_LVDS_IG_B_CLKP NC_LVDS_IG_BKL_PWM

NC_SMC_BS_ALRT_L

MEM_B_BA<2..0>

TRUE

MEM_B_CKE<1..0>

TRUE

MEM_B_CLK_N<1..0>

TRUE

MEM_B_CLK_P<1..0>

TRUE

MEM_B_CS_L<1..0>

TRUE

MEM_B_ODT<1..0>

TRUE

MEM_B_SA<1..0>

TRUE

MEM_B_DQ<63..0>

TRUE

MEM_B_DQS_N<7..0>

TRUE

MEM_B_DQS_P<7..0>

TRUE

FB_B0_DQ<31..0>

TRUE

I1546

I1547

I1548

I1549

I1550

I1551

I1552

I1554

I1553

I1555

I1557

I1556

FB_B0_A<8..0>

TRUE

FB_B0_ABI_L

TRUE

FB_B0_EDC<3..0>

TRUE

FB_B0_WCLK_N<1..0>

TRUE

FB_B0_WCLK_P<1..0>

TRUE

FB_B0_DBI_L<3..0>

TRUE

FB_B1_DQ<31..0>

TRUE

FB_B1_A<8..0>

TRUE

FB_B1_ABI_L

TRUE

FB_B1_EDC<3..0>

TRUE

FB_B1_WCLK_N<1..0>

TRUE

FB_B1_WCLK_P<1..0>

TRUE

FB_B1_DBI_L<3..0>

TRUE

SYNC_DATE=04/27/2010

44 45

38 40

38 40 94

DRAWING NUMBER

REVISION

BRANCH

PAGE

7 OF 132

SHEET

6 OF 101

6

38

6

38

6

11 28 91

28

11 27 28 91

6

11 28 91

11 27 28 91

75 77 97

75 77 97 97

75 77

75 77 97

75 77 97 97

75 77

75 77 97

SIZE

D

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

C

17

B

97 77 75

97 75 77

97 77 75

97 75 77

A

D

49 62 63

PPBUS_G3H

6 7 8 35 39 48 88

G3H Rails

69

PPVIN_S5_HS_COMPUTING_ISNS

7

49 64

66 67 68

D

PPVIN_S5_HS_GPU_ISNS

7

49

81 86

PPVIN_S5_HS_OTHER_ISNS

7

49

65

63 48

PPDCIN_G3H

6 7 62

63 52 46 44 25

PP3V42_G3H

6 7 42 45 47 62 72

C

For PCH RTC Power

PPVRTC_G3H

7

16 17

20 25

5V Rails

PP5V_S5

6 7

53 65

71

PP5V_SUS

7

22 71

65 66 71 81

PP5V_S3

6 7

29 31

41 42 43 45 100

B

69 71 72 86

PP5V_S0

6 7 8

22 41 46 51

53 64 67 68 88

101

3.3V Rails

7

45 52 53 71

A

7

16 17 18 19 20

22 45 70 71 72

72 82 85 89 98

345678

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE

PP3V3_S4

PP3V3_SUS

PPBUS_G3H PPBUS_G3H PPBUS_G3H

PPBUS_G3H

PPBUS_G3H PPBUS_G3H PPBUS_G3H

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE

PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS

PPVIN_S5_HS_GPU_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_HS_GPU_ISNS

PPVIN_S5_HS_OTHER_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_HS_OTHER_ISNS PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPDCIN_G3H PPDCIN_G3H

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H

PPVRTC_G3H

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

PPVRTC_G3H

PP5V_S5

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP5V_S5 PP5V_S5 PP5V_S5 PP5V_S5

PP5V_SUS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP5V_SUS

PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PP5V_S3 PP5V_S3

PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3

PP5V_S3

PP5V_S3 PP5V_S3 PP5V_S3

PP5V_S0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0

PP5V_S0 PP5V_S0

PP5V_S0

PP5V_S0 PP5V_S0 PP5V_S0

PP3V3_S4

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S4

PP3V3_SUS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_SUS

PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS

PP3V3_SUS PP3V3_SUS

VOLTAGE=18.5V MAKE_BASE=TRUE

VOLTAGE=3.42V MAKE_BASE=TRUE

VOLTAGE=5V MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=3.3V

VOLTAGE=12.8V MAKE_BASE=TRUE

VOLTAGE=5V MAKE_BASE=TRUE

6 7 8

7

49 64 66 67 68 69

7

49 81 86

7

49 81 86

7

49 81 86

7

49 65

7

49 65

6 7

48 62 63

6 7

48 62 63

6 7

48 62 63

6 7

25 42 44 45 46 47 52 62 63

72

6 7

25 42 44 45 46 47 52 62 63

72 6 7

25 42 44 45 46 47 52 62 63

72

6 7

25 42 44 45 46 47 52 62 63

72 6 7

25 42 44 45 46 47 52 62 63

72 6 7

25 42 44 45 46 47 52 62 63

72

6 7 72

7

16 17 20 25

6 7

53 65 71

6 7

53 65 71

6 7

53 65 71

6 7

53 65 71

6 7

53 65 71

7

22 71

7

22 71

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7

29 31 41 42 43 45 65 66 71 81

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

101

6 7 8 88

7

20 22 45 70 71 72 7 16 17 18 19

7

72 7 45 70 71

7

72 7 45 70 71

8 7 5 4 2 1

PP3V3_S5

6 7

17 19 20 22

23 24 25 29 39 45 55 65 70 71

35 39 48 49 62 63 88

49 64 66 67 68 69

53 54 71 72 87

PP3V3_S3

6 7 8

18

19 24 25 29 30 31 32 47 48 49

25 42 44 45 46 47 52 62 63

82 83 84 87 88 89 98 47 48 49 50 51

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 53 56 60 61 71 72 79

100

22 41 46 51 53 64 67 68 69 71 72 86

101

22 41 46 51 53 64 67 68 69 71 72 86

101

7

45 52 53 71

7

45 52 53 71

7

16 17 18 19 20 22 45 70 71 72

16 17 18 19 20 22

16 17 18 19 20 22 45 70 71 72

16 17 18 19 20 22

7

16 19 25 33 34

35 87

7

34 35

7 8

35 85

T29 Rails

PP3V3_T29

PP1V05_T29

PP15V_T29

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S3

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3

PP3V3_S3

PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 mm

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_T29

MIN_LINE_WIDTH=0.4 MM

PP3V3_T29

PP3V3_T29 PP3V3_T29 PP3V3_T29

PP1V05_T29

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP15V_T29

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

PP1V05_T29

PP15V_T29

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

VOLTAGE=1.05V MAKE_BASE=TRUE

VOLTAGE=15V MAKE_BASE=TRUE

6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98

98 6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98

6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98

6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98

6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98

6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98

6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98

6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98

6 7

17 19 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98 6 7

17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89 98

6

45 55 65 70 71 72 82 85 89

7

17 19 20 22 23 24 25 29 39

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

6 7 8

18 19 24 25 29 30 31 32

47 48

8

54 71

6

72 87

7

48 49 53 54 71 72 87

18 19 24 25 29 30 31 32 47

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87 6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87 6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87 6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

6 7 8

18 19 24 25 29 30

31 32 47 48 49 53 54 71 72 87

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47

79 82 83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 26 28 32 35 36 39 40 41 45 47 6 7

12 16 17 18 19 20 22 23 25 47 48 49 50 51 53 56 60 61

6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

6

17

7

12 16 17 18 19 20 22 23 25 12

32 35 36 39 40 41 45 47 48

6

49 50 51 53 56 60 61 71 72

7

79 82 83 84 87 88 89 98 16 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 48 49 50 51 53 56 60 61 71 72 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

6 7

12 16 17 18 19 20 22 23 25

32 35 36 39 40 41 45 47 48 49 50 51 53 56 60 61 71 72 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

79 82 83 84 87 88 89 98 48 49 50 51 53 56 60 61 71 72 26 28 32 35 36 39 40 41 45 47 6 7

12 16 17 18 19 20 22 23 25 48 49 50 51 53 56 60 61 71 72

6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

6

17

7

12 16 17 18 19 20 22 23 25 12

32 35 36 39 40 41 45 47 48

6

49 50 51 53 56 60 61 71 72

7

79 82 83 84 87 88 89 98 16 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 48 49 50 51 53 56 60 61 71 72 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25

26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 26 28 32 35 36 39 40 41 45 47 6 7

12 16 17 18 19 20 22 23 25

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

6 7

12 16 17 18 19 20 22 23 25

32 35 36 39 40 41 45 47 48 49 50 51 53 56 60 61 71 72

82

79 82 83 84 87 88 89 98 48 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 49 50 51 53 56 60 61 71 72 79

6

83 84 87 88 89 98

7

12

12 16 17 18 19 20 22 23 25

6

26 28 32 35 36 39 40 41 45

7

51 53 56 60 61 71 72 79

16

82 83 84 87 88 89 98 17 18 19 20 22 23 25 26 28 32 36 39 40 41 45 47 48 49 50 51 53 56 60 61 71 72 79 82 83 84 87 88 89 98

6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 50 51 53 56 60 61 71 72 79 82 84 87 88 89 98

7

16 19 25 33 34 35 87

7

16 19 25 33 34 35 87

7

16 19 25 33 34 35 87

7

16 19 25 33 34 35 87

7

16 19 25 33 34 35 87

7

34 35

7

34 35

7 8

35 85

7 8

35 85

PP1V8_S0

6 7

14 17 20 22 25 70 71 87

2A max supply

PP1V8_S0_CPU_VCCPLL_R

PP1V5_S3

PP1V5_S3RS0_CPUDDR

98

49 53

PP1V5_S0

7

16 20 22 25 41 56 70

PPVTTDDR_S3

6 7

30 66

7

26 28 29 66

PP0V75_S0_DDRVTT

6

79 82

PP1V2_S0

PP1V05_SUS

7

23 70

26 28

PP1V05_S0

26 28

98

89 87 88 83 84

79 82

26 28

47 48 49 50

35

PPBUS_SW_BKL

7

88

83

100

48 49

PP3V3_ENET

6 7

25 36

70 72

PP1V2_ENET

6 7

36 70

1.8V/1.5V/1.2V/1.05V Rails

Backlight Rails

ENET Rails

PP1V8_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0

PP1V8_S0

PP1V8_S0_CPU_VCCPLL_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PP1V5_S3

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3

PP1V5_S3RS0_CPUDDR

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S3RS0_CPUDDR PP1V5_S3RS0_CPUDDR

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S0 PP1V5_S0

PP1V5_S0

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE

PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT

PP1V2_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE

PP1V2_S0

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_SUS

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

PP3V3_ENET

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_ENET PP3V3_ENET PP3V3_ENET

PP1V2_ENET

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE

PP1V2_ENET

MAKE_BASE=TRUE VOLTAGE=12.8V

VOLTAGE=1.8V MAKE_BASE=TRUE

36

6 7

14 17 20 22 25 70 71 87

PP3V3_S0GPU PP3V3_S0GPU

6 7

71 74 78 79 81 83

6 7

14 17 20 22 25 70 71 87

6 7

14 17 20 22 25 70 71 87

6 7

14 17 20 22 25 70 71 87

6 7

14 17 20 22 25 70 71 87

6 7

14 17 20 22 25 70 71 87

6 7

14 17 20 22 25 70 71 87

6 7

14 17 20 22 25 70 71 87

7

12 14

6 7

26 28 29 66 71

100

6 7

26 28 29 66 71

6 7

26 28 29 66 71

6 7

26 28 29 66 71

6 7

26 28 29 66 71

6 7

26 28 29 66 71

7

10 13 15 29 71 72

7

10 13 15 29 71 72

7

10 13 15 29 71 72

7

16 20 22 25 41 56 70

7

16 20 22 25 41 56 70

7

16 20 22 25 41 56 70

7

16 20 22 25 41 56 70

100

6 7

30 66

6 7

26 28 29 66

6 7

26 28 29 66

6 7

26 28 29 66

6 7

26 28 29 66

100

6 7

70 87

6 7

70 87

7

23 70

7

23 70

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17

20 22 23 35 39 44 67 69 72 6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

23 35 39 44 67 69 72 6 7 9

10 12 13 14 16 17

20 22 6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13

14 16 17 20 22 23 35 39 44 67 69 72

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17

20 22 23 35 6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

39 44 67 69 72 6 7 9

10 12 13 14 16 17

20 22 23 35 6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17

20 22 23 35 39 44 67 69 6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17

20 22 23

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72 101 6 7 9

10 12

13 14 16 17 20 22 23 35 39 44 67 69 72

7

88

100

6 7

25 36 70 72

6 7

25 36 70 72

6 7

25 36 70 72

6 7

25 36 70 72

6 7

36 70

6 7

36 70

PP1V8_GPUIFPX

6 7

71

100

PP1V8_S0GPU_ISNS

7

74 78 80

PP1V5_GPU_REG

7

86

100

PP1V5_S0GPU_ISNS

7

74 75 76 77

PP1V0_S0GPU

7

86

100

PP1V0_S0GPU_ISNS

7

73 74 78 80

PPVCORE_GPU

6 7

48 74 81

PPVCORE_S0_CPU

101

67 69 72

101

PPVCORE_S0_AXG

7

12 13 15 48 68

PP1V5_S3_CPU_VCCDQ

7

12 15

39 44 67 69 72

72

35 39 44 67 69 72

101

PP1V05_S0_CPU_VCCPQE

7

10 12 14

67 69 72

101

PPVCCSA_S0_REG

7

12 15 64

101

PPVP_FW

101

PP3V3_FW_FWPHY

6 7

38 39 40

101

PP1V0_FW_FWPHY

6 7

38 39

101

2 1

"GPU" Rails

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU

PP1V8_GPUIFPX

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_GPUIFPX

PP1V8_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V5_GPU_REG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_GPU_REG

PP1V5_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S0GPU_ISNS PP1V5_S0GPU_ISNS PP1V5_S0GPU_ISNS PP1V5_S0GPU_ISNS PP1V0_S0GPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE

PP1V0_S0GPU

PP1V0_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS PP1V0_S0GPU_ISNS

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCORE_GPU

Chipset "VCore" Rails

101

FireWire Rails

SYNC_MASTER=K18_MLB

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

PPVCORE_S0_CPU

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_AXG

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_CPU_VCCPQE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVP_FW

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PPVP_FW

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY

PP1V0_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V0_FW_FWPHY

Power Aliases

Apple Inc.

PPVCCSA_S0_REG

6 7

71 74 78 79

81 83

6 7

71 74 78 79

81 83

6 7

71 74 78 79

81 83 6 7

71 74 78 79

81 83

6 7

71 74 78 79

81 83 6 7

71 74 78 79

81 83 6 7

71 74 78 79

81 83

6 7

71

6 7

71

7

74 78 80

100

7

74 78 80

7

74 78 80

7

74 78 80

7

74 78 80

7

74 78 80

7

74 78 80

7

74 78 80

7

74 78 80

7

74 78 80

7

74 78 80

7

74 78 80

7

74 78 80

7

86

100

7

86

100

7

74 75 76 77

100

7

74 75 76 77

100 7

74 75 76 77

100 7

74 75 76 77

100 7

74 75 76 77

100

7

86

100

7

86

100

7

73 74 78 80

VOLTAGE=1.0V MAKE_BASE=TRUE

MAKE_BASE=TRUE VOLTAGE=1.25V

MAKE_BASE=TRUE VOLTAGE=1.05V

MAKE_BASE=TRUE VOLTAGE=1.5V

VOLTAGE=1.05V MAKE_BASE=TRUE

VOLTAGE=0.9V MAKE_BASE=TRUE

VOLTAGE=12.8V MAKE_BASE=TRUE

VOLTAGE=3.3V MAKE_BASE=TRUE

VOLTAGE=1.0V MAKE_BASE=TRUE

100

7

73 74 78 80

100

7

73 74 78 80

100 7

73 74 78 80

100

7

73 74 78 80

100 7

73 74 78 80

100 7

73 74 78 80

100

7

73 74 78 80

100

6 7

6 7 48 68

7 15 48 68

7

7 14

7 64

7

12 15 64

6 7

39 40

6 7

39 40

6 7

39 40

6 7

38 39 40

6 7

38 39 40

6 7

38 39

6 7

38 39

48 74 81

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

8 OF 132

SHEET

7 OF 101

100

12 13

12 15

10 12

12 15

12 14

SIZE

D

100

C

101

B

A

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0984

ZT0987

ZT0980

D

ZT0915

3R2P5

ZT0940

3R2P5

ZT0950

SL-3.1X2.7-6CIR-NSP

ZT0960

3R2P5

ZT0990

3R2P5

C

POGO-2.0OD-3.5H-K86-K87

B

1.4DIA-SHORT-SILVER-K99

Heat spreader mounting boss for T29 router

A

Heat spreader mounting boss for PCH

SH0902

SH0903

SH0904

Short (IO Row) EMI pogo pins

SH0910

SH0912

SH0901

SH0914

STDOFF-4.0OD1.85H-SM

STDOFF-4.0OD2.23H-SM

8 7 5 4 2 1

Thermal Module Holes

1

Frame Holes

1

GND

1

GND

TH

1

GND

1

GND

1

GND

Tall EMI pogo pins

SM

1

SM

1

SM

1

SM

1

SM

1

SM

1

SM

1

GND_CHASSIS_AUDIO_JACK

SH0920

1

SH0921

1

STDOFF-4.0OD1.85H-SM

STDOFF-4.0OD2.23H-SM

STDOFF-4.5OD.98H-1.1-3.48-TH

POGO-2.0OD-3.5H-K86-K87

1.4DIA-SHORT-SILVER-K99

ZT0981

1

ZT0985

1

ZT0986

1

SH0900

SM

1

SH0916

SM

1

SH0911

SM

1

SH0913

SM

1

SH0917

SM

1

60

85

SH0923

1

SH0922

1

Fan Holes

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0930

1

ZT0988

1

ZT0989

1

ZT0991

1

Left Speaker Holes

ZT0934

STDOFF-4.0OD3.0H-TH

1

ZT0935

1

Keyboard / IPD Conn Protect

ZT0952

T29_A_BIAS_R

8

85

T29_A_BIAS_R

8

85

T29_A_BIAS_R

8

85

T29_A_BIAS_R

8

4.0OD1.85H-M1.6X0.35

ZT0953

R0921

51

1

1/20W

201

R0922

51

5%

1/20W

MF

201

R0923

51

5%

1/20W

MF

201

R0924

51

5%

1/20W

MF

201

1

2

T29_A_BIAS_R2D_P0

5%

1

MF

2

21

T29_A_BIAS_R2D_N0

1

C0902

0.01UF

10% 10V

2

X5R 201

21

T29_A_BIAS_R2D_P1

1

C0903

0.01UF

10% 10V

2

X5R 201

21

T29_A_BIAS_R2D_N1

1

C0904

0.01UF

10% 10V

2

X5R 201

C0901

0.01UF

10% 10V X5R 201

22 41 46 51 53 64 67 68 69 71 72 86

101

6 7 88

16

PP5V_S0

8

84

100

84

16

84

16

JTAG_ISP_TCK

8

19 23 33 87

MAKE_BASE=TRUE

JTAG_ISP_TDI

8

19 33 87

MAKE_BASE=TRUE

JTAG_ISP_TDO

8

19 33 87

MAKE_BASE=TRUE

T29_LSEO_LSOE3

8

33

T29_LSEO_LSOE2

8

33

PM_ALL_GPU_PGOOD

8

73 81 86 87 89

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

8

87

MAKE_BASE=TRUE

8

18 87

8

18 87

6 8

82 88

8

19 39

8

38 39

8

16

16 93

8

52

EG_RESET_L

8

73 87

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

PPVOUT_S0_LCDBKLT

MAKE_BASE=TRUE

GMUX_VSYNC

8

87 88

MAKE_BASE=TRUE

PEX_CLKREQ_L

8

79 87

MAKE_BASE=TRUE

PEG_CLKREQ_L

8

16 87

MAKE_BASE=TRUE

PM_ENET_EN

8

MAKE_BASE=TRUE

FW_PLUG_DET_L

MAKE_BASE=TRUE

FW643_WAKE_L

MAKE_BASE=TRUE

TP_SMC_EXCARD_PWR_EN

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2R_N

8

NC_PCIE_EXCARD_D2R_P

8

NC_PCIE_EXCARD_R2D_C_N

8

NC_PCIE_EXCARD_R2D_C_P

8

NC_PCIE_CLK100M_EXCARD_N

8

NC_PCIE_CLK100M_EXCARD_P

8

NC_PEG_B_CLKRQ_L_GPIO56

NC_PCIECLKRQ4_L_GPIO26

TP_ISSP_SCLK_P1_1

6 8

MAKE_BASE=TRUE

TP_ISSP_SDATA_P1_0

6 8

MAKE_BASE=TRUE

GND GND GND GND

GND

8

MAKE_BASE=TRUE

8

MAKE_BASE=TRUE

8

MAKE_BASE=TRUE

NC_PCH_CLKOUT_DPN

NC_PCH_CLKOUT_DPP

NC_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO65_CLKOUTFLEX1 NC_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO67_CLKOUTFLEX3

NC_FSB_CLK133M_PCHP

MAKE_BASE=TRUE

NC_FSB_CLK133M_PCHN

MAKE_BASE=TRUE

NC_LT_GAIN_TP

NC_RT_GAIN_TP

NC_SW_GAIN_TP

XW0901

1 2

XW0902

1 2

XW0903

1 2

T29 / GMUX JTAG Signals

JTAG_ISP_TCK

JTAG_ISP_TDI

JTAG_ISP_TDO

T29_LSEO_LSOE3

MAKE_BASE=TRUE

T29_LSEO_LSOE2

MAKE_BASE=TRUE

NO_TEST=TRUE

GMUX ALIASES

PM_ALL_GPU_PGOOD

NO_TEST=TRUE

SM

PP5V_S0_AUDIO

SM

PP5V_S0_AUDIO_AMP_L

SM

PP5V_S0_AUDIO_AMP_R

TP_LVDS_MUX_SEL_EG

EG_RESET_L

LVDS_IG_BKL_ON

LVDS_IG_PANEL_PWR

PPVOUT_S0_LCDBKLT

GMUX_VSYNC

PEX_CLKREQ_L

PEG_CLKREQ_L

PM_ENET_EN

FW_PLUG_DET_L

FW643_WAKE_L

TP_SMC_EXCARD_PWR_EN

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_FSB_CLK133M_PCHP

NC_FSB_CLK133M_PCHN

NC_LT_GAIN_TP

NC_RT_GAIN_TP

NC_SW_GAIN_TP

MAKE_BASE=TRUE

PP5V_S0_AUDIO

T29_LSEO_LSOE3

T29_LSEO_LSOE2

8

73 87

8

18 87

8

87 88

8

79 87

8

16 87

8

NC_PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P

NC_PCIE_CLK100M_EXCARD_N

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_P

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PEG_B_CLKRQ_L_GPIO56

NC_PCIECLKRQ4_L_GPIO26

TP_ISSP_SCLK_P1_1

TP_ISSP_SDATA_P1_0

TRUE

MAKE_BASE=TRUE

NC_PCH_CLKOUT_DPN

NC_PCH_CLKOUT_DPP

NC_PCH_GPIO64_CLKOUTFLEX0 NC_PCH_GPIO65_CLKOUTFLEX1 NC_PCH_GPIO66_CLKOUTFLEX2 NC_PCH_GPIO67_CLKOUTFLEX3

73 81 86 87 89

8

87

8

18 87

6 8

82 88

8

56

8

56

59

CPU_VID<0..6>

90

MAKE_BASE=TRUE

GFX_VID<0..6>

90

MAKE_BASE=TRUE

29 66

MEMVTT_EN

8

19 23 33

8

87

MAKE_BASE=TRUE

8

19 23 33 87

8

19 33 87

NC_PEG_D2R_P<15..12>

9

MAKE_BASE=TRUE

NC_PEG_D2R_N<15..12>

8

19 33 87

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15..12>

9

8

33

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<15..12>

9

8

33

MAKE_BASE=TRUE

PCIE_T29_D2R_P<3..0>

9

33 93

MAKE_BASE=TRUE

PCIE_T29_D2R_N<3..0>

9

33 93

MAKE_BASE=TRUE

PCIE_T29_R2D_C_P<3..0>

9

33 93

MAKE_BASE=TRUE

PCIE_T29_R2D_C_N<3..0>

9

33 93

MAKE_BASE=TRUE

PEG_D2R_P<7..0>

73 90

MAKE_BASE=TRUE

PEG_D2R_N<7..0>

73 90

MAKE_BASE=TRUE

100

PEG_R2D_C_P<7..0>

73 90

MAKE_BASE=TRUE

PEG_R2D_C_N<7..0>

73 90

MAKE_BASE=TRUE

T29_D2R_P<3..2>

95

T29_D2R_N<3..2>

95

T29_R2D_C_P<3..2>

95

T29_R2D_C_N<3..2>

95

8

19 39

8

38 39

8

6 8

52

6 8

52

8

16

8

16

8

16

8

16

8

16

LCD_BKLT_EN

87 88

8

PPBUS_G3H

6 7

35 39 48 49 62 63 88

345678

CPU signals

CPUIMVP_VID<0..6>

GFXIMVP_VID<0..6>

MEMVTT_EN

Unused PEG signals

NO_TEST=TRUE

T29 Signals Through PEG

=PEG_D2R_P<15..12>

=PEG_D2R_N<15..12>

GPU signals

=PEG_D2R_P<7..0>

=PEG_D2R_N<7..0>

=PEG_R2D_C_P<7..0>

=PEG_R2D_C_N<7..0>

Unused T29 Ports

8

16

DP_EG_AUXCH_N

8

78 83 97

MAKE_BASE=TRUE

8

16

DP_EG_AUXCH_P

8

16

MAKE_BASE=TRUE

8

16

NC_DPB_EG_AUX_CHN

8

MAKE_BASE=TRUE

NC_DPB_EG_AUX_CHP

8

MAKE_BASE=TRUE

8

16 93

NC_DPB_EG_DDC_CLK

8

MAKE_BASE=TRUE

8

16 93

NC_DPB_EG_DDC_DATA

8

MAKE_BASE=TRUE

NC_DPB_EG_MLN<3..0>

MAKE_BASE=TRUE

8

NC_DPB_EG_MLP<3..0>

MAKE_BASE=TRUE

8 8

T29_A_BIAS_R

8

85

8

16

1

R0901

4.7K

5% 1/16W MF-LF 402

2

NC_T29_D2RP<3..2>

MAKE_BASE=TRUE

NC_T29_D2RN<3..2>

MAKE_BASE=TRUE

NC_T29_R2D_CP<3..2>

MAKE_BASE=TRUE

NC_T29_R2D_CN<3..2>

MAKE_BASE=TRUE

17

MAKE_BASE=TRUE

17

MAKE_BASE=TRUE

8

17 83 92

MAKE_BASE=TRUE

8

17 83 92

MAKE_BASE=TRUE

8

17 79 83

MAKE_BASE=TRUE

8

17 79 83

MAKE_BASE=TRUE

8

17 83

MAKE_BASE=TRUE

T29BST:N

R0950

0

1 2

5%

1/8W

MF-LF

805

36

8

=PEG_R2D_C_P<15..12>

=PEG_R2D_C_N<15..12>

=PEG_D2R_P<11..8>

=PEG_D2R_N<11..8>

=PEG_R2D_C_P<11..8>

=PEG_R2D_C_N<11..8>

NO_TEST=TRUE

DP_EG_AUXCH_N

DP_EG_AUXCH_P

NO_TEST=TRUE

R0926

51

5%

1/20W

MF

201

NC_DP_IG_MLP<3..0>

NC_DP_IG_MLN<3..0>

DP_IG_AUX_CH_P

NC_DPB_EG_AUX_CHN

NC_DPB_EG_AUX_CHP

NC_DPB_EG_DDC_CLK

NC_DPB_EG_DDC_DATA

DPB_EG_ML_N<3..0>

DPB_EG_ML_P<3..0>

21

T29_A_BIAS_D2R_P1

1

C0906

0.01UF

10% 10V

2

X5R 201

NO_TEST=TRUE

DP_IG_AUX_CH_N

DP_IG_DDC_CLK

DP_IG_DDC_DATA

DP_IG_HPD

PP15V_T29

29 66

7

9

33

35 85

2 1

TP_CPU_VTT_SELECT

8

90

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

6 8

18

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

6 8

18

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM

6 8

18

MAKE_BASE=TRUE

NC_GPU_XTALOUT

8

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

8

18 92

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

8

18 92

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

8

18

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

8

18

MAKE_BASE=TRUE

NC_USB_HUB1_OCS4

8

24

MAKE_BASE=TRUE

NC_USB_HUB2_OCS4

8

24

MAKE_BASE=TRUE

PP3V3_S3

NOSTUFF

R0913

84

TP_DP_IG_B_MLP<3..0>

TP_DP_IG_B_MLN<3..0>

DP_IG_AUX_CH_P

DP_IG_AUX_CH_N

DP_IG_DDC_CLK

DP_IG_DDC_DATA

DP_IG_HPD

1

10K

5% 1/16W MF-LF

402

2

8

78 83 97

8

78 83 97

T29_A_BIAS_R

85

8

85

DP_A_BIAS0

SYNC_MASTER=K18_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

NO_TEST=TRUE

NOSTUFF

R0903

NOSTUFF

1

R0914

10K

5% 1/16W MF-LF 402

2

USB_SDCARD_P

8

24

MAKE_BASE=TRUE

USB_SDCARD_N

8

24

MAKE_BASE=TRUE

8

17 83 92

8

17 83 92

8

17 79 83

8

17 79 83

8

17 83

TP_CPU_VTT_SELECT

TP_LVDS_IG_B_CLKP

TP_LVDS_IG_B_CLKN

TP_LVDS_IG_BKL_PWM

NC_GPU_XTALOUT

NC_LVDS_IG_A_DATAP<3>

NC_LVDS_IG_A_DATAN<3>

NC_LVDS_IG_B_DATAP<3>

NC_LVDS_IG_B_DATAN<3>

NC_USB_HUB1_OCS4

NC_USB_HUB2_OCS4

PP3V3_S3

NOSTUFF

1

10K

1/16W MF-LF

R0904

10K

5%

5% 1/16W MF-LF

402

2

USB_EXTC_N USB_EXTC_P

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

USB_SDCARD_P

USB_SDCARD_N

PP3V3_S3

1

R0915

R0927

1 2

1/20W

201

DP_A_BIAS2

84

10K

1/16W MF-LF

51

5%

MF

1

2

R0916

10K

5%

1/16W MF-LF 402

402

2

USB_T29A_N USB_T29A_P

T29_A_BIAS_D2R_N1

1

C0907

0.01UF

10% 10V

2

X5R 201

C0905

0.01UF

10% 10V X5R 201

GND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.095 mm VOLTAGE=0V

Digital Ground

Signal Aliases

Apple Inc.

R

8

90

6 8

18

6 8

18

6 8

18

8

18 92

8

18 92

8

18

8

18

8

24

8

24

6 7 8

18 19 24 25 29 30 31

32 47 48 49 53 54 71 72 87

24 92

8

24

47 48 49 53 54 6 7 8

18 19 24 25 29 30 31 32 71 72 87

24 92

85

1

C0908

0.01UF

10% 10V

2

X5R 201

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

9 OF 132

SHEET

8 OF 101

24

SIZE

D

C

B

A

D

345678

2 1

PP1V05_S0

1

R1010

24.9

1% 1/16W MF-LF 402

2

1/16W MF-LF

N10

DMI_RX_0*

R10

DMI_RX_1*

R8

DMI_RX_2*

U10

DMI_RX_3*

N8

DMI_RX_0

T9

DMI_RX_1

R6

DMI_RX_2

U8

DMI_RX_3

N4

DMI_TX_0*

R4

DMI_TX_1*

P1

DMI_TX_2*

U6

DMI_TX_3*

N2

DMI_TX_0

R2

DMI_TX_1

P3

DMI_TX_2

T5

DMI_TX_3

V7

FDI_TX_0*

W8

FDI_TX_1*

AA8

FDI_TX_2*

AC10

FDI_TX_3*

U4

FDI_TX_4*

W2

FDI_TX_5*

V1

FDI_TX_6*

Y5

FDI_TX_7*

W6

FDI_TX_0

W10

FDI_TX_1

Y9

FDI_TX_2

AA10

FDI_TX_3

U2

FDI_TX_4

W4

FDI_TX_5

V3

FDI_TX_6

AA6

FDI_TX_7

AC8

FDI0_FSYNC

AA2

FDI1_FSYNC

AD9

FDI_INT

AB7

FDI0_LSYNC

AB3

FDI1_LSYNC

AG2

EDP_TX_0*

AF1

EDP_TX_1*

AE6

EDP_TX_2*

AG6

EDP_TX_3*

AG4

EDP_TX_0

AF3

EDP_TX_1

AF7

EDP_TX_2

AG8

EDP_TX_3

AE4

EDP_AUX

AE2

EDP_AUX*

AB1

EDP_ICOMPO

AC2

EDP_COMPIO

AE8

EDP_HPD

CPU_CFG<16>

9

23 90

CPU_CFG<3>

9

23 90

CPU_CFG<1>

9

23 90

CPU_CFG<0>

9

23 90

1

1K

5%

402

2

NOSTUFF

R1040

1/16W MF-LF

1

1K

5%

402

2

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

(SYM 1 OF 11)

OMIT

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

PCI EXPRESS BASED INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

NOSTUFF

1

R1041

1K

5% 1/16W MF-LF

402

2

NOSTUFF

R1043

1/16W MF-LF

402

1K

5%

1

2

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_0* PEG_RX_1* PEG_RX_2* PEG_RX_3* PEG_RX_4* PEG_RX_5* PEG_RX_6* PEG_RX_7* PEG_RX_8*

PEG_RX_9* PEG_RX_10* PEG_RX_11* PEG_RX_12* PEG_RX_13* PEG_RX_14* PEG_RX_15*

PEG_RX_10

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX_0*

PEG_TX_1*

PEG_TX_2*

PEG_TX_3*

PEG_TX_4*

PEG_TX_5*

PEG_TX_6*

PEG_TX_7*

PEG_TX_8*

PEG_TX_9* PEG_TX_10* PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

DMI_S2N_N<0>

17 90

IN

DMI_S2N_N<1>

6

17 90

IN

DMI_S2N_N<2>

17 90

IN

DMI_S2N_N<3>

17 90

D

C

72 23 35 39 44 13 14 16 17

PP1V05_S0

6 7 9 10 12 20 22 67 69 101

B

1

R1031

10K

1% 1/16W MF-LF 402

2

PLACE_NEAR=U1000.AB1:12.7mm

CPU_CFG<7>

9

23 90

CPU_CFG<6>

9

23 90

CPU_CFG<5>

9

23 90

CPU_CFG<4>

9

23 90

CPU_CFG<2>

9

23 90

A

IN

DMI_S2N_P<0>

17 90

IN

DMI_S2N_P<1>

6

17 90

IN

DMI_S2N_P<2>

17 90

IN

DMI_S2N_P<3>

17 90

IN

DMI_N2S_N<0>

17 90

OUT

DMI_N2S_N<1>

17 90

OUT

DMI_N2S_N<2>

17 90

OUT

DMI_N2S_N<3>

17 90

OUT

DMI_N2S_P<0>

17 90

OUT

DMI_N2S_P<1>

17 90

OUT

DMI_N2S_P<2>

17 90

OUT

DMI_N2S_P<3>

17 90

OUT

FDI_DATA_N<0>

17 90

OUT

FDI_DATA_N<1>

6

17 90

OUT

FDI_DATA_N<2>

17 90

OUT

FDI_DATA_N<3>

17 90

OUT

FDI_DATA_N<4>

17 90

OUT

FDI_DATA_N<5>

17 90

OUT

FDI_DATA_N<6>

17 90

OUT

FDI_DATA_N<7>

17 90

OUT

FDI_DATA_P<0>

17 90

OUT

FDI_DATA_P<1>

6

17 90

OUT

FDI_DATA_P<2>

17 90

OUT

FDI_DATA_P<3>

17 90

OUT

FDI_DATA_P<4>

17 90

OUT

FDI_DATA_P<5>

17 90

OUT

FDI_DATA_P<6>

17 90

OUT

FDI_DATA_P<7>

17 90

OUT

FDI_FSYNC<0>

6

17 90

IN

FDI_FSYNC<1>

6

17 90

IN

FDI_INT

6

17 90

IN

FDI_LSYNC<0>

6

17 90

IN

FDI_LSYNC<1>

6

17 90

IN

TP_EDP_TX_N<0> TP_EDP_TX_N<1> TP_EDP_TX_N<2> TP_EDP_TX_N<3>

TP_EDP_TX_P<0>

1

R1030

24.9

1% 1/16W MF-LF 402

2

TP_EDP_TX_P<1> TP_EDP_TX_P<2> TP_EDP_TX_P<3>

TP_EDP_AUX_P TP_EDP_AUX_N

CPU_EDP_COMP

CPU_EDP_HPD

10K PU disables eDP HPD

CPU_CFG<4> should be pulled down to enable EDP

NOSTUFF

R1042

1/16W MF-LF

EDP

1

R1044

1K

5%

1/16W MF-LF

402

2

R1045

1/16W MF-LF

NOSTUFF

1

R1046

1K

5%

1/16W MF-LF

402

2

NOSTUFF

R1047

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9

NOSTUFF

R1049

1K

5% 1/16W MF-LF

402

G2 H1 F3

F23 H23 H21 H19 J20 G18 K17 F15 H15 H13 H11 J12 E8 G10 J8 F7

G22 K23 K21 F19 K19 H17 K15 G14 J16 K13 F11 K11 F9 H9 H7 G6

A22 B23 C18 D21 B19 E20 A14 D17 B15 E16 D13 A10 B11 D9 B7 E12

C22 D23 A18 B21 D19 F21 C14 B17 D15 F17 B13 C10 D11 B9 D7 F13

1

2

CPU_PEG_COMP

90

=PEG_D2R_N<0> =PEG_D2R_N<1> =PEG_D2R_N<2> =PEG_D2R_N<3> =PEG_D2R_N<4> =PEG_D2R_N<5> =PEG_D2R_N<6> =PEG_D2R_N<7> PCIE_T29_D2R_N<0> PCIE_T29_D2R_N<1> PCIE_T29_D2R_N<2> PCIE_T29_D2R_N<3> NC_PEG_D2R_N<12> NC_PEG_D2R_N<13> NC_PEG_D2R_N<14> NC_PEG_D2R_N<15>

=PEG_D2R_P<0> =PEG_D2R_P<1> =PEG_D2R_P<2> =PEG_D2R_P<3> =PEG_D2R_P<4> =PEG_D2R_P<5> =PEG_D2R_P<6> =PEG_D2R_P<7> PCIE_T29_D2R_P<0> PCIE_T29_D2R_P<1> PCIE_T29_D2R_P<2> PCIE_T29_D2R_P<3> NC_PEG_D2R_P<12> NC_PEG_D2R_P<13> NC_PEG_D2R_P<14> NC_PEG_D2R_P<15>

=PEG_R2D_C_N<0> =PEG_R2D_C_N<1> =PEG_R2D_C_N<2> =PEG_R2D_C_N<3> =PEG_R2D_C_N<4> =PEG_R2D_C_N<5> =PEG_R2D_C_N<6> =PEG_R2D_C_N<7> PCIE_T29_R2D_C_N<0> PCIE_T29_R2D_C_N<1> PCIE_T29_R2D_C_N<2> PCIE_T29_R2D_C_N<3> NC_PEG_R2D_C_N<12> NC_PEG_R2D_C_N<13> NC_PEG_R2D_C_N<14> NC_PEG_R2D_C_N<15>

=PEG_R2D_C_P<0> =PEG_R2D_C_P<1> =PEG_R2D_C_P<2> =PEG_R2D_C_P<3> =PEG_R2D_C_P<4> =PEG_R2D_C_P<5> =PEG_R2D_C_P<6> =PEG_R2D_C_P<7> PCIE_T29_R2D_C_P<0> PCIE_T29_R2D_C_P<1> PCIE_T29_R2D_C_P<2> PCIE_T29_R2D_C_P<3> NC_PEG_R2D_C_P<12> NC_PEG_R2D_C_P<13> NC_PEG_R2D_C_P<14> NC_PEG_R2D_C_P<15>

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

IN

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

These can be Placed close to J2500 and Only for debug access

FOR SANDYBRIDGE PROCESSOR

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

8 7 5 4 2 1

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

33 93

NOTE:

Intel is investigating processor driven VREF_DQ generation. This connection is to support the same.

33 93

PP0V75_S3_MEM_VREFDQ_A

26 30

PP0V75_S3_MEM_VREFDQ_B

28 30

NOSTUFF

R1023

0

1 2

5% 1/16W MF-LF

402

NOSTUFF

R1021

0

1 2

5% 1/16W MF-LF

402

1

R1022

1K

1% 1/16W MF-LF 402

2

1

R1020

1K

1% 1/16W MF-LF 402

2

23 90

23

23 90

50 98

BI

50 98

BI

CPU_CFG<0>

9

CPU_CFG<1>

9

CPU_CFG<2>

9

CPU_CFG<3>

9

CPU_CFG<4>

9

CPU_CFG<5>

9

CPU_CFG<6>

9

CPU_CFG<7>

9

CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15> CPU_CFG<16>

9

CPU_CFG<17>

CPU_MEM_VREFDQ_A CPU_MEM_VREFDQ_B

CPU_THERMD_P CPU_THERMD_N

B57

CFG_0

(IPU)

D57

CFG_1

B55

CFG_2

A54

CFG_3

A58

CFG_4

D55

CFG_5

C56

CFG_6

E54

CFG_7

J54

CFG_8

G56

CFG_9

F55

CFG_10

K55

CFG_11

F57

CFG_12

E58

CFG_13

H57

CFG_14

H55

CFG_15

D53

CFG_16

K57

CFG_17

BB17 AY17 BD29 BD33 BC30 BE32 AW42 BA48 BC42 AW46 BG26 BB25 BG34 BH35 BJ34 BF35 BF41 BH43 BJ42 BF43

AW50 BB57 BF63

AD5 AH5 AJ6

BF3

BG4 BD19 AY45 AY41 BG62 BB43

D49

B53

G52

G64

AJ10

BE6

AA4

AC4

AC6

C52

C24

D25

B25

K47

H47

D3 C4

RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18 RSVD_19 RSVD_20

RSVD_22 RSVD_23 RSVD_24

RSVD_25 RSVD_26 RSVD_27

RSVD_28 RSVD_29 RSVD_30 RSVD_31 RSVD_32 RSVD_33 RSVD_34

RSVD_35 RSVD_36

RSVD_38 RSVD_39

RSVD_40

RSVD_41 RSVD_42 RSVD_43 RSVD_44

RSVD_45

RSVD_46 RSVD_47 RSVD_48 RSVD_49 RSVD_50

RSVD_51 RSVD_52

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC

NC NC NC NC NC

NC NC

NC

NC NC NC NC

NC

NC NC NC NC NC

U1000

(IPU)

SANDY-BRIDGE

(IPU)

MOBILE-REV1

(IPU)

(5 OF 11)

(IPU)

RESERVED

(IPU)

(DDR_VREF0)

(DDR_VREF1)

(THERMDA)

(THERMDC)

BGA

OMIT

PAGE TITLE

F5

RSVD_53 RSVD_54 RSVD_55 RSVD_56 RSVD_57 RSVD_58 RSVD_59 RSVD_60 RSVD_61 RSVD_62 RSVD_63 RSVD_64 RSVD_65 RSVD_66 RSVD_67 RSVD_68

RSVD_69 RSVD_70 RSVD_71 RSVD_72

RSVD_78 RSVD_79 RSVD_80 RSVD_81 RSVD_82 RSVD_83 RSVD_84 RSVD_85 RSVD_86 RSVD_87 RSVD_88 RSVD_89 RSVD_90 RSVD_91 RSVD_92 RSVD_93 RSVD_94 RSVD_95 RSVD_96 RSVD_97

K9 H5 L10 G4 K7 K5 M9 L6 J2 L2 P7 M5 J4 L4 N6

G48 K49 H49 J50

AY13 BB13 BB15 AY15 AW14 BD13 BA16 BE16 BD15 BC14 BF19 BH19 BF21 BH21 BF23 BH23 BF25 BH25 BJ22 BG22

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

REVISION

BRANCH

PAGE

10 OF 132

SHEET

9 OF 101

SIZE

D

C

B

A

D

36

345678

2 1

D

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

1

R1101

68

5%

1/16W

MF-LF

402

2

CPU_PROC_SEL_L

17 90

C

CPU_PROCHOT_L

45 67 90

BI

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

PLT_RST_CPU_BUF_L

23 25

IN

R1126

1/16W MF-LF

1

75

1%

402

2

R1103

56

5% 1/16W MF-LF

402

12

R1125

43.2

12

1% 1/16W MF-LF

402

OUT

CPU_CATERR_L

90

OUT

CPU_PECI

19 44 90

BI

CPU_PROCHOT_R_L

PM_THRMTRIP_L

19 90

OUT

PLT_RESET_LS1V1_L

PM_SYNC

17 90

IN

CPU_PWRGD

19 23 90

IN

PM_MEM_PWRGD_R

CPU_MEM_RESET_L

29

PP1V5_S3RS0_CPUDDR

7

10 13 15 29 71 72

PLACE_NEAR=R1121.2:1mm

PM_MEM_PWRGD

17 29 90

B

R1120 and R1121 are Intel recommended values

IN

PP1V5_S3RS0_CPUDDR

7

10 13 15 29 71 72

PLACE_NEAR=U1000.BJ44:2.54mm

NOSTUFF

R1130

NOSTUFF

R1131

100

1/16W MF-LF

100

1/16W MF-LF

402

1

R1120

200

1% 1/16W MF-LF

402

2

PLACE_NEAR=U1000.AY25:51.562mm

1

1%

2

1

1%

2

NOSTUFF

1

C1130

0.1UF

10% 16V

2

X5R 402

R1121

130

1% 1/16W MF-LF

402

12

OUT

CPU_DDR_VREF

1

2

PLACE_NEAR=U1000.BJ46:12.7mm

R1113

R1112

25.5

140

1%

1/16W

MF-LF

402

2

PLACE_NEAR=U1000.BG46:12.7mm

NOSTUFF

1

R1100

1K

5%

1/20W

MF

201

2

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1> CPU_SM_RCOMP<2>

1

R1114

200

1%

PLACE_NEAR=U1000.BF45:12.7mm

1/16W MF-LF 402

2

NOSTUFF

1

R1104

51

5% 1/16W MF-LF 402

2

NOSTUFF

1

R1102

1K

5% 1/20W MF 201

2

B59

PROC_DETECT*

NC

AH9

PROC_SELECT*

H53

CATERR*

F53

PECI

H51

PROCHOT*

F51

THERMTRIP*

K51

RESET*

K53

PM_SYNC

C60

UNCOREPWRGOOD

AY25

SM_DRAMPWROK

BE24

SM_DRAMRST*

BJ44

SM_VREF

BJ46

SM_RCOMP_0

BG46

SM_RCOMP_1

BF45

SM_RCOMP_2

1

R1111

10K

5%

PLACE_NEAR=U1800.AY11:157mm

1/16W MF-LF 402

2

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

(2 OF 11)

OMIT

THERMAL

PWR MGMT

DDR3 MISC

DPLL_REF_CLK

DPLL_REF_CLK*

BCLK_ITP

BCLK_ITP*

CLOCKS

(IPU)

(IPD)

(IPU)

BPM_0*

(IPU)

BPM_1*

(IPU)

JTAG & BPM

BPM_2*

(IPU)

BPM_3*

(IPU)

BPM_4*

(IPU)

BPM_5*

(IPU)

BPM_6*

(IPU)

BPM_7*

(IPU)

BCLK

BCLK*

PRDY* PREQ*

TCK TMS

TRST*

TDI TDO

DBR*

AJ4 AJ2

K63 K65

D5 C6

J62 H65

J58 H59 H63

K61 K59

H61

C62 D61 E62 F63 D59 F61 F59 G60

DPLL_REF_CLK DPLL_REF_CLK_L

1

R1141

1K

5% 1/16W MF-LF 402

2

PP1V05_S0_CPU_VCCPQE

1

R1140

1K

5% 1/16W MF-LF 402

2

Unused eDP CLK

ITPCPU_CLK100M_P ITPCPU_CLK100M_N

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

XDP_CPU_PRDY_L XDP_CPU_PREQ_L

XDP_CPU_TCK XDP_CPU_TMS XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

7

12 14

16 90

IN

16 90

IN

16 90

IN

16 90

IN

23 90

OUT

23 90

IN

23 90

IN

23 90

IN

23 90

IN

23 90

IN

23 90

OUT

23 25 90

OUT

23 90

BI

23 90

BI

23 90

BI

23 90

BI

23 90

BI

23 90

BI

23 90

BI

23 90

BI

D

C

B

PLACE_NEAR=U1000.BJ44:2.54mm

A

8 7 5 4 2 1

36

PAGE TITLE

CPU CLOCK/MISC/JTAG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

11 OF 132

SHEET

10 OF 101

SIZE

A

D

345678

2 1

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

MEM_A_DQ<0>

6

27 91

BI

MEM_A_DQ<1>

6

27 91

BI

MEM_A_DQ<2>

6

27 91

BI

MEM_A_DQ<3>

6

27 91

BI

MEM_A_DQ<4>

6

27 91

D

C

B

BI

MEM_A_DQ<5>

6

27 91

BI

MEM_A_DQ<6>

6

27 91

BI

MEM_A_DQ<7>

6

27 91

BI

MEM_A_DQ<8>

6

27 91

BI

MEM_A_DQ<9>

6

27 91

BI

MEM_A_DQ<10>

6

27 91

BI

MEM_A_DQ<11>

6

27 91

BI

MEM_A_DQ<12>

6

27 91

BI

MEM_A_DQ<13>

6

27 91

BI

MEM_A_DQ<14>

6

27 91

BI

MEM_A_DQ<15>

6

27 91

BI

MEM_A_DQ<16>

6

27 91

BI

MEM_A_DQ<17>

6

27 91

BI

MEM_A_DQ<18>

6

27 91

BI

MEM_A_DQ<19>

6

27 91

BI

MEM_A_DQ<20>

6

27 91

BI

MEM_A_DQ<21>

6

27 91

BI

MEM_A_DQ<22>

6

27 91

BI

MEM_A_DQ<23>

6

27 91

BI

MEM_A_DQ<24>

6

27 91

BI

MEM_A_DQ<25>

6

27 91

BI

MEM_A_DQ<26>

6

27 91

BI

MEM_A_DQ<27>

6

27 91

BI

MEM_A_DQ<28>

6

27 91

BI

MEM_A_DQ<29>

6

27 91

BI

MEM_A_DQ<30>

6

27 91

BI

MEM_A_DQ<31>

6

27 91

BI

MEM_A_DQ<32>

6

26 27 91

BI

MEM_A_DQ<33>

6

27 91

BI

MEM_A_DQ<34>

6

27 91

BI

MEM_A_DQ<35>

6

27 91

BI

MEM_A_DQ<36>

6

27 91

BI

MEM_A_DQ<37>

6

27 91

BI

MEM_A_DQ<38>

6

27 91

BI

MEM_A_DQ<39>

6

27 91

BI

MEM_A_DQ<40>

6

27 91

BI

MEM_A_DQ<41>

6

27 91

BI

MEM_A_DQ<42>

6

27 91

BI

MEM_A_DQ<43>

6

27 91

BI

MEM_A_DQ<44>

6

27 91

BI

MEM_A_DQ<45>

6

27 91

BI

MEM_A_DQ<46>

6

27 91

BI

MEM_A_DQ<47>

6

27 91

BI

MEM_A_DQ<48>

6

27 91

BI

MEM_A_DQ<49>

6

27 91

BI

MEM_A_DQ<50>

6

27 91

BI

MEM_A_DQ<51>

6

27 91

BI

MEM_A_DQ<52>

6

27 91

BI

MEM_A_DQ<53>

6

27 91

BI

MEM_A_DQ<54>

6

27 91

BI

MEM_A_DQ<55>

6

27 91

BI

MEM_A_DQ<56>

6

27 91

BI

MEM_A_DQ<57>

6

27 91

BI

MEM_A_DQ<58>

6

27 91

BI

MEM_A_DQ<59>

6

27 91

BI

MEM_A_DQ<60>

6

27 91

BI

MEM_A_DQ<61>

6

27 91

BI

MEM_A_DQ<62>

6

27 91

BI

MEM_A_DQ<63>

6

27 91

BI

MEM_A_BA<0>

6

26 91

OUT

MEM_A_BA<1>

6

26 91

OUT

MEM_A_BA<2>

6

26 91

OUT

MEM_A_CAS_L

6

26 91

OUT

MEM_A_RAS_L

6

26 91

OUT

MEM_A_WE_L

6

26 91

OUT

AL6 AL8 AP7 AM5

AK7 AL10 AN10

AM9 AR10

AR8

AV7

AY5

AT5

AR6

AW6

AT9

BA6

BA8

BG6

AY9

AW8

BB7

BC8

BE4 AW12 AV11 BB11 BA12

BE8 BA10 BD11 BE12 BB49 AY49 BE52 BD51 BD49 BE48 BA52 AY51 BC54 AY53 AW54 AY55 BD53 BB53 BE56 BA56 BD57 BF61 BA60 BB61 BE60 BD63 BB59 BC58 AW58 AY59 AL60 AP61 AW60 AY57 AN60 AR60

BA36 BC38 BB19

BE44 BE36 BA44

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

SA_BS_0 SA_BS_1 SA_BS_2

SA_CAS* SA_RAS* SA_WE*

(SYM 3 OF 11)

OMIT

MEMORY CHANNEL A

SA_CK_0*

SA_CKE_0

SA_CK_1*

SA_CKE_1

SA_CS_0* SA_CS_1*

SA_ODT_0 SA_ODT_1

SA_DQS_0* SA_DQS_1* SA_DQS_2* SA_DQS_3* SA_DQS_4* SA_DQS_5* SA_DQS_6* SA_DQS_7*

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7

SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_CK_0

SA_CK_1

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9

BB31 BA32

BC18

AW34 AY33

BD17

BD41 BD45

BB41 BC46

AN8 AU6 BC6 BD9 BC50 BB55 BD59 AU60

AN6 AU8 BD5 BC10 BB51 BD55 BD61 AV61

BD27 BA28 BB27 AW26 BB23 BA24 AY21 BD21 BC22 BB21 AW38 AW22 BA20 BB45 BE20 AW18

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<0> MEM_A_CS_L<1>

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13> MEM_A_A<14> MEM_A_A<15>

MEM_B_DQ<0>

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

26 27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

26 27 91

BI

6

27 91

BI

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

6

26 91

OUT

27 91

BI

MEM_B_DQ<1>

6

27 91

BI

MEM_B_DQ<2>

6

27 91

BI

MEM_B_DQ<3>

6

27 91

BI

MEM_B_DQ<4>

6

27 91

BI

MEM_B_DQ<5>

6

27 91

BI

MEM_B_DQ<6>

6

27 91

BI

MEM_B_DQ<7>

6

27 91

BI

MEM_B_DQ<8>

6

27 91

BI

MEM_B_DQ<9>

6

27 91

BI

MEM_B_DQ<10>

6

27 91

BI

MEM_B_DQ<11>

6

27 91

BI

MEM_B_DQ<12>

6

27 91

BI

MEM_B_DQ<13>

6

27 91

BI

MEM_B_DQ<14>

6

27 91

BI

MEM_B_DQ<15>

6

27 91

BI

MEM_B_DQ<16>

6

27 91

BI

MEM_B_DQ<17>

6

27 91

BI

MEM_B_DQ<18>

6

27 91

BI

MEM_B_DQ<19>

6

27 91

BI

MEM_B_DQ<20>

6

27 91

BI

MEM_B_DQ<21>

6

27 91

BI

MEM_B_DQ<22>

6

27 91

BI

MEM_B_DQ<23>

6

27 91

BI

MEM_B_DQ<24>

6

27 91

BI

MEM_B_DQ<25>

6

27 91

BI

MEM_B_DQ<26>

6

27 91

BI

MEM_B_DQ<27>

6

27 91

BI

MEM_B_DQ<28>

6

27 91

BI

MEM_B_DQ<29>

6

27 91

BI

MEM_B_DQ<30>

6

27 91

BI

MEM_B_DQ<31>

6

27 91

BI

MEM_B_DQ<32>

6

27 28 91

BI

MEM_B_DQ<33>

6

27 91

BI

MEM_B_DQ<34>

6

27 91

BI

MEM_B_DQ<35>

6

27 91

BI

MEM_B_DQ<36>

6

27 91

BI

MEM_B_DQ<37>

6

27 91

BI

MEM_B_DQ<38>

6

27 91

BI

MEM_B_DQ<39>

6

27 91

BI

MEM_B_DQ<40>

6

27 91

BI

MEM_B_DQ<41>

6

27 91

BI

MEM_B_DQ<42>

6

27 91

BI

MEM_B_DQ<43>

6

27 91

BI

MEM_B_DQ<44>

6

27 91

BI

MEM_B_DQ<45>

6

27 91

BI

MEM_B_DQ<46>

6

27 91

BI

MEM_B_DQ<47>

6

27 91

BI

MEM_B_DQ<48>

6

27 91

BI

MEM_B_DQ<49>

6

27 91

BI

MEM_B_DQ<50>

6

27 91

BI

MEM_B_DQ<51>

6

27 91

BI

MEM_B_DQ<52>

6

27 91

BI

MEM_B_DQ<53>

6

27 91

BI

MEM_B_DQ<54>

6

27 91

BI

MEM_B_DQ<55>

6

27 91

BI

MEM_B_DQ<56>

6

27 91

BI

MEM_B_DQ<57>

6

27 91

BI

MEM_B_DQ<58>

6

27 91

BI

MEM_B_DQ<59>

6

27 91

BI

MEM_B_DQ<60>

6

27 91

BI

MEM_B_DQ<61>

6

27 91

BI

MEM_B_DQ<62>

6

27 91

BI

MEM_B_DQ<63>

6

27 91

BI

MEM_B_BA<0>

6

28 91

OUT

MEM_B_BA<1>

6

28 91

OUT

MEM_B_BA<2>

6

28 91

OUT

MEM_B_CAS_L

6

28 91

OUT

MEM_B_RAS_L

6

28 91

OUT

MEM_B_WE_L

6

28 91

OUT

AL4 AK3 AP3 AR2 AL2 AK1 AP1 AR4 AV3 AU4 BA4 BB1 AV1 AU2 BA2 BB3 BC2

BF7 BF11 BJ10

BC4

BH7 BH11 BG10 BJ14 BG14 BF17 BJ18 BF13 BH13 BH17 BG18 BH49 BF47 BH53 BG50 BF49 BH47 BF53 BJ50 BF55 BH55 BJ58 BH59 BJ54 BG54 BG58 BF59 BA64 BC62 AU62 AW64 BA62 BC64 AU64 AW62 AR64 AT65 AL64 AM65 AR62 AT63 AL62 AM63

BJ38 BD37 AY29

BH39 BG38 BF39

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

SB_BS_0 SB_BS_1 SB_BS_2

SB_CAS* SB_RAS* SB_WE*

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

(SYM 4 OF 11)

OMIT

MEMORY CHANNEL B

SB_CK_0

SB_CK_0*

SB_CKE_0

SB_CK_1

SB_CK_1*

SB_CKE_1

SB_CS_0* SB_CS_1*

SB_ODT_0 SB_ODT_1

SB_DQS_0* SB_DQS_1* SB_DQS_2* SB_DQS_3* SB_DQS_4* SB_DQS_5* SB_DQS_6* SB_DQS_7*

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

BF33 BH33

BD25

BF37 BH37

BJ26

BE40 BH41

BG42 BH45

AN4 AW2 BH9 BF15 BF51 BH57 AY63 AN62

AN2 AW4 BF9 BH15 BH51 BF57 AY65 AN64

BF31 BH31 BB37 BC34 BF27 BB33 BH27 BG30 BH29 BF29 AY37 BJ30 AW30 BA40 BB29 BE28

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CS_L<0> MEM_B_CS_L<1>

MEM_B_ODT<0> MEM_B_ODT<1>

MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13> MEM_B_A<14> MEM_B_A<15>

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 28 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 91

BI

6

27 28 91

BI

6

27 91

BI

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

6

28 91

OUT

D

C

B

A

PAGE TITLE

CPU DDR3 INTERFACES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=06/15/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

12 OF 132

SHEET

11 OF 101

SIZE

A

D

345678

2 1

D

7

15

7

14

7

10 14

49 50 51 53 56 60 61 71 72 79 6 7

16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 48 82 83 84 87 88 89 98

101

PPVCORE_S0_CPU

6 7

12 14 48 68

R46

VCC_0

R42

VCC_1

R40

VCC_2

R36

VCC_3

R34

VCC_4

R29

VCC_5

R27 G38

VCC_6

R23

VCC_7

R21

VCC_8

N45

VCC_9

N43

VCC_10

N39

VCC_11

N37

VCC_12

N33

VCC_13

N30

VCC_14

N26

VCC_15

N24

VCC_16

N20

VCC_17

M46

VCC_18

M42

VCC_19

M40

VCC_20

M36

VCC_21

M34

VCC_22

M29

VCC_23

M27

VCC_24

M23

VCC_25

M21

VCC_26

L44

VCC_27

L40

VCC_28

L38

VCC_29

L34

VCC_30

L32

VCC_31

L28

VCC_32

L26

VCC_33

L22

VCC_34

K45

VCC_35

K43

VCC_36

K41

VCC_37

K37

VCC_38

K35

VCC_39

K31

VCC_40

K29

VCC_41

K25

VCC_42

J44

VCC_43

J40

VCC_44

J38

VCC_45

J34

VCC_46

J32

VCC_47

J28

VCC_48

J26

VCC_49

H45

VCC_50

H43

VCC_51

H41

VCC_52

H37

VCC_53

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

(6 OF 11)

CORE POWER

OMIT

VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98

VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107

H35 H31 H29 H25 G44 G40

G34 G32 G28 G26 F45 F43 F41 F37 F35 F31 F29 F25 E44 E40 E38 E34 E32 E28 E26 D45 D43 D41 D37 D35 D31 D29 C44 C40 C38 C34 C32 C28 C26 B45 B43 B41 B37 B35 B31 B29 A44 A40 A38 A34 A32 A28 A26

PPVCORE_S0_CPU

6 7

12 14 48 68

PP3V3_S0

For Future Compatibility

1

R1320

10K

5% 1/16W MF-LF

PPVCCSA_S0_REG

7

PP1V05_S0

PLACE_NEAR=R1310.1:2.54mm

1

R1300

75

1% 1/16W MF-LF 402

CPU_VIDSOUT

67 90

BI

CPU_VIDSCLK

67 90

OUT

CPU_VIDALERT_L

67 90

IN

PPVCORE_S0_CPU PP1V05_S0

C

NOSTUFF

1

R1360

PLACE_NEAR=U1000.B47:50.8mm

PLACE_SIDE=BOTTOM

100

1% 1/16W MF-LF

402

2

67 90

OUT

67 90

OUT

67 90

OUT

67 90

OUT

69 90

OUT

69 90

OUT

PPVCORE_S0_AXG

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AW10:50.8mm

NOSTUFF

1

2

1

R1362

100

R1366

1% 1/16W MF-LF 402

100

NOSTUFF

1% 1/16W MF-LF 402

2

PLACE_NEAR=U1000.F49:50.8mm

PLACE_NEAR=U1000.E50:50.8mm

PLACE_SIDE=BOTTOM

1

R1367

100

1% 1/16W MF-LF 402

2

NOSTUFF

2

6 7

12 14 48 68

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

PLACE_SIDE=BOTTOM

64

CPU_VCCSASENSE

OUT

1 2

1/16W

402

0

1 2

402

1/16W MF-LF

0

1 2

402

1/16W

101

7

12 13

15 48 68

R1364

49.9

NOSTUFF

1%

1/20W

MF

201

R1312

5%

R1311

5%

R1310

5%

43

PLACE_NEAR=U1000.B51:38mm

PPVCORE_S0_AXG

PLACE_SIDE=BOTTOM

NOSTUFF

1

R1370

49.9

1% 1/20W MF 201

2

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

PP1V05_S0

1

R1302

130

PLACE_NEAR=U1000.A50:2.54mm

1% 1/16W MF-LF 402

2

MF-LF

CPU_VIDSOUT_R

CPU_VIDSCLK_R

CPU_VIDALERT_L_R

MF-LF

PPVCORE_S0_CPU

PPVCCSA_S0_REG

1

R1368

100

1% 1/16W MF-LF 402

2

B

PLACE_NEAR=U1000.A46:50.8mm

PLACE_SIDE=BOTTOM

R1361

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AU10:50.8mm

1

R1363

100

1%

1/16W

MF-LF

402

2

NOSTUFF

PLACE_SIDE=BOTTOM

R1365

49.9

NOSTUFF

1/20W

1

R1371

PLACE_SIDE=BOTTOM

49.9

1%

MF

201

2

NOSTUFF

1% 1/20W MF 201

2

12 15 64

6 7 9 23 35 39 44 67 69 72

6 7

12 14

48 68

101

7

12 13 15 48

68

7

12

15 64

CPU_VCCSA_VID<0>

OUT

CPU_VCCSA_VID<1>

64

OUT

CPU_VCCSENSE_P CPU_VCCSENSE_N

CPU_AXG_SENSE_P CPU_AXG_SENSE_N

CPU_VCCIOSENSE_P CPU_VCCIOSENSE_N

TP_CPU_VDDQSENSE_P TP_CPU_VDDQSENSE_N

TP_CPU_DIE_SENSE

CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N

10 12 13 14 16 17 20 22

R1314

10K

5% 1/16W MF-LF

402

101

1

2

R1313

10K

5% 1/16W MF-LF 402

W17

VCCSA_0

W15

VCCSA_1

W12

VCCSA_2

U17

VCCSA_3

U15

VCCSA_4

U12

VCCSA_5

T16

VCCSA_6

T14

VCCSA_7

T11

VCCSA_8

N18

VCCSA_9

N16

VCCSA_10

N14

VCCSA_11

M17

VCCSA_12

M15

VCCSA_13

M12

VCCSA_14

M11

VCCSA_15

L18

VCCSA_16

L14

VCCSA_17

A50

VIDSOUT

D51

VIDSCLK

B51

VIDALERT*

AE10

VCCSA_VID_0

AG10

VCCSA_VID_1

B47

VCC_SENSE

A46

VSS_SENSE

F49

VAXG_SENSE

E50

VSSAXG_SENSE

AW10

VCCIO_SENSE

AU10

VSS_SENSE_VCCIO

AY19

VDDQ_SENSE

AW20

VSS_SENSE_VDDQ

K3

VCCSA_SENSE

F47

VCC_DIE_SENSE

D47

VCC_VAL_SENSE

C48

VSS_VAL_SENSE

B49

VAXG_VAL_SENSE

A48

VSSAXG_VAL_SENSE

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

(9 OF 11)

OMIT

(IPU)

VCCIO_SEL

VCCDQ_0 VCCDQ_1 VCCDQ_2 VCCDQ_3

VCCPLL_0 VCCPLL_1 VCCPLL_2

VCCPQE_0 VCCPQE_1 VCCPQE_2 VCCPQE_3

VSS_NCTF_0 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15

DC_TEST_A4 DC_TEST_A62 DC_TEST_A64

DC_TEST_B3 DC_TEST_B63 DC_TEST_B65 DC_TEST_BF1

DC_TEST_BF65

DC_TEST_BG2

DC_TEST_BG64

DC_TEST_BH1 DC_TEST_BH3

DC_TEST_BH63 DC_TEST_BH65

DC_TEST_BJ2 DC_TEST_BJ4

DC_TEST_BJ62 DC_TEST_BJ64

DC_TEST_C2 DC_TEST_C64

DC_TEST_D1 DC_TEST_D65

AJ8

AV23 AT23 AP23 AL23

AK65 AK63 AK61

AV21 AT21 AP21 AL21

BJ60 BJ6 BH61 BH5 BE64 BE2 BD65 BD1 F65 F1 E64 E2 B61 B5 A60 A6

A4 A62 A64 B3 B63 B65 BF1 BF65 BG2 BG64 BH1 BH3 BH63 BH65 BJ2 BJ4 BJ62 BJ64 C2 C64 D1 D65

6

CPU_VCCIO_SEL

TP_DC_TEST_A4 TP_DC_TEST_A62 DC_TEST_B63_A64 DC_TEST_B3_C2

DC_TEST_B65_C64 TP_DC_TEST_BF1 TP_DC_TEST_BF65 DC_TEST_BH1_BG2 DC_TEST_BG64_BH65

DC_TEST_BH3_BJ2 DC_TEST_BJ64_BH63

TP_DC_TEST_BJ4 TP_DC_TEST_BJ62

TP_DC_TEST_D1 TP_DC_TEST_D65

402

2

PP1V5_S3_CPU_VCCDQ

PP1V8_S0_CPU_VCCPLL_R

PP1V05_S0_CPU_VCCPQE

6

D

101

C

B

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side. NOTE: Intel validation sense lines per doc 439028 rev1.0

HR_PPDG sections 6.2.1 and 6.3.1.

A

SYNC_MASTER=K92_MLB

PAGE TITLE

CPU POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=08/03/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

13 OF 132

SHEET

12 OF 101

SIZE

A

D

345678

2 1

BJ56

VSS_0

BJ52

VSS_1

BJ48

VSS_2

BJ40

VSS_3

BJ32

VSS_4

BJ24

VSS_5

BJ20

VSS_6

BJ16

VSS_7

D

C

B

BJ12

BG60 BG56 BG52 BG48 BG44 BG36 BG28 BG24 BG20 BG16 BG12

BE62 BE58 BE54 BE50 BE46 BE42 BE38 BE34 BE30 BE26 BE22 BE18 BE14 BE10 BD35

BC60 BC56 BC52 BC48 BC44 BC40 BC36 BC32 BC28 BC26 BC24 BC20 BC16 BC12 BB65 BB63 BB47 BB39

BA58 BA54 BA50 BA46 BA42 BA38 BA34 BA30 BA26 BA22 BA18 BA14 AY61 AY11

AW56 AW52 AW48 AW44 AW40 AW36 AW32 AW28 AW24

BJ8

BG8 BF5

BD7 BD3

BB9 BB5

AY7 AY3 AY1

VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85

A

8 7 5 4 2 1

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

(10 OF 11)

OMIT

VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171

AW16 AV65 AV63 AV59 AV57 AV50 AV44 AV38 AV31 AV25 AV19 AV9 AV5 AU54 AU47 AU41 AU35 AU28 AU22 AU16 AU14 AT61 AT57 AT50 AT44 AT38 AT31 AT25 AT19 AT11 AT7 AT3 AT1 AR54 AR47 AR41 AR35 AR28 AR22 AP65 AP63 AP57 AP50 AP44 AP38 AP31 AP25 AP19 AP17 AP15 AP12 AP11 AP9 AP5 AN54 AN47 AN41 AN35 AN28 AN22 AM61 AM7 AM3 AM1 AL57 AL50 AL44 AL38 AL31 AL25 AL19 AK16 AK14 AK11 AK9 AK5 AJ64 AJ62 AJ60 AJ57 AH7 AH3 AH1 AG57 AG17 AG15

AG12 AF65 AF63 AF61 AF11

AF9

AF5 AE57 AD16 AD14

AD7

AD3

AD1 AC64 AC62 AC60 AC57 AB11

AB9

AB5 AA57 AA17 AA15 AA12

Y65

Y63

Y61

W57

V16

V14

V11

U64

U62

U60

U57

R57

R50

R44

R38

R31

R25

R19

R17

R15

R12

P65

P63

P61

P11

N54

N47

N41

N35

N28

N22

M57

M50

M44

M38

M31

M25

M19

L64

L62

L60

L58

L54

L50

L46

L42

L36

L30

L24

Y7 Y3 Y1

V9 V5

T7 T3 T1

P9 P5

M7 M3 M1

VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

(11 Of 11)

OMIT

VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343

L20 L16 L12 L8 K39 K33 K27 K1 J64 J60 J56 J52 J48 J46 J42 J36 J30 J24 J22 J18 J14 J10 J6 H39 H33 H27 H3 G62 G58 G54 G50 G46 G42 G36 G30 G24 G20 G16 G12 G8 F39 F33 F27 E60 E56 E52 E48 E46 E42 E36 E30 E24 E22 E18 E14 E10 E6 E4 D63 D39 D33 D27 C58 C54 C50 C46 C42 C36 C30 C20 C16 C12 C8 B39 B33 B27 A56 A52 A42 A36 A30 A24 A20 A16 A12

A8

PPVCORE_S0_AXG

7

12 15 48 68

AH65 AH63 AH61 AH58 AH56 AG64 AG62 AG60 AF58 AF56 AE64 AE62 AE60 AD65 AD63 AD61 AD58 AD56 AB65 AB63 AB61 AB58 AB56 AA64 AA62 AA60

Y58 Y56 W64 W62 W60 V65 V63 V61 V58 V56 T65 T63 T61 T58 T56 R64 R62 R60 R55 R53 R48 N64 N62 N60 N58 N56 N52 N49 M65 M63 M61 M59 M55 M53 M48 L56 L52 L48

VAXG_0 VAXG_1 VAXG_2 VAXG_3 VAXG_4 VAXG_5 VAXG_6 VAXG_7 VAXG_8 VAXG_9 VAXG_10 VAXG_11 VAXG_12 VAXG_13 VAXG_14 VAXG_15 VAXG_16 VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25 VAXG_26 VAXG_27 VAXG_28 VAXG_29 VAXG_30 VAXG_31 VAXG_32 VAXG_33 VAXG_34 VAXG_35 VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43 VAXG_44 VAXG_45 VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56 VAXG_57 VAXG_58 VAXG_59 VAXG_60 VAXG_61 VAXG_62 VAXG_63

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

(8 OF 11)

OMIT

IO POWER DDR3

GRAPHIC CORE POWER

VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26 VDDQ_27 VDDQ_28 VDDQ_29 VDDQ_30 VDDQ_31 VDDQ_32 VDDQ_33 VDDQ_34 VDDQ_35 VDDQ_36 VDDQ_37 VDDQ_38 VDDQ_39 VDDQ_40 VDDQ_41 VDDQ_42 VDDQ_43 VDDQ_44 VDDQ_45 VDDQ_46 VDDQ_47 VDDQ_48 VDDQ_49 VDDQ_50 VDDQ_51 VDDQ_52 VDDQ_53 VDDQ_54 VDDQ_55 VDDQ_56 VDDQ_57 VDDQ_58 VDDQ_59 VDDQ_60 VDDQ_61 VDDQ_62 VDDQ_63 VDDQ_64 VDDQ_65 VDDQ_66 VDDQ_67 VDDQ_68

BJ36 BJ28 BG40 BG32 BD47 BD43 BD39 BD31 BD23 BB35 AY47 AY43 AY39 AY35 AY31 AY27 AY23 AV46 AV42 AV40 AV36 AV34 AV29 AV27 AU45 AU43 AU39 AU37 AU33 AU30 AU26 AU24 AT46 AT42 AT40 AT36 AT34 AT29 AT27 AR45 AR43 AR39 AR37 AR33 AR30 AR26 AR24 AP46 AP42 AP40 AP36 AP34 AP29 AP27 AN45 AN43 AN39 AN37 AN33 AN30 AN26 AN24 AL46 AL42 AL40 AL36 AL34 AL29 AL27

PP1V5_S3RS0_CPUDDR

72

101

10 12 13 14 16 17

6 7 9 20 22 23 35 39 44 67 69

7

10 15 29 71 72

36

AV55 AV53 AV48 AV17 AV15 AV12 AU58 AU56 AU52 AU49 AU20 AU18 AT55 AT53 AT48 AT17 AT15 AT12 AR58 AR56 AR52 AR49 AR20 AR18 AR16 AR14 AP55 AP53 AP48 AN58 AN56 AN52 AN49

VCCIO_0 VCCIO_1 VCCIO_2 VCCIO_3 VCCIO_4 VCCIO_5 VCCIO_6 VCCIO_7 VCCIO_8 VCCIO_9 VCCIO_10 VCCIO_11 VCCIO_12 VCCIO_13 VCCIO_14 VCCIO_15 VCCIO_16 VCCIO_17 VCCIO_18 VCCIO_19 VCCIO_20 VCCIO_21 VCCIO_22 VCCIO_23 VCCIO_24 VCCIO_25 VCCIO_26 VCCIO_27 VCCIO_28 VCCIO_29 VCCIO_30 VCCIO_31 VCCIO_32

U1000

SANDY-BRIDGE

MOBILE-REV1

BGA

(7 OF 11)

IO POWER

OMIT

PAGE TITLE

VCCIO_33 VCCIO_34 VCCIO_35 VCCIO_36 VCCIO_37 VCCIO_38 VCCIO_39 VCCIO_40 VCCIO_41 VCCIO_42 VCCIO_43 VCCIO_44 VCCIO_45 VCCIO_46 VCCIO_47 VCCIO_48 VCCIO_49 VCCIO_50 VCCIO_51 VCCIO_52 VCCIO_53 VCCIO_54 VCCIO_55 VCCIO_56 VCCIO_57 VCCIO_58 VCCIO_59 VCCIO_60 VCCIO_61 VCCIO_62 VCCIO_63 VCCIO_64 VCCIO_65

AN20 AN18 AN16 AN14 AM11 AL55 AL53 AL48 AL17 AL15 AL12 AK58 AK56 AJ17 AJ15 AJ12 AH16 AH14 AH11 AF16 AF14 AE17 AE15 AE12 AD11 AC17 AC15 AC12 AB16 AB14 Y16 Y14 Y11

CPU POWER AND GND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

D

PP1V05_S0PP1V05_S0

67 69 72

101

6 7 9

10 12 13 14 16

17 20 22 23 35 39 44

C

B

A

DRAWING NUMBER

REVISION

BRANCH

PAGE

14 OF 132

SHEET

13 OF 101

SIZE

D

345678

2 1

CPU VCORE DECOUPLING

Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF) Apple Implementation: 4x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 16x 22uF 0603, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0603 (NOSTUFF)

PPVCORE_S0_CPU

6 7

12 48 68

101

D

PLACEMENT_NOTE (C1600-C16C7):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1600

1UF

10% 10V

2

X5R 402

1

C1601

1UF

10% 10V

2

X5R 402

1

C1602

1UF

10% 10V

2

X5R 402

1

C1603

1UF

10% 10V

2

X5R 402

1

C1604

1UF

10% 10V

2

X5R

1

C1605

1UF

10% 10V

2

X5R 402

1

C1606

1UF

10% 10V

2

X5R 402

1

C1607

1UF

10% 10V

2

X5R 402

1

C1608

1UF

10% 10V

2

X5R 402

1

C1609

1UF

10% 10V

2

X5R 402

1

C1610

1UF

10% 10V

2

X5R 402

1

C1611

1UF

10% 10V

2

X5R 402

1

C1612

1UF

10% 10V

2

X5R 402

1

C1613

1UF

10% 10V

2

X5R 402

1

C1614

1UF

10% 10V

2

X5R 402

1

C1615

1UF

10% 10V

2

X5R 402

1

C1616

1UF

10% 10V

2

X5R 402

1

C1617

1UF

10% 10V

2

X5R 402

1

C1618

1UF

10% 10V

2

X5R 402402

1

C1619

1UF

10% 10V

2

X5R 402

D

NOSTUFF

1

C16A0

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16C0

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16A1

1UF

20%

6.3V

2

X5R 0201

NOSTUFF NOSTUFF

1

C16C1

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16A2

1UF

20%

6.3V

2

X5R 0201

1

C16C2

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16A3

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16C3

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16A4

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16C4

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16A5

1UF

20%

6.3V

2

X5R 0201

1

2

NOSTUFF

C16C5

1UF

20%

6.3V X5R 0201

NOSTUFF

1

C16A6

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16C6

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16A7

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16C7

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16A8

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16A9

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B0

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B1

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B2

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B3

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B4

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B5

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B6

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B7

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B8

1UF

20%

6.3V

2

X5R 0201

NOSTUFF

1

C16B9

1UF

20%

6.3V

2

X5R 0201

PLACEMENT_NOTE (C1620-C1623):

Place near U1000 on bottom side

CRITICAL

1

C1620

10UF

20%

6.3V

2

CERM-X5R

0402-1

C

PLACEMENT_NOTE (C1624-C16D5):

Place near inductors on bottom side.

CRITICAL

1

C1624

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1621

10UF

20%

6.3V

2

CERM-X5R 0402-1

Place near inductors on bottom side.

CRITICAL

1

C1625

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1622

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1623

10UF

20%

6.3V

2

CERM-X5R 0402-1

Place near inductors on bottom side.

CRITICAL

1

C1626

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1627

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1628

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1629

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1630

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1631

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1632

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1633

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1634

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1635

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1636

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1637

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1638

22UF

20%

6.3V

2

X5R-CERM1 0603

CRITICAL

1

C1639

22UF

20%

6.3V

2

X5R-CERM1 0603

NOSTUFF

1

C16D0

22UF

20%

6.3V

2

X5R-CERM1 0603

NOSTUFF

1

C16D1

22UF

20%

6.3V

2

X5R-CERM1 0603

NOSTUFF

1

C16D2

22UF

20%

6.3V

2

X5R-CERM1 0603

NOSTUFF

1

C16D3

22UF

20%

6.3V

2

X5R-CERM1 0603

NOSTUFF

1

C16D4

22UF

20%

6.3V

2

X5R-CERM1 0603

NOSTUFF

1

C16D5

22UF

20%

6.3V

2

X5R-CERM1 0603

C

PLACEMENT_NOTE (C1640-C1645):

Place near inductors on bottom side.

CRITICAL

1

C1640

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT D2T-SM

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402 Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

1

C1641

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT D2T-SM

CRITICALCRITICAL

1

C1642

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT D2T-SM

PLACEMENT_NOTE (C1646-C1671):

101 22 23 35 39

PP1V05_S0

6 7 9

10 12

13 16 17 20

B

44 67 69 72

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1646

1UF

10% 10V

2

X5R 402

1

C1659

1UF

10% 10V

2

X5R 402

1

C1647

1UF

10% 10V

2

X5R 402

1

C1660

1UF

10% 10V

2

X5R 402

1

C1648

1UF

10% 10V

2

X5R 402

1

C1661

1UF

10% 10V

2

X5R 402

1

C1649

1UF

10% 10V

2

X5R 402

1

C1662

1UF

10% 10V

2

X5R 402

1

C1650

1UF

10% 10V

2

X5R 402

1

C1663

1UF

10% 10V

2

X5R 402

CRITICAL

1

C1643

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT D2T-SM

1

C1651

1UF

10% 10V

2

X5R

1

C1664

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1644

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT D2T-SM

1

C1652

1UF

10% 10V

2

X5R 402402

1

C1665

1UF

10% 10V

2

X5R 402

1

C1653

1UF

10% 10V

2

X5R 402

1

C1666

1UF

10% 10V

2

X5R 402

1

C1654

1UF

10% 10V

2

X5R 402

1

C1667

1UF

10% 10V

2

X5R 402

1

C1655

1UF

10% 10V

2

X5R 402

1

C1668

1UF

10% 10V

2

X5R 402

1

C1656

1UF

10% 10V

2

X5R 402

1

C1669

1UF

10% 10V

2

X5R 402

1

C1657

1UF

10% 10V

2

X5R 402

1

C1670

1UF

10% 10V

2

X5R 402

1

C1658

1UF

10% 10V

2

X5R 402

1

C1671

1UF

10% 10V

2

X5R 402

17 20 22 25 70 71 87

PP1V8_S0

6 7

CPU VCCPLL DECOUPLING

R1600

0

1

2

5% 1/16W MF-LF

402

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

1

C1685

1UF

10% 10V

2

X5R 402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

CPU VCCPLL Low pass filter

1

C1686

1UF

10% 10V

2

X5R 402

PP1V8_S0_CPU_VCCPLL_R

CRITICAL

C1687

1

330UF-0.006OHM

20% 2V POLY

2

CASE-D2-SM PLACE_NEAR=U1000.AK61:5 mm

7

12

B

PLACEMENT_NOTE (C1672-C1681):

Place near U1000 on bottom side

CRITICAL

1

C1672

10UF

20%

6.3V

2

X5R 603

Place near inductors on bottom side

C1682

1

330UF-0.006OHM

20% 2V POLY

2

A

CASE-D2-SM

CRITICAL

1

C1673

10UF

20%

6.3V

2

X5R 603

CRITICAL

C1683

1

330UF-0.006OHM

20% 2V POLY

2

CASE-D2-SM

CRITICAL

1

C1674

10UF

20%

6.3V

2

X5R 603

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1601

0.010

21

PP1V05_S0_CPU_VCCPQE

1/4W

0603

1%

MF

1

C1684

1UF

10% 10V

2

X5R 402

8 7 5 4 2 1

7

10 12

CRITICAL

1

C1675

10UF

20%

6.3V

2

X5R 603

CRITICAL

1

C1676

10UF

20%

6.3V

2

X5R 603

CRITICAL

1

C1677

10UF

20%

6.3V

2

X5R 603

CRITICAL

1

C1678

10UF

20%

6.3V

2

X5R 603

CRITICAL

1

C1679

10UF

20%

6.3V

2

X5R 603

CRITICAL

1

C1680

10UF

20%

6.3V

2

X5R 603

CRITICAL

1

C1681

10UF

20%

6.3V

2

X5R 603

SIZE

A

D

SYNC_MASTER=K92_MLB

PAGE TITLE

CPU DECOUPLING-I

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=08/19/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

16 OF 132

SHEET

14 OF 101

36

345678

2 1

VAXG DECOUPLING

Intel recommendation: 2x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 6x 22uF 0805, 2x 22uF 0805 (NOSTUFF), 6x 10uF 0603, 2x 10uF 0603 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF) Apple Implementation: 2x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 6x 22uF 0603, 2x 22uF 0603 (NOSTUFF), 6x 10uF 0402, 2x 10uF 0402 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)

PPVCORE_S0_AXG

7

12 13 48 68

D

C

PLACEMENT_NOTE (C1700-C1708):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1700

1UF

10% 10V

2

X5R 402

1

C1701

1UF

10% 10V

2

X5R 402

1

C1702

1UF

10% 10V

2

X5R 402

PLACEMENT_NOTE (C1718-C1723):

Place close to U1000 on bottom side

1

C1718

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1719

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1720

10UF

20%

6.3V

2

CERM-X5R 0402-1

PLACEMENT_NOTE (C1726-C1731):

Place near inductors on bottom side.

1

C1726

22UF

20%

6.3V

2

X5R-CERM1 0603

1

C1727

22UF

20%

6.3V

2

X5R-CERM1 0603

1

C1728

22UF

20%

6.3V

2

X5R-CERM1 0603

PLACEMENT_NOTE (C1734-C1735):

Place near inductors on bottom side.

1

C1734

470UF-4MOHM

20%

2.0V

23

POLY-TANT D2T-SM

1

C1735

470UF-4MOHM

20%

2.0V

23

POLY-TANT D2T-SM

1

C1703

1UF

10% 10V

2

X5R 402

1

C1721

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1729

22UF

20%

6.3V

2

X5R-CERM1 0603

NOSTUFF

1

C1737

470UF-4MOHM

20%

2.0V

23

POLY-TANT D2T-SM

1

C1704

1UF

10% 10V

2

X5R 402

1

C1722

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1730

22UF

20%

6.3V

2

X5R-CERM1 0603

1

C1705

1UF

10% 10V

2

X5R 402

1

C1723

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

C1731

22UF

20%

6.3V

2

X5R-CERM1 0603

1

C1706

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1724

10UF

20%

6.3V

2

CERM-X5R 0402-1

NOSTUFF

1

C1732

2

22UF

20%

6.3V X5R-CERM1 0603

1

C1707

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1725

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

2

NOSTUFF

C1733

22UF

20%

6.3V X5R-CERM1 0603

1

C1708

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1709

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1710

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1711

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1712

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1713

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1714

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1715

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1716

1UF

10% 10V

2

X5R 402

NOSTUFF

1

C1717

1UF

10% 10V

2

X5R 402

D

C

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402 Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

PP1V5_S3RS0_CPUDDR

7

10 13 29 71 72

B

PLACEMENT_NOTE (C1738-C1747):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

C1738

1UF

10% 10V

2

X5R 402

Place close to U1000 on bottom side

1

C1748

10UF

20%

6.3V

2

X5R 603

1

C1739

1UF

10% 10V

2

X5R 402

1

C1749

10UF

20%

6.3V

2

X5R 603

1

C1740

1UF

10% 10V

2

X5R 402

1

C1750

10UF

20%

6.3V

2

X5R 603

Place near inductors on bottom side

C1756

1

330UF-0.006OHM

20% 2V POLY

2

CASE-D2-SM

1

C1741

1UF

10% 10V

2

X5R 402

1

C1751

10UF

20%

6.3V

2

X5R 603

1

C1742

1UF

10% 10V

2

X5R 402

1

C1752

10UF

20%

6.3V

2

X5R 603

1

C1743

1UF

10% 10V

2

X5R 402

1

C1753

10UF

20%

6.3V

2

X5R 603

1

C1744

1UF

10% 10V

2

X5R 402

1

C1754

10UF

20%

6.3V

2

X5R 603

1

C1745

1UF

10% 10V

2

X5R 402

1

C1755

10UF

20%

6.3V

2

X5R 603

1

C1746

1UF

10% 10V

2

X5R 402

1

C1747

1UF

10% 10V

2

X5R 402

PPVCCSA_S0_REG

7

12 64

CPU VCCSA DECOUPLING

Intel recommendation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402 Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

PLACEMENT_NOTE (C1758-C1762):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

1

2

1

2

1

C1768

270UF

20% 2V

2

TANT CASE-B4-SM

C1758

1UF

10% 10V X5R 402

C1763

10UF

20%

6.3V X5R 603

1

C1759

1UF

10% 10V

2

X5R 402

1

C1764

10UF

20%

6.3V

2

X5R 603

1

C1760

1UF

10% 10V

2

X5R 402

1

C1765

10UF

20%

6.3V

2

X5R 603

1

C1761

1UF

10% 10V

2

X5R 402

1

C1766

10UF

20%

6.3V

2

X5R 603

1

C1762

1UF

10% 10V

2

X5R 402

1

C1767

10UF

20%

6.3V

2

X5R 603

B

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1700

0.010

1 2

1/4W

0603

1%

MF

PP1V5_S3_CPU_VCCDQ

1

C1757

1UF

10% 10V

2

X5R 402

7

12

A

SYNC_MASTER=K92_MLB

PAGE TITLE

CPU DECOUPLING-II

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=08/19/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

17 OF 132

SHEET

15 OF 101

SIZE

A

D

345678

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

47 48 49 50

SYSCLK_CLK32K_RTC

25

IN

RTC_RESET_L

16

PCH_SRTCRST_L

16

PCH_INTRUDER_L

56 93

IN

JTAG_T29_TMS

16 33

OUT

ENET_MEDIA_SENSE_RDIV

25

IN

23

IN

23

IN

23

IN

23

OUT

46 93

OUT

46 93

OUT

16

PCH_INTVRMEN_L

16

HDA_BIT_CLK_R

16 93

HDA_SYNC_R

16 93

PCH_SPKR

16

HDA_RST_R_L

16 93

HDA_SDIN0 NC_HDA_SDIN1

6

NC_HDA_SDIN2

6

NC_HDA_SDIN3

6

HDA_SDOUT_R

16 93

XDP_PCH_TCK

XDP_PCH_TMS

XDP_PCH_TDI

XDP_PCH_TDO

SPI_CLK_R

SPI_CS0_R_L

D

C

TP_SPI_CS1_L

SPI_MOSI_R

46 93

OUT

SPI_MISO

46 93

IN

B

PPVRTC_G3H

7

17 20 25

1

R1800

330K

5%

1/20W

MF

201

2

A

R1802

1

20K

R1801

1M

1/20W 5% 1/20W MF 201

2

C1802

1UF

10% 10V X5R 402

Q1850 376S0859 376S0859 VGS 0.35~1V

5%

MF

201

2

1

2

16 93

A20

RTCX1

C20

RTCX2

NC

D20

RTCRST*

G22

SRTCRST*

K22

INTRUDER*

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST*

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN*/GPIO33

N32

HDA_DOCK_RST*/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0*

T1

SPI_CS1*

V4

SPI_MOSI

U3

SPI_MISO

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

1

R1803

20K

5% 1/20W MF 201

2

RTC_RESET_L PCH_SRTCRST_L PCH_INTRUDER_L

PCH_INTVRMEN_L

1

C1803

1UF

10% 10V

2

X5R 402

PCH_CLK14P3M_REFCLK PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

98 71 72 79 82 83 84 87 88 89 47 48 49 50 51 53 56 60 61

12 16 17 18 19 20 22 23

16 17 18 19 20 22 45 70 71

16

1

2

COUGAR-POINT

PP3V3_T29

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45

PP3V3_SUS

7 72

R1843

16

R1891

10K

5% 1/20W MF 201

U1800

MOBILE

FCBGA

(1 OF 10)

OMIT

1

10K

5%

1/20W

MF

201

2

16 17 18 19 20 22 45 70 71

1

R1892

10K

5% 1/20W MF 201

2

RTC

IHDA

JTAG

SPI

R1848

10K

1/20W

12 16 17 18 19 20 22 23

PP3V3_SUS

7 72

LPC

SATA

201

FWH4/LFRAME*

LDRQ1*/GPIO23

SATAICOMPO SATAICOMPI

SATA0GP/GPIO21 SATA1GP/GPIO19

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

1

R1846

5%

MF

2

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

1

R1893

10K

5% 1/20W MF 201

2

UNUSED clock terminations for FCIM MODE

8 7 5 4 2 1

12 16 17 18 19 20 22 23

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LDRQ0*

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATALED*

1

10K

5%

1/20W

MF

201 201

2

R1847

10K

5%

1/20W

MF

201

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45 51 53 56 60 61 71 72 79 82 83 84 87 88 89 98

C38 A38 B37 C37

D36

E36 K36

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

92

Y11 Y10

P3

V14 P1

AB13 AB12 AH1

1

R1845

R1844

10K

5%

1/20W

MF

2

NOSTUFF

R1833

10K

5%

1/20W

MF

1

2

201

PCIECLKRQ5_L_GPIO44

1

R1894

10K

5% 1/20W MF 201

2

1

2

LPC_R_AD<0>

LPC_R_AD<1>

LPC_R_AD<2>

LPC_R_AD<3>

LPC_FRAME_R_L

NC_LPC_DREQ0_L

T29_PWR_EN_PCH

R1862

R1863

R1864

LPC_SERIRQ

SATA_HDD_D2R_N SATA_HDD_D2R_P SATA_HDD_R2D_C_N SATA_HDD_R2D_C_P

SATA_ODD_D2R_N SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

TP_SATA_C_D2RN TP_SATA_C_D2RP TP_SATA_C_R2D_CN TP_SATA_C_R2D_CP

NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP

NC_SATA_E_D2RN NC_SATA_E_D2RP NC_SATA_E_R2D_CN NC_SATA_E_R2D_CP

NC_SATA_F_D2RN NC_SATA_F_D2RP NC_SATA_F_R2D_CN NC_SATA_F_R2D_CP

PCH_SATAICOMP

PCH_SATALED_L

DP_AUXCH_ISOL

SATARDRVR_EN

(IPU)

PLACE_NEAR=U1800.AB12:2.54mm

PCH_SATA3COMP

92

PCH_SATA3RBIAS

1

R1878

1

5%

MF

201

2

1

R1834

2

R1895

10K

5% 1/20W MF 201

1/20W

4.7K

10K

201

5%

MF

1/20W

201

1

2

5%

MF

2

16

1

R1896

10K

5% 1/20W MF 201

2

R1842

DP_AUXCH_ISOL

SATARDRVR_EN

R1860

R1861

5%

1/20W

10K

1/20W

201

5%

MF

1/20W

5%

1

R1869

2

1

R1897

10K

5% 1/20W MF 201

2

21

MF

21

MF

33

6

OUT

IN

OUT

IN

OUT

6

16

OUT

10K

1/20W

201

16 23 90

16 23 84

16 23 41

21

33

MF5%

21

MF

LPC_AD<2>

201

LPC_AD<3>

20133MF

LPC_FRAME_L

201

(IPU)

1

5%

MF

2

33

41 92

LPC_AD<0>

201

LPC_AD<1>

201

19

BI

6

44 46 87 93

BI

6

44 46 87 93

BI

6

44 46 87 93

OUT

PP1V05_S0

1

R1831

16 23 84

49.9

1%

16 23 41

1/20W

R1832

MF

201

2

PLACE_NEAR=U1800.AH1:2.54mm

1

2

R1876

1/20W

10K

1

5%

MF

201

2

R1877

4.7K

1/20W

5%

MF

201

ITPXDP_CLK100M_N

ITPXDP_CLK100M_P

HDA_BIT_CLK_R

16 93

HDA_SYNC_R

16 93

PLACE_NEAR=U1800.K34:1.27mm

HDA_RST_R_L

16 93

HDA_SDOUT_R

16 93

6

44 46 87 93

6

44 46 87 93

1

750

5%

1/20W

MF

201

2

JTAG_T29_TMS PCH_SPKR FW_CLKREQ_L AP_CLKREQ_L PCH_SATALED_L EXCARD_CLKREQ_L T29_CLKREQ_L PEG_CLKREQ_L PEG_B_CLKRQ_L_GPIO56 ENET_CLKREQ_L

R1840

R1841

R1830

37.4

1

1/20W

R1820

10K

2

6 7 9 39 44 67 69 72

NOSTUFF

2 1

NOSTUFF

2 1

201 5% 1/20W MF 201

6

44 46

BI

10 12 13 14 16 17 20 22 23 35

101

0

1/20W

201

0

1/20W

5%

201

1%

MF

PLACE_NEAR=U1800.N34:1.27mm

R1810

33

1 2

5%

1/20W

PLACE_NEAR=U1800.L34:1.27mm

MF

201

R1812

33

1/20W

201

R1811

33

5%

1/20W

MF

201

21

5%

PLACE_NEAR=U1800.A36:1.27mm

MF

R1813

33

5%

1/20W

MF

201

PLACE_NEAR=U1800.Y11:2.54mm

1

PCIE_ENET_D2R_N

36 93

2

16 33

16

16 23 39

16 23 31

16

16 35

8

16 87

16

16 36

MF5%

MF

IN

36 93

IN

36 93

OUT

36 93

OUT

6

31 93

IN

6

31 93

IN

31 93

OUT

31 93

OUT

38 93

IN

38 93

IN

38 93

OUT

38 93

OUT

8

IN

8

IN

8

OUT

8

OUT

36 93

OUT

36 93

OUT

31 93

OUT

31 93

OUT

38 93

OUT

38 93

OUT

16 23 39

IN

8

93

OUT

8

93

OUT

33 93

OUT

33 93

OUT

6

16

6

16 36

IN

16 23 31

IN

16

IN

16 35

IN

8

16 87

IN

16

ITPCPU_CLK100M_N

ITPCPU_CLK100M_P

PCIE_ENET_D2R_P PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_P

PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

PCIE_FW_D2R_N PCIE_FW_D2R_P PCIE_FW_R2D_C_N PCIE_FW_R2D_C_P

NC_PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P

PCIE_CLK100M_ENET_N PCIE_CLK100M_ENET_P

PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P

PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P

FW_CLKREQ_L

NC_PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_T29_N PCIE_CLK100M_T29_P

NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P

PCIECLKRQ5_L_GPIO44

NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP

ENET_CLKREQ_L AP_CLKREQ_L EXCARD_CLKREQ_L

T29_CLKREQ_L

PEG_CLKREQ_L PEG_B_CLKRQ_L_GPIO56

HDA_BIT_CLK

21

HDA_SYNC

HDA_RST_L

21

HDA_SDOUT

SMC_SCI_L

19 44

IN

NC_PCIE_5_D2RN NC_PCIE_5_D2RP NC_PCIE_5_R2D_CN NC_PCIE_5_R2D_CP

NC_PCIE_6_D2RN NC_PCIE_6_D2RP NC_PCIE_6_R2D_CN NC_PCIE_6_R2D_CP

NC_PCIE_7_D2RN NC_PCIE_7_D2RP NC_PCIE_7_R2D_CN NC_PCIE_7_R2D_CP

NC_PCIE_8_D2RN NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN NC_PCIE_8_R2D_CP

PP1V5_S0

7

20 22 25 41 56 70

10 90

56 93

OUT

56 93

OUT

56 93

OUT

56 93

OUT

R1888

NOSTUFF

R1866

1/20W

16 17 18 19 20 22 45 70 71

16

NOSTUFF

0

2 1

201

10K

NOSTUFF

1

R1849

1

10K

5%

1/20W

MF

201

2

25

PP3V3_SUS

1/20W

5%

2

IN

MF

201

7 72

SML_PCH_0_ALERT_L SML_PCH_1_ALERT_L

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2*/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5*/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

J2

PCIECLKRQ0*/GPIO73

M1

PCIECLKRQ1*/GPIO18

A8

PCIECLKRQ3*/GPIO25

L12

PCIECLKRQ4*/GPIO26

M10

PEG_A_CLKRQ*/GPIO47

E6

PEG_B_CLKRQ*/GPIO56

U1800

COUGAR-POINT

MOBILE

FCBGA

(2 OF 10)

OMIT

SML1ALERT*/PCHHOT*/GPIO74

SMBUS

PEG

PCI-E*

FROM CLK BUFFER

CLOCK

R1849 cannot be used w/ VCCSUSHDA on S0

HDA_SYNC_R HDA_SDOUT_R

SYSCLK_CLK25M_SB

1

R1854

10K

5% 1/20W MF 201

2

PCH_GPIO11

16

16 93

1

R1855

10K

5% 1/20W MF 201

2

R1872

604

1% 1/16W MF-LF

402

1

R1853

10K

5% 1/20W MF 201

2

21

36

SMBALERT*/GPIO11

SML0ALERT*/GPIO60

SML1CLK/GPIO58

SML1DATA/GPIO75

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

FLEX

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

SYSCLK_CLK25M_SB_R

1

R1873

1K

1% 1/20W MF 201

2

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKIN_GND1_N CLKIN_GND1_P

1.8V -> 1.1V

2 1

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

PLACE_NEAR=U1800.Y47:2.54mm

E12

H14

SMBCLK

C9

SMBDATA

A12

C8

SML0CLK

SML0DATA

G12

C13

E14 M16

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

G24 E24

AK7 AK5

K45

H45

V47 V49

NC

Y47

K43

F47

H47

K49

AK14 AK13

BJ30 BG30

M7

CL_CLK1

CL_DATA1

CL_RST1*

T11

P10

R1870

1/20W

16

SYNC_MASTER=K91_MLB

PAGE TITLE

PCH SATA/PCIE/CLK/LPC/SPI

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

PCH_GPIO11

SMBUS_PCH_CLK SMBUS_PCH_DATA

SML_PCH_0_ALERT_L

SML_PCH_0_CLK SML_PCH_0_DATA

SML_PCH_1_ALERT_L

SML_PCH_1_CLK SML_PCH_1_DATA

PEG_CLK100M_N PEG_CLK100M_P

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

NC_PCH_CLKOUT_DPN NC_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

PCH_CLK33M_PCIIN

DOES THIS NEED LENGTH MATCH???

SYSCLK_CLK25M_SB_R

PCH_XCLK_RCOMP

NC_PCH_GPIO64_CLKOUTFLEX0

NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCH_GPIO66_CLKOUTFLEX2

NC_PCH_GPIO67_CLKOUTFLEX3

ITPXDP_CLK100M_N ITPXDP_CLK100M_P

PCH_CLKIN_GNDN1 PCH_CLKIN_GNDP1

NC_CLINK_CLK

NC_CLINK_DATA

NC_CLINK_RESET_L

1

R1871

10K

5%

5% 1/20W

MF

201

2

R

Apple Inc.

1

R1890

90.9

MF 1%

1/20W

201

16

23 26 28 30 41 47

OUT

61 88 93

BI

16

47 93

OUT

BI

16

47 93

OUT

BI

73 93

OUT

73 93

OUT

10 90

OUT

10 90

OUT

8

OUT

8

OUT

16 93

IN

16 93

IN

16 93

IN

16 93

IN

16 93

IN

16 93

IN

16 93

IN

25 93

IN

16

8

16 23 90

6

23 26 28 30 41 47 61 88 93

47 93

2

SYNC_DATE=10/19/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

18 OF 132

SHEET

16 OF 101

SIZE

D

C

B

A

D

345678

2 1

PP3V3_SUS

1

R1905

10K

5% 1/20W MF 201

2

D

1

R1920

750

1% 1/20W MF 201

2

C

PD on SMC page

PP1V05_S0

1

R1900

49.9

1%

PLACE_NEAR=U1800.BJ24:12.7mm

1/20W MF 201

2

90

PLACE_NEAR=U1800.BH21:2.54mm

90

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

OUT

6 9

OUT

9

OUT

9

OUT

9

OUT

6 9

OUT

9

OUT

9

OUT

DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>

DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>

DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>

PCH_DMI2RBIAS

PCH_DMI_COMP

PM_SYSRST_L

6

25 44

IN

PM_PCH_SYS_PWROK

23 89

IN

PM_PCH_PWROK

17 19 89

IN

PM_MEM_PWRGD

10 29 90

OUT

PM_DSW_PWRGD

44

IN

PM_PCH_PWROK

17 19 89

IN

PM_RSMRST_L

6

72

IN

SUSWARN_L

17

OUT

PM_PWRBTN_L

17 23 44

IN

SMC_ADAPTER_EN

44 45 72

IN

PM_BATLOW_L

45

IN

PCH_RI_L

B

7

16 17 18 19 20 22 45 70 71 72

6 7 9

10 12 13 14 16 20 22 23 35 39 44 67

69 72

101

BC24 BE20 BG18 BG20

BE24 BC20 BJ18 BJ20

AW24 AW20 BB18 AV18

AY24 AY20 AY18 AU18

BH21

BJ24 BG25

1

R1909

100K

5%

1/20W

MF

201

2

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

COUGAR-POINT

DMI2RBIAS

DMI_ZCOMP DMI_IRCOMP

K3

SYS_RESET*

P12

SYS_PWROK

L22

PWROK

B13

DRAMPWROK

E22

DPWROK

L10

APWROK

C21

RSMRST*

K16

SUSWARN*/SUSPWRDNACK/GPIO30

E20

PWRBTN*

H20

ACPRESENT/GPIO31

E10

BATLOW*/GPIO72

A10

RI*

DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low Set to Vcc when High

U1800

MOBILE

FCBGA

(3 OF 10)

DMI

OMIT

FDI

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

FDI_FSYNC0 FDI_FSYNC1

FDI_LSYNC0 FDI_LSYNC1

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

MANAGEMENT

SYSTEM POWER

SLP_S4*

SLP_S3*

SLP_A*

PMSYNCH

SLP_LAN*/GPIO29

DF_TVS

DSWVRMEN

SLP_SUS*

SUSACK*

WAKE*

TP23

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12 BC10

AV14 BB10

B9

N3

G8

N14

D10

H4

F4

G10

AY16

AP14

K14

AY1

A18

G16

C12

FDI_DATA_N<0> FDI_DATA_N<1> FDI_DATA_N<2> FDI_DATA_N<3> FDI_DATA_N<4> FDI_DATA_N<5> FDI_DATA_N<6> FDI_DATA_N<7>

FDI_DATA_P<0> FDI_DATA_P<1> FDI_DATA_P<2> FDI_DATA_P<3> FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6> FDI_DATA_P<7>

FDI_INT

FDI_FSYNC<0> FDI_FSYNC<1>

FDI_LSYNC<0> FDI_LSYNC<1>

PCIE_WAKE_L

PM_CLKRUN_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

TP_PM_SLP_A_L

TP_PCH_TP23

PM_SYNC

GPIO29_SLP_LAN_L

PCH_DF_TVS

R1980

PCH_DSWVRMEN

PM_SLP_SUS_L

PCH_SUSACK_L

9

90

6 9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

6 9

90

9

90

9

90

9

90

9

90

9

90

9

90

OUT

IN

BI

OUT

17

1K

2 1

201

OUT

IN

6 9

90

6 9

90

6 9

90

6 9

90

6 9

90

6

17 25 31 84

6

17 44 46

6

44 46

45

17 44 72

17 29 42 44 65 72

6

17 29 44 72

R1981

2.2K

10 90

1/20W

17 72

17

16 20 25

PP1V8_S0

1

5%

MF

201

2

MF5%

CPU_PROC_SEL_L

PLACE_NEAR=U1800.T43:2.54mm

PPVRTC_G3H

10 90

6 7 14 20 22 25 70 71 87

1

R1915

390K

5%

1/20W

MF

201

2

NC_CRT_IG_BLUE

6

NC_CRT_IG_GREEN

6

NC_CRT_IG_RED

6

NC_CRT_IG_DDC_CLK

6

NC_CRT_IG_DDC_DATA

6

NC_CRT_IG_HSYNC

6

NC_CRT_IG_VSYNC

6

PCH_DAC_IREF

1

R1951

1K

5% 1/20W MF 201

2

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

AT1 AT3 AT4 AT5

AT8 AT10 AT12

AU2

AU3

AV1

AV3

AV5

AV7 AV10

AY3

AY5

AY7

BA2

BA3

BB1

BB3

BB5

BB7

BC8

BD4

BE8

BF3

BF6

BG4

N48

P49

T49

T39

M40

M47

M49

T43

T42

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

U1800

COUGAR-POINT

MOBILE

FCBGA

(4 OF 10) OMIT

CRT

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48

AU47

AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DIGITAL DISPLAY INTERFACE

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

DDPD_HPD

NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP

NC_SDVO_STALLN NC_SDVO_STALLP

NC_SDVO_INTN NC_SDVO_INTP

DP_IG_DDC_CLK DP_IG_DDC_DATA

DP_IG_AUX_CH_N DP_IG_AUX_CH_P DP_IG_HPD

NC_DP_IG_MLN<0> NC_DP_IG_MLP<0> NC_DP_IG_MLN<1> NC_DP_IG_MLP<1> NC_DP_IG_MLN<2> NC_DP_IG_MLP<2> NC_DP_IG_MLN<3> NC_DP_IG_MLP<3>

NC_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_AUXN NC_DP_IG_C_AUXP NC_DP_IG_C_HPD

NC_DP_IG_C_MLN<0> NC_DP_IG_C_MLP<0> NC_DP_IG_C_MLN<1> NC_DP_IG_C_MLP<1> NC_DP_IG_C_MLN<2> NC_DP_IG_C_MLP<2> NC_DP_IG_C_MLN<3> NC_DP_IG_C_MLP<3>

NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA

NC_DP_IG_D_AUXN NC_DP_IG_D_AUXP NC_DP_IG_D_HPD

NC_DP_IG_D_MLN<0> NC_DP_IG_D_MLP<0> NC_DP_IG_D_MLN<1> NC_DP_IG_D_MLP<1> NC_DP_IG_D_MLN<2> NC_DP_IG_D_MLP<2> NC_DP_IG_D_MLN<3> NC_DP_IG_D_MLP<3>

6

8

79 83

8

79 83

8

83 92

8

83 92

8

83

8

6

6 7

6

D

C

B

17

17 23 44

6

17 25 31 84

0

2 1

201

MF

5%

1/20W

PCH_SUSACK_L

48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 18 19 20 22 23 25

26 28 32 35 36 39 40 41 45 47 72 79 82 83 84 87 88 89 98

17

R1991

8.2K

1/20W

1

5%

MF

201

2

PM_CLKRUN_L

PM_SLP_S3_L

6

17 29 44 72

PM_SLP_SUS_L

17 72

PM_SLP_S5_L

17 44 72

PM_SLP_S4_L

17 29 42 44 65 72

R1921

100K

1/20W

6

17 44 46

SIZE

A

D

1

5%

MF

201

2

R1922

100K

1/20W

1

5%

MF

201

2

R1923

100K

1/20W

1

5%

MF

201

2

R1924

100K

1/20W

1

5%

MF

201

2

PAGE TITLE

PCH DMI/FDI/GRAPHICS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

19 OF 132

SHEET

17 OF 101

36

R1986

1

2

17

R1983

1/20W

SUSWARN_L

1

10K

5%

MF

201

2

SUSWARN_L GPIO29_SLP_LAN_L PM_PWRBTN_L

PCIE_WAKE_L

6

17 25 31 84

MAKE_BASE=TRUE

72

PP3V3_SUS

7

16 17 18 19 20 22 45 70

71

82 85 89 98

PP3V3_S5

6 7

19 20 22 23 24

25 29 39 45 55 65 70 71 72

PP3V3_SUS

7

16 17 18 19 20 22 45

70 71 72

R1925

A

1/20W

PCIE_WAKE_L

1

1K

1%

MF

201

2

R1985

1/20W

6

17 25 31 84

IN

1

R1982

1K

10K

1%

MF

201

5%

1/20W

MF

201

2

PCIE_WAKE_L

8 7 5 4 2 1

345678

48 49 50 51 53 56 60 61 71 72

PP3V3_S0

6 7

12 16 17 19 20 22 23 25

26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

D

C

PLACE_NEAR=U1800.AF37:2.54mm

B

R2010 R2011 R2012 R2013

R2016 R2017 R2018

R2030 R2014 R2031

10K 10K 10K 10K

10K 10K 10K

1 2

1

1 2

5% MF

1/20W

5%

2

1/20W

21

1/20W

2

1/20W

5%

2

5% MF

1/20W

5%

1/20W

21

1/20W

5% MF

1/20W

5%

5%211/20W

1

R2050

2.37K

1%

1/20W

MF

201

2

PCI_INTA_L

201

87

201

18

201

61

201

84

201

61

6

25 29 39

OUT

25 93

OUT

25

OUT

25

6

25

OUT

87 92

OUT

87 92

OUT

87 92

OUT

8

92

OUT

87 92

OUT

87 92

OUT

87 92

OUT

8

92

OUT

87 92

OUT

87 92

OUT

87 92

OUT

87 92

OUT

87 92

OUT

8

OUT

87 92

OUT

87 92

OUT

87 92

OUT

8

OUT

6 8

OUT

6 8

OUT

6 8

OUT

8

18 87

OUT

8

18 87

OUT

6

83

OUT

83

OUT

PCI_INTB_L PCI_INTC_L PCI_INTD_L

JTAG_GMUX_TMS PCH_MLB_REVB_PD PCI_REQ3_L

PCH_PCI_GNT1_L PCH_PCI_GNT2_L PCH_PCI_GNT3_L

PCI_INTE_L AUD_IP_PERIPHERAL_DET T29_MCU_INT_L AUD_I2C_INT_L

NC_PCI_PME_L

PLT_RESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R LPC_CLK33M_GMUX_R NC_PCI_CLK33M_OUT3 PCH_CLK33M_PCIOUT

LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_N<2> NC_LVDS_IG_A_DATAN<3>

LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_P<2> NC_LVDS_IG_A_DATAP<3>

LVDS_IG_A_CLK_N LVDS_IG_A_CLK_P

LVDS_IG_B_DATA_N<0> LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2> NC_LVDS_IG_B_DATAN<3>

LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_P<2> NC_LVDS_IG_B_DATAP<3>

TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP

PCH_LVDS_IBG NC_PCH_LVDS_VBG

6

TP_LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_DATA LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

MF

MF5%

MF

AN48 AM47 AK47 AJ48

AN47 AM49 AK49 AJ47

AK39 AK40

AH45 AH47 AF49 AF45

AH43 AH49 AF47 AF43

AF40 AF39

AF37 AF36

AE48 AE47

K40 K38 H38 G38

C46 C44 E40

D47 E42 F46

G42 G40 C42 D44

K10

H49 H43 J48 K42 H40

P45 J47 M45 T45 P39 T40 K47

C6

PIRQA* PIRQB* PIRQC* PIRQD*

REQ1*/GPIO50 REQ2*/GPIO52 REQ3*/GPIO54

GNT1*/GPIO51 GNT2*/GPIO53 GNT3*/GPIO55

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

PME*

PLTRST*

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

LVDSA_DATA0* LVDSA_DATA1* LVDSA_DATA2* LVDSA_DATA3*

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSA_CLK* LVDSA_CLK

LVDSB_DATA0* LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3*

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

LVDSB_CLK* LVDSB_CLK

LVD_IBG LVD_VBG

LVD_VREFH LVD_VREFL

L_BKLTCTL L_BKLTEN L_VDD_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA

U1800

COUGAR-POINT

MOBILE

FCBGA

(5 OF 10)

OMIT

PCI

USB

LVDS

USBP0N USBP0P

USBP1N USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBP10N USBP10P

USBP11N USBP11P

USBP12N USBP12P

USBP13N USBP13P

USBRBIAS*

USBRBIAS

OC0*/GPIO59 OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

C24 A24

C25 B25

C26 A26

K28 H28

E28 D28

C28 A28

C29 B29

N28 M28

L30 K30

G30 E30

C30 A30

L32 K32

G32 E32

C32 A32

C33 B33

A14 K20 B17 C16 L16 A16 D14 C14

USB_HUB1_UP_N USB_HUB1_UP_P

NC_USB_1N NC_USB_1P

NC_USB_2N NC_USB_2P

NC_USB_3N NC_USB_3P

NC_USB_4N NC_USB_4P

NC_USB_5N NC_USB_5P

NC_USB_6N NC_USB_6P

NC_USB_7N NC_USB_7P

USB_HUB2_UP_N USB_HUB2_UP_P

USB_CAMERA_N USB_CAMERA_P

NC_USB_10N NC_USB_10P

NC_USB_11N NC_USB_11P

NC_USB_12N NC_USB_12P

NC_USB_13N NC_USB_13P

PCH_USB_RBIAS

92

R2070

22.6

1/20W

24 92

BI

24 92

BI

24 92

BI

24 92

BI

31

Camera

31

Unused

AP_PWR_EN

31 72

1

1%

MF

PLACE_NEAR=U1800.B33:2.54mm

201

2

R2060

1/20W

USB HUB 1

Unused

USB HUB 2

1

10K

5%

MF

201

2

R2065

1/20W

10K

1

R2061

10K

5%

5% 1/20W

MF

201

2

201

2

R2062

1/20W

10K

1

R2064

1

10K

5%

1/20W MF

MF

201

2

201

2

1

R2067

10K

5% 1/20W MF 201

2

R2069

1/20W

2 1

10K

PP3V3_S3

PP3V3_SUS

1

R2068

10K

5% 1/20W MF 201

2

1

5%

MF

201

2

USB_HUB_SOFT_RESET_L SDCONN_STATE_RST_L ENET_PWR_EN PCH_GPIO43_OC4_L SDCONN_STATE_CHANGE PCH_GPIO10_OC6_L PCH_GPIO14_OC7_L

6 7 8 48 49 53 54 71 72 87

7

16 17 19 20 22 45 70 71 72

23 24

23

23 32

23

D

19 24 25 29 30 31 32 47

C

B

LVDS_IG_PANEL_PWR

8

18 87

LVDS_IG_BKL_ON

8

18 87

PCH_PCI_GNT3_L

18

PCH_PCI_GNT2_L

18

PCH_PCI_GNT1_L

18

NOSTUFF

R2052

10K

1/20W

NOSTUFF

R2053

1

10K

5%

MF

201

1/20W

2

NOSTUFF

R2054

1/20W

10K

1

R2055

5%

MF

201

100K

5% 1/20W MF

2

201

2

1

5%

MF

201

2

A

8 7 5 4 2 1

1

R2015

100K

5% 1/16W MF-LF 402

2

SIZE

A

D

SYNC_MASTER=K92_MLB

PAGE TITLE

SYNC_DATE=07/06/2010

PCH PCI/FLASHCACHE/USB

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

20 OF 132

SHEET

18 OF 101

36

345678

2 1

7

16 19 25 33 34 35 87

1

2

PP3V3_T29

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25

26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

1

R2199

10K

5%

1/20W

MF

201

2

NOSTUFF

1

R2198

10K

5%

1/20W

MF

201

2

PP3V3_S3

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

T29_PWR_EN_PCH

16

PM_PCH_PWROK

17 19 89

AUD_IPHS_SWITCH_EN_PCH

19 23

PM_PCH_PWROK

17 19 89

SYNC_MASTER=K91_MLB

PAGE TITLE

R2116

1/20W

1

10K

5%

MF

201

2

CRITICAL

1

2

5

6

A

U2152

08

B

A

U2152

08

B

PCH MISC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

JTAG_ISP_TDI PCH_GPIO36_SATA2GP

ENET_LOW_PWR_PCH

1

C2152

0.1UF

20% 10V

2

CERM 402

74LVC2G08GT

8

SOT833

7

Y

4

74LVC2G08GT

8

SOT833

3

AUD_IPHS_SWITCH_EN

Y

4

8

19 33

87 19 23

19 23

T29_PWR_EN

35

OUT

61

OUT

SYNC_DATE=10/20/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

21 OF 132

SHEET

19 OF 101

SIZE

D

C

B

A

D

PCH_GPIO0

19 23

IN

FW_PLUG_DET_L

8

19 39

D

C

12 16

16 19 25

49 50 51 36 39 40 22 23 25

8

19 23 33 87

19 41

19 87

PP3V3_T29

7 33 34 35 87

PP3V3_S0

6 7 17 18 19 20 26 28 32 35 41 45 47 48 53 56 60 61 71 72 79 82 83 84 87 88 89 98

JTAG_ISP_TCK

ODD_PWR_EN_L

GMUX_INT

PP3V3_SUS

7

16 17 18 19 20 22 45 70

71 72

R2111

R2193

100K

1/20W

R2160

84 87 88 89 98 41 45 47 48 49 50 51

PP3V3_S0

6 7

12 16 17 18 19 20

22 23 25 26 28 32 35 36 39 40 53 56 60 61 71 72 79 82 83

1

R2190

100K

5%

1/20W

MF

1

20K

5%

1/20W

MF

201

2

1

5%

MF

201

2

1

10K

5%

1/20W

MF

201

2

R2112

R2192

1/20W

R2184

1/20W

10K

1

10K

5%

1/20W

MF

201

2

1

5%

MF

201

2

1

5%

MF

201

2

R2113

R2194

1/20W

R2185

1/20W

10K

5%

1/20W

MF

201

1

5%

MF

201

2

1

5%

MF

201

2

1

2

T29_SW_RESET_L

19 35

PCH_GPIO12 PCH_GPIO24 SPIROM_USE_MLB

1

R2186

10K

5%

1/20W

MF

201

2

19

6

19 46 55

6

46

201

BI

(PU necessary?)

1/20W

(PUs necessary?)

2

R2180

0

1 2

5%

201

IN

GMUX_INT

19 87

IN

SMC_RUNTIME_SCI_L

19 44

IN

PCH_GPIO12

19

PCH_GPIO15

PD on audio page

19

AUD_IPHS_SWITCH_EN_PCH

19 23

OUT

LPCPLUS_GPIO

ODD_PWR_EN_L

19 41

OUT

PCH_GPIO24

19

SMC_SCI_L

16 19 44

IN

ISOLATE_CPU_MEM_L

23 29

OUT

8

19 23 33 87

OUT

8

19 33 87

IN

8

19 33 87

OUT

19 72

OUT

19

OUT

19 23

OUT

6

19 46 55

BI

T29_SW_RESET_L_R

NC_GPIO35

PCH_GPIO36_SATA2GP

19 23

JTAG_ISP_TCK

JTAG_ISP_TDO

JTAG_ISP_TDI

WOL_EN

PCH_GPIO46

19 23

FW_PWR_EN_PCH

ENET_LOW_PWR_PCH

SPIROM_USE_MLB

PCH_GPIO68_TACH4

19

PCH_GPIO69_TACH5

19

PCH_GPIO70_TACH6

19

PCH_GPIO71_TACH7

19

MF

(NC-ed per Intel chklist)

(IPU)

B

JTAG_ISP_TDO FW_PLUG_DET_L FW_PWR_EN_PCH PCH_GPIO0

WOL_EN

19 72

1

R2114

10K

5%

1/20W

MF

201

2

83 84 87 88 89 53 56 60 61 71 40 41 45 47 48 23 25 26 28 32

PP3V3_S0

6 7

12 16 17 18

19 20 22 35 36 39 49 50 51 72 79 82 98

A

R2175

1/20W

10K

5%

MF

201

1

2

R2174

1/20W

10K

1

5%

MF

201

2

R2173

1/20W

10K

1

5%

MF

201

2

R2172

1/20W

10K

6 7

17 20 22 23 24 25 29 39

45 55 65 70 71 72 82 85 89 98

1

5%

MF

201

2

16 17 18 19 20 22 45 70 71

PP3V3_S5

PP3V3_SUS

7 72

NOSTUFF

R2115

R2191

1/20W

10K

201

1/20W

5%

MF

10K

1

2

1

5%

MF

201

2

NOSTUFF

1

R2117

10K

5%

1/20W

MF

201

2

PCH_GPIO46

SMC_SCI_L

PCH_GPIO68_TACH4 PCH_GPIO69_TACH5 PCH_GPIO70_TACH6 PCH_GPIO71_TACH7

8

19 33 87

8

19 39

19

19 23

PCH_GPIO15

16 19 44

19

T7 V40

BMBUSY*/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

NC

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

(IPU)

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI*/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

T13

PCIECLKRQ6*/GPIO45

K12

PCIECLKRQ7*/GPIO46

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

C40

TACH4/GPIO68

B41

TACH5/GPIO69

C41

TACH6/GPIO70

A40

TACH7/GPIO71

A4

VSS_NCTF

A44

VSS_NCTF

A45

VSS_NCTF

A46

VSS_NCTF

A5

VSS_NCTF

A6

VSS_NCTF

B3

VSS_NCTF

B47

VSS_NCTF

BD1

VSS_NCTF

BD49

VSS_NCTF

BE1

VSS_NCTF

BE49

VSS_NCTF

BF1

VSS_NCTF

BF49

VSS_NCTF

BG2

VSS_NCTF

BG48

VSS_NCTF

BH3

VSS_NCTF

BH47

VSS_NCTF

BJ4

VSS_NCTF

BJ44

VSS_NCTF

BJ45

VSS_NCTF

BJ46

VSS_NCTF

BJ5

VSS_NCTF

BJ6

VSS_NCTF

C2

VSS_NCTF

C48

VSS_NCTF

D1

VSS_NCTF

D49

VSS_NCTF

E1

VSS_NCTF

E49

VSS_NCTF

F1

VSS_NCTF

F49

VSS_NCTF

AH8

TS_VSS1

AK11

TS_VSS2

AH10

TS_VSS3

AK10

TS_VSS4

U47

VSSADAC

8 7 5 4 2 1

U1800

COUGAR-POINT

MOBILE

FCBGA

(6 OF 10)

OMIT

MISC

GPIO

RSVD

NCTF

CPU

CLKOUT_PCIE6N CLKOUT_PCIE6P

CLKOUT_PCIE7N CLKOUT_PCIE7P

A20GATE

PECI

RCIN*

PROCPWRGD

THRMTRIP*

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

TP20

TP21

TP22

TP24

TP25

TP26

TP27

TP28

TP29

TP30

TP31

TP32

TP33

TP34

TP35

TP36

NC_1

INIT3_3V*

TP38 TP37 TP39 TP40

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

V42

V38 V37

P4

AU16

P5

AY11

AY10

BG26

BJ26

BH25

BJ16

BG16

AH38

AH37

AK43

AK45

C18

N30

H3

AH12

AM4

AM5

Y13

K24

L24

AB46

AB45

B21

M20

BG46

BE28

BC30

BE32

BJ32

BC28

BE30

BF32

BG32

AV26

BB26

AU28

AY30

P37

T14

AY26 AU26 AV28 AW30

12 16 17 18 19 20 22 23

NC

NC NC NC NC

47 48 49 50 51 53 56 60 61 71 6 7 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P

PCH_A20GATE

PCH_PECI

NOSTUFF

1 2

1/20W

PCH_RCIN_L

PCH_PROCPWRGD

PM_THRMTRIP_L_R

45

ALL RSVD TPs NC-ed per INTEL approval

PCH_INIT3V3_L

PP3V3_S0

R2196

10K

5%

1/20W

MF

201

R2170

43

5%

201

NOSTUFF

1

R2197

2

MF

1/20W

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

ENET_LOW_PWR_PCH

19 23

PM_PCH_PWROK

17 19 89

FW_PWR_EN_PCH

19

PM_PCH_PWROK

17 19 89

1

10K

5%

1/20W

MF

201

2

6

CPU_PECI

R2140

0

1 2

5%

201

PP3V3_S3

19

T29_SW_RESET_L SMC_RUNTIME_SCI_L

1

R2150

10K

5%

1/20W

MF

10 44 90

R2156

390

1 2

5%

1/20W

MF

201

MF

201

2

CPU_PWRGD

1

R2155

10K

5%

1/20W

MF

201

2

OUT

PM_THRMTRIP_L

10 23 90

GPIO ISOLATION CIRCUIT

1

C2150

0.1UF

20% 10V

2

CERM 402

CRITICAL

This has internal pull up and should not pulled low.

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

1

2

B

5

6

B

A

U2150

08

A

U2150

08

74LVC2G08GT

8

SOT833

7

Y

4

74LVC2G08GT

8

SOT833

3

Y

4

19

ENET_LOW_PWR

FW_PWR_EN

PCH_INIT3V3_L

19 35

19 44

36

PP3V3_S0

IN

OUT

NOSTUFF

R2130

1/20W

1K

201

10 90

32 36

39

5%

MF

345678

2 1

D

C

PLACE_NEAR=U1800.N16:2.54mm

PLACE_NEAR=U1800.V16:2.54mm

B

101

PPVOUT_G3_PCH_DCPRTC

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

1

C2210

0.1UF

20% 10V

2

CERM 402

MIN_LINE_WIDTH=0.2 mm

1

C2222

0.1UF

20% 10V

2

CERM 402

PCH output, for decoupling only

101

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

VCCACLK pin left as NC per DG

98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

TP_PPVOUT_PCH_DCPSUSBYP

PP3V3_S0_PCH_VCC3_3_CLK_F

22

VCCAPLLDMI2 pin left as NC per DG

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

AL24 left as NC per DG

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

PP1V8_S0

6 7

14 17 20 22 25 70 71 87

PP1V05_S0_PCH_VCCADPLLA_F

22

PP1V05_S0_PCH_VCCADPLLB_F

22

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35

39 44 67 69 72

55mA Max, 5mA Idle

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35

101

39 44 67 69 72

VOLTAGE=3.3V

NC-ed per DG

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

PPVRTC_G3H

7

16 17 25

AD49

NC

T16

V12

T38

BH23

NC

AL29

AL24

NC

AA19 AA21 AA24 AA26 AA27 AA29 AA31 AC26 AC27 AC29 AC31 AD29 AD31

W21 W23 W24 W26 W29 W31 W33

N16

Y49

BD47 BF47

AF17

AF33 AF34 AG34

AG33

V16

T17

NC

V19

NC

BJ8

A22

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3_4_CLK

VCCAPLLDMI2

VCCIO_12_PLLCLK

DCPSUS_0_CLK

VCCASW_3_CLK VCCASW_4_CLK VCCASW_5_CLK VCCASW_6_CLK VCCASW_7_CLK VCCASW_8_CLK VCCASW_9_CLK VCCASW_10_CLK VCCASW_11_CLK VCCASW_12_CLK VCCASW_13_CLK VCCASW_14_CLK VCCASW_15_CLK VCCASW_16_CLK VCCASW_17_CLK VCCASW_18_CLK VCCASW_19_CLK VCCASW_20_CLK VCCASW_21_CLK VCCASW_22_CLK

DCPRTC

VCCVRM_0_CLK

VCCADPLLA VCCADPLLB

VCCIO_13_CLK

VCCDIFFCLKN_0 VCCDIFFCLKN_1 VCCDIFFCLKN_2

VCCSSC

DCPSST

DCPSUS_1_CLK DCPSUS_2_CLK

V_PROC_IO

VCCRTC

U1800

COUGAR-POINT

MOBILE

FCBGA

(8 OF 10)

VCCSUS3_3_5_GPIO

OMIT

VCCSUS3_3_6_GPIO VCCSUS3_3_7_GPIO VCCSUS3_3_8_GPIO

LPC

PCI/GPIO/

VCCIO_5_PLLSATA

VCCIO_15_SATA3 VCCIO_16_SATA3

VCCIO_9_PLLSATA3

SATA

CLK/MISC

MISC

USB

VCCSUS3_3_1_USB VCCSUS3_3_2_USB VCCSUS3_3_3_USB VCCSUS3_3_4_USB VCCSUS3_3_9_USB

VCCIO_14_PLLUSB

VCCSUS3_3_0_SUS

CPURTC

HDA

V5REF

VCC3_3_2_GPIO VCC3_3_3_GPIO VCC3_3_1_GPIO

VCC3_3_0_SATA

VCCAPLLSATA

VCCVRM_1_SATA

VCCIO_6_SATA VCCIO_7_SATA VCCIO_8_SATA

VCCASW_2_MISC VCCASW_1_MISC VCCASW_0_MISC

VCCIO_0_USB VCCIO_1_USB VCCIO_2_USB VCCIO_3_USB VCCIO_4_USB

V5REF_SUS

DCPSUS_3_SUS

VCCSUSHDA

P34

PP5V_S0_PCH_V5REF

N20

PP3V3_SUS N22 P20 P22

AA16 W16 T34

AJ2

PP3V3_S0

AF13

AH13 AH14

PP1V05_S0

AF14

AK1

VCCAPLLSATA pin left as NC per DG

NC

AF11

AC16 AC17 AD17

T21 V21 T19

N26 P26 P28 T27 T29

T23 T24 V23 V24 P24

T26

M26

AN23

AN24

P32

PP1V8_S0

PP1V05_S0

PP3V3_SUS

PP1V05_S0

PP5V_SUS_PCH_V5REFSUS

NC-ed per DG

NC

PP3V3_SUS

PP1V5_S0

10 mA Max, 1mA Idle

22

7

16 17 18 19 20 22 45 70 71 72

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7

14 17 20 22 25 70 71 87

6 7 9

10 12 13 14 16 17 20 22 23 35 39 44

67 69 72

101

6 7 9

10 12 13 14 16 17 20 22 23

35 39 44 67 69 72

6 7 9 67 69 72

7

16 17 18 19 20 22 45 70 71 72

6 7 9 67 69 72

22

7

16 22 25 41 56 70

101

10 12 13 14 16 17 20 22 23 35 39 44

101

10 12 13 14 16 17 20 22 23 35 39 44

101

7

16 17 18 19 20 22 45 70 71 72

D

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

1.44 A Max, 474mA Idle

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

TP_1V05_S0_PCH_VCCAPLLEXP

6

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO_11_PLLPCIE

BJ22

VCCAPLLEXP

AN16

VCCIO_17_FDI

AN17

VCCIO_18_FDI

AN21

VCCIO_19_PCIE

AN26

VCCIO_20_PCIE

AN27

VCCIO_21_PCIE

AP21

VCCIO_22_PCIE

AP23

VCCIO_23_PCIE

AP24

VCCIO_24_PCIE

AP26

VCCIO_25_PCIE

AT24

VCCIO_26_PCIE

AN33

VCCIO_27_DP

AN34

VCCIO_28_DP

BH29

VCC3_3_5_PCI

U1800

COUGAR-POINT

MOBILE

FCBGA

(7 OF 10)

OMIT

LVDS

VCC CORE

VCC3_3_6_HVCMOS VCC3_3_7_HVCMOS

HVCMOS

DMI

DFT/SPI

VCCIO

FDI CRT

VCCIO_10_PLLFDI

VCCALVDS

VSSALVDS

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

VCCVRM_3_DMI

VCCDMI_1_DMI

VCCCLKDMI

VCCDFTERM VCCDFTERM VCCDFTERM VCCDFTERM

VCCSPI

VCCADAC

VCCVRM_2_FDI

VCCAFDIPLL

VCCDMI_0_FDI

AK36

PP3V3_S0

AK37

AM37 AM38 AP36 AP37

V33 V34

AT16

AT20

AB36

AG16 AG17 AJ16 AJ17

V1

U48

AP16

BG6

AP17

AU20

PP1V8_S0_PCH_VCCTX_LVDS_F

PP3V3_S0

PP1V8_S0

PP1V05_S0

PP1V05_S0_PCH_VCCCLKDMI_F

PP1V8_S0

PP3V3_S5

PP3V3_S0_PCH_VCCA_DAC_F

PP1V8_S0

VCCAFDIPLL pin left as NC per DG

NC

PP1V05_S0

47 48 49 50 51 53 56 60 61 71 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

22

47 48 49 50 51 53 56 60 61 71 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

6 7

14 17 20 22 25 70 71 87

6 7 9

10 12 13 14 16 17 20 22

23 35 39 44 67 69 72

22

6 7

14 17 20 22 25 70 71 87

98 6 7

17 19 20 22 23 24 25 29 39 45 55 65 70 71 72 82 85 89

22

6 7

14 17 20 22 25 70 71 87

6 7 9

10 12 13 14 16 17 20 22

23 35 39 44 67 69 72

6 7 9

10 12 13 14 16 17 20 22

23 35 39 44 67 69 72

101

C

B

1

C2231

1UF

10%

6.3V

2

PLACE_NEAR=U1800.A22:2.54mm

CERM 402

A

8 7 5 4 2 1

1

2

1

C2232

0.1UF

20% 10V CERM 402

C2233

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U1800.A22:2.54mm PLACE_NEAR=U1800.A22:2.54mm

SIZE

A

D

PAGE TITLE

PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

22 OF 132

SHEET

20 OF 101

36

345678

2 1

AJ3 N24

BG29

H5

AA17

D

C

B

A

AA33 AA34 AB11 AB14 AB39

AB43

AC19

AC21 AC24 AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD14 AD16 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD40 AD42 AD43 AD45 AD46 AD47

AF10 AF12 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38

AF42 AF46

AG19

AG31 AG48 AH11

AH36 AH39 AH40 AH42 AH46

AJ19 AJ21 AJ24 AJ33 AJ34 AK12

AK38

AK42

AA2 AA3

AB4

AB5 AB7

AC2

AD4

AD8 AE2 AE3

AF4

AF5 AF7 AF8

AG2

AH3

AH7

AK3

AK4

VSS

COUGAR-POINT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U1800

MOBILE

FCBGA

(9 OF 10)

VSS OMIT

8 7 5 4 2 1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP13 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV11 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AY12 AY22 AY28 AY4 AY42 AY46 AY8 B11 B15 B19 B23 B27 B31

B35

B39 B43

BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38

BB4 BB46 BC14 BC18

BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48

BD3 BD46

BD5 BE10 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BF30 BF38 BF40

BF8 BG17 BG21 BG22 BG24 BG33 BG41 BG44

BG8 BH11 BH15 BH17 BH19 BH27 BH31 BH33 BH35 BH39 BH43

BH7

C22

D12

D16

D18

D22

D24

D26

D30

D32

D34

D38

D42

E18

E26

F45

G14

G18

G20

G26

G28

G36

B7

D3

D8

F3

VSS

COUGAR-POINT

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

U1800

MOBILE

FCBGA

(10 OF 10)

VSS

OMIT

G48

VSS

H10

VSS

H12

VSS

H16

VSS

H18

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H22 H24 H26 H30 H32 H34 H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 M14 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 N47 P11 P16 P18 P30 P40 P43 P47 P7 R2 R48 T12 T31 T33 T36 T37 T4 T46 T47 T8 V11 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W34 W48 Y12 Y38 Y4 Y42 Y46 Y8 V17 AP3 AP1 BE16 BC16 BG28 BJ28

SYNC_MASTER=K92_MLB

PAGE TITLE

PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=04/30/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

23 OF 132

SHEET

21 OF 101

SIZE

D

C

B

A

D

36

345678

2 1

39 44 67 69 72

PP1V05_S0

6 7 9

10 12 13 14 16

17 20 22 23 35 101

D

87

PP1V8_S0

6 7

14 17 20 22

25 70 71

83 84 50 51 45 47 36 39 26 28

98

20 22

61 71 72

PP3V3_S0

6 7

12 16 17

18 19

53 56 60

23 25

87 88 89

32 35 40 41 48 49 79 82

C

B

PLACE_NEAR=U1800.M26:2.54mm

PLACE_NEAR=U1800.BH29:2.54mm

A

PLACE_NEAR=U1800.V33:2.54mm

CRITICAL

L2406

10UH-0.45A

1210-HF

21

PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

PLACE_NEAR=U1800.AB36:2.54mm

R2415

1

5% 1/16W MF-LF

402

PP3V3_SUS

7

16 17 18 19 20 22 45 70 71

21

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V MAKE_BASE=TRUE

1

C2411

1UF

10% 16V

2

X5R 402

20

72

PLACE_NEAR=U1800.P24:2.54mm

CRITICAL

L2407

0.1UH

88

101

12 16 17 18 19 20 22 23

41 46 51 53 64 67 68 69 71 72 86

PLACE_NEAR=U1800.P34:2.54mm

PP3V3_SUS

7

16 17 18 19 20 22 45 70 71

72

PP5V_SUS

7

71

1 mA S0-S5

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

88 89 98 41 45 47 48 49 50 51 53 56

PP3V3_S0

6 7

12 16 17 18 19 20 22

23 25 26 28 32 35 36 39 40 60 61 71 72 79 82 83 84 87

1

47 48 49 50 51 53 56 60 61 71 6 7 25 26 28 32 35 36 39 40 41 45

72 79 82 83 84 87 88 89 98 6 7 8

2

PP1V8_S0_PCH_VCCTX_LVDS_F

0805

R2450

1/20W

CRITICAL

PLACE_NEAR=U1800.U48:2.54mm PLACE_NEAR=U1800.U48:2.54mm PLACE_NEAR=U1800.U48:2.54mm

PP3V3_S0 PP5V_S0

1 mA

R2404

1/16W MF-LF

C2438

0.1UF

20% 10V

CERM

402

20

CRITICAL

1

C2400

22UF

20%

6.3V

2

CERM

805

PLACE_NEAR=U1800.AM37:2.54mm PLACE_NEAR=U1800.AM37:2.54mm PLACE_NEAR=U1800.AM37:2.54mm

0

21

5%

MF

201

1

C2450

10

5%

402

2

1

2

1

2

10UF

20%

6.3V CERM

805

C2439

NC

C2421

0.1UF

10% 16V X5R 402

C2451

2

R2405

100

5% 1/16W MF-LF

402

1

1UF

10% 10V

2

X5R 402

PCH V5REF_SUS Filter & Follower (PCH Reference for 5V Tolerance on USB)

4

2

D2400

NC

BAT54DW-X-G

SOT-363

3

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V MAKE_BASE=TRUE

1

C2424

0.1UF

10% 16V

2

X5R 402

C2406

0.01UF

CERM

1

10% 16V

2

402

C2408

0.01UF

CERM

1

10% 16V

2

402

PP3V3_S0_PCH_VCCA_DAC_F

1

0.1UF

10% 16V

2

X5R 402

PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)

1

5

NC

D2400

NC

BAT54DW-X-G

SOT-363

6

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE

1

C2455

0.01UF

10% 16V

2

CERM

402

PP5V_S0_PCH_V5REF

NEED PWR CONSTRAINT

<1 MA S0-S5

PP5V_SUS_PCH_V5REFSUS

12 16 17 18 19 20 22 23

47 48 49 50 51 53 56 60 61 71 6 7 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

20 22

PP3V3_S0

PLACE_NEAR=U1800.AJ2:2.54mm

12 16 17 18 19 20 22 23

PLACE_NEAR=U1800.T34:2.54mm

PLACE_NEAR=U1800.AA16:2.54mm

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.8V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

<1 MA

20 22

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

20 22

101

20

10 12 13 14 16 17 20 22 23 35 39

101

87 88 89 98 47 48 49 50 51 53

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 56 60 61 71 72 79 82 83 84

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

1

C2423

0.1UF

10% 16V

2

X5R 402

C2486

0.1UF

10% 25V X5R 402

1

2

C2485

0.1UF

10% 25V X5R 402

1

2

8 7 5 4 2 1

PCH VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)

1

C2484

0.1UF

10% 16V

2

X5R 402

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

PLACE_NEAR=U1800.BJ8:2.54mm PLACE_NEAR=U1800.BJ8:2.54mm PLACE_NEAR=U1800.BJ8:2.54mm

PCH VCCIO BYPASS

PP1V05_S0

6 7 9 44 67 69 72

PCH VCC3_3 BYPASS (PCH PCI 3.3V PWR)

PLACE_NEAR=U1800.AT20:2.54mm

R2451

1

21

5% 1/16W MF-LF

402

R2490

0

21

5% 1/16W MF-LF

402

R2491

0

21

5% 1/16W MF-LF

402

1

C2413

0.1UF

10% 16V

2

X5R 402

PLACE_NEAR=U1800.V24:2.54mm

1

C2416

4.7UF

20%

6.3V 2

X5R 402

1

C2419

1UF

10%

6.3V

2

CERM 402

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=3.3V

PP1V05_S0_PCH_VCCADPLLA_R

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLB_R

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V

1

C2417

2

0.1UF

10% 16V X5R 402

1

C2430

2

0.1UF

10% 16V X5R 402

98 6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

PLACE_NEAR=U1800.T16:2.54mm

CRITICAL

L2451

10UH-0.12A-0.36OHM

21

0603

CRITICAL

C2453

10UF

20%

6.3V X5R 603

PLACE_NEAR=U1800.T38:2.54mm PLACE_NEAR=U1800.T38:2.54mm

CRITICAL

L2490

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.BD47:2.54MM

CASE-B2-SM1

CRITICAL

L2491

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.BF47:2.54MM

CASE-B2-SM1

PP1V8_S0

6 7

14 17 20 22 25 70 71 87

PLACE_NEAR=U1800.AJ16:2.54mm

PCH VCCSUSHDA BYPASS

PP1V5_S0

7

16 20 25 41 56 70

PLACE_NEAR=U1800.P32:2.54mm

98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

PLACE_NEAR=U1800.V1:2.54mm

PP3V3_S5

PP3V3_S0_PCH_VCC3_3_CLK_F

20

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM VOLTAGE=3.3V

1

2

PCH VCCADPLLA Filter (PCH DPLLA PWR)

PP1V05_S0_PCH_VCCADPLLA_F

MIN_LINE_WIDTH=0.4 MM

21

MIN_NECK_WIDTH=0.2 MM

0603

CRITICAL

C2491

220UF

POLY-TANT

0603

CRITICAL

C2493

220UF

POLY-TANT

2.5V

20%

VOLTAGE=1.05V

NO STUFF

1

C2492

1UF

10%

6.3V

2

CERM 402

PCH VCCADPLLB Filter (PCH DPLLB PWR)

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM

21

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

NO STUFF

1

C2494

1UF

10%

6.3V

2

CERM 402

C2499

C2454

1UF

0.1UF

CERM

10% 10V X5R 402

PCH VCCIO BYPASS

1

C2440

0.1UF

20% 10V

2

CERM 402

1

C2441

0.1UF

20% 10V

2

CERM 402

1

C2442

1UF

10%

6.3V

2

CERM 402

1

20% 10V

2

402

1

2

101

PLACE_NEAR=U1800.AH13:2.54mm

PLACE_NEAR=U1800.AC17:2.54mm

10 12 13 14 16 17 20 22 23 35 39

101

PLACE_NEAR=U1800.AG33:2.54mm

10 12 13 14 16 17 20 22 23 35 39

101

PLACE_NEAR=U1800.AF34:2.54mm

10 12 13 14 16 17 20 22 23 35 39

101

20

68 mA

10 12 13 14 16 17 20 22 23 35 39

101

20

69 mA

1

C2444

1UF

10%

6.3V

2

CERM 402

PP1V05_S0

6 7 9 44 67 69 72

PP1V05_S0

6 7 9 44 67 69 72

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

PLACE_NEAR=U1800.AD21:2.54mm PLACE_NEAR=U1800.AG24:2.54mm PLACE_NEAR=U1800.AJ27:2.54mm PLACE_NEAR=U1800.AG26:2.54mm

PP1V05_S0

6 7 9 44 67 69 72

PP1V05_S0

6 7 9 44 67 69 72

1

C2481

1UF

10%

6.3V

2

CERM 402

1

C2426

1UF

10%

6.3V

2

CERM 402

PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm

1

2

1

C2452

1UF

10%

6.3V

2

CERM 402

1

C2475

1UF

10%

6.3V

2

CERM 402

1

2

1

C2482

1UF

10%

6.3V

2

CERM 402

1

C2456

1UF

10%

6.3V

2

CERM 402

1

2

C2414

1UF

10%

6.3V CERM 402

C2429

1UF

10%

6.3V CERM 402

SYNC_MASTER=K92_MLB

PAGE TITLE

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

(PCH USB 1.05V PWR)

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35

101

39 44 67 69 72

PLACE_NEAR=U1800.P28:2.54mm

PP3V3_SUS

7

16 17 18 19 20 22 45 70 71

72

PLACE_NEAR=U1800.P22:2.54mm

PP1V05_S0

6 7 9

10 12 13 14 16 17 20

101

C2434

1UF

10%

6.3V CERM 402

1

2

PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm

22 23 35 39 44 67 69 72

PLACE_NEAR=U1800.AF17:2.54mm

PCH VCCCORE BYPASS

(PCH 1.05V CORE PWR)

1

C2483

2

C2496

1UF

10%

6.3V CERM 402

1

C2407

2

1UF

6.3V CERM 402

1UF

10%

6.3V CERM 402

C2460

C2428

22UF

6.3V CERM

1

2

10UF

20%

805

C2463

1UF

10%

6.3V CERM 402

10%

PCH DECOUPLING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

36

1

20%

6.3V

2

CERM

805

C2420

22UF

6.3V CERM

C2401

10UF

X5R-CERM

1

20%

2

805

10% 16V

0805

1

2

SYNC_DATE=07/06/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

24 OF 132

SHEET

22 OF 101

1

C2446

1UF

10%

6.3V

2

CERM 402

D

1

C2476

1UF

10%

6.3V

2

CERM 402

1

C2469

1UF

10%

6.3V

2

CERM 402

C

B

1

2

A

SIZE

D

345678

2 1

D

PLACE_NEAR=U1000.C60:2.54mm

PLACE_NEAR=U1000.B57:2.54mm

C

B

A

PROCESSOR MINI XDP

101

NOSTUFF

R2540

1/16W MF-LF

1

1K

5%

402

2

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2 HOOK3

SDA

SCL TCK1 TCK0

XDP

1

C2500

0.1uF

10% 16V

2

X5R 402

CRITICAL XDP_CONN

J2500

DF40C-60DS-0.4V

F-ST-SM-HF

1

2

3

4

5

6

7 8

10

9

11 12

13 14

15 16

17 18

19

20

21 22

23 24

25 26

27 28

29

30

31 32

33 34

35 36

37 38

39

40

41 42

43 44

45 46

47 48

49

50

51 52

53 54

55 56

NC

57 58

59

60

517S0774

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28 TDO TRSTn TDI TMS XDP_PRESENT#

XDP

1

C2501

0.1uF

10% 16V

2

X5R 402

CPU_CFG<16> CPU_CFG<17>

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<2> CPU_CFG<3>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<4> CPU_CFG<5>

CPU_CFG<6> CPU_CFG<7>

XDP_CPU_CLK100M_P

90

XDP_CPU_CLK100M_N

90

XDP_CPURST_L

90

XDP_DBRESET_L

XDP_CPU_TDO XDP_CPU_TRST_L XDP_CPU_TDI XDP_CPU_TMS

IN

OUT

IN

OUT

9

90

9

90

9

23 90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

10 23 25 90

10 23 90

1 2

5%

1 2

5%

1 2

5%

PLACE_NEAR=R1841.1:2.54mm

XDP

R2515

0

1/20W

MF

201

PLACE_NEAR=R1840.1:2.54mm

XDP

R2516

0

1/20W

MF

201

XDP

R2505

1K

1/20W

MF

201

PLT_RST_CPU_BUF_L

PLACE_NEAR=U1000.G3:2.54mm

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

PLACE_NEAR=J2500.52:2.54mm

XDP_CPU_TDO

10 23 90

XDP_CPU_TDI

10 23 90

XDP_CPU_TMS

10 23 90

XDP_CPU_TCK

10 23 90

XDP_CPU_TRST_L

10 23 90

PLACE_NEAR=U1000.H63:2.54mm

16 90

IN

16 90

IN

10 25

IN

XDP_BPM_L<4>

10 90

IN

XDP_BPM_L<5>

10 90

IN

XDP_BPM_L<6>

10 90

IN

XDP_BPM_L<7>

10 90

IN

CPU_CFG<12>

9

IN

CPU_CFG<13>

9

IN

CPU_CFG<14>

9

IN

CPU_CFG<15>

9

IN

CPU_PWRGD

10 19 90

IN

PLACE_NEAR=U4900.P17:2.54mm

PM_PWRBTN_L

17 23 44

OUT

CPU_CFG<0>

9

23 90

OUT

PM_PCH_SYS_PWROK

17 89

OUT

R2564 R2565 R2566 R2567

5%

R2560 R2561 R2562 R2563

XDP

R2500

1K

1 2

MF

201

XDP

R2501

1K

1 2

MF

201

5%

MF

5%

MF

5%

MF

5%

MF

1 2

5%

MF

1 2

5%

MF 5%

MF

5%

MF

0

1 2

0

1 2

0

1 2

0

1 2

0 0

0

1 2

0

1 2

1/20W

R2502

1 2

5%

1/20W

R2504

1 2

5%

XDP

201

0

MF

XDP

330

201

1/20W

MF

201

1/20W

201

1/20W

XDP_CPU_BPM XDP_CPU_BPM XDP_CPU_BPM XDP_CPU_BPM

XDP_CPU_CFG XDP_CPU_CFG

1/20W

10 90

9

90

9

90

88 93 16 23 26 28 30 41 47 61

16 23 26 28 30 41 47 61 88 93

10 23 90

48 49 50 51 53 56 60 61 71 72

PP3V3_S0

6 7

12 16 17 18 19 20 22 25

26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

XDP_CPU_PREQ_L

BI

XDP_CPU_PRDY_L

IN

XDP_BPM_L<0>

IN

XDP_BPM_L<1>

IN

XDP_BPM_L<2>

IN

XDP_BPM_L<3>

IN

CPU_CFG<10>

IN

CPU_CFG<11>

IN

XDP_OBSDATA_B<0> XDP_OBSDATA_B<1>

XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>

XDP_CPU_PWRGD

90

XDP_CPU_PWRBTN_L

XDP_CPU_CFG<0>

XDP_VR_READY

SMBUS_PCH_DATA

BI

SMBUS_PCH_CLK

IN

XDP_CPU_TCK

OUT

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

PLACE_NEAR=J2550.52:2.54mm

XDP_PCH_TDO

16 23

XDP_PCH_TDI

16 23

XDP_PCH_TMS

16 23

XDP_PCH_TCK

16 23

PCH MINI XDP

PP3V3_S5

6 7

17 19 20 22 24 25 29 39

45 55 65 70 71 72 82 85 89 98

CRITICAL XDP_CONN

J2550

DF40C-60DS-0.4V

NC

F-ST-SM-HF

1

3

5

7 8

9

11 12

13 14

15 16

17 18

19

21 22

23 24

25 26

27 28

29

31 32

33 34

35 36

37 38

39

41 42

43 44

45 46

47 48

49

51 52

53 54

55 56

57 58

59

517S0774

2

4

6

10

20

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D1

30

40

50

60

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28 TDO TRSTn TDI TMS XDP_PRESENT#

XDP

1

C2581

0.1uF

10% 16V

2

X5R 402

XDP_PCH_ISOLATE_CPU_MEM_L

PCH_GPIO0

XDP_FW_CLKREQ_L XDP_AP_CLKREQ_L

DP_AUXCH_ISOL

SATARDRVR_EN

TP_XDP_PCH_OBSFN_D<0> TP_XDP_PCH_OBSFN_D<1>

PCH_GPIO36_SATA2GP JTAG_ISP_TCK

XDP_PCH_AUD_IPHS_SWITCH_EN

ENET_LOW_PWR_PCH

TP_XDP_PCH_HOOK4 TP_XDP_PCH_HOOK5

XDPPCH_PLTRST_L XDP_DBRESET_L

XDP_PCH_TDO TP_XDP_PCH_TRST_L XDP_PCH_TDI XDP_PCH_TMS

IN

OUT

IN

OUT

19

16 84

16 41

19

8

19

25

10 23 25 90

16 23

5%

MF

5%

MF

5%

MF

19 33 87

5%

MF

1K series R on PCH Support P. 28

PLACE_NEAR=U1800.K12:2.54mm

PCH_GPIO46

19

IN

PLACE_NEAR=U1800.A14:2.54mm

USB_HUB_SOFT_RESET_L

18 24

IN

PLACE_NEAR=U1800.K20:2.54mm

SDCONN_STATE_RST_L

18

IN

PLACE_NEAR=U1800.C16:2.54mm

ENET_PWR_EN

18

IN

PLACE_NEAR=U1800.A16:2.54mm

SDCONN_STATE_CHANGE

18 32

IN

PLACE_NEAR=J2550.39:2.54mm

ALL_SYS_PWRGD

44 72 87 89

IN

PLACE_NEAR=U4900.P17:2.54mm

PM_PWRBTN_L

17 23 44

OUT

1 2

5%

MF

1 2

5%

MF

1 2

5%

MF

1 2

5%

MF

1 2

5%

MF

1 2

5%

MF

1 2

5%

MF

XDP

R2582

0

XDP

R2580

0

XDP

R2586

0

XDP

R2587

0

XDP

R2581

0

XDP

R2584

1K

XDP

R2585

0

1/20W

201

1/20W

201

1/20W

201

1/20W

201

1/20W

201

1/20W

201

1/20W

201

TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>

XDP_PCH_GPIO46 XDP_PCH_USB_HUB_SOFT_RST_L

XDP_PCH_SDCONN_STATE_RST_L XDP_PCH_ENET_PWR_EN

TP_XDP_PCH_OBSFN_B<0> TP_XDP_PCH_OBSFN_B<1>

PCH_GPIO43_OC4_L

18

IN

XDP_PCH_SDCONN_DET_L

PCH_GPIO10_OC6_L

18

IN

PCH_GPIO14_OC7_L

18

IN

XDP_PCH_S5_PWRGD

XDP_PCH_PWRBTN_L

TP_XDPPCH_HOOK2

6

TP_XDPPCH_HOOK3

6

SMBUS_PCH_DATA

16 23 26 28 30 41 47 61 88 93

BI

SMBUS_PCH_CLK

16 23 26 28 30 41 47 61 88 93

IN

XDP_PCH_TCK

16 23

OUT

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_D0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2 HOOK3

SDA

SCL TCK1 TCK0

XDP

1

C2580

0.1uF

10% 16V

2

X5R 402

8 7 5 4 2 1

PLACE_NEAR=U1800.P8:2.54mm

XDP

R2578

0

1 2

1/20W

201

XDP

R2576

1 2

R2577

1 2

R2579

1 2

PLACE_NEAR=U1800.V10:2.54mm

0

1/20W

201

XDP

PLACE_NEAR=U1800.M1:2.54mm

0

1/20W

201

PLACE_NEAR=U1800.U2:2.54mm

XDP

0

1/20W

201

ISOLATE_CPU_MEM_L

FW_CLKREQ_L

AP_CLKREQ_L

AUD_IPHS_SWITCH_EN_PCH

36

19 29

IN

16 39

IN

16 31

IN

19

IN

DESIGN NOTE:

ODT AVAILABLE ON JTAG

PLACEMENT NOTE:

PLACE TDO TERM NEAR SNB XDP CONN

R2510

1/20W

XDP

1

R2511

51

5%

MF

201

2

PLACE_NEAR=U1000.K61:2.54mm

XDP

1

R2513

PLACEMENT NOTE:

PLACE TDO TERM NEAR PCH XDP CONN

R2550

1/20W

51

201

1/20W

XDP

R2514

5%

MF

2

1

R2551

51

5%

MF

201

2

PLACE_NEAR=U1800.J3:2.54mm

SYNC_MASTER=K91_MLB

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

1/20W

XDP

51

201

XDP

1

5%

MF

2

R2512

1/20W

1

51

5%

MF

201

2

PLACE_NEAR=U1000.H59:2.54mm

XDP

PLACE_NEAR=U1000.J58:2.54mm

1

51

5%

1/20W

MF

201

2

PLACEMENT NOTE: PLACE TCK/TDI/TMS/TRST*

TERM NEAR CPU

PP1V05_SUS

PLACE_NEAR=U1800.K5:2.54mm

XDP

1/20W

51

201

XDP

1

5%

MF

2

1

R2552

51

5%

1/20W

MF

201

2

XDP

1

R2556

51

5%

1/20W

MF

201

2

PLACEMENT NOTE: PLACE TCK/TDI/TMS/TRST*

TERM NEAR PCH

PLACE_NEAR=U1800.H7:2.54mm

CPU & PCH XDP

Apple Inc.

72

101

PP1V05_S0

20 22 23 35 6 7 9 13 14 16 17 39 44 67 69

7

70

SYNC_DATE=10/17/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

25 OF 132

SHEET

23 OF 101

10 12

SIZE

D

C

B

A

D

C

B

A

18 19 24 25 29 30

HUB1_NONREM1_1

R2601

10K

1/16W MF-LF

HUB1_NONREM1_0

R2602

10K

1/16W MF-LF

18 19 24 25 29

HUB2_NONREM1_1

R2651

10K

1/16W MF-LF

HUB2_NONREM1_0

R2652

10K

1/16W MF-LF

345678

BOM GROUP

72 87

PP3V3_S3

6 7 8 31 32 47 48 49 53 54 71

1

5%

402

2

1

5%

402

2

71 72 87

PP3V3_S3

6 7 8 30 31 32 47 48 49 53 54

1

5%

402

2

1

5%

402

2

CRITICAL

C2619

HUB1_NONREM0_1

1

R2603

10K

5% 1/16W MF-LF 402

2

HUB1_NONREM0_0

1

R2604

10K

5% 1/16W MF-LF 402

2

CRITICAL

C2669

HUB2_NONREM0_1

1

R2653

10K

5% 1/16W MF-LF 402

2

HUB2_NONREM0_0

1

R2654

10K

5% 1/16W MF-LF 402

2

BYPASS=U2600.5::5MM

BYPASS=U2600.23::5MM

CRITICAL

Y2600

SM-2

24.000MHZ-16PF

18PF

CERM

1

5%

50V

2

402

42

R2630

1M

5% 1/16W MF-LF

402

CRITICAL

BYPASS=U2650.5::5MM

C2652

4.7UF

20%

6.3V X5R 603

BYPASS=U2650.15::2MM

BYPASS=U2650.23::5MM

C2657

4.7UF

20%

6.3V X5R 603

CRITICAL

Y2650

SM-2

24.000MHZ-16PF

18PF

CERM

1

5%

50V

2

402

42

R2680

1M

5% 1/16W MF-LF

402

CRITICAL

1

C2602

4.7UF

20%

6.3V 2

X5R 603

BYPASS=U2600.15::2MM

1

C2607

4.7UF

20%

6.3V 2

X5R 603

BYPASS=U2600.36::2MM

31

21

1

2

C2653

0.1UF

X7R-CERM

CRITICAL

1

C2620

18PF

5% 50V

2

CERM 402

1

10% 16V

2

402

BYPASS=U2650.10::2MM

1

C2658

0.1UF

10%

X7R-CERM

16V

402

2

BYPASS=U2650.36::2MM

31

21

CRITICAL

1

C2670

18PF

5% 50V

2

CERM 402

1

C2603

0.1UF

10% 16V

2

X7R-CERM

402

BYPASS=U2600.10::2MM

1

C2608

0.1UF

X7R-CERM

C2609

10% 16V

2

X7R-CERM

402

BYPASS=U2600.29::2MM

R2605

100

21

5% 1/16W MF-LF

402

1

R2606

10K

5% 1/16W MF-LF 402

2

BYPASS=U2650.5::2MM

1

C2661

0.1UF

10% 16V

2

X7R-CERM 402

BYPASS=U2650.23::2MM

1

C2659

0.1UF

10%

X7R-CERM

16V

402

2

BYPASS=U2650.29::2MM

R2655

100

21

5% 1/16W MF-LF

402

1

R2656

10K

5% 1/16W MF-LF 402

2

BYPASS=U2600.5::2MM

1

C2611

0.1UF

10% 16V

2

X7R-CERM 402

1

2

BYPASS=U2600.23::2MM

1

0.1UF

C2610

0.1UF

10% 16V

402

10% 16V

2

X7R-CERM

402

USB_HUB1_TEST

USB_HUB_RESET_L

24

USB_HUB1_XTAL1 USB_HUB1_XTAL2

USB_HUB1_NONREM0

USB_HUB1_NONREM1

USB_HUB1_CFG_SEL0

USB_HUB1_CFG_SEL1

1

R2607

10K

5% 1/16W MF-LF 402

2

1

C2662

0.1UF

10% 16V

2

X7R-CERM 402

0.1UF

X7R-CERM

1

10% 16V

2

402

1

C2660

2

USB_HUB2_TEST

USB_HUB_RESET_L

24

USB_HUB2_XTAL1 USB_HUB2_XTAL2

USB_HUB2_NONREM0

USB_HUB2_NONREM1

USB_HUB2_CFG_SEL0

USB_HUB2_CFG_SEL1

1

R2657

10K

5% 1/16W MF-LF 402

2

C2612

0.1UF

10% 16V X7R-CERM 402

1

2

11

TEST

26

RESET*

33

XTALIN/CLKIN

32

XTALOUT

28

SUSP_IND/LOCAL_PWR/NON_REM0

22

SDA/SMBDATA/NON_REM1

24

SCL/SMBCLK/CFG_SEL0

25

HS_IND/CFG_SEL1

11

TEST

26

RESET*

33

XTALIN/CLKIN

32

XTALOUT

28

SUSP_IND/LOCAL_PWR/NON_REM0

22

SDA/SMBDATA/NON_REM1

24

SCL/SMBCLK/CFG_SEL0

25

HS_IND/CFG_SEL1

5

VDD33

SYM VER 1

U2600

USB2513B

OMIT

THRM_PAD

VDD33

SYM VER 1

U2650

USB2513B

OMIT

THRM_PAD

PPUSB_HUB1_VDD1V8

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB1_VDD1V8PLL

3629231510

34

14

CRFILT

PLLFILT

QFN

USBDM_DN1/PRT_DIS_M1 USBDP_DN1/PRT_DIS_P1

USBDM_DN2/PRT_DIS_M2 USBDP_DN2/PRT_DIS_P2

USBDM_DN3/PRT_DIS_M3 USBDP_DN3/PRT_DIS_P3

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2* PRTPWR3/BC_EN3*

37

PPUSB_HUB2_VDD1V8

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8PLL

3629231510

34

14

CRFILT

PLLFILT

QFN

USBDM_DN1/PRT_DIS_M1 USBDP_DN1/PRT_DIS_P1

USBDM_DN2/PRT_DIS_M2 USBDP_DN2/PRT_DIS_P2

USBDM_DN3/PRT_DIS_M3 USBDP_DN3/PRT_DIS_P3

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2* PRTPWR3/BC_EN3*

37

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

1 2

3 4

6 7

8

NC

9

NC

12 16 18 20

NC

13

OCS1*

IPU IPU IPU IPU

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

IPU IPU IPU IPU

OCS2* OSC3*

RBIAS

VBUS_DET

USBDM_UP USBDP_UP

OCS1* OCS2* OSC3*

RBIAS

VBUS_DET

USBDM_UP USBDP_UP

17 19 21

NC

35

27

30 31

1 2

3 4

6 7

8

NC

9

NC

12 16 18 20

NC

13 17 19 21

NC

35

27

30 31

1

C2615

0.1UF

10% 16V

2

X7R-CERM 402

USB_T29A_N USB_T29A_P

USB_IR_N USB_IR_P

USB_EXTB_N USB_EXTB_P

USB_EXTC_N USB_EXTC_P

TP_USB_HUB1_PRTPWR1 NC_USB_HUB1_PRTPWR2 NC_USB_HUB1_PRTPWR3 NC_USB_HUB1_PRTPWR4

TP_USB_HUB1_OCS1 NC_USB_HUB1_OCS2

USB_EXTB_OC_L

NC_USB_HUB1_OCS4

USB_HUB1_RBIAS

USB_HUB1_VBUS_DET

USB_HUB1_UP_N USB_HUB1_UP_P

1

C2665

0.1UF

10% 16V

2

X7R-CERM 402

USB_BT_N USB_BT_P

USB_TPAD_N USB_TPAD_P

USB_EXTA_N USB_EXTA_P

USB_SDCARD_N USB_SDCARD_P

TP_USB_HUB2_PRTPWR1 NC_USB_HUB2_PRTPWR2 NC_USB_HUB2_PRTPWR3 NC_USB_HUB2_PRTPWR4

TP_USB_HUB2_OCS1 NC_USB_HUB2_OCS2

USB_EXTA_OC_L

NC_USB_HUB2_OCS4

USB_HUB2_RBIAS

USB_HUB2_VBUS_DET

USB_HUB2_UP_N USB_HUB2_UP_P

1

C2616

1UF

10% 16V

2

X5R 402

8

BI

8

BI

43 92

BI

43 92

BI

42 92

BI

42 92

BI

8

BI

8

BI

1

C2666

1UF

10% 16V

2

X5R 402

6

BI

1

C2617

0.1UF

10% 16V

2

X7R-CERM 402

92

T29 - no longer used, pulled up to 3V3 S0

92

IR Receiver

External B

92

External C

92

6

42

IN

8

IN

CRITICAL

1

18 92

R2600

12K

18 92

1% 1/16W MF 402

2

1

C2667

0.1UF

10% 16V

2

X7R-CERM 402

31 92

BI

Bluetooth

31 92

BI

52 92

BI

Trackpad/Keyboard

52 92

BI

42 92

BI

External A

42 92

BI

8

BI

SD Card/Express Card

8

BI

6

42

IN

8

IN

CRITICAL

1

18 92

R2650

12K

18 92

1% 1/16W MF 402

2

8 7 5 4 2 1

HUB1_1NONREM

HUB1_2NONREM

HUB1_3NONREM

HUB2_1NONREM

HUB2_2NONREM

HUB2_3NONREM

1

2

PP3V3_S3

1

R2620

10K

5% 1/16W MF-LF 402

2

1

2

PP3V3_S3

1

R2670

10K

5% 1/16W MF-LF 402

2

HUB1_ALLREM

HUB2_ALLREM

C2618

1UF

10% 16V X5R 402

C2668

1UF

10% 16V X5R 402

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

6 7

17 19 20 22 23 25 29 39

45 55 65 70 71 72 82 85 89 98

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

NON_REM1 NON_REM0 DESCRIPTION

0 0 All ports are removable 0 1 Port 1 is non removable 1 0 Port 1 and 2 are non removable 1 1 Port 1, 2, and 3 are non removable

PART#

338S0720

338S0824

338S0721

338S0923

QTY

2

DESCRIPTION

SMSC USB2514

SMSC USB2514B

SMSC USX2061

SMSC USX2513B

PP3V3_S3

R2640

NOSTUFF

1

C2641

100PF

5% 50V

2

CERM 402

20K

1/16W MF-LF

PP3V3_S5

R2642

100K

1/16W MF-LF

1

5%

402

2

P3V3S3_EN_RC

1

C2640

0.47UF

10%

6.3V

2

CERM-X5R 402

36

HUB1_NONREM1_0,HUB1_NONREM0_0

HUB1_NONREM1_0,HUB1_NONREM0_1

HUB1_NONREM1_1,HUB1_NONREM0_0

HUB1_NONREM1_1,HUB1_NONREM0_1

HUB2_NONREM1_0,HUB2_NONREM0_0

HUB2_NONREM1_0,HUB2_NONREM0_1

HUB2_NONREM1_1,HUB2_NONREM0_0

HUB2_NONREM1_1,HUB2_NONREM0_1

BOM TABLE

5%

402

2 1

BOM OPTIONS

REFERENCE DESIGNATOR(S)

U2600,U2650

21

USB_HUB_RESET

6

CRITICAL

D

Q2640

2

18 23

2N7002DW-X-G

G

S

SOT-363

1

USB_HUB_SOFT_RESET_L

IN

SYNC_MASTER=K91_ERIC

PAGE TITLE

5

G

USB HUBS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

1

R2641

10K

5% 1/16W MF-LF 402

2

USB_HUB_RESET_L

3

D

S

4

D2600

SOD-523

2 1

BAT54XV2T1

SYNC_DATE=10/08/2010

CRITICAL BOM OPTION

CRITICAL

Q2640

2N7002DW-X-G

SOT-363

USBHUB_2514

USBHUB_2514B

USBHUB_2061

USBHUB_2513B

DRAWING NUMBER

REVISION

BRANCH

PAGE

26 OF 132

SHEET

24 OF 101

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

SIZE

D

C

B

A

D

345678

2 1

Platform Reset Connections

33

5%

402

0

5%

402

1K

5%

402

LPCPLUS_RESET_L

MAKE_BASE=TRUE

SMC_LRESET_L

PCA9557D_RESET_L

XDPPCH_PLTRST_L

GMUX_RESET_L

MAKE_BASE=TRUE

GMUX_RESET_L

OUT

25 87

OUT

6

25 46 87 93

6

25 46 87 93

44

30

23

25 87

D

PLT_RESET_L

Unbuffered

IN

PCH Reset Button

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45

D

10 23 90

IN

72 79 82 83 84 87 88 89 98

XDP_DBRESET_L

XDP

R2896

0

1 2

5% 1/16W MF-LF

402

1

R2895

4.7K

5% 1/16W MF-LF 402

2

PM_SYSRST_L

OMIT

1

R2897

0

5% 1/16W MF-LF 402

2

6

17 44

BI

Ethernet WAKE# Isolation

PP3V3_ENET

CRITICAL

Q2830

SSM3K15FV

SOD-VESM-HF

PCIE_WAKE_L ENET_WAKE_L

6

17 31 84 25 36

OUT

D

3

1

GS

2

1

R2830

10K

5% 1/16W MF-LF 402

2

ENET_WAKE_L

25 36

MAKE_BASE=TRUE

6 7

25 36 70 72

IN

SILK_PART=SYS RESET

MAKE_BASE=TRUE

R2881

33

1 2

5% 1/16W MF-LF

402

R2887

0

1 2

5% 1/16W MF-LF

402

R2883

1 2

1/16W MF-LF

R2871

1 2

1/16W MF-LF

XDP

R2889

1 2

1/16W MF-LF

ENET_MEDIA_SENSE ISOLATION CIRCUIT

PLACE_NEAR=U1800.N32:5mm

ENET_MEDIA_SENSE

36

IN

C

R2855

LPC_CLK33M_SMC_R

18 93

IN

LPC_CLK33M_LPCPLUS_R

18

IN

LPC_CLK33M_GMUX_R

18 25

IN

PCH_CLK33M_PCIOUT

18

IN

LPC_CLK33M_GMUX_R

18 25

MAKE_BASE=TRUE

PLACE_NEAR=U1800.N52

PLACE_NEAR=U1800.P53

PLACE_NEAR=U1800.P46

PLACE_NEAR=U1800.P48

22

1 2

5%

1/20W

MF

201

R2857

22

1 2

5%

1/20W

MF

201

R2856

22

1 2

5%

1/20W

MF

201

R2859

22

1 2

5%

1/20W

MF

201

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

LPC_CLK33M_GMUX

PCH_CLK33M_PCIIN

44 93

OUT

6

46 93

OUT

87

OUT

16 93

OUT

16 20 22 41 56 70

18 19 24 29 30 31 32 47

PP1V5_S0

7

PP3V3_S3

6 7 8 48 49 53 54 71 72 87

R2811

100K

5%

1/20W

MF

201

ENET_MEDIA_SENSE_EN_L

R2812

0

5%

1/16W

MF-LF

402

ENET_MEDIA_SENSE_EN

System RTC Power Source & 32kHz / 25MHz Clock Generator

B

A

VDDIO_25M_A: SB power rail for XTAL circuit. VDDIO_25M_B: Ethernet power rail for XTAL circuit. VDDIO_25M_C: T29 power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

GreenClk 25MHz Power

Ethernet XTAL Power SB XTAL Power T29 XTAL Power

C2805

12PF

2 1

CERM

C2806

12PF

1 2

CERM

PP3V3_ENET

6 7

25 36 70 72

PP3V3_ENET

6 7

25 36 70 72

PP1V8_S0

6 7

14 17 20 22 70 71 87

PP3V3_T29

7

16 19 33 34 35 87

0.1UF

CERM

10V

1

20%

2

402

C2824

SYSCLK_CLK25M_X2

5%

50V

402

5%

50V

402

CRITICAL

1

Y2805

NC

SM-3.2X2.5MM

NC

4 2

25.000MHZ-12PF-20PPM

3

NOTE: 30 PPM crystal required

8 7 5 4 2 1

C2822

0.1UF

10V

CERM

R2805

0

1 2

5% 1/16W MF-LF

402

PP3V42_G3H

6 7

42 44 45 46 47 52 62 63

72

Coin-Cell: VBAT (300-ohm & 10uF RC) No Coin-Cell: 3.42V G3Hot (no RC)

98

PP3V3_S5

6 7

17 19 20 22 23 24 29 39

45 55 65 70 71 72 82 85 89

Coin-Cell & G3Hot: 3.42V G3Hot Coin-Cell & No G3Hot: 3.3V S5 No Coin-Cell: 3.3V S5

1

C2820

20%

2

402

NO STUFF

1

2

1

0.1UF

20%

10V

2

CERM

402

SYSCLK_CLK25M_X2_R

R2806

1M

5% 1/16W MF-LF 402

SYSCLK_CLK25M_X1

No bypass necessary

1

C2802

1UF

10%

10V

2

X5R 402-1

11

VDDIO_25M_A

6

VDDIO_25M_B

14

VDDIO_25M_C

3

X2

4

X1

2513

+V3.3A

VDD_25M

U2800

SLG3NB148V

TQFN

CRITICAL

VDD_RTC_OUT

GND

71016

32KHZ_A

25MHZ_A 25MHZ_B 25MHZ_C

THRM

PAD

17

VBAT and +V3.3A are internally ORed to

+3.42V

create VDD_RTC_OUT.

+V3.3A should be first available ~3.3V power to reduce VBAT draw.

12

SYSCLK_CLK32K_RTC

9

SYSCLK_CLK25M_SB

8

SYSCLK_CLK25M_ENET_R

15

SYSCLK_CLK25M_T29 PPVRTC_G3H

1

For SB RTC Power

1

C2810

1UF

10%

6.3V

2

CERM 402

1 2

402

CRITICAL

SSM6N37FEAPE

Q2810

1

2

SSM6N37FEAPE

Q2810

1

SOT563

2

7

16 17 20

R2810

12K

MF-LF 1/16W

SOT563

5

D

SG

16

OUT

33

OUT

5%

D

SG

6

1

ENET_MEDIA_SENSE_RDIV

1

R2819

3

10K

5%

1/20W

MF

201

2

4

R2800

0

1 2

SYSCLK_CLK25M_ENET

5%

1/20W

MF

201

16

OUT

Buffered

12 16 17 18 19 20 22 23

89 98 45 47 48 49 50 51 53 56 60

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 61 71 72 79 82 83 84 87 88

Note: Based on K91/K92 layout, ENET,AP and BKLT are moved to Buffered reset.

CRITICAL

5

MC74VHC1G08

1

2

0.1UF

CERM

20% 10V

CERM

402

20% 10V

402

1

2

Buffered CPU reset

1

2

C2880

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

C2890

NOTE: This page is different for K92. ENET_RESET_L hooked up differently on both the projects.

36

OUT

U2880

3

2

NC

SC70-HF

35

4

25 32

CRITICAL

5

U2890

74LVC1G07

SC70

4

31

NC

PLT_RST_BUF_L

MAKE_BASE=TRUE

1

R2880

100K

5% 1/16W MF-LF 402

2

25

PLT_RST_CPU_BUF_L

10 23

MAKE_BASE=TRUE

1

R2890

100K

5% 1/16W MF-LF 402

2

R2888

1 2

1/16W MF-LF

402

R2893

1 2

1/16W MF-LF

402

VTT voltage divider on CPU page

SYNC_MASTER=K92_MLB

PAGE TITLE

Chipset Support

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

36

PLT_RESET_L

Series R is R4283

PLT_RST_BUF_L

Series R on Pg38, R3803

0

5%

0

5%

AP_RESET_L

BKLT_PLT_RST_L

PLT_RST_CPU_BUF_L

Apple Inc.

OUT

SYNC_DATE=07/06/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

18 25 29 39

OUT

25 32 35

OUT

25 32 35

OUT

31

OUT

88

OUT

10 23 25

28 OF 132

25 OF 101

SIZE

C

B

A

D

345678

2 1

Page Notes

Power aliases required by this page:

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

BOM options provided by this page:

D

(NONE)

C

B

61 71 72 79 82 36 39 40 41 45

6 7

12 16 17 18

19 20 22 23 25 28 32 35 47 48 49 50 51 53 56 60 83 84 87 88 89 98

A

PP1V5_S3

6 7

28 29 66 71

PLACE_NEAR=J2900.75:2.54mm

1

C2900

10UF

20%

6.3V

2

X5R 603

1

C2901

10UF

20%

6.3V

2

X5R 603

PLACE_NEAR=J2900.75:2.54mm

OMIT_TABLE

CKE0

VDD NC

BA2

VDD A12/BC* A9

VDD A8 A5

VDD A3 A1

VDD CK0 CK0*

VDD A10/AP BA0

VDD WE* CAS*

VDD A13 S1*

VDD TEST

VSS DQ32 DQ33

VSS DQS4* DQS4

VSS DQ34 DQ35

VSS DQ40 DQ41

VSS DM5

VSS DQ42 DQ43

VSS DQ48 DQ49

VSS DQS6* DQS6

VSS DQ50 DQ51

VSS DQ56 DQ57

VSS DM7

VSS DQ58 DQ59

VSS SA0 VDDSPD SA1

VTT

KEY

CKE1

VDD

J2900

F-RT-THB

A15 A14

VDD

A11

A7

VDD

A6 A4

VDD

(SYMBOL 2 OF 2)

A2 A0

VDD

CK1

DDR3-SODIMM-DUAL-K6

CK1*

VDD

BA1

RAS*

VDD

S0*

ODT0

VDD

ODT1

NC

VDD

VREFCA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5*

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7*

DQS7

VSS DQ62 DQ63

VSS

EVENT*

SDA SCL

VTT

516-0229

PP3V3_S0

1

C2940

2.2UF

20%

6.3V

2

CERM 402-LF

11 91

27

11 27 91

27

1

R2940

10K

2

6

5% 1/16W MF-LF 402

IN

BI

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_A_A<12> MEM_A_A<9>

MEM_A_A<8> MEM_A_A<5>

MEM_A_A<3> MEM_A_A<1>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_A<10> MEM_A_BA<0>

MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<13> MEM_A_CS_L<1>

=MEM_A_DQ<32> =MEM_A_DQ<33>

=MEM_A_DQS_N<4> =MEM_A_DQS_P<4>

=MEM_A_DQ<34> =MEM_A_DQ<35>

=MEM_A_DQ<40> =MEM_A_DQ<41>

=MEM_A_DQ<42> =MEM_A_DQ<43>

=MEM_A_DQ<48> =MEM_A_DQ<49>

MEM_A_DQS_N<6> MEM_A_DQS_P<6>

=MEM_A_DQ<50> =MEM_A_DQ<51>

=MEM_A_DQ<56> =MEM_A_DQ<57>

=MEM_A_DQ<58> =MEM_A_DQ<59>

MEM_A_SA<0>

6

MEM_A_SA<1>

6

1

R2941

10K

5% 1/16W MF-LF 402

2

73 74 75 76 77

NC

79 81 82 83 85 87 88

91 93 94

99 101 103 105 106 107 109 111 112 113 115 117 118 119 121 123 124 125

NC

127 128 129 131 133 134 135 137 139 141 143 145 147 149 151 153 155 156 157 159 161 162 163 165 167 168 169 171 173 175 177 179 181 183 185 187 189 190 191 193 195 196 197 199 201 202 203 204

SPD ADDR=0xA0(WR)/0xA1(RD)

8 7 5 4 2 1

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

78 80

84 86

9089 92

9695 9897 100 102 104

108 110

114 116

120 122

126

130 132

136 138 140 142 144 146 148 150 152 154

158 160

164 166

170 172 174 176 178 180 182 184 186 188

192 194

198 200

NC

1

C2910

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm

MEM_A_CKE<1>

MEM_A_A<15> MEM_A_A<14>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<6> MEM_A_A<4>

MEM_A_A<2> MEM_A_A<0>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_BA<1> MEM_A_RAS_L

MEM_A_CS_L<0> MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_DQ<32> =MEM_A_DQ<37>

=MEM_A_DQ<38> =MEM_A_DQ<39>

=MEM_A_DQ<44> =MEM_A_DQ<45>

=MEM_A_DQS_N<5> =MEM_A_DQS_P<5>

=MEM_A_DQ<46> =MEM_A_DQ<47>

=MEM_A_DQ<52> =MEM_A_DQ<53>

=MEM_A_DQ<54> =MEM_A_DQ<55>

=MEM_A_DQ<60> =MEM_A_DQ<61>

=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>

=MEM_A_DQ<62> =MEM_A_DQ<63>

MEM_EVENT_L SMBUS_PCH_DATA SMBUS_PCH_CLK

1

C2911

0.1UF

20% 10V

2

CERM 402

PP0V75_S3_MEM_VREFDQ_A

9

30

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 27 91

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

28 44

OUT

16 23 28 30 41 47 61 88 93

BI

16 23 28 30 41 47 61 88 93

IN

1

C2912

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm

1

C2950

1UF

10% 10V

2

X5R 402

1

C2935

2

2.2UF

20%

6.3V CERM 402-LF

1

C2913

0.1UF

20% 10V

2

CERM 402

1

2

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

1

C2951

1UF

10% 10V

2

X5R 402

1

C2914

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm

1

C2930

2.2UF

20%

6.3V CERM 402-LF

C2931

0.1UF

20% 10V

2

CERM 402

=MEM_A_DQ<0> =MEM_A_DQ<1>

=MEM_A_DQ<2> =MEM_A_DQ<3>

=MEM_A_DQ<8> =MEM_A_DQ<9>

=MEM_A_DQS_N<1> =MEM_A_DQS_P<1>

=MEM_A_DQ<10> =MEM_A_DQ<11>

=MEM_A_DQ<16> =MEM_A_DQ<17>

=MEM_A_DQS_N<2> =MEM_A_DQS_P<2>

=MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<24> =MEM_A_DQ<25>

=MEM_A_DQ<26> =MEM_A_DQ<27>

PP0V75_S3_MEM_VREFCA_A

1

C2936

0.1UF

20% 10V

2

CERM 402

1

C2952

1UF

10% 10V

2

X5R 402

1

C2915

0.1UF

20% 10V

2

CERM 402

3 5 7 9

11

15 17

21 23

27 29

33 35

39 41

45 47 49 51 53 55 57 59 61 63

67 69

PP0V75_S0_DDRVTT

1

C2953

1UF

10% 10V

2

X5R 402

1

C2916

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm

1

C2917

0.1UF

20% 10V

2

CERM 402

OMIT_TABLE

VREFDQ

VSS DQ0 DQ1

VSS DM0

VSS DQ2 DQ3

VSS DQ8 DQ9

VSS DQS1* DQS1

VSS DQ10 DQ11

VSS DQ16 DQ17

VSS DQS2* DQS2

VSS DQ18 DQ19

VSS DQ24 DQ25

VSS DM3

VSS DQ26 DQ27

VSS

CRITICAL

J2900

F-RT-THB

VSS DQ4 DQ5

VSS

DQS0*

DQS0

VSS

DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

(SYMBOL 1 OF 2)

RESET*

VSS DQ14

DDR3-SODIMM-DUAL-K6

DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3*

DQS3

VSS DQ30 DQ31

VSS

KEY

See CSA05 BOM table

30

6 7

28 29 66

1

C2918

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm

21 4 6 8 10 12 1413 16 18 2019 22 24 2625 28 30 3231 34 36 3837 40 42 4443 46 48 50 52 54 56 58 60 62 64 6665 68 70 7271

1

C2919

0.1UF

20% 10V

2

CERM 402

=MEM_A_DQ<4> =MEM_A_DQ<5>

=MEM_A_DQS_N<0> =MEM_A_DQS_P<0>

=MEM_A_DQ<6> =MEM_A_DQ<7>

=MEM_A_DQ<12> =MEM_A_DQ<13>

MEM_RESET_L

=MEM_A_DQ<14> =MEM_A_DQ<15>

=MEM_A_DQ<20> =MEM_A_DQ<21>

=MEM_A_DQ<22> =MEM_A_DQ<23>

=MEM_A_DQ<28> =MEM_A_DQ<29>

=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>

=MEM_A_DQ<30> =MEM_A_DQ<31>

36

1

C2920

0.1UF

20% 10V

2

CERM 402

1

2

PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm

27

BI

27

BIBI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

28 29

IN

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

C2921

0.1UF

20% 10V CERM 402

1

C2922

0.1UF

20% 10V

2

CERM 402

1

C2923

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm

"Factory" (top) slot

SYNC_MASTER=K92_SUMA SYNC_DATE=06/23/2010

PAGE TITLE

DDR3 SO-DIMM Connector A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

29 OF 132

SHEET

26 OF 101

SIZE

D

C

B

A

D

345678

2 1

CPU CHANNEL A DQS 0 -> DIMM A DQS 0

MEM_A_DQS_N<0>

6

11 91

MEM_A_DQS_P<0>

6

11 91

MEM_A_DQ<7>

6

11 91

MEM_A_DQ<6>

6

11 91

MEM_A_DQ<5>

6

11 91

MEM_A_DQ<4>

6

11 91

MEM_A_DQ<3>

6

11 91

MEM_A_DQ<2>

6

11 91

MEM_A_DQ<1>

6

11 91

MEM_A_DQ<0>

6

D

C

B

A

11 91

CPU CHANNEL A DQS 1 -> DIMM A DQS 1

MEM_A_DQS_N<1>

6

11 91

MEM_A_DQS_P<1>

6

11 91

MEM_A_DQ<15>

6

11 91

MEM_A_DQ<14>

6

11 91

MEM_A_DQ<13>

6

11 91

MEM_A_DQ<12>

6

11 91

MEM_A_DQ<11>

6

11 91

MEM_A_DQ<10>

6

11 91

MEM_A_DQ<9>

6

11 91

MEM_A_DQ<8>

6

11 91

CPU CHANNEL A DQS 2 -> DIMM A DQS 2

MEM_A_DQS_N<2>

6

11 91

MEM_A_DQS_P<2>

6

11 91

MEM_A_DQ<23>

6

11 91

MEM_A_DQ<22>

6

11 91

MEM_A_DQ<21>

6

11 91

MEM_A_DQ<20>

6

11 91

MEM_A_DQ<19>

6

11 91

MEM_A_DQ<18>

6

11 91

MEM_A_DQ<17>

6

11 91

MEM_A_DQ<16>

6

11 91

CPU CHANNEL A DQS 3 -> DIMM A DQS 3

MEM_A_DQS_N<3>

6

11 91

MEM_A_DQS_P<3>

6

11 91

MEM_A_DQ<31>

6

11 91

MEM_A_DQ<30>

6

11 91

MEM_A_DQ<29>

6

11 91

MEM_A_DQ<28>

6

11 91

MEM_A_DQ<27>

6

11 91

MEM_A_DQ<26>

6

11 91

MEM_A_DQ<25>

6

11 91

MEM_A_DQ<24>

6

11 91

CPU CHANNEL A DQS 4 -> DIMM A DQS 4

MEM_A_DQS_N<4>

6

11 91

MEM_A_DQS_P<4>

6

11 91

MEM_A_DQ<39>

6

11 91

MEM_A_DQ<38>

6

11 91

MEM_A_DQ<37>

6

11 91

MEM_A_DQ<36>

6

11 91

MEM_A_DQ<35>

6

11 91

MEM_A_DQ<34>

6

11 91 26

MEM_A_DQ<33>

6

11 91

MEM_A_DQ<32>

6

11 26 27 91

CPU CHANNEL A DQS 5 -> DIMM A DQS 5

MEM_A_DQS_N<5>

6

11 91

MEM_A_DQS_P<5>

6

11 91

MEM_A_DQ<47>

6

11 91

MEM_A_DQ<46>

6

11 91

MEM_A_DQ<45>

6

11 91

MEM_A_DQ<44>

6

11 91

MEM_A_DQ<43>

6

11 91

MEM_A_DQ<42>

6

11 91

MEM_A_DQ<41>

6

11 91

MEM_A_DQ<40>

6

11 91

CPU CHANNEL A DQS 6 -> DIMM A DQS 6

MEM_A_DQS_N<6>

6

11 26 27 91

MEM_A_DQS_P<6> MEM_A_DQS_P<6>

6

11 26 27 91

MEM_A_DQ<55>

6

11 91

MEM_A_DQ<54>

6

11 91

MEM_A_DQ<53>

6

11 91

MEM_A_DQ<52>

6

11 91

MEM_A_DQ<51>

6

11 91

MEM_A_DQ<50>

6

11 91

MEM_A_DQ<49>

6

11 91

MEM_A_DQ<48>

6

11 91

CPU CHANNEL A DQS 7 -> DIMM A DQS 7

MEM_A_DQS_N<7>

6

11 91

MEM_A_DQS_P<7>

6

11 91

MEM_A_DQ<63>

6

11 91

MEM_A_DQ<62>

6

11 91

MEM_A_DQ<61>

6

11 91

MEM_A_DQ<60>

6

11 91

MEM_A_DQ<59>

6

11 91

MEM_A_DQ<58>

6

11 91 26

MEM_A_DQ<57>

6

11 91

MEM_A_DQ<56>

6

11 91

MAKE_BASE=TRUE

=MEM_A_DQS_N<0> =MEM_A_DQS_P<0>

=MEM_A_DQ<3> =MEM_A_DQ<6> =MEM_A_DQ<5> =MEM_A_DQ<4> =MEM_A_DQ<7> =MEM_A_DQ<0> =MEM_A_DQ<1> =MEM_A_DQ<2>

=MEM_A_DQS_N<1> =MEM_A_DQS_P<1>

=MEM_A_DQ<15> =MEM_A_DQ<14> =MEM_A_DQ<12> =MEM_A_DQ<13> =MEM_A_DQ<10> =MEM_A_DQ<11> =MEM_A_DQ<9> =MEM_A_DQ<8>

=MEM_A_DQS_N<2> =MEM_A_DQS_P<2>

=MEM_A_DQ<23> =MEM_A_DQ<22> =MEM_A_DQ<17> =MEM_A_DQ<20> =MEM_A_DQ<19> =MEM_A_DQ<18> =MEM_A_DQ<16> =MEM_A_DQ<21>

=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>

=MEM_A_DQ<31> =MEM_A_DQ<30> =MEM_A_DQ<29> =MEM_A_DQ<28> =MEM_A_DQ<27> =MEM_A_DQ<26> =MEM_A_DQ<25> =MEM_A_DQ<24>

=MEM_A_DQS_N<4> =MEM_A_DQS_P<4>

=MEM_A_DQ<38> =MEM_A_DQ<37> =MEM_A_DQ<39> =MEM_A_DQ<33> =MEM_A_DQ<35> =MEM_A_DQ<34> =MEM_A_DQ<32> MEM_A_DQ<32>

=MEM_A_DQS_N<5> =MEM_A_DQS_P<5>

=MEM_A_DQ<47> =MEM_A_DQ<41> =MEM_A_DQ<43> =MEM_A_DQ<44> =MEM_A_DQ<40> =MEM_A_DQ<46> =MEM_A_DQ<42> =MEM_A_DQ<45>

MEM_A_DQS_N<6>

=MEM_A_DQ<49> =MEM_A_DQ<54> =MEM_A_DQ<55> =MEM_A_DQ<52> =MEM_A_DQ<51> =MEM_A_DQ<50> =MEM_A_DQ<53> =MEM_A_DQ<48>

=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>

=MEM_A_DQ<59> =MEM_A_DQ<58> =MEM_A_DQ<56> =MEM_A_DQ<61> =MEM_A_DQ<63> =MEM_A_DQ<62> =MEM_A_DQ<57> =MEM_A_DQ<60>

26

6

11 26 27 91

26

6

11 26 27 91

6

11 26 27 91

26

8 7 5 4 2 1

CPU CHANNEL B DQS 0 -> DIMM B DQS 0

MEM_B_DQS_N<0>

6

11 91

MEM_B_DQS_P<0>

6

11 91

MEM_B_DQ<7>

6

11 91

MEM_B_DQ<6>

6

11 91

MEM_B_DQ<5>

6

11 91

MEM_B_DQ<4>

6

11 91

MEM_B_DQ<3>

6

11 91

MEM_B_DQ<2>

6

11 91

MEM_B_DQ<1>

6

11 91

MEM_B_DQ<0>

6

11 91

CPU CHANNEL B DQS 1 -> DIMM B DQS 1

MEM_B_DQS_N<1>

6

11 91

MEM_B_DQS_P<1>

6

11 91

MEM_B_DQ<15>

6

11 91

MEM_B_DQ<14>

6

11 91

MEM_B_DQ<13>

6

11 91

MEM_B_DQ<12>

6

11 91

MEM_B_DQ<11>

6

11 91

MEM_B_DQ<10>

6

11 91

MEM_B_DQ<9>

6

11 91

MEM_B_DQ<8>

6

11 91

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

MEM_B_DQS_N<2>

6

11 91

MEM_B_DQS_P<2>

6

11 91

MEM_B_DQ<23>

6

11 91

MEM_B_DQ<22>

6

11 91

MEM_B_DQ<21>

6

11 91

MEM_B_DQ<20>

6

11 91

MEM_B_DQ<19>

6

11 91

MEM_B_DQ<18>

6

11 91

MEM_B_DQ<17>

6

11 91

MEM_B_DQ<16>

6

11 91

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

MEM_B_DQS_N<3>

6

11 91

MEM_B_DQS_P<3>

6

11 91

MEM_B_DQ<31>

6

11 91

MEM_B_DQ<30>

6

11 91

MEM_B_DQ<29>

6

11 91

MEM_B_DQ<28>

6

11 91

MEM_B_DQ<27>

6

11 91

MEM_B_DQ<26>

6

11 91

MEM_B_DQ<25>

6

11 91

MEM_B_DQ<24>

6

11 91

CPU CHANNEL B DQS 4 -> DIMM B DQS 4

MEM_B_DQS_N<4>

6

11 91

MEM_B_DQS_P<4>

6

11 91

MEM_B_DQ<39>

6

11 91

MEM_B_DQ<38>

6

11 91

MEM_B_DQ<37>

6

11 91

MEM_B_DQ<36>

6

11 91

MEM_B_DQ<35>

6

11 91

MEM_B_DQ<34>

6

11 91

MEM_B_DQ<33>

6

11 91

MEM_B_DQ<32>

6

11 27

28 91

CPU CHANNEL B DQS 5 -> DIMM B DQS 5

MEM_B_DQS_N<5>

6

11 91

MEM_B_DQS_P<5>

6

11 91

MEM_B_DQ<47>

6

11 91

MEM_B_DQ<46>

6

11 91

MEM_B_DQ<45>

6

11 91

MEM_B_DQ<44>

6

11 91

MEM_B_DQ<43>

6

11 91

MEM_B_DQ<42>

6

11 91

MEM_B_DQ<41>

6

11 91

MEM_B_DQ<40>

6

11 91

CPU CHANNEL B DQS 6 -> DIMM B DQS 6

MEM_B_DQS_N<6>

6

11 27

28 91

MEM_B_DQS_P<6>

6

11 27

28 91

MEM_B_DQ<55>

6

11 91

MEM_B_DQ<54>

6

11 91

MEM_B_DQ<53>

6

11 91

MEM_B_DQ<52>

6

11 91

MEM_B_DQ<51>

6

11 91

MEM_B_DQ<50>

6

11 91

MEM_B_DQ<49>

6

11 91

MEM_B_DQ<48>

6

11 91

CPU CHANNEL B DQS 7 -> DIMM B DQS 7

MEM_B_DQS_N<7>

6

11 91

MEM_B_DQS_P<7>

6

11 91

MEM_B_DQ<63>

6

11 91

MEM_B_DQ<62>

6

11 91

MEM_B_DQ<61>

6

11 91

MEM_B_DQ<60>

6

11 91

MEM_B_DQ<59>

6

11 91

MEM_B_DQ<58>

6

11 91

MEM_B_DQ<57>

6

11 91

MEM_B_DQ<56>

6

11 91

MAKE_BASE=TRUE

=MEM_B_DQS_N<0> =MEM_B_DQS_P<0>

=MEM_B_DQ<6> =MEM_B_DQ<3> =MEM_B_DQ<5> =MEM_B_DQ<4> =MEM_B_DQ<1> =MEM_B_DQ<7> =MEM_B_DQ<2> =MEM_B_DQ<0>

=MEM_B_DQS_N<1> =MEM_B_DQS_P<1>

=MEM_B_DQ<15> =MEM_B_DQ<14> =MEM_B_DQ<13> =MEM_B_DQ<12> =MEM_B_DQ<11> =MEM_B_DQ<10> =MEM_B_DQ<9> =MEM_B_DQ<8>

=MEM_B_DQS_N<2> =MEM_B_DQS_P<2>

=MEM_B_DQ<23> =MEM_B_DQ<22> =MEM_B_DQ<21> =MEM_B_DQ<20> =MEM_B_DQ<19> =MEM_B_DQ<18> =MEM_B_DQ<17> =MEM_B_DQ<16>

=MEM_B_DQS_N<3> =MEM_B_DQS_P<3>

=MEM_B_DQ<31> =MEM_B_DQ<30> =MEM_B_DQ<29> =MEM_B_DQ<28> =MEM_B_DQ<27> =MEM_B_DQ<26> =MEM_B_DQ<25> =MEM_B_DQ<24>

=MEM_B_DQS_N<4> =MEM_B_DQS_P<4>

=MEM_B_DQ<39> =MEM_B_DQ<38> =MEM_B_DQ<37> =MEM_B_DQ<36> =MEM_B_DQ<35> =MEM_B_DQ<34> =MEM_B_DQ<33> MEM_B_DQ<32>

=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>

=MEM_B_DQ<47> =MEM_B_DQ<46> =MEM_B_DQ<45> =MEM_B_DQ<44> =MEM_B_DQ<43> =MEM_B_DQ<42> =MEM_B_DQ<41> =MEM_B_DQ<40>

MEM_B_DQS_N<6> MEM_B_DQS_P<6>

=MEM_B_DQ<55> =MEM_B_DQ<54> =MEM_B_DQ<53> =MEM_B_DQ<52> =MEM_B_DQ<51> =MEM_B_DQ<50> =MEM_B_DQ<49> =MEM_B_DQ<48>

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

=MEM_B_DQ<63> =MEM_B_DQ<62> =MEM_B_DQ<61> =MEM_B_DQ<60> =MEM_B_DQ<59> =MEM_B_DQ<58> =MEM_B_DQ<57> =MEM_B_DQ<56>

28

6

11 27 28 91

28

6

11 27 28 91

6

11 27 28 91

28

D

C

B

SIZE

A

D

SYNC_MASTER=K92_SUMA SYNC_DATE=05/10/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DDR3 Byte/Bit Swaps

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

30 OF 132

SHEET

27 OF 101

36

345678

2 1

Power aliases required by this page:

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

BOM options provided by this page:

D

(NONE)

C

B

A

Page Notes

26 29 66 71

PP1V5_S3

6 7

PLACE_NEAR=J3100.75:2.54mm

OMIT_TABLE

73 74

CKE0

75 76

VDD

77

NC

79

BA2

81 82

85 87 88 89

93 94

99 101 103 105 106 107 109 111 112 113 115 117 118 119 121 123 124 125 127 128 129 131 133 134 135 137 139 141 143 145 147 149 151 153 155 156 157 159 161 162 163 165 167 168 169 171 173 175 177 179 181 183 185 187 189 190 191 193 195 196 197 199 201 202 203 204

205 206 207 208 209 210 211 212

J3100

VDD A12/BC* A9

VDD A8 A5

VDD A3 A1

VDD CK0 CK0*

VDD A10/AP BA0

VDD WE* CAS*

VDD A13 S1*

VDD TEST

VSS DQ32 DQ33

VSS DQS4* DQS4

VSS DQ34 DQ35

VSS DQ40 DQ41

VSS DM5

VSS DQ42 DQ43

VSS DQ48 DQ49

VSS DQS6* DQS6

VSS DQ50 DQ51

VSS DQ56 DQ57

VSS DM7

VSS DQ58 DQ59

VSS SA0 VDDSPD SA1

VTT

MTG PIN

MTG PIN MTG PIN

MTG PIN

SPD ADDR=0xA4(WR)/0xA5(RD)

12 16 17 18 19

82 83 84 87 88 89 40 41 45 47 48 49

PP3V3_S0

6 7 20 22 23 25 26 32 35 36 39 50 51 53 56 60 61 71 72 79 98

1

C3140

2

2.2UF

20%

6.3V CERM 402-LF

1

R3140

10K

5% 1/16W MF-LF 402

2

MEM_B_CKE<0>

6

11 91

IN

MEM_B_BA<2>

6

11 91

IN

MEM_B_A<12>

6

11 91

IN

MEM_B_A<9>

6

11 91

IN

MEM_B_A<8>

6

11 91

IN

MEM_B_A<5>

6

11 91

IN

MEM_B_A<3>

6

11 91

IN

MEM_B_A<1>

6

11 91

IN

MEM_B_CLK_P<0>

6

11 91

IN

MEM_B_CLK_N<0>

6

11 91

IN

MEM_B_A<10>

6

11 91

IN

MEM_B_BA<0>

6

11 91

IN

MEM_B_WE_L

6

11 91

IN

MEM_B_CAS_L

6

11 91

IN

MEM_B_A<13>

6

11 91

IN

MEM_B_CS_L<1>

6

11 91

IN

MEM_B_DQ<32>

6

11 27 91

BI

=MEM_B_DQ<33>

27

BI

=MEM_B_DQS_N<4>

27

BI

=MEM_B_DQS_P<4>

27

BI

=MEM_B_DQ<34>

27

BI

=MEM_B_DQ<35>

27

BI

=MEM_B_DQ<40>

27

BI

=MEM_B_DQ<41>

27

BI

=MEM_B_DQ<42>

27

BI

=MEM_B_DQ<43>

27

BI

=MEM_B_DQ<48>

27

BI

=MEM_B_DQ<49>

27

BI

MEM_B_DQS_N<6>

6

11 27 91

BI

MEM_B_DQS_P<6>

6

11 27 91

BI

=MEM_B_DQ<50>

27

BI

=MEM_B_DQ<51>

27

BI

=MEM_B_DQ<56>

27

BI

=MEM_B_DQ<57>

27

BI

=MEM_B_DQ<58>

27

BI

=MEM_B_DQ<59>

27

BI

MEM_B_SA<0>

6

MEM_B_SA<1>

6

1

R3141

10K

5% 1/16W MF-LF 402

2

8 7 5 4 2 1

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

1

C3100

10UF

20%

6.3V

2

X5R 603

KEY

F-RT-BGA6

DDR3-SODIMM

MTG PINS

516S0806

CKE1

VDD

(2 OF 2)

VDD

CK1*

VDD

RAS*

VDD

ODT0

VDD

ODT1

VDD

VREFCA

VSS DQ36 DQ37

VSS

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5*

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7*

DQS7

VSS DQ62 DQ63

VSS

EVENT*

VTT

MTG PIN

A15 A14

A11

VDD

CK1

BA1

S0*

DM4

DM6

SDA SCL

1

2

A7

A6 A4

A2 A0

NC

C3101

10UF

20%

6.3V X5R 603

78 80

8483 86

90 9291

9695 9897 100 102 104

108 110

114 116

120 122

126

130 132

136 138 140 142 144 146 148 150 152 154

158 160

164 166

170 172 174 176 178 180 182 184 186 188

192 194

198 200

PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm

MEM_B_CKE<1>

MEM_B_A<15> MEM_B_A<14>

MEM_B_A<11> MEM_B_A<7>

MEM_B_A<6> MEM_B_A<4>

MEM_B_A<2> MEM_B_A<0>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_BA<1> MEM_B_RAS_L

MEM_B_CS_L<0> MEM_B_ODT<0>

MEM_B_ODT<1>

NC

=MEM_B_DQ<36> =MEM_B_DQ<37>

=MEM_B_DQ<38> =MEM_B_DQ<39>

=MEM_B_DQ<44> =MEM_B_DQ<45>

=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>

=MEM_B_DQ<46> =MEM_B_DQ<47>

=MEM_B_DQ<52> =MEM_B_DQ<53>

=MEM_B_DQ<54> =MEM_B_DQ<55>

=MEM_B_DQ<60> =MEM_B_DQ<61>

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

=MEM_B_DQ<62> =MEM_B_DQ<63>

MEM_EVENT_L SMBUS_PCH_DATA SMBUS_PCH_CLK

1

C3110

0.1UF

20% 10V

2

CERM 402

1

C3111

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm

PP0V75_S3_MEM_VREFDQ_B

9

30

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

6

11 91

IN

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

26 44

OUT

16 23 26 30 41 47 61 88 93

BI

16 23 26 30 41 47 61 88 93

IN

1

C3150

1UF

10% 10V

2

X5R 402

1

C3151

1UF

10% 10V

2

X5R 402

1

C3112

0.1UF

20% 10V

2

CERM 402

1

2

1

C3152

1UF

10% 10V

2

X5R 402

1

2

27

C3135

2.2UF

20%

6.3V CERM 402-LF

C3113

0.1UF

20% 10V CERM 402

1

2

BI

1

C3114

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm

1

C3130

2.2UF

20%

6.3V CERM 402-LF

C3131

0.1UF

20% 10V

2

CERM 402

=MEM_B_DQ<0> =MEM_B_DQ<1>

=MEM_B_DQ<2> =MEM_B_DQ<3>

=MEM_B_DQ<8> =MEM_B_DQ<9>

=MEM_B_DQS_N<1> =MEM_B_DQS_P<1>

=MEM_B_DQ<10> =MEM_B_DQ<11>

=MEM_B_DQ<16> =MEM_B_DQ<17>

=MEM_B_DQS_N<2> =MEM_B_DQS_P<2>

=MEM_B_DQ<18> =MEM_B_DQ<19>

=MEM_B_DQ<24> =MEM_B_DQ<25>

=MEM_B_DQ<26> =MEM_B_DQ<27>

PP0V75_S3_MEM_VREFCA_B

1

C3136

0.1UF

20% 10V

2

CERM 402

PP0V75_S0_DDRVTT

1

C3153

1UF

10% 10V

2

X5R 402

1

C3115

0.1UF

20% 10V

2

CERM 402

1

C3116

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm

OMIT_TABLE

1 2

VREFDQ

3

VSS

5

DQ0 DQ1

VSS

DM0

VSS DQ2 DQ3

VSS DQ8 DQ9

VSS DQS1* DQS1

VSS DQ10 DQ11

VSS DQ16 DQ17

VSS DQS2* DQS2

VSS DQ18 DQ19

VSS DQ24 DQ25

VSS DM3

VSS DQ26 DQ27

VSS

CRITICAL

J3100

F-RT-BGA6

516S0806

7

9 11 13 14 15 17 19 20 21 23 25 26 27 29 31 32 33 35 37 38 39 41 43 44 45 47 49 51 53 55 57 59 61 63 65 66 67 69 71 72

6 7

26 29 66

1

C3117

0.1UF

20% 10V

2

CERM 402

(1 OF 2)

DDR3-SODIMM

RESET*

KEY

30

DQS0*

DQS0

VSS

VSS DQ12 DQ13

VSS

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3*

DQS3

VSS DQ30 DQ31

VSS

1

C3118

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm

VSS

4

DQ4

6

DQ5

8

VSS

10 12

16

DQ6

18

DQ7

22 24

28

DM1

30

34 36

40 42

46

DM2

48 50 52 54 56 58 60 62 64

68 70

36

1

C3119

0.1UF

20% 10V

2

CERM 402

=MEM_B_DQ<4> =MEM_B_DQ<5>

=MEM_B_DQS_N<0> =MEM_B_DQS_P<0>

=MEM_B_DQ<6> =MEM_B_DQ<7>

=MEM_B_DQ<12> =MEM_B_DQ<13>

MEM_RESET_L

=MEM_B_DQ<14> =MEM_B_DQ<15>

=MEM_B_DQ<20> =MEM_B_DQ<21>

=MEM_B_DQ<22> =MEM_B_DQ<23>

=MEM_B_DQ<28> =MEM_B_DQ<29>

=MEM_B_DQS_N<3> =MEM_B_DQS_P<3>

=MEM_B_DQ<30> =MEM_B_DQ<31>

1

C3120

0.1UF

20% 10V

2

CERM 402

1

C3121

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

26 29

IN

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

27

BI

1

C3122

0.1UF

20% 10V

2

CERM 402

1

C3123

0.1UF

20% 10V

2

CERM 402

"Expansion" (bottom) slot

PAGE TITLE

DDR3 SO-DIMM Connector B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm

SYNC_DATE=06/23/2010SYNC_MASTER=K92_SUMA

DRAWING NUMBER

REVISION

BRANCH

PAGE

31 OF 132

SHEET

28 OF 101

SIZE

D

C

B

A

D

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

D

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

PM_SLP_S4_L

17 42 44 65 72

IN

PP3V3_S3

6 7 8

18 19 24 25 30 31 32 47

48 49 53 54 71 72 87

C

ISOLATE_CPU_MEM_L

19 23

IN IN

PP5V_S3

6 7

29 31 41 42 43 45 65 66 71 81

100

CPUMEM_S0

B

CPU_MEM_RESET_L

10 29

IN

R3215

100K

1/16W MF-LF

402

1

5%

2

CRITICAL

CPUMEM_S0

Q3215

SSM6N15FEAPE

SOT563

D

6

MEMRESET_ISOL_LS5V_L

CPU_MEM_RESET_L

MAKE_BASE=TRUE

2

S G

1

CPUMEM_S0

R3201

CRITICAL

CPUMEM_S0

Q3200

SSM6N15FEAPE

SOT563

CPUMEM_S0

R3202

CRITICAL

CPUMEM_S0

Q3200

SSM6N15FEAPE

SOT563

CRITICAL

CPUMEM_S0

Q3215

SSM6N15FEAPE

5

S G

4

5

2

100K

1/16W MF-LF

100K

1/16W MF-LF

SOT563

402

1

5%

2

3

D

SG

4

1

5%

2

6

D

SG

1

D

3

CRITICAL

CPUMEM_S0

Q3205

SSM6N15FEAPE

P1V5CPU_EN_L

CRITICAL

CPUMEM_S0

Q3210

SSM6N15FEAPE

MEMVTT_EN_L

PP1V5_S3

CPUMEM_S0

1

R3216

20K

5% 1/16W MF-LF 402

2

SOT563

2

3

4

2

3

4

D

S G

D

S G

1

2

CPUMEM_S0

C3216

0.1UF

10% 16V X5R 402

CPUMEM_S0

1

R3205

10K

5% 1/16W MF-LF 402

2

P1V5CPU_EN

6

D

SG

1

CRITICAL

CPUMEM_S0

Q3205

SSM6N15FEAPE

SOT563

5

PM_SLP_S3_L

CPUMEM_S0

1

R3210

10K

5% 1/16W MF-LF 402

2

MEMVTT_EN

6

D

SG

1

CRITICAL

CPUMEM_S0

Q3210

SSM6N15FEAPE

SOT563

5

PLT_RESET_L

6 7

26 28 66 71

MEM_RESET_L

71

OUT

6

17 44 72

8

29 66

OUT

18 25 39

IN

26 28

OUT

CPUMEM_S3

R3217

0

1 2

5% 1/16W MF-LF

402

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

1 0 1 1 1 1 1 1 1 2 0 0 1 1 1 1 0 1

to

A

3 0 0 0 1 X 1 0 0

S3

4 0 0 1 1 X 1 0 1 5 0 1 1 1 0 (*) 1 1 1

to

6 0 1 1 1 1 1 1 1 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

8 7 5 4 2 1

PP1V5_S3RS0_CPUDDR

7

10 13 15 71 72

100

345678

1V5 S0 "PGOOD" for CPU

PP3V3_S5

6 7

17 19 20 22 23 24 25 39

45 55 65 70 71 72 82 85 89 98

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

1

R3222

10K

5%

R3220

27.4K

1/16W MF-LF

R3221

33.2K

1/16W MF-LF

1

1%

402

2

1

1%

402

2

P1V5_S0_DIV

NO STUFF

C3220

0.001UF

20% 50V

CERM

402

1/16W MF-LF 402

2

PM_MEM_PWRGD_L

3

CRITICAL

Q3220

5

DMB53D0UV

SOT-563

1

2

4

CRITICAL

G

2

MEMVTT Clamp

Ensures CKE signals are held low in S3

PP0V75_S0_DDRVTT

6 7

26 28 66

PP5V_S3

6 7

29 31 41 42 43 45 65 66 71 81

CPUMEM_S0

R3251

100K

1/16W MF-LF

1

5%

402

2

CRITICAL

CPUMEM_S0

Q3250

SSM6N15FEAPE

MEMVTT_EN

8

29 66

IN

SOT563

D

5

SG

36

CRITICAL

CPUMEM_S0

SSM6N15FEAPE

VTTCLAMP_EN

NO STUFF

3

C3251

0.001UF

4

Q3250

SOT563

20% 50V

CERM

402

2

1

2

6

D

S

1

CPUMEM_S0

VTTCLAMP_L

6

D

SG

1

2 1

PM_MEM_PWRGD

Q3220

DMB53D0UV

SOT-563

1

R3250

10

5% 1/10W MF-LF

603

2

SYNC_MASTER=K18_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

10 17 90

OUT

75mA max load @ 0.75V 60mW max power

SYNC_DATE=04/27/2010

CPU Memory S3 Support

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

32 OF 132

29 OF 101

SIZE

D

C

B

A

D

345678

2 1

NOTE: Must not enable more than two SO-DIMM margining

PP3V3_S3

6 7 8

18 19 24 25 29 31 32 47

48 49 53 54 71 72 87

OMIT

R3318

SHORT

1 2

D

OMIT

R3319

SHORT

1 2

C

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

116S0004

B

116S0004

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm

NONE

MIN_NECK_WIDTH=0.2 mm

NONE

VOLTAGE=3.3V

NONE

402

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm

NONE

MIN_NECK_WIDTH=0.2 mm

NONE

VOLTAGE=3.3V

NONE

402

QTY

2

VREFMRGN

C3300

2.2UF

20%

6.3V CERM

402-LF

SMBUS_PCH_CLK

16 23 26 28 30 41 47 61 88 93

IN

SMBUS_PCH_DATA

16 23 26 28 30 41 47 61 88 93

BI

Addr=0x98(WR)/0x99(RD)

VREFMRGN

C3302

0.1UF

Addr=0x30(WR)/0x31(RD)

SMBUS_PCH_CLK

16 23 26 28 30 41 47 61 88 93

IN

SMBUS_PCH_DATA

16 23 26 28 30 41 47 61 88 93

BI

PCA9557D_RESET_L

25

IN

RST* on ’platform reset’ so that system watchdog will disable margining.

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

DESCRIPTION

RES,MTL FILM,0,5%,0402,SM,LF

1

2

20% 10V

CERM

402

VREFMRGN

1

C3301

0.1UF

20% 10V

2

CERM 402

6

7

9

10

1

2

3 4 5

1 2

REFERENCE DES

8

VDD

SCL

MSOP

SDA

A0

A1

GND

3

16

VCC

U3301

PCA9557

QFN

A0 A1 A2

SCL SDA

THRM

GND

PAD

8

17

R3303,R3305

R3309,R3311

CRITICAL VREFMRGN

U3300

VOUTA

VOUTB

VOUTC

VOUTD

DAC5574

CRITICAL VREFMRGN

(OD)

P0 P1 P2 P3 P4 P5 P6 P7

RESET*

1

VREFMRGN_SODIMMA_DQ

2

VREFMRGN_SODIMMB_DQ

4

VREFMRGN_SODIMMS_CA

5

VREFMRGN_MEMVREG_FBVREF

NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable both at the same time!

6

NC

7

VREFMRGN_DQ_SODIMMA_EN

9

VREFMRGN_DQ_SODIMMB_EN

10

VREFMRGN_CA_SODIMMA_EN

11

VREFMRGN_CA_SODIMMB_EN

12

VREFMRGN_MEMVREG_EN

13

VREFMRGN_FRAMEBUF_EN

14

NC

15

CRITICAL

BOM OPTION

VREFMRGN_NOT

VREFMRGN

1

R3301

100K

5% 1/16W MF-LF 402

2

VREFMRGN

1

R3302

100K

5% 1/16W MF-LF 402

2

VREFMRGN

1

R3307

100K

5% 1/16W MF-LF 402

2

VREFMRGN

1

R3308

100K

5% 1/16W MF-LF 402

2

VREFMRGN

C3303

0.1UF

CERM

VREFMRGN

C3304

0.1UF

CERM

VREFMRGN

C3305

20% 10V

402

20% 10V

402

0.1UF

CERM

20% 10V

402

CRITICAL

1

2

A2

A3

B1

V+

V-

B4

VREFMRGN

U3302

MAX4253

UCSP

A1

A4

CRITICAL

VREFMRGN

B1

V+

V-

B4

U3302

MAX4253

UCSP

C1

C4

C2

C3

CRITICAL

1

2

A2

A3

B1

V+

V-

B4

VREFMRGN

U3303

MAX4253

UCSP

A1

A4

CRITICAL

VREFMRGN

B1

V+

V-

B4

B1

V+

V-

B4

U3303

MAX4253

UCSP

C1

C4

CRITICAL VREFMRGN

U3304

MAX4253

UCSP

C1

C4

C2

C3

1

C2

2

C3

buffers at once or VRef source may be overloaded.

VREFMRGN

PPVTTDDR_S3

6 7

66

10mA max load

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_MEMVREG_BUF

R3303

200

1 2

1% 1/16W MF-LF

402

VREFMRGN

R3304

133

1 2

1% 1/16W MF-LF

402

VREFMRGN

R3305

200

1 2

1% 1/16W MF-LF

402

VREFMRGN

R3306

133

1 2

1% 1/16W MF-LF

402

VREFMRGN

R3309

200

1 2

1% 1/16W MF-LF

402

VREFMRGN

R3310

133

1 2

1% 1/16W MF-LF

402

VREFMRGN

R3311

200

1 2

1% 1/16W MF-LF

402

VREFMRGN

R3312

133

1 2

1% 1/16W MF-LF

402

VREFMRGN

R3314

33.2K

1 2

1% 1/16W MF-LF

402

PLACE_NEAR=J2900.1:2.54mm

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3303.2:1mm

PLACE_NEAR=J3100.1:2.54mm

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3305.2:1mm

PLACE_NEAR=J2900.126:2.54mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3309.2:1mm

PLACE_NEAR=J3100.126:2.54mm

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3311.2:1mm

DDRREG_FB

PLACE_NEAR=R7320.2:1mm

9

26

9

28

26

28

OUT

D

C

66

B

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page: VREFMRGN - Stuffs VREF Margining Circuitry. VREFMRGN_NOT - Bypasses VREF Margining Circuitry.

A

DAC Channel: PCA9557D Pin: Nominal value Margined target: DAC range: VRef current: DAC step size:

8 7 5 4 2 1

MEM A VREF DQ

A

MEM B VREF DQ

B 21

MEM A VREF CA

C 3 4

0.75V (DAC: 0x3A)

0.300V - 1.200V (+/- 450mV)

0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced)

7.69mV / step @ output

MEM B VREF CA

C

VREFMRGN

1

R3316

0

5% 1/16W MF-LF

402

2

VREFMRGN_MEMVREG_FBVREF_R

MEM VREG

D 5

1.5V (DAC: 0x3A)

1.000V - 2.000V (+/- 500mV)

0.000V - 3.000V (0x00 - 0x74) +61uA - -61uA (- = sourced)

8.59mV / step @ output

VREFMRGN

1

R3313

100K

5% 1/16W MF-LF 402

2

VREFMRGN

1

R3315

100K

5% 1/16W MF-LF 402

2

CRITICAL

VREFMRGN_FRAMEBUF_BUF

VREFMRGN

B1

V+

V-

B4

U3304

MAX4253

UCSP

A1

A4

VREFMRGN_FRAMEBUF_BUF_R

A2

A3

GPU Frame Buffer (1.8V, 70% VRef)

D 6

1.267V (DAC: 0x8B)

1.056V - 1.442V (+/- 180mV)

0.000V - 3.300V (0x00 - 0xFF) +6.0mA - -5.0mA (- = sourced)

1.51mV / step @ output

36

VREFMRGN

1

R3317

0

5% 1/16W MF-LF 402

2

SYNC_MASTER=K18_MLB

PAGE TITLE

FSB/DDR3/FRAMEBUF Vref Margining

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

33 OF 132

30 OF 101

SIZE

A

D

2 1

OMIT_TABLE

L3470

0.6NH+/-0.1NH-0.85A

NOSTUFF

1

C3470

0.1UF

10% 16V

2

X5R-CERM 0201

0201

PCIE_AP_R2D_PI_P

21

NOSTUFF

1

C3471

0.1UF

10% 16V

2

X5R-CERM 0201

PLACE_NEAR=J3401.15:2.54mm

C3431

1 2

0.1UF

X5R16V10%

PCIE_AP_R2D_C_P

402-1

PART NUMBER

117S0002

QTY

4

345678

16 93

IN

DESCRIPTION

RES, 0OHM, 0201

REFERENCE DES

L3470,L3471,L3473,L3474

CRITICAL

BOM OPTION

L3471

1

21

PCIE_AP_R2D_PI_N

NOSTUFF

1

C3473

0.1UF

10% 16V

2

X5R-CERM 0201

PCIE_AP_D2R_P

NOSTUFF

1

C3475

0.1UF

10% 16V

2

X5R-CERM 0201

PLACE_NEAR=J3401.17:2.54mm

D

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

WIFI_EVENT_L

93

6

44 47 50 79 96

BI

6

44 47 50 79 96

IN

6

44 45

IN

PCIE_AP_R2D_P

6

PCIE_AP_R2D_N

0.6NH+/-0.1NH-0.85A

NOSTUFF

1

C3472

0.1UF

10% 16V

2

X5R-CERM 0201

L3473

0.6NH+/-0.1NH-0.85A

1

2

C3474

0.1UF

10% 16V X5R-CERM 0201

0201

NOSTUFF

0201

OMIT_TABLE

L3474

0.6NH+/-0.1NH-0.85A

21

1

C3432

0.01UF

10% 16V CERM 402

2

C3476

0.1UF

10%

NOSTUFF

16V X5R-CERM 0201

L3406

2 1

FERR-120-OHM-1.5A

PLACE_NEAR=J3401.27:2.54MM

516S0582

CRITICAL

J3401

500913-0302

F-ST-SM

32

C

31

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

34

33

PCIE_AP_D2R_PI_P

PCIE_AP_D2R_PI_N

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PCIE_CLK100M_AP_CONN_P

6

98

PCIE_CLK100M_AP_CONN_N

6

98

PP3V3_S3_BT_F

1

2

0402-LF

0201

OMIT_TABLE

CRITICAL

L3401

90-OHM-100MA

4

1 2

PLACE_NEAR=J3401.11:2.54mm

DLP11S

SYM_VER-1

PP3V3_S3

PCIE_AP_D2R_N

NOSTUFF

1

C3477

0.1UF

10% 16V

2

X5R-CERM 0201

AIRPORT

3

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

BLUETOOTH

6 7 8 47 48 49 53 54 71 72 87

B

PCIE_WAKE_L

6

17 25 84

OUT

2

0.1UF

X5R

16V

10%

C3430

6

16 93

OUT

6

16 93

OUT

USB_BT_P

USB_BT_N

18 19 24 25 29 30 31 32

6

PCIE_AP_R2D_C_N

402-1

PLACE_NEAR=J3401.29:2.54MM

24 92

BI

24 92

BI

AP_RESET_CONN_L

AP_CLKREQ_Q_L

16 93

IN

1A PEAK

45 31

16 93

IN

16 93

IN

FERR-120-OHM-3A

PP3V3_WLAN

6

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.2 mm

C3422

0.1uF

20% 10V

CERM

402

155S0367

L3404

1 2

0603

1

2

3V S3 WLAN FET

MOSFET

CHANNEL

RDS(ON)

LOADING

MIN_NECK_WIDTH=0.4 mm MIN_LINE_WIDTH=1 mm

PP3V3_WLAN_F

1

C3421

0.1uF

20% 10V

2

CERM

402

PLACE_NEAR=J3401.29:2.54MM

1

R3453

100K

1% 1/16W MF-LF 402

2

TPCP8102

P-TYPE

20-30 MOHM @2.5V

1 A (EDP)

CRITICAL

Q3450

TPCP8102

6 5 78

C3450

0.1UF

1

10% 16V X5R

402-1

23V1K-SM

D

2

XW3452

SM

2 1

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.5 mm

PP3V3_WLAN_R

Supervisor & CLKFREG # Isolation

Delay = 60 ms +/- 20%

PP3V3_WLAN_F

1

R3454

232K

1% 1/16W MF-LF 402

2

P3V3WLAN_VMON

1

R3455

100K

1% 1/16W MF-LF 402

2

4

7

PP3V3_S3

31

1

CRITICAL

VDD

U3440

SLG4AP016V

TDFN

SENSE

+

-

0.7V

THRM

PAD

DLY

GND

9

RESET*

IN

1

2

3

MR*

6

EN

8

OUT

(OD)

5

3

S

21

G

4

P3V3WLAN_SS

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

C3440

0.1uF

20% 10V CERM 402

AP_RESET_L

AP_PWR_EN

AP_CLKREQ_L

C3451

0.033UF

D

PP3V3_S3

1

25

18 72

16 23

R3451

10K

5% 1/16W MF-LF 402

2

PM_WLAN_EN_L

1

10% 16V

2

X5R 402

R3450

33K

1

5% 1/16W MF-LF

402

IN

OUT

49 53 54 71 72 87 6 7 8

18 19 24 25

29 30 31 32 47 48

72

IN

C

B

A

518S0816

CRITICAL

J3402

CCR20-6K710S

F-RT-SM

8

6

5

4

3

2

1

7

PP5V_S3_ALSCAMERA_F

6

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA USB_CAMERA_CONN_P

6

92

USB_CAMERA_CONN_N

6

92

IN

BI

6

44 47 53 54 96

6

44 47 53 54 96

8 7 5 4 2 1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

CRITICAL

L3407

90-OHM DLP0NS

SYM_VER-1

1 2

PLACE_NEAR=J3402.3:2.54MM

ALS CAMERA

34

USB_CAMERA_P

USB_CAMERA_N

275 mA peak 206 mA nominal max

18

BI

18

BI

PLACE_NEAR=J3402.6:2.54MM

L3408

FERR-120-OHM-1.5A

1

C3452

0.1uF

20% 10V

2

CERM 402

0402-LF

12

PP5V_S3

6 7

29 41 42 43 45 65 66 71 81

100

SYNC_MASTER=K91_MARY SYNC_DATE=10/08/2010

PAGE TITLE

X19/ALS/CAMERA CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

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36

34 OF 132

31 OF 101

SIZE

A

D

345678

2 1

SD CARD 3.3V OVERCURRENT PROTECTION CHIP WITH ACTIVE LOAD DISCHARGE

TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.

CRITICAL

U3500

TPS2065-1

2

DGN

D

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

ENET_CR_PWREN

36

CRITICAL

1

C3500

10UF

20%

6.3V

2

X5R 603

1

C3501

0.1UF

10% 16V

2

X7R-CERM 402

IN0

3

IN1

4

353S3004

EN

GND

1

THRM

PAD

9

OUT0 OUT1 OUT2

OC*

6 7 8

5

CRITICAL

1

C3502

10UF

20%

6.3V

2

X5R 603

1

C3503

0.1UF

10% 16V

2

X7R-CERM 402

SDCONN_OC_L_R

NOSTUFF

1

R3500

47K

5% 1/16W MF-LF 402

2

R3502

1 2

PP3V3_S0_SW_SD_PWR

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

R3501

0

5% 1/16W MF-LF

402

10K

1/16W MF-LF

402

PP3V3_S0

1

5%

2

SDCONN_OC_L

32

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

D

SDCONN DETECT DEBOUNCE, INVERSION, AND DETECT-CHANGED PCH GPIO LATCH CIRCUIT

PP3V3_S3

6 7 8

18 19 24 25 29 30 31 47

C

48 49 53 54 71 72 87

1UF

10% 10V X5R

402-1

1

2

Must STUFF R3512 and NOSTUFF R3514 when R3511 is NOT STUFFED.

C3510

C

CRITICAL

1

R3511 and R3510 mutually exclusive to control effect of =ENET_RESET_L

PLT_RST_BUF_L

25 35

IN

-> FROM PCH GPIO

on DET_CHANGED# logic.

R3511

0

1 2

5% 1/16W MF-LF

402

NOSTUFF

R3510

10K

5% 1/16W MF-LF

402

ENET_LOW_PWR

19 36

IN

SLG_ENET_RESET_IN_L

SDCONN_DETECT

32

FROM SD CONN ->

1

2

3

6

B

SLG4AP014V

LOW_PWR

RST_IN*

DET_IN

DLY

(IPU)

GND PAD

5

VDD

U3511

TDFN

RST

LOGIC

RST_OUT*

XOR

DET_CHNGD*

DET_OUT

THRM

9

4

SLG_ENET_RESET_OUT_L

(OD)

8

SDCONN_STATE_CHANGE

(OD)

7

SDCONN_DETECT_L

DLY block is 20ms nominal When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms regardless ofmove RST_IN# state. Otherwise RST_OUT# follows RST_IN#

-> TO ENET CHIP

R3514

0

1 2

5% 1/16W MF-LF

-> TO PCH GPIO

402

18 23

OUT

36

OUT

R3514 and R3512 mutually exclusive to bypass reset logic

ENET_RESET_L

NOSTUFF

1

R3512

0

5% 1/16W MF-LF 402

2

36 94

OUT

B

SD CARD CONNECTOR

516-0225 CRITICAL

J3500

SD-CARD-K19-K24

CRITICAL

L3500

OUT

BI

32

OUT

SDCONN_CLK SDCONN_CMD SDCONN_DATA<0> SDCONN_DATA<1> SDCONN_DATA<2> SDCONN_DATA<3> SDCONN_DATA<4> SDCONN_DATA<5> SDCONN_DATA<6> SDCONN_DATA<7> SDCONN_DETECT

36 94

IN

36 94

A

36 94

36

32

R3579 R3561 R3571 R3572 R3573 R3574 R3575 R3576 R3577 R3578 R3560

33

0

1332

1 2

5%

1/16W MF-LF

5%331/16W MF-LF

21

5%

21

5%331/16W MF-LF

21

5%331/16W MF-LF

21

5%331/16W MF-LF

21

5%331/16W MF-LF

21

5%331/16W MF-LF

21

5%331/16W MF-LF

21

5%

402

SDCONN_CLK_R

402

MF-LF1/16W

402

MF-LF1/16W

402

MF-LF1/16W

402

94

NOSTUFF

1

C3571

22PF

5% 50V

2

CERM 402

47NH-1.3OHM

1 2

SDCONN_CMD_R SDCONN_R_DATA<0> SDCONN_R_DATA<1> SDCONN_R_DATA<2> SDCONN_R_DATA<3> SDCONN_R_DATA<4> SDCONN_R_DATA<5> SDCONN_R_DATA<6> SDCONN_R_DATA<7> SDCONN_DETECT_R

SDCONN_WP PP3V3_S0_SW_SD_PWR

0402

SDCONN_CLK_R_L

94 94

1

2

NOSTUFF

C3570

15PF

5% 50V CERM 402

8 7 5 4 2 1

F-RT-TH

3

VSS

6

VSS

5

CLK

2

CMD

7

DAT0

8

DAT1

9

DAT2

1

CD/DAT3

10

DAT4

11

DAT5

12

DAT6

13

DAT7

14

CARD_DETECT_SW

15

CARD_DETECT_GND

16

WRITE_PROTECT_SW

4

VDD

17

SHLD_PIN

18

SHLD_PIN

19

SHLD_PIN

20

SHLD_PIN

(CARD INSERTED = OPEN) CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG MAKES THE ACTIVE-HIGH CASE UNUSABLE.

36

SYNC_MASTER=K91_ERIC

PAGE TITLE

SD READER CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=10/08/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

35 OF 132

SHEET

32 OF 101

SIZE

A

D

345678

2 1

CRITICAL

RECEIVE

EEPROM

OMIT_TABLE

(SYM 1 OF 2)

CLK REQUEST

TEST PORT

PORT0PORT1

U3600

T29

FCBGA

PCIE GEN2

MISC

SINK PORT 0SINK PORT 1

SOURCE PORT 0

DPSRC0_HOT_PLUG_DET

DISPLAY

PORTS

PET_0_P PET_0_N

PET_1_P PET_1_N

TRANSMIT

PET_2_P PET_2_N

PET_3_P PET_3_N

WAKE*

PERST*

RSENSE

RBIAS

PCIE_RST_0* PCIE_RST_1* PCIE_RST_2* PCIE_RST_3*

POWER ON RESET

REFCLK_100_IN_P REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

CLOCKS

TMU_CLK_OUT

TMU_CLK_IN

DPSRC0_ML_LANE_3P DPSRC0_ML_LANE_3N

DPSRC0_ML_LANE_2P DPSRC0_ML_LANE_2N

DPSRC0_ML_LANE_1P DPSRC0_ML_LANE_1N

DPSRC0_ML_LANE_0P DPSRC0_ML_LANE_0N

DPSRC0_AUX_CHP DPSRC0_AUX_CHN

DP_ATEST DP_RES_0 DP_RES_1

PRT2_T29T_P PRT2_T29T_N

PRT2_T29R_P PRT2_T29R_N

PORT2

T29_2_LSEO T29_2_LSOE

PRT3_T29T_P PRT3_T29T_N

PRT3_T29R_P PRT3_T29R_N

PORT3

T29_3_LSEO T29_3_LSOE

1

2

1

2

10K

1/16W MF-LF

5%

402

1

2

C3640

C3641

C3642

C3643

C3644

C3645

C3646

C3647

R3651

IN

6

IN

OUT

IN

1

2

6

R3632

100K

5% 1/16W MF-LF 402

OUT

IN

OUT

IN

OUT

IN

OUT

IN

0.1uF

35

8

19 87

16

8

19 23 87

8

19 87

16 93

8

33

8

33

8

33

8

33

10K

V21

PCIE_T29_D2R_C_P<0>

93

T21

PCIE_T29_D2R_C_N<0>

93

P21

PCIE_T29_D2R_C_P<1>

93

M21

PCIE_T29_D2R_C_N<1>

93

K21

PCIE_T29_D2R_C_P<2>

93

H21

PCIE_T29_D2R_C_N<2>

93

F21

PCIE_T29_D2R_C_P<3>

93

D21

PCIE_T29_D2R_C_N<3>

93

F1

T29_PCIE_WAKE_L

E6

T29_RESET_L

E14

T29_RSENSE

R3655

1.0K

0.5% 1/16W MF-LF

603

NO STUFF

JTAG

TDI TMS TCK TDO

E16

T29_RBIAS

Not used in host mode.

K1

TP_T29_PCIE_RESET0_L

J2

TP_T29_PCIE_RESET1_L

K3

TP_T29_PCIE_RESET2_L

J4

TP_T29_PCIE_RESET3_L

T3

JTAG_ISP_TDI

R4

JTAG_T29_TMS

R2

JTAG_ISP_TCK

T1

JTAG_ISP_TDO

PCIE_CLK100M_T29_P

H17 G16

PCIE_CLK100M_T29_N

P17

SYSCLK_CLK25M_T29_R

R16

TP_T29_XTAL25OUT

U2

T29_TMU_CLK_OUT

E2

T29_TMU_CLK_IN

R3699

AA18

TP_DP_T29SRC_ML_CP<3>

Y17

TP_DP_T29SRC_ML_CN<3>

AA16

TP_DP_T29SRC_ML_CP<2>

Y15

TP_DP_T29SRC_ML_CN<2>

AA14

TP_DP_T29SRC_ML_CP<1>

Y13

TP_DP_T29SRC_ML_CN<1>

AA12

TP_DP_T29SRC_ML_CP<0>

Y11

TP_DP_T29SRC_ML_CN<0>

W16

TP_DP_T29SRC_AUXCH_CP

U16

TP_DP_T29SRC_AUXCH_CN

V3

DP_T29SRC_HPD

Y19

T29_DP_ATEST

Y21 AA20

T29_DP_RES

R3685

14.0K

1% 1/16W MF-LF

402

A14

NC_T29_R2D_CP<2>

A12

NC_T29_R2D_CN<2>

C12

NC_T29_D2RP<2>

C10

NC_T29_D2RN<2>

G4

T29_LSEO_LSOE2

H3

T29_LSEO_LSOE2

A18

NC_T29_R2D_CP<3>

A16

NC_T29_R2D_CN<3>

C16

NC_T29_D2RP<3>

C14

NC_T29_D2RN<3>

G2

T29_LSEO_LSOE3

H1

T29_LSEO_LSOE3

NOTE: All unused LSOE/EO pairs should be aliased together. Other signals okay to float (TP/NC).

36

1 2

2 1

C3685

100PF

CERM

50V

402

PCIE_T29_D2R_P<0>

16V 402X5R10%

PCIE_T29_D2R_N<0>

X5R 40210%

16V

PCIE_T29_D2R_P<1>

16V 40210%

X5R

PCIE_T29_D2R_N<1>

X5R16V10% 402

PCIE_T29_D2R_P<2>

10% X5R16V 402

PCIE_T29_D2R_N<2>

10% 402X5R16V

PCIE_T29_D2R_P<3>

X5R 40210%

16V

PCIE_T29_D2R_N<3>

16V10%

X5R 402

PP3V3_T29

5%

MF-LF1/16W

PP3V3_T29

1

R3698

10K

5% 1/16W MF-LF 402

2

R3696

1/16W MF-LF

402

R3695

1 2

1/16W

1

MF-LF

1K

5%

2

100pF SRF > 40MHz

BYPASS=U3600.Y19::2mm

BYPASS=U3600.Y19::5.08mm

1

C3686

5%

0.01UF

10% 16V

2

CERM 402

8 9

93

OUT

8 9

93

OUT

8 9

93

OUT

8 9

93

OUT

8 9

93

OUT

8 9

93

OUT

8 9

93

OUT

8 9

93

OUT

7

16 19 25 33 34 35 87

402

7

16 19 25 33 34 35 87

806

SYSCLK_CLK25M_T29

1%

402

SYNC_MASTER=T29_REF

PAGE TITLE

T29 Host (1 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

25

IN

SYNC_DATE=10/12/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

36 OF 132

33 OF 101

SIZE

D

C

B

A

D

0.1uF

R3622

10K

5% 1/16W MF-LF 402

1

R3625

0

5% 1/16W MF-LF 402

2

R3629

79 83

R3630

79 83

R3631

1 2

10% 16V X5R 402

1 2

10% 16V X5R 402

1 2

R3610

R3611

C3615

C3616

1

R3621

10K

5% 1/16W MF-LF 402

2

1

0

5% 1/16W MF-LF

402

2

OUT

1

100K

5% 1/16W MF-LF

402

2

OUT

1

100K

5% 1/16W MF-LF

402

2

16V10%

NO STUFF

1 2

0

1 2

0

NO STUFF

0.1uF

X5R

1 2

PCIE_T29_R2D_P<0>

93

40216V10%

PCIE_T29_R2D_N<0>

93

402X5R16V10%

PCIE_T29_R2D_P<1>

93

PCIE_T29_R2D_N<1>

93

PCIE_T29_R2D_P<2>

93

402X5R

PCIE_T29_R2D_N<2>

93

402X5R16V10%

PCIE_T29_R2D_P<3>

93

402X5R

PCIE_T29_R2D_N<3>

93

40210% 16V

T29_MONDC0

5%

1/16W

T29_MONDC1

5%

1/16W MF-LF

T29_MONOBSP

10% 402X5R16V

T29_MONOBSN

16V10%

T29_CLKREQ_ISOL_L

35

OUT

T29_GPIO<1> T29_GPIO<2> T29_RSVD

T29_SPI_MOSI

95

T29_SPI_MISO

95

T29_SPI_CS_L

95

T29_SPI_CLK

95

T29_THERMD_P

50

Use B1 GND ball for THERM_DN

T29_TEST_EN TP_T29_TEST_POINT_0 TP_T29_TEST_POINT_1 TP_T29_TEST_POINT_2 T29_TEST_POINT_3

DP_T29SNK0_ML_P<3>

6

33 95

DP_T29SNK0_ML_N<3>

6

33 95

DP_T29SNK0_ML_P<2>

6

33 95

DP_T29SNK0_ML_N<2>

6

33 95

DP_T29SNK0_ML_P<1>

6

33 95

DP_T29SNK0_ML_N<1>

6

33 95

DP_T29SNK0_ML_P<0>

6

33 95

DP_T29SNK0_ML_N<0>

6

33 95

DP_T29SNK0_AUXCH_P

6

33 95

DP_T29SNK0_AUXCH_N

6

33 95

DP_T29SNK0_HPD

DP_T29SNK1_ML_P<3>

6

33 95

DP_T29SNK1_ML_N<3>

6

33 95

DP_T29SNK1_ML_P<2>

6

33 95

DP_T29SNK1_ML_N<2>

6

33 95

DP_T29SNK1_ML_P<1>

6

33 95

DP_T29SNK1_ML_N<1>

6

33 95

DP_T29SNK1_ML_P<0>

6

33 95

DP_T29SNK1_ML_N<0>

6

33 95

DP_T29SNK1_AUXCH_P

6

33 95

DP_T29SNK1_AUXCH_N

6

33 95

DP_T29SNK1_HPD

T29_R2D_C_P<0>

6

84 95

OUT

T29_R2D_C_N<0>

6

84 95

OUT

T29_D2R_P<0>

6

84 95

IN

T29_D2R_N<0>

6

84 95

IN

T29_LSEO<0>

84

OUT

T29_LSOE<0>

84

IN

T29_R2D_C_P<1>

6

84 95

OUT

T29_R2D_C_N<1>

6

84 95

OUT

T29_D2R_P<1>

6

84 95

IN

T29_D2R_N<1>

6

84 95

IN

T29_LSEO<1>

84

OUT

T29_LSOE<1>

84

IN

I2C_T29_SDA

47 84 95

BI

I2C_T29_SCL

47 84 95

OUT

402X5R

MF-LF

402

V19

PER_0_P

T19

PER_0_N

P19

PER_1_P

M19

PER_1_N

K19

PER_2_P

H19

PER_2_N

F19

PER_3_P

D19

PER_3_N

B21

MONDC0

A20

MONDC1

K17

MONOBSP

M17

MONOBSN

P3

PCIE_CLKREQ_0*

N4

PCIE_CLKREQ_1*

M3

PCIE_CLKREQ_2*

L4

PCIE_CLKREQ_3*

P1

EE_DI

M1

EE_DO

N2

EE_CS*

L2

EE_CLK

A2

THERM_DP

E4

TEST_EN

P5

TEST_POINT_0

N6

TEST_POINT_1

M5

TEST_POINT_2

L6

TEST_POINT_3

AA4

DPSNK0_ML_LANE_3P

Y3

DPSNK0_ML_LANE_3N

AA6

DPSNK0_ML_LANE_2P

Y5

DPSNK0_ML_LANE_2N

AA8

DPSNK0_ML_LANE_1P

Y7

DPSNK0_ML_LANE_1N

AA10

DPSNK0_ML_LANE_0P

Y9

DPSNK0_ML_LANE_0N

V1

DPSNK0_AUX_CHP

W2

DPSNK0_AUX_CHN

V5

DPSNK0_HOT_PLUG_DET

V9

DPSNK1_ML_LANE_3P

U8

DPSNK1_ML_LANE_3N

V11

DPSNK1_ML_LANE_2P

U10

DPSNK1_ML_LANE_2N

V13

DPSNK1_ML_LANE_1P

U12

DPSNK1_ML_LANE_1N

V15

DPSNK1_ML_LANE_0P

U14

DPSNK1_ML_LANE_0N

V7

DPSNK1_AUX_CHP

U6

DPSNK1_AUX_CHN

U4

DPSNK1_HOT_PLUG_DET

A6

PRT0_T29T_P

A4

PRT0_T29T_N

C4

PRT0_T29R_P

C2

PRT0_T29R_N

J6

T29_0_LSEO

K5

T29_0_LSOE

A10

PRT1_T29T_P

A8

PRT1_T29T_N

C8

PRT1_T29R_P

C6

PRT1_T29R_N

G6

T29_1_LSEO

H5

T29_1_LSOE

F3

T29_SDA

F5

T29_SCL

10K

402

C3600

C3601

C3602

C3603

C3604

C3605

C3606

C3607

1

5%

2

PCIE_T29_R2D_C_P<0>

8 9

93

IN

PCIE_T29_R2D_C_N<0>

8 9

93

IN

PCIE_T29_R2D_C_P<1>

8 9

93

IN

PCIE_T29_R2D_C_N<1>

8 9

93

IN

PCIE_T29_R2D_C_P<2>

8 9

93

IN

D

1

402

5%

2

1

R3691

2

(T29_SPI_CLK)

R3690

3.3K

1/16W MF-LF

C

(T29_SPI_CS_L)

C3690

3.3K

5% 1/16W MF-LF 402

T29ROM_WP_L

T29ROM_HOLD_L

1UF

10%

6.3V CERM

402

2

5

6

1

3

7

D

C

S_L

W_L

HOLD_L

8

VCC

U3690

M95160

2KX8-1.8V

MLP

VSS

4

CRITICAL OMIT_TABLE

2

Q

THM PAD

9

93

PCIE_T29_R2D_C_N<2>

8 9

IN

PCIE_T29_R2D_C_P<3>

8 9

IN

PCIE_T29_R2D_C_N<3>

8 9

IN

DEBUG: For monitoring current/voltage

DEBUG: For monitoring clock

R3692

(T29_SPI_MISO)(T29_SPI_MOSI)

3.3K

1/16W MF-LF

402

TP_T29_MONDC0

TP_T29_MONDC1

TP_T29_MONOBSP

TP_T29_MONOBSN

PP3V3_T29

7

16 19 25 33 34 35 87

1

R3623

5%

2

1

R3693

3.3K

5% 1/16W MF-LF 402

2

1/16W MF-LF

SNK0 AC Coupling

0.1uF

1 2

DP_T29SNK0_ML_P<0>

10%

16V

X5R

402

DP_T29SNK0_ML_N<0>

10%

16V

X5R 402

DP_T29SNK0_ML_P<1>

16V10% 402

X5R

DP_T29SNK0_ML_N<1>

10% 16V X5R 402

DP_T29SNK0_ML_P<2>

16V

10% X5R 402

DP_T29SNK0_ML_N<2>

10%

16V

X5R

402

DP_T29SNK0_ML_P<3>

16V10%

X5R

402

DP_T29SNK0_ML_N<3>

10%

16V 402

X5R

DP_T29SNK0_AUXCH_P

16V10% 402

X5R

DP_T29SNK0_AUXCH_N

10%

16V 402

X5R

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

DP_T29SNK0_ML_C_P<0>

6

78 95

IN

DP_T29SNK0_ML_C_N<0>

6

78 95

IN

DP_T29SNK0_ML_C_P<1>

6

78 95

IN

DP_T29SNK0_ML_C_N<1>

6

78 95

IN

B

DP_T29SNK0_ML_C_P<2>

6

78 95

IN

DP_T29SNK0_ML_C_N<2>

6

78 95

IN

DP_T29SNK0_ML_C_P<3>

6

78 95

IN

DP_T29SNK0_ML_C_N<3>

6

78 95

IN

DP_T29SNK0_AUXCH_C_P

6

78 95

BI

DP_T29SNK0_AUXCH_C_N

6

78 95

BI

C3620

C3621

C3622

C3623

C3624

C3625

C3626

C3627

C3628

C3629

SNK1 AC Coupling

0.1uF

1 2

DP_T29SNK1_ML_P<0>

10%

16V

X5R 402

DP_T29SNK1_ML_N<0>

10%

16V

X5R 402

DP_T29SNK1_ML_P<1>

10% 16V X5R

402

DP_T29SNK1_ML_N<1>

10%

16V

X5R

402

DP_T29SNK1_ML_P<2>

10%

16V

X5R

402

DP_T29SNK1_ML_N<2>

10%

16V

X5R 402

DP_T29SNK1_ML_P<3>

10%

16V

X5R

402

DP_T29SNK1_ML_N<3>

10%

16V

X5R 402

DP_T29SNK1_AUXCH_P

10%

16V

X5R 402

DP_T29SNK1_AUXCH_N

10% 16V

402X5R

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

DP_T29SNK1_ML_C_P<0>

6

78 95

IN

DP_T29SNK1_ML_C_N<0>

6

78 95

IN

DP_T29SNK1_ML_C_P<1>

6

78 95

IN

DP_T29SNK1_ML_C_N<1>

6

78 95

IN

DP_T29SNK1_ML_C_P<2>

6

78 95

A

IN

DP_T29SNK1_ML_C_N<2>

6

78 95

IN

DP_T29SNK1_ML_C_P<3>

6

78 95

IN

DP_T29SNK1_ML_C_N<3>

6

78 95

IN

DP_T29SNK1_AUXCH_C_P

6

78 95

BI

DP_T29SNK1_AUXCH_C_N

6

78 95

BI

C3630

C3631

C3632

C3633

C3634

C3635

C3636

C3637

C3638

C3639

8 7 5 4 2 1

345678

2 1

D

PP1V05_T29

7

35

2100 mA (Single Port) 2250 mA (Dual Port) EDP: 3000 mA

R3720

0

1 2

5% 1/16W MF-LF

402

C

L3730

FERR-120-OHM-1.5A

1 2

0402

1

C3700

10UF

20%

6.3V 2

X5R 603

1

C3701

10UF

20%

6.3V 2

X5R 603

PP1V05_T29_VDD_DP

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PP1V05_T29_VDD_DPPLL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

1

C3705

1UF

10%

6.3V

2

CERM 402

1

C3710

1UF

10%

6.3V

2

CERM 402

1

C3706

1UF

10%

6.3V

2

CERM 402

1

C3711

1UF

10%

6.3V

2

CERM 402

1

C3707

1UF

10%

6.3V

2

CERM 402

1

C3712

1UF

10%

6.3V

2

CERM 402

1

C3720

1UF

10%

6.3V

2

CERM 402

1

C3708

1UF

10%

6.3V

2

CERM 402

1

C3713

1UF

10%

6.3V

2

CERM 402

1

C3721

1UF

10%

6.3V

2

CERM 402

1

C3709

1UF

10%

6.3V

2

CERM 402

1

C3714

1UF

10%

6.3V

2

CERM 402

1

C3722

1UF

10%

6.3V

2

CERM 402

1

C3730

2.2UF

20%

6.3V

2

CERM 402-LF

B

H9

VCC1P0

H11

VCC1P0

H13

VCC1P0

K9

VCC1P0

K11

VCC1P0

K13

VCC1P0

M9

VCC1P0

M11

VCC1P0

M13

VCC1P0

H15

VCC1P0_PE

K15

VCC1P0_PE

M15

VCC1P0_PE

E8

VCC1P0_PE

E10

VCC1P0_PE

E12

VCC1P0_PE

G14

VCC1P0_PE

R8

VDD1P0_DP_RX1

R10

VDD1P0_DP_TXRX

R12

VDD1P0_DP_TXRX

R14

VDD1P0_DP_PLL

G8

VSS

J8

VSS

J10

VSS

J12

VSS

J14

VSS

L8

VSS

L10

VSS

L12

VSS

L14

VSS

N8

VSS

N10

VSS

N12

VSS

N14

VSS

B1

VSSPE

B3

VSSPE

B5

VSSPE

B7

VSSPE

B9

VSSPE

B11

VSSPE

B13

VSSPE

B15

VSSPE

B17

VSSPE

B19

VSSPE

C18

VSSPE

C20

VSSPE

D1

VSSPE

D3

VSSPE

D5

VSSPE

D7

VSSPE

D9

VSSPE

D11

VSSPE

D13

VSSPE

D15

VSSPE

D17

VSSPE

E18

VSSPE

E20

VSSPE

F7

VSSPE

CRITICAL

OMIT_TABLE

U3600

T29

FCBGA

(SYM 2 OF 2)

VCC3P3_DP_TXRXBIAS

GND VCC

VCC3P3 VCC3P3 VCC3P3

VCC3P3_T29 VCC3P3_T29

VCC3P3_DP_RX1 VCC3P3_DP_RX1

VCC3P3_DP_TXRX VCC3P3_DP_TXRX

VDD3P3DP_PLL

VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP VSSDP

VSSDP_PLL

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

H7 M7 K7

G10 G12

P7 R6

P9 P11

P13

P15

T5 T7 T9 T11 T15 T17 V17 W4 W6 W8 W10 W12 W14 Y1 AA2

T13

F9 F11 F13 F15 F17 G18 G20 J16 J18 J20 L16 L18 L20 N16 N18 N20 R18 R20 U18 U20 W18 W20

C3744

1UF

6.3V CERM

C3753

1UF

6.3V CERM

C3760

2.2UF

6.3V CERM

402-LF

C3770

2.2UF

6.3V CERM

402-LF

1

C3743

10%

2

402

1

C3752

10%

2

402

PP3V3_T29_PLL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

20%

2

PP3V3_T29_DPBIAS

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

20%

2

1UF

6.3V CERM

1UF

6.3V CERM

10%

402

10%

402

1

2

1

2

C3745

1UF

10%

6.3V CERM

402

C3751

1UF

10%

6.3V CERM

402

1

2

1

2

1

C3746

10UF

20%

6.3V

2

X5R 603

C3750

1UF

6.3V CERM

PP3V3_T29_DP

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

10%

2

402

1

C3747

10UF

20%

6.3V

2

X5R 603

R3750

0

1 2

5% 1/16W MF-LF

402

R3760

0

1 2

5% 1/16W MF-LF

402

L3770

FERR-120-OHM-1.5A

1 2

0402

PP3V3_T29

135 mA (Single-Port) 152 mA (Dual-Port) EDP: 200 mA

0-ohms are placeholders for now, replace with proper values after characterization.

7

16 19 25 33 35 87

D

C

B

A

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T29_REF

PAGE TITLE

T29 Host (2 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=10/12/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

37 OF 132

SHEET

34 OF 101

36

345678

2 1

Page Notes

Power aliases required by this page:

- =PPVIN_SW_T29BST (8-13V Boost Input)

- =PP18V_T29_REG (18V Boost Output)

- =PP3V3_T29_P3V3T29FET (3.3V FET Input)

- =PP3V3_T29_FET (3.3V FET Output)

- =PP3V3_S0_T29PWRCTL

- =PP1V05_T29_P1V05T29FET (1.05V FET Input)

- =PP1V05_T29_FET (1.05V FET Output)

Signal aliases required by this page:

- =T29_CLKREQ_L

D

- =T29_RESET_L

BOM options provided by this page: T29BST:Y - Stuffs 18V boost circuitry.

C

12 16 17 18 19 20 22 23

Platform (PCIe) Reset

PLT_RST_BUF_L

25 32

IN

Open-Drain GPIO

T29_SW_RESET_L

19

IN

T29_CLKREQ_L

16

OUT

Pull-up provided by SB page.

Supervisor & CLKREQ# Isolation

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

C3800

0.1UF

2

R3803

10K

5% 1/16W MF-LF

402

1

10% 25V X5R 402

1

2

VDD

U3800

SLG4AP016V

TDFN

DLY

3

MR*

6

EN

8

OUT

(OD)

GND

5

1

CRITICAL

SENSE

+

-

RESET*

THRM

PAD

9

0.7V

SI8409DB:

CRITICAL T29BST:Y

Q3880

PPBUS_G3H

6 7 8

39 48 49 62 63 88

8-13V Input Changes required for 2S.

T29BST:Y

R3880

470K

1/16W MF-LF

T29BST:Y

R3881

330K

1/16W MF-LF

1

5%

402

2

1

5%

402

2

T29BST_PWREN_L

T29BST:Y

1

C3880

0.1UF

10% 25V

2

X5R 402

T29BST_PWREN_DIV_L

T29BST:Y

Q3805

SSM3K15FV

SOD-VESM-HF

1

T29_A_HV_EN

84 85

IN

PP3V3_T29

1

R3807

100K

5% 1/16W MF-LF 402

2

PP1V05_T29

2

4

7

IN

T29_RESET_L

DLY = 60 ms +/- 20%

T29_CLKREQ_ISOL_L T29_CLKREQ_ISOL_L

MAKE_BASE=TRUE

7

16 19 25 33 34 35 87

7

34 35

OUT

33 35

33

33 35

IN

G S

UVLO(falling) = 1.22 * (R1 + R2) / R2 UVLO(rising) = UVLO(falling) + (2uA * R1) UVLO = 4.55V (falling), 4.95 (rising)

SI8409DB

SGD

4

1

T29BST:Y

3

D

C3892

4.7UF

2

T29BST:Y

1

R3892

73.2K

1% 1/16W MF-LF 402

2

<R2>

Vds(max): -30V Vgs(max): +/-12V Vgs(th): -1.4V Rds(on): 46mOhm @ 4.5V Vgs Id(max): 3.7A @ 70C

BGA

32

PPVIN_SW_T29BST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

Voltage not specified here, add property on another page.

1

C3887

47PF

10% 10V X5R 805

5% 50V

22

CERM 402

T29BST_VC_RC

T29BST:Y

1

C3893

3300PF

10% 50V

2

X7R-CERM 0402

T29BST:Y

R3893

10K

1/16W MF-LF

T29BST:Y

R3894

T29BST:Y

1

1%

402

2

41.2K

1/16W MF-LF

402

R3891

200K

1/16W MF-LF

<R1>

1

1%

2

6

1

402

T29 15V Boost Regulator

T29BST:Y

C3890

1

1%

2

T29BST_EN_UVLO

T29BST_VC

T29BST_RT

T29BST_SS

T29BST:Y

1

C3894

0.33UF

10%

6.3V

2

CERM-X5R 402

GND_T29BST_SGND

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

T29BST:Y

D

Q3888

SSM6N37FEAPE

SOT563

S G

T29BST:Y

1

10UF

C3891

10% 25V X5R 805

10UF

2

T29BST_INTVCC

Max Vgs: 10V

2

T29BST_SHDN_DIV

T29BST:Y

1

R3887

330K

5% 1/16W MF-LF 402

2

1

10% 25V

2

X5R 805

25

28

30

33

32

34

T29BST:Y

1

R3888

330K

5% 1/16W MF-LF 402

2

T29BST:Y

3

D

Q3888

SSM6N37FEAPE

SOT563

S G

4

CRITICAL T29BST:Y

L3895

10UH-4A-68-MOHM

PCMB063T-100MS

9

CRITICAL T29BST:Y

U3890

LT3957

QFN

372423

8

GND

27

VIN

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SGND

4

SGND shorted to GND inside package, no XW necessary.

5

SMC_DELAYED_PWRGD

21

T29BST_BOOST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE DIDT=TRUE

38

21

20

SW

SNS1

SNS2

NC

FBX

17

1615141312

Vout = 1.6V * (1 + Ra / Rb)

T29BST_SNS1

T29BST:Y

6

3

1 2 10

NC

35 36

31

T29BST_SNS2

T29BST_VSNS

1

C3888

10PF

5% 50V

2

CERM 402

T29BST_FBX

NO STUFF

1

C3889

100PF

5% 50V

2

CERM 402

R3889

1/16W MF-LF

XW3895

T29BST:Y

R3895

<Ra>

T29BST:Y

R3896

15.8K

<Rb>

1

0

5%

402

2

SM

2 1

137K

1/16W MF-LF

402

1/16W MF-LF

402

CRITICAL T29BST:Y

1

D3895

POWERDI-123

DFLS230L

2

PLACE_NEAR=C3895.1:2 mm

1

1%

2

T29BST:Y

1

C3895

4.7UF

10% 50V

2

X7R-CERM

1

1206

1%

T29BST:Y

C3896

2

4.7UF

X7R-CERM

1206

D

PP15V_T29

T29BST:Y

1

C3897

4.7UF

10% 50V

2

X7R-CERM 1206

T29BST:Y

1

C3898

10% 50V

4.7UF

2

X7R-CERM

Vout = 15V Max Current = 0.8A Freq = 300KHz

T29BST:Y

1

C3899

0.001UF

10% 50V

2

X7R 402

1206

10% 50V

7 8

85

C

44 89

IN

B

72 79 82 83 84 47 48 49 50 51 25 26 28 32 35

PP3V3_S0

6 7

12 16 17

18 19 20 22 23 36 39 40 41 45 53 56 60 61 71 87 88 89 98

C3810

1UF

10%

6.3V CERM

402

3.3V T29 Switch

U3810

TPS22924

CSP

A2 B2

1

C2

2

VIN

CRITICAL

ON

GND

C1

VOUT

PP3V3_T29

A1

Max Current = 1.7A (85C)

B1

U3810 & U3815/U3816

Part

Type

R(on)

7

16 19 25 33 34 35 87

TPS22924C

Load Switch

18 mOhm Typ 50 mOhm Max

B

Max Output: 2A per IC

1.05V T29 Switch

44 67 69 72

101

10 12 13 14 16

PP1V05_S0

6 7 9 17 20 22 23 39

C3815

1UF

6.3V CERM

1

10%

2

402

A

T29_PWR_EN

19

IN

Pull-up provided by SB page.

8 7 5 4 2 1

U3815

TPS22924

CSP

VOUT

VIN

B2 B1

CRITICAL

C2

ON

GND

C1

U3816

TPS22924

CSP

A2 B2

C2

VIN

CRITICAL

ON

GND

C1

VOUT

PP1V05_T29

A1A2

Max Current = 3.4A (85C)

A1 B1

U3816.A2:

PLACE_NEAR=U3815.B2:3 mm

7

34 35

SIZE

A

D

SYNC_MASTER=T29_REF

PAGE TITLE

T29 Power Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=10/12/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

38 OF 132

SHEET

35 OF 101

36

345678

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below. If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY. If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

Special Star routing needed on these pins. Decoupling on Pg 37.

PP3V3_ENET

6 7

25 36 70 72

281mA (1000base-T max power, Caesar IV)

CRITICAL

L3900

FERR-600-OHM-0.5A

D

CRITICAL

L3905

FERR-600-OHM-0.5A

CRITICAL

L3910

FERR-600-OHM-0.5A

1

48 49 50 51 53 56 60 61 71 72

PP3V3_S0

6 7

C

PCIE_ENET_D2R_N

16 93

OUT

PCIE_ENET_D2R_P

16 93

OUT

PCIE_ENET_R2D_C_P

16 93

IN

PCIE_ENET_R2D_C_N

16 93

IN

ENET_WAKE_L

25

OUT

(See note)

WAKE#

Must isolate from PCIe WAKE# if PHY is powered-down in S3/S5. Standard N-channel FET isolation suggested.

B

If PHY is always powered then alias =ENET_WAKE_L to PCIE_WAKE_L.

12 16 17 18 19 20 22 23

25 26 28 32 35 39 40 41 45 47 79 82 83 84 87 88 89 98

C3950

C3955

0.1uF

R3943

0.1uF

10% 16V X5R 402

0

5% 1/16W MF-LF

402

21

C3951

0.1uF

10% 16V X5R 402

C3956

0.1uF

10% 16V X5R 402

21

PP3V3_S3_ENET_PHY_XTALVDDH

SM

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

21

PP3V3_S3_ENET_PHY_BIASVDDH

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

2

PP3V3_S3_ENET_PHY_AVDDH

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

R3941

4.7K

5%

1/16W MF-LF 402

402

2

ENET_VMAIN_PRSNT

PCIE_ENET_D2R_C_N

93

PCIE_ENET_D2R_C_P

93

PCIE_ENET_R2D_P

93

PCIE_ENET_R2D_N

93

PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N

ENET_RESET_L

ENET_CLKREQ_L

1

R3942

1K

5% 1/16W MF-LF 402

2

R3940

4.7K

1/16W MF-LF

Current Limiting Resistor

16 93

IN

16 93

IN

32 94

IN

16

OUT

C3900

X7R-CERM

R3910

4.7K

1/16W MF-LF

0.1UF

1

5%

402

2

10% 16V

402

C3915

4.7UF

X5R-CERM

ENET_WAKE_R_L

19 32

IN

BCM57765_SCLK

36

BCM57765_MISO

36

BCM57765_MOSI

36

BCM57765_CS_L

36

TP_BCM57765_SPD100LED_L TP_BCM57765_TRAFFICLED_L

25

IN

ENET_LOW_PWR

BCM57765_SMB_CLK BCM57765_SMB_DATA

SYSCLK_CLK25M_ENET

BCM57765_RDAC

1

R3965

1.24K

1% 1/16W MF-LF 402

2

6 7

25 36 70 72

PHY Non-Volatile Memory

ROM contains MAC address, PCIe config info as well as code for Bonjour proxy. Required for proper PHY operation.

PP3V3_ENET

(Required ROM size TBD)

VDD for Card Reader I/O

PP3V3R1V8_ENET_LR_OUT_REG

36

1

2

1

C3905

0.1UF

10% 16V

2

X7R-CERM 402

10%

6.3V 603

1

2

C3910

0.1UF

10% 16V X7R-CERM 402

1

2

1

2

1

C3916

0.1UF

10% 16V

2

X7R-CERM 402

C3911

0.1UF

10% 16V X7R-CERM 402

58

VMAIN_PRSNT

27

PCIE_TXD_N

28

PCIE_TXD_P

33

PCIE_RXD_P

34

PCIE_RXD_N

31

PCIE_REFCLK_P

30

PCIE_REFCLK_N

11

PERST*

12

CLKREQ*

3

WAKE*

4

LOW_PWR

6

SMB_CLK

10

SMD_DATA

66

SCLK

64

SI/LINKLED*

65

SO

63

CS*

2

SPD100LED*/SERIAL_DO

67

TRAFFICLED*/SERIAL_DI

18

XTALI

19

XTALO

NC

38

RDAC

ENET_SR_LX

PP1V2_ENET

13

42

AVDDH

48

17

37

XTALVDDH

BIASVDDH

206256

7

VDDO

151416

SR_VDD

SR_VDDP

SR_LX

AVDDL

SR_VFB

OMIT

(IPD)

(OD)

SD_DETECT can only be used active low due to errata.

(IPD)

U3900

BCM57765B0

QFN-8X8

NOTE: "IPx" == Programmable pull-up/down

(IPU)

(OD) (OD)

THRM_PAD

69

70

Internal 1.2V Switching Regulator pins.

6 7

36 70

PP1V2_ENET_PHY_AVDDL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

1

C3920

4.7UF

10%

6.3V

2

X5R-CERM 603

PP1V2_ENET_PHY_PCIEPLL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

1

C3925

4.7UF

10%

6.3V

2

X5R-CERM 603

PP1V2_ENET_PHY_GPHYPLL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

1

C3930

4.7UF

10%

6.3V

2

X5R-CERM 603

CRITICAL

1

C3935

10UF

10%

6.3V

2

X5R 805

ENET_MDI_P<0> ENET_MDI_N<0> ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3>

TP_CE_L_MS_INS_L ENET_CR_PWREN

BDM57765_SR_DISABLE

32

29

514539

PCIE_PLLVDDL

GPIO_1/CR_BUS_PWR

(IPD)

SD_DETECT/WE*

(IPx)

(IPU)

CR_CLK/RY_BY*

(IPU)

CE*/MS_INS*

(IPU)

CR_WP*/XD_WP*

C3921

0.1UF

X7R-CERM

C3926

0.1UF

X7R-CERM

C3931

0.1UF

X7R-CERM

61

35

36

VDDC

GPHY_PLLVDDL

TRD0_P TRD0_N TRD1_P TRD1_N TRD2_P TRD2_N TRD3_P TRD3_N

GPIO_0

RE*/GPIO_2

CR_CMD/CLE

CR_DATA0 CR_DATA1 CR_DATA2 CR_DATA3 CR_DATA4 CR_DATA5 CR_DATA6 CR_DATA7

CR_LED/ALE

XD_DETECT

10% 16V

402

10% 16V

402

10% 16V

402

C3936

X7R-CERM

40 41 44 43 46 47 50 49

5 8 9

1

o

26

21

25 24 23 22 52 53 54 55

59 60 57 68

1

2

1

2

1

2

0.1UF

NC

10% 16V

402

BCM57765 supports both active-levels for WP.

CRITICAL

FERR-600-OHM-0.5A

CRITICAL

FERR-600-OHM-0.5A

CRITICAL

FERR-600-OHM-0.5A

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for the card reader on-chip I/O. Connect only to U3900 pin 20.

37 94

BI

37 94

BI

37 94

BI

37 94

BI

37 94

BI

37 94

BI

37 94

BI

37 94

BI

No MS (Memory Stick) Insert feature needed. Control signal to light LED or control SD bus power.

32

OUT

R3980

1K

L3920

SM

L3925

SM

L3930

SM

1

C3970

4.7UF

10%

6.3V

2

X5R-CERM 603

SR_DISABLE must be pulled down to use internal SR. IPD has a race condition.

PP1V2_ENET

21

5% 402

1/16W

2 1

6 7

???mA (1000base-T, Caesar V)

1

C3971

0.1UF

10% 16V

2

X7R-CERM 402

MF-LF

36 70

PP3V3R1V8_ENET_LR_OUT_REG

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C3972

0.1UF

10% 16V

2

X7R-CERM 402

ENET_MEDIA_SENSE

SDCONN_DETECT_L

SDCONN_CMD

SDCONN_CLK

SDCONN_DATA<0> SDCONN_DATA<1> SDCONN_DATA<2> SDCONN_DATA<3> SDCONN_DATA<4> SDCONN_DATA<5> SDCONN_DATA<6> SDCONN_DATA<7>

SDCONN_WP

D

C

36

25

OUT

32

IN

32 94

IN

32 94

OUT

32 94

BI

32 94

BI

32 94

BI

32 94

BI

32 94

BI

32 94

BI

32 94

BI

32 94

BI

32

IN

B

6

VCC

U3990

AT45DB011D

4

5

3

SCK

CS*

WP*

RESET*

SOIC-8S1

OMIT

GND

7

SI

SO

BCM57765_SCLK

A

36

BCM57765_CS_L

36

8 7 5 4 2 1

1

C3990

0.1UF

10% 16V

2

X7R-CERM 402

12

8

NOSTUFF

1

R3990

4.7K

5% 1/16W MF-LF 402

2

BCM57765_MOSI

BCM57765_MISO

1

R3997

4.7K

5% 1/16W MF-LF 402

2

NOTE: Pull-down on SO plus internal pull-ups on other 3 SPI pins configures ENET for the Atmel AT45DB011D (1Mbit) ROM. If a different ROM is used then the straps must change. NOTE: ENETM requires SI pull-down instead of SO.

36

PAGE TITLE

ETHERNET PHY (CAESAR IV)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=10/11/2010SYNC_MASTER=K91_ERIC

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

39 OF 132

36 OF 101

SIZE

A

D

36

Page Notes

Power aliases required by this page: (NONE)

Signal aliases required by this page: (NONE)

BOM options provided by this page: (NONE)

345678

2 1

D

Place one of 0.1uf cap close to each centertap pin of transformer

D

ENETCONN_CTAP

1

C4000

0.1UF

10% 16V

2

X5R 402-1

1

C4002

0.1UF

10% 16V

2

X5R 402-1

1

C4004

0.1UF

10% 16V

2

X5R 402-1

1

C4006

0.1UF

10% 16V

2

X5R 402-1

CRITICAL

T4000

ENET_MDI_P<0>

36 94

BI

36 94

BI

C

ENET_MDI_N<1>

36 94

BI

ENET_MDI_P<1>

36 94

BI

ENET_MDI_N<2>

36 94

BI

ENET_MDI_P<2>

36 94

BI

ENET_MDI_N<3> ENETCONN_N<3>

36 94

BI

ENET_MDI_P<3>

36 94

BI

Transformers should be mirrored on opposite sides of the board

1

2

3

4

5

6 7

1

2

3

4

5

6 7

B

SM

TX

TLA-6T213HF

RX

CRITICAL

T4001

SM

TX

TLA-6T213HF

RX

12

ENETCONN_P<0>

98

11

ENETCONN_N<0>ENET_MDI_N<0>

98

10

ENET_CTAP0

9

ENET_CTAP1

8

ENETCONN_N<1>

98

ENETCONN_P<1>

98

12

ENETCONN_N<2>

98

11

ENETCONN_P<2>

98

10

ENET_CTAP2

9

ENET_CTAP3

8

98

ENETCONN_P<3>

98

R4000

75

5% 1/16W MF-LF

402

1

R4001

1/16W MF-LF

2

75

402

CRITICAL

J4000

RJ45-M97-3

F-RT-TH

9

10

1

2

3

4

5

6

7

8

11

12

514-0636

1

R4002

75

5%

5% 1/16W MF-LF 402

2

1

R4003

75

5% 1/16W MF-LF 402

2

ENET_BOB_SMITH_CAP

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

CRITICAL

C4008

1000PF

1 2

10%

2KV CERM 1206

C

B

5 421679

IONCNC

IO

NC

D4001

RCLAMP0524P

SLP2510P8

CRITICAL

NOSTUFF

PLACE_NEAR=T4001.1:5mm

10

IONCIO

GND

3

5 421679

IONCNC

IO

NC

D4000

RCLAMP0524P

SLP2510P8

CRITICAL

NOSTUFF

A

8 7 5 4 2 1

PLACE_NEAR=T4000.5:5mm

10

IONCIO

GND

3

SIZE

A

D

SYNC_MASTER=K91_TRINHNI

PAGE TITLE

Ethernet Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=05/26/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

40 OF 132

SHEET

37 OF 101

36

345678

2 1

7 mA I/O

1

C4120

1UF

10%

6.3V 2

CERM

402

D

L4110

PP1V0_FW_FWPHY

6 7

39

135 mA

R4100

0

1 2

5% 1/16W MF-LF

402

PP1V0_FW_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V

120-OHM-0.3A-EMI

1 2

0402-LF

110 mA Digital Core

1

C4100

1UF

10%

6.3V

2

CERM 402

1

C4101

1UF

10%

6.3V

2

CERM 402

PP1V0_FW_FWPHY_AVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V

1

C4102

1UF

10%

6.3V

2

CERM 402

1

C4103

1UF

10%

6.3V

2

CERM 402

1

C4104

1UF

10%

6.3V

2

CERM 402

25 mA PCIe SerDes

1

C4110

1UF

10%

6.3V

2

CERM 402

1

C4105

1UF

10%

6.3V

2

CERM 402

1

C4111

1UF

10%

6.3V

2

CERM 402

1

C4106

1UF

10%

6.3V

2

CERM 402

C4121

1UF

6.3V CERM

C4130

1UF

6.3V CERM

1

C4122

10%

2

402

114 mA FireWire PHY

1

C4131

10%

2

402

17 mA PCIe SerDes

C4135

1

1UF

10%

6.3V 2

CERM

402

1

1UF

10%

6.3V 2

CERM

402

1

1UF

10%

6.3V 2

CERM

402

0 mA VReg PWR

C4141

C4123

C4132

C4136

0.1UF

CERM

20% 10V

402

1

C4124

1UF

10%

6.3V 2

CERM

402

PP3V3_FW_FWPHY_VDDA

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

1

1UF

10%

6.3V 2

CERM

402

PP3V3_FW_FWPHY_VP25

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

1

1UF

10%

6.3V 2

CERM

402

1

C4140

1UF

10%

6.3V

2

CERM 402

1UF

10%

6.3V CERM

402

1

2

L4130

120-OHM-0.3A-EMI

1 2

0402-LF

L4135

120-OHM-0.3A-EMI

1 2

0402-LF

PP3V3_FW_FWPHY

C

C4170

A1

B1

B12

C13E2E10H2H12K2L1

NT-OUT

NOTE: NT-xx notes show NAND tree order.

(IPD) NT-18

(IPU)

(IPD) NT-11

(IPU) NT-8

(Reserved)

D4

D10

VDD10

E4E5E9F4F6

B13

ATBUSB

NC

A13

ATBUSH

NC

A11

ATBUSN

NC

FWPHY_DS0

40

IN

FWPHY_DS1

40

IN

FWPHY_DS2

40

IN

NC_FW0_TPAN

40 94

BI

NC_FW0_TPAP

6

40 94

BI

FW_PORT1_TPA_N

40 94

BI

FW_PORT1_TPA_P

40 94

BI

NC_FW2_TPAN

6

40

BI

NC_FW2_TPAP

6

40

BI

NC_FW0_TPBN

6

40 94

BI

NC_FW0_TPBP

6

40 94

BI

FW_PORT1_TPB_N

40 94

BI

FW_PORT1_TPB_P

40 94

BI

NC_FW2_TPBN

6

40

PPVP_FW_CPS

40

1

R4160

B

PLACE_NEAR=U4100.B10:2mm

C4150

22PF

1 2

5%

50V

CERM

402

C4151

22PF

1 2

5%

50V

CERM

402

NC NC

13

2 4

FW_CLK24P576M_XO CRITICAL

Y4150

24.576MHZ

SM-3.2X2.5MM

R4150

412

1 2

1% 1/16W MF-LF

402

200K

1% 1/16W MF-LF

402

2

R4161

2.94K

1/16W MF-LF

402

R4162

470K

1/16W MF-LF

402

1

R4170

191

1%

1/16W MF-LF 402

2

1

C4162

0.33UF

5%

10%

6.3V

2

CERM-X5R 402

2

BI

NC_FW2_TPBP

6

40

BI

NC_FW0_TPBIAS

40

BI

FW_P1_TPBIAS

39 40

BI

NC_FW2_TPBIAS

6

40

BI

FW643_R0 FW643_TPCPS

TP_FW643_NAND_TREE

6

FW643_REXT FW_CLK24P576M_XO_R FW_CLK24P576M_XI

TP_FW643_SE

6

TP_FW643_SM

6

TP_FW643_MODE_A TP_FW643_CE

6

TP_FW643_FW620_L

6

TP_FW643_JASI_EN

6

NC_FW643_AVREG

6

TP_FW643_VBUF

6

FW643_PU_RST_L

TP_FW643_OCR10_CTL

6

F12

DS0

(IPD) NT-19

E12

DS1

(IPD) NT-20

E13

DS2

(IPD) NT-21

B8

TPA0N

A8

TPA0P

B5

TPA1N

A5

TPA1P

B3

TPA2N

A3

TPA2P

B9

TPB0N

A9

TPB0P

B6

TPB1N

A6

TPB1P

B4

TPB2N

A4

TPB2P

B7

TPBIAS0

C3

TPBIAS1

A2

TPBIAS2

B11

R0

B10

TPCPS

K1

NAND_TREE

L8

REXT

F13

XO

G13

XI

NT-9

M13

SE

(IPD)

N13

SM

(IPD)

J2

MODE_A

L13

CE

(IPD)

D12

FW620*

D1

JASI_EN

A10

AVREG

H13

VBUF

K13

FW_RESET*

J12

OCR_CTL_V10

J13

OCR_CTL_V12

NC

B2

M12N3N11

MISCELLANEOUS

F7

F8

F10

C1

C12F1G12J1L3

1394 PHY

G4G6G7

VDD33

OMIT

CRITICAL

U4100

FW643

VSS

G8

H4

G10

BGA

H6D7H7

L11M2A12D5D6D8L5

VDDH

PCI EXPRESS PHY

TEST CONTROLLER

FIXME!!! - TYPO IN SYMBOL REGCTL

POWER MANAGEMENT

NT-12 (IPD)

SCIF

SERIAL EEPROM CONTROLLER

CHIP RESET

H8

J4J5J9

H10

J10

L10L6L9

VP25

VP

NT-10 (IPD)

NT-13

NT-16 (IPD) NT-14 (IPD)

NT-15 (IPD)

K4K5K7D9K8K9L7

K12

VREG_PWR

NT-2 (IPU)

NT-17

K6

PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N PCIE_TXD0P

REFCLKN REFCLKP

NT-4 (IPU) NT-3 (IPU)

(IPU)

NT-1 (IPU)

VAUX_DETECT

VAUX_DISABLE

CLKREQN

(OD)

SCIFCLK SCIFDAIN SCIFDOUT

NT-7 NT-6

NT-5

VREG_VSS

K10

L12

TCK TDI TDO TMS

TRST*

WAKE*

REGCLT

SCIFMC

SCL SDA

PERST*

N8 N7 N5 N6

N9 N10

M4 N2 M1 M3

N1

C2 D13 E1 D2 L2

G2 G1 H1 F2

N12 M11

N4

PCIE_FW_R2D_N

93

PCIE_FW_R2D_P

93

PCIE_FW_D2R_C_N

93

PCIE_FW_D2R_C_P

93

PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P

TP_FW643_TCK NC_FW643_TDI TP_FW643_TDO TP_FW643_TMS

FW643_TRST_L

FW643_WAKE_L FW643_REGCTL FW643_VAUX_DETECT TP_FW643_VAUX_ENABLE FW_CLKREQ_PHY_L

TP_FW643_SCIFCLK TP_FW643_SCIFDAIN TP_FW643_SCIFDOUT TP_FW643_SCIFMC

FW643_SCL TP_FW643_SDA

FW_RESET_L

1

R4163

10K

5% 1/16W MF-LF 402

2

16 93

IN

16 93

IN

6

8

39

OUT

6

39

OUT

6

39

IN

0.1UF

C4171

0.1UF

C4175

0.1UF

C4176

0.1UF

1 2

402-1

X5R 10%

1 2

X5R

402-1

10%

1 2

402-1

X5R 10%

1 2

402-1

X5R

FW643_LDO

R4165

1

R4164

10K

5% 1/16W MF-LF 402

2

6 7

38 39 40

138 mA

PLACE_NEAR=U1800.AV34:2.54mm

16V10%

PCIE_FW_R2D_C_N

PLACE_NEAR=U1800.AU34:2.54mm

16V

PCIE_FW_R2D_C_P

PLACE_NEAR=U1800.BG36:2.54mm

16V

PCIE_FW_D2R_N

PLACE_NEAR=U1800.BJ36:2.54mm

16V

PCIE_FW_D2R_P

PP3V3_FW_FWPHY

1

402

R4166

10K

5%

5% 1/16W MF-LF 402

2

10K

1/16W MF-LF

D

C

16 93

IN

16 93

IN

16 93

OUT

16 93

OUT

6 7

38 39 40

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K18_MLB

PAGE TITLE

FireWire LLC/PHY (FW643)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

41 OF 132

SHEET

38 OF 101

SIZE

A

D

345678

2 1

Page Notes

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (FW VP FET Input)

- =PPBUS_FW_FET (FW VP FET Output)

- =PP3V3_FW_P3V3FWFET (3.3V FET Input)

- =PP3V3_FW_FET (3.3V FET Output)

- =PP3V3_FW_FWPHY (PHY 3.3V Power)

- =PP3V3_S0_FWLATEVG

- =PP3V3_S0_FWPWRCTL

- =PP1V05_S0_FWPWRCTL (5KPD Bias Rail)

- =PP1V05_FW_P1V0FWFET (1.0V FET Input)

- =PP1V0_FW_FET_R (1.0V FET Output)

D

- =PP1V0_FW_FWPHY (PHY 1.0V)

Signal aliases required by this page:

- =FW_CLKREQ_L

- =FW_PME_L

BOM options provided by this page: (NONE)

C

69 72

101

PP1V05_S0

6 7 9

10 12 13 14 16

17 20 22 23 35 39 44 67

R4275

FW_PWR_EN

19 39

IN

B

A

8 7 5 4 2 1

2

G

1/16W MF-LF

402

1

1K

5%

2

6

D

S

1

PPBUS_G3H

6 7 8

35 48 49 62 63 88

1

R4262

10K

5% 1/16W MF-LF

402

2

1

R4263

10

5% 1/16W MF-LF

402

2

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

FireWire Port 5K Pull-Down Detect

All FireWire devices require 5K pull-down on TPB pair. Host can detect as load on TPBIAS signal. Current source only active when FW_PWR_EN is low.

FW_PWR_EN_L

CRITICAL

Q4275

DMB53D0UV

SOT-563

CRITICAL

Q4270

BC847CDXV6TXG

SOT563

1

R4270

330K

5% 1/16W MF-LF 402

2

3

5

4

FW_P1_TPBIAS_R

PLACE_NEAR=C4360.1:2 mm

FW_P1_TPBIAS

38 40

IN

FWDET_MIRROR

1

R4272

1K

5% 1/16W MF-LF

402

2

R4271

56K

1/16W MF-LF

2

1

5%

402

2

FW_5KPD_DET_RC

CRITICAL

6

Q4270

BC847CDXV6TXG SOT563

1

FWDET_EMIT

R4273

FireWire PHY WAKE# Support

When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.

PP3V3_FW_FWPHY

6 7

38 39 40

R4277

1/16W MF-LF

8

38 39

FW643_WAKE_L

IN

FW643_WAKE_L

MAKE_BASE=TRUE

FireWire Port Power Switch

Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)

1

R4260

300K

5%

1

1/16W MF-LF 402

2

FWPORT_PWREN_L_DIV

1

R4261

470K

5% 1/16W MF-LF 402

2

FWPORT_PWREN_L

3

D

G S

2

OUT

8

19

FWPORT_FASTOFF_L_DIV

FWPORT_FASTOFF_L

FWPORT_PWR_EN

40

IN

0.1UF

1

2

1

10% 16V

2

X5R 402

G

2

1/16W MF-LF

10K

402

12K

402

5%

C4270

5%

1

2

5

1

R4276

100K

5% 1/16W MF-LF 402

2

FW_WAKE

6

D

S

1

Q4276

5

6

D

G

2

S

1

FW_5KPD_DET_L

MAKE_BASE=TRUE

CRITICAL

3

Q4275

DMB53D0UV

SOT-563

4

NO STUFF

C4276

0.1UF

10% 16V X5R 402

CRITICAL

DMB53D0UV

SOT-563

G

CRITICAL

Q4262

BSS8402DW

SOT-363

(SYM-VER1)

SSM3K15FV

1

2

4

(SYM-VER2)

SOT-363

S

BSS8402DW

Q4262

CRITICAL

D

3

CRITICAL

Q4261

SOD-VESM-HF

Dual-purpose output:

1) 5K Pull-down Detect when FW_PWR_EN is low.

2) FW643 WAKE# (PME#) when PHY is powered.

FW_PLUG_DET_L

Pull-up provided on another page. CRITICAL

3

Q4276

5

DMB53D0UV

SOT-563

4

NO STUFF

C4261

0.1UF

C4260

0.1UF

1

10% 25V

2

X5R 402

10% 25V X5R 402

1

2

CRITICAL

Q4260

FDC638P_G

4

CRITICAL

SM

6

PPBUS_FW_FWPWRSW_F

MIN_LINE_WIDTH=0.5 mm

5

MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

2

1

3

F4260

1.1A-24V

1 2

MINISMDC110H24

PPBUS_FW_FWPWRSW_D

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

CRITICAL

D4260

SM

1 2

CRS08-1.5A-30V

PPVP_FW

6 7

40

D

Supervisor & CLKREQ# Isolation

PP3V3_FW_FWPHY

6 7

1

2

38 39 40

VDD

U4290

SLG4AP016V

TDFN

DLY

3

MR*

6

EN

8

OUT

(OD)

GND

5

1

CRITICAL

SENSE

+

-

RESET*

THRM

PAD

9

0.7V

1

R4290

100K

5% 1/16W MF-LF 402

2

4

7

IN

PP1V0_FW_FWPHY

FW_RESET_L

DLY = 60 ms +/- 20%

FW_CLKREQ_PHY_L FW_CLKREQ_PHY_L

MAKE_BASE=TRUE

6 7

OUT

38 39

38

38 39

IN

C

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

PLT_RESET_L

18 25 29

IN

2

R4283

10K

5% 1/16W MF-LF 402

1

FW_RESET_R_L

FW_PWR_EN

19 39

IN

FW_CLKREQ_L

16 23

OUT

Pull-up provided by another page.

C4290

0.1UF

10% 25V X5R 402

3.3V FW Switch

U4201

17 19 20 22 23 24 25 29

PP3V3_S5

6 7 45 55 65 70 71 72 82 85 89 98

C4201

1UF

6.3V CERM

1

10%

2

402

TPS22924

A2

VIN

B2

CRITICAL

C2

ON

CSP

VOUT

GND

C1

1.0V FW Switch

U4202

PP1V05_S0

6 7 9

10 12 13 14 16 17 20 22 23 35 39

44 67 69 72

101

1

C4202

1UF

10%

6.3V 2

CERM

402

TPS22924

A2

VIN

B2

CRITICAL

C2

ON

CSP

VOUT

GND

C1

PP3V3_FW_FWPHY

A1

Max Current = 1.7A (85C)

B1

6 7

38 39 40

U4201 & U4202

Part

Type

R(on)

Max Output: 2A

PP1V05_FW_FET

MIN_LINE_WIDTH=0.4 mm

A1

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

B1

1

R4202

0.549

1% 1/16W MF 402

2

PP1V0_FW_FWPHY

SYNC_MASTER=T27_REF

PAGE TITLE

LSI FireWire PHY requires 1.0V. To avoid an extra power supply,

1.05V is used with a series R to reduce voltage.

FireWire Port & PHY Power

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

6 7

38 39

TPS22924C

Load Switch

18 mOhm Typ 50 mOhm Max

SYNC_DATE=06/10/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

42 OF 132

39 OF 101

SIZE

B

A

D

36

345678

2 1

Page Notes

Power aliases required by this page:

- =PPVP_FW_PORT1

- =PPVP_FW_PHY_CPS_FET (From Port)

- =PPVP_FW_PHY_CPS (To PHY)

- =PP3V3_FW_FWPHY

- =PP3V3_S0_FWLATEVG

Signal aliases required by this page:

- =FW_PHY_DS0

- =FW_PHY_DS1

- =FW_PHY_DS2

D

NOTE: This page is expected to contain the necessary aliases to map the FireWire TPA/TPB pairs to their appropriate connectors and/or to properly terminate unused signals.

BOM options provided by this page: (NONE)

1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)

C

FW643 TPCPS Leakage Protection

FW643 has internal leakage path from TPCPS pin to VDD33. FET blocks current to TPCPS until VDD33 is powered.

BSS8402DW

SOT-363

Q4300

(SYM-VER2)

6 7

39 40

38 39 40

From Port

PPVP_FW

PP3V3_FW_FWPHY

6 7

R4311

470K

1/16W MF-LF

402

4

1

5%

2

G

2

CRITICAL

SGD

5

CPS_EN_L_DIV

CPS_EN_L

6

CRITICAL

D

Q4300

BSS8402DW

SOT-363

S

(SYM-VER1)

1

3

R4312

PPVP_FW_CPS

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE

PPVP_FW_CPS

1

330K

5% 1/16W MF-LF

402

2

To FW643

38 40

Unused FireWire Ports

Disabled per LSI instructions (All unused port signals TP/NC)

38 40

IN

6

38 40 94

BI

38 40 94

BI

6

38 40 94

BI

6

38 40 94

BI

6

38 40

IN

6

38 40

BI

6

38 40

BI

6

38 40

BI

6

38 40

BI

NC_FW0_TPBIAS

NC_FW0_TPAP

NC_FW0_TPAN

NC_FW0_TPBP

NC_FW0_TPBN

NC_FW2_TPBIAS

NC_FW2_TPAP

NC_FW2_TPAN

NC_FW2_TPBP

NC_FW2_TPBN

NC_FW0_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPAP

MAKE_BASE=TRUE

NC_FW0_TPAN

MAKE_BASE=TRUE

NC_FW0_TPBP

MAKE_BASE=TRUE

NC_FW0_TPBN

MAKE_BASE=TRUE

NC_FW2_TPBIAS

MAKE_BASE=TRUE

NC_FW2_TPAP

MAKE_BASE=TRUE

NC_FW2_TPAN

MAKE_BASE=TRUE

NC_FW2_TPBP

MAKE_BASE=TRUE

NC_FW2_TPBN

MAKE_BASE=TRUE

NO_TEST=TRUE

38 40

6

38 40 94

6

38 40 94

6

38 40 94

6

38 40

6

38 40

6

38 40

6

38 40

6

38 40

FireWire PHY Config Straps

Configures PHY for:

- Port "1" Bilingual (1394B) PP3V3_FW_FWPHY

6 7

38 39 40

1

1%

402

2

38 40

40 38

1

R4380

10K

1% 1/16W MF-LF 402

2

FWPHY_DS0

MAKE_BASE=TRUE

FWPHY_DS1

38 40

MAKE_BASE=TRUE

FWPHY_DS2

MAKE_BASE=TRUE

1

R4381

10K

1% 1/16W MF-LF 402

2

R4382

10K

1/16W MF-LF

FWPHY_DS0

FWPHY_DS1

FWPHY_DS2

38 40

OUT

38 40

OUT

38 40

OUT

D

C

Termination

Place close to FireWire PHY

FW_P1_TPBIAS

38 39

IN

B

FW_PORT1_TPA_P

38 40 94

BI

FW_PORT1_TPA_N

38 40 94

BI

FW_PORT1_TPB_P

38 40 94

BI

FW_PORT1_TPB_N

38 40 94

BI

A

1

C4360

0.33UF

10%

6.3V

2

CERM-X5R 402

SIGNAL_MODEL=EMPTY

1

R4360

56.2

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

1

R4362

56.2

1% 1/16W MF-LF 402

2

FW_PORT1_TPB_C

1

C4364

220pF

5% 25V

2

CERM 402

R4361

56.2

1/16W MF-LF

R4363

56.2

1/16W MF-LF

R4364

4.99K

1/16W MF-LF

402

(FW_PORT1_TPB_N)

(FW_PORT1_TPB_P)

"Snapback" & "Late VG" Protection

48 49 50 51 53 56 60 61 71 72

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 41 45 47

1

1%

2

40 94

FW_PORT1_TPA_P

38

MAKE_BASE=TRUE

40 94

FW_PORT1_TPA_N

38

MAKE_BASE=TRUE

40 94

FW_PORT1_TPB_P

38

MAKE_BASE=TRUE

40 94

FW_PORT1_TPB_N

38

MAKE_BASE=TRUE

1

1%

2

1

1%

2

79 82 83 84 87 88 89 98

PLACE_NEAR=U4350.1:2 mm

TP_FWLATEVG_VCLMP

FWPORT_PWR_EN

39

OUT

(FW_PORT1_TPA_N)

(FW_PORT1_TPA_P)

C4350

0.1UF

R4350

100K

1/16W MF-LF

402

1

10% 16V

2

X5R 402

1

5%

2

TPD4S1394

3

VCLMP

4

FWPWR_EN

Cable Power

6 7

39 40

1

VCC

U4350

LLP

CRITICAL

GND

2

PPVP_FW

8

D1+

7

D1-

6

D2+

5

D2-

PLACE_NOTE=J4310.5:2 mm

8 7 5 4 2 1

CRITICAL

L4310

FERR-250-OHM

1 2

SM

1

C4314

0.01UF

10% 50V

2

X7R 402

C4319

0.1uF

603-1

1

R4319

1M

5% 1/16W MF-LF 402

2

Note: Trace PPVP_FW_PORT1 must handle up to 5A PPVP_FW_PORT1_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

PORT 1

BILINGUAL

CRITICAL

J4310

1394B-M97

F-RT-TH

TPB-

(FW_PORT1_TPB_N) (FW_PORT1_BREF) (FW_PORT1_TPB_P)

(GND) (FW_PORT1_TPA_N)

FW_PORT1_AREF

(FW_PORT1_TPA_P)

PLACE_NEAR=J4310.5:2 mm

1

10% 50V

2

X7R

1 9 2 8 7

NC

6

TPA-

3 5

TPA+

4

10 11

CHASSIS

12

GND

13

514S0605

AREF needs to be isolated from all local grounds per 1394b spec

When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue)

BREF should be hard-connected to logic ground for speed signaling and connection

36

TPB(R)

VPTPB+

SC/NC

VG

TPA(R)

TPB-

TPB<R>

TPB+

VP

NC

VG

TPA-

TPA<R>

TPA+

OUTPUT

INPUT

SYNC_MASTER=T27_REF

PAGE TITLE

FireWire Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=06/10/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

43 OF 132

SHEET

40 OF 101

SIZE

B

A

D

345678

SATA ODD Connector

2 1

D

100

NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.

C

19

IN

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

SSM6N15FEAPE

ODD_PWR_EN_L

R4597

CRITICAL

Q4596

SOT563

5

100K

1/16W MF-LF

402

1

5%

2

3

D

SG

4

SATA HDD / IR / SIL Connector

100

B

A

8 7 5 4 2 1

29 31 41 42 43 45 65 66 71 81

ODD Power Control

PP5V_S3

6 7

29 31 41 42 43 45 65 66 71 81

1

R4596

100K

5% 1/16W MF-LF

402

2

ODD_PWR_EN_LS5V_L

SSM6N15FEAPE

ODD_PWR_EN

PP5V_S3

6 7

CRITICAL

Q4596

SOT563

R4532

1/16W MF-LF

6

D

2

SG

1

2

0

5%

402

1

PP5V_S3_IR_R

6

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm VOLTAGE=5V

1

C4532

0.1UF

10% 16V

2

X7R-CERM 402

6

92

SATA_HDD_R2D_N

SATA_HDD_R2D_P

6

41

1

C4595

0.068UF

10% 10V

2

CERM

402

R4595

100K

1 2

5% 1/16W MF-LF

402

PP5V_SW_ODD_R

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

PP5V_S0_HDD_FLT

6

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

CRITICAL

J4501

54722-0224

F-ST-SM

1

2

NC

NC NC

43

5

6

7

8

9

10

11

12

14

13

1615

18

17

19

20

2221

516S0687

CRITICAL

FL4501

12-OHM-100MA-8.5GHZ

TCM0806-4SM

SYM_VER-1

1

ODD_PWR_SS

SATA_HDD_D2R_RC_C_P

SATA_HDD_D2R_RC_C_N

SATA_HDD_R2D_UF_N

92

4

32

SATA_HDD_R2D_UF_P

92

CRITICAL

Q4590

TPCP8102

23V1K-SM

S

123

XW4598

D

G

4

C4596

0.01UF

1 2

10% 16V

CERM

402

SM

21

PLACE_NEAR=J4501.9:3mm

CRITICAL

L4500

FERR-70-OHM-4A

0603

1

C4501

0.1UF

20% 10V

2

CERM 402

PP5V_SW_ODD

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

7

5 68

21

PP5V_SW_ODD_R

6

41

PP5V_S0_HDD_R

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

1

C4502

0.1UF

20% 10V

2

CERM 402

IR_RX_OUT

SYS_LED_ANODE_R

6

C4531

0.001UF

R4536

GND_VOID=TRUE

68.1

C4536

5PF

1

+/-0.25PF

R4535

68.1

1

C4535

5PF

1 2

+/-0.25PF

D2R values for 4.5dB de-emphasis

1

10% 50V

2

CERM

402

MF-LF

1%

21

1/16W

402

2

CERM

402

50V

1%

MF-LF

2

1/16W

402

CERM

402

50V

R2D values for 3dB de-emphasis

GND_VOID=TRUE

R4534

41.2

1 2

C4534

15PF

1 2

R4533

41.2

1 2

C4533

15PF

1 2

5%

50V

5%

50V

1/16W

1%

CERM

402

1%

CERM

402

MF-LF

402

SATA_HDD_R2D_RC_UF_N

MF-LF

402

SATA_HDD_R2D_RC_UF_P

41

6

41

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

SMC_ODD_DETECT

6

44

OUT

Indicates disc presence

R4531

4.7

2 1

92

5% 1/16W MF-LF

402

SATA_HDD_D2R_C_P

6

SATA_HDD_D2R_C_N

6

SYS_LED_ANODE

C4516

0.01UF

C4515

0.01UF

GND_VOID=TRUE

16 23

GND_VOID=TRUE

C4511

0.01UF

C4510

0.01UF

GND_VOID=TRUE

PP5V_SW_ODD

R4590

33K

5% 1/16W MF-LF

402

XW4599

SM

2

1

OUT

IN

GND_VOID=TRUE

21

SATARDRVR_EN

IN

SATARDRVR_I2C_ADDR0

41

SATARDRVR_I2C_ADDR1

41

1

1 2

10%

1

2

PP5V_S0

PP1V5_S0

7

16 20 22 25 41 56 70

6

43

6

45

SATA_HDD_D2R_RDRVR_IN_P

CERM

16V10%

SATA_HDD_D2R_RDRVR_IN_N

CERM

16V 402

10%

SATA_HDD_R2D_RDRVR_OUT_N

SATA_HDD_R2D_RDRVR_OUT_P

40216V210%

CERM

16V

CERM

402

CRITICAL

J4500

54722-0164

1

3 4

56

78

9

11 12

13 14

15 16

516S0616

NO STUFF

R4510

4.7K

1/16W MF-LF

402

SATARDRVR_I2C_EN_L

SATARDRVR_TEST

1

R4511

0

5% 1/16W MF-LF 402

2

F-ST-SM

2

10

6 7 8

22 46 51 53 64 67 68 69 71 72 86 88

101

5%

1 2

5

7

8

9

10

18

SATA_ODD_R2D_P

6

92

SATA_ODD_R2D_N

6

92

SATA_ODD_D2R_UF_N

6

92

SATA_ODD_D2R_UF_P

6

92

7

16 20 22 25 41 56 70

U4510

PS8521A

A_INP A_INN

B_OUTN B_OUTP

EN

B_PRE0/I2C_ADDR0

APRE0/I2C_ADDR1

I2C_EN*

TEST

PP1V5_S0

6

16

VDD

TQFN

CRITICAL

A_PRE1/SCL_CTL

B_PRE1/SDA_CTL

THRM

GND

PAD

3

13

21

1

C4514

0.1UF

20% 10V

2

CERM 402

A_OUTP A_OUTN

B_INN B_INP

1

2

PLACE_NEAR=U4510.16:2 mm PLACE_NEAR=U4510.6:2 mm

15 14

124 11

20

REXT

19

17

338S0907

36

CRITICAL

FL4520

90-OHM-100MA

DLP11S

SYM_VER-1

3 4

CRITICAL

FL4525

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

C4519

0.01UF

20% 16V CERM 402

SATARDRVR_REXT

SATA_ODD_R2D_UF_P

12

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_C_N

6

21

SATA_ODD_D2R_C_P

6

SATA_HDD_D2R_RDRVR_OUT_P

SATA_HDD_D2R_RDRVR_OUT_N

SATA_HDD_R2D_RDRVR_IN_N

SATA_HDD_R2D_RDRVR_IN_P

R4512

4.99K

1% 1/16W MF-LF

402

C4521

D

1 2

SATA_ODD_R2D_C_P

40216V10%

CERM

SATA_ODD_R2D_C_N

10% 402

16V

CERM

2

SATA_ODD_D2R_N

10%

CERM

16V 402

21

SATA_ODD_D2R_P

10% 16V

CERM

402

SATARDRVR_I2C_ADDR0

SATARDRVR_I2C_ADDR1

41

PP1V5_S0

7

16 20 22 25 41 56 70

R4513

4.7K

1/16W MF-LF

402

1

5%

2

0.01UF

C4520

0.01UF

C4526

0.01UF

C4525

0.01UF

NO STUFF

R4515

4.7K

1/16W MF-LF

402

1 2

1

5%

2

Internally PD ~150K

Write:0xB6 Read:0xB7

ADDR1

ADD0

L L H

GND_VOID=TRUE

C4518

0.01UF

C4517

0.01UF

C4513

0.01UF

C4512

0.01UF

1

2

PAGE TITLE

2

1

GND_VOID=TRUE

1

2

GND_VOID=TRUE

1 2

GND_VOID=TRUE

SATA/IR/SIL Connectors

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Address (R/W)

L H L HH

10% 402

CERM

16V

CERM

10%

10% 16V

CERM

10% 16V

Apple Inc.

0x96/0x97 0x98/0x99 0xB6/0xB7 0xB8/0xB9

SATA_HDD_D2R_P

SATA_HDD_D2R_N

402

SATA_HDD_R2D_C_N

402

SATA_HDD_R2D_C_P

402

SMBUS_PCH_CLK

SMBUS_PCH_DATA

OUT

IN

BI

SYNC_DATE=11/08/2010SYNC_MASTER=K91_ERIC

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

16 92

IN

16 92

IN

16 92

OUT

16 92

OUT

16 92

16 23 26 28 30 47 61 88 93

45 OF 132

41 OF 101

SIZE

C

B

A

D

345678

2 1

D

USB Port Power Switch

Left USB Port A

CRITICAL

100

C

17 29 44 65 72

PM_SLP_S4_L

R4690

5.1K

1/16W MF-LF

402

C4692

0.47UF

10% 10V X5R 402

29 31 41 43 45 65 66 71 81

1

5%

2

1

220UF-35MOHM

2

CRITICAL

C4696

6.3V

POLY-TANT

CASE-B2-SM1

20%

1

2

24

OUT

24

OUT

CRITICAL

NOSTUFF

1

C4616

100UF

20%

6.3V

2

POLY-TANT CASE-B2-SM

USB_EXTA_OC_L USB_EXTB_OC_L

USB_PWR_EN

CRITICAL

C4690

10UF

6.3V

20% X5R

603

1

C4691

0.1UF

20% 10V

2

CERM 402

PP5V_S3

6 7

TPS2561DR

2

IN_0

3

IN_1

10

FAULT1*

6

FAULT2*

4

EN1

5

EN2

U4600

SON

THRM

GND

1

PAD

11

OUT1 OUT2

ILIM

9 8

7

USB_ILIM

R4600

23.2K

1/16W MF-LF

402

1%

1

2

CRITICAL

C4695

10UF

20%

6.3V X5R 603

PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

1

2

CRITICAL

C4617

10UF

6.3V X5R 603

20%

0.01uF

CERM

20% 16V

402

1

2

C4605

USB2_EXTA_MUXED_N

1

2

98

USB2_EXTA_MUXED_P

98

Current limit per port (R4600): 2.18A min / 2.63A max

0.01uF

CERM

20% 16V

402

1

2

B

C4615

USB/SMC Debug Mux

PP3V42_G3H

6 7

25 44 45 46

47 52 62 63 72

SMC_DEBUG_YES

SMC_RX_L

6

44 45 46

IN

SMC_TX_L

6

44 45 46

OUT

USB_EXTA_P

24 92

BI

USB_EXTA_N

24 92

BI

A

C4650

0.1UF

20% 10V

CERM

402

1

2

5 4

7 6

8

9

VCC

M+ M-

U4650

PI3USB102ZLE

TQFN

D+

CRITICAL

D-

SMC_DEBUG_YES

GND

3

1

Y+

2

Y-

10

SELOE*

SMC_DEBUG_NO

R4651

1/16W MF-LF

402

8 7 5 4 2 1

0

5%

SMC_DEBUG_YES

1

R4650

10K

5% 1/16W MF-LF 402

2

USB_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB

21

SMC_DEBUG_NO

R4652

0

1 2

5% 1/16W MF-LF

402

USB_EXTB_N

24 92

BI

USB_EXTB_P

24 92

BI

44

IN

CRITICAL

L4605

FERR-120-OHM-3A

1 2

0603

CRITICAL

L4600

90-OHM-100MA

DLP11S

SYM_VER-1

4

1

CRITICAL

L4615

FERR-120-OHM-3A

1 2

0603

PP5V_S3_RTUSB_A_F

6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

3

98

2

98

PP5V_S3_RTUSB_B_F

6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

CRITICAL

L4610

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

USB2_LT1_N

6

USB2_LT1_P

6

21

52

IOIONC

NC

6

VBUS

1

GND

D4600

RCLAMP0502N

SLP1210N6

CRITICAL

We can add protection to 5V if we want, but leaving NC for now

USB_LT2_N

6

98

USB_LT2_P

6

98

6

VBUS

1

GND

D4610

RCLAMP0502N

SLP1210N6

CRITICAL

Left USB Port B

36

CRITICAL

J4600

USB

F-RT-TH-M97-4

5

6

1

2

3

4

43

7

8

Place L4605 and L4615 at connector pin

CRITICAL

J4610

USB

F-RT-TH-M97-4

5

6

1

2

3

4

7

5 42 3

IOIONC

NC

8

SYNC_MASTER=K91_ERIC

PAGE TITLE

External USB Connectors

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

R

SYNC_DATE=10/08/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

46 OF 132

SHEET

42 OF 101

SIZE

C

B

A

D

IR SUPPORT

345678

2 1

D

100

24 92

BI

24 92

BI

C

PP5V_S3

6 7

29 31 41 42 45 65 66 71 81

DIFFERENTIAL_PAIR=USB2_IR DIFFERENTIAL_PAIR=USB2_IR

1

C4801

0.1UF

10% 16V

2

X7R-CERM 402

USB_IR_P USB_IR_N

IR_VREF_FILTER

1

C4803

1UF

10% 10V

2

X5R 402-1

CY7C63803-LQXC

12

P1.0/D+

13

P1.1/D-

15

P1.2/VREG

16

P1.3/SSEL

17

P1.4/SCLK

18

P1.5/SMOSI

19

P1.6/SMISO

8 9

10

P/N 338S0633

20

NC

21 22 23 24

THRML

14

VCC

U4800

QFN

CRITICAL

OMIT

25

P0.0

P0.1 INT0/P0.2 INT1/P0.3 INT2/P0.4 TIO0/P0.5 TIO1/P0.6

VSSPAD

11

7 6 5 4 3 2 1

IR_RX_OUT_RC

1

C4804

0.001UF

10% 50V

2

CERM 402

R4800

100

1 2

5% 1/16W MF-LF

402

IR_RX_OUT

6

41

IN

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K18_MLB

PAGE TITLE

Front Flex Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

48 OF 132

SHEET

43 OF 101

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

D

TP_SMC_P10

6

45

TP_SMC_RSTGATE_L

45

OUT

ALL_SYS_PWRGD

23 72 87 89

IN

S5_PWRGD

65 72

IN

PM_DSW_PWRGD

17

OUT

SMC_DELAYED_PWRGD

35 89

OUT

PM_PWRBTN_L

17 23

OUT

TP_SMC_P20

45

TP_SMC_P24

6

45

SMC_BMON_MUX_SEL

45 49

LPC_AD<0>

6

16 46 87 93

BI

LPC_AD<1>

6

16 46 87 93

BI

LPC_AD<2>

6

16 46 87 93

BI

LPC_AD<3>

6

16 46 87 93

C

BI

LPC_FRAME_L

6

16 46 87 93

IN

SMC_LRESET_L

25

IN

LPC_CLK33M_SMC

25 93

IN

LPC_SERIRQ

6

16 46

BI

TP_SMC_P41

6

45

SMBUS_SMC_MGMT_SDA

47 96

100

BI

TP_SMC_P43

45

SMC_GFX_THROTTLE_L

79

OUT

SMC_SYS_KBDLED

53

OUT

SMC_TX_L

6

42 44 45 46

OUT

SMC_RX_L

6

42 44 45 46

IN

SMBUS_SMC_0_S0_SCL

6

31 47 50 79 96

BI

NC

NC NC NC

NC

(OC)

NC NC

(OC)

B12 A13 A12 B13 D11 C13 C12 D10

D13 E11 D12 F11 E13 E12 F13 E10

345678

PP3V3_S5_AVREF_SMC

6

45

PP3V42_G3H

6 7

25 42 45 46 47 52 62 63

72

1

C4902

22UF

20%

6.3V CERM

805

P10 P11 P12 P13 P14 P15

P17

P20 P21 P22 P23 P24 P25 P26 P27

A9

P30

D9

P31

C8

P32

B7

P33

A8

P34

D8

P35

D7

P36

D6

P37

D4

P40

A5

P41

B4

P42

A1

P43

C2

P44

B2

P45

C1

P46

C3

P47

G2

P50

F3

P51

E4

P52

U4900

DF2117RVPLP20HV

TLP-145V (1 OF 3)

OMIT

P60 P61 P62 P63 P64 P65 P66P16 P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81 P82 P83 P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

L13 K12 K11 J12 K13 J10 J11 H12

N10 M11 L10 N11 N12 M13 N13 L12

A7 B6 C7 D5 A6 B5 C6

J4 G3 H2 G1 H4 G4 F4 F1

SMC_PM_G2_EN

NC NC NC

SMC_ADAPTER_EN

NC

SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L

SMC_CPU_VSENSE SMC_CPU_ISENSE SMC_GPU_VSENSE SMC_GPU_ISENSE SMC_GFX_VSENSE SMC_GFX_ISENSE SMC_P1V5S3_ISENSE SMC_CPUVCCIO_ISENSE

SMC_SCI_L

NC

PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L SMBUS_SMC_MGMT_SCL

(OC)

SMC_ONOFF_L SMC_BC_ACOK SMC_PME_S4_WAKE_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_CLK32K SMBUS_SMC_0_S0_SDA

(OC)

OUT

IN

OUT

IN

OUT

IN

BI

IN

BI

65 72

17 45 72

45

6

45 62

45 48

45 49

45 48

45 49

45 48

16 19

6

17 46

6

17 46

6

42 44 45 46

6

42 44 45 46

47 96

100

6

45 52

45 48 62 63

45 52

6

17 29 72

17 29 42 65 72

17 72

45

6

31 47 50 79 96

1

C4903

0.1UF

20%

2

10V

2

CERM 402

R4999

4.7

1 2

5% 1/16W MF-LF

402

1

C4904

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U4900.M12:3mm

PP3V3_S5_SMC_AVCC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=3.3V

6

45 46 63

IN

45

1

2

C4920

0.1UF

SMC_RESET_L

SMC_XTAL SMC_EXTAL

C4905

0.1UF

20% 10V CERM 402

20% 10V

CERM

402

1

C4906

0.1UF

20% 10V

2

CERM 402

1

2

M12

B1M1H10

AVCC

VCC

U4900

DF2117RVPLP20HV

TLP-145V (3 OF 3)

VCL

L11

E1

AVREF

OMIT

D3

RES*

A3

XTAL

A2

EXTAL

ETRST*

VSS

D2

L3

F10

B11

AVSS

C5

XW4900

SM

PLACE_NEAR=U4900.L3:4mm

2 1

E5

D1 H1

E3

H3

L9

12

C4907

0.47UF

6.3V

CERM-X5R

NC

GND_SMC_AVSS

PLACE_NEAR=U4900.E1:3mm

1

10%

2

402

R4909

10K

1/20W

SMC_KBC_MDE

1

R4902

10K

5% 1/20W MF 201

2

1

R4998

10K

5% 1/20W MF 201

2

45 48 49

201

1

5% MF

2

SMC_VCL

NC

MD1 MD2

NMI

1

R4901

10K

5% 1/20W MF 201

2

SMC_MD1

SMC_NMI

SMC_TRST_L

D

6

46

IN

6

46

IN

6

46

IN

C

U4900

DF2117RVPLP20HV

TLP-145V

(2 OF 3)

OMIT

PECI/PH3 PEVREF/PH4 PEVSTP/PH5

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2

K1 J3 K2 J1 K4 K5

N5 M6 L5 M5 N4 L4 M4

M8 N7 K8 K7 K6 N6 M7 L6

E2 F2 J2

A4 B3 C4

SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS G3_POWERON_L

SMC_SYS_LED SMC_LID

NC NC

TP_SMC_PF5

NC NC

NC

SMS_INT_L SMBUS_SMC_BSA_SDA

(OC)

SMBUS_SMC_BSA_SCL

(OC)

SMBUS_SMC_A_S3_SDA

(OC)

SMBUS_SMC_A_S3_SCL

(OC)

SMBUS_SMC_B_S0_SDA

(OC)

SMBUS_SMC_B_S0_SCL

(OC)

SMC_PROCHOT SMC_THRMTRIP

NC

CPU_PECI_R PVCCIO_S0_SMC_R PM_PECI_PWRGD_R

C4910

0.1UF

20% 10V

CERM

402

45

IN

6

45 46

IN

6

45 46

IN

6

45 46

OUT

6

45 46

IN

45

INBI

45

OUT

45 52 62

IN

6

45

45 54

IN

6

47 62 63 96

BI

6

47 62 63 96

BI

6

31 47 53 54 96

BI

6

31 47 53 54 96

BI

47 50 96

BI

47 50 96

BI

45

OUT

45

OUT

1

2

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

R4910

43

1 2

5% 1/16W MF-LF

402

R4911

0

1 2

5% 1/16W MF-LF

402

R4912

0

1 2

5% 1/16W MF-LF

402

CPU_PECI

PP1V05_S0

PM_PECI_PWRGD

10 19 90

6 7 9

10 12 13 14 16 17 20 22 23 35 39 67

69 72

101

72

SYNC_MASTER=K91_BEN

PAGE TITLE

SMC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=07/12/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

49 OF 132

SHEET

44 OF 101

SIZE

B

A

D

36

A10 C10 B10 C11 A11

G11 G13 F12 H13 G10 G12 H11 J13

M10

K10

N3

PA0

N1

PA1

M3

PA2

M2

PA3

N2

PA4

L1

PA5

K3

PA6

L2

PA7

B8

PB0

C9

PB1

B9

PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0

N9

PD1 PD2

L8

PD3

M9

PD4

N8

PD5

K9

PD6

L7

PD7

SMC_PA0_PU

45

TP_SPI_DESCRIPTOR_OVERRIDE_L

6

PM_SYSRST_L

6

17 25

OUT

USB_DEBUGPRT_EN_L

42

OUT

MEM_EVENT_L

26 28

BI

WIFI_EVENT_L

6

B

A

31 45

SYS_ONEWIRE

62

BI

SMC_BATLOW_L

45 72

OUT

SMC_RUNTIME_SCI_L

19

OUT

SMC_ODD_DETECT

6

41

IN

SMC_S4_WAKESRC_EN

45 72 85

OUT

SMC_PB4

45

SMC_DP_HPD_L

45

IN

SMC_GFX_OVERTEMP_L

79

IN

SMC_FAN_0_CTL

51

OUT

SMC_FAN_1_CTL

51

OUT

NC_SMC_FAN_2_CTL

6

45

OUT

NC_SMC_FAN_3_CTL

6

45

OUT

SMC_FAN_0_TACH

51

IN

SMC_FAN_1_TACH

51

IN

NC_SMC_FAN_2_TACH

6

45

IN

NC_SMC_FAN_3_TACH

6

45

IN

SMC_SA_ISENSE

45 48

IN

SMC_DCIN_VSENSE

45 48

IN

SMC_DCIN_ISENSE

45 49

IN

SMC_PBUS_VSENSE

45 48

IN

SMC_BMON_ISENSE

45 49

IN

SMC_CPU_HI_ISENSE

45 49

IN

SMC_GPU_HI_ISENSE

45 49

IN

SMC_OTHER_HI_ISENSE

45 49

IN

(OC) (OC) (OC) (OC) (OC) (OC) (OC) (OC)

NC

8 7 5 4 2 1

345678

2 1

NC_SMC_FAN_2_CTL

6

SMC Reset "Button", Supervisor & AVREF Supply

PP3V42_G3H

6 7

25 42 44 45 46 47 52

62 63 72

PP3V42_G3H

6 7

25 42 44 45 46 47 52

62 63 72

Desktops: 5V Mobiles: 3.42V

1

C5020

0.47UF

10%

6.3V 2

CERM-X5R

C5001

0.01UF

CERM

10% 16V

402

1

2

SMC_TPAD_RST_L

52

D

IN

SMC_ONOFF_L

6

44 45 52

IN

SMC_MANUAL_RST_L

OMIT

1

R5001

0

5% 1/10W MF-LF 603

2

SILK_PART=SMC_RST

1

V+

U5010

VREF-3.3V-VDET-3.0V

6

MR1*

(IPU)

MR2*

DELAY

GND

(IPU)

2

SN0903048

CRITICAL

7

4

3

VIN

DFN

RESET*

REFOUT

THRM

PAD

9

PLACEMENT_NOTE=Place R5001 on BOTTOM side

MR1* and MR2* must both be low to cause manual reset. Used on mobiles to support SMC reset via keyboard.

5

8

C5025

10uF

6.3V

20% X5R

603

1

R5000

1K

5% 1/16W MF-LF 402

2

SMC_RESET_L

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

1

C5026

0.01UF

10% 16V

2

CERM 402

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

44 48 49

6

44 46 63

OUT

6

44

NOTE: Internal pull-ups are to VIN, not V+.

Debug Power "Buttons"

SMC_ONOFF_L

603

OMIT

1

R5015

0

5%

2

PLACE_SIDE=TOP 5% 1/10W MF-LF 603

SILK_PART=PWR_BTN

C

R5016

PLACE_SIDE=BOTTOM

1/10W MF-LF

SILK_PART=PWR_BTN

OMIT

6

44 45 52

OUT

PM_CLK32K_SUSCLK_R

17

IN

44 45

NC_SMC_FAN_2_TACH

6

44 45

NC_SMC_FAN_3_CTL

6

44 45

NC_SMC_FAN_3_TACH

6

44 45

SMC_BC_ACOK

44 45 48 62 63

SMS_INT_L

44 45 54

SMC_CPU_VSENSE

44 45 48

SMC_CPU_ISENSE

44 45 49

SMC_GPU_VSENSE

44 45 48

SMC_GPU_ISENSE

44 45 48

SMC_GFX_VSENSE

44 45 48

SMC_GFX_ISENSE

44 45 49

SMC_P1V5S3_ISENSE

44 45 48

SMC_CPUVCCIO_ISENSE

44 45 48

SMC_SA_ISENSE

44 45 48 44 45 48

SMC_DCIN_VSENSE

44 45 48

SMC_DCIN_ISENSE

44 45 49

SMC_PBUS_VSENSE

44 45 48

SMC_BMON_ISENSE

44 45 49

SMC_CPU_HI_ISENSE

44 45 49

SMC_GPU_HI_ISENSE

44 45 49

SMC_OTHER_HI_ISENSE

44 45 49 44 45 49

TP_SMC_P10

6

44 45

TP_SMC_P20

44 45

TP_SMC_P24

6

44 45

SMC_BMON_MUX_SEL

44 45 49

TP_SMC_P41

6

44 45

TP_SMC_P43

44 45

TP_SMC_PF5

6

44 45

TP_SMC_RSTGATE_L

44 45

PLACE_NEAR=U1800.N14:5.1mm

SMC Crystal Circuit

1

2

C5010

15pF

5%

50V

CERM

402

C5011

15pF

5%

50V

CERM

402

21

IN

DP_A_EXT_HPD

83 84

CRITICAL

Q5020

SSM3K15FV

SOD-VESM-HF

1

G S

R5010

0

21

SMC_XTAL

44

1/16W MF-LF

B

SMC_EXTAL

44

5%

402

SMC_XTAL_R

CRITICAL

Y5010

20.00MHZ

5X3.2-SM

System (Sleep) LED Circuit

100 43 65 66 71

PP5V_S3

6 7 29 31 41 42 81

1

R5031

523

1/16W MF-LF

402

1%

2

1

R5030

20

1% 1/16W MF-LF 402

2

SYS_LED_ILIM

44 45 52 44 45 52

SYS_LED_L_VDIV

1

R5032

1.47K

1%

A

1/16W MF-LF

402

2

5

BD

SYS_LED_L

Q1

GS

1 2463

SMC_SYS_LED

44

IN

CRITICAL

E

Q5030

DMB54D0UV

SOT-563

Q2

C

SYS_LED_ANODE

6

41

OUT

17 19 20 22 23 24 25 29

44 72

IN

SMC_PME_S4_WAKE_L

IN

PP3V3_S5

6 7 39 55 65 70 71 72 82 85 89 98

SMC_BATLOW_L

BATLOW# Isolation

CRITICAL

1

R5040

100K

1/20W

5%

MF

201

2

Q5040

SSM3K15FV

SOD-VESM-HF

8 7 5 4 2 1

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

SMC_BC_ACOK

MAKE_BASE=TRUE

SMS_INT_L

MAKE_BASE=TRUE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_GPU_VSENSE

MAKE_BASE=TRUE

SMC_GPU_ISENSE

MAKE_BASE=TRUE

SMC_GFX_VSENSE

MAKE_BASE=TRUE

SMC_GFX_ISENSE

MAKE_BASE=TRUE

SMC_P1V5S3_ISENSE

MAKE_BASE=TRUE

SMC_CPUVCCIO_ISENSE

MAKE_BASE=TRUE

SMC_SA_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_GPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

TP_SMC_P10

MAKE_BASE=TRUE

TP_SMC_P20

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

TP_SMC_P43

MAKE_BASE=TRUE

TP_SMC_PF5

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

R5012

22

1 2

5% 1/16W MF-LF

402

1

R5020

100K

5% 1/20W MF 201

2

3

D

2

1

R5076

100K

5% 1/20W MF 201

2

1

GS

D

3

R5041

0

1 2

5% 1/16W MF-LF

402

2

NOSTUFF

6

44 45

6

44 45

6

44 45

6

44 45

44 45 48 62 63

44 45 54

44 45 48

44 45 49

44 45 48

44 45 49

44 45 48

44 45 49

44 45 48

44 45 49

6

44 45

6

44 45

44 45 49

6

44 45

6

44 45

SMC_CLK32K

PP3V3_S4

SMC_DP_HPD_L

PP3V3_S4

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

PP3V3_SUS

7

45 52 53 71

OUT

7

45 52 53 71

44

OUT

44

OUT

7

16 17 18 19 20 22 70 71 72

Internal 20K pull-up on PM_BATLOW_L in PCH.

PM_BATLOW_L

17

OUT

TO CPU

CPU_PROCHOT_L

10 67 90

BI

PM_THRMTRIP_L_R

19

OUT

SMC FSB to 3.3V Level Shifting

48 49 50 51 53 56 60 61 71 72

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 47 79 82 83 84 87 88 89 98

1

R5061

100K

5% 1/16W MF-LF 402

2

CPU_PROCHOT_BUF

CRITICAL

3

Q5060

5

DMB53D0UV

SOT-563

4

SMC_ONOFF_L

6

G3_POWERON_L

44

SMC_LID

44 52 62

SMC_TX_L

6

SMC_RX_L

6

SMC_TMS

6

SMC_TDO

6

SMC_TDI

6

SMC_TCK

6

SMC_BIL_BUTTON_L

6

SMC_BC_ACOK

44 45 48 62 63

SMS_INT_L

44 45 54

SMC_PA0_PU

44

SMC_ADAPTER_EN

17 44 72

SMC_CASE_OPEN

44

SMC_PB4

44

SMC_S4_WAKESRC_EN

44 72 85

WIFI_EVENT_L

6

SYNC_MASTER=K91_BEN

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

6

1

3

4

R5062

D

S G

D

S G

3.3K

21

CPU_PROCHOT_L_R

5% 1/16W MF-LF

CRITICAL

402

Q5059

SSM6N15FEAPE

SOT563

2

SMC_PROCHOT

CRITICAL

Q5059

SSM6N15FEAPE

SOT563

5

SMC_THRMTRIP

44 45 52

42 44 46

44 46

44 62

31 44

36

G

2

R5070 R5072 R5071 R5073 R5074

R5077 R5078 R5079 R5080 R5081 R5087 R5093

R5091

R5085 R5086

R5088 R5090

R5089

10K 10K

100K

10K

100K

10K 10K 10K 10K 10K

470K

10K

100K

10K 10K

10K

100K

10K

SMC Support

Apple Inc.

R

1

R5060

10K

5% 1/16W MF-LF 402

2

SMC_PROCHOT_3_3_L

6

CRITICAL

D

Q5060

DMB53D0UV

SOT-563

S

1

PP3V42_G3H

6 7

25 42 44 45 46 47 52 62

63 72

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5%

1/20W

21

5% 201

1

NOSTUFF

1

31

1

1/20W

2

5%

1/20W

21

1/20W

5%

21

5%

1/20W

21

5%

1/20W

2

5%

1/20W

21

5% 201

1/20W

21

1/20W

5%

21

5% 201

1/20W

2

5% 201

1/20W

2

1/20W

5% MF

21

1/20W

5% 201MF

PP3V3_WLAN

6

5% MF2201

1/20W

SYNC_DATE=07/12/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

TO SMC

OUT

IN

201

MF

201

MF MF

201

MF

201 201

MF

201MF 201MF 201

MF

201

MF

201

MF MF

MF 201

MF MF

201

50 OF 132

45 OF 101

44

D

44

C

44

B

A

SIZE

D

345678

2 1

D

PP3V42_G3H

6 7

25 42 44 45 47 52 62 63

72

PP5V_S0

6 7 8

22 41 51 53 64 67 68 69 71 72 86

88

101

6

16 44 87 93

BI

6

16 44 87 93

BI

6

46

IN

6

46

OUT

6

16 44 87 93

IN

6

17 44

OUT

6

44 45

OUT

6

25 87 93

IN

6

44 45

OUT

6

44

IN

6

44

OUT

6

42 44 45

IN

C

LPC+SPI Connector

CRITICAL

LPCPLUS_CONN:YES

J5100

55909-0374

M-ST-SM

31

32

2

1

4

LPC_AD<0> LPC_AD<1>

SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS LPCPLUS_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

33

34

LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3>

SPIROM_USE_MLB SPI_ALT_CLK

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO

6

25 93

IN

6

16 44 87 93

BI

6

16 44 87 93

BI

6

19 55

OUT

6

46

IN

6

46

IN

6

16 44

BI

6

17 44

IN

6

44 45

OUT

6

44 45

OUT

6

44 45 63

OUT

6

44

OUT

6

42 44 45

OUT

6

19

OUT

D

C

516S0573

SPI Bus Series Termination

SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK

LPCPLUS_R:YES

1

R5128

0

5% 1/16W MF-LF 402

2

SPI_CS0_R_L

PLACE_NEAR=U1800.AV3:5mm

16 93

IN

B

16 93

PLACE_NEAR=U1800.AY1:5mm

16 93

PLACE_NEAR=U1800.BA2:5mm

SPI_CLK_R

IN

SPI_MOSI_R

IN

SPI_MISO

OUT

R5112

1 2

1/16W MF-LF

402

R5111

1 2

1/16W

15

5%

MF-LF

15

402

R5110

15

1 2

1/16W MF-LF

5%

402

5%

SPI_CS0_L

93

SPI_CLK

93

SPI_MOSI

93

LPCPLUS_R:YES

1

2

R5123

15

1 2

5%

PLACE_NEAR=U6100.2:5mm

1/16W MF-LF

402

R5127

47

5% 1/16W MF-LF 402

R5122

1 2

LPCPLUS_R:YES

1

R5126

47

5% 1/16W MF-LF 402

2

R5121

1 2

1/16W

47

5% 1/16W MF-LF

402

MF-LF

PLACE_NEAR=R5127.2:5mm

LPCPLUS_R:YES

1

R5125

47

5% 1/16W MF-LF 402

2

R5120

1 2

1/16W

47

5%

402

MF-LF

PLACE_NEAR=R5126.2:5mm

SPI_ALT_CS_L

PLACE_NEAR=J5100.14:5mm PLACE_NEAR=J5100.12:5mm PLACE_NEAR=J5100.9:5mm PLACE_NEAR=J5100.11:5mm

47

SPI_MLB_CS_L

5%

PLACE_NEAR=R5125.2:5mm

402

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_MLB_MISO

6

46

6

46

6

46

6

46

55

OUT

55

OUT

55

OUT

55

IN

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K18_MLB

PAGE TITLE

LPC+SPI Debug Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

51 OF 132

46 OF 101

SIZE

A

D

345678

2 1

Cougar Point

U1800

(MASTER)

88 93

SMBUS_PCH_CLK

16 23 26 28 30 41 47 61

MAKE_BASE=TRUE

D

88 93

SMBUS_PCH_DATA

16 23 26 28 30 41 47 61

MAKE_BASE=TRUE

VRef DACs

(Write: 0x98 Read: 0x99)

U3300

47 61 88

SMBUS_PCH_CLK

16 23 26 28 30 41 93 47 61 88

SMBUS_PCH_DATA

16 23 26 28 30 41 93

Margin Control

(Write: 0x30 Read: 0x31)

U3301

47 61 88

SMBUS_PCH_CLK

16 23 26 28 30 41 93 47 61 88

SMBUS_PCH_DATA

16 23 26 28 30 41 93

SATA Redriver

88 93

SMBUS_PCH_CLK

16 23 26 28 30 41 47 61

88 93

SMBUS_PCH_DATA

16 23 26 28 30 41 47 61

U4510

C

(Write: 0xB6 Read: 0xB7)

XDP Connectors

J2500 & J2550

(MASTER)

88 93

SMBUS_PCH_CLK

16 23 26 28 30 41 47 61

88 93

SMBUS_PCH_DATA

16 23 26 28 30 41 47 61

B

Cougar Point

U1800

(MASTER)

SML_PCH_0_CLK

16 93

MAKE_BASE=TRUE

SML_PCH_0_DATA

16 93

MAKE_BASE=TRUE

Cougar Point

A

(Write: 0x88 Read: 0x89)

U1800

SML_PCH_1_CLK

16 93

MAKE_BASE=TRUE

SML_PCH_1_DATA

16 93

MAKE_BASE=TRUE

SMLink 1 is slave port to access PCH & CPU via PECI.

8 7 5 4 2 1

PCH SMBus "0" Connections

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

1

402

R5201

1K

5%

1/16W MF-LF 402

2

(Write: 0xA0 Read: 0xA1)

R5200

1/16W MF-LF

(Write: 0xA4 Read: 0xA5)

(WRITE: 0x58 READ: 0x59)

(Write: 0x72 Read: 0x73)

SDRVI2C:SB

1

SDRVI2C:SB

R5237

1/16W MF-LF

402

1

0

5%

2

R5236

0

5% 1/16W MF-LF 402

2

I2C_DPSDRVA_SCL

47 84

MAKE_BASE=TRUE

I2C_DPSDRVA_SDA

47 84

MAKE_BASE=TRUE

(Write: 0x94 Read: 0x95)

PCH "SMLink 0" Connections

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

1

402

1

R5211

8.2K

5%

5% 1/16W MF-LF 402

2

R5210

8.2K

1/16W MF-LF

PCH "SMLink 1" Connections

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

NO STUFF

R5220

8.2K

1/16W MF-LF

402

NO STUFF

1

R5221

8.2K

5%

1/16W MF-LF 402

2

R5223

R5222

SO-DIMM "A"

J2900

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SO-DIMM "B"

J3100

SMBUS_PCH_CLK

SMBUS_PCH_DATA

LED BACKLIGHT

U9701

SMBUS_PCH_CLK

SMBUS_PCH_DATA

Mikey

U6880

SMBUS_PCH_CLK

SMBUS_PCH_DATA

DP SDRV "A"

U9310

I2C_DPSDRVA_SCL

I2C_DPSDRVA_SDA

0

5% 1/16W MF-LF

402

21

0

5% 1/16W MF-LF

402

47 61 88 16 23 26 28 30 41 93 47 61 88 16 23 26 28 30 41 93

47 84

SMC

U4900

(MASTER)

SMBUS_SMC_0_S0_SCL

6

31 44 47

50 79 96

SMBUS_SMC_0_S0_SDA

6

31 44 47

50 79 96

SMC

U4900

(MASTER)

SMBUS_SMC_A_S3_SCL

6

31 44 47

53 54 96

SMBUS_SMC_A_S3_SDA

6

31 44 47

53 54 96

SMC

U4900

(MASTER)

SMBUS_SMC_B_S0_SCL

44 47 50 96

SMBUS_SMC_B_S0_SDA

44 47 50 96

SMC "0" SMBus Connections

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

1

402

R5251

4.7K

5%

1/16W MF-LF 402

2

1

R5271

1K

5%

5% 1/16W MF-LF 402

2

R5250

4.7K

1/16W MF-LF

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

PP3V3_S3

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

R5270

1/16W MF-LF

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMC "B" SMBus Connections

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

1

96 47 50

SMBUS_SMC_B_S0_SCL

44

MAKE_BASE=TRUE

96

47 50

SMBUS_SMC_B_S0_SDA

44

MAKE_BASE=TRUE

R5260

4.7K

1/16W MF-LF

402

R5261

4.7K

5%

1/16W MF-LF 402

2

GPU Temp (Ext)

EMC1414-A: U5550

(Write: 0x98 Read: 0x99)

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

GPU Temp (Int)

Whistler: U8000

(Write: 0x82 Read: 0x83)

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

X19

(Write: 0x90 Read: 0x91)

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

Trackpad

(Write: 0x90 Read: 0x91)

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

(Write: 0x72 Read: 0x73)

(Write: 0x32 Read: 0x33)

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

J5800

J3401

ALS

Lid Angle Detect

Digital SMS

LIS331DLH: U5920

(Write: 0x30 Read: 0x31)

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

CPU Temp

EMC1414-A: U5570

(Write: 0x98 Read: 0x99)

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

T29 Temp

EMC1412-A: U5520

(Write: 0x90 Read: 0x91)

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

79 96 6

31

44 47 50

79 96 6

31

44 47 50

96 50 44 6 31 47 79

96 50 6

31 44 47 79 50

96 6

31 44 47 79

54 96 6

31

44 47 53

54 96 6

31

44 47 53

54 96 6

31

44 47 53

54 96 6

31

44 47 53

54 96 6

31

44 47 53

54 96 6

31

44 47 53

44 47 50 96

SMC "Battery A" SMBus Connections

PP3V42_G3H

6 7

25 42 44 45 46 52 62 63

72

SMC

U4900

(MASTER)

SMBUS_SMC_BSA_SCL

6

44 47 62

63 96

SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA

6

44 47 62

63 96

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

Battery

Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x92 Read: 0x93)

SMC "Management" SMBus Connections

PP3V3_S3

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 54 71 72 87

SMC

SMBUS_SMC_MGMT_SCL

44 47 96

100

SMBUS_SMC_MGMT_SDA

44 47 96

100

(MASTER)

100 47 96

SMBUS_SMC_MGMT_SCL

44

MAKE_BASE=TRUE

100

47 96

SMBUS_SMC_MGMT_SDA

44

MAKE_BASE=TRUE

T29 SMBus Connections

72 79 82 83 84 87 88 89 98 39 40 41 45 47

PP3V3_S0

6 7

12 16 17 18

19 20 22 23 25 26 28 32 35 36 48 49 50 51 53 56 60 61 71

T29 IC

U3600

(MASTER)

I2C_T29_SCL

33 47 84 95

MAKE_BASE=TRUE

I2C_T29_SDA

33 47 84 95

MAKE_BASE=TRUE

SDRVI2C:MCU

R5234

1/16W MF-LF

402

1

0

5%

2

R5230

4.7K

1/16W MF-LF

SDRVI2C:MCU

1

R5235

0

5% 1/16W MF-LF 402

2

I2C_DPSDRVA_SCL

47 84

MAKE_BASE=TRUE

I2C_DPSDRVA_SDA

47 84

MAKE_BASE=TRUE

SYNC_MASTER=K18_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

36

R5280

2.0K

1/16W MF-LF

R5290

4.7K

1/16W MF-LF

402

1

5%

402

2

1

R5281

2.0K

5%

5% 1/16W MF-LF

402

2

Battery Charger

ISL6258 - U7000

(Write: 0x12 Read: 0x13)

SMBUS_SMC_BSA_SCL

Battery

(See Table) SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

The bus formerly known as "Battery B"

1

R5291

4.7K

5%

1/16W MF-LF 402

2

Sensor ADC A

(Write: 0x10 Read: 0x11)

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

1

R5231

4.7K

5% 1/16W MF-LF 402

2

T29 Port A MCU

(Write: 0x26 Read: 0x27)

I2C_T29_SCL

I2C_T29_SDA

DP SDRV "A"

(Write: 0x94 Read: 0x95)

I2C_DPSDRVA_SCL

I2C_DPSDRVA_SDA

SMBus Connections

Apple Inc.

R

6

44 47

62 63 96

6

44 47

62 63 96

J6955

6

44 47

62 63 96

6

44 47

62 63 96

U5930U4900

44 47 96 100

J9330

33 47 84 95

U9310

47 84

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

52 OF 132

SHEET

47 OF 101

SIZE

D

C

B

A

D

345678

2 1

PBUS Voltage Sense Enable & Filter

CRITICAL

Q5300

NTUD3169CZ

SOT-963

Enables PBUS VSense divider when in S0.

71 72

D

35 39

PM_SLP_S3_R_L

IN

PPBUS_G3H

6 7 8 49 62 63 88

R5301

100K

1/16W MF-LF

N-CHANNEL

G

2

1

G

5

4

1

1%

402

2

P-CHANNEL

PBUSVSENS_EN_L_DIV

6

D

S

D

S

PBUSVSENS_EN_L

3

PBUS_S0_VSENSE

DC-In Voltage Sense Enable & Filter

CRITICAL

Q5310

NTUD3169CZ

SOT-963

Enables DC-In VSense divider when AC present.

SMC_BC_ACOK

44 45 62

C

63

6 7

62 63

IN

PPDCIN_G3H

R5311

100K

1/16W MF-LF

N-CHANNEL

G

2

1

G

5

4

1

1%

402

2

P-CHANNEL

PDCINVSENS_EN_L_DIV

6

D

S

D

S

DCINVSENS_EN_L

3

DCIN_S5_VSENSE

CPU Vcore Voltage Sense / Filter

PPVCORE_S0_CPU

6 7

12 14 68

101

B

XW5320

SM

21

PLACE_NEAR=R7510.2:5 MM

CPUVSENSE_IN

PLACE_NEAR=U4900.N10:5MM

R5320

1

R5302

100K

1% 1/16W MF-LF

402

2

R5303

PLACE_NEAR=U4900.L8:5MM

R5304

1

R5312

100K

1% 1/16W MF-LF

402

2

R5313

PLACE_NEAR=U4900.N9:5MM

R5314

4.53K

21

1% 1/16W MF-LF

402

SMC_CPU_VSENSE

PLACE_NEAR=U4900.N10:5MM

1

C5320

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

SMC Key VP0R SMC_ADC11

1

27.4K

1%

1/16W

PLACE_NEAR=U4900.L8:5MM

MF-LF

RTHEVENIN = 4573 Ohms

402

2

1

5.49K

1/16W MF-LF

27.4K

1/16W MF-LF

5.49K

1/16W MF-LF

1

1%

2

402

2

1

1%

PLACE_NEAR=U4900.N9:5MM

RTHEVENIN = 4573 Ohms

402

2

PLACE_NEAR=U4900.N9:5MM

1

1%

2

402

2

44 45 48 49

SMC_PBUS_VSENSE

PLACE_NEAR=U4900.L8:5MM

C5304

0.22UF

20%

6.3V X5R 402

GND_SMC_AVSS

SMC Key VD0R SMC_ADC9

44 45 48 49

SMC_DCIN_VSENSE

C5314

0.22UF

20%

6.3V X5R 402

GND_SMC_AVSS

SMC Key VC0C SMC_ADC0

44 45

OUT

44 45 48 49

GPU VCore Load Side Current Sense / Filter

47 49 50 51 53 56 60 61 71 72

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 79 82 83 84 87 88 89 98

EDP:28A

Vimon=31xVoltage across R8940=0.868V

GFXIMVP6_IMON

81

IN

ISNS_ON:YES

44 45

OUT

EDP:21.329A

Vi=Voltage across R7640=0.02139V

CPUVCCIOS0_CS_P

69 98

IN

CPUVCCIOS0_CS_N

69 98

IN

ISNS_ON:YES

44 45

OUT

EDP:6A

Vi=Voltage across R7140=0.006V

VCCSAS0_CS_P

64 98

IN

VCCSAS0_CS_N

64 98

IN

ISNS_ON:YES

SIGNAL_MODEL=EMPTY

R5305

2.87K

1% 1/16W MF-LF

402

R5306

10K

1% 1/16W MF-LF

402

SIGNAL_MODEL=EMPTY

CPU 1.05V VCCIO Current Sense / Filter

PP3V3_S3

6 7 8

18 19 24 25 29 30 31 32

47 49 53 54 71 72 87

ISNS_ON:YES

21

R5323

6.49K

R5324

6.49K

1% 1/16W MF-LF

402

GPUISENS_P

98

GPUISENS_N

98

ISNS_ON:YES

21

CPUVCCIOISNS_R_P

98

1% 1/16W MF-LF

402

21

CPUVCCIOISNS_R_N

ISNS_ON:YES

3

2

SIGNAL_MODEL=EMPTY

ISNS_ON:YES

1

R5325

1M

1% 1/16W MF-LF 402

2

CPU SA Current Sense / Filter

ISNS_ON:YES

R5363

1.82K

1

2

VCCSAISNS_R_P

98

1% 1/16W MF-LF

402

R5364

1.82K

21

VCCSAISNS_R_N

1% 1/16W MF-LF

402

ISNS_ON:YES

1

R5365

1M

1% 1/16W MF-LF 402

2

ISNS_ON:YES

CRITICAL

U5310

OPA2333

8

DFN

V+

1

V-

THRM

4

9

R5307

4.02K

21

1% 1/16W MF-LF

402

5

6

THRM

R5326

1/16W MF-LF

ISNS_ON:YES

3

2

THRM

R5366

1

1/16W MF-LF

SIGNAL_MODEL=EMPTY

ISNS_ON:YES

8

V+

V-

4

9

1M

21

1%

402

8

V+

V-

4

9

1M

2

1%

402

ISNS_ON:YES

1

C5310

0.1UF

20% 10V

2

CERM 402

ISNS_ON:YES

PLACE_NEAR=U4900.N11:5mm

R5308

GPUVCORE_IOUT

Gain: 3.75x

CRITICAL

U5310

OPA2333

DFN

7

ISENSE_CPUVCCIO_IOUT

4.53K

1/16W MF-LF

ISNS_ON:YES

Gain: 154x

402

SIGNAL_MODEL=EMPTY

ISNS_ON:YES

CRITICAL

U5360

OPA2333

DFN

1

ISENSE_SA_IOUT

ISNS_ON:YES

GAIN:549X

21

SMC_GPU_ISENSE

1%

1

C5308

0.22UF

20%

6.3V

2

PLACE_NEAR=U4900.L12:5mm

R5327

ISNS_ON:YES

X5R 402

GND_SMC_AVSSGND_SMC_AVSS

4.53K

21

1% 1/16W MF-LF

402

ISNS_ON:YES

1

C5360

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=U4900.M10:5mm

R5367

4.53K

21

SMC_SA_ISENSE

1% 1/16W MF-LF

1

402

C5367

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

SMC Key IG0C

SMC_ADC3

44 45

OUT

PLACE_NEAR=U4900.N11:5mm

44 45 48 49

SMC Key IC1C

SMC_ADC7

SMC_CPUVCCIO_ISENSE

1

C5327

PLACE_NEAR=U4900.L12:5mm

0.22UF

20%

6.3V

2

ISNS_ON:YES

X5R 402

GND_SMC_AVSS

44 45 48 49

SMC Key IC2C

SMC_ADC8

PLACE_NEAR=U4900.M10:5mm

ISNS_ON:YES

44 45 48 49

D

44 45

OUT

C

44 45

OUT

B

DESCRIPTION

RES, 0OHM, 0402

SMC Key IM0C

SMC_ADC6

PLACE_NEAR=U4900.N13:5mm

20%

6.3V X5R

ISNS_ON:YES

402

OUT

44 45 48 49

44 45

R5377

4.53K

1% 1/16W MF-LF

402

QTY

4

21

SMC_P1V5S3_ISENSE

1

C5377

0.22UF

2

GND_SMC_AVSS

36

AXG Vcore Voltage Sense / Filter

PPVCORE_S0_AXG

7

12 13 15

68

XW5330

SM

21

PLACE_NEAR=R7550.2:5 MM

GFXVSENSE_IN

PLACE_NEAR=U4900.N12:5MM

R5330

4.53K

1% 1/16W MF-LF

402

21

SMC_GFX_VSENSE

PLACE_NEAR=U4900.N12:5MM

1

C5330

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

GPU Vcore Voltage Sense / Filter

A

6 7

74 81

PPVCORE_GPU

XW5335

SM

21

PLACE_NEAR=R8940.1:5 MM

GPUVSENSE_IN

PLACE_NEAR=U4900.L10:5MM

R5335

4.53K

1% 1/16W MF-LF

402

21

SMC_GPU_VSENSE

PLACE_NEAR=U4900.L10:5MM

1

C5335

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

SMC Key VN0R

SMC_ADC4

44 45

OUT

44 45 48 49

SMC Key VG0C

SMC_ADC2

44 45 48 49

44 45

OUT

EDP:18A

Vi=Voltage across R7350=0.006V=0.018V

ISNS_1V5_S3_P

66 98

IN

ISNS_1V5_S3_N

66 98

IN

DDR3 1.5V S3 Current Sense / Filter

CRITICAL

U5360

OPA2333

8

DFN

V+

V-

THRM

4

9

1M

21

1% 1/16W MF-LF

402

ISNS_ON:YES

7

ISENSE_P1V5S3_IOUT

R5373

5.49K

1/16W MF-LF

R5374

5.49K

1% 1/16W MF-LF

402

ISNS_ON:YES

21

ISNS_1V5_S3_R_P

98

1%

402

21

ISNS_1V5_S3_R_N

1

R5375

1M

1% 1/16W MF-LF 402

2

ISNS_ON:YES

5

6

R5376

Gain: 182x

SIGNAL_MODEL=EMPTY

PART NUMBER

116S0090

PLACE_NEAR=U4900.N13:5mm

ISNS_ON:YES

8 7 5 4 2 1

REFERENCE DES

C5308,C5327,C5367,C5377

SYNC_MASTER=K91_DINESH

PAGE TITLE

CRITICAL

BOM OPTION

ISNS_ON:NO

Voltage & Load Side Current Sensing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=08/16/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

53 OF 132

SHEET

48 OF 101

SIZE

A

D

345678

2 1

COMPUTING High Side Current Sense / Filter

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

EDP Current:20.1A

PPVIN_S5_HS_COMPUTING_ISNS

7

64 66 67 68 69

OUT

R5400

D

Power Drop across R5400 at EDP becomes 1.21W

CRITICAL

PPBUS_G3H

6 7 8

35 39 48 49 62

IN

63 88

0612

98

0.003

432

ISNS_HS_COMPUTING_N

MF 1W 1%

ISNS_HS_COMPUTING_P

98

1

5

4

Gain:50x

IN-

3

V+

U5400

INA213

SC70

CRITICAL

GND

2

OUT

REFIN+

C5401

1

0.1UF

20% 10V CERM

2

402

6

HS_COMPUTING_IOUT

1

PLACE_NEAR=U4900.N8:5MM

R5403

4.53K

1% 1/16W MF-LF

402

GRAPHICS High Side Current Sense / Filter

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

EDP Current:4.9A

PPVIN_S5_HS_GPU_ISNS

7

81 86

OUT

PPBUS_G3H

6 7 8

35 39

IN

48 49 62 63 88

R5410

0612

0.003

CRITICAL

MF 1W 1%

1

432

ISNS_HS_GPU_N

98

ISNS_HS_GPU_P

98

5

4

Gain:200x

IN-

3

V+

U5410

INA210

SC70

CRITICAL

GND

2

OUT

REFIN+

6

1

C5411

1

0.1UF

20% 10V CERM

2

402

HS_GPU_IOUT

PLACE_NEAR=U4900.K9:5MM

R5413

4.53K

21

1% 1/16W MF-LF

402

C

SMC Key IC0R SMC_ADC13

21

SMC_CPU_HI_ISENSE

PLACE_NEAR=U4900.N8:5MM

C5403

1

0.22UF

20%

6.3V X5R

2

402

GND_SMC_AVSS

SMC Key IG0R SMC_ADC14

SMC_GPU_HI_ISENSE

PLACE_NEAR=U4900.K9:5MM

C5413

1

0.22UF

20%

6.3V X5R

2

402

GND_SMC_AVSS

OUT

44 45 48 49

PLACE_NEAR=R7510.3:5MM

CPUIMVP_ISNS1_P

67 68

IN

PLACE_NEAR=R7520.3:5MM

44 45

OUT

CPUIMVP_ISNS2_P

67 68

IN

PLACE_NEAR=R7530.3:5MM

CPUIMVP_ISNS3_P

67 68

IN

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7510.4:5MM

CPUIMVP_ISNS1_N

68

IN

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7520.4:5MM

CPUIMVP_ISNS2_N

68

IN

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7530.4:5MM

CPUIMVP_ISNS3_N

68

IN

SIGNAL_MODEL=EMPTY

Sense R is R7510, R7520 & R7530 Individual Sense R is 0.75mOhm

(Effective Sense R is 0.25mOhm due to summing of the 3 phases)

SIGNAL_MODEL=EMPTY

IMVPISNS_ENG

R5456

5.23K

21

0.5%

1/16W

MF

402

R5457

5.23K

21

0.5%

1/16W

MF

IMVPISNS_ENG

402

R5458

5.23K

1 2

0.5%

1/16W

MF

402

R5470

5.23K

0.5%

1/16W

402

R5471

5.23K

0.5%

1/16W

402

R5472

5.23K

1/16W

MF

0.5% MF

402

EDP: 94A TDP :45A

CPU VCore Load Side Current Sense / Filter

IMVPISNS_ENG

SIGNAL_MODEL=EMPTY

IMVPISNS_ENG

CPUIMVP_ISNS_P

98

IMVPISNS_ENG

21

CPUIMVP_ISNS_N

21

SIGNAL_MODEL=EMPTY

R5452

3.48K

1% 1/16W MF-LF

402

R5453

3.48K

1% 1/16W MF-LF

402

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

21

CPUIMVP_ISUM_R_P

21

CPUIMVP_ISUM_R_N

IMVPISNS_ENG

1

R5454

732K

1% 1/16W MF-LF 402

2

1

3

IMVPISNS_ENG

R5455

732K

1/16W MF-LF

IMVPISNS_ENG

CRITICAL

U5450

OPA333DCKG4

5

+

SC70-5

V+

4

V-

2

21

1%

SIGNAL_MODEL=EMPTY

402

IMVPISNS_ENG

PLACE_NEAR=U5450.5:3MM

1

C5450

0.1UF

20% 10V

2

CERM 402

CPUIMVP_ISUM_IOUT

SMC Key IC0C SMC_ADC1

IMVPISNS_ENG

ISNS_ON:YES

Gain:140x

Scale: 28.55A / V Max VOut: 3.3V at 94.2A

PLACE_NEAR=U4900.M11:5MM

R5451

4.53K

21

1% 1/16W MF-LF

402

PLACE_NEAR=U4900.M11:5MM

1

C5451

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

SMC_CPU_ISENSE

44 45 48 49

D

44 45

OUT

C

EDP Current:12.546A

PPVIN_S5_HS_OTHER_ISNS

7

65

OUT

PPBUS_G3H

6 7 8

35 39 48

IN

49 62 63 88

B

18 19 24 25 29 30 31 32

Charger/Load side

Sense R is R7050, 5mOhm NOTE: Monitoring current from battery to PBUS (battery discharge)

For engineering, Bmon=6.6A*100*R7050=3.3V

63 98

63

A

DC-IN (AMON) Current Sense Filter

EDP Current:4.6A

63

8 7 5 4 2 1

OTHER High Side Current Sense / Filter

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

R5430

0.005

CRITICAL

0612

432

ISNS_HS_OTHER_N

98

MF 1W 1%

ISNS_HS_OTHER_P

1

5

IN-

4

Gain:50x

CHARGER BMON High Side (BATTERY DISCHARGE) Current Sense, MUX & Filter

PP3V3_S3

6 7 8 47 48 53 54 71 72 87

CRITICAL

3

EDP Current:6.6A

CHGR_CSO_R_P BMON_INA_OUT

IN

CHGR_CSO_R_N

IN

5

4

Battery side

CHGR_BMON

IN

From charger

PLACE_NEAR=U4900.K10:5MM

R5441

IN

CHGR_AMON

4.53K

1% 1/16W MF-LF

402

V+

U5420

INA214

SC70

IN-

IN+ REF

For engineering, stuff BMON_ENG For production, stuff BMON_PROD

21

OUT

BMON:ENG (100V/V)

GND

2

SMC_DCIN_ISENSE

PLACE_NEAR=U4900.K10:5MM

1

C5441

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

BMON:ENG

1

C5420

0.1uF

20% 10V

2

CERM 402

6

1

Gain:100x

SMC Key ID0R SMC_ADC10

44 45 48 49

3

V+

U5430

INA213

SC70

CRITICAL

GND

2

OUT

REFIN+

BMON:ENG

44 45

C5431

1

0.1UF

20% 10V CERM

2

402

6

HS_OTHER_IOUT

1

C5421

0.1uF

20% 10V

2

CERM

402

PLACE_NEAR=U5421.1:5MM

SMC Key IO0R SMC_ADC15

PLACE_NEAR=U4900.L7:5MM

R5433

4.53K

21

SMC_OTHER_HI_ISENSE

1% 1/16W MF-LF

402

CRITICAL

BMON:ENG

U5421

NC7SB3157P6XG

SC70

B1

1

2

GND

3 4

B0

BMON:PROD

For Production, Bmon=36*18.33A*R7050=3.3V

1

0

VER 1

R5420

0

5% 1/16W MF-LF

402

SEL

6

5

VCC

A

12

PLACE_NEAR=U4900.L7:5MM

C5433

1

0.22UF

20%

6.3V X5R

2

402

GND_SMC_AVSS

SMC_BMON_MUX_SEL

BMON_AMUX_OUT

BMON:ENG

1

R5423

100K

5% 1/16W MF-LF 402

2

44 45

OUT

SMC Key IB0R SMC_ADC12

ISL6259 Gain: 36x

44 45

IN

PLACE_NEAR=U4900.M9:5MM

R5422

45.3K

21

1% 1/16W MF-LF

402

RC values chosen per K17 Radar 7337775

PLACE_NEAR=R7550.3:5MM

CPUIMVP_ISNS1G_P

68 98

IN

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7550.4:5MM

CPUIMVP_ISNS1G_N

68 98

IN

SIGNAL_MODEL=EMPTY

SMC_BMON_ISENSE

C5422

1

0.022UF

10%

PLACE_NEAR=U4900.M9:5MM

16V CERM-X5R

2

402

GND_SMC_AVSS

12 16 17 18 19 20 22 23

IMVPISNS_ENG

R5466

0

21

CPUIMVP_ISNS1G_R_P

5% 1/16W MF-LF

402

IMVPISNS_ENG

R5467

0

21

CPUIMVP_ISNS1G_R_N

5% 1/16W MF-LF

402

Sense R is R7550, 0.75mOhm

44 45

OUT

44 45 48 49

GFX/IG VCore Load Side Current Sense / Filter

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

IMVPISNS_ENG

R5462

5.49K

21

1% 1/16W MF-LF

402

IMVPISNS_ENG

R5463

5.49K

1% 1/16W MF-LF

402

CPUIMVP_ISUMG_R_P

21

CPUIMVP_ISUMG_R_N

IMVPISNS_ENG

1

R5464

732K

1% 1/16W MF-LF 402

2

IMVPISNS_ENG

5

1

+

V+

V-

3

-

2

IMVPISNS_ENG

R5465

732K

1% 1/16W MF-LF

402

CRITICAL

U5460

OPA333DCKG4

SC70-5

4

CPUIMVP_ISUMG_IOUT

21

SIGNAL_MODEL=EMPTY

IMVPISNS_ENG

PLACE_NEAR=U5460.5:3MM

1

C5460

0.1UF

20% 10V

2

CERM 402

SIGNAL_MODEL=EMPTY

PART NUMBER

116S0090

QTY

2

DESCRIPTION

RES, 0OHM, 0402

REFERENCE DES

SYNC_MASTER=K91_DINESH

PAGE TITLE

High Side and CPU/AXG Current Sensing

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

36

C5451,C5461

IMVPISNS_ENG

PLACE_NEAR=U4900.M13:5MM

R5461

4.53K

21

1% 1/16W MF-LF

402

ISNS_ON:YES

Gain:133.33x

Scale: 10A / V Max VOut: 3.3V at 33AEDP: 33A TDP: 21.5A

CRITICAL

Apple Inc.

R

SMC Key IN0R

SMC_ADC5

SMC_GFX_ISENSE

PLACE_NEAR=U4900.M13:5MM

1

C5461

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

44 45 48 49

BOM OPTION

ISNS_ON:NO

SYNC_DATE=10/29/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

54 OF 132

SHEET

49 OF 101

44 45

OUT

B

A

SIZE

D

345678

2 1

GPU Proximity/GPU Die/Left Heat Pipe/Right Fin Stack

R5550

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

78 98

D

Detect Right Fin Stack Temperature

Placement note:

Place Q5501 on bottom side close to the right fin stack

CRITICAL

Q5501

BC846BMXXH

SOT732-3

2

1

3

Detect GPU Die Temperature

SOT732-3

3

2

CRITICAL

Q5503

BC846BMXXH

1

BI

78 98

BI

GPUTHMSNS_D_P

98

GPUTHMSNS_D_N

98

GPU_TDIODE_P

Detect Left Heat Pipe Temperature

Place Q5503 on top side under left heat pipe near GPU

Placement note:

47

1 2

5% 1/16W MF-LF

402

SIGNAL_MODEL=EMPTY

GPU_TDIODE_N

SIGNAL_MODEL=EMPTY

PP3V3_S0_GPUTHMSNS_R

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PLACE_NEAR=U5550.2:5mm

PLACE_NEAR=U5550.3:5mm

C5551

0.0022uF

C5552

0.0022uF

1

10% 50V

2

CERM

402

1

10% 50V

2

CERM

402

PLACE_NEAR=U5550.4:5mm PLACE_NEAR=U5550.5:5mm

1

VDD

U5550

EMC1414-A

2

4

5

MSOP

THERM*/ADDR

DP1

DN1

DP2/DN3

DN2/DP3

ALERT*

CRITICAL

SMDATA

SMCLK

GND 6

Write Address: 0x98 Read Address: 0x99

1

C5550

0.1uF

20% 10V

2

CERM 402

7

GPUTHMSNS_THM_L

83

GPUTHMSNS_ALERT_L

9

SMBUS_SMC_0_S0_SDA

10

SMBUS_SMC_0_S0_SCL

Placement note:

Place U5550 on bottom side under GPU

R5551

10K

1/16W MF-LF

402

1

R5552

10K

5%

5% 1/16W MF-LF 402

2

BI

6

31 44 47 79 96

6

31 44 47 79 96

D

CPU Proximity/CPU Die/PCH Proximity/LVDS Connector Proximity

R5570

C

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

9

98

BI

CPU_THERMD_P

Detect CPU Die Temperature

CPU_THERMD_N

CRITICAL

Q5504

BC846BMXXH

SOT732-3

3

1

2

Detect LVDS Connector Proximity Temperature

Placement note:

Place Q5502 on bottom side close to the LVDS Connector

CRITICAL

Q5502

BC846BMXXH

SOT732-3

9

98

BI

2

1

3

Detect PCH Proximity Temperature

B

Placement note:

Place Q5504 under PCH

47

1 2

SIGNAL_MODEL=EMPTY

CPUTHMSNS_D2_P

98

MIN_LINE_WIDTH=0.25 mm

5%

MIN_NECK_WIDTH=0.2 mm

1/16W

VOLTAGE=3.3V

MF-LF

402

PLACE_NEAR=U5570.2:5mm

PLACE_NEAR=U5570.3:5mm

C5571

0.0022uF

CERM

SIGNAL_MODEL=EMPTY

0.0022uF

CPUTHMSNS_D2_N

98

PLACE_NEAR=U5570.4:5mm PLACE_NEAR=U5570.5:5mm

PP3V3_S0_CPUTHMSNS_R

2

1

10% 50V

2

402

C5590

10% 50V

CERM

402

1

2

4

5

DP1

DN1

DP2/DN3

DN2/DP3

1

VDD

U5570

EMC1414-A

MSOP

THERM*/ADDR

CRITICAL

GND 6

7

CPUTHMSNS_THM_L

83

ALERT*

SMDATA

Write Address: 0x98 Read Address: 0x99

CPUTHMSNS_ALERT_L

9

10

SMCLK

Placement note:

Place U5570 under CPU

1

C5570

0.1uF

R5571

20% 10V

2

CERM 402

10K

1/16W MF-LF

5%

402

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

1

R5572

10K

5% 1/16W MF-LF 402

2

Note: EMC1414 can perform Beta

Compensation for External Diode 1 only

44 47 50 96

BI

44 47 50 96

BI

C

B

T29 Proximity

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

PLACE_NEAR=U3600

PLACE_SIDE=BOTTOM

T29 Die

T29_THERMD_P

33 50

BI BI

A

Use GND pin B1 on U3600 for N leg

PLACE_NEAR=U3600.B1:2mm

XW5520

21

SM

T29_THERMD_P

33 50

MAKE_BASE=TRUE

PLACE_SIDE=BOTTOM

T29_THERMD_N

NOSTUFF

1

R5520

10K

5% 1/16W MF-LF 402

2

44 47 50 96

BI

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

C1

V+

U5520

TMP105

WCSP-6

A1

SDA

CRITICAL

SCL

A2

A0

ALERT

GNDS

8 7 5 4 2 1

1

C5520

0.1uF

20% 10V

2

CERM 402

C2

B2B1

NC

Placement note:

Place U5520 close to T29 router on BOTTOM side

Write Address: 0x90 Read Address: 0x91

36

SYNC_MASTER=K91_DINESH

PAGE TITLE

Thermal Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=09/22/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

55 OF 132

SHEET

50 OF 101

SIZE

A

D

345678

2 1

D

C

PP5V_S0

6 7 8

22 41 46 51 53 64 67 68 69 71 72

86 88

101

47 48 49 50 51 53

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 56 60 61 71 72 79 82 83 84 87 88 89 98

SMC_FAN_0_TACH

44 44

OUT OUT

R5651

100K

5% 1/16W MF-LF

402

44

IN

SMC_FAN_0_CTL

Left Fan

1

G

2

S D

4

R5655

47K

1 2

1/16W MF-LF

5

5%

402

PP5V_S0

6 7 8

22 41 46 51 53 64 67 68 69 71 72

86 88

101

47 48 49 50 51 53

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45

CRITICAL

1

R5650

47K

5% 1/16W MF-LF

402

FAN_LT_TACH

6

Q5660

2N7002DW-X-G

SOT-363

3

FAN_LT_PWM

6 6

2

J5650

78171-0004

M-RT-SM

5

1 2 3 4

6

518S0369

56 60 61 71 72 79 82 83 84 87 88 89 98

44

IN

SMC_FAN_1_TACH

R5661

100K

1/16W MF-LF

SMC_FAN_1_CTL

5%

402

Right Fan

R5665

1 2

1

2

G

2

S D

1

47K

6

5% 1/16W MF-LF

402

Q5660

2N7002DW-X-G

SOT-363 6

R5660

FAN_RT_TACH

FAN_RT_PWM

47K

1/16W MF-LF

402

CRITICAL

1

5%

2

J5660

78171-0004

M-RT-SM

5

1 2 3 4

6

518S0369

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=K18_MLB

PAGE TITLE

Fan Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

56 OF 132

SHEET

51 OF 101

345678

2 1

PSOC USB CONTROLLER

- USB INTERFACES TO MLB

- SPI HOST TO Z2

- TRACKPAD PICK BUTTONS

- KEYBOARD SCANNER

PP3V3_S4

7

45 52 53 71

D

SMC_PME_S4_WAKE_L

44 45

OUT

PICKB_L

6

53

BUTTON_DISABLE

52

Z2_HOST_INTN

6

53

WS_LEFT_SHIFT_KEY

52

WS_LEFT_OPTION_KEY

52

WS_CONTROL_KEY

52

Z2_KEY_ACT_L

6

53

TPAD_VBUS_EN

72

IN

Z2_DEBUG3

6

53

Z2_RESET

6

53

PSOC_MISO

6

53

PSOC_F_CS_L

6

53

PSOC_MOSI

6

C

53

PSOC_SCLK

6

53

Z2_MISO

6

53

Z2_CS_L

6

53

Z2_MOSI

6

53

Z2_SCLK

6

53

TP_PSOC_SCL

6

TP_PSOC_SDA

6

NC_PSOC_P1_3

6

TP_ISSP_SCLK_P1_1

6 8

ISSP SCLK/I2C SCL

USB_TPAD_P

24 92

USB_TPAD_N

24 92

R5704

0

2 1

5% 1/16W MF-LF

402

NC

R5701

24

5% 1/16W MF-LF

402

R5702

24

5% 1/16W MF-LF

402

PP3V3_S4_PSOC

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

1

R5703

220K

5% 1/16W MF-LF 402

2

554456

1

P2_5

P2_7

P0_3

P0_5

P1_7

15

P1_5

P0_1

CRITICAL

U5701

CY8C24794

(SYM-VER2)

337S2983

P1_1

P1_3

VSS

P2_3

2

P2_1

3

P4_7

4

P4_5

5

P4_3

6

P4_1

7

P3_7

8

P3_5

9

P3_3

10 33

P3_1

11 32

P5_7

12 31

P5_5

13 30

P5_3

14 29

P5_1

21

USB_TPAD_R_P

98

21

USB_TPAD_R_N

98

BYPASS=U5701.49:50:5 mm

1

2

50194922

51485247534654

VDD

VSS

P0_4

P0_7

P0_6

OMIT

MLF

P7_7

P7_0

D+

D-

VDD

23

24

21

20

1

C5702

100PF

5% 50V

2

CERM 402

BYPASS=U5701.22:19:5 mm

C5704

100PF

5% 50V CERM 402

P0_2

P1_0

BYPASS=U5701.49:50:8 mm

1

2

43

45

P2_4

P2_6

P0_0

P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0

THRML

PAD

P1_2

P1_4

P1_6

28162717261825

TP_ISSP_SDATA_P1_0

ISSP SDATA/I2C SDA

1

C5703

2

BYPASS=U5701.22:19:8 mm

C5705

0.1UF

10% 16V X7R-CERM 402

0.1UF

10% 16V X7R-CERM 402

BYPASS=U5701.49:50:11 mm

1

2

WS_KBD23 WS_KBD22 WS_KBD21 WS_KBD20 WS_KBD19 WS_KBD18

42

WS_KBD17

41

WS_KBD16N

40

WS_KBD15_C

39

WS_KBD14

38

WS_KBD13

37

WS_KBD12

36

WS_KBD11

35

WS_KBD10

34

WS_KBD9 WS_KBD8 WS_KBD7 WS_KBD1 WS_KBD2 WS_KBD3

57

WS_KBD4 WS_KBD5 WS_KBD6

Z2_CLKIN TP_P7_7

(PP3V3_S4_PSOC)

1

C5701

4.7UF

20%

6.3V

2

X5R 603

BYPASS=U5701.22:19:11 mm

C5706

4.7UF

20%

6.3V X5R 603

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6

52

6 8

6

53

6

IC

TMP102

3V3 LDO

PSOC

18V BOOSTER

SMC Manual Reset & Isolation

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

Keys ANDed with PSOC power to isolate when PSOC is not powered.

PIN NAME

V+

VDD VOUT

VDD

VIN

6 7

25 42 44 45 46 47 52 62

63 72

7

45 52 53 71

PP3V42_G3H

PP3V3_S4

B

WS_LEFT_SHIFT_KBD

6

52

TPAD Buttons Disable

WS_LEFT_OPTION_KBD

6

BUTTON_DISABLE

52

SSM6N15FEAPE

44 45 62

IN

CRITICAL

Q5701

SMC_LID

SOT563

2

PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

6

D

THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED

SG

1

LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V

A

52

WS_CONTROL_KBD

6

52

CURRENT

10UA 80UA

60MA (MAX) 60MA (MAX)

8MA (TYP) 14MA (MAX)

4MA (MAX)

2.55 KOHM

10 OHM

0.2 OHM

1.5 OHM

4.7 OHM

CRITICAL

2

IN_A1

(IPD)

3

IN_A2

(IPD)

7

IN_A3_B2

(IPD)

6

IN_B1

(IPD)

CRITICAL

2

IN_A1

(IPD)

3

IN_A2

(IPD)

7

IN_A3_B2

(IPD)

6

IN_B1

(IPD)

0.0255 V

0.204 V

0.6 V

0.012 V

0.021 V

0.0188 V

1

VDD

U5750

SLG4AP006

TDFN

THRM

GND

PAD

5

9

1

VDD

U5755

SLG4AP006

TDFN

THRM

GND

PAD

5

9

OUT_A

OUT_B

OUT_A

OUT_B

8 7 5 4 2 1

POWERV_SNSR_SNS

0.255E-6 W

16.32E-6 W

36E-3 W

0.72E-3 W

96E-6 W

294E-6 W

75.2E-6 W

1

C5750

0.1UF

10% 16V

2

X7R-CERM 402

4

WS_LEFT_SHIFT_KEY

8

WS_LEFT_OPTION_KEY

1

C5755

0.1UF

10% 16V

2

X7R-CERM 402

4

SMC_TPAD_RST

8

WS_CONTROL_KEY

CRITICAL

Q5701

SSM6N15FEAPE

SOT563

36

6

44 45

OUT

52

D

5

SG

52

Keyboard Connector

WS_KBD15_C

52

WS_KBD16N

52

SMC_ONOFF_L

1

C5710

0.1UF

20% 10V

2

CERM

PLACEMENT_NOTE=NEAR J5713

Pull-up in U5010.

SMC_TPAD_RST_L

3

4

402

R5714

470

1% 1/16W MF-LF

402

R5715

10K

1% 1/16W MF-LF

402

R5710

1K

5% 1/16W MF-LF

402

OUT

PP3V3_S4

7

45 52 53 71

PP3V42_G3H

6 7

25 42 44 45 46 47 52 62

63 72

WS_KBD1

6

52

WS_KBD2

6

52

WS_KBD3

6

52

WS_KBD4

6

52

WS_KBD5

6

52

WS_KBD6

6

52

WS_KBD7

6

52

WS_KBD8

6

52

WS_KBD9

6

52

WS_KBD10

6

52

WS_KBD11

6

52

WS_KBD12

6

52

21

WS_KBD13

6

52

WS_KBD14

6

52

WS_KBD15_CAP

6

WS_KBD16_NUM

6

WS_KBD17

6

52

WS_KBD18

6

52

WS_KBD19

6

52

WS_KBD20

6

52

WS_KBD21

6

52

WS_KBD22

6

52

WS_KBD23

6

52

WS_KBD_ONOFF_L

6

WS_LEFT_SHIFT_KBD

6

52

WS_LEFT_OPTION_KBD

6

52

WS_CONTROL_KBD

6

52

32

NC

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

31

NC

F-RT-SM

FF14-30A-R11B-B-3H

J5713

CRITICAL

518S0637

45

SYNC_MASTER=K91_ERIC SYNC_DATE=10/08/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

WELLSPRING 1

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

57 OF 132

SHEET

52 OF 101

SIZE

D

C

B

A

D

345678

2 1

D

PP5V_S5

6 7

65 71

C

R5805

2 1

1/16W MF-LF

C5816

X7R-CERM

BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION

- DROOP LINE REGULATION

- RIPPLE TO MEET ERS

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

- R5812,R5813,C5818 MODIFIED

0

5%

402

0.1UF

16V

CRITICAL

L5801

3.3UH-870MA

1

L

3

DO

THRML

1 2

VLF3010AT-SM-HF

2

VIN

U5805

TPS61045

QFN

CRITICAL

PAD

PGND

7

9

CTRL

6

FB

SW

GND

PP5V_S4_P18V5S5

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V

PP5V_S5_P18V5S5_VIN

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V

1

C5817

10%

402

2.2UF

10%

16V

2

X5R 603

NC

P18V5S4_SW

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE

4

P18V5S4_FB

5

Z2_BOOST_EN

1

8

R5811

100K

1% 1/16W MF-LF 402

2

CRITICAL

D5802

B0520WSXG

C5818

6

53

SOD-323

1 2

39PF

CERM

50V

PP18V5_S4

0

5%

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V

PP3V3_S3

6 7 8

18 19 24 25 29 30 31 32

47 48 49 54 71 72 87

VOLTAGE=3.3V MIN_NECK_WIDT=0.20MM MIN_LINE_WIDTH=0.50MM

R5800

0

1 2

5% 1/16W MF-LF

402

NO STUFF

R5806

PP18V5_S4_R

MIN_LINE_WIDTH=0.50MM VOLTAGE=18.5V

1

R5812

1

1M

1%

5%

1/16W

2

MF-LF

402

2

1

R5813

71.5K

1% 1/16W MF-LF 402

2

C5819

1UF

25V

603-1

1

10%

2

X5R

1

C5815

1000PF

5% 25V

2

NP0-C0G 402

1 2

1/16W MF-LF

402

IPD Flex Connector

CRITICAL

J5800

7

45 52 71

PP3V3_S4

6

52

6

52

6

52

6

52

6

52

6

53

6

52

6

52

Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN PP3V3_S3_TPAD Z2_CLKIN

55560-0228

M-ST-SM

2

10

20

516S0689

1

34

56

78

9

1112

1314

1516

1718

19

2122

PP18V5_S4

Z2_KEY_ACT_L Z2_RESET PSOC_F_CS_L PICKB_L PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL

6

52

6

53

6

31 44 47 54 96

6

31 44 47 54 96

D

C

Keyboard Backlight Driver & Detection

PP5V_S0

6 7 8

22 41 46 51 64 67 68 69 71 72 86

88

101

B

To detect Keyboard backlight, SMC will tristate and read SMC_SYS_KBDLED:

If LOW, keyboard backlight present If HIGH, keyboard backlight not present

R5853 always stuffed, R5854 only grounded when KB BL flex connected.

12 16 17 18 19 20 22 23

44

BI

47 48 49 50 51 56 60 61 71 72

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45 79 82 83 84 87 88 89 98

SMC_SYS_KBDLED

R5853

470K

1/16W MF-LF

1

5%

402

2

KB_BL

1

R5854

4.7K

5% 1/16W MF-LF 402

2

NO STUFF

KB_BL

C5850

R5852

10K

1/16W MF-LF

402

1UF

402-1

5%

10V

1

10%

2

X5R

1

2

6

CTRL

CRITICAL

A

8 7 5 4 2 1

CRITICAL

KB_BL

L5850

10UH-0.58A-0.35OHM

1 2

1098AS-SM

1

VIN

KB_BL

U5850

LT3491

DFN

GND

2

THRML

PAD

3

SW

5

LED

4

CAP

7

KBDLED_SW

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE

KBDLED_ANODE

6

KB_BL

1

R5855

10

1% 1/16W MF-LF 402

2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

KBDLED_CAP

(SMC_KBDLED_PRESENT_L)

KB_BL

1

C5855

1UF

10%

35V

2

X5R 603

Keyboard Backlight Connector

CRITICAL

KB_BL

J5815

FF18-4A-R11AD-B-3H

F-RT-SM

SMC_KDBLED_PRESENT_L

6

1

J5815 pin 1 is grounded

2

on keyboard backlight flex

3

4

518S0691

36

SYNC_MASTER=K91_ERIC SYNC_DATE=07/14/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

WELLSPRING 2

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

58 OF 132

SHEET

53 OF 101

SIZE

B

A

D

345678

2 1

D

PP3V3_S3

6 7 8

18 19 24 25 29 30 31 32

47 48 49 53 71 72 87

C5926

C

10UF

6.3V

BYPASS=U5920.14:13:8 mm

44 45

OUT

PLACEMENT_NOTE=See schematic for orientation.

BYPASS=U5920.14:13:8 mm

1

C5922

0.1UF

20%

X5R 603

SMS_INT_L TP_SMS_INT2

10%

6.3V

2

X5R 201

CRITICAL

1

14

VDD

2

NC

3

NC

1

R5924

10K

5%

1/20W

MF

201

2

Desired orientation when placed on board bottom-side (view thru top):

10

RESERVED

15

11

INT1CSSDA/SDI/SDO

9

INT2

VDD_IO

U5920

LIS331DLH

LGA

SCL/SPC

GND

5

16

13

12

8

SMS_I2C_SEL

7

SMS_ADDR_SELECT

SDO

6

I2C_SMC_SMS_SDA_R

4

I2C_SMC_SMS_SCL_R

338S0687

+Y

+X

Front of system

R5920

10K

1/20W

201

5%

MF

1

R5925

2

R5921

1

NOSTUFF

10K

5%

1/20W

MF

10K

1/20W

201

R5923

2

1

5%

MF

2

0

21

SMBUS_SMC_A_S3_SDA

5%

1/20W

MF

201

R5922

0

21

SMBUS_SMC_A_S3_SCL

5%

1/20W

MF

201

SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd) SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)

BI

IN

NOTE: SDA and SCL have internal pull-ups to VDD_IO.

6

31 44 47 53 96

6

31 44 47 53 96

D

C

+Z (dn)

B

A

8 7 5 4 2 1

Circle indicates pin 1 location when placed in correct orientation

SYNC_MASTER=K91_DINESH

PAGE TITLE

Digital Accelerometer

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=08/06/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

59 OF 132

SHEET

54 OF 101

36

SIZE

B

A

D

345678

2 1

D

C

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 65 70 71 72 82 85 89 98

1

R6101

3.3K

5% 1/16W MF-LF 402

2

46 46

46

6

19 46

NOTE: If HOLD* is asserted ROM will ignore SPI cycles.

SPI_MLB_CLK

IN IN

SPI_MLB_CS_L

IN

SPI_WP_L SPIROM_USE_MLB

IN

C6100

0.1UF

CERM

20% 10V

402

1

2

6

SCK

1

3

7

SST25VF064C

CE* WP* HOLD*

8

VDD

U6100

64MBIT

SOIC

OMIT

VSS

4

CRITICAL

SI

SO

5

2

SPI_MLB_MOSI

SPI_MLB_MISO

46

OUT

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K91_BEN

PAGE TITLE

SPI ROM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=06/08/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

61 OF 132

SHEET

55 OF 101

345678

AUDIO CODEC

CRITICAL

L6201

FERR-220-OHM

PP1V5_S0

7

16 20 22 25 41 70

IN

D

C

GND_AUDIO_HPAMP

56 58 60

PP4V5_AUDIO_ANALOG

56

IN

AUD_DMIC_SDA1

60

TP_AUD_GPIO_1

NC

6

TP_AUD_GPIO_2

NC

6

AUD_GPIO_3

59

OUT

AUD_SENSE_A

61

IN

HDA_BIT_CLK

16 93

IN

HDA_SYNC

16 93

IN

HDA_SDIN0

16 93

OUT

HDA_SDOUT

16 93

IN

HDA_RST_L

16 93

IN

60

IN

60

OUT

GND_AUDIO_CODEC

56 57 61

AUD_SPDIF_IN

AUD_SPDIF_OUT

1 2

0402

R6211

39

1 2

5% 1/16W MF-LF

402

CRITICAL

C6210

4.7UF

20% 4V X5R-1 402

1

R6210

2.67K

1% 1/16W MF-LF 402

2

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

AUD_SDI_R

93

1

2

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

R6212

39

1

2

5% 1/16W MF-LF

402

1

2

B

PP1V5_S0_AUDIO_DIG

C6211

0.1UF

10% 16V X5R 402-1

CRITICAL

C6221

10UF

20%

6.3V X5R 603

CRITICAL

VOLTAGE=1.5V MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

CRITICAL

C6219

TANT-POLY

2012-LLP

CRITICAL

1

2

C6222

2.2UF

20%

6.3V CERM 402-LF

C6220

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

10UF

20%

6.3V X5R 603

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

CS4206_FLYP CS4206_FLYC

CRITICAL

1

C6223

2 2

CS4206_FLYN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

AUD_SPDIF_OUT_CHIP

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

GND_AUDIO_HPAMP

56 58 60

1

10UF

20% 16V

2

CS4206_FP CS4206_FN

2.2UF

20%

6.3V CERM

402-LF

VBIAS_DAC

APPLE P/N 353S3199

9

24

VA_REF

29

VBIAS_DAC

44

VHP_FILT+

41

VHP_FILT-

2

GPIO0/DMIC_SDA1

12

GPIO1/DMIC_SDA2

14

GPIO2

15

GPIO3

13

SENSE_A

45

FLYP

43

FLYC

42

FLYN

3

VL_HD

1

VL_IF

6

BITCLK

10

SYNC

8

SDI

5

SDO

11

RESET*

47

SPDIF_IN

48

SPDIF_OUT

DGND

VD

/SPDIF_OUT2

7

CRITICAL

U6201

CS4206B

THRM_PAD

49

VA_HP

QFN

AGND

C6218

25

46

VA

HPOUT_L HPOUT_R

HPREF

LINEOUT_L1+ LINEOUT_L1LINEOUT_R1+ LINEOUT_R1-

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+ LINEOUT_R2-

MICBIAS

VCOM

LINEIN_L+ LINEIN_CLINEIN_R+

MICIN_L+ MICIN_LMICIN_R+ MICIN_R-

VREF+_ADC

DMIC_SCL

26

0.1UF

10% 16V X5R

402-1

CRITICAL

C6224

CASE-P3-HF

CRITICAL

C6216

1UF

CRITICAL

1

2

38

MIN_LINE_WIDTH=0.30MM

40

MIN_LINE_WIDTH=0.30MM

39

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

35 34 36 37

31 30 32 33

16

CS4206_VCOM

28

21

22

23

18 17 19 20

27

4

1

1UF

10% 20V

2

TANT

10% 10V

C6217

X5R 402-1

10UF

20% 16V TANT-POLY 2012-LLP

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

CS4206_VREF_ADC

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

CRITICAL

1

C6225

10UF

20% 16V

2

POLY-TANT CASE-B2-SM

1

C6215

2

AUD_DMIC_CLK

1

10% 16V X5R

2

C6214

0.1UF

402-1

0.1UF

402-1

MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM

NC

60

10% 16V X5R

1

2

CRITICAL

1

C6213

10UF

20%

6.3V

2

X5R 603

1

R6213

100K

5% 1/16W MF-LF 402

2

PP5V_S0_AUDIO

PP3V3_S0

PP4V5_AUDIO_ANALOG

GND_AUDIO_HPAMP

GND_AUDIO_CODEC

AUD_HP_PORT_L AUD_HP_PORT_R

AUD_HP_PORT_REF

TP_AUD_LO1_L_P TP_AUD_LO1_L_N

AUD_LO1_R_P AUD_LO1_R_N

AUD_LO2_L_P AUD_LO2_L_N AUD_LO2_R_P AUD_LO2_R_N

AUD_CODEC_MICBIAS

AUD_LI_P_L AUD_LI_REF AUD_LI_P_R

AUD_MIC_INP_L AUD_MIC_INN_L AUD_MIC_INP_R AUD_MIC_INN_R

2 1

8

56

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

56

IN

56 58 60

56 57 61

58

OUT

58

OUT

60

IN

NC

6

NC

6

59 98

OUT

59 98

OUT

59 98

OUT

59 98

OUT

59 98

OUT

59 98

OUT

61

OUT

57

IN

57

IN

57

IN

61

IN

61

IN

61

IN

61

IN

D

C

B

4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2234

CRITICAL

L6200

FERR-220-OHM

PP5V_S0_AUDIO

8

56

IN

89 98 45 47 48 49 50 51 53 56 60

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

IN

25 26 28 32 35 36 39 40 41 61 71 72 79 82 83 84 87 88

1 2

0402

R6200

2.21K

1 2

1% 1/16W MF-LF

402

A

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=5V

4V5_REG_IN

4V5_REG_EN

1

C6200

1UF

10% 10V

2

X5R 402-1

XW6200

SM

1 2

NOSTUFF

R6201

0

1 2

5% 1/16W MF-LF

402

XW6201

SM

1 2

8 7 5 4 2 1

MAX8840-4.5V

1

IN OUT

3

SHDN*

CRITICAL

1

C6201

1UF

10% 10V

2

X5R 402-1

CRITICAL

U6200

UDFN

BP

NC

GND

2

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

VOLTAGE=0V

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

6

4

4V5_NR

5

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM VOLTAGE=4.5V

C6202

0.1UF

1 2

X7R-CERM

VOLTAGE=0V

PP4V5_AUDIO_ANALOG

CRITICAL

1

C6203

1UF

10% 10V

2

10% 16V

402

X5R 402-1

GND_AUDIO_CODEC

GND_AUDIO_HPAMP

OUT

56

56 57 61

56 58 60

NOTES ON CODEC I/O

DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS

36

SYNC_MASTER=K91_AUDIO

PAGE TITLE

SYNC_DATE=09/30/2010

AUDIO: CODEC/REGULATOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

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DRAWING NUMBER

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PAGE

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SHEET

56 OF 101

SIZE

A

D

345678

2 1

D

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS NET RIN = 18K OHMS FC = 8 HZ VIN = 2VRMS, CODEC VIN = 1.14 VRMS

CRITICAL

60

IN

AUD_LI_L

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

1 2

1% 1/16W MF-LF

402

AUD_LI_L_DIV

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

R6300

7.87K

C

NOSTUFF

1

C6301

820PF

10% 50V

2

CERM 402

60

AUD_LI_GND

IN

1

R6303

10

1% 1/16W MF-LF 402

2

R6301

21.5K

1/16W MF-LF

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

402

1

1%

2

C6300

3.3UF

10% 16V

TANT

SMA-HF1

CRITICAL

C6302

3.3UF

10% 16V

TANT

SMA-HF1

12

AUD_LI_P_L

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

56

OUT

C

12

AUD_LI_REF

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

56

OUT

GND_AUDIO_CODEC

56 61

IN

1

R6305

21.5K

B

1/16W MF-LF

402

1%

2

NOSTUFF

1

C6304

820PF

10% 50V

2

CERM 402

B

CRITICAL

60

IN

AUD_LI_R

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

1 2

1% 1/16W MF-LF

402

AUD_LI_R_DIV

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

R6306

7.87K

A

8 7 5 4 2 1

C6303

3.3UF

10% 16V

TANT

SMA-HF1

12

AUD_LI_P_R

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

56

OUT

SIZE

A

D

SYNC_MASTER=K91_AUDIO

PAGE TITLE

AUDIO: LINE INPUT FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=07/12/2010

DRAWING NUMBER

REVISION

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PAGE

63 OF 132

SHEET

57 OF 101

36

345678

2 1

D

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

R6501

0

AUD_HP_PORT_L

56

C

IN

AUD_HP_ZOBEL_L

NC

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

GND_AUDIO_HPAMP

56 60

IN

AUD_HP_ZOBEL_R

NC

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_R

56

IN

CRITICAL

C6500

0.1UF

X7R-CERM

R6500

1/16W MF-LF

R6510

39

1/16W MF-LF

402

CRITICAL

C6510

0.1UF

10% 16V

X7R-CERM

402

10% 16V

402

39

5%

402

1

5%

2

1

2

B

1 2

5% 1/10W MF-LF

1

2

1

2

603

R6511

0

1 2

5% 1/10W MF-LF

603

AUD_HP_L

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

1

R6502

3.32K

1% 1/16W MF-LF 402

2

1

R6512

3.32K

1% 1/16W MF-LF 402

2

AUD_HP_R

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

60

OUT

60

OUT

C

B

A

SYNC_MASTER=K91_AUDIO

PAGE TITLE

AUDIO: HEADPHONE FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=07/12/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

65 OF 132

SHEET

58 OF 101

SIZE

A

D

345678

2 1

3X MONO SPEAKER AMPLIFIERS (SSM2375)

APN: 353S2958

GAIN = +3 DB 1ST ORDER FC (L&R) = ~737 HZ 1ST ORDER FC (SUB) = ~90 HZ

D

PP5V_S0_AUDIO_AMP_L

8

PLACE C6611 CLOSE TO VDD PIN

D

CRITICAL

1

C6612

TANT-POLY

CASE-A4

SSM2375L_P SSM2375L_N

47UF

6.3V

20%

2

CRITICAL

B1

IN+

A1

IN-

A2

SD*

C2

VDD

U6610

SSM2375

WLCSP

GND

C1

OUT+ OUT-

GAIN

EDGE

C3 B3

A3

B2

TP_LT_GAIN

56 98

AUD_LO2_L_P

IN

56 98

AUD_LO2_L_N

IN

AUD_SPKRAMP_SHUTDOWN_L

59

AUD_GPIO_3

56

IN

CRITICAL

L6610

FERR-1000-OHM

1 2

CRITICAL

L6611

FERR-1000-OHM

1 2

CRITICAL

L6601

FERR-1000-OHM

1 2

0402

AUD_SPKRAMP_LIN_P

98

NO_TEST=TRUE

AUD_SPKRAMP_LIN_N

98

NO_TEST=TRUE

R6600

100K

1/16W MF-LF

402

CRITICAL

C6613

0.0027UF

1 2

10% 50V

CERM

402

CRITICAL

C6614

0.0027UF

1 2

10% 50V

CERM

402

1

5%

2

98

C

IN+ IN-

SD*

C2

VDD

U6620

SSM2375

WLCSP

GND

C1

PLACE C6621 CLOSE TO VDD PIN

C3

OUT+

B3

OUT-

A3

GAIN

EDGE

TP_RT_GAIN

B2

PP5V_S0_AUDIO_AMP_R

8

59

CRITICAL

L6620

FERR-1000-OHM

56 98

AUD_LO2_R_P

IN

AUD_LO2_R_N

IN

AUD_SPKRAMP_SHUTDOWN_L

59

B

1 2

98

0402

CRITICAL

L6621

FERR-1000-OHM

1 2

98

0402

AUD_SPKRAMP_RIN_P

NO_TEST=TRUE

AUD_SPKRAMP_RIN_N

NO_TEST=TRUE

1

R6601

100K

5% 1/16W MF-LF

402

2

CRITICAL

C6623

0.0027UF

1 2

10% 50V

CERM

402

CRITICAL

C6624

0.0027UF

1 2

10% 50V

CERM

402

98

TANT-POLY

SSM2375R_P SSM2375R_N

C6622

47UF

20%

6.3V

CASE-A4

1

2

CRITICAL

B1 A1

A2

NC

CRITICAL

1

C6611

0.1UF

10% 16V

2

X5R 402-1

CRITICAL

1

C6621

0.1UF

10% 16V

2

X5R 402-1

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRCONN_L_OUT_P

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRCONN_L_OUT_N

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRCONN_R_OUT_N

6

60 98

OUT

6

60 98

OUT

C

6

60 98

OUT

6

60 98

OUT

B

IN+ IN-

SD*

C2

VDD

U6630

SSM2375

WLCSP

GND

C1

PLACE C6631 CLOSE TO VDD PIN

C3

OUT+

B3

OUT-

A3

GAIN

EDGE

TP_SW_GAIN

B2

NC

CRITICAL

1

C6631

0.1UF

10% 16V

2

X5R 402-1

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRCONN_S_OUT_P

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRCONN_S_OUT_N

6

60 98

OUT

6

60 98

OUT

SIZE

A

D

SYNC_MASTER=K91_AUDIO

PAGE TITLE

AUDIO: SPEAKER AMP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=07/12/2010

DRAWING NUMBER

REVISION

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PAGE

66 OF 132

SHEET

59 OF 101

36

PP5V_S0_AUDIO_AMP_R

8

59

98

CRITICAL

SSM2375S_P SSM2375S_N

CRITICAL

L6630

FERR-1000-OHM

56 98

A

AUD_LO1_R_P

IN

AUD_LO1_R_N

IN

AUD_SPKRAMP_SHUTDOWN_L

59

1 2

98

0402

CRITICAL

L6631

FERR-1000-OHM

1 2

98

0402

AUD_SPKRAMP_SUBIN_P

NO_TEST=TRUE

AUD_SPKRAMP_SUBIN_N

NO_TEST=TRUE

CRITICAL

C6633

0.022UF

1 2

10% 25V X7R

0402

CRITICAL

C6634

0.022UF

1 2

10% 25V X7R

0402

C6632

100UF

20%

6.3V TANT

CASE-AL1

1

2

CRITICAL

B1 A1

A2

8 7 5 4 2 1

345678

2 1

MIC CONNECTOR

Dual DMIC removed.Added single analog mic like K18.

Sept 21st 2010

AUDIO JACK 1 LO/HP JACK, SPDIF TX

Place this in place of DMIC connector J6780

CRITICAL

D

MIN_LINE_WIDTH=0.40MM

88 89 98 61 71 72 79 45 47 48 49 25 26 28 32

PP3V3_S0

6 7

12 16 17

18 19 20 22 23 35 36 39 40 41 50 51 53 56 60

82 83 84 87

APN: 514-0671

CRITICAL

J6700

SPDIF-TXRX-K24

F-RT-TH

6

MIC

5

DETECT

2

SWITCH

1

LEFT

3

RIGHT

4

GND

AUDIO

7

A - VIN

8

B - VCC

9

C

OPERATING VOLTAGE 3.3

60 61 71 72 79 35 36 39 40 41

PP3V3_S0

6 7

12 16 17 18

19 20 22 23 25 26 28 32 45 47 48 49 50 51 53 56 82 83 84 87 88 89 98

B

APN: 514-0635

DETECT FOR PLUG TYPE

C - GND

POF

SHELL

SHIELD

PINS

CRITICAL

J6750

AUDIO-RCVR-M97

F-RT-TH5

SWITCH

LEFT

RIGHT

GROUND

10 11 12 13

5 2 1 3 4

AUDIO

6

A - VDD

7

B - GND

SHELL

SHIELD

PINS

8

9 10 11 12

C - VOUT

OPERATING VOLTAGE 3.3

POF

A

AUD_CONNJ1_SLEEVE2 AUD_CONNJ1_SLEEVEDET AUD_CONNJ1_TIPDET AUD_CONNJ1_TIP AUD_CONNJ1_RING

AUD_CONNJ1_SLEEVE

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

1

C6700

0.1UF

10% 16V

2

X5R 402-1

AUD_J2_OPT_OUT

1

C6750

1UF

10% 10V

2

X5R 402-1

1

C6701

2.2UF

20%

6.3V

2

CERM 402-LF

AUD_CONNJ2_TIPDET

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

AUD_CONNJ2_RING

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

AUD_CONNJ2_TIP

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

AUD_CONNJ2_SLEEVE

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

60

R6749

4.7

21

5% 1/16W MF-LF

402

CRITICAL

DZ6703

6.8V-100PF

GND_CHASSIS_AUDIO_JACK

8

CRITICAL

2

1

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

2

402

1

GND PATCH

CRITICAL

DZ6758

ESDALC5-1BM2

DZ6757

ESDALC5-1BM2

SOD882

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

CRITICAL

DZ6704

6.8V-100PF

2

DZ6706

6.8V-100PF

402

1

SOD882

402

CRITICAL

2

1

2

1

CRITICAL

2

DZ6756

6.8V-100PF

402

1

2

1

6.8V-100PF

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

CRITICAL

DZ6700

6.8V-100PF

CRITICAL

DZ6701

6.8V-100PF

402

CRITICAL

DZ6754

402

XW6701

SM

XW6702

SM

R6701

0

5% 1/16W MF-LF

402

2

402

1

21

L6703

FERR-1000-OHM

0402

L6702

FERR-1000-OHM

0402

CRITICAL

L6701

FERR-220-OHM-2.5A

0603

2

1

C6705

100PF

5% 50V

2

CERM 402

FERR-1000-OHM

600-OHM-300MA

1 2

FERR-1000-OHM

1

C6756

100PF

5% 50V

2

CERM 402

CRITICAL

21

CRITICAL

21

FERR-220-OHM

21

CRITICAL

L6704

FERR-220-OHM

0402

CRITICAL

L6706

FERR-220-OHM

1

0402

R6700

10K

5% 1/16W MF-LF

402

L6705

FERR-1000-OHM

1

0402

CRITICAL

L6754

21

0402

CRITICAL

L6756

21

0402

CRITICAL

L6758

0402

CRITICAL

L6752

21

0402

L6707

0402

21

CRITICAL

21

2

CRITICAL

2

GND_CHASSIS_AUDIO_JACK

AUD_SPDIF_OUT

HS_MIC_P

HS_MIC_N

AUD_HP_PORT_REF

GND_AUDIO_HPAMP

AUD_HP_R

AUD_HP_L

AUD_J1_SLEEVEDET_R

AUD_J1_TIPDET_R

AUD_SPDIF_IN

AUD_LI_R

AUD_LI_L

AUD_LI_GND

AUD_J2_TIPDET_R

8

60

8

AUDIO JACK 2 LINE IN JACK, SPDIF RX

8 7 5 4 2 1

56

IN

61

OUT

61

OUT

56

BI

56 58

OUT

DIGI_MIC

AUD_DMIC_CLK

58

BI

56

OUT

DIGI_MIC

AUD_DMIC_SDA1

56

58

BI

OUT

DIGI_MIC

61

OUT

61

OUT

12 16 17 18 19 20 22 23

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

CRITICAL

L6783

600-OHM-300MA

0402

CRITICAL

L6784

600-OHM-300MA

0402

CRITICAL

L6785

600-OHM-300MA

1

0402

SPEAKER CONNECTOR

6

61

OUT

6

61

OUT

6

61

OUT

BI_MIC_N BI_MIC_SHIELD BI_MIC_P

21

CON_DMIC_CLK

CON_DMIC_SDA

21

CON_DMIC_PWR

2

APN: 518S0519

SPKRCONN_L_OUT_P

6

59 98

IN

SPKRCONN_L_OUT_N

6

60

59 98

IN

APN: 518S0521

SPKRCONN_S_OUT_P

6

59 98

IN

SPKRCONN_S_OUT_N

6

59 98

IN

SPKRCONN_R_OUT_P

6

59 98

IN

SPKRCONN_R_OUT_N

6

59 98

IN

56

OUT

57

BI

57

BI

57

61

OUT

NOSTUFF CRITICAL

C6781

33PF

50V

CERM

402

1

5%

2

SYNC_MASTER=K91_AUDIO

PAGE TITLE

CRITICAL

NOSTUFF

CRITICAL

1

C6782

33PF

5% 50V

2

CERM 402

NOSTUFF

C6783

33PF

50V

CERM

402

1

5%

2

AUDIO: JACKS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

36

78171-0003

DIGI_MIC

CRITICAL

78171-0004

NOSTUFF CRITICAL

1

C6784

33PF

5% 50V

2

CERM 402

J6780

M-RT-SM

4

1

2

3

5

J6783

M-RT-SM

5

1

2

3

4

6

CRITICAL

J6781

78171-0002

M-RT-SM

3

1 2

4

CRITICAL

J6782

78171-0004

M-RT-SM

5

1 2 3 4

6

SYNC_DATE=09/30/2010

DRAWING NUMBER

REVISION

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SHEET

67 OF 132

60 OF 101

SIZE

D

C

B

A

D

345678

2 1

CODEC OUTPUT SIGNAL PATHS

FUNCTION HP/LINE OUT SATELLITES SUB SPDIF OUT

VOLUME 0X02 (2) 0X04 (4) 0X03 (3) N/A

CONVERTER 0X02 (2) 0X04 (4) 0X03 (03) 0X08 (8)

PIN COMPLEX 0X09 (9,A) 0X0B (11) 0X0A (10) 0X10 (16)

CODEC INPUT SIGNAL PATHS

D

FUNCTION LINE IN SPDIF IN BUILT-IN MIC HEADSET MIC

CONVERTER 0X05 (5) 0X07 (7) 0X06 (6) 0X06 (6)

PIN COMPLEX 0X0C (12,C) 0X0F (15) 0X0D (13) 0X0D (13,V22,B,LEFT)

SYSTEM INT AND GPIO LINES

FUNCTION MIKEY ENABLE MIKEY INTERRUPT PERIPHERAL DETECT

INT

PIRQ H GPIO 5 PIRQ F

GPIO SATA4GP/GPIO 16

GPIO 3

PORT A DETECT (HEADPHONES)

AUD_SENSE_A

56 61

OUT

PP3V3_S0_AUDIO_F

61

C

AUD_J1_TIPDET_R

60 61

IN

GND_AUDIO_CODEC

56 57 61

PP3V3_S0_AUDIO_F

61

AUD_J1_SLEEVEDET_R

60 61

IN

GND_AUDIO_CODEC

56 57 61

1

R6801

220K

5% 1/16W MF-LF 402

2

R6802

47K

1 2

5% 1/16W MF-LF

402

1

R6804

220K

5% 1/16W MF-LF 402

2

SSM6N15FEAPE

AUD_J1_DET_RC

1

C6801

0.1UF

20%

2

CERM

R6803

220K

1 2

5% 1/16W MF-LF

402

SSM6N15FEAPE

1

C6802

0.01UF

10% 16V

2

CERM 402

APN:376S0613

AUD_OUTJACK_INSERT_L

3

Q6800

SOT563

10V 402

D

5

SG

4

AUD_J1_SLEEVEDET_INV

6

Q6800

SOT563

D

2

SG

1

SSM6N15FEAPE

B

EXTRACTION NOTIFICATION

CRITICAL

L6862

89 98 53 56 60 61 71 72 32 35 36 39 40 41

PP3V3_S0

6 7

12 16 17 18 19

IN

20 22 23 25 26 28 45 47 48 49 50 51 79 82 83 84 87 88

GND_AUDIO_CODEC

56 57 61

R6866

TIPDET_UNFILT

0

1 2

5% 1/16W MF-LF

402

AUD_J1_TIPDET_R

A

60 61

GND_AUDIO_CODEC

56 57 61

FERR-1000-OHM

1 2

R6864

220K

1 2

1/16W MF-LF

R6860

15K

1 2

5% 1/16W MF-LF

402

0402

C6861

0.1UF

10V

20%

402

CERM

AUD_J1_TIPDET_INV

5%

402

61

SSM6N15FEAPE

TIPDET_FILT

1

C6860

0.1UF

10V

20%

2

CERM

402

1

2

Q6803

SOT563

2

PP3V3_S0_AUDIO_F MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM

R6865

100K

1 2

1/16W MF-LF

402

6

D

SG

1

AUD_PERPH_DET_R

5%

SSM6N15FEAPE

VOLTAGE=3.3V

Q6803

SOT563

61

R6867

1 2

1/16W MF-LF

402

3

D

5

SG

4

MUTE CONTROL

N/A GPIO_3 GPIO_3 N/A

VREF

N/A N/A N/A

3

Q6801

SOT563

0

5%

D

5

SG

AUD_J1_SLEEVEDET_R

60 61

AUD_IP_PERIPHERAL_DET

DET ASSIGNMENT 0X09 (A) N/A N/A 0X0C (B)

DET ASSIGNMENT 0X0C (12,C) N/A N/A MIKEYMIKEY

16 23 26 28 30 41 47 88 93

18

19

PORT B DETECT(SPDIF DELEGATE)

1

R6806

39.2K

1% 1/16W MF-LF 402

2

AUD_PORTA_DET_L AUD_PORTB_DET_L

Q6801

SSM6N15FEAPE

4

SOT563

1

R6805

20.0K

1% 1/16W MF-LF 402

2

NC

6

D

2

SG

1

18

OUT

PULLUPS ON MCP PAGE

SMBUS_PCH_CLK

IN

SMBUS_PCH_DATA

BI

AUD_I2C_INT_L

OUT

AUD_IPHS_SWITCH_EN

IN

NC

AUD_SENSE_A

56 61

OUT

PP3V3_S0_AUDIO_F

61

AUD_J2_TIPDET_R

60

IN

GND_AUDIO_CODEC

56 57 61

12 16 17 18 19 20 22 23

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

1

R6811

270K

5% 1/16W MF-LF 402

2

R6812

1 2

R6883

0

1 2

5% 1/16W MF-LF

402

R6885

0

1 2

5% 1/16W MF-LF

402

47K

5% 1/16W MF-LF

402

FERR-1000-OHM

1 2

1

R6886

10K

5%

R6882

0

1 2

5% 1/16W MF-LF

402

R6884

0

1 2

5% 1/16W MF-LF

402

56

56 57 61

1/16W MF-LF

402

2

GND_AUDIO_CODEC

56 57 61

56

OUT

56

OUT

GND_AUDIO_CODEC

56 57 61

AUD_CODEC_MICBIAS

IN

GND_AUDIO_CODEC

56 57 61

AUD_MIC_INP_R

OUT

AUD_MIC_INN_R

OUT

GND_AUDIO_CODEC

1

R6887

100K

5% 1/16W MF-LF 402

2

AUD_MIC_INP_L

AUD_MIC_INN_L

PORT C DETECT (LINE-IN)

1

R6813

10K

1% 1/16W MF-LF

402

2

Q6802

SSM3K15FV

SOD-VESM-HF

AUD_J2_DET_RC

1

C6811

0.1UF

10V

20%

2

CERM

402

AUD_INJACK_INSERT_L

1

G S

CRITICAL

L6880

0402

CRITICAL

C6880

CRITICAL

C6850

0.1UF

1 2

CRITICAL

C6851

0.1UF

1 2

3

D

APN:376S0612

2

10UF

6.3V

10% 25V X5R 402

1

20%

2

X5R 603

R6850

1 2

1/16W MF-LF

R6853

2.4K

1 2

1/16W 402-1

8 7 5 4 2 1

PORT B LEFT(HEADSET MIC)

HP=80HZ, LP=8.82KHZ

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V

PP3V3_S0_HS_RX

CRITICAL

1

C6887

0.1UF

10% 25V

2

X5R 402

C3

B3

D3

A3

A1

B2

10% 25V X5R 402

SM

TIPDET_UNFILT

61

CRITICAL

C6886

0.1UF

1 2

10% 25V X5R 402

HS_SCL

HS_SDA

HS_INT_L

HS_ENABLE

CRITICAL

C6883

0.1UF

1 2

XW6880

1 2

PORT B RIGHT(BUILT-IN MIC)

100

MIC_BIAS_FILT

1%

402

CRITICAL

1

C6852

2.2UF

20%

6.3V

2

TANT 402

BI_MIC_HI_F

CRITICAL

1

R6852

100K

C6853

5%

0.001UF

2

1/16W MF-LF 402

50V 402

BI_MIC_LO_F

1% MF

HP=80HZ

NC

36

A2

CRITICAL

AVDD

U6880

CD3282A1

WCSP

SCL

MICBIAS

SDA

DETECT

BYPASS

INT*

ENABLE

HDET

CS

AGND

DGND

D2

C2

HS_MIC_HI_RC

1

R6888

100K

5% 1/16W MF-LF 402

2

R6851

2.4K

1 2

1%

1/16W

MF

402-1

1

10%

2

CERM

CSP MIKEY

APN:353S2640

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

C1

HS_MIC_BIAS

B1

HS_SW_DET

D1

HS_RX_BP

1

C6881

0.01UF

16V

10%

2

CERM

402

1

1K

1%

402

2

0402

XW6851

SM

1 2

R6881

2.2K

5% 1/16W MF-LF 402

2

1

C6885

27PF

5%

2

CERM

CRITICAL

BI_MIC_P

BI_MIC_N

BI_MIC_SHIELD

1

C6884

0.0082UF

10%

2

CRITICAL

R6890

2.2K

1 2

5% 1/16W MF-LF

402

25V 402X7R

FERR-1000-OHM

R6880

1/16W MF-LF

L6850

1 2

L6851

1 2

Place this next to the connector

SYNC_MASTER=K91_AUDIO

PAGE TITLE

AUDIO: JACK TRANSLATORS

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

CRITICAL

1

C6882

2.2UF

20%

6.3V

2

TANT 402

GND_AUDIO_CODEC

HS_MIC_P

50V 402

HS_MIC_N

Apple Inc.

56 57 61

60

IN

60

IN

6

60

IN

6

60

IN

6

60

IN

SYNC_DATE=09/21/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

68 OF 132

SHEET

61 OF 101

SIZE

D

C

B

A

D

MagSafe DC Power Jack

345678

2 1

20% 50V CERM 603

BI

CRITICAL

F6905

6AMP-24V

1 2

1206-2

SYS_ONEWIRE

1

R6929

2.0K

5% 1/16W MF-LF 402

2

4

CRITICAL

1

VCC

U6900

MAX9940

SC70-5

GND

2

SMC_BC_ACOK_VCC

5

EXTINT

NC

3

NC

PPDCIN_G3H

PP3V42_G3H

1

C6908

0.1UF

20% 10V

402

R6961

100

5%

MF-LF

2

12

1/16W

C6955

0.001UF

CERM 402

10% 50V

CERM

402

1

2

CRITICAL

TC7SZ08AFEAPE

SOT665

5

2

A

4

Y

U6901

1

B

3

44 45 52

SMC_LID

OUT

6 7

25 42 44 45 46 47 52 62 63

72

PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

SMC_BC_ACOK

PP3V42_G3H

6 7

25 42 44 45 46 47 52 62

63 72

6

96

6

44 47

BI

62 63

6

44 47

BI

62 63 96

SMC_LID_R

SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL

C6953

C6951

0.1UF

47PF

50V

CERM

402

1

10% 25V

2

X5R 402

1

C6952

5%

2

44 45 48 63

IN

BIL CONNECTOR

516S0523

CRITICAL

J6955

CPB6312-0101F

F-ST-SM

2

NC

10

1

47PF

5%

50V

2

CERM

402

1314

1

34

NC

56

78

9

1112

1516

SMC_BIL_BUTTON_L

C6954

0.001UF

CERM

TO SMC

6

44 45

OUT

1

10% 50V

2

402

6 7

48 62 63

D

C

CRITICAL

J6900

D

78048-0573

M-RT-SM

1

PWR

2

PWR

3

GND

4

GND

5

SIG

PP18V5_DCIN_FUSE

6

MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V

1

C6905

0.01UF

2

44

1-Wire OverVoltage Protection

ADAPTER_SENSE

6

The chassis ground will otherwise float and can send transients onto ADAPTER_SENSE when AC is

C

connected.

3.425V "G3Hot" Supply

CRITICAL

D6990

BAT30CWFILM

PPBUS_G3H

6 7 8

35 39 48 49 63 88

R6990

47

PPDCIN_G3H

6 7

48 62 63

B

1 2

1%

1/3W

MF

805

PPDCIN_S5_P3V42G3H

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V

SOT-323

1

2

3

C6990

4.7UF

X5R-CERM

0805

1

10% 35V

2

518-0375

CRITICAL

J6950

BAT-K90-K91-K92

M-RT-TH

1

P1

2

P2

3

P3

4

P4

5

P5

6

P6

7

P7

8

P8

9

P9

SHLD_PIN SHLD_PIN SHLD_PIN

A

SHLD_PIN

10

11

12

13

6

63

BATTERY CONNECTOR

SMBUS_SMC_BSA_SCL

SYS_DETECT_L

SMBUS_SMC_BSA_SDA

PPVBAT_G3H_CONN

6

1

C6950

0.1UF

10% 25V X5R 402

C6960

1UF

10%

603-1

25V X5R

2

1

2

D6950

RCLAMP2402B

CRITICAL

SC-75

6

44 47 62 63 96

6 44 47 62 63 96

1

2

3

R6950

1

10K

5% 1/16W MF-LF

402

2

8 7 5 4 2 1

Supply needs to guarantee 3.31V delivered to SMC VRef generator

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V

1

R6995

1M

5% 1/16W MF-LF 402

2

P3V42G3H_TON

P3V42G3H_FB

C6991

1UF

3

4

8

2

1

NC

1

10% 25V X5R 402

353S2776

2

TON

EN

VCC

FB

REF

7

VIN

U6990

PM6640

DFN

CRITICAL

THRM

GND

PAD

5

P3V42G3H_REF3

10

REF3

BYP

SW

11

C6994

0.1UF

402-1

C6995

0.1UF

20% 10V

CERM

402

9

6

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE

1

10% 16V

2

X5R

1

2

B

CRITICAL

33UH-20%-0.44A-0.455OHM

DIDT=TRUE

L6995

1 2

D52LC-SM

PP3V42_G3H

Vout = 3.425

300mA max output

f = 470 kHz

1

C6999

22UF

20%

6.3V

2

X5R-CERM-1 603

PAGE TITLE

DC-In & Battery Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

6 7

25 42 44 45 46 47 52 62 63

72

SYNC_DATE=10/08/2010SYNC_MASTER=K91_ERIC

DRAWING NUMBER

REVISION

BRANCH

PAGE

69 OF 132

SHEET

62 OF 101

SIZE

A

D

36

345678

CRITICAL

Q7080

IRF9395TRPBF

DIRECTFET-MC

NC

879

FROM ADAPTER

PPDCIN_G3H

6 7

48 62

1

D

ACIN pin threshold is 3.2V, +/- 50mV

Divider sets ACIN threshold at 13.55V

Input impedance of ~40K meets sparkitecture requirements

PP3V42_G3H

6 7

25 42 44 45 46 47 52 62

72

1

470PF

10% 50V CERM 402

C7002

C7015

220PF

10% 50V

X7R-CERM

402

R7016

3.01K

1/16W MF-LF

1UF

10% 10V

2

X5R 402

GND_CHGR_AGND

R7000

0

1 2

5% 1/16W MF-LF

402

1

2

1

1%

402

2

C

1

2

1

2

R7012

1/16W MF-LF

R7010

30.1K

1% 1/16W MF-LF 402

R7011

9.31K

1% 1/16W MF-LF 402

402

1

1K

1%

2

SMC_RESET_L

IN

1

R7015

330K

5% 1/16W MF-LF 402

2

CHGR_VCOMP_R

B

CHGR_VNEG_R

1

C7016

2

63

SMBUS_SMC_BSA_SCL

6

44 47

IN

62 96

SMBUS_SMC_BSA_SDA

6

44 47

BI

62 96

CHGR_VFRQ

72

IN

CHGR_CELL

CHGR_ACIN

CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P

96

CHGR_CSO_N

96

1

2

30mA max load

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=5.1V

C7050

1UF

C7085

0.1UF

10% 25V

2

X5R 402

CRITICAL

D7005

BAT30CWFILM

SOT-323

1

2

PP5V1_CHGR_VDD

NO STUFF

1

R7002

100K

5% 1/16W MF-LF 402

2

CHGR_RST_L

10% 16V X5R 402

3

Inrush Limiter

1

R7085

470K

1% 1/16W MF-LF

402

2

R7086

332K

1/16W MF-LF

402

CHGR_DCIN_D_R

12

VHST

13

SMB_RST_N

11

SCL

10

SDA

4

VFRQ

6

CELL

3

ACIN

5

ICOMP

7

VCOMP

8

VNEG

18

CSOP

17

CSON

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

1

1%

2

R7005

20

1 2

5% 1/16W MF-LF

402

R7001

4.7

1 2

5% 1/16W MF-LF

402

19

VDD

CRITICAL

U7000

(AGND)

29

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

20

VDDP

DCIN

SGATE AGATE

TQFN

CSIP CSIN

BOOT UGATE PHASE

ISL6259

LGATE

BGATE

AMON

20V/V

BMON

36V/V

ACOK

(OD)

THRM_PAD

PGND

353S2392

22

XW7000

SM

1 2

PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm

415

S

G

6

(CHGR_DCIN)

C7001

1UF

10% 10V X5R 402

2

CHGR_DCIN

26

CHGR_SGATE

1

CHGR_AGATE

28

CHGR_CSI_P

96

27

CHGR_CSI_N

96

25

CHGR_BOOT

24

CHGR_UGATE

23

CHGR_PHASE

21

CHGR_LGATE

16

CHGR_BGATE

9

CHGR_AMON

15

CHGR_BMON

14

SMC_BC_ACOK

(GND)

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

D

1

2

NC

10

2

S

G

3

Reverse-Current Protection

D

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

(CHGR_SGATE)(CHGR_AGATE)

1

C7020

0.047UF

10% 10V

2

CERM 402

1

C7022

0.1UF

10% 25V

2

X5R 402

PLACE_NEAR=U7000.25:2mm

49

44 45 48 62

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

OUT

1

C7025

0.22UF

10% 10V

2

CERM 402

4

R7021

1 2

R7022

1 2

1

C7021

0.1UF

10% 25V

2

X5R 402

5

1 23

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

1

R7080

100K

5% 1/16W MF-LF 402

2

1

R7081

62K

5% 1/16W MF-LF 402

2

10

5% 1/16W MF-LF

402

10

5% 1/16W MF-LF

402

4

CRITICAL

Q7035

RJK0305DPB

LFPAK-HF

R7051 R7052

CHGR_CSI_R_P

98

CHGR_CSI_R_N

98

5

D

G

S

1 23

1 2

2.2

1 2

0

3

CRITICAL

Q7030

RJK0332DPB-01

LFPAK-SM

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_PHASE_RC

DIDT=TRUE

NO STUFF

1

C7039

470PF

10% 50V

2

CERM 402

CHGR_CSO_R_P

49 98

5%

1/16W

MF-LF

CHGR_CSO_R_N

49 98

MF-LF

5%

1/16W

(PPVBAT_G3H_CHGR_R)

CRITICAL

214

R7020

0.020

0.5% 1W MF-LF 0612

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

Max Current = 8A (L7030 limit) f = 400 kHz

NO STUFF

R7039

180

1/10W MF-LF

402

1

5%

603

2

CRITICAL

1

C7030

22UF

20% 25V

2

POLY-TANT CASE-D2-SM

CRITICAL

L7030

3

4.7UH-10.2A

2

FDA1254F-SM

1

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

CRITICAL

R7050

0.005

1% 1W MF

0612

2 1 43

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

CRITICAL

1

C7031

22UF

20% 25V

2

POLY-TANT CASE-D2-SM

C7055

1UF

603-1

1

2

10% 25V X5R

1

C7035

1UF

10% 25V

2

X5R 603-1

CRITICAL

C7040

22UF

20% 25V POLY-TANT CASE-D2-SM

1

C7056

0.1UF

2

402-1

10% 16V X5R

1

C7036

1UF

10% 25V

2

X5R 603-1

1

C7057

2

1

C7045

0.001UF

10% 50V

2

X7R 402

0.01uF

2 1

1

C7037

0.001UF

10% 50V

2

X7R 402

CRITICAL

F7040

8AMP-24V

1 2

1206

CRITICAL

F7041

8AMP-24V

1 2

1206

CRITICAL

Q7055

SI7137DP

SO-8

10% 16V

CERM

402

S

1

2

1 23

D

5

G

4

TO SYSTEM

PPBUS_G3H

TO/FROM BATTERY

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

6 7 8

35 39 48 49 62 88

6

62

D

C

B

(CHGR_BGATE)

1

C7042

0.068UF

10% 10V

2

CERM 402

C7011

0.01UF

CERM

10% 16V

402

1

C7000

1UF

10% 10V

2

X5R 402-1

C7005

0.22UF

1

20% 25V

2

X5R 603

GND_CHGR_AGND

63

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

C7026

0.001UF

CERM

10% 50V

402

1

2

A

8 7 5 4 2 1

36

SYNC_MASTER=K91_CHANG

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=07/20/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

70 OF 132

SHEET

63 OF 101

SIZE

A

D

345678

2 1

D

PPVIN_S5_HS_COMPUTING_ISNS

7

49 66 67 68 69

PP5V_S0

6 7 8

22 41 46 51 53 67 68 69 71 72 86

88

101

1

R7101

2.2

5% 1/16W MF-LF

402

PP5V_S0_VCCSAS0_VCC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

C

CPU_VCCSASENSE

12

IN

72

IN

VCCSAS0_SREF

1

R7147

113K

1% 1/16W MF-LF 402

2

CERM-X5R

1000PF

5% 25V NP0-C0G 402

1

10% 16V

2

1

402

R7148

140K

1% 1/16W MF-LF 402

2

1

R7149

47.5K

1% 1/16W MF-LF 402

2

C7103

0.022UF

1

C7105

2

B

72

OUT

XW7101

1

C7102

2.2UF

10% 16V

2

X5R

PLACE_NEAR=C1763.2:3mm

603

12

IN

PVCCSA_EN

VCCSAS0_VO

VCCSAS0_OCSET

PVCCSA_PGOOD

VCCSAS0_RTN

VCCSAS0_FSEL

VCCSAS0_SET0

R7103

1/16W MF-LF

VCCSAS0_SET1

1

0

5%

402

2

SM

1

CPU_VCCSA_VID<1>

VCCSAS0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

10

7

12

11

14

13

2

19

VCC

U7100

ISL95870A

UTQFN

EN

CRITICAL

FB

OMIT_TABLE

SREF

VO

OCSET

PGOOD

4

RTN

FSEL

8

SET0

9

SET1

6

VID0

5

VID1

GND

3

XW7100

SM

1 2

PLACE_NEAR=U7100.3:1mm

PVCC

PGND

1

C7101

10UF

2

20

BOOT

UGATE

PHASE

LGATE

2

CRITICAL

20% 10V X5R 603

1815

17

16

1

VCCSAS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

R7130

1/10W MF-LF

VCCSAS0_VBST

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

VCCSAS0_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

VCCSAS0_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

VCCSAS0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

(VCCSAS0_OCSET)

(VCCSAS0_VO)

PART NUMBER

CRITICAL

C7119

1

C7130

1

0.22UF

0

5%

603

10% 10V

2

CERM 402

2

237

1

6

10UF

X5R-CERM

CRITICAL

8

4 5

QTY

IC,ISL95870A,PWM,2BIT-VID,RMOT-SNSE,20P

CRITICAL

1

C7120

10% 16V

2

X5R-CERM

0805

Q7100

SIZ700DT

POWERPAIR-6X3.7

R7141

1K

1% 1/16W MF-LF

402

DESCRIPTION

1

10UF

10% 16V

2

0805

CRITICAL

L7100

1.0UH-7.7A

1 2

FDV0630H-SM

1

C7140

2

1000PF

5%

25V

NP0-C0G

402

C7121

X7R-CERM

48 98

12

PLACE_NEAR=Q7100.2:1.5mm

1

0.1UF

10% 16V

2

402

PPVCCSA_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

VCCSAS0_CS_P

VCCSAS0_CS_N

1

R7142

1K

1% 1/16W MF-LF 402

2

REFERENCE DES

1

C7122

1000PF

5% 25V

2

NP0-C0G 402

CRITICAL

R7140

0.001

1%

1W MF-1 0612

1 2 34

OCP = R7141 x 8.5uA / R7140 OCP = 8.5A

CRITICAL

CRITICAL1353S3074 U7100

BOM OPTION

PPVCCSA_S0_REG

6A Max Output f = 300 kHz

7

12 15

D

C

B

VID1 VID0 Voltage

0 0 0.9V

1 0 0.8V

A

8 7 5 4 2 1

36

SYNC_MASTER=K91_ERIC SYNC_DATE=10/08/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

System Agent Supply

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

71 OF 132

SHEET

64 OF 101

SIZE

A

D

345678

2 1

D

PPVIN_S5_HS_OTHER_ISNS

7

49

100

PP5V_S3

6 7

29 31 41 42

43 45 65 66 71 81

Vout = 5.0V

14.4A MAX OUTPUT

C

CRITICAL

CASE-D3L-SM1

B

C7252

330UF

6.3V

POLY-TANT

1

20%

2

1

2

1

2

CRITICAL

1

C7271

0.001UF

10% 50V

2

X7R 402

CRITICAL

C7250

10UF

XW7222

P5VS3_VFB1_R

R7220

40.2K

1% 1/16W MF-LF 402

R7221

10K

1% 1/16W MF-LF 402

C7240

68UF

POLY-TANT

CASE-D2E-SM

1

20% 10V

2

X5R 805

SM

XW7220

CRITICAL

1

C7242

20% 16V

PLACE_NEAR=L7220.1:3mm

2

1

SM

68UF

2

POLY-TANT

CASE-D2E-SM

1

CRITICAL

L7220

2.2UH-14A-7.0M-OHM

PIMB104E2R2MS-SM

2

P5VS3_VSW

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

PLACE_NEAR=L7220.1:3mm

PLACE_NEAR=L7220.2:3mm

2

XW7221

SM

1

P5VS3_CSP1_R

1

C7241

1UF

20% 16V

10% 25V

2

X5R 603-1

NO STUFF

1

R7299

1

5% 1/10W MF-LF 603

2

P5VS3_SNUBR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

NO STUFF

C7299

0.0033UF

1

C7270

0.001UF

10% 50V

2

X7R 402

CSD58864Q5D

VIN

1

VSW

6 7 8

PGND

1

10% 50V

2

CERM

402

CRITICAL

Q7220

SON5X6

9

TG

TGR

BG

R7256

9.09K

1/16W MF-LF

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

1

C7224

0.1UF

10% 50V

2

X7R 603-1

3

P5VS3_TG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

4

5

402

C7218

0.1UF

R7247

5.11K

1

1%

2

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

1 2

10% 16V X5R

402-1

1% 1/16W MF-LF

402

D

PP5V_S3

6 7

100

C7200

1UF

10% 25V X5R

603-1

1

R7244

4.7

5% 1/16W MF-LF

402

2

GATE_NODE=TRUEMIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

GATE_NODE=TRUE

1

R7249

0

5% 1/16W

21

2

MF-LF 402

47PF

CERM

5%

50V

402

1

2

17 29 42 44 72

72

NO STUFF

1

R7237

20.0K

1% 1/16W MF-LF 402

2

29 31 41 42 43 45 65 66 71 81

1

2

NO STUFF

1

R7248

0

5% 1/16W MF-LF 402

2

P5VS3_VBST

DIDT=TRUE

P5VS3_DRVH

DIDT=TRUE

P5VS3_LL

DIDT=TRUE

P5VS3_DRVL

DIDT=TRUE

P5VS3_CSP1 P5VS3_CSN1

P5VS3_MODE P5VS3_VFB1 P5VS3_COMP1

PM_SLP_S4_L

IN

P5VS3_PGOOD

OUT

R7236

P5VS3_COMP1_R

1

C7236C7237

4700PF

10% 100V

2

CERM 402

10K

1/16W MF-LF

PP5V_S5

Vout = 5V 100mA MAX OUTPUT

CRITICAL

1

C7205

P5VP3V3_VREG3

P5VP3V3_VREF2

2

23

29

VIN

V5SW

6

SKIPSEL1

19

SKIPSEL2

14

OCSEL

31

1

32

30

DRVL1

7

CSP1

8

11

MODE

9

VFB1 VFB2

10

4 5

1

1%

402

2

CRITICAL

U7201

GND

28

VREG5

QFN

22

VREG3

VBST2VBST1

DRVH2DRVH1

DRVL2

TPS51980

CSP2 CSN2CSN1

COMP2COMP1

PGOOD2PGOOD1

THRM_PAD

33

13

VREF2

EN

SW2SW1

RF

EN2EN1

12

26

24

25

27

18 17

3 16 15

21 20

C7201

0.22UF

10% 10V

CERM

402

SMC_PM_G2_EN

P3V3S5_VBST

DIDT=TRUE

P3V3S5_DRVH

DIDT=TRUE

P3V3S5_LL

DIDT=TRUE

P3V3S5_DRVL

DIDT=TRUE

P3V3S5_CSP2 P3V3S5_CSN2

P3V3S5_RF P3V3S5_VFB2 P3V3S5_COMP2

P3V3S5_EN S5_PWRGD

NO STUFF

1

R7238

10K

1% 1/16W MF-LF 402

2

P3V3S5_COMP2_R

(P5VP3V3_VREF2)(P5VP3V3_VREF2)

1

C7203

2.2UF

20% 10V

2

X5R-CERM 402

44 72

IN

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

72

IN

44 72

OUT

R7239

7.5K

1/16W MF-LF

NO STUFF

C7238

4700PF

10% 100V CERM

402

10UF

20%

6.3V

2

X5R 603

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

R7263

5% 1/16W MF-LF

402

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

R7206

1

1%

402

2

1

2

C7239

330PF

10% 50V

2

CERM 402

0

249K

1/16W MF-LF

21

1%

402

6 7

53 71

C7264

0.1UF

603-1

P3V3S5_TG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE GATE_NODE=TRUE

C7288

0.22UF

1 2

10%

1

2

10V

CERM

402

R7246

511

1 2

1% 1/16W MF-LF

402

1

10% 50V

2

X7R

2

1

6

4

3

1

R7216

3.16K

1% 1/16W MF-LF 402

2

P3V3S5_CSP2_R

CRITICAL

Q7260

RJK0214DPA

WPAK2

7

5

1

2

CRITICAL

C7280

POLY-TANT

CASE-D2E-SM

NO STUFF

R7298

P3V3S5_SNUBR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

NO STUFF

C7298

0.001UF

10% 50V X7R 402

1

68UF

20% 16V

2

CRITICAL

L7260

2.2UH-14A

IHLP2525CZ-SM1

10

5% 1/10W MF-LF

603

XW7260

CRITICAL

C7282

POLY-TANT

CASE-D2E-SM

1

2

68UF

SM

1

C7281

1UF

20% 16V

10% 25V

2

X5R 603-1

PP3V3_S5

Vout = 3.3V

2

10A MAX OUTPUT f = 400 kHZf = 400 kHZ

C7272

1

PLACE_NEAR=L7260.1:3mm

2

1

0.001UF

CRITICAL

1

C7290

10UF

20%

6.3V

2

X5R 603

PLACE_NEAR=L7260.2:3mm

2

XW7262

SM

1

PLACE_NEAR=L7260.2:3mm

P3V3S5_VFB2_R

2

XW7261

SM

1

C7283

0.001UF

10% 50V

2

X7R 402

1

10% 50V

2

X7R 402

R7260

23.2K

1/16W MF-LF

R7261

1/16W MF-LF

402

10K

402

CRITICAL

1

C7292

330UF

20%

6.3V

2

POLY-TANT CASE-D3L-SM1

1

1%

2

1

1%

2

98 39 45 55 70 71 6 7

17 19 20

22 23 24 25 29

72 82 85 89

C

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K91_ERIC SYNC_DATE=10/08/2010

PAGE TITLE

5V / 3.3V Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

72 OF 132

SHEET

65 OF 101

SIZE

A

D

345678

2 1

D

PPVIN_S5_HS_COMPUTING_ISNS

7

49 64 67 68 69

CRITICAL

C7330

POLY-TANT

1

2

CASE-D2E-SM

(DDRREG_DRVH)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

CRITICAL

1

C7361

10UF

20%

6.3V

2

X5R 603

PLACE_NEAR=C3101.1:3mm

PP1V5_S3

6 7

26 28 29 66 71

DDRREG_FB

DDRREG_MODE

DDRREG_TRIP

1

R7318

47.5K

1% 1/16W MF-LF 402

2

CRITICAL

C7301

1

10UF

20% 10V

2

X5R 603

2

VLDOIN

12 15

V5IN

S3 S5

VREF

REFIN

MODE TRIP

TPS51916

CRITICAL

PGND

10

U7300

QFN

VTT

GND

7

4

PGOOD

VDDQSNS

VTTSNS

VTTREF

THRM

PADGND

21

17 16

6

8

19 18

XW7300

VBST DRVH

DRVL

VTT

SM

14 13

SW

11 20 9 3 1

5

2

1

DDRREG_VBST

DDRREG_DRVH

GATE_NODE=TRUE

DDRREG_LL

SWITCH_NODE=TRUE

DDRREG_DRVL

GATE_NODE=TRUE

TP_DDRREG_PGOOD

DDRREG_VDDQSNS

PP0V75_S0_DDRVTT

DDRREG_VTTSNS

30

PPVTTDDR_S3

6 7

10mA max load

C7350

0.22UF

PLACE_NEAR=U7300.7:1mm

CERM

MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

PLACE_NEAR=C7361.1:3mm

PLACE_NEAR=C3101.1:1mm

C7360, C7361 close to memory

1

10% 10V

2

402

89

OUT

XW7360

SM

1 2

CRITICAL

C7360

10UF

6.3V

20% X5R

603

PP5V_S3

6 7

100

29 31 41 42 43 45 65 71 81

CRITICAL

C7300

10UF

20% 10V X5R 603

1

2

C

MEMVTT_EN

8

29

IN

DDRREG_EN

72

IN

1

0.1UF

10% 16V X5R 402

1

2

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0V

C7315

B

R7315

20.0K

1% 1/16W MF-LF 402

2

1

R7316

100K

1% 1/16W MF-LF 402

2

1

C7316

0.01UF

10% 16V

2

CERM 402

1

R7317

200K

2

(VTT Enable)

(VDDQ/VTTREF Enable)

DDRREG_1V8_VREF

30

1% 1/16W MF-LF 402

68UF

20% 16V

1

2

CRITICAL

C7331

68UF

20% 16V

POLY-TANT

CASE-D2E-SM

R7330

4.7

1 2

5% 1/16W MF-LF

402

C7325

0.1UF

1 2

10% 50V X7R

603-1

(DDRREG_LL)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

1

2

DDRREG_DRVH_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

C7332

1UF

10% 25V X5R 603-1

1

C7333

0.001UF

10% 50V

2

X7R 402

CRITICAL

CSD58864Q5D

TG

3

TGR

4

BG

5

Q7330

SON5X6

9

1

C7334

1UF

10% 25V

2

X5R 603-1

VIN

VSW

PGND

1

6 7 8

DDRREG_VSW

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

CRITICAL

L7330

1.0UH-21A

1 2

FDU1040D-SM

CRITICAL

1

C7340

270UF

20% 2V

2

TANT CASE-B4-SM

CRITICAL

C7341

270UF

CASE-B4-SM

VOLTAGE=1.5V MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.8 MM

PPDDR_S3_REG_R

CRITICAL

1

20%

2V

2

TANT

2

C7345

10UF

20%

6.3V X5R 603

1

C7346

0.001UF

10% 50V

2

X7R 402

ISNS_1V5_S3_P

ISNS_1V5_S3_N

43

2 1

0612 MF-1

1W 1%

0.001

R7350

CRITICAL

2

XW7301

SM

1

PP1V5_S3

Vout = 1.5V 18A max output (Q7335 limit) f = 400 kHz

OUT

48 98

6 7

26 28 29 66 71

D

C

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K91_ERIC SYNC_DATE=10/08/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

1.5V DDR3 Supply

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

73 OF 132

SHEET

66 OF 101

SIZE

A

D

345678

2 1

PART NUMBER

QTY

353S3259

NO STUFF

1

C7419

100PF

5% 50V

2

CERM 402

PP5V_S0

1

C7403

2.2UF

20% 10V

2

X5R-CERM 402

6

OUT

68

OUT

68

OUT

68

OUT

67

OUT

67

R7402

90.9K

1

1% 1/16W MF-LF

402

68

NO STUFF

1

C7414

100PF

5% 50V

2

CERM 402

2

D

R7401

10

31

39

5

19 10

1

16 18 17

33 34

32

29 30

1 2

1/16W MF-LF

40

VCC

U7400

MAX17511

DRVPWMA

OMIT_TABLE

CRITICAL

CSPA3 VRHOT*

POKA POKB

EN

VDIO CLK ALERT*

THERMA THERMB

SR

IMAXA IMAXB

GNDSA

3

5%

402

QFN

GNDSB

7

24

VDDA

BSTA1

CSPA1

CSPAAVE

CSPA2 BSTA2

CSPB1

41

15

VDDB

2

TON

20

22

DHA1

21

LXA1

23

DLA1

36

35 37

68

CSNA

4

FBA

38 28 26

DHA2

27

LXA2

25

DLA2

11

BSTB

13

DHB

12

LXB

14

DLB

8

9

CSNB

6

FBB

PAD

THRM

XW7400

SM

1

C7402

2.2UF

20% 10V

2

X5R-CERM 402

CPUIMVP_TON

CPUIMVP_BOOT1 CPUIMVP_UGATE1 CPUIMVP_PHASE1 CPUIMVP_LGATE1 CPUIMVP_ISUM1_P

CPUIMVP_ISUM CPUIMVP_ISUM_N CPUIMVP_FBA

CPUIMVP_ISUM2_P CPUIMVP_BOOT2 CPUIMVP_UGATE2 CPUIMVP_PHASE2 CPUIMVP_LGATE2

CPUIMVP_BOOT1G CPUIMVP_UGATE1G CPUIMVP_PHASE1G CPUIMVP_LGATE1G

CPUIMVP_ISUMG_P CPUIMVP_ISUMG_N CPUIMVP_FBB

NO STUFF

1

C7418

100PF

5% 50V

12

2

CERM 402

PLACE_NEAR=U7400.24:2mm PLACE_NEAR=U7400.15:2mm

PP5V_S0_CPUIMVP_VCC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

C

101

10 12 13 14 16 17 20 22 23 35 39

PP1V05_S0

6 7 9 44 69 72

PLACE_NEAR=U7400.18:2mm

CPUIMVP_VR_ON

72

IN

CPU_VIDSOUT

12 90

IN

CPU_VIDSCLK

12 90

IN

CPU_VIDALERT_L

12 90

IN

R7479

54.9

1/16W MF-LF

1

R7480

130

1%

1% 1/16W MF-LF

402

2

PLACE_NEAR=U7400.16:2mm

68

OUT

67 68

10 45 90

OUT

89

OUT

89

OUT

2.2UF

X5R-CERM

1

20% 10V

2

402

C7401

CPUIMVP_PWM3

CPUIMVP_ISUM3_P CPU_PROCHOT_L

CPUIMVP_PGOOD CPUIMVP_AXG_PGOOD

CPUIMVP_NTC CPUIMVP_NTCG

CPUIMVP_SLEW

CPUIMVP_IMAXA

1

R7468

5.76K

1% 1/16W MF-LF 402

2

1

CRITICAL

R7469

100KOHM

0402

B

2

1

R7466

5.76K

1% 1/16W MF-LF 402

2

1

CRITICAL

R7467

100KOHM

0402

2

OMIT

1

R7464

NOSTUFF

NONE NONE NONE 402

2

1

R7465

200K

1% 1/16W MF-LF 402

2

1

R7462

215K

1% 1/16W MF-LF 402

2

1

R7463

137K

1% 1/16W MF-LF 402

2

1

R7460

215K

1% 1/16W MF-LF 402

2

1

R7461

137K

1% 1/16W MF-LF 402

2

CPUIMVP_IMAXB

6 7 8

22 41 46 51 53 64 68 69 71 72 86 88

101

PPVIN_S5_HS_COMPUTING_ISNS

SIGNAL_MODEL=EMPTY

NO STUFF

1

C7415

100PF

5% 50V

2

CERM 402

NO STUFF

1

C7416

100PF

5% 50V

2

CERM 402

1

C7404

2200PF

5% 10V

2

CERM 0402

SIGNAL_MODEL=EMPTY

1

C7405

2200PF

5% 10V

2

CERM 0402

OUT

DESCRIPTION

IC,MAX15092,3+1PH CPU REG,IMVP7,5X5QFN40

7

49 64 66 68 69

SIGNAL_MODEL=EMPTY

C7408

150PF

68

OUT

1

C7406

2200PF

5% 10V

2

CERM 0402

CPUIMVP_ISUM3_P

68

NO STUFF

1

C7417

100PF

5% 50V

2

CERM 402

1

5%

50V

CERM

402

C7409

2

NO STUFF

470PF

1 2

10% 50V

CERM

402

REFERENCE DES

CPUIMVP_ISUM_R

R7410

1 2

1/16W

NO STUFF

R7409

40.2K

1 2

1/16W MF-LF

SIGNAL_MODEL=EMPTY

1

C7407

0.001UF

10% 50V

2

CERM 402

SIGNAL_MODEL=EMPTY

MF-LF

1%

67 68

402

CRITICAL

BOM OPTION

CRITICALU74001

D

R7406

300

1 2

5% 1/16W MF-LF

402

R7407

300

1 2

5% 1/16W MF-LF

402

R7408

300

1 2

5% 1/16W MF-LF

402

CPUIMVP_ISNS1_P

CPUIMVP_ISNS2_P

CPUIMVP_ISNS3_P

49 68

IN

49 68

IN

C

49 68

IN

1

5%

402

68

OUT

68

OUT

B

GND_CPUIMVP_SGND PLACE_NEAR=Q7510.1:1mm PLACE_NEAR=Q7550.1:1mm

A

8 7 5 4 2 1

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

SIGNAL_MODEL=EMPTY

1

C7441

1000PF

5% 25V

2

NP0-C0G 402

SIGNAL_MODEL=EMPTY

1

C7440

1000PF

5% 25V

2

NP0-C0G 402

CPU_AXG_SENSE_R

CPU_VCCSENSE_R

OMIT

1

C7442

NOSTUFF

NONE NONE

2

NONE 402

R7440

10

1 2

5% 1/16W MF-LF

402

R7441

10

1 2

5%

OMIT

1

C7443

NOSTUFF

NONE NONE

2

NONE 402

1/16W MF-LF

402

SIGNAL_MODEL=EMPTY

CPU_AXG_SENSE_N

CPU_VCCSENSE_N

SIGNAL_MODEL=EMPTY

1

C7412

1000PF

5%

12 90

IN

CPUIMVP_FBA

67

12 90

IN

CPUIMVP_FBB

67

R7412

12.7K

1 2

1% 1/16W MF-LF

402

R7422

8.06K

1 2

1% 1/16W MF-LF

402

25V

2

NP0-C0G 402

CPUIMVP_FBA_R

SIGNAL_MODEL=EMPTY

C7422

1000PF

25V

NP0-C0G

402

CPUIMVP_FBB_R

SYNC_MASTER=K91_ERIC SYNC_DATE=10/08/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

R7413

10

1 2

5% 1/16W MF-LF

402

1

5%

2

R7423

10

1 2

5% 1/16W MF-LF

402

CPU IMVP7 & AXG VCore Regulator

Apple Inc.

R

CPU_VCCSENSE_P

CPU_AXG_SENSE_P

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

12 90

IN

12 90

IN

74 OF 132

67 OF 101

SIZE

A

D

36

PPVIN_S5_HS_COMPUTING_ISNS

7

49 64 66 67 68 69

CRITICAL

1

C7513

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CRITICAL

L7510

PIMA104E-SM

152S1019

1

5%

2

1

2

G

56

CRITICAL

D

Q7510

IRF6723M2DPBF

DIRECTFET-MA

S

4

0.36UH-20%-40A-0.00075OHM

PPVCORE_S0_CPU_PH1_L

NOSTUFF

R7512

2.2

1/10W MF-LF

603

7621

CRITICAL

D

Q7515

IRF6798MTRPBF

DIRECTFET-MX

S

43

376S0872

PHASE 1

CPUIMVP_BOOT1_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

D

CPUIMVP_BOOT1

6

67

IN

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

67

CPUIMVP_UGATE1

IN

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1

IN

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1

IN IN

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

1

R7511

0

5% 1/16W MF-LF

402

2

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

1

C7511

0.22UF

10% 10V

2

CERM 402

3

5

376S0930

CRITICAL

1

C7514

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

PPVCORE_S0_CPU_PH1

21

CPUIMVP_ISNS1_P CPUIMVP_ISNS1_N

49 67 49

CPUIMVP_PH1_SNUB

NOSTUFF

C7512

0.001UF

10% 50V CERM 402

DIDT=TRUE

CRITICAL

1

C7515

10UF

10% 16V

2

X5R-CERM 0805

R7513

46.4

1/16W MF-LF

CRITICAL

1

C7516

10UF

10% 16V

2

X5R-CERM 0805

R7510

0.00075

1%

402

CRITICAL

1% 1W MF

0612

1

2

THESE TWO CAPS ARE FOR EMC

1

2

21 43

1

R7514

10.2

1% 1/16W MF-LF 402

2

1

C7517

1UF

10% 16V X5R 402

C7518

0.001UF

10% 50V

2

X7R 402

PPVCORE_S0_CPU

CPUIMVP_ISUM_N

NOSTUFF

1

C7571

330PF

10% 50V

2

CERM 402

1

C7519

0.001UF

10% 50V

2

X7R 402

CPUIMVP_ISUM1_P

67 68

67

12 14 48 68 6 7

67

101

CPUIMVP_BOOT2

IN

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE2

IN

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE2

IN

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE2

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

PHASE 2

CPUIMVP_BOOT2_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

1

R7521

0

5% 1/16W MF-LF

402

2

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

1

C7521

0.22UF

10% 10V

2

CERM 402

376S0872

376S0930

345678

CRITICAL

1

78

CRITICAL

D

G

2

G

5

Q7510

IRF6723M2DPBF

DIRECTFET-MA

S

1

0.36UH-20%-40A-0.00075OHM

PPVCORE_S0_CPU_PH2_L

NOSTUFF

R7522

2.2

1/10W MF-LF

603

7621

CRITICAL

D

Q7525

IRF6798MTRPBF

DIRECTFET-MX

S

43

C7523

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CRITICAL

L7520

PIMA104E-SM

152S1019

1

5%

2

CPUIMVP_PH2_SNUB

1

2

CRITICAL

1

C7524

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

PPVCORE_S0_CPU_PH2

21

NOSTUFF

C7522

0.001UF

10% 50V CERM 402

CPUIMVP_ISNS2_P

49 67

DIDT=TRUE

2 1

CRITICAL

1

C7525

10UF

10% 16V

2

X5R-CERM 0805

R7523

46.4

1/16W MF-LF

402

CRITICAL

1

C7526

10UF

10% 16V

2

X5R-CERM 0805

CRITICAL

R7520

0.00075

1% 1W MF

0612

1 2 34

1

1%

2

THESE TWO CAPS ARE FOR EMC

1

2

C7527

1UF

10% 16V X5R 402

1

C7528

0.001UF

10% 50V

2

X7R 402

PPVCORE_S0_CPU

CPUIMVP_ISNS2_N

49

1

R7524

10.2

1% 1/16W MF-LF 402

2

CPUIMVP_ISUM_N

1

2

CPUIMVP_ISUM2_P

NOSTUFF

C7572

330PF

10% 50V CERM 402

1

C7529

0.001UF

10% 50V

2

X7R 402

12 14 48

101

D

6 7 68

67 68

67

CRITICAL

Q7530

376S0772

C

22 41 46 51 53 64 67 69 71 72 86

6 7 8 88

101

PP5V_S0

1

2

R7547

10K

5% 1/16W MF-LF 402

67

CPUIMVP_PWM3

IN

CPUIMVP_SKIP

2

PWN

6

SKIP*

5

VDD

U7541

MAX17491

TQFN

CRITICAL

THRM

GND

PAD

3

9

BST

1

C7541

1UF

10% 16V

2

X5R 402

1

8

DH

7

LX

4

DL

CPUIMVP_BOOT3

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE3

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE3

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE3

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

PHASE 3

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_BOOT3_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

1

R7531

0

5% 1/16W MF-LF

402

2

1

C7531

0.22UF

10% 10V

2

CERM 402

376S0930

IRF6710

S1

D

4 6

G

S

3

SWITCH_NODE=TRUE

5

G

PPVCORE_S0_CPU_PH3_L

D

S

43

1

2

5

0.36UH-20%-40A-0.00075OHM

NOSTUFF

R7532

2.2

1/10W MF-LF

603

7621

CRITICAL

Q7535

IRF6798MTRPBF

DIRECTFET-MX

CRITICAL

1

C7533

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CRITICAL

L7530

PIMA104E-SM

152S1019

1

5%

2

1

2

B

PPVIN_S5_HS_COMPUTING_ISNS

7

49 64 66 67 68 69

CRITICAL

1

C7553

68UF

20% 16V

AXG PHASE

CRITICAL

Q7550

R7556

0

21

CPUIMVP_BOOT1G_R

MIN_LINE_WIDTH=0.25 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

DIDT=TRUE

MF-LF

CPUIMVP_BOOT1G

67

IN

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUIMVP_UGATE1G

67

IN

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1G

67

IN

MIN_LINE_WIDTH=1.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1G

67

IN

A

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE GATE_NODE=TRUE

402

R7555

4.7

21

5% 1/16W MF-LF

402

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_UGATE1G_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE GATE_NODE=TRUE

C7551

0.22UF

CERM

10% 10V

402

1

2

CSD58864Q5D

TG

3

TGR

4

BG

5

SON5X6

PGND

9

376S0906

VIN

VSW

1

6 7 8

2

POLY-TANT CASE-D2E-SM

CPUIMVP_VSWG

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

SWITCH_NODE=TRUE

CRITICAL

1

C7554

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

0.36UH-20%-40A-0.00075OHM

NOSTUFF

1

R7552

2.2

5% 1/10W MF-LF 603

2

CPUIMVP_AXG_SNUB

NOSTUFF

1

C7552

0.001UF

10% 50V

2

CERM 402

CRITICAL

1

C7555

2

CRITICAL

L7550

PIMA104E-SM

DIDT=TRUE

10UF

10% 16V X5R-CERM 0805

CRITICAL

1

C7556

10UF

10% 16V

2

X5R-CERM 0805

PPVCORE_S0_AXG_L

21

152S1019

CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N

49 98 49 98

THESE TWO CAPS ARE FOR EMC

C7557

1UF

10% 16V X5R 402

R7553

46.4

1/16W MF-LF

402

CRITICAL

R7550

0.00075

1

1%

2

1

C7558

0.001UF

10% 50V

2

X7R 402

1% 1W MF

0612

21 43

1

2

1

2

1

C7559

0.001UF

10% 50V

2

X7R 402

PPVCORE_S0_AXG

R7554

10.2

1% 1/16W MF-LF 402

CPUIMVP_ISUMG_N

NOSTUFF

1

C7574

330PF

10% 50V

2

CERM 402

CPUIMVP_ISUMG_P

67

CRITICAL

1

C7534

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

PPVCORE_S0_CPU_PH3

21

CPUIMVP_ISNS3_P

49 67

CPUIMVP_PH3_SNUB

NOSTUFF

C7532

0.001UF

10% 50V CERM 402

DIDT=TRUE

CRITICAL

1

C7561

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

Additonal Input Bulk Caps

7

12 13 15 48

CRITICAL

1

C7535

10UF

10% 16V

2

X5R-CERM 0805

8 7 5 4 2 1

R7533

CRITICAL

1

C7562

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

46.4

1/16W MF-LF

402

CRITICAL

1

C7536

10UF

10% 16V

2

X5R-CERM 0805

CRITICAL

R7530

0.00075

1

1%

2

36

1% 1W MF

0612

CRITICAL

1

C7563

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

THESE TWO CAPS ARE FOR EMC

1

2

2 43

CPUIMVP_ISNS3_N

49

1

R7534

10.2

1% 1/16W MF-LF 402

2

1

C7537

1UF

10% 16V X5R 402

C7538

0.001UF

10% 50V

2

X7R 402

PPVCORE_S0_CPU

CPUIMVP_ISUM_N

1

2

CPUIMVP_ISUM3_P

CRITICAL

1

C7564

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

NOSTUFF

C7573

330PF

10% 50V CERM 402

1

2

CRITICAL

1

C7565

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

C7539

0.001UF

10% 50V X7R 402

67 68

67

6 7

12 14 48 68

101

CRITICAL

1

C7566

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

SYNC_MASTER=K91_ERIC SYNC_DATE=09/22/2010

PAGE TITLE

CRITICAL

1

C7567

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CRITICAL

1

C7568

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CRITICAL

1

C7569

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

CPU IMVP7 & AXG VCore Output

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

REVISION

BRANCH

PAGE

75 OF 132

SHEET

68 OF 101

SIZE

C

B

A

D

345678

2 1

D

CPU VCCIO (1.05V S0) Regulator

PPVIN_S5_HS_COMPUTING_ISNS

7

49 64 66 67 68

PP5V_S0

6 7 8

22 41 46 51 53 64 67 68 71 72 86

88

101

1

R7601

2.2

5% 1/10W MF-LF

C

CPU_VCCIOSENSE_P

12 90

CPU_VCCIOSENSE_N

12 90

1

R7604

3.01K

1/16W MF-LF

R7605

2.74K

1/16W MF-LF

B

R7644

3.01K

1%

1/16W MF-LF 402

402

2

<Ra>

1

R7645

2.74K

1%

1/16W MF-LF 402

402

2

<Rb>

1

C7604

47PF

CERM

50V

402

1

C7605

5%

47PF

5% 50V

2

CERM 402

C7602

1

C7603

0.047UF

10% 16V

2

X7R 402

72

2.2UF

PP5V_S0_CPUVCCIOS0_VCC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

IN

CPUVCCIOS0_EN

CPUVCCIOS0_FB

CPUVCCIOS0_SREF

CPUVCCIOS0_VO

CPUVCCIOS0_OCSET

OUT

CPUVCCIOS0_PGOOD

CPUVCCIOS0_RTN

CPUVCCIOS0_FSEL

1

R7603

1

0

10% 16V X5R 603

5% 1/16W

2

MF-LF 402

2

CPUVCCIOS0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

603

2

13

VCC

U7600

ISL95870

3

6

4

8

7

9

2

5

UTQFN

EN

CRITICAL

FB

SREF

VO

OCSET

PGOOD

RTN

FSEL

GND

1

XW7600

SM

PLACE_NEAR=U7600.1:1mm

CRITICAL

1

2

14

PVCC

BOOT

UGATE

PHASE

LGATE

PGND

16

21

C7601

10UF

20% 10V X5R 603

12

11

10

15

CPUVCCIOS0_VBST

CPUVCCIOS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

1

R7630

2.2

5% 1/10W MF-LF

603

2

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

CPUVCCIOS0_DRVH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

CPUVCCIOS0_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

CPUVCCIOS0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

(CPUVCCIOS0_OCSET)

(CPUVCCIOS0_VO)

OCP = R7641 x 8.5uA / R7640 OCP = 25.6A Vout = 0.5V * (1 + Ra / Rb)

1

C7630

1UF

10% 16V

2

X5R 402

CRITICAL

C7620

POLY-TANT

CASE-D2E-SM

5

68UF

20% 16V

CRITICAL

1

C7621

2

POLY-TANT

CASE-D2E-SM

68UF

20% 16V

1

C7622

1000PF

5% 25V

2

NP0-C0G 402

PLACE_NEAR=Q7630.1:1.5mm

C

CRITICAL

1

5

D

S

1 23

32

Q7630

RJK0365DPA-01

WPAK

CRITICAL

L7630

0.68UH-22A-2.7MOHM

1 2

PIMB104T-SM

CRITICAL

Q7635

RJK0208DPA

WPAK

1

R7641

3.01K

1% 1/16W MF-LF

C7640

402

2

1000PF

2 1

5%

25V

NP0-C0G

402

PPCPUVCCIO_S0_REG_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

CPUVCCIOS0_CS_P

48 98

CPUVCCIOS0_CS_N

48 98

1

R7642

3.01K

1% 1/16W MF-LF 402

2

CRITICAL

R7640

0.001

1%

1W MF-1 0612

12 3

4

PLACE_NEAR=L7630.2:1.5mm

C7623

1000PF

NP0-C0G

25V 402

101 35 39 44

PP1V05_S0

NO STUFF

CRITICAL

C7649

1

5%

2

NO STUFF

1

2

CASE-B4-SM

CRITICAL

C7648

270UF

20% 2V TANT CASE-B4-SM

270UF

Vout = 1.05V 21A Max Output

1

f = 300 kHz

20%

2V

2

TANT

16 17 20 6 7 9 12 13 14

22 23 67 72

10

B

4

G

4

A

PAGE TITLE

CPU VCCIO (1.05V) Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=10/08/2010SYNC_MASTER=K91_ERIC

DRAWING NUMBER

REVISION

BRANCH

PAGE

76 OF 132

SHEET

69 OF 101

SIZE

A

D

345678

2 1

72 82 85 89 98

PP3V3_S5

6 7

17 19 20 22 23

24 25 29 39 45 55 65 70 71

CRITICAL

1

C7724

1000PF

5%

25V

2

NP0-C0G

402

72

D

IN

72

OUT

C7720

P1V8S0_EN

P1V8S0_PGOOD

22UF

6.3V CERM

1

20%

2

805

ISL8014A

5 14

EN

7

PG

4

SYNCH

SGND

9

10

1

2

VIN

U7720

QFN

CRITICAL

PGND

11

12

3

VDD

THRM_PAD

17

VFB

LX LX

NC

Vout = 0.8V * (1 + Ra / Rb)

C

1.8V S0 Regulator

152S1302

L7720

1.0UH-7A

PIMB053T-SM

P1V8S0_SW

SWITCH_NODE=TRUE

15

DIDT=TRUE

8

P1V8S0_FB

16

NC

6

NC

13

NC

1 2

CRITICAL

R7720

113K

1/16W MF-LF

<Ra>

R7721

90.9K

1/16W MF-LF

<Rb>

402

1

1%

402

2

1

1%

2

1

C7723

47PF

5% 50V

2

CERM 402

CRITICAL

1

C7721

22UF

20%

6.3V

2

CERM 805

CRITICAL

C7722

22UF

PP1V8_S0

Vout = 1.794V Max Current = 4A Freq = 1 MHz

1

20%

6.3V 2

CERM

805

6 7

14 17 20 22 25 71 87

1.05V SUS LDO

Cougar Point-M requires JTAG pull-ups to be powered at 1.05V in Sus. Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage dividers (200/100) to 3.3V Sus, which burns 100mW in all S-states.

CRITICAL

XDP_PCH

U7740

7

16 17 18 19 20 22 45 71 72

PP3V3_SUS

XDP_PCH

C7740

1UF

6.3V CERM

1

10%

2

402

4

6

3

BIAS

IN

EN

TPS720105

SON

5

THRM

PADGND

7

OUT

PP1V05_SUS

Vout = 1.05V

1

Max Current = 0.35A

2

NC

XDP_PCH

1

C7741

2.2UF

10%

6.3V

2

X5R 402

D

7

23

C

1.5V S0 Regulator

98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

CRITICAL

1

8

6

54

C7750

22UF

20%

6.3V

2

CERM 805

1V5_S0_SW

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

1V5_S0_FB

CRITICAL

L7770

2.2UH-3.25A

1 2

IHLP1616BZ-SM

C7776

47PF

CERM

1

R7780

1

100K

1%

5%

50V

402

1/16W

2

MF-LF 402

2

<Ra>

1

R7781

113K

1% 1/16W MF-LF 402

2

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

PP1V5_S0

Vout = 1.508V

Max Current = 0.8A

Freq = 1.6MHZ

CRITICAL

1

C7771

22UF

20%

6.3V

2

CERM 805

7

16 20 22 25 41 56

PP3V3_ENET

6 7

25 36 72

CAESAR IV 1.2V INT.VR CMPTS

CRITICAL

L7730

4.7UH-0.8A

1 2

1

C7737

4.7UF

20%

6.3V

2

X5R 402

1

C7738

0.1UF

10% 16V

2

X5R 402

PCAA031B-SM

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V

SWITCH_NODE=TRUE DIDT=TRUE

PP1V2_ENET

ENET_SR_LX

PP1V2_ENET

36

B

6 7

36 70

6 7

36 70

1

VIN

U7710

ISL8009B

DFN

353S2535

2

EN

CRITICAL

3

POR

SKIP

GND

7

THRM_PAD

9

LX

VFB

RSI

72

IN

OUT

P1V5S0_EN

P1V5S0_PGOOD

B

CRITICAL

1

PP3V3_S5

72 82 85 89 98 6 7

17 19 20 22 23 24

25 29 39 45 55 65 70 71

A

NO STUFF

1

R7760

0

5% 1/16W MF-LF 402

2

CRITICAL

1

C7760

10UF

20% 4V

2

X5R 402

72

1

2

IN

C7764

0.1UF

10% 16V X5R 402

P1V2S0_EN

P1V2S0_SYNC_PWM

1

R7761

0

5% 1/16W MF-LF 402

2

8 7 5 4 2 1

1.2V S0 (GMUX) Regulator

CRITICAL

U7760

SC194A

1

VIN

353S2719

4

EN

3

SYNC/PWM

6

VID0

7

VID1

2

MODE

GND PAD

8

MLP10

PGND

10

P1V2S0_SW

LX

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

5

VOUT

P1V2S0_FB

THRM

9

11

152S0771

2.2UH-1.2A

PCAA031B-SM

1 2

SWITCH_NODE=TRUE DIDT=TRUE

XW7761

SM

1 2

CRITICAL

L7760

PLACE_NEAR=L7760.2:1MM

1

2

CRITICAL

C7761

PP1V2_S0

Vout = 1.2V MAX CURRENT = 0.7A FREQ = 1MHZ

22UF

20%

6.3V CERM 805

6 7

87

36

C7735

10UF

20% 4V

2

X5R 402

1

C7736

0.1UF

10% 16V

2

X5R 402

SYNC_MASTER=K91_ERIC

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=11/01/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

77 OF 132

SHEET

70 OF 101

SIZE

A

D

345678

R7803

0

12

5% 1/16W MF-LF

402

1

PP3V3_S4

7

3.3V S4 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

1

PP3V3_S3

6 7 8 47 48 49 53 54 72 87

3.3V S3 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

APN 376S0651

5

CRITICAL

D

Q7801

4

G

SI7108DN

PWRPK-1212-8-HF

S

1 23

PP1V5_S3RS0_CPUDDR

1.5V S3/S0 FET

89

OUT

MOSFET

CHANNEL

RDS(ON)

LOADING

NCP4543

N-TYPE

18 mOhm @4.5V

2.4A (EDP)

6 7

14 17 20 22 25 70 87

5V_SUS FET inuot filter

R7843

0

PP5V_S5

PLACE_NEAR=Q7840.4:5mm

1 2

5% 1/16W MF-LF

402

PP5V_S5_P5VSUSFET_R

45 52 53

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

0.7? A (EDP)

18 19 24 25 29 30 31 32

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

3 A (EDP)

SI7108DN

N-TYPE

6 mOhm @4.5V

5 A (EDP)

1

C7843

2.2UF

20% 10V

2

X5R-CERM

402

NO STUFF

7

10 13 15 29 72

98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

1

R7822

3

Q7802

SSM6N15FEAPE

PM_SUS_EN

71 72

IN

PP5V_S5_P5VSUSFET_R

71

Q7842

SSM3K15FV

SOD-VESM-HF

PM_SUS_EN

71 72

IN

98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

Q7812

SSM6N15FEAPE

PM_SLP_S3_R_L

48 71 72

IN

98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

D

SOT563

5

SG

4

3

D

1

G S

2

3

D

SOT563

5

SG

4

R7872

1/16W MF-LF

51K

402

R7842

R7832

1

5%

2

100K

220K

47K

1/16W MF-LF

402

5%

2

P3V3SUS_EN_L

1

5%

2

P5VSUS_EN_L

1

2

P3V3S0_EN_L

P3V3GPU_EN_L

Q7872

SSM3K15FV

SOD-VESM-HF

P3V3GPU_EN

87 89

IN

PP5V_S3

6 7

100

29 31 41 42 43 45 65 66 81

1

G S

R7862

220K

3

D

2

1

5% 1/16W MF-LF

402

2

P5V0S0_EN_L

Q7865

48 71 72

IN

PM_SLP_S3_R_L

SSM3K15FV

SOD-VESM-HF

1

G S

3

D

2

3.3V S4 FET

98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

D

P3V3_S4_EN

72

IN

Q7802

SSM6N15FEAPE

D

SOT563

2

SG

1

220K

1/16W MF-LF

5%

402

2

P3V3S4_EN_L

NOSTUFF

1

R7802

6

C7809

0.033UF

NOSTUFF

R7800

1 2

NOSTUFF

5.1K

5% 1/16W MF-LF

402

1

10% 16V

2

X5R 402

P3V3S3_S4

3.3V S3 FET

98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

1

R7812

6

SOT563

D

2

SG

1

Q7812

SSM6N15FEAPE

P3V3S3_EN

72

IN

100K

1/16W MF-LF

5%

402

2

P3V3S3_EN_L

1 2

C

C7811

0.033UF

R7810

47K

5% 1/16W MF-LF

402

1

10% 16V

2

X5R 402

P3V3S3_SS

NOSTUFF

4 7

SIA427DJ

4 7

376S0945

CRITICAL

Q7800

SIA427DJ

SC70-6L

S

G

3

NOSTUFF

C7800

0.01UF

CRITICAL

Q7810

SC70-6L

S

G

3

C7810

0.01UF

1 2

10% 16V

CERM

402

D

10% 16V

CERM

402

D

1.5V S3/S0 FET

PP1V5_S3

6 7

0.1UF

26 28 29 66

1

20% 10V

2

CERM

402

2

3

1

VCC

U7801

SLG5AP020

TDFN

ON

CRITICAL

SHDN*

GND

4

THRM

PAD

9

5

D

7

G

6

S

8

PG

P1V5S3RS0FET_GATE

R7801

0

5% 1/16W MF-LF

402

21

P1V5S3RS0FET_GATE_R

TP_P1V5S3RS0_RAMP_DONE

PP5V_S5

6 7

53 65 71

C7801

P1V5CPU_EN

29

IN

NO STUFF

1

C7802

1UF

10% 10V

2

X5R

402

B

1.8V GPU FET

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

PLACE_NEAR=U7880.2:2.54mm

PP1V8_GPUIFPX

6 7

71

100

load side

P1V8GPU_EN

89

IN

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

A

C7881

NO STUFF

0.1UF

20% 10V

CERM

402

GPUFET_C_DELAY

1

2

C7882

1000PF

NO STUFF

1

C7880

0.1UF

20% 10V

2

CERM

402

GPUFET_C_SR

1

5%

25V

2

NP0-C0G

402

PP1V8_GPUIFPX

353S3256

2

VCC

U7880

NCP4543IMN5RG-A

6 7 8

13

R_BLEED

15 12

EN

16

EN_POL_CTRL

1

C_DELAY

17

C_SR

SOURCE

6 7

71

100

QFN

CRITICAL

GND

3

THRM

PAD

DRAIN

NC

19

1.8V GPU FET

MOSFET

CHANNEL

PP1V8_S0

input side

RDS(ON)

LOADING

6 7

53 65 71 71

4 5 9 10 11

14 18

U7880 default Turn on delay EN--> on is 200~650us.

8 7 5 4 2 1

3.3V_SUS FET

C7821

0.033UF

R7820

12K

1 2

5% 1/16W MF-LF

402

5V_SUS FET

C7841

0.033UF

R7840

3.3K

1 2

5% 1/16W MF-LF

402

3.3V S0 FET

C7831

0.033UF

R7830

33K

1 2

5%

1/16W MF-LF

402

3.3V S0 GPU FET

1

C7871

1UF

10% 10V

2

X5R 402

R7870

1K

1 2

5% 1/16W MF-LF

402

5.0V S0 FET

1

C7861

0.033UF

10% 16V

2

X5R 402

R7860

10K

1 2

5% 1/16W MF-LF

402

36

1

10% 16V

2

X5R 402

1

10% 16V

2

X5R 402

1

10% 16V

2

X5R

402

P3V3S0_SS

P3V3GPU_SS

P5V0S0_SS

P3V3SUS_SS

P5VSUS_SS

4 7

S

1 23

CRITICAL

Q7870

SIA427DJ

S

3

CRITICAL

Q7860

SI7615DN

PWRPK-1212-8

G

4

2 1

CRITICAL

Q7820

SIA427DJ

SC70-6L

4 7

CRITICAL

Q7840

SIA413DJ

4 7

CRITICAL

Q7830

SI7615DN

PWRPK-1212-8

S

1 23

SC70-6L

G

C7870

0.01UF

1 2

10% 16V

CERM

402

C7860

0.01UF

1

S

3

SC70-6L

S

3

G

4

10% 16V

CERM

402

1

D

G

C7820

0.01UF

1 2

10% 16V

CERM

402

D

G

C7840

0.01UF

1 2

10% 16V

CERM

402

C7830

0.01UF

1 2

10% 16V

CERM

402

1

D

5

2

SYNC_MASTER=K91_MARY SYNC_DATE=10/14/2010

PAGE TITLE

1

D

5

PP3V3_S0GPU

PP5V_S0

PP3V3_SUS

MOSFET

CHANNEL

RDS(ON)

LOADING

PP5V_SUS

MOSFET

CHANNEL

RDS(ON)

LOADING

PP3V3_S0

MOSFET

CHANNEL

RDS(ON)

LOADING

3.3V S0 GPU FET

MOSFET

CHANNEL

RDS(ON)

LOADING

5.0V S0 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

7

16 17 18 19 20 22 45 70 72

3.3V SUS FET

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

100? mA (EDP)

7

22

5V SUS FET

SiA413

P-TYPE 12V

29 mOhm @4.5V

2 mA (EDP)

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

3.3V S0 FET

SI7615DN

P-TYPE 20V/12V

5.5 mOhm @4.5V

5.6 A (EDP)

6 7

74 78 79 81 83

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

0.11A (EDP)

6 7 8

22 41 46 51 53 64 67 68 69 72 86 88

101

SI7615DN

P-TYPE 20V/12V

5.5 MOHM @4.5V

8 A (EDP)

Power FETs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

78 OF 132

SHEET

71 OF 101

SIZE

D

C

B

A

D

C

B

A

44 65 72

OUT

44 65 72

IN

25 42 44 45 46 47 52

ALL_SYS_PWRGD

23 44 72 87 89

98 72 79 82 83 49 50 51 53 35 36 39 40 19 20 22 23

PP3V3_S0

6 7 12 16 17 18 25 26 28 32 41 45 47 48 56 60 61 71 84 87 88 89

1

R7952

7.15K

1/16W MF-LF 402

2

10 12 13 14 16 17 20 22 23 35

101

Thresholds: VDD: 2.734V-3.010V V2MON: 2.815V-3.099V V3MON: 0.572V-0.630V V4MON: 0.572V-0.630V

101 86 88 67 68 46 51

PP5V_S0

6 7 8 22 41 53 64 69 71

S0PGOOD_ISL

R7960

S0PGOOD_ISL

R7961

6.04K

1/16W MF-LF

15.0K

1/16W

MF-LF

7

10 13 15 29 71 72

1

S0PGOOD_ISL

1%

402

2

1

S0PGOOD_ISL

1%

402

2

PP1V5_S3RS0_CPUDDR

PP5V_DIV_VMON

345678

3.3V,5V S3 ENABLE

PLACE_NEAR=U7300.16:6mm

2

1

70 72

R7922

100K

21

5% 1/16W MF-LF

402

5

G

SMC_PM_G2_EN

MAKE_BASE=TRUE

PP3V42_G3H

6 7 62 63 72

PLACE_NEAR=U7201.20:7mm

S5_PWRGD

44 65 72

R7974

PLACE_NEAR=U7400.7:5mm

R7976

NO STUFF

0

21

5% 1/16W MF-LF

402

82 85 89 98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72

1

R7951

15.0K

1% 1/16W MF-LF 402

2

VMON_3V3_DIV

1%

PP1V5_S3RS0_CPUDDR

7

10 13 15 29 71 72

PP1V5_S3RS0

PP1V05_S0

6 7 9 39 44 67 69 72

S0 Rail PGOOD Circuitry

(ISL Version in development)

PP1V05_S0

1

R7970

S0PGOOD_ISL

10K

R7972

1%

402

2

1

S0PGOOD_ISL

10K

1%

402

2

6.04K

1/16W MF-LF

PP1V5_DIV_VMON

R7973

15.0K

1/16W

1/16W MF-LF

R7971

1/16W

MF-LF

S5 Rail Enables & PGOOD

R7940

100

2

R7941

100K

1/16W MF-LF

0

5% 1/16W MF-LF

402

12 16 17 18 19 20 22 23

1

1%

402

2

1

1%

MF-LF

402

2

5%

402

21

47 48 49 50 51 53 56 60 61 71 6 7 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

S0PGOOD_ISL

PP1V05_VID_VMON

1

5% 1/16W MF-LF

PLACE_NEAR=U7201.21:7mm

1

2

402

S5_PWRGD

MAKE_BASE=TRUE

CPUVCORE ENABLE

PLACE_NEAR=U7400.7:5mm

CPUVCCIOS0_PGOOD

69 72

R7956

150K

1/16W MF-LF

R7953

1K

21

VMON_Q2_BASE

5% 1/16W MF-LF

402

R7954

1K

21

5% 1/16W MF-LF

402

R7955

1K

5%

1/16W MF-LF

402

PP3V3_S0

C7960

0.1uF

VMON_Q3_BASE

21

VMON_Q4_BASE

Worst-Case Thresholds:

Q2: 0.XXXV Q3: 0.640V

3.3V w/Divider: 2.345V Q4: 0.660V

S0PGOOD_ISL

1

20% 10V

2

CERM

402

3

V2MON

5

V3MON

6

402

P1V5S0_PGOOD from U7710

U7960

ISL88042IRTEZ

GND

P3V3S5_EN P3V3S5_EN

65 72

MAKE_BASE=TRUE

1

C7942

0.0033UF

10% 50V

2

CERM 402

NO STUFF

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

SMC-->PM_DSW_PWRGD

44 65

OUT

72

CPUIMVP_VR_ON

PLACE_NEAR=U7400.7:5mm

R7975

0

21

5% 1/16W MF-LF

402

S0 Rail PGOOD (BJT Version)

1

1%

2

S0PGD_C

6

5

Q2

8

NC

7

Q3

CRITICAL

2

NC

1

Q4

3

70

IN

70

IN

65

IN

69 72

7

2

VDD

TDFN

CRITICAL

THRM_PAD

4

9

(IPU)

MR*

RST*V4MON

353S2310

IN

64

IN

1

NC

8

ALL_SYS_PWRGD_R

PM_PECI_PWRGD

ALL_SYS_PWRGD

4

Q7950

Q1

ASMCC0179

DFN2015H4-8

353S2809

S0PGD_BJT_GND_R

12 16 17 18 19 20 22 23

P1V5S0_PGOOD

P1V8S0_PGOOD

P5VS3_PGOOD

CPUVCCIOS0_PGOOD

PVCCSA_PGOOD

S0PGOOD_ISL

R7962

67

OUT

R7957

100

1/16W MF-LF

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7 25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

R7965

R7963

330

5% 1/16W MF-LF

402

65 72

OUT

98

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

PLACE_NEAR=U7940.1:2.3mm

SMC_BATLOW_L:100K pull up on SMC page

PM_SLP_SUS_L:100K pull down on PCH page

44

No stuff C7931, 12ms Min delay time

U7930 Sense input threhold is 3.07V

44 45

17

23 44 72 87 89

98 6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 89

IN

PP3V3_S5

CRITICAL

5 1

SENSE

TPS3808G33DBVRG4

4

CT

1

C7931

0.001UF

20% 50V

2

CERM 402

NO STUFF

1

5%

2

21

23 44 72 87 89

OUT

5%

402

100

1/16W MF-LF

402

100

1/16W MF-LF

402

21

1

2

R7968

5%

PP3V3_SUS

7

16 17 18 19 20 22 45 70

71 72

R7967

100

21

5%

1/16W

R7966

MF-LF

402

100

1/16W MF-LF

21

R7964

100

5% 1/16W MF-LF

402

21

ALL_SYS_PWRGD

Sus_PGOOD_CT

10K

1/16W MF-LF

402

5%

402

21

State

Run (S0)

Sleep (S3)

Deep Sleep (S4)

Deep Sleep (S5)

Battery Off (G3Hot)

PM_SLP_S5_L

17 44

IN

PM_SLP_S5_L:100K pull down on PCH page

3.3V/5.0V Sus ENABLE

1

C7940

0.1uF

20% 10V

2

CERM

402

SMC_BATLOW_L

PM_SLP_SUS_L

1

3

6

NO STUFF

R7917

0

5% 1/16W MF-LF

402

3.3V SUS Detect

PLACE_NEAR=U7930.6:2.3mm

6

VDD

RESET*

U7930

SOT23-6

GND

2

SMC_S4_WAKESRC_EN

44 45 72 85

MAKE_BASE=TRUE

C7930

0.1uF

CERM

MR*

1

20% 10V

2

402

3

SMC_PM_G2_ENABLE

1

1 0

0

3.3V/5.0V S4 ENABLE

NOSTUFF

R7916

0

72

1 2

PLACE_NEAR=U1800.G18:5mm

5

VCC

U7940

74AUP1G3208

SOT891

A

B

Y

C

GND

2

21

R7933

100K

5% 1/16W MF-LF

402

PM_RSMRST_L

PM_RSMRST_L goes to U1800.C21

SMC_S4_WAKESRC_EN

5% 1/16W MF-LF

402

4

PP3V3_SUS

1

2

71

PM_SUS_EN

71 72

MAKE_BASE=TRUE

OUT

P3V3_S4_EN

MAKE_BASE=TRUE

6

17

OUT

PM_SLP_S5_L

7

16 17 18 19 20 22 45 70 71 72

44 45 72 85

PM_SLP_S4_L

1

0

P3V3_S4_EN

PM_SLP_S3_L:100K pull down in PCH page

PM_SUS_EN

OUT

17 29 44 72

OUT

18 19 24 25 29 30 31 32

6

17 29 44 72

IN

19

IN

17 44 45

IN

8 7 5 4 2 1

PM_SLP_S3_L

1

01

0

71 72

PM_SLP_S3_L

6

IN

72 47

46

71 72

63

71 72

SSM3K15FV

PP3V3_S3

6 7 8 47 48 49 53 54 71 87

PM_SLP_S3_L

2N7002DW-X-G

WOL_EN

SMC_ADAPTER_EN

1

0

S0 ENABLE

R7978

100

21

5% 1/16W MF-LF

402

CHGR VFRQ Generation

62 45 42

PP3V42_G3H

6 7 25 44 52

Q7931

SOD-VESM-HF

Q7925

2

1

3

D

1

G S

2

R7921

10K

1/16W MF-LF

402

SOT-363

5

G

Q7920

2N7002DW-X-G

SOT-363

2

G

R7931

100K

5% 1/16W MF-LF

402

CHGR_VFRQ

1

5%

2

D

S

D

S

PM_SLP_S4_L

17 29 42 44 65 72

IN

MAKE_BASE=TRUE

PM_SLP_S4_L:100K pull down in PCH page

(PM_SLP_S3_R_L)

R7987

2

33K

5%

1/16W

1

MF-LF

402

PLACE_NEAR=U7100.15:6mm

PVCCSA_EN

64 72

MAKE_BASE=TRUE

PLACE_NEAR=U7100.15:6mm

63

OUT

1

C7987

0.47UF

10%

6.3V

2

CERM-X5R 402

VFRQ Low: Fix Frequency VFRQ High: Variable Frequency

R7981

2

20K

5%

1/16W

1

MF-LF 402

PLACE_NEAR=U7600.3:6mm

CPUVCCIOS0_EN

69 72

MAKE_BASE=TRUE

PLACE_NEAR=U7600.3:6mm

1

C7981

0.47UF

10%

6.3V

2

CERM-X5R 402

ENET Enable Generation

PM_SLP_S3_ENET

Q7921

3

4

AC_EN_L

6

1

NO STUFF

R7929

1/16W MF-LF

402

SSM3K15FV

SOD-VESM-HF

1

0

5%

2

3

D

1

G S

2

(AC_EN_L)

Q7920

2N7002DW-X-G

(PM_SLP_S3_L)

SOT-363

36

2 1

(PM_SLP_S4_L)

2

R7911

5.1K

5% 1/16W MF-LF

1

402

1

C7910

0.47UF

10%

6.3V

2

CERM-X5R 402

R7985

20K

5% 1/16W MF-LF 402

PLACE_NEAR=U7760.4:6mm

P1V2S0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7760.4:6mm

1

C7985

1UF

10%

6.3V

2

CERM-X5R 402

1

C7921

0.033UF

10% 16V

2

X5R 402

2

R7912

0

5% 1/16W

MF-LF

1

402

PLACE_NEAR=Q7812.2:6mm

NO STUFF

1

C7912

0.47UF

10%

6.3V

2

CERM-X5R 402

PM_SLP_S3_R_L

48 71 72

MAKE_BASE=TRUE

21

R7988

P1V5S0_EN P1V5S0_EN

70 72

MAKE_BASE=TRUE

PLACE_NEAR=U7710.2:6mm

1

2

R7986

1

PLACE_NEAR=U7720.5:6mm

MAKE_BASE=TRUE

CRITICAL

Q7922

NTR4101P

SOT-23-HF

2

5.1K

5% 1/16W MF-LF 402

72 70

10K

5% 1/16W MF-LF 402

C7988

0.47UF

10%

6.3V CERM-X5R 402

3.3V ENET FET

G

1

P3V3ENET_SS

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up

on open-drain AP_PWR_EN signal.

PM_WLAN_EN_L

6

Q7925

D

2N7002DW-X-G

SOT-363

2

G

S

1

PAGE TITLE

3

D

S

4

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

AP_PWR_EN

Power Control 1/ENABLE

Apple Inc.

R

21

P3V3S3_EN

71 72

MAKE_BASE=TRUE

DDRREG_EN

66 72

MAKE_BASE=TRUE

P1V8S0_EN

PLACE_NEAR=U7720.5:6mm

1

C7986

0.47UF

10%

6.3V

2

CERM-X5R 402

DS

3

C7922

0.01UF

2 1

10% 16V

CERM

402

PLACE_NEAR=U5701.4:6mm

R7913

3.3K

5% 1/16W MF-LF 402

PM_SLP_S3_R_L

P1V8S0_EN

P1V2S0_EN

CPUVCCIOS0_EN

PVCCSA_EN

PP3V3_ENET

PM_SLP_S4_L

TPAD_VBUS_EN

P3V3S3_EN

DDRREG_EN

31

OUT

18 31

IN

SYNC_DATE=07/22/2010SYNC_MASTER=K91_MARY

DRAWING NUMBER

REVISION

BRANCH

PAGE

79 OF 132

SHEET

72 OF 101

6 7

OUT

25 36 70

OUT

48 71 72

70 72

69 72

64 72

65 72 17 29 42 44

52

71

OUT

72

66

OUT

72

D

C

B

A

SIZE

D

Power aliases required by this page:

- =PP1V2_GPU_PEX_PLLXVDD

- =PP1V2_GPU_PEX_IOVDDQ

- =PP1V2_GPU_PEX_IOVDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

D

90

C

90

B

PEG_R2D_C_P<0>

8

IN

PEG_R2D_C_N<0>

8

IN

PEG_R2D_C_P<1>

8

IN

PEG_R2D_C_N<1>

8

IN

PEG_R2D_C_P<2>

8

IN

PEG_R2D_C_N<2>

8

IN

PEG_R2D_C_P<3>

8

IN

PEG_R2D_C_N<3>

8

IN

PEG_R2D_C_P<4>

8

IN

PEG_R2D_C_N<4>

8

IN

PEG_R2D_C_P<5>

8

IN

PEG_R2D_C_N<5>

8

IN

PEG_R2D_C_P<6>

8

IN

PEG_R2D_C_N<6>

8

IN

PEG_R2D_C_P<7>

8

IN

PEG_R2D_C_N<7>

8

IN

Page Notes

C8020

C8021

C8022

C8023

C8024

C8025

C8026

C8027

C8028

C8029

C8030

C8031

C8032

C8033

C8034

C8035

0.1UF

21 10% 21 10%

6.3V

201

X5R

X5R 201

PEG_R2D_P<0>

PEG_R2D_N<0>

PEG_R2D_P<1>

PEG_R2D_N<1>

PEG_R2D_P<2>

PEG_R2D_N<2>

PEG_R2D_P<3>

PEG_R2D_N<3>

PEG_R2D_P<4>

PEG_R2D_N<4>

PEG_R2D_P<5>

PEG_R2D_N<5>

PEG_R2D_P<6>

PEG_R2D_N<6>

PEG_R2D_P<7>

PEG_R2D_N<7>

73 90

PEG_D2R_C_P<0>

73 90

PEG_D2R_C_N<0>

73 90 73 90

PEG_D2R_C_P<1>

73 90

PEG_D2R_C_N<1>

73 90

PEG_D2R_C_P<2>

73 90

PEG_D2R_C_N<2>

73 90

PEG_D2R_C_P<3>

73 90

PEG_D2R_C_N<3>

73 90

PEG_D2R_C_P<4>

73 90

PEG_D2R_C_N<4>

73 90

PEG_D2R_C_P<5>

73 90

PEG_D2R_C_N<5>

73 90

PEG_D2R_C_P<6>

73 90

PEG_D2R_C_N<6>

73 90

PEG_D2R_C_P<7>

73 90

PEG_D2R_C_N<7>

73 90

C8055

C8056

C8057

C8058

C8059

C8060

C8061

C8062

C8063

C8064

C8065

C8066

C8067

C8068

C8069

C8070

8

81 86 87 89

0.1UF

PM_ALL_GPU_PGOOD

IN

21 10% 21 10%

6.3V

X5R 201

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<6>

PEG_D2R_N<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

R8003

NOSTUFF

1

5% 1/16W MF-LF

402

345678

2 1

D

PEG_R2D_P<0>

16 93

0

1 2

5% 1/16W MF-LF

402

73 90

PEG_R2D_N<0>

73 90

PEG_R2D_P<1>

73 90

PEG_R2D_N<1>

73 90

PEG_R2D_P<2>

73 90

PEG_R2D_N<2>

73 90

PEG_R2D_P<3>

73 90

PEG_R2D_N<3>

73 90

PEG_R2D_P<4>

73 90

PEG_R2D_N<4>

73 90

PEG_R2D_P<5>

73 90

PEG_R2D_N<5>

73 90

PEG_R2D_P<6>

73 90

PEG_R2D_N<6>

73 90

PEG_R2D_P<7>

73 90

PEG_R2D_N<7>

73 90

PEG_CLK100M_P

IN

PEG_CLK100M_N

IN

GPU_PWRGOOD

GPU_RESET_R_L

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

8

90

OUT

0

2

1

R8004

10K

5% 1/16W MF-LF 402

2

87

8

IN

EG_RESET_L

R8000

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38 M37

M35 L36

L38 K37

K35 J36

J38 H37

H35 G36

G38 F37

F35 E37

AB35 AA36

AH16

AA30

PCIE_RX8P PCIE_RX8N

PCIE_RX9P PCIE_RX9N

PCIE_RX10P PCIE_RX10N

PCIE_RX11P PCIE_RX11N

PCIE_RX12P PCIE_RX12N

PCIE_RX13P PCIE_RX13N

PCIE_RX14P PCIE_RX14N

PCIE_RX15P PCIE_RX15N

PCIE_REFCLKP PCIE_REFCLKN

PWRGOOD

PERST*

NC NC

U8000

FCBGA

(1 OF 9)

PCIE

40NM-ES

WHISTLER

OMIT

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

PCIE_CALRP PCIE_CALRN

Y33 Y32

W33 W32

U33 U32

U30 U29

T33 T32

T30 T29

P33 P32

P30 P29

N33 N32

N30 N29

L33 L32

L30 L29

K33 K32

J33 J32

K30 K29

H33 H32

Y30 Y29

7

74 78 80

100

PEG_D2R_C_P<0> PEG_D2R_C_N<0>

PEG_D2R_C_P<1> PEG_D2R_C_N<1>

PEG_D2R_C_P<2> PEG_D2R_C_N<2>

PEG_D2R_C_P<3> PEG_D2R_C_N<3>

PEG_D2R_C_P<4> PEG_D2R_C_N<4>

PEG_D2R_C_P<5> PEG_D2R_C_N<5>

PEG_D2R_C_P<6> PEG_D2R_C_N<6>

PEG_D2R_C_P<7> PEG_D2R_C_N<7>

NC NC

PEG_CALRP PEG_CALRN

R8001

PP1V0_S0GPU_ISNS

2.0K

1/16W MF-LF

73 90

C

1221

R8002

1.27K

1%

1/16W MF-LF 402

402

B

A

PAGE TITLE

Whistler PCI-E

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=06/15/2010SYNC_MASTER=K92_SUMA

DRAWING NUMBER

REVISION

BRANCH

PAGE

80 OF 132

SHEET

73 OF 101

SIZE

A

D

345678

CRITICAL

L8150

1

C8161

1UF

10% 25V

2

X5R 402

1

C8171

1UF

10% 25V

2

X5R 402

1

C8181

1UF

10% 25V

2

X5R 402

1

C8191

10UF

20% 10V

2

X5R 603

1

C81A1

1UF

10% 25V

2

X5R 402

1

C81B1

10UF

20% 10V

2

X5R 603

120OHM-0.3A

1 2

PPVCORE_GPU

6 7

48 81

1

2

1

2

1

2

1

2

1

2

1

2

0402

C8162

1UF

10% 25V X5R 402

C8172

1UF

10% 25V X5R 402

C8182

1UF

10% 25V X5R 402

C8192

10UF

20% 10V X5R 603

C81A2

1UF

10% 25V X5R 402

C81B2

10UF

20% 10V X5R 603

36

1

C8163

1UF

10% 25V

2

X5R 402

1

C8173

1UF

10% 25V

2

X5R 402

1

C8183

1UF

10% 25V

2

X5R 402

1

C8193

10UF

20% 10V

2

X5R 603

1

C81A3

1UF

10% 25V

2

X5R 402

PP1V8_GPU_VDDR4

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8164

1UF

10% 25V

2

X5R 402

1

C8174

1UF

10% 25V

2

X5R 402

1

C8184

1UF

10% 25V

2

X5R 402

1

C8194

10UF

20% 10V

2

X5R 603

1

C81A4

1UF

10% 25V

2

X5R 402

1

2

1

C81C0

1UF

10% 25V

2

X5R 402

C81C1

0.1UF

10%

6.3V X5R 201

1

C8165

2

1

C8175

2

1

C8185

2

1

C8195

2

1

C81A5

2

1UF

10% 25V X5R 402

1UF

10% 25V X5R 402

1UF

10% 25V X5R 402

10UF

20% 10V X5R 603

1UF

10% 25V X5R 402

PP1V5_S0GPU_ISNS PP1V8_S0GPU_ISNS

7

75 76 77

100

1

C8100

10UF

20% 10V

2

X5R 603

1

C8101

10UF

20% 10V

2

X5R 603

1

C8102

10UF

20% 10V

2

X5R 603

D

1

C8105

1UF

10% 25V

2

X5R 402

1

C8115

0.1UF

10%

6.3V

2

X5R 201

PP1V8_S0GPU_ISNS

7

74 78 80

100

1

C8106

1UF

10% 25V

2

X5R 402

1

C8116

0.1UF

10%

6.3V

2

X5R 201

C

PP1V0_S0GPU_ISNS

7

73 74 78 80

100

74

1

C8107

1UF

10% 25V

2

X5R 402

1

C8117

0.1UF

10%

6.3V

2

X5R 201

CRITICAL

L8130

470OHM-1A-150MOHM

1 2

0603

GND_GPU_PLL

1

C8108

1UF

10% 25V

2

X5R 402

1

C8118

0.1UF

10%

6.3V

2

X5R 201

L8120

120OHM-0.3A

1 2

0402

CRITICAL

1

C8130

10UF

20% 10V

2

X5R 603

1

C8109

1UF

10% 25V

2

X5R 402

1

C8119

0.1UF

10%

6.3V

2

X5R 201

1

C8125

10UF

20% 10V

2

X5R 603

1

C8131

1UF

10% 25V

2

X5R 402

1

C8110

1UF

10% 25V

2

X5R 402

1

C8120

0.1UF

10%

6.3V

2

X5R 201

PP1V8_GPU_VDD_CT

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8126

1UF

10% 25V

2

X5R 402

PP1V0_GPU_PLL

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V

1

C8132

0.1UF

10%

6.3V

2

X5R 201

CRITICAL

L8131

PP1V8_S0GPU_ISNS

7

74 78 80

100

B

PP1V8_S0GPU_ISNS

7

74 78 80

100

PP1V8_S0GPU_ISNS

7

74 78 80

100

PP1V0_S0GPU_ISNS

L8155

FERR-120-OHM-3A

1 2

0603

CRITICAL

A

470OHM-1A-150MOHM

1 2

0603

CRITICAL

L8132

120OHM-0.3A

1 2

0402

XW8100

SM

1 2

FERR-220-OHM-2A

1 2

CRITICAL

7

73 74 78 80

100

1

C8151

10UF

20% 10V

2

X5R 603

1

C8137

10UF

20% 10V

2

X5R 603

1

C8142

10UF

20% 10V

2

X5R 603

L8140

0603

1

C8152

1UF

10% 25V

2

X5R 402

PP1V8_GPU_MEM_PLL

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8138

1UF

10% 25V

2

X5R 402

1

C8143

1UF

10% 25V

2

X5R 402

1

C8145

10UF

20% 10V

2

X5R 603

1

C8153

1UF

10% 25V

2

X5R 402

1

C8139

1UF

10% 25V

2

X5R 402

PP1V8_GPU_PLL

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8144

0.1UF

10%

6.3V

2

X5R 201

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

PP1V8_GPU_PCIE_VDDR

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8146

1UF

10% 25V

2

X5R 402

PP1V0_GPU_PCIE_VDDC

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V

1

C8154

1UF

10% 25V

2

X5R 402

1

C8111

1UF

10% 25V

2

X5R 402

1

C8121

0.1UF

10%

6.3V

2

X5R 201

1

C8127

1UF

10% 25V

2

X5R 402

1

C8133

10UF

20% 10V

2

X5R 603

1

C8140

0.1UF

10%

6.3V

2

X5R 201

PP1V0_GPU_PLL

74

GND_GPU_PLL

74

1

C8147

1UF

10% 25V

2

X5R 402

1

C8155

1UF

10% 25V

2

X5R 402

1

C8112

1UF

10% 25V

2

X5R 402

1

C8122

0.1UF

10%

6.3V

2

X5R 201

1

C8128

1UF

10% 25V

2

X5R 402

1

C8134

1UF

10% 25V

2

X5R 402

1

C8141

0.1UF

10%

6.3V

2

X5R 201

1

C8148

1UF

10% 25V

2

X5R 402

1

C8156

1UF

10% 25V

2

X5R 402

71 78 79 81 83

81

TBD mA

1

C8103

10UF

20% 10V

2

X5R 603

1

C8113

1UF

10% 25V

2

X5R 402

1

C8123

0.1UF

10%

6.3V

2

X5R 201

219mA

1

C8129

0.1UF

10%

6.3V

2

X5R 201

PP3V3_S0GPU

6 7

60 mA

1

C8135

1UF

10% 25V

2

X5R 402

PP1V8_GPU_VDDR4

74

TBD mA

150mA

75mA

120mA

GPU_VDD_SENSE

OUT

GPU_GND_SENSE

OUT

504mA

1

C8149

0.1UF

10%

6.3V

2

X5R 201

1920mA

1

C8157

1UF

10% 25V

2

X5R 402

1

C8104

10UF

20% 10V

2

X5R 603

1

C8114

1UF

10% 25V

2

X5R 402

1

C8124

0.1UF

10%

6.3V

2

X5R 201

1

C8136

1UF

10% 25V

2

X5R 402

1

C8150

0.1UF

10%

6.3V

2

X5R 201

1

C8158

1UF

10% 25V

2

X5R 402

7

74 78 80

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

100

1

C8160

1UF

10% 25V

2

X5R 402

1

C8170

1UF

10% 25V

2

X5R 402

1

C8180

1UF

10% 25V

2

X5R 402

1

C8190

10UF

20% 10V

2

X5R 603

1

C81A0

1UF

10% 25V

2

X5R 402

1

C81B0

10UF

20% 10V

2

X5R 603

AC7

VDDR1_AC7

AD11

VDDR1_AD11

AF7

VDDR1_AF7

AG10

VDDR1_AG10

AJ7

VDDR1_AJ7

AK8

VDDR1_AK8

AL9

VDDR1_AL9

G11

VDDR1_G11

G14

VDDR1_G14

G17

VDDR1_G17

G20

VDDR1_G20

G23

VDDR1_G23

G26

VDDR1_G26

G29

VDDR1_G29

H10

VDDR1_H10

J7

VDDR1_J7

J9

VDDR1_J9

K8

VDDR1_K8

K11

VDDR1_K11

K13

VDDR1_K13

L7

VDDR1_L7

L12

VDDR1_L12

L16

VDDR1_L16

L21

VDDR1_L21

L23

VDDR1_L23

L26

VDDR1_L26

M11

VDDR1_M11

N11

VDDR1_N11

P7

VDDR1_P7

R11

VDDR1_R11

U7

VDDR1_U7

U11

VDDR1_U11

Y7

VDDR1_Y7

Y11

VDDR1_Y11

AF26

VDD_CT_AF26

AF27

VDD_CT_AF27

AG26

VDD_CT_AG26

AG27

VDD_CT_AG27

AF23

VDDR3_AF23

AF24

VDDR3_AF24

AG23

VDDR3_AG23

AG24

VDDR3_AG24

AF13

VDDR4_AF13

AF15

VDDR4_AF15

AG13

VDDR4_AG13

AG15

VDDR4_AG15

AD12

VDDR4_AD12

AF11

VDDR4_AF11

AF12

VDDR4_AF12

AG11

VDDR4_AG11

M20 M21

U12 V12

AM10

AN9

AN10

AF28

AG28

AH29

AA31 AA32 AA33 AA34 AB37

V28 W29 W30 Y31

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

H7 H8

NC/VDDRHA NC/VSSRHA

NC/VSSRHB NC/VDDRHB

MPV18_H7 MPV18_H8

SPV18

SPV10

SPVSS

FB_VDDC

FB_VDDCI

FB_GND

PCIE_VDDR_AA31 PCIE_VDDR_AA32 PCIE_VDDR_AA33 PCIE_VDDR_AA34 PCIE_VDDR_AB37 PCIE_VDDR_V28 PCIE_VDDR_W29 PCIE_VDDR_W30 PCIE_VDDR_Y31

PCIE_VDDC_G30 PCIE_VDDC_G31 PCIE_VDDC_H29 PCIE_VDDC_H30 PCIE_VDDC_J29 PCIE_VDDC_J30 PCIE_VDDC_L28 PCIE_VDDC_M28 PCIE_VDDC_N28 PCIE_VDDC_R28 PCIE_VDDC_T28 PCIE_VDDC_U28

NC NC

NC

OMIT

U8000

WHISTLER

40NM-ES

FCBGA

(7 OF 9)

MEM I/O

CORE

TRNSL

LEVEL

PLL I/O

VOLT

SENSE

PCIE

ISOLATED CORE I/O

VDDC_AA15 VDDC_AA17 VDDC_AA20 VDDC_AA22 VDDC_AA24 VDDC_AA27 VDDC_AB16 VDDC_AB18 VDDC_AB21 VDDC_AB23 VDDC_AB26 VDDC_AB28 VDDC_AC17 VDDC_AC20 VDDC_AC22 VDDC_AC24 VDDC_AC27 VDDC_AD18 VDDC_AD21 VDDC_AD23 VDDC_AD26 VDDC_AF17 VDDC_AF20 VDDC_AF22 VDDC_AG16 VDDC_AG18 VDDC_AG21 VDDC_AH22 VDDC_AH27 VDDC_AH28

VDDC_M26 VDDC_N24

BIF_VDDC_N27

VDDC_R18 VDDC_R21 VDDC_R23 VDDC_R26 VDDC_T17 VDDC_T20 VDDC_T22 VDDC_T24

BIF_VDDC_T27

VDDC_U16 VDDC_U18 VDDC_U21 VDDC_U23 VDDC_U26 VDDC_V17 VDDC_V20 VDDC_V22 VDDC_V24 VDDC_V27 VDDC_Y16 VDDC_Y18 VDDC_Y21 VDDC_Y23 VDDC_Y26 VDDC_Y28

VDDCI_AA13 VDDCI_AB13 VDDCI_AC12 VDDCI_AC15 VDDCI_AD13 VDDCI_AD16

VDDCI_M15 VDDCI_M16 VDDCI_M18 VDDCI_M23 VDDCI_N13 VDDCI_N15 VDDCI_N17 VDDCI_N20 VDDCI_N22 VDDCI_R12 VDDCI_R13 VDDCI_R16 VDDCI_T12 VDDCI_T15 VDDCI_V15 VDDCI_Y13

8 7 5 4 2 1

2 1

Page Notes

Power aliases required by this page:

- =PPVCORE_GPU

- =PP1V5R1V35_GPU_FB_VDDR1

- =PP1V8_GPU_VDD_CT

- =PP1V0_GPU_PLL

- =PP3V3_GPU_VDDR3

- =PP3V3_GPU_VDDR4

- =PP1V8_GPU_MEM_PLL

- =PP1V8_GPU_PLL

- =PP1V8_GPU_PCIE_VDDR

- =PP1V8_GPU_PCIE_VDDC

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

1

C8166

1UF

10% 25V

2

X5R 402

1

C8176

1UF

10% 25V

2

X5R 402

1

C8186

1UF

10% 25V

2

X5R 402

1

C8196

10UF

20% 10V

2

X5R 603

1

C81A6

1UF

10% 25V

2

X5R 402

SYNC_MASTER=K92_SUMA SYNC_DATE=06/15/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

1

C8167

1UF

10% 25V

2

X5R 402

1

C8177

1UF

10% 25V

2

X5R 402

1

C8187

1UF

10% 25V

2

X5R 402

1

C8197

10UF

20% 10V

2

X5R 603

1

C81A7

1UF

10% 25V

2

X5R 402

Whistler CORE/FB POWER

R

1

C8168

1UF

10% 25V

2

X5R 402

1

C8178

1UF

10% 25V

2

X5R 402

1

C8188

1UF

10% 25V

2

X5R 402

1

C8198

10UF

20% 10V

2

X5R 603

1

C81A8

1UF

10% 25V

2

X5R 402

Apple Inc.

1

C8169

1UF

10% 25V

2

X5R 402

1

C8179

1UF

10% 25V

2

X5R 402

1

C8189

1UF

10% 25V

2

X5R 402

1

C8199

10UF

20% 10V

2

X5R 603

1

C81A9

1UF

10% 25V

2

X5R 402

DRAWING NUMBER

REVISION

BRANCH

PAGE

81 OF 132

SHEET

74 OF 101

SIZE

D

C

B

A

D

C

B

PP1V5_S0GPU_ISNS

GPU:WHISTLER

R8210

4021%1/16W MF-LF

R8211

402

R8212

402

R8213

402

R8214

402

R8215

402

PP1V5_S0GPU_ISNS

7

74 75 76

77

100

A

PLACE_NEAR=U8000.L18:2.54MM

345678

C37

DQA0_0/DQA_0

C35

DQA0_1/DQA_1

A35

DQA0_2/DQA_2

E34

DQA0_3/DQA_3

G32

DQA0_4/DQA_4

D33

DQA0_5/DQA_5

F32

DQA0_6/DQA_6

E32

DQA0_7/DQA_7

D31

DQA0_8/DQA_8

F30

DQA0_9/DQA_9

C30

DQA0_10/DQA_10

A30

DQA0_11/DQA_11

F28

DQA0_12/DQA_12

C28

DQA0_13/DQA_13

A28

DQA0_14/DQA_14

E28

DQA0_15/DQA_15

D27

DQA0_16/DQA_16

F26

DQA0_17/DQA_17

C26

DQA0_18/DQA_18

A26

DQA0_19/DQA_19

F24

DQA0_20/DQA_20

C24

DQA0_21/DQA_21

A24

DQA0_22/DQA_22

E24

DQA0_23/DQA_23

C22

DQA0_24/DQA_24

A22

DQA0_25/DQA_25

F22

DQA0_26/DQA_26

D21

DQA0_27/DQA_27

A20

DQA0_28/DQA_28

F20

DQA0_29/DQA_29

D19

DQA0_30/DQA_30

E18

DQA0_31/DQA_31

C18

DQA1_0/DQA_32

A18

DQA1_1/DQA_33

F18

DQA1_2/DQA_34

D17

DQA1_3/DQA_35

A16

DQA1_4/DQA_36

F16

DQA1_5/DQA_37

D15

DQA1_6/DQA_38

E14

DQA1_7/DQA_39

F14

DQA1_8/DQA_40

D13

DQA1_9/DQA_41

F12

DQA1_10/DQA_42

A12

DQA1_11/DQA_43

D11

DQA1_12/DQA_44

F10

DQA1_13/DQA_45

A10

DQA1_14/DQA_46

C10

DQA1_15/DQA_47

G13

DQA1_16/DQA_48

H13

DQA1_17/DQA_49

J13

DQA1_18/DQA_50

H11

DQA1_19/DQA_51

G10

DQA1_20/DQA_52

G8

DQA1_21/DQA_53

K9

DQA1_22/DQA_54

K10

DQA1_23/DQA_55

G9

DQA1_24/DQA_56

A8

DQA1_25/DQA_57

C8

DQA1_26/DQA_58

E8

DQA1_27/DQA_59

A6

DQA1_28/DQA_60

C6

DQA1_29/DQA_61

E6

DQA1_30/DQA_62

A5

DQA1_31/DQA_63

L18

MVREFDA

L20

MVREFSA

L27

MEM_CALRN0

N12

MEM_CALRN1

AG12

MEM_CALRN2

M27

MEM_CALRP0

M12

MEM_CALRP1

AH12

MEM_CALRP2

PP1V5_S0GPU_ISNS

7

74 75 76 77

GPU:WHISTLER

PLACE_NEAR=U8000.L20:2.54MM

75

C8200

0.1UF

10% 16V X5R 402-1

GPU:WHISTLER

U8000

WHISTLER

40NM-ES

FCBGA

(4 OF 9)

MEM INTERFACE A

OMIT

EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3

EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7

DDBIA0_0/QSA_0B/WDQSA_0 DDBIA0_1/QSA_1B/WDQSA_1 DDBIA0_2/QSA_2B/WDQSA_2 DDBIA0_3/QSA_3B/WDQSA_3

DDBIA1_0/QSA_4B/WDQSA_4 DDBIA1_1/QSA_5B/WDQSA_5 DDBIA1_2/QSA_6B/WDQSA_6 DDBIA1_3/QSA_7B/WDQSA_7

100

1

R8202

40.2

1% 1/16W MF-LF 402

2

FB_A_VREFS

1

R8203

100

1% 1/16W MF-LF 402

2

MAA0_0/MMA_0 MAA0_1/MMA_1 MAA0_2/MMA_2 MAA0_3/MMA_3 MAA0_4/MMA_4 MAA0_5/MMA_5 MAA0_6/MMA_6 MAA0_7/MMA_7

MAA1_0/MMA_8

MAA1_1/MMA_9 MAA1_2/MMA_10 MAA1_3/MMA_11 MAA1_4/MMA_12

MAA1_5/MMA_13_BA2 MAA1_6/MMA_14_BA0

MAA1_7/MMA_A15_BA1

WCKA0_0/DQMA_0

WCKA0_0*/DQMA_1

WCKA0_1/DQMA_2

WCKA0_1*/DQMA_3

WCKA1_0/DQMA_4

WCKA1_0*/DQMA_5

WCKA1_1/DQMA_6

WCKA1_1*/DQMA_7

ADBIA0/ODTA0

ADBIA1/ODTA1

PP1V5_S0GPU_ISNS

7

74 75 76 77

PLACE_NEAR=U8000.Y12:2.54MM

75

PLACE_NEAR=U8000.L20:2.54MM

1

C8201

0.1UF

10% 16V

2

X5R 402-1

GPU:WHISTLER

243

1 2

243

1 2

MF-LF

1/16W

1%

243

GPU:WHISTLER

1 2

MF-LF

1/16W

1%

243

1 2

MF-LF1/16W

1%

243

1 2

MF-LF1/16W

1%

243

1 2

1/16W

1%

MF-LF

GPU:WHISTLER

FB_A0_DQ<0>

6

76 97

BI

FB_A0_DQ<1>

6

76 97

BI

FB_A0_DQ<2>

6

76 97

BI

FB_A0_DQ<3>

6

76 97

BI

FB_A0_DQ<4>

6

76 97

BI

FB_A0_DQ<5>

6

76 97

BI

FB_A0_DQ<6>

6

76 97

BI

FB_A0_DQ<7>

6

76 97

BI

FB_A0_DQ<8>

6

76 97

BI

FB_A0_DQ<9>

6

76 97

BI

FB_A0_DQ<10>

6

76 97

BI

FB_A0_DQ<11>

6

76 97

BI

FB_A0_DQ<12>

6

76 97

BI

FB_A0_DQ<13>

6

76 97

BI

FB_A0_DQ<14>

6

76 97

BI

FB_A0_DQ<15>

6

76 97

BI

FB_A0_DQ<16>

6

76 97

BI

FB_A0_DQ<17>

6

76 97

BI

FB_A0_DQ<18>

6

76 97

BI

FB_A0_DQ<19>

6

76 97

BI

FB_A0_DQ<20>

6

76 97

BI

FB_A0_DQ<21>

6

76 97

BI

FB_A0_DQ<22>

6

76 97

BI

FB_A0_DQ<23>

6

76 97

BI

FB_A0_DQ<24>

6

76 97

BI

FB_A0_DQ<25>

6

76 97

BI

FB_A0_DQ<26>

6

76 97

BI

FB_A0_DQ<27>

6

76 97

BI

FB_A0_DQ<28>

6

76 97

BI

FB_A0_DQ<29>

6

76 97

BI

FB_A0_DQ<30>

6

76 97

BI

FB_A0_DQ<31>

6

76 97

BI

FB_A1_DQ<0>

6

76 97

BI

FB_A1_DQ<1>

6

76 97

BI

FB_A1_DQ<2>

6

76 97

BI

FB_A1_DQ<3>

6

76 97

BI

FB_A1_DQ<4>

6

76 97

BI

FB_A1_DQ<5>

6

76 97

BI

FB_A1_DQ<6>

6

76 97

BI

FB_A1_DQ<7>

6

76 97

BI

FB_A1_DQ<8>

6

76 97

BI

FB_A1_DQ<9>

6

76 97

BI

FB_A1_DQ<10>

6

76 97

BI

FB_A1_DQ<11>

6

76 97

BI

FB_A1_DQ<12>

6

76 97

BI

FB_A1_DQ<13>

6

76 97

BI

FB_A1_DQ<14>

6

76 97

BI

FB_A1_DQ<15>

6

76 97

BI

FB_A1_DQ<16>

6

76 97

BI

FB_A1_DQ<17>

6

76 97

BI

FB_A1_DQ<18>

6

76 97

BI

FB_A1_DQ<19>

6

76 97

BI

FB_A1_DQ<20>

6

76 97

BI

FB_A1_DQ<21>

6

76 97

BI

FB_A1_DQ<22>

6

76 97

BI

FB_A1_DQ<23>

6

76 97

BI

FB_A1_DQ<24>

6

76 97

BI

FB_A1_DQ<25>

6

76 97

BI

FB_A1_DQ<26>

6

76 97

BI

FB_A1_DQ<27>

6

76 97

BI

FB_A1_DQ<28>

6

76 97

BI

FB_A1_DQ<29>

6

76 97

BI

FB_A1_DQ<30>

6

76 97

BI

FB_A1_DQ<31>

6

76 97

BI

FB_A_VREFD

75

FB_A_VREFS

75

7

74 75 76 77

FB_CALRN0 FB_CALRN1 FB_CALRN2

GPU:WHISTLER

FB_CALRP0 FB_CALRP1 FB_CALRP2

GPU:WHISTLER

1

R8200

40.2

1% 1/16W MF-LF 402

2

FB_A_VREFD

1

R8201

100

1% 1/16W MF-LF 402

2

100

PLACE_NEAR=U8000.L18:2.54MM

1

2

GPU:WHISTLER

8 7 5 4 2 1

CLKA0

CLKA0*

CLKA1

CLKA1*

RASA0* RASA1*

CASA0* CASA1*

CSA0_0* CSA0_1*

CSA1_0* CSA1_1*

CKEA0 CKEA1

WEA0* WEA1*

MAA0_8 MAA1_8

G24 J23 H24 J24 H26 J26 H21 G21

H19 H20 L13 G16 J16 H16 J17 H17

A32 C32

D23 E22

C14 A14

E10 D9

C34 D29 D25 E20

E16 E12 J10 D7

A34 E30 E26 C20

C16 C12 J11 F8

J21 G19

H27 G27

J14

H14

K23 K19

K20 K17

K24 K27

M13 K16

K21 J20

K26 L15

H23 J19

FB_A0_A<0> FB_A0_A<1> FB_A0_A<2> FB_A0_A<3> FB_A0_A<4> FB_A0_A<5> FB_A0_A<6> FB_A0_A<7>

FB_A1_A<0> FB_A1_A<1> FB_A1_A<2> FB_A1_A<3> FB_A1_A<4> FB_A1_A<5> FB_A1_A<6> FB_A1_A<7>

FB_A0_WCLK_P<0> FB_A0_WCLK_N<0>

FB_A0_WCLK_P<1> FB_A0_WCLK_N<1>

FB_A1_WCLK_P<0> FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1> FB_A1_WCLK_N<1>

FB_A0_EDC<0> FB_A0_EDC<1> FB_A0_EDC<2> FB_A0_EDC<3>

FB_A1_EDC<0> FB_A1_EDC<1> FB_A1_EDC<2> FB_A1_EDC<3>

FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<2> FB_A0_DBI_L<3>

FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<2> FB_A1_DBI_L<3>

FB_A0_ABI_L FB_A1_ABI_L

FB_A0_CLK_P FB_A0_CLK_N

FB_A1_CLK_P FB_A1_CLK_N

FB_A0_RAS_L FB_A1_RAS_L

FB_A0_CAS_L FB_A1_CAS_L

FB_A0_CS_L

NC

FB_A1_CS_L

NC

FB_A0_CKE_L FB_A1_CKE_L

FB_A0_WE_L FB_A1_WE_L

FB_A0_A<8> FB_A1_A<8>

1

R8204

40.2

1% 1/16W MF-LF 402

2

FB_B_VREFD

1

R8205

100

1% 1/16W MF-LF 402

2

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

OUT

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

6

76 97

BI

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

76 97

OUT

6

76 97

OUT

6

76 97

OUT

R8250

10K

1/16W MF-LF

PP1V5_S0GPU_ISNS

7

74 75 76 77

100

75

PLACE_NEAR=U8000.Y12:2.54MM

1

C8202

0.1UF

10% 16V

2

X5R 402-1

PLACE_NEAR=U8000.AA12:2.54MM

FB_B0_DQ<0>

6

77 97

BI

FB_B0_DQ<1>

6

77 97

BI

FB_B0_DQ<2>

6

77 97

BI

FB_B0_DQ<3>

6

77 97

BI

FB_B0_DQ<4>

6

77 97

BI

FB_B0_DQ<5>

6

77 97

BI

FB_B0_DQ<6>

6

77 97

BI

FB_B0_DQ<7>

6

77 97

BI

FB_B0_DQ<8>

6

77 97

BI

FB_B0_DQ<9>

6

77 97

BI

FB_B0_DQ<10>

6

77 97

BI

FB_B0_DQ<11>

6

77 97

BI

FB_B0_DQ<12>

6

77 97

BI

FB_B0_DQ<13>

6

77 97

BI

FB_B0_DQ<14>

6

77 97

BI

FB_B0_DQ<15>

6

77 97

BI

FB_B0_DQ<16>

6

77 97

BI

FB_B0_DQ<17>

6

77 97

BI

FB_B0_DQ<18>

6

77 97

BI

FB_B0_DQ<19>

6

77 97

BI

FB_B0_DQ<20>

6

77 97

BI

FB_B0_DQ<21>

6

77 97

BI

FB_B0_DQ<22>

6

77 97

BI

FB_B0_DQ<23>

6

77 97

BI

FB_B0_DQ<24>

6

77 97

BI

FB_B0_DQ<25>

6

77 97

BI

FB_B0_DQ<26>

6

77 97

BI

FB_B0_DQ<27>

6

77 97

BI

FB_B0_DQ<28>

6

77 97

BI

FB_B0_DQ<29>

6

77 97

BI

FB_B0_DQ<30>

6

77 97

BI

FB_B0_DQ<31>

6

77 97

BI

FB_B1_DQ<0>

6

77 97

BI

FB_B1_DQ<1>

6

77 97

BI

FB_B1_DQ<2>

6

77 97

BI

FB_B1_DQ<3>

6

77 97

BI

FB_B1_DQ<4>

6

77 97

BI

FB_B1_DQ<5>

6

77 97

BI

FB_B1_DQ<6>

6

77 97

BI

FB_B1_DQ<7>

6

77 97

BI

FB_B1_DQ<8>

6

77 97

BI

FB_B1_DQ<9>

6

77 97

BI

FB_B1_DQ<10>

6

77 97

BI

FB_B1_DQ<11>

6

77 97

BI

FB_B1_DQ<12>

6

77 97

BI

FB_B1_DQ<13>

6

77 97

BI

FB_B1_DQ<14>

6

77 97

BI

FB_B1_DQ<15>

6

77 97

BI

FB_B1_DQ<16>

6

77 97

BI

FB_B1_DQ<17>

6

77 97

BI

FB_B1_DQ<18>

6

77 97

BI

FB_B1_DQ<19>

6

77 97

BI

FB_B1_DQ<20>

6

77 97

BI

FB_B1_DQ<21>

6

77 97

BI

FB_B1_DQ<22>

6

77 97

BI

FB_B1_DQ<23>

6

77 97

BI

FB_B1_DQ<24>

6

77 97

BI

FB_B1_DQ<25>

6

77 97

BI

FB_B1_DQ<26>

6

77 97

BI

FB_B1_DQ<27>

6

77 97

BI

FB_B1_DQ<28>

6

77 97

BI

FB_B1_DQ<29>

6

77 97

BI

FB_B1_DQ<30>

6

77 97

BI

FB_B1_DQ<31>

6

77 97

BI

FB_B_VREFD

75

FB_B_VREFS

75

GPU_TEST_EN

1

5%

402

2

GPU_CLK_TEST_P GPU_CLK_TEST_N

1

R8206

40.2

1% 1/16W MF-LF 402

2

FB_B_VREFS

1

R8207

100

1% 1/16W MF-LF 402

2

C5

DQB0_0/DQB_0

C3

DQB0_1/DQB_1

E3

DQB0_2/DQB_2

E1

DQB0_3/DQB_3

F1

DQB0_4/DQB_4

F3

DQB0_5/DQB_5

F5

DQB0_6/DQB_6

G4

DQB0_7/DQB_7

H5

DQB0_8/DQB_8

H6

DQB0_9/DQB_9

J4

DQB0_10/DQB_10

K6

DQB0_11/DQB_11

K5

DQB0_12/DQB_12

L4

DQB0_13/DQB_13

M6

DQB0_14/DQB_14

M1

DQB0_15/DQB_15

M3

DQB0_16/DQB_16

M5

DQB0_17/DQB_17

N4

DQB0_18/DQB_18

P6

DQB0_19/DQB_19

P5

DQB0_20/DQB_20

R4

DQB0_21/DQB_21

T6

DQB0_22/DQB_22

T1

DQB0_23/DQB_23

U4

DQB0_24/DQB_24

V6

DQB0_25/DQB_25

V1

DQB0_26/DQB_26

V3

DQB0_27/DQB_27

Y6

DQB0_28/DQB_28

Y1

DQB0_29/DQB_29

Y3

DQB0_30/DQB_30

Y5

DQB0_31/DQB_31

AA4

DQB1_0/DQB32

AB6

DQB1_1/DQB33

AB1

DQB1_2/DQB34

AB3

DQB1_3/DQB35

AD6

DQB1_4/DQB36

AD1

DQB1_5/DQB37

AD3

DQB1_6/DQB38

AD5

DQB1_7/DQB39

AF1

DQB1_8/DQB40

AF3

DQB1_9/DQB41

AF6

DQB1_10/DQB42

AG4

DQB1_11/DQB43

AH5

DQB1_12/DQB44

AH6

DQB1_13/DQB45

AJ4

DQB1_14/DQB46

AK3

DQB1_15/DQB47

AF8

DQB1_16/DQB48

AF9

DQB1_17/DQB49

AG8

DQB1_18/DQB50

AG7

DQB1_19/DQB51

AK9

DQB1_20/DQB52

AL7

DQB1_21/DQB53

AM8

DQB1_22/DQB54

AM7

DQB1_23/DQB55

AK1

DQB1_24/DQB56

AL4

DQB1_25/DQB57

AM6

DQB1_26/DQB58

AM1

DQB1_27/DQB59

AN4

DQB1_28/DQB60

AP3

DQB1_29/DQB61

AP1

DQB1_30/DQB62

AP5

DQB1_31/DQB63

Y12

MVREFDB

AA12

MVREFSB

AD28

TESTEN

AK10

CLKTESTA

AL10

CLKTESTB

NOSTUFF

C8251

GPU_CLK_TEST_RC_P

R8251

NOSTUFF

75

PLACE_NEAR=U8000.AA12:2.54MM

1

C8203

0.1UF

10% 16V

2

X5R 402-1

U8000

WHISTLER

40NM-ES

FCBGA

(5 OF 9)

MEM INTERFACE B

OMIT

DDBIB0_0/QSB_0B/WDQSB_0 DDBIB0_1/QSB_1B/WDQSB_1 DDBIB0_2/QSB_2B/WDQSB_2 DDBIB0_3/QSB_3B/WDQSB_3

DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_1/QSB_5B/WDQSB_5 DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_3/QSB_7B/WDQSB_7

1

0.1UF

402-1

51.1

1/16W MF-LF

10% 16V X5R

1

2

1

1%

402

2

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7

MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0_0*/DQMB_1

WCKB0_1/DQMB_2

WCKB0_1*/DQMB_3

WCKB1_0/DQMB_4

WCKB1_0*/DQMB_5

WCKB1_1/DQMB_6

WCKB1_1*/DQMB_7

EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3

EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7

ADBIB0/ODTB0

ADBIB1/ODTB1

NOSTUFF

C8252

0.1UF

10% 16V X5R 402-1

GPU_CLK_TEST_RC_N

R8252

51.1

NOSTUFF

1% 1/16W MF-LF 402

CLKB0

CLKB0*

CLKB1

CLKB1*

RASB0* RASB1*

CASB0* CASB1*

CSB0_0* CSB0_1*

CSB1_0* CSB1_1*

CKEB0 CKEB1

WEB0* WEB1*

MAB0_8 MAB1_8

DRAM_RST

P8 T9 P9 N7 N8 N9 U9 U8

Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

H3 H1

T3 T5

AE4 AF5

AK6 AK5

F6 K3 P3 V5

AB5 AH1 AJ9 AM5

G7 K1 P1 W4

AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8

AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

T8 W8

AH11

FB_B0_A<0> FB_B0_A<1> FB_B0_A<2> FB_B0_A<3> FB_B0_A<4> FB_B0_A<5> FB_B0_A<6> FB_B0_A<7>

FB_B1_A<0> FB_B1_A<1> FB_B1_A<2> FB_B1_A<3> FB_B1_A<4> FB_B1_A<5> FB_B1_A<6> FB_B1_A<7>

FB_B0_WCLK_P<0> FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1> FB_B0_WCLK_N<1>

FB_B1_WCLK_P<0> FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1> FB_B1_WCLK_N<1>

FB_B0_EDC<0> FB_B0_EDC<1> FB_B0_EDC<2> FB_B0_EDC<3>

FB_B1_EDC<0> FB_B1_EDC<1> FB_B1_EDC<2> FB_B1_EDC<3>

FB_B0_DBI_L<0> FB_B0_DBI_L<1> FB_B0_DBI_L<2> FB_B0_DBI_L<3>

FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3>

FB_B0_ABI_L FB_B1_ABI_L

FB_B0_CLK_P FB_B0_CLK_N

FB_B1_CLK_P FB_B1_CLK_N

FB_B0_RAS_L FB_B1_RAS_L

FB_B0_CAS_L FB_B1_CAS_L

FB_B0_CS_L

NC

FB_B1_CS_L

NC

FB_B0_CKE_L FB_B1_CKE_L

FB_B0_WE_L FB_B1_WE_L

FB_B0_A<8> FB_B1_A<8>

GPU_FB_RESET_L

R8260

36

2 1

6

77 97

5.1K

1/16W MF-LF

OUT

1

5%

402

2

Power aliases required by this page:

6

77 97

- =PP1V5R1V35_FB_CAL

6

77 97

- =PP1V5R1V35_FB_REF

6

77 97

Signal aliases required by this page:

6

77 97

(NONE)

6

77 97

6

77 97

BOM options provided by this page:

6

77 97

(NONE)

6

77 97

6

77 97

6

77 97

6

77 97

6

77 97

6

77 97

6

77 97

6

77 97

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

6

77 97

BI

77 97

6

77 97

6

77 97

R8261

10

1/16W MF-LF

402

5%

FB_RESET_RC_L

1

C8260

120PF

5% 50V

2

CERM 402

1 2

SYNC_MASTER=K92_MLB

PAGE TITLE

Whistler FRAME BUFFER I/F

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Page Notes

Apple Inc.

R8262

51

1 2

5% 1/16W MF-LF

402

FB_RESET_L

OUT

SYNC_DATE=08/03/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

82 OF 132

SHEET

75 OF 101

76 77 97

SIZE

D

C

B

A

D

Page Notes

Power aliases required by this page:

- =PP1V5R1V35_S0_FB_VDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

GPU:WHISTLER is the BOM option called out on all Rs and Cs on this page

PP1V5_S0GPU_ISNS

7

74 75 76 77

100

D

75 97

1

R8400

120

1%

R8404

1/20W

MF

201

120

2

1/20W

C

77

100

PP1V5_S0GPU_ISNS

7

74

75 76

1

C8400

4.7UF

20%

6.3V

2

X5R

402

1

C8403

4.7UF

20%

6.3V

2

X5R 402

1

C8406

1UF

B

A

10%

6.3V

2

CERM-X5R 402

1

C8410

1UF

10%

6.3V

2

CERM-X5R 402

1

C8414

1UF

10%

6.3V

2

CERM-X5R 402

1

C8418

0.1UF

10%

6.3V

2

X5R 201

1

C8422

0.1UF

10%

6.3V

2

X5R 201

1

C8401

4.7UF

20%

6.3V

2

X5R 402

1

C8404

4.7UF

20%

6.3V

2

X5R 402

1

C8407

1UF

10%

6.3V

2

CERM-X5R 402

1

C8411

1UF

10%

6.3V

2

CERM-X5R 402

1

C8415

1UF

10%

6.3V

2

CERM-X5R 402

1

C8419

0.1UF

10%

6.3V

2

X5R 201

1

C8423

0.1UF

10%

6.3V

2

X5R 201

8 7 5 4 2 1

IN

1

1%

MF

201

2

1

C8402

4.7UF

20%

6.3V

2

X5R 402

1

C8405

4.7UF

20%

6.3V

2

X5R 402

1

C8408

1UF

10%

6.3V

2

CERM-X5R 402

1

C8412

1UF

10%

6.3V

2

CERM-X5R 402

1

C8416

0.1UF

10%

6.3V

2

X5R 201

1

C8420

0.1UF

10%

6.3V

2

X5R 201

1

C8424

0.1UF

10%

6.3V

2

X5R 201

FB_A0_VREFC

76

FB_A0_VREFD1

76

FB_A0_VREFD2

76

1

R8401

60.4

1% 1/16W MF-LF 402

2

R8403

120

1/20W

1

C8409

2

1

C8413

2

1

C8417

2

1

C8421

2

1

C8425

2

1%

MF

201

1UF

10%

6.3V CERM-X5R 402

1UF

10%

6.3V CERM-X5R 402

0.1UF

10%

6.3V X5R 201

0.1UF

10%

6.3V X5R 201

0.1UF

10%

6.3V X5R 201

1

R8402

60.4

2

1

2

1% 1/16W MF-LF 402

FB_A0_A<2>

6

75 97

IN

FB_A0_A<5>

6

75 97

IN

FB_A0_A<4>

6

75 97

IN

FB_A0_A<3>

6

75 97

IN

FB_A0_A<7>

6

75 97

IN

FB_A0_A<1>

6

75

IN

97

FB_A0_A<0>

6

75

IN

97

FB_A0_A<6>

6

75 97

IN

FB_A0_CKE_L

75 97

IN

FB_A0_CLK_P FB_A0_CLK_N FB_A0_CS_L

75 97

IN

FB_A0_WE_L

75 97

IN

FB_A0_CAS_L

75 97

IN

FB_A0_RAS_L

75 97

IN

FB_A0_ZQ FB_A0_MF FB_A0_SEN FB_RESET_L

75 76 77 97

IN

FB_A0_ABI_L

6

75 97

IN

FB_A0_EDC<0>

6

75 97

BI

FB_A0_EDC<1>

6

75 97

BI

FB_A0_EDC<3>

6

75 97

BI

FB_A0_EDC<2>

6

75 97

BI

FB_A0_WCLK_P<0>

6

75 97

IN

FB_A0_WCLK_N<0>

6

75 97

IN

FB_A0_WCLK_P<1>

6

75 97

IN

FB_A0_WCLK_N<1>

6

75 97

IN

U8400

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

C10 D11

G11 G14

L11 L14 P11

R10

B12 B14

D12 D14

E10

F12 F14

G13

H12

K12

L13

M12 M14

N10

P12 P14

T12 T14

J14 A10 U10

C5

G1 G4

VDD

L1 L4

R5

B1 B3

D1 D3

E5

F1 F3

G2

VDDQ

H3

K3

L2

M1 M3

N5

P1 P3

T1 T3

VREFC

VREFD

(2 OF 2)

BGA

OMIT

VSSQ

VSS

32MX32-1.25GHZ-MFL

BA0/A2 BA1/A5 BA2/A4 BA3/A3

A8/A7 A9/A1 A10/A0 A11/A6 CKE*

CK CK* CS* WE* CAS* RAS*

MFZQ(MF=0) SEN RESET*

ABI*

EDC0 EDC1 EDC2 EDC3

WCK01 WCK01*

WCK23 WCK23*

PP1V5_S0GPU_ISNS

7

74 75

76 77

100

FB_A0_VREFC

76

PP1V5_S0GPU_ISNS

7

74 75

76 77

100

FB_A0_VREFD1

76

PP1V5_S0GPU_ISNS

7

74 75

76 77

100

FB_A0_VREFD2

76

H5GQ1H24AFR-T2C

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

H11 K10 K11 H10

J12 J11 G12 L12

J13

J10

C13 R13

K4 H5 H4 K5 J3

L3 G3

J1

J2

J4

C2

R2

D4 D5

P4 P5

U8400

BGA

(1 OF 2)

OMIT

1

R8430

2.37K

1% 1/16W MF-LF 402

2

1

R8431

5.49K

1% 1/16W MF-LF 402

2

1

R8432

2.37K

1% 1/16W MF-LF 402

2

1

R8433

5.49K

1% 1/16W MF-LF 402

2

1

R8434

2.37K

1% 1/16W MF-LF 402

2

1

R8435

5.49K

1% 1/16W MF-LF 402

2

DBI0* DBI1* DBI2* DBI3*

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

NC

GPU:WHISTLER is the BOM option called out on ALL Rs and Cs on this page!

D2 D13 P13 P2

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

A5

NC

J5 U5

NC

1

C8430

1UF

10%

6.3V

2

CERM-X5R 402

1

C8431

1UF

10%

6.3V

2

CERM-X5R 402

1

C8432

1UF

10%

6.3V

2

CERM-X5R 402

1

C8433

1UF

10%

6.3V

2

CERM-X5R 402

1

C8434

1UF

10%

6.3V

2

CERM-X5R 402

1

C8435

1UF

10%

6.3V

2

CERM-X5R 402

FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<3> FB_A0_DBI_L<2>

FB_A0_DQ<0> FB_A0_DQ<1> FB_A0_DQ<2> FB_A0_DQ<3> FB_A0_DQ<4> FB_A0_DQ<5> FB_A0_DQ<6> FB_A0_DQ<7> FB_A0_DQ<8> FB_A0_DQ<9> FB_A0_DQ<10> FB_A0_DQ<11> FB_A0_DQ<14> FB_A0_DQ<13> FB_A0_DQ<12> FB_A0_DQ<15> FB_A0_DQ<31> FB_A0_DQ<30> FB_A0_DQ<29> FB_A0_DQ<28> FB_A0_DQ<26> FB_A0_DQ<27> FB_A0_DQ<24> FB_A0_DQ<25> FB_A0_DQ<20> FB_A0_DQ<23> FB_A0_DQ<21> FB_A0_DQ<22> FB_A0_DQ<17> FB_A0_DQ<18> FB_A0_DQ<16> FB_A0_DQ<19>

100

FB_A0_A<8>

100

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

PP1V5_S0GPU_ISNS

7

74 75 76 77

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

IN

PP1V5_S0GPU_ISNS

7

74 75 76 77

1

C8450

4.7UF

20%

6.3V

2

X5R 402

1

C8453

4.7UF

20%

6.3V

2

X5R 402

1

C8456

1UF

10%

6.3V

2

CERM-X5R 402

1

C8460

1UF

10%

6.3V

2

CERM-X5R 402

1

C8464

1UF

10%

6.3V

2

CERM-X5R 402

1

C8468

0.1UF

10%

6.3V

2

X5R 201

1

C8472

0.1UF

10%

6.3V

2

X5R 201

R8450

120

1/20W

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1%

MF

201

2

C8451

4.7UF

20%

6.3V X5R 402

C8454

4.7UF

20%

6.3V X5R 402

C8457

1UF

10%

6.3V CERM-X5R 402

C8461

1UF

10%

6.3V CERM-X5R 402

C8465

1UF

10%

6.3V CERM-X5R 402

C8469

0.1UF

10%

6.3V X5R 201

C8473

0.1UF

10%

6.3V X5R 201

75 97

IN

75 97

IN

R8454

120

1/20W

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

1%

MF

201

2

C8452

4.7UF

20%

6.3V X5R 402

C8455

4.7UF

20%

6.3V X5R 402

C8458

1UF

10%

6.3V CERM-X5R 402

C8462

1UF

10%

6.3V CERM-X5R 402

C8466

0.1UF

10%

6.3V X5R 201

C8470

0.1UF

10%

6.3V X5R 201

C8474

0.1UF

10%

6.3V X5R 201

FB_A1_VREFC

76

FB_A1_VREFD1

76

FB_A1_VREFD2

76

1

R8451

60.4

1% 1/16W MF-LF 402

2

R8453

1

2

1

2

1

2

1

2

1

2

1

120

1%

1/20W

MF

201

2

C8459

1UF

10%

6.3V CERM-X5R 402

C8463

1UF

10%

6.3V CERM-X5R 402

C8467

0.1UF

10%

6.3V X5R 201

C8471

0.1UF

10%

6.3V X5R 201

C8475

0.1UF

10%

6.3V X5R 201

1

R8452

60.4

1% 1/16W MF-LF 402

2

FB_A1_A<2>

6

75 97

IN

FB_A1_A<5>

6

75 97

IN

FB_A1_A<4>

6

75 97

IN

FB_A1_A<3>

6

75 97

IN

FB_A1_A<7>

6

75 97

IN

FB_A1_A<1>

6

75

IN

97

FB_A1_A<0>

6

75

IN

97

FB_A1_A<6>

6

75 97

IN

FB_A1_CKE_L

75 97

IN

FB_A1_CLK_P FB_A1_CLK_N FB_A1_CS_L

75 97

IN

FB_A1_WE_L

75 97

IN

FB_A1_CAS_L

75 97

IN

FB_A1_RAS_L

75 97

IN

FB_A1_ZQ FB_A1_MF FB_A1_SEN

FB_RESET_L

75 76 77 97

IN

FB_A1_ABI_L

6

75 97

IN

FB_A1_EDC<0>

6

75 97

BI

FB_A1_EDC<1>

6

75 97

BI

FB_A1_EDC<2>

6

75 97

BI

FB_A1_EDC<3>

6

75 97

BI

FB_A1_WCLK_P<0>

6

75 97

IN

FB_A1_WCLK_N<0>

6

75 97

IN

FB_A1_WCLK_P<1>

6

75 97

IN

FB_A1_WCLK_N<1>

6

75 97

IN

U8450

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

C10 D11

G11 G14

L11 L14 P11

R10

B12 B14

D12 D14

E10

F12 F14

G13

H12

K12

L13

M12 M14

N10

P12 P14

T12 T14

J14 A10 U10

C5

G1 G4

VDD

L1 L4

R5

B1 B3

D1 D3

E5

F1 F3

G2

VDDQ

H3

K3

L2

M1 M3

N5

P1 P3

T1 T3

VREFC

VREFD

(2 OF 2)

BGA

OMIT

345678

U8450

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT

PP1V5_S0GPU_ISNS

7 76 77

FB_A1_VREFC

PP1V5_S0GPU_ISNS

7 76 77

FB_A1_VREFD1

76

VSSQ

VSS

32MX32-1.25GHZ-MFL

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J3

CKE*

J12

CK

J11

CK*

G12

CS*

L12

WE*

L3

CAS*

G3

RAS*

J13

J1

MFZQ(MF=0)

J10

SEN

J2

RESET*

J4

ABI*

C2

EDC0

C13

EDC1

R13

EDC2

R2

EDC3

D4

WCK01

D5

WCK01*

P4

WCK23

P5

WCK23*

B5 B10

74 75

D10

100

G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3

74 75

100

A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

2 1

D2

DBI0*

D13

DBI1*

P13

DBI2*

P2

DBI3*

A4

DQ0

A2

DQ1

B4

DQ2

B2

DQ3

E4

DQ4

E2

DQ5

F4

DQ6

F2

DQ7

A11

DQ8

A13

DQ9

B11

DQ10

B13

DQ11

E11

DQ12

E13

DQ13

F11

DQ14

F13

DQ15

U11

DQ16

U13

DQ17

T11

DQ18

T13

DQ19

N11

DQ20

N13

DQ21

M11

DQ22

M13

DQ23

U4

DQ24

U2

DQ25

T4

DQ26

T2

DQ27

N4

DQ28

N2

DQ29

M4

DQ30

M2

DQ31

A5

NC

J5

NC

U5

NC

100

1

R8480

2.37K

1% 1/16W MF-LF 402

2

1

R8481

5.49K

1% 1/16W MF-LF 402

2

1

R8482

2.37K

1% 1/16W MF-LF 402

2

1

R8483

5.49K

1% 1/16W MF-LF 402

2

1

C8480

1UF

10%

6.3V

2

CERM-X5R 402

1

C8481

1UF

10%

6.3V

2

CERM-X5R 402

1

C8482

1UF

10%

6.3V

2

CERM-X5R 402

1

C8483

1UF

10%

6.3V

2

CERM-X5R 402

SYNC_MASTER=K92_MLB

PAGE TITLE

GDDR5 Frame Buffer A

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<2> FB_A1_DBI_L<3>

FB_A1_DQ<1> FB_A1_DQ<0> FB_A1_DQ<3> FB_A1_DQ<2> FB_A1_DQ<4> FB_A1_DQ<6> FB_A1_DQ<5> FB_A1_DQ<7> FB_A1_DQ<9> FB_A1_DQ<8> FB_A1_DQ<11> FB_A1_DQ<10> FB_A1_DQ<12> FB_A1_DQ<13> FB_A1_DQ<14> FB_A1_DQ<15> FB_A1_DQ<21> FB_A1_DQ<22> FB_A1_DQ<23> FB_A1_DQ<20> FB_A1_DQ<18> FB_A1_DQ<19> FB_A1_DQ<17> FB_A1_DQ<16> FB_A1_DQ<31> FB_A1_DQ<30> FB_A1_DQ<28> FB_A1_DQ<29> FB_A1_DQ<25> FB_A1_DQ<27> FB_A1_DQ<24> FB_A1_DQ<26>

FB_A1_A<8>

PP1V5_S0GPU_ISNS

7

74 75 76 77

FB_A1_VREFD2

76 76

Apple Inc.

R

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

IN

1

R8484

2.37K

1% 1/16W MF-LF 402

2

1

R8485

5.49K

1% 1/16W MF-LF 402

2

1

C8484

1UF

10%

6.3V

2

CERM-X5R 402

1

C8485

1UF

10%

6.3V

2

CERM-X5R 402

SYNC_DATE=08/19/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

84 OF 132

SHEET

76 OF 101

SIZE

D

C

B

A

D

36

Power aliases required by this page:

- =PP1V5R1V35_S0_FB_VDD

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

7

74 75 76 77

100

D

C

77

100

PP1V5_S0GPU_ISNS

7

74

75 76

1

2

1

2

1

B

A

2

1

2

1

2

1

2

1

2

345678

Page Notes

U8500

32MX32-1.25GHZ-MFL

VSSQ

VSS

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

H11 K10 K11 H10

J12 J11 G12 L12

J13

J10

C13 R13

K4 H5 H4 K5 J3

L3 G3

J1

J2

J4

C2

R2

D4 D5

P4 P5

BA0/A2 BA1/A5 BA2/A4 BA3/A3

A8/A7 A9/A1 A10/A0 A11/A6 CKE*

CK CK* CS* WE* CAS* RAS*

MFZQ(MF=0) SEN RESET*

ABI*

EDC0 EDC1 EDC2 EDC3

WCK01 WCK01*

WCK23 WCK23*

100

PP1V5_S0GPU_ISNS

7

74 75

76 77

FB_B0_VREFC

77

PP1V5_S0GPU_ISNS

7

74 75

76 77

FB_B0_VREFD1

77

PP1V5_S0GPU_ISNS

7

74 75

76 77

FB_B0_VREFD2

77

PP1V5_S0GPU_ISNS

1

R8500

120

1%

1/20W

MF

201

2

C8500

4.7UF

20%

6.3V X5R 402

C8503

4.7UF

20%

6.3V X5R 402

C8506

1UF

10%

6.3V CERM-X5R 402

C8510

1UF

10%

6.3V CERM-X5R 402

C8514

1UF

10%

6.3V CERM-X5R 402

C8518

0.1UF

10%

6.3V X5R 201

C8522

0.1UF

10%

6.3V X5R 201

1

C8501

4.7UF

20%

6.3V

2

X5R 402

1

C8504

4.7UF

20%

6.3V

2

X5R 402

1

C8507

1UF

10%

6.3V

2

CERM-X5R 402

1

C8511

1UF

10%

6.3V

2

CERM-X5R 402

1

C8515

1UF

10%

6.3V

2

CERM-X5R 402

1

C8519

0.1UF

10%

6.3V

2

X5R 201

1

C8523

0.1UF

10%

6.3V

2

X5R 201

75 97

R8504

120

1/20W

IN

1

1%

MF

201

2

1

C8502

4.7UF

20%

6.3V

2

X5R 402

1

C8505

4.7UF

20%

6.3V

2

X5R 402

1

C8508

1UF

10%

6.3V

2

CERM-X5R 402

1

C8512

1UF

10%

6.3V

2

CERM-X5R 402

1

C8516

0.1UF

10%

6.3V

2

X5R 201

1

C8520

0.1UF

10%

6.3V

2

X5R 201

1

C8524

0.1UF

10%

6.3V

2

X5R 201

FB_B0_VREFC

77

FB_B0_VREFD1

77

FB_B0_VREFD2

77

1

R8501

60.4

1% 1/16W MF-LF 402

2

R8503

120

1/20W

1

C8509

2

1

C8513

2

1

C8517

2

1

C8521

2

1

C8525

2

1%

MF

201

1UF

10%

6.3V CERM-X5R 402

1UF

10%

6.3V CERM-X5R 402

0.1UF

10%

6.3V X5R 201

0.1UF

10%

6.3V X5R 201

0.1UF

10%

6.3V X5R 201

1

R8502

60.4

2

1

2

1% 1/16W MF-LF 402

FB_B0_A<2>

6

75 97

IN

FB_B0_A<5>

6

75 97

IN

FB_B0_A<4>

6

75 97

IN

FB_B0_A<3>

6

75 97

IN

FB_B0_A<7>

6

75 97

IN

FB_B0_A<1>

6

75

IN

97

FB_B0_A<0>

6

75

IN

97

FB_B0_A<6>

6

75 97

IN

FB_B0_CKE_L

75 97

IN

FB_B0_CLK_P FB_B0_CLK_N FB_B0_CS_L

75 97

IN

FB_B0_WE_L

75 97

IN

FB_B0_CAS_L

75 97

IN

FB_B0_RAS_L

75 97

IN

FB_B0_ZQ FB_B0_MF FB_B0_SEN FB_RESET_L

75 76 77 97

IN

FB_B0_ABI_L

6

75 97

IN

FB_B0_EDC<0>

6

75 97

BI

FB_B0_EDC<1>

6

75 97

BI

FB_B0_EDC<3>

6

75 97

BI

FB_B0_EDC<2>

6

75 97

BI

FB_B0_WCLK_P<0>

6

75 97

IN

FB_B0_WCLK_N<0>

6

75 97

IN

FB_B0_WCLK_P<1>

6

75 97

IN

FB_B0_WCLK_N<1>

6

75 97

IN

U8500

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

C10 D11

G11 G14

L11 L14 P11

R10

B12 B14

D12 D14

E10

F12 F14

G13

H12

K12

L13

M12 M14

N10

P12 P14

T12 T14

J14 A10 U10

C5

G1 G4

VDD

L1 L4

R5

B1 B3

D1 D3

E5

F1 F3

G2

VDDQ

H3

K3

L2

M1 M3

N5

P1 P3

T1 T3

VREFC

VREFD

(2 OF 2)

BGA

OMIT

8 7 5 4 2 1

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT

1

R8530

2.37K

1% 1/16W MF-LF 402

2

1

R8531

5.49K

1% 1/16W MF-LF 402

2

1

R8532

2.37K

1% 1/16W MF-LF 402

2

1

R8533

5.49K

1% 1/16W MF-LF 402

2

1

R8534

2.37K

1% 1/16W MF-LF 402

2

1

R8535

5.49K

1% 1/16W MF-LF 402

2

DBI0* DBI1* DBI2* DBI3*

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

NC

D2 D13 P13 P2

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

A5

NC

J5 U5

NC

1

C8530

1UF

10%

6.3V

2

CERM-X5R 402

1

C8531

1UF

10%

6.3V

2

CERM-X5R 402

1

C8532

1UF

10%

6.3V

2

CERM-X5R 402

1

C8533

1UF

10%

6.3V

2

CERM-X5R 402

1

C8534

1UF

10%

6.3V

2

CERM-X5R 402

1

C8535

1UF

10%

6.3V

2

CERM-X5R 402

FB_B0_DBI_L<0> FB_B0_DBI_L<1> FB_B0_DBI_L<3> FB_B0_DBI_L<2>

FB_B0_DQ<0> FB_B0_DQ<1> FB_B0_DQ<2> FB_B0_DQ<3> FB_B0_DQ<4> FB_B0_DQ<5> FB_B0_DQ<6> FB_B0_DQ<7> FB_B0_DQ<8> FB_B0_DQ<9> FB_B0_DQ<10> FB_B0_DQ<11> FB_B0_DQ<12> FB_B0_DQ<13> FB_B0_DQ<14> FB_B0_DQ<15> FB_B0_DQ<31> FB_B0_DQ<30> FB_B0_DQ<29> FB_B0_DQ<28> FB_B0_DQ<25> FB_B0_DQ<26> FB_B0_DQ<27> FB_B0_DQ<24> FB_B0_DQ<23> FB_B0_DQ<22> FB_B0_DQ<19> FB_B0_DQ<21> FB_B0_DQ<20> FB_B0_DQ<18> FB_B0_DQ<17> FB_B0_DQ<16>

100

FB_B0_A<8>

100

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

PP1V5_S0GPU_ISNS

7

74 75 76 77

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

IN

PP1V5_S0GPU_ISNS

7

74 75 76 77

1

C8550

4.7UF

20%

6.3V

2

X5R 402

1

C8553

4.7UF

20%

6.3V

2

X5R 402

1

C8556

1UF

10%

6.3V

2

CERM-X5R 402

1

C8560

1UF

10%

6.3V

2

CERM-X5R 402

1

C8564

1UF

10%

6.3V

2

CERM-X5R 402

1

C8568

0.1UF

10%

6.3V

2

X5R 201

1

C8572

0.1UF

10%

6.3V

2

X5R 201

R8550

120

1/20W

1

1%

MF

201

2

1

C8551

4.7UF

20%

6.3V

2

X5R 402

1

C8554

4.7UF

20%

6.3V

2

X5R 402

1

C8557

1UF

10%

6.3V

2

CERM-X5R 402

1

C8561

1UF

10%

6.3V

2

CERM-X5R 402

1

C8565

1UF

10%

6.3V

2

CERM-X5R 402

1

C8569

0.1UF

10%

6.3V

2

X5R 201

1

C8573

0.1UF

10%

6.3V

2

X5R 201

75 97

R8554

120

1/20W

IN

1

1%

MF

201

2

1

C8552

4.7UF

20%

6.3V

2

X5R 402

1

C8555

4.7UF

20%

6.3V

2

X5R 402

1

C8558

1UF

10%

6.3V

2

CERM-X5R 402

1

C8562

1UF

10%

6.3V

2

CERM-X5R 402

1

C8566

0.1UF

10%

6.3V

2

X5R 201

1

C8570

0.1UF

10%

6.3V

2

X5R 201

1

C8574

0.1UF

10%

6.3V

2

X5R 201

FB_B1_VREFC

77

FB_B1_VREFD1

77

FB_B1_VREFD2

77

1

R8551

60.4

1% 1/16W MF-LF 402

2

R8553

120

1/20W

1

C8559

1UF

10%

6.3V

2

CERM-X5R 402

1

C8563

1UF

10%

6.3V

2

CERM-X5R 402

1

C8567

0.1UF

10%

6.3V

2

X5R 201

1

C8571

0.1UF

10%

6.3V

2

X5R 201

1

C8575

0.1UF

10%

6.3V

2

X5R 201

201

1%

MF

1

R8552

60.4

1% 1/16W MF-LF 402

2

1

2

FB_B1_A<2>

6

75 97

IN

FB_B1_A<5>

6

75 97

IN

FB_B1_A<4>

6

75 97

IN

FB_B1_A<3>

6

75 97

IN

FB_B1_A<7>

6

75 97

IN

FB_B1_A<1>

6

75

IN

97

FB_B1_A<0>

6

75

IN

97

FB_B1_A<6>

6

75 97

IN

FB_B1_CKE_L

75 97

IN

FB_B1_CLK_P FB_B1_CLK_N FB_B1_CS_L

75 97

IN

FB_B1_WE_L

75 97

IN

FB_B1_CAS_L

75 97

IN

FB_B1_RAS_L

75 97

IN

FB_B1_ZQFB_B1_ZQ

77 77

FB_B1_MF FB_B1_SEN FB_RESET_L

75 76 77 97

IN

FB_B1_ABI_L

6

75 97

IN

FB_B1_EDC<0>

6

75 97

BI

FB_B1_EDC<1>

6

75 97

BI

FB_B1_EDC<2>

6

75 97

BI

FB_B1_EDC<3>

6

75 97

BI

FB_B1_WCLK_P<0>

6

75 97

IN

FB_B1_WCLK_N<0>

6

75 97

IN

FB_B1_WCLK_P<1>

6

75 97

IN

FB_B1_WCLK_N<1>

6

75 97

IN

U8550

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

C10 D11

G11 G14

L11 L14 P11

R10

B12 B14

D12 D14

E10

F12 F14

G13

H12

K12

L13

M12 M14

N10

P12 P14

T12 T14

J14 A10 U10

C5

G1 G4

VDD

L1 L4

R5

B1 B3

D1 D3

E5

F1 F3

G2

VDDQ

H3

K3

L2

M1 M3

N5

P1 P3

T1 T3

VREFC

VREFD

(2 OF 2)

BGA

OMIT

VSS

VSSQ

36

32MX32-1.25GHZ-MFL

H11

BA0/A2

K10

BA1/A5

K11

BA2/A4

H10

BA3/A3

K4

A8/A7

H5

A9/A1

H4

A10/A0

K5

A11/A6

J3

CKE*

J12

CK

J11

CK*

G12

CS*

L12

WE*

L3

CAS*

G3

RAS*

J13

J1

MFZQ(MF=0)

J10

SEN

J2

RESET*

J4

ABI*

C2

EDC0

C13

EDC1

R13

EDC2

R2

EDC3

D4

WCK01

D5

WCK01*

P4

WCK23

P5

WCK23*

B5 B10

74 75

D10

100

G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

A1 A3

74 75

100

A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

U8550

BGA

H5GQ1H24AFR-T2C

(1 OF 2)

OMIT

PP1V5_S0GPU_ISNS

7 76 77

FB_B1_VREFC

77

PP1V5_S0GPU_ISNS

7 76 77

FB_B1_VREFD1

77

2 1

D2

DBI0*

D13

DBI1*

P13

DBI2*

P2

DBI3*

A4

DQ0

A2

DQ1

B4

DQ2

B2

DQ3

E4

DQ4

E2

DQ5

F4

DQ6

F2

DQ7

A11

DQ8

A13

DQ9

B11

DQ10

B13

DQ11

E11

DQ12

E13

DQ13

F11

DQ14

F13

DQ15

U11

DQ16

U13

DQ17

T11

DQ18

T13

DQ19

N11

DQ20

N13

DQ21

M11

DQ22

M13

DQ23

U4

DQ24

U2

DQ25

T4

DQ26

T2

DQ27

N4

DQ28

N2

DQ29

M4

DQ30

M2

DQ31

A5

NC

J5

NC

U5

NC

100

1

R8580

2.37K

1% 1/16W MF-LF 402

2

1

R8581

5.49K

1% 1/16W MF-LF 402

2

1

R8582

2.37K

1% 1/16W MF-LF 402

2

1

R8583

5.49K

1% 1/16W MF-LF 402

2

1

C8580

1UF

10%

6.3V

2

CERM-X5R 402

1

C8581

1UF

10%

6.3V

2

CERM-X5R 402

1

C8582

1UF

10%

6.3V

2

CERM-X5R 402

1

C8583

1UF

10%

6.3V

2

CERM-X5R 402

SYNC_MASTER=K92_MLB

PAGE TITLE

GDDR5 Frame Buffer B

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3>

FB_B1_DQ<0> FB_B1_DQ<3> FB_B1_DQ<1> FB_B1_DQ<2> FB_B1_DQ<6> FB_B1_DQ<5> FB_B1_DQ<7> FB_B1_DQ<4> FB_B1_DQ<8> FB_B1_DQ<9> FB_B1_DQ<10> FB_B1_DQ<11> FB_B1_DQ<12> FB_B1_DQ<13> FB_B1_DQ<14> FB_B1_DQ<15> FB_B1_DQ<23> FB_B1_DQ<22> FB_B1_DQ<21> FB_B1_DQ<20> FB_B1_DQ<19> FB_B1_DQ<18> FB_B1_DQ<16> FB_B1_DQ<17> FB_B1_DQ<31> FB_B1_DQ<26> FB_B1_DQ<30> FB_B1_DQ<29> FB_B1_DQ<27> FB_B1_DQ<28> FB_B1_DQ<24> FB_B1_DQ<25>

FB_B1_A<8>

PP1V5_S0GPU_ISNS

7

74 75 76 77

FB_B1_VREFD2

77

Apple Inc.

R

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

BI

6

75 97

IN

1

R8584

2.37K

1% 1/16W MF-LF 402

2

1

R8585

5.49K

1% 1/16W MF-LF 402

2

1

C8584

1UF

10%

6.3V

2

CERM-X5R 402

1

C8585

1UF

10%

6.3V

2

CERM-X5R 402

SYNC_DATE=08/19/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

85 OF 132

SHEET

77 OF 101

SIZE

D

C

B

A

D

VRAM BOM OPTION TABLE

K92 SAMSUNG 1G

K92 HYNIX 1G

K91F SAMSUNG 512M

K91F HYNIX 512M

K91F SAMSUNG 1G

K91F HYNIX 1G

D

NOTE:

AMD STRAPS FOR IDENTIFYING VRAM VENDOR & SIZE FOR WHISTLER K92 Samsung 1G - NOSTUFF R8613, NOSTUFF R8612, STUFF R8611

K92 Hynix 1G - STUFF R8613, NOSTUFF R8612, STUFF R8611

K91FSamsung 512M - NOSTUFF R8613, NOSTUFF R8612, NOSTUFF R8611 K91FHynix 512M - NOSTUFF R8613, STUFF R8612, NOSTUFF R8611 K91FSamsung 1G - STUFF R8613, NOSTUFF R8612, NOSTUFF R8611 K91FHynix 1G - STUFF R8613, STUFF R8612, NOSTUFF R8611

NO STRAP CHANGES ARE REQUIRED FOR SEYMOUR BASED SYSTEMS

C

B

PP1V8_S0GPU_ISNS

100 7

74

78 80

VOLTAGE=1.8V

PP1V0_S0GPU_ISNS

100 7

73

74 80

A

PP1V8_S0GPU_ISNS

100 7

74

78 80

345678

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

AJ21

NC NC

NC

SWAPLOCKA

AK21

SWAPLOCKB

AK26

SCL

AJ26

SDA

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH23

GPIO_3_SMBDATA

AJ23

GPIO_4_SMBCLK

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21_BB_EN

AK13

GPIO_22_ROMCS*

AN13

GPIO_23_CLKREQ*

AM23

JTAG_TRST*

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AK24

HPD1

AH13

VREFG

AM32

DPLL_PVDD

AN32

DPLL_PVSS

AN31

DPLL_VDDC

AV33

XTALIN

AU34

XTALOUT

AW34

XO_IN

AW35

XO_IN2

AF29

DPLUS

AG29

DMINUS

AK32

TS_FDO

AL31

TSA/NC

AJ32

TSVDD

AJ33

TSVSS

OMIT

U8000

WHISTLER

40NM-ES

FCBGA

(2 OF 9)

MULTI GFX

I2C

GPIO

PLL/CLKTHERMAL

DPADPBDPCDPD

DAC1DAC2

DDC/AUX

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

TXCCP_DPC3P TXCCM_DPC3N

TX0P_DPC2P TX0M_DPC2N

TX1P_DPC1P TX1M_DPC1N

TX2P_DPC0P TX2M_DPC0N

TXCDP_DPD3P TXCDM_DPD3N

TX3P_DPD2P TX3M_DPD2N

TX4P_DPD1P TX4M_DPD1N

TX5P_DPD0P TX5M_DPD0N

H2SYNC/GENLK_CLK

V2SYNC/GENLK_VSYNC

VDD2DI/NC VSS2DI/NC

A2VDDQ/NC

A2VSSQ/TSVSSQ

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDCCLK_AUX7P

DDCDATA_AUX7N

XW8600

SM

XW8601

SM

VRAM_DVP0

NO

YES

NO

YES

470OHM-1A-150MOHM

GND_GPU_DPLL

21

GND_GPU_TSVSS

VRAM_DVP1 (STUFF R8612?)(STUFF R8613?)

NO

YES

NO

YES

CRITICAL

L8600

0603

CRITICAL

L8601

0603

CRITICAL

L8602

120OHM-0.3A

0402

VRAM_DVP2 (STUFF R8611?)

YES

NO

21

1

2

21

1

2

21

1

2

100

C8601

10UF

20% 10V X5R 603

C8604

10UF

20% 10V X5R 603

C8607

10UF

20% 10V X5R 603

PP1V8_S0GPU_ISNS

7

74 78 80

1

R8610

10K

5% 1/16W MF-LF

402

2

NOSTUFF

PP3V3_S0GPU

6 7

71 74 78 79 81 83

PP1V8_S0GPU_ISNS

7

74 78 80

100

1

C8602

1UF

10% 25V

2

X5R 402

1

C8605

1UF

10% 25V

2

X5R 402

1

C8608

1UF

10% 25V

2

X5R 402

1

R8611

VRAM_DVP2

10K

5% 1/16W MF-LF

402

R8600

2

4.7K

R8612

VRAM_DVP1

5% 1/16W MF-LF

402

R8602

R8603

C8600

1

0.1UF

10% 16V

2

X5R

402-1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8603

0.1UF

10% 16V

2

X5R 402-1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V

1

C8606

0.1UF

10% 16V

2

X5R 402-1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8609

0.1UF

10% 16V

2

X5R 402-1

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

1

2

499

1/16W MF-LF

249

1/16W MF-LF

402

10K

1%

5%

402

1

2

1

2

1

2

1

R8601

4.7K

5% 1/16W MF-LF 402

2

VOLTAGE=0V

1

R8613

10K

5% 1/16W MF-LF

402

2

VRAM_DVP0

GPU_PCIE_TX_PWR

79

GPU_GPIO_TX_DEEMP

79

GPU_PCIE_GEN2

79

GPU_SMB_DAT

79

GPU_SMB_CLK

79

GPU_AC_BATT

79

GPU_VCORE_VID0

79 81

EG_BKLT_EN

79 87

GPU_ROM_SO

79

GPU_ROM_SI

79

GPU_ROM_SCLK

79

GPU_CONFIG_0

79

GPU_CONFIG_1

79

GPU_CONFIG_2

79

DP_T29SNK0_HPD_GPU

79

GPU_VCORE_VID1

79 81

GPU_VCORE_VID2

79 81

SMC_GFX_THROTTLE_R_L

79

DP_T29SNK1_HPD_GPU

79

SMC_GFX_OVERTEMP_R_L

79

GPU_VCORE_VID3

79 81

FBVDD_ALTVO

79 86

GPU_ROM_CS_L

79

PEX_CLKREQ_L_R

79

TP_GPU_JTAG_TRST_L

79

TP_GPU_JTAG_TDI

79

TP_GPU_JTAG_TCK

79

TP_GPU_JTAG_TMS

79

TP_GPU_JTAG_TDO

79

NC_GPU_GENERICA

79

NC_GPU_GENERICB

79

NC_GPU_GENERICC

79

DP_CA_DET_EG_R

79

NC_GPU_GENERICE

79

NC_GPU_GENERICF

79

NC_GPU_GENERICG

79

DP_EG_HPD

79 83

GPU_VREFG

PP1V8_GPU_DPLL

(GND_GPU_DPLL)

PP1V0_GPU_DPLL

79 97

IN

79 97

IN

50 98

IN

50 98

OUT

PP1V8_GPU_TSVDD

(GND_GPU_TSVSS)

TP_DVPCNTL_M<0> TP_DVPCNTL_M<1>

TP_DVPCNTL<0> TP_DVPCNTL<1> TP_DVPCNTL<2>

TP_DVPCLK

DVPDATA<0>

DVPDATA<1> DVPDATA<2> DVPDATA<3> TP_DVPDATA<4> TP_DVPDATA<5> TP_DVPDATA<6> TP_DVPDATA<7> TP_DVPDATA<8> TP_DVPDATA<9> TP_DVPDATA<10> TP_DVPDATA<11> TP_DVPDATA<12> TP_DVPDATA<13> TP_DVPDATA<14> TP_DVPDATA<15> TP_DVPDATA<16> TP_DVPDATA<17> TP_DVPDATA<18> TP_DVPDATA<19> TP_DVPDATA<20> TP_DVPDATA<21> TP_DVPDATA<22> TP_DVPDATA<23>

GPU_I2C_SCL

GPU_I2C_SDA

75mA

125mA

GPU_CLK27M

GPU_CLK100M

GPU_TDIODE_P

GPU_TDIODE_N

20mA

8 7 5 4 2 1

HSYNC VSYNC

RSET

AVDD

AVSSQ

VDD1DI VSS1DI

R2/NC

R2*/NC

G2/NC

G2*/NC

B2/NC

B2*/NC

C/NC Y/NC

COMP/NC

A2VDD/NC

R2SET/NC

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDC6CLK

DDC6DATA

AU24 AV23

AT25 AR24

AU26 AV25

AT27 AR26

AR30 AT29

AV31 AU30

AR32 AT31

AT33 AU32

AU14 AV13

AT15 AR14

AU16 AV15

AT17 AR16

AU20 AT19

AT21 AR20

AU22 AV21

AT23 AR22

AD39

R

AD37

R*

AE36

G

AD35

G*

AF37

B

AE38

B*

AC36 AC38

AB34

AD34 AE34

AC33 AC34

AC30 AC31

AD30 AD31

AF30 AF31

AC32 AD32 AF32

AD29 AC29

AG31 AG32

AG33

AD33

AF33

AA29

AM26 AN26

AM27 AL27

AM19 AL19

AN20 AM20

AL30 AM30

AL29 AM29

AN21 AM21

AJ30 AJ31

AK30 AK29

DP_EXTA_ML_C_P<3> DP_EXTA_ML_C_N<3>

DP_EXTA_ML_C_P<2> DP_EXTA_ML_C_N<2>

DP_EXTA_ML_C_P<1> DP_EXTA_ML_C_N<1>

DP_EXTA_ML_C_P<0> DP_EXTA_ML_C_N<0>

DP_T29SNK0_ML_C_P<3> DP_T29SNK0_ML_C_N<3>

DP_T29SNK0_ML_C_P<2> DP_T29SNK0_ML_C_N<2>

DP_T29SNK0_ML_C_P<1> DP_T29SNK0_ML_C_N<1>

DP_T29SNK0_ML_C_P<0> DP_T29SNK0_ML_C_N<0>

DP_T29SNK1_ML_C_P<3> DP_T29SNK1_ML_C_N<3>

DP_T29SNK1_ML_C_P<2> DP_T29SNK1_ML_C_N<2>

DP_T29SNK1_ML_C_P<1> DP_T29SNK1_ML_C_N<1>

DP_T29SNK1_ML_C_P<0> DP_T29SNK1_ML_C_N<0>

NC NC

GPU_AUD_1 GPU_AUD_0

NC

NC NC

NC NC NC

NC NC

PP1V8_S0GPU_ISNS

NC

GND_GPU_TVSSQ

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

NC

DP_EG_DDC_CLK DP_EG_DDC_DATA

DP_EG_AUXCH_P DP_EG_AUXCH_N

NC NC

DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N

DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N

NC NC

LVDS_EG_DDC_CLK LVDS_EG_DDC_DATA

NC NC

XW8602

SM

84 97

OUT

84 97

OUT

84 97

OUT

84 97

OUT

84 97

OUT

84 97

OUT

84 97

OUT

84 97

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

6

33 95

OUT

1

R8604

10K

5% 1/16W MF-LF

402

2

7

74 78 80

100

21

79 83

OUT

79 83

BI

8

83 97

BI

8

83 97

BI

6

33 95

BI

6

33 95

BI

6

33 95

BI

6

33 95

BI

83

OUT

83

BI

U8000

FCBGA

(3 OF 9)

WHISTLER

LVDS CNTL

40NM-ES

OMIT

LVTMDP

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

36

2 1

Page Notes

Power aliases required by this page:

- =PP3V3_GPU_I2C

- =PP1V8_GPU_VREFG

- =PP1V8_GPU_DPLL

- =PP1V0_GPU_DPLL

- =PP1V0_GPU_TS

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

PP3V3_S0GPU

Straps for audio on DP and HDMI

1

R8605

10K

5% 1/16W MF-LF 402

2

AK27

VARY_BL

AJ27

DIGON

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

TXOUT_U3P TXOUT_U3N

TXOUT_L3P TXOUT_L3N

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36 AP37

SYNC_MASTER=K92_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

6 7

71 74 78 79 81 83

LVDS_EG_BLK_PWM EG_LCD_PWR_EN

NC_LVDS_EG_B_CLK_P NC_LVDS_EG_B_CLK_N

LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<0>

LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2>

NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_N<3>

LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_N<0>

LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_P<2> LVDS_EG_A_DATA_N<2>

NC_LVDS_EG_A_DATA_P<3> NC_LVDS_EG_A_DATA_N<3>

Whistler LVDS/DP/GPIO

Apple Inc.

R

79 87

OUT

79

OUT

87 97

79 97

87 97

79 97

1

R8606

10K

5% 1/16W MF-LF 402

2

SYNC_DATE=12/01/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

86 OF 132

SHEET

78 OF 101

SIZE

D

C

B

A

D

345678

Native Func

GPU_PCIE_TX_PWR

78 79

GPU_GPIO_TX_DEEMP

78 79

GPU_PCIE_GEN2

78 79

GPU_SMB_DAT

78 79

GPU_SMB_CLK

78 79

GPU_AC_BATT

D

78 79

GPU_VCORE_VID0

78 79 81

EG_BKLT_EN

78 79 87

GPU_ROM_SO

78 79

GPU_ROM_SI

78 79

GPU_ROM_SCLK

78 79

GPU_CONFIG_0

78 79

GPU_CONFIG_1

78 79

GPU_CONFIG_2

78 79

DP_T29SNK0_HPD_GPU

78 79

GP

GPIOs

GPU_PCIE_TX_PWR

MAKE_BASE=TRUE

GPU_GPIO_TX_DEEMP

MAKE_BASE=TRUE

GPU_PCIE_GEN2

MAKE_BASE=TRUE

GPU_SMB_DAT

MAKE_BASE=TRUE MAKE_BASE=TRUE

GPU_SMB_CLK

MAKE_BASE=TRUE

GPU_AC_BATT

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

GPU_ROM_SO

MAKE_BASE=TRUE

GPU_ROM_SI

MAKE_BASE=TRUE

GPU_ROM_SCLK

MAKE_BASE=TRUE

GPU_CONFIG_0

MAKE_BASE=TRUE

GPU_CONFIG_1

MAKE_BASE=TRUE

GPU_CONFIG_2

MAKE_BASE=TRUE

DP_T29SNK0_HPD_GPU

MAKE_BASE=TRUE

GPU_VCORE_VID1GPU_VCORE_VID1

MAKE_BASE=TRUE

78 79

78 79 81

78 79 87

78 79

78 79 81 78 79 81

GPU_VCORE_VID2

78 79 81

SMC_GFX_THROTTLE_R_L

78 79

DP_T29SNK1_HPD_GPU

78 79

SMC_GFX_OVERTEMP_R_L

78 79

GPU_VCORE_VID3

78 79 81

FBVDD_ALTVO

78 79 86

GPU_ROM_CS_L

78 79

PEX_CLKREQ_L_R

78 79

NC_GPU_GENERICA

78 79

NC_GPU_GENERICB

78 79

NC_GPU_GENERICC

78 79

DP_CA_DET_EG_R

78 79

NC_GPU_GENERICE NC_GPU_GENERICE

78 79 78 79

NC_GPU_GENERICF

78 79

NC_GPU_GENERICG

78 79

DP_EG_HPD

78 79 83

Native Func

GP

GPIOs

GPU_VCORE_VID2

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

DP_T29SNK1_HPD_GPU

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_R_L

GPU_VCORE_VID3

MAKE_BASE=TRUE

FBVDD_ALTVO

MAKE_BASE=TRUE

GPU_ROM_CS_L

MAKE_BASE=TRUE

PEX_CLKREQ_L_R

MAKE_BASE=TRUE

NC_GPU_GENERICA

MAKE_BASE=TRUE

NC_GPU_GENERICB

MAKE_BASE=TRUE

NC_GPU_GENERICC

MAKE_BASE=TRUE

DP_CA_DET_EG_R

MAKE_BASE=TRUE

NC_GPU_GENERICF

MAKE_BASE=TRUE

NC_GPU_GENERICG

MAKE_BASE=TRUE

DP_EG_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

78 79 81

78 79

78 79 81

78 79 86

78 79

78 79 83

DP_T29SNK0_HPD

33 83

PP3V3_S0GPU

6 7

71 74 78 79 81 83

DP_T29SNK1_HPD

33 83

Config Straps

PP3V3_S0GPU

6 7

71 74 78 79 81 83

NOSTUFF

R8700

1/16W MF-LF

C

B

GPU_PCIE_TX_PWR

78 79

GPU_GPIO_TX_DEEMP

78 79

GPU_PCIE_GEN2

78 79

GPU_SMB_DAT

78 79

GPU_SMB_CLK

78 79

GPU_AC_BATT

78 79

EG_BKLT_EN

78 79 87

GPU_ROM_SO

78 79

GPU_ROM_SI

78 79

GPU_ROM_SCLK

78 79

GPU_CONFIG_0

78 79

GPU_CONFIG_1

78 79

NOSTUFF

R8703

1/16W MF-LF

NOSTUFF

R8706

1/16W MF-LF

NOSTUFF

R8709

1/16W MF-LF

GPU_ROM:YES

R8712

1/16W MF-LF

GPU_CONFIG_2

A

78 79

FBVDD_ALTVO

78 79 86

PEX_CLKREQ_L_R

78 79

10K

402

NOSTUFF

1

1%

2

1

1%

2

1

1%

2

1

1%

2

1

1%

2

R8701

10K

1/16W MF-LF

NOSTUFF

R8704

10K

1/16W MF-LF

NOSTUFF

R8707

10K

1/16W MF-LF

R8710

10K

1/16W MF-LF

NOSTUFF

R8713

10K

1/16W MF-LF

402

1

1%

2

1

1%

2

1

1%

2

1

1%

2

1

1%

2

R8702

10K

1/16W MF-LF

NOSTUFF

R8705

10K

1/16W MF-LF

NOSTUFF

R8708

10K

1/16W MF-LF

NOSTUFF

R8711

10K

1/16W MF-LF

NOSTUFF

R8714

10K

1/16W MF-LF

402

1

1%

2

PP3V3_S0GPU

6 7

71 74 78 79 81 83

PAD

1

2

1

2

GPU_ROM:YES

2

GPU_ROM_SO_R

Q

C8721

0.1UF

20% 10V CERM 402

71 74 78 79 81 83

R8792

R8726

33

21

5% 1/16W MF-LF

402

GPU_ROM:YES

PP3V3_S0GPU

6 7

SMC_GFX_OVERTEMP_R_L

78 79

SMC_GFX_THROTTLE_R_L

78 79

1

R8793

10K

1/16W MF-LF

402

5%

10K

5% 1/16W MF-LF

402

2

GPU_ROM:YES

33

5%

402

33

5%

402

33

5%

402

NO STUFF

R8750

2

21

R8720

2.2K

1/16W MF-LF

402

5%

R8723

GPU_ROM_SI

1

1%

2

78 79

GPU_ROM:YES

GPU_ROM_SCLK

78 79

GPU_ROM:YES

GPU_ROM_CS_L

78 79

GPU_ROM:YES

1

1%

2

1

1%

2

78 83

8

17 83

8

1

1%

2

17 83

1

1/16W MF-LF

R8724

1/16W MF-LF

R8725

1/16W MF-LF

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

PP3V3_S0GPU

6 7

71 74 78 79 81 83

DP_EG_DDC_CLK

IN

DP_EG_DDC_DATA

BI

DP_IG_DDC_CLK

IN

DP_IG_DDC_DATA

BI

GPU_ROM:YES

1

R8721

10K

5% 1/16W MF-LF

1/16W MF-LF

402

2

GPU_ROM_SI_R

GPU_ROM_SCLK_R

GPU_ROM_CS_L_R

GPU_ROM_WP_L

NO STUFF

1

R8722

0

5% 1/16W MF-LF 402

2

NO STUFF

1

2

R8751

2.2K

1/16W MF-LF

402

1

5%

2

1

0

5%

402

2

R8752

4.7K

1/16W MF-LF

402

5

D

U8701

6

M25P10A

C

1

S*

3

W*

OMIT_TABLE

7

HOLD*

1

R8753

5%

2

VCC

UFDFPN8

CRITICAL

THRM

VSS

489

4.7K

5% 1/16W MF-LF

402

6 7

71 74 78 79 81 83

GPU_ROM_SO

NO STUFF

R8796

1

R8794

10K

1/16W MF-LF

2

PP3V3_S0GPU

2.2K

5% 1/16W MF-LF

402

1

5%

402

2

8 7 5 4 2 1

T29 HPD GPU isolation

CRITICAL

PP3V3_GPU_VDD33_R

1

R8741

0

5% 1/16W MF-LF 402

2

120OHM-0.3A

78 79

27MHZ-15PPM-18PF

5%

30PF

CERM

1

2

1

5%

50V

2

402

R8798

78 79

1

2

R8797

2.2K

1/16W MF-LF

C8700

402

R8799

PP3V3_S0

74LVC2G08GT

8

SOT833

1

A

7

Y

U8741

2

08

B

4

PP3V3_S0

74LVC2G08GT

8

SOT833

5

A

Y

U8741

6

08

B

4

L8703

21

0402

L8702

21

0402

CRITICAL

Y8700

SM-2.5X2.0MM

31

42

DP_CA_DET_EG_R

PEX_CLKREQ_L_R

0

21

1

C8741

0.1UF

20% 10V

2

CERM 402

DP_T29SNK0_HPD_GPU

3

DP_T29SNK1_HPD_GPU

PP3V3_GPU_OSC_27M

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_GPU_OSC_100M

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

1

C8702

0.1UF

10% 16V

2

X5R 402-1

GPU_OSC_27M_XTALIN GPU_OSC_27M_XTALOUT

1

C8701

30PF

5% 50V

2

CERM 402

R8791

R8795

5% 402

5%

1/16W

MF-LF

MF-LF1/16W

EG_LCD_PWR_EN

EG_BKLT_EN

FBVDD_ALTVO

36

72 79 82 83 84 87 88 89 35 36 39 40 41 45 47 48 6 7

12 16 17 18 19 20 22 23 25 26 28 32 49 50 51 53 56 60 61 71 98

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

1

C8703

0.1UF

10% 16V

2

X5R

402-1

0

SMC_GFX_OVERTEMP_L

SMC_GFX_THROTTLE_L

402

TP_GPU_JTAG_TCK

78 79

MAKE_BASE=TRUE

TP_GPU_JTAG_TDI

MAKE_BASE=TRUE

TP_GPU_JTAG_TDO

78 79

MAKE_BASE=TRUE

TP_GPU_JTAG_TMS

78 79

MAKE_BASE=TRUE

TP_GPU_JTAG_TRST_L

78 79

MAKE_BASE=TRUE

NC_LVDS_EG_B_CLK_P

78 79

MAKE_BASE=TRUE

78 79

NC_LVDS_EG_B_CLK_N

78 79

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_P<3>

78 79 97

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_N<3>

78 79 97

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_P<3>

78 79 97

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_N<3>

78 79 97

MAKE_BASE=TRUE

ISOLATION R’s for GPU Int Temp Sense

78 79

4

VDD1

U8700

SL16010DC

XIN/CLKIN

XOUT

TDFN

1

10

CRITICAL

VSS1

6

21

DP_CA_DET_EG

5%

21

PEX_CLKREQ_L

5%

1/16W MF-LF

OUT

2 1

Unused signals

NO_TEST=TRUE

NOSTUFF

R8780

0

GPU_SMB_DAT

78 79

GPU_SMB_CLK

78 79

GPU Reference Clocks

8

VDD2

VSS2

2

MF-LF1/16W

78 87

78 79 87

78 79 86

SSCLK

REFCLK

SSEL0 SSEL1

PAD

THM

11

OUT

IN

GPU_CLK100M_R

5 9

GPU_CLK27M_R

7 3

87

IN

402

8

87

OUT

402

44

SYNC_MASTER=K92_MLB

PAGE TITLE

Whistler GPIOs & STRAPs

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

21

5% 1/16W MF-LF

402

R8781

0

1 2

5% 1/16W MF-LF

402

NOSTUFF

Apple Inc.

TP_GPU_JTAG_TCK

TP_GPU_JTAG_TDI

TP_GPU_JTAG_TDO

TP_GPU_JTAG_TMS

TP_GPU_JTAG_TRST_L

NC_LVDS_EG_B_CLK_P

NC_LVDS_EG_B_CLK_N

NC_LVDS_EG_A_DATA_P<3>

NC_LVDS_EG_A_DATA_N<3>

NC_LVDS_EG_B_DATA_P<3>

NC_LVDS_EG_B_DATA_N<3>

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

R8730

0

21

GPU_CLK100M

5% 1/16W MF-LF

402

R8731

0

21

GPU_CLK27M

5% 1/16W MF-LF

402

SYNC_DATE=11/23/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

6

31 44 47

50 96

6 50 96

78 97

OUT

78 97

OUT

87 OF 132

79 OF 101

78 79

78 79 78 79

78 79

31 44 47

SIZE

D

97

D

78 79

97 78 79

C

B

A

345678

2 1

Page Notes

PP1V8_GPU_DP_CD

80

PP1V0_GPU_DP_CD

80

D

R8802

150

1 2

1% 1/16W MF-LF

402

PP1V8_GPU_DP_CD

80

PP1V0_GPU_DP_CD

80

GPU_DP_CD_CALR

PP1V8_GPU_DP_EF

80

PP1V0_GPU_DP_EF

80

PP1V8_GPU_DP_EF

80

PP1V0_GPU_DP_EF

80

C

R8801

150

1 2

1% 1/16W MF-LF

402

L8800

PP1V8_S0GPU_ISNS

7

74 78

80

100

B

PP1V8_S0GPU_ISNS

7

74 78

80

100

PP1V8_S0GPU_ISNS PP1V0_S0GPU_ISNS

7

74 78

80

100

470OHM-1A-150MOHM

1 2

0603

L8804

470OHM-1A-150MOHM

1 2

0603

L8802

470OHM-1A-150MOHM

1 2

0603

GPU_DP_EF_CALR

1

C8800

10UF

20% 10V

2

X5R 603

1

C8812

10UF

20% 10V

2

X5R 603

1

C8806

10UF

20% 10V

2

X5R 603

1

2

1

2

1

2

C8801

1UF

10% 25V X5R 402

C8813

1UF

10% 25V X5R 402

C8807

1UF

10% 25V X5R 402

AP20

DPCD/DPC_VDD18_AP20

AP21

DPCD/DPC_VDD18_AP21

AP13

DPCD/DPC_VDD10_AP13

AT13

DPCD/DPC_VDD10_AT13

AN17

DP/DPC_VSSR_AN17

AP16

DP/DPC_VSSR_AP16

AP17

DP/DPC_VSSR_AP17

AW14

DP/DPC_VSSR_AW14

AW16

DP/DPC_VSSR_AW16

AP22

DPCD/DPD_VDD18_AP22

AP23

DPCD/DPD_VDD18_AP23

AP14

DPCD/DPD_VDD10_AP14

AP15

DPCD/DPD_VDD10_AP15

AN19

DP/DPD_VSSR_AN19

AP18

DP/DPD_VSSR_AP18

AP19

DP/DPD_VSSR_AP19

AW20

DP/DPD_VSSR_AW20

AW22

DP/DPD_VSSR_AW22

AW18

DPCD_CALR

AH34

DPEF/DPE_VDD18_AH34

AJ34

DPEF/DPE_VDD18_AJ34

AL33

DPEF/DPE_VDD10_AL33

AM33

DPEF/DPE_VDD10_AM33

AN34

DP/DPE_VSSR_AN34

AP39

DP/DPE_VSSR_AP39

AR39

DP/DPE_VSSR_AR39

AU37

DP/DPE_VSSR_AU37

AF34

DPEF/DPF_VDD18_AF34

AG34

DPEF/DPF_VDD18_AG34

AK33

DPEF/DPF_VDD10_AK33

AK34

DPEF/DPF_VDD10_AK34

AF39

DP/DPF_VSSR_AF39

AH39

DP/DPF_VSSR_AH39

AK39

DP/DPF_VSSR_AK39

AL34

DP/DPF_VSSR_AL34

AM34

DP/DPF_VSSR_AM34

AM39

DPEF_CALR

300mA

PP1V8_GPU_DP_AB

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8802

0.1UF

10% 16V

2

X5R 402-1

300mA

PP1V8_GPU_DP_CD

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8814

0.1UF

10% 16V

2

X5R 402-1

300mA

PP1V8_GPU_DP_EF

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

1

C8808

0.1UF

10% 16V

2

X5R 402-1

DPAB/DPA_VDD18_AN24 DPAB/DPA_VDD18_AP24

DPAB/DPA_VDD10_AP31 DPAB/DPA_VDD10_AP32

DP/DPA_VSSR_AN27 DP/DPA_VSSR_AP27 DP/DPA_VSSR_AP28 DP/DPA_VSSR_AW24 DP/DPA_VSSR_AW26

DPAB/DPB_VDD18_AP25 DPAB/DPB_VDD18_AP26

DPAB/DPB_VDD10_AN33 DPAB/DPB_VDD10_AP33

DP/DPB_VSSR_AN29 DP/DPB_VSSR_AP29 DP/DPB_VSSR_AP30 DP/DPB_VSSR_AW30 DP/DPB_VSSR_AW32

DPAB_VDD18/DPA_PVDD_AU28

DP_VSSR/DPA_PVSS_AV27

DPAB_VDD18/DPB_PVDD_AV29

DP_VSSR/DPB_PVSS_AR28

DPCD_VDD18/DPC_PVDD_AU18

DP_VSSR/DPC_PVSS_AV17

DPCD_VDD18/DPD_PVDD_AV19

DP_VSSR/DPD_PVSS_AR18

DPEF_VDD18/DPE_PVDD_AM37

DP_VSSR/DPE_PVSS_AN38

DPEF_VDD18/DPF_PVDD_AL38

DP_VSSR/DPF_PVSS_AM35

PP1V0_S0GPU_ISNS

7

PP1V0_S0GPU_ISNS

7

DPAB_CALR

470OHM-1A-150MOHM

WHISTLER (6 OF 9)

40NM-ES

100

80

100

80

U8000

FCBGA

OMIT

DP C/D PWR

DP A/B PWR

DP E/F PWR

DP OLL POWER

73 74 78 80

470OHM-1A-150MOHM

80 80

100

7

73 74 78 80

PP1V8_GPU_DP_AB

AN24 AP24

PP1V0_GPU_DP_AB

AP31 AP32

AN27 AP27 AP28 AW24 AW26

PP1V8_GPU_DP_AB

AP25 AP26

PP1V0_GPU_DP_AB

AN33 AP33

AN29 AP29 AP30 AW30 AW32

GPU_DP_AB_CALR

AW28

PP1V8_GPU_DP_AB

AU28 AV27

PP1V8_GPU_DP_AB

AV29 AR28

PP1V8_GPU_DP_CD

AU18 AV17

PP1V8_GPU_DP_CD

AV19 AR18

PP1V8_GPU_DP_EF

AM37 AN38

PP1V8_GPU_DP_EF

AL38 AM35

L8801

1 2

0603

L8805

1 2

0603

L8803

1 2

0603

1

C8803

10UF

20% 10V

2

X5R 603

1

C8815

10UF

20% 10V

2

X5R 603

1

C8809

10UF

20% 10V

2

X5R 603

80

1

C8804

1UF

10% 25V

2

X5R 402

1

C8816

1UF

10% 25V

2

X5R 402

1

C8810

1UF

10% 25V

2

X5R 402

R8800

150

1 2

1% 1/16W MF-LF

402

220mA

PP1V0_GPU_DP_AB

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1V

1

C8805

0.1UF

10% 16V

2

X5R 402-1

220mA

PP1V0_GPU_DP_CD

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1V

1

C8817

0.1UF

10% 16V

2

X5R 402-1

220mA

PP1V0_GPU_DP_EF

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1V

1

C8811

0.1UF

10% 16V

2

X5R 402-1

AB39

PCIE_VSS_AB39

E39

PCIE_VSS_E39

F34

PCIE_VSS_F34

F39

PCIE_VSS_F39

G33

PCIE_VSS_G33

G34

PCIE_VSS_G34

H31

PCIE_VSS_H31

H34

PCIE_VSS_H34

H39

PCIE_VSS_H39

J31

PCIE_VSS_J31

J34

PCIE_VSS_J34

K31

PCIE_VSS_K31

K34

PCIE_VSS_K34

K39

PCIE_VSS_K39

L31

PCIE_VSS_L31

L34

PCIE_VSS_L34

M34

PCIE_VSS_M34

M39

PCIE_VSS_M39

N31

PCIE_VSS_N31

N34

PCIE_VSS_N34

P31

PCIE_VSS_P31

P34

PCIE_VSS_P34

P39

PCIE_VSS_P39

R34

PCIE_VSS_R34

T31

PCIE_VSS_T31

T34

PCIE_VSS_T34

T39

PCIE_VSS_T39

U31

PCIE_VSS_U31

U34

PCIE_VSS_U34

V34

PCIE_VSS_V34

V39

PCIE_VSS_V39

W31

PCIE_VSS_W31

W34

PCIE_VSS_W34

Y34

PCIE_VSS_Y34

Y39

PCIE_VSS_Y39

A39

VSS_MECH_A39

AW1

VSS_MECH_AW1

AW39

80

VSS_MECH_AW39

U8000

FCBGA

(8 OF 9)

40NM-ES

WHISTLER

OMIT

GND_A3 GND_A37 GND_AA2 GND_AA6

GND_AA16 GND_AA18 GND_AA21 GND_AA23 GND_AA26 GND_AA28 GND_AB12 GND_AB15 GND_AB17 GND_AB20 GND_AB22 GND_AB24 GND_AB27

GND_AC2 GND_AC6

GND_AC11 GND_AC13 GND_AC16 GND_AC18 GND_AC21 GND_AC23 GND_AC26 GND_AC28

GND_AD9

GND_AD15 GND_AD17 GND_AD20 GND_AD22 GND_AD24 GND_AD27

GND_AE2 GND_AE6

GND_AF10 GND_AF16 GND_AF18

A3 A37 AA2 AA6 AA16 AA18 AA21 AA23 AA26 AA28 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC2 AC6 AC11 AC13 AC16 AC18 AC21 AC23 AC26 AC28 AD9 AD15 AD17 AD20 AD22 AD24 AD27 AE2 AE6 AF10 AF16 AF18

Power aliases required by this page:

- =PP1V8_GPU_DP_AB

- =PP1V8_GPU_DP_CD

- =PP1V8_GPU_DP_EF

- =PP1V0_GPU_DP_AB

- =PP1V0_GPU_DP_CD

- =PP1V0_GPU_DP_EF

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

(NONE)

AF21

AG17 AG20 AG22 AH21

AJ10 AJ11 AJ28

AK11 AK31

AL11 AL14 AL17 AL20 AL23 AL26 AL32

AM11 AM31

AN11 AN30

AP11

AG2 AG6 AG9

AJ2 AJ6

AK7

AL2 AL6 AL8

AM9

AN2 AN6 AN8

AP7 AP9

AR5

B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33

C39

E35

F11 F13 F15 F17 F19 F21 F23 F25 F27 F29

B7 B9

C1

E5

F7 F9

GND_AF21 GND_AG2 GND_AG6 GND_AG9 GND_AG17 GND_AG20 GND_AG22 GND_AH21 GND_AJ2 GND_AJ6 GND_AJ10 GND_AJ11 GND_AJ28 GND_AK7 GND_AK11 GND_AK31 GND_AL2 GND_AL6 GND_AL8 GND_AL11 GND_AL14 GND_AL17 GND_AL20 GND_AL23 GND_AL26 GND_AL32 GND_AM9 GND_AM11 GND_AM31 GND_AN2 GND_AN6 GND_AN8 GND_AN11 GND_AN30 GND_AP7 GND_AP9 GND_AP11 GND_AR5 GND_B7 GND_B9 GND_B11 GND_B13 GND_B15 GND_B17 GND_B19 GND_B21 GND_B23 GND_B25 GND_B27 GND_B29 GND_B31 GND_B33 GND_C1 GND_C39 GND_E5 GND_E35 GND_F7 GND_F9 GND_F11 GND_F13 GND_F15 GND_F17 GND_F19 GND_F21 GND_F23 GND_F25 GND_F27 GND_F29

U8000

FCBGA

(9 OF 9)

OMIT

40NM-ES

WHISTLER

GND_F31 GND_F33

GND_G2 GND_G6 GND_H9 GND_J2 GND_J6 GND_J8

GND_J27

GND_K7

GND_K14

GND_L2

GND_L6 GND_L11 GND_L17 GND_L22 GND_L24 GND_M17 GND_M22 GND_M24

GND_N2

GND_N6 GND_N16 GND_N18 GND_N21 GND_N23 GND_N26

GND_R2

GND_R6 GND_R15 GND_R17 GND_R20 GND_R22 GND_R24 GND_R27 GND_T11 GND_T13 GND_T16 GND_T18 GND_T21 GND_T23 GND_T26

GND_U2

GND_U6

NC/GND GND_U15 GND_U17 GND_U20 GND_U22 GND_U24 GND_U27 GND_V11

NC/GND GND_V16 GND_V18 GND_V21 GND_V23 GND_V26

GND_W2

GND_W6 GND_Y15 GND_Y17 GND_Y20 GND_Y22 GND_Y24 GND_Y27

GND/PX_EN

F31 F33 G2 G6 H9 J2 J6 J8 J27 K7 K14 L2 L6 L11 L17 L22 L24 M17 M22 M24 N2 N6 N16 N18 N21 N23 N26 R2 R6 R15 R17 R20 R22 R24 R27 T11 T13 T16 T18 T21 T23 T26 U2 U6 U13 U15 U17 U20 U22 U24 U27 V11 V13 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 AL21

D

C

B

NC

A

PAGE TITLE

Whistler DP PWR/GNDs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=06/15/2010SYNC_MASTER=K92_SUMA

DRAWING NUMBER

REVISION

BRANCH

PAGE

88 OF 132

SHEET

80 OF 101

SIZE

A

D

345678

2 1

100 43 45 65

PP5V_S3

6 7

29

31 41 42 66 71

D

83

PP3V3_S0GPU

6 7

71 74 78

79 81

PPVCORE_GPU

6 7

48 74 81

C

GPU_VDD_SENSE

74

MIN_NECK_WIDTH=0.10 mm MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.25V

GPU_GND_SENSE

74

MIN_NECK_WIDTH=0.10 mm MIN_LINE_WIDTH=0.25 mm VOLTAGE=0V

R8925

100

1/16W MF-LF

402

12

1%

PLACE_NEAR=U8900.8:7mm

PLACE_NEAR=U8900.9:7mm

B

GPU_VCORE_VID0

78 79

IN

GPU_VCORE_VID1

78 79

A

IN

GPU_VCORE_VID2

78 79

IN

GPU_VCORE_VID3

78 79

IN

R8911

1

1 2

5% 1/16W MF-LF

402

R8904

10

1 2

1% 1/16W MF-LF

402

R8907

1

R8924

100

1% 1/16W MF-LF

402

2

R8920

20

1 2

5% 1/16W MF-LF

R8908

1 2

1/16W MF-LF

GFXIMVP6_COMP_RC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

1

R8950

150K

1% 1/16W MF-LF 402

2

71 74 78 79 81 83

R8990

1 2

R8993

R8994

1 2

R8998

1 2

1

C8920

402

20

5%

402

1

R8951

150

2

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

0.001UF

10% 50V

2

CERM 402

1% 1/16W MF-LF 402

GFXIMVP6_VDIFF_RC

PP3V3_S0GPU

6 7

0

5% 1/16W MF-LF

402

0

21

5% 1/16W MF-LF

402

0

5% 1/16W MF-LF

402

0

5% 1/16W MF-LF

402

PP5V_S3_GFXIMVP6_PVCC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

PP5V_S3_GFXIMVP6_VDD

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

1

C8901

1uF

10% 10V

2

X5R 402

R8905

150K

2 1

10K

1/16W MF-LF

402

1

5%

2

C8950

330PF

10% 50V

CERM

402

C8951

0.0068UF

1

R8910

10K

5% 1/16W MF-LF 402

2

R8909

7.15K

12

1 2

10% 25V

CERM

402

GPUVID0_1

R8987

2.2K

1/16W MF-LF

402

GPUVID0_0

1%

1/16W

C8904

MF-LF

402

0.033UF

48

OUT

8

73 86 87 89

OUT

87 89

IN

GFXIMVP6_VSEN_P

1

1% 1/16W MF-LF

402

2

1

C8952

330PF

10% 50V

2

CERM 402

1

R8953

3.01K

1% 1/16W MF-LF 402

2

GPUVID1_1

1

5%

2

R8988

2.2K

5% 1/16W MF-LF

402

GFXIMVP6_RBIAS

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

12

GFXIMVP6_SOFT

MIN_LINE_WIDTH=0.3MM

10% 16V X5R 402

81

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_IMON

PM_ALL_GPU_PGOOD GFXIMVP6_VID0 GFXIMVP6_VID1 GFXIMVP6_VID2 GFXIMVP6_VID3 GFXIMVP6_VID4 GPUVCORE_EN GFXIMVP6_AF_EN GFXIMVP6_FDE

GFXIMVP6_VSEN_N

1

C8923

0.001UF

10% 50V

2

CERM 402

(GFXIMVP6_AGND)

GFXIMVP6_VW

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

1

C8922

0.001UF

10% 50V

2

X7R 402

GFXIMVP6_COMP

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_FB

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VDIFF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

R8984

2.2K

1/16W MF-LF

GPUVID1_0

1

2

1

5%

402

2

R8985

0.001UF

GPUVID2_1

R8982

1

2.2K

5% 1/16W MF-LF

402

2

C8921

8 7 5 4 2 1

GPU VCore Regulator

1

2

1

RBIAS

2

SOFT

28

IMON

31

PGOOD

23

VID0

24

VID1

25

VID2

26

VID3

27

VID4

29

VR_ON

30

AF_EN

32

FDE

8

VSEN

9

RTN

4

VW

5

COMP

6

FB

7

VDIFF

PGND

20

GPUVID3_1

R8995

2.2K

1/16W MF-LF

GPUVID3_0

1

5%

402

2

1

C8903

0.01uF

10% 16V

2

CERM 402

22

16

PVCC

VDD

CRITICAL

U8900

QFN

ISL6263C

THRM_PAD

VSS

15

XW8900

SM

1 2

PLACE_NEAR=U8900.33:2mm PLACE_NEAR=U8900.15:2mm

GPUVID4_1

1

R8991

5%

402

2

1

R8996

2.2K

5% 1/16W MF-LF

402

2

14

VIN

18

UGATE

17

BOOT

19

PHASE

21

LGATE

12

VO

3

OCSET

13

ISP

11

ISN

10

ICOMP

33

353S2289

1

2.2K

5% 1/16W MF-LF

402

2

GPUVID4_0

R8992

C8902

2.2UF

20% 10V

X5R-CERM

402

1

10% 50V

2

CERM

402

1

2.2K

5% 1/16W MF-LF

402

2

GPUVID2_0

R8983

2.2K

1/16W MF-LF

CRITICAL

C8930

POLY-TANT

GFXIMVP6_VIN

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_UGATE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

GATE_NODE=TRUE

GFXIMVP6_BOOT

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

GFXIMVP6_PHASE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

SWITCH_NODE=TRUE

DIDT=TRUE

GFXIMVP6_LGATE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

GATE_NODE=TRUE

DIDT=TRUE

1

C8953

680pF

10% 50V

2

CERM 402

GFXIMVP6_VO

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM

GFXIMVP6_OCSET

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSUM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM

GFXIMVP6_DFB

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DROOP

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GND_GFXIMVP6_AGND

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

1

2.2K

5% 1/16W MF-LF

402

2

1

68UF

20% 16V

2

D3L

DIDT=TRUE

R8902

9.76K

GFXIMVP6_VID0 GFXIMVP6_VID1 GFXIMVP6_VID2 GFXIMVP6_VID3 GFXIMVP6_VID4

PPVIN_S5_HS_GPU_ISNS

7

49 86

1

C8932

1UF

10%

C8933

25V

2

X5R 603-1

603-1

C8956

0.22UF

R8900

7.32K

1 2

1% 1/16W MF-LF

402

2

1% 1/16W MF-LF

C8971

402

1

68PF

1 2

5%

50V

CERM

402-1

1

1UF

10% 25V

2

X5R

1

10% 16V

2

X7R 603

1

R8901

9.09K

1% 1/16W MF-LF 402

2

C8972

0.001UF

CERM

81

R8930

10% 50V

402

1

C8934

2

1/16W MF-LF

1

2

0.001UF

10% 50V X7R 402

1

1K

5%

402

2

R8903

C8906

330PF

CRITICAL

1

C8931

68UF

20% 16V

2

POLY-TANT CASE-D2E-SM

5

CRITICAL

D

1 23

G

S

5

D

S

1 23

Q8950

RJK0365DPA-02

WPAK

CRITICAL

L8920

0.56UH-31A

1 2

FDU1040D-SM

CRITICAL

Q8951

RJK0208DPA

WPAK

PPVCORE_GPU_REG_R

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V

CRITICAL

R8940

0.001

1%

1W MF-1 0612

12 34

C8969

0.001UF

G

4

GFXIMVP6_PHASE_VSUM

1

1K

1% 1/16W MF-LF

402

2

1

5%

50V

2

COG 402

(PPVCORE_GPU_REG)

K91F Default Vcore Setpoints

BOM GROUP

GPUVID_1P11V

VIMON = 31 x Io x Rsns x (1 + Ris2/Ris1) In K9x, the equation will be:

VIMON = 31 x Io x R8940 x (1+ R8902/R8901) VIMON = 31x Io x 1mOhm x 2.074 = Io x 64.29 mV/A

36

Vout = 0.75V - 0.90V

10% 50V X7R 402

1

2

PPVCORE_GPU

CRITICAL

C8942

330UF

POLY-TANT

D2T-SM2

CRITICAL

1

C8943

330UF

20%

2.0V

2

3

POLY-TANT D2T-SM2

20%

2.0V

1

2 3

CRITICAL

1

2

C8966

10UF

20%

6.3V X5R 603

CRITICAL

1

C8965

10UF

20%

6.3V

2

X5R 603

CRITICAL

C8968

1

2

10UF

1

C8967

4.7UF

10%

6.3V

2

X5R-CERM 603

20%

6.3V X5R 603

6 7

48 74 81

30A max output (L8920 limit)

GPU VCore Setpoints

VID1 VID0VID3VID4

VID2

1

0

10 1

01

1 -

Voltage

0.74675V

1

0001

0.82400V

11

0.90125V

Max Batt

K18

-

K18

-

GPU VCore Setpoints not up-to-date!

BOM OPTIONS

GPUVID4_0,GPUVID3_0,GPUVID2_1,GPUVID1_1,GPUVID0_1

PAGE TITLE

GPU (Whistler) CORE SUPPLY

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

R

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

SYNC_DATE=12/21/2010SYNC_MASTER=K91_ERIC

DRAWING NUMBER

REVISION

BRANCH

PAGE

89 OF 132

SHEET

81 OF 101

D

C

Max perfBalanced

-

K18

B

A

SIZE

D

345678

2 1

D

C

B

87

17 19 20 22 23 24 25 29

LCD_PWR_EN

IN

PP3V3_S5

6 7 39 45 55 65 70 71 72 85 89 98

R9094

10K

1/16W MF-LF

402

1

5%

2

CRITICAL

U9000

FPF1009

MFET-2X2

ON

1

C9009

0.1UF

10% 16V

2

X5R 402-1

2

3

VIN_1

VIN_2

GND 617

VOUT_1

VOUT_2

THRM

PAD

4

5

LCD (LVDS) INTERFACE

1

2

100K pull-ups are for

no-panel case (development).

Panel has 2K pull-ups

LVDS_CONN_A_CLK_N

83 97

LVDS_CONN_A_CLK_P

83 97

LVDS_CONN_B_CLK_N

83 97

LVDS_CONN_B_CLK_P

83 97

C9011

0.1UF

10% 16V X5R 402-1

Place close to the connector

1

C9012

10UF

20%

6.3V

2

X5R 603

47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 83 84 87 88 89 98

LVDS_DDC_CLK

6

83

LVDS_DDC_DATA

6

83

CRITICAL

L9010

90-OHM-100MA

DLP11S

SYM_VER-1

1 2

CRITICAL

L9011

90-OHM-100MA

DLP11S

SYM_VER-1

1 2

CRITICAL

L9000

FERR-250-OHM

10% 16V X5R

1

2

1

2

1 2

C9002

0.001UF

LED_RETURN_6

6

88

LED_RETURN_5

6

88

LED_RETURN_4

6

88

LED_RETURN_3

6

88

LED_RETURN_2

6

88

LED_RETURN_1

6

88

PPVOUT_S0_LCDBKLT

6 8

88

100

SM

1

10% 50V

2

X7R 402

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

LVDS_CONN_A_DATA_N<0>

6

83 97

LVDS_CONN_A_DATA_P<0>

6

83 97

LVDS_CONN_A_DATA_N<1>

6

83 97

LVDS_CONN_A_DATA_P<1>

6

83 97

LVDS_CONN_A_DATA_N<2>

6

83 97

LVDS_CONN_A_DATA_P<2>

6

83 97

LVDS_CONN_A_CLK_F_N

6

97

LVDS_CONN_A_CLK_F_P

6

97

LVDS_CONN_B_DATA_N<0>

6

83 97

LVDS_CONN_B_DATA_P<0>

6

83 97

LVDS_CONN_B_DATA_N<1>

6

83 97

LVDS_CONN_B_DATA_P<1>

6

83 97

LVDS_CONN_B_DATA_N<2>

6

83 97

LVDS_CONN_B_DATA_P<2>

6

83 97

LVDS_CONN_B_CLK_F_N

6

97

LVDS_CONN_B_CLK_F_P

6

97

PP3V3_SW_LCD

6

NC

C9000

0.001UF

10% 50V

CERM

402

1

2

CRITICAL

J9000

20474-040E-11

F-RT-SM 41

42

1 2 3 4 5

NC

6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

43 44

518S0651

PP3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

C9001

0.1UF

402-1

1

402

R9011

100K

5%

1/16W MF-LF 402

2

C9010

0.001UF

10% 50V X7R 402

R9010

100K

1/16W MF-LF

34

D

C

B

A

SYNC_MASTER=K18_MLB

PAGE TITLE

LVDS Display Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

90 OF 132

SHEET

82 OF 101

SIZE

A

D

345678

2 1

LVDS Transmitter Termination

All emulated LVDS outputs require this termination

D

LVDS_A_CLK_P

87 97

IN

LVDS_A_CLK_N

87 97

IN

LVDS_A_DATA_P<0>

87 97

IN

PLACE_NEAR=U9600.B9:7mm

LVDS_A_DATA_N<0>

87 97

IN

LVDS_A_DATA_P<1>

87 97

IN

PLACE_NEAR=U9600.A9:7mm

C

PLACE_NEAR=U9600.C10:7mm

LVDS_A_DATA_N<1>

87 97

IN

LVDS_A_DATA_P<2>

87 97

IN

PLACE_NEAR=U9600.B10:7mm

PLACE_NEAR=U9600.A10:7mm

LVDS_A_DATA_N<2>

87 97

IN

LVDS_B_CLK_P

87 97

IN

PLACE_NEAR=U9600.C8:7mm

PLACE_NEAR=U9600.C9:7mm

LVDS_B_CLK_N

87 97

IN

LVDS_B_DATA_P<0>

87 97

B

IN

PLACE_NEAR=U9600.A2:7mm

PLACE_NEAR=U9600.A3:7mm

LVDS_B_DATA_N<0>

87 97

IN

LVDS_B_DATA_P<1>

87 97

IN

PLACE_NEAR=U9600.A1:7mm

PLACE_NEAR=U9600.B3:7mm

LVDS_B_DATA_N<1>

87 97

IN

LVDS_B_DATA_P<2>

87 97

IN

PLACE_NEAR=U9600.C5:7mm

LVDS_B_DATA_N<2>

87 97

A

IN

PLACE_NEAR=U9600.A5:7mm

8 7 5 4 2 1

PLACE_NEAR=U9600.A6:7mm

R9220

357

1%

1/20W

MF

201

PLACE_NEAR=U9600.A7:7mm

R9222

357

1%

1/20W

MF

201

PLACE_NEAR=U9600.A8:7mm

R9230

357

1%

1/20W

MF

201

R9232

357

1%

1/20W

MF

201

R9240

357

1%

1/20W

MF

201

R9242

357

1%

1/20W

MF

201

R9250

357

1%

1/20W

MF

201

R9252

357

1%

1/20W

MF

201

21

R9225

357

1%

1/20W

MF

201

R9227

357

1%

1/20W

MF

201

R9235

357

1

1%

1/20W

MF

201

R9237

357

1%

1/20W

MF

201

R9245

357

1

1%

1/20W

MF

201

R9247

357

1%

1/20W

MF

201

R9255

357

1%

1/20W

MF

201

R9257

357

1%

1/20W

MF

201

LVDS_CONN_A_CLK_P

LVDS_CONN_A_CLK_N

21

LVDS_CONN_A_DATA_P<0>

21

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_A_DATA_P<1>

LVDS_CONN_A_DATA_N<1>

2

LVDS_CONN_A_DATA_P<2>

21

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_B_CLK_P

LVDS_CONN_B_CLK_N

2

LVDS_CONN_B_DATA_P<0>

21

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<1>

21

LVDS_CONN_B_DATA_P<2>

21

LVDS_CONN_B_DATA_N<2>

82 97

OUT

82 97

OUT

6

82 97

OUT

6

82 97

OUT

6

OUT

6

OUT

6

OUT

6

OUT

82 97

OUT

82 97

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

6

OUT

17

82 97

DP AUX, DDC, & HPD muxing to IG/EG

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

1

R9202

10K

5% 1/16W MF-LF

402

8

78 79

OUT

R9204

100K

1/16W MF-LF

2

DP_IG_AUX_CH_P

8

17 92

BI

DP_IG_AUX_CH_N

8

17 92

BI

DP_EG_AUXCH_P

8

78 97

BI

DP_EG_AUXCH_N

8

78 97

BI

DP_IG_DDC_CLK

8

17 79

IN

DP_IG_DDC_DATA

8

17 79

BI

DP_EG_DDC_CLK

78 79

IN

DP_EG_DDC_DATA

78 79

BI

DP_IG_HPD

DP_EG_HPD

DP_MUX_SEL_EG

87

R9205

100K

1/16W MF-LF

1

5%

402

2

1

5%

402

2

87

IN

DP_MUX_EN

17

14 13

12 11

10

15

9 8

7

5

DAUX1+ DAUX1-

DAUX2+ DAUX2-

DDC_CLK1 DDC_DAT1

DDC_CLK2 DDC_DAT2

HPD_1

HPD_2

GPU_SEL

XSD*

6

18

VDD

U9220

CBTL03062

BGA

CRITICAL

GND

19

AUX+ AUX-

DDC_CLK DDC_DAT

HPDIN

84

LVDS DDC MUX

PP3V3_S0GPU

6 7

71 74 78 79 81

1

47 48 49 50 51 53 56 60 61 71 6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

LVDS_DDC_SEL_EG

87

IN

LVDS_DDC_SEL_IG

87

IN

PP3V3_S0

C9270

0.1UF

CERM

R9270

20K

1/16W MF-LF

1

R9273

20K

5%

1/16W MF-LF 402

402

2

VCC

U9270

QFN1

C1

C2

C3

C4

GND

7

R9272

20K

14

1/16W MF-LF

1

A1

2

B1

4

A2

3

B2

8

A3

9

B3

SN74LV4066A

11

A4

10

B4

THRM

CRITICAL

15

1

20% 10V

2

402

13

5

6

12

R9271

20K

5%

1/16W MF-LF 402

402

2

LVDS_EG_DDC_CLK

LVDS_IG_DDC_CLK LVDS_DDC_CLK

LVDS_EG_DDC_DATA

LVDS_IG_DDC_DATA LVDS_DDC_DATA

1

C9220

0.1UF

20% 10V

2

CERM 402

2016

DP_EXTA_AUXCH_C_P

1

DP_EXTA_AUXCH_C_N

2

DP_EXTA_DDC_CLK

3

DP_EXTA_DDC_DATA

(DP_EXTA_HPD)

4

IN

1

C9230

0.1UF

20% 10V

2

CERM 402

DP_EXTA_HPD

DP_T29SNK0_HPD

33 79

DP_T29SNK1_HPD

33 79

(DP_EXTA_HPD)

DP_A_EXT_HPD

45 84

IN

84 97

BI

84 97

BI

84

OUT

84

BI

T29/DP HOT PLUG IN

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

CRITICAL

T29_DP_HPD:MCU_GMUX

78

IN

18

IN

6

82

OUT

78

BI

18

BI

6

82

BI

36

T29_DP_HPD:MUX_GMUX

T29_DP_HPD:ALL_OR

8

74LVC2G32GT

5

SOT833

A

Y

U9210

6

B

4

Q9280

SSM3K15FV

SOD-VESM-HF

1

GS

D

3

2

R9206

0

12

5% 1/16W MF-LF

402

T29_DP_HPD:ALL_OR

3

T29_HOTPLUG_DET_OR

C9210

PP3V3_S0

T29_DP_HPD:MCU_GMUX

1

R9281

100K

5% 1/16W MF-LF 402

2

1

0.1UF

20% 10V

2

CERM

402

T29_DP_HPD:ALL_OR

8

74LVC2G32GT

1

SOT833

A

U9210

2

B

4

83 84 87 88 89 98 40 41 45 47 48 49 50 51 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 53 56 60 61 71 72 79 82

SYNC_MASTER=K92_MLB

PAGE TITLE

7

Y

DP_HOTPLUG_DET

Muxed Graphics Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

87

OUT

SYNC_DATE=11/21/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

92 OF 132

SHEET

83 OF 101

SIZE

D

C

B

A

D

1% 1/16W MF-LF 402

1

83

21

10% X5R 402

21

10% X5R 402

21

10% X5R

21

10% 16V

21

10% X5R 402

21

X5R

21

10% X5R 402

21

10% X5R 402

21

10% X5R

2

X5R

C9310

2.2UF

6.3V CERM

402-LF

84

IN

BI

84

OUT

16V

16V 402

402X5R

16V

16V10% 402

16V

16V 402

16V10% 402

DP_EXTA_ML_P<0>

DP_EXTA_ML_N<0>

DP_EXTA_ML_P<1>

DP_EXTA_ML_N<1>

DP_EXTA_ML_P<2>

DP_EXTA_ML_N<2>

DP_EXTA_ML_P<3>

DP_EXTA_ML_N<3>

R9309

DP_EXTA_AUXCH_P

DP_EXTA_AUXCH_N

R9308

1

C9311

0.1UF

20%

DP_EXTA_ML_P<0> DP_EXTA_ML_N<0>

DP_EXTA_ML_P<1> DP_EXTA_ML_N<1>

DP_EXTA_ML_P<2> DP_EXTA_ML_N<2>

DP_EXTA_ML_P<3> DP_EXTA_ML_N<3>

DP_EXTA_DDC_CLK DP_EXTA_DDC_DATA

DP_EXTA_AUXCH_P DP_EXTA_AUXCH_N

DP_EXTA_HPD

20% 10V

2

CERM 402

DPSDRVA_I2C_CTL_EN

DPSDRVA_I2C_ADDR0 DPSDRVA_I2C_ADDR1

I2C_DPSDRVA_SCL

47

IN

I2C_DPSDRVA_SDA

47

BI

DPSDRVA_REXT

DP_AUXCH_ISOL

16 23

IN

DP_A_PWRDWN_R

PS8301 has internal ~150K pull-down on PD pin. Okay to drive this pin even when VCC=0V per Parade (pin is 5V-tolerant).

DP_A_CA_DET

84 87

T29_LSEO<0>

33

IN

I2C_T29_SCL

33 47 95

IN

I2C_T29_SDA

33 47 95

BI

T29DPA_HPD

85

IN

T29_A_BIAS

84 85

OUT

T29_LSOE<0>

33

OUT

T29_LSOE<1>

33

OUT

T29_MCU_INT_L

18

OUT

DP A Super-Driver

DP_EXTA_ML_C_P<0>

78 97

IN

DP_EXTA_ML_C_N<0>

78 97

IN

DP_EXTA_ML_C_P<1>

78 97

IN

DP_EXTA_ML_C_N<1>

78 97

IN

DP_EXTA_ML_C_P<2>

78 97

D

IN

DP_EXTA_ML_C_N<2>

78 97

IN

DP_EXTA_ML_C_P<3>

78 97

IN

DP_EXTA_ML_C_N<3>

78 97

IN

DP_EXTA_AUXCH_C_P

83 97

BI

DP_EXTA_AUXCH_C_N

83 97

BI

If GPU uses common pins for AUX_CH and DDC, alias nets together at GPU.

82 83 84 87 51 53 56 60 39 40 41 45 22 23 25 26

PP3V3_S0

6 7

12 16

17 18 19 20 28 32 35 36 47 48 49 50 61 71 72 79 88 89 98

C9300

0.1uF

C9301

0.1uF

C9302

0.1uF

C9303

0.1uF

C9304

0.1uF

C9305

0.1uF

C9306

0.1uF

C9307

0.1uF

C9308

0.1uF

C9309

0.1uF

PS8301 I2C Addresses:

C

A1 A0 Addr (W/R) 0 0 0x96/0x97 0 1 0xB6/0xB7 1 0 0x94/0x95 1 1 0xB4/0xB5

Note: Other Parade devices use 96/B6, so only 94/B4 are used for this part.

NO STUFF

1

R9312

1K

5% 1/16W MF-LF 402

2

R9311

1/16W MF-LF

1

R9310

1K

5%

5% 1/16W MF-LF

402

2

B

SDRV_PD

R9318

1/16W MF-LF

DP_A_PWRDWN

84

=T29_WAKE_L:

A

use PCIe WAKE#

PCIE_WAKE_L

6

17 25 31

OUT

OMIT

R9330

1/16W MF-LF

T29_A_UC_ADDR R9330 provides pads for programming/debug of MCU, please make accessible. If project has space for 10-pin programming header it should be used.

84

1

2

R9319

4.99K

0

5%

402

2

1

SWCLK

0

5%

402

2

SWDIO

8 7 5 4 2 1

345678

T29_A_BIAS_R2D_P0

8

(C9372.2)

(C9373.2)

8

(C9383.2)

8

IN

1

R9393

2

R9338

R9334

10K

5% 1/16W MF-LF

402

IN

C9370

0.47UF

C9371

0.47UF

GND_VOID=TRUE

C9372

0.47UF

C9373

0.47UF

GND_VOID=TRUE

T29_A_BIAS_R2D_N0

IN

T29_A_BIAS_R2D_P1

IN

C9380

0.47UF

C9381

0.47UF

GND_VOID=TRUE

C9382

0.47UF

C9383

0.47UF

GND_VOID=TRUE

T29_A_BIAS_R2D_N1

C9364

0.22UF

C9365

0.22UF

C9360

0.22UF

C9361

0.22UF

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

DP_A_PWRDWN

84

IC supports input high while Vcc = 0V.

51

5% 1/16W MF-LF 402

1

10K

5% 1/16W MF-LF

402

2

21

T29_A_HV_EN

1

R9339

1M

5% 1/16W MF-LF 402

2

1

4V

20%

CERM-X5R-1

201

21

4V

20%

CERM-X5R-1

201

2

1

10%

6.3V

CERM-X5R

402

1 2

10%

6.3V

CERM-X5R

402

1

2

4V

20%

CERM-X5R-1

201

21

4V

20%

CERM-X5R-1

201

1

10%26.3V CERM-X5R

402

2

10%16.3V CERM-X5R

402

1 2

20%

6.3V 0201

X5R

1 2

6.3V

20%

0201

X5R

1 2

6.3V

20%

0201

X5R

1 2

20%

6.3V 0201

X5R

C9359

0.1UF

10% 16V X5R 402

2

R9396

1K

5% 1/16W MF-LF

402

1

P2R = Plug to Receptacle R2P = Receptacle to Plug

GND_VOID=TRUE

R9372

1.5K

1

T29_R2D_P<0>

6

95

T29_R2D_N<0>

6

95

R9373

1.5K

1

GND_VOID=TRUE

T29 Path Biasing

GND_VOID=TRUE

R9382

1.5K

1

T29_R2D_P<1>

6

95

T29_R2D_N<1>

6

95

R9383

1.5K

1

GND_VOID=TRUE

DP_SDRVA_ML_P<0>

6

95

DP_SDRVA_ML_N<0>

6

95

DP_SDRVA_ML_P<2>

6

95

DP_SDRVA_ML_N<2>

6

95

1

2

1

CRITICAL

5

U9359

74LVC1G04DBDCK

2

3

R9397

1K

5% 1/16W MF-LF 402

CBTL04DP081 (353S3151) and PI3vEDP212 (353S3055) are footprint-compatible parts with similar pinouts. NXP uses pin 10 for ML and HPD, Pericom uses pin 10 for ML and pin 11 for HPD.

35 85

OUT

4

SC70

DP/T29 A Low-Speed MUX

DP_SDRVA_ML_N<3>

95

DP_SDRVA_ML_P<3>

95

DP_SDRVA_ML_N<1>

95

DP_SDRVA_ML_P<1>

95

DP_SDRVA_AUXCH_P

95

DP_SDRVA_AUXCH_N

95

DP_SDRVA_HPD

CKPLUS_WAIVE=NdifPr_badTerm

T29_A_RSVD_N T29_A_RSVD_P

(T29_A_LSX_P2R) (T29_A_LSX_R2P)

T29_D2R1_BIASP T29_D2R1_BIASN

DP_A_PWRDWN

84

T29_A_BIAS

84 85

GND_VOID=TRUE

84

21

1M

21

1

C9312

0.1UF

20% 10V

2

CERM 402

MF-LF5%402

84

5%

MF-LF

1

IN_D0P

2

IN_D0N

4

IN_D1P

5

IN_D1N

7

IN_D2P

8

IN_D2N

9

IN_D3P

10

IN_D3N

14

IN_SCL

13

IN_SDA

16

IN_AUXP

15

IN_AUXN

3

IN_HPD

26

I2C_CTL_EN

36

I2C_ADDR0

35

I2C_ADDR1

38

SCL_CTL

37

SDA_CTL

12

REXT

39

AUXDDC_OFF

34

PD

PP3V3_S0

1/16W

R9308/R9309 maintain bias on C9308/C9309

1/16W

PS8301TQFN40GTR-A2

to prevent spikes when U9310 AUXDDC_OFF

402

transitions from high to low.

40

21

VDD

U9310

QFN

CRITICAL

OUT_AUXP_SCL OUT_AUXN_SDA

(IPD)

(IPU)

(IPD) (IPD)

(IPD)

GND 6

THMPAD

33

41

OUT_D0P OUT_D0N

OUT_D1P OUT_D1N

OUT_D2P OUT_D2N

OUT_D3P OUT_D3N

AC_AUXP AC_AUXN

OUT_HPD

CA_DET

CEXT

T29 signals are P/N-swapped after AC caps to improve layout.

88 89 98 48 49 50 51 53 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 56 60 61 71 72 79 82 83 84 87

30

DP_SDRVA_ML_C_P<0>

29

DP_SDRVA_ML_C_N<0>

28

DP_SDRVA_ML_C_P<1>

95

27

DP_SDRVA_ML_C_N<1>

95

25

DP_SDRVA_ML_C_P<2>

24

DP_SDRVA_ML_C_N<2>

23

DP_SDRVA_ML_C_P<3>

95

22

DP_SDRVA_ML_C_N<3>

95

20

DP_SDRVA_AUXCH_C_P

95

19

DP_SDRVA_AUXCH_C_N

95

18

(DP_SDRVA_AUXCH_P)

17

(DP_SDRVA_AUXCH_N)

31

(DP_SDRVA_HPD)

32

DP_A_CA_DET

11

DPSDRVA_CEXT

PLACE_NEAR=U9310.11:2 mm

C9319

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

6

33 95

2.2UF

OUT

IN

OUT

IN

6.3V CERM

402-LF

20%

T29_D2R_N<0> T29_D2R_P<0>

T29_R2D_C_N<0> T29_R2D_C_P<0>

T29_D2R_N<1> T29_D2R_P<1>

T29_R2D_C_N<1> T29_R2D_C_P<1>

R9354

R9355 R9350

R9351

84 87

IN

1

2

5%

1/20W

MF 201

1/20W

5%

1/20W

MF 201

1/20W

5%

201MF

OVERSIZE_PAD=0.875 mm^2

(Both L’s)

L9372

1.0NH+/-0.1NH

L9373

1.0NH+/-0.1NH Inductor values TBD

OVERSIZE_PAD=0.875 mm^2

(Both L’s)

L9382

L9383

30

1 2

1.0NH+/-0.1NH

1 2

1.0NH+/-0.1NH

1 2

1

R9353

270

5%

1/20W

MF

201

2

21

0.1uF

201MF5%

21

1

1 2

C9363

C9362

C9367

C9366

AUXCH Snoop Port, used by PS8301 during training.

C9369

C9368

21

95

0201-1

95

21

0201-1

95

0201-1

95

0201-1

DP_SDRVA_ML_R_P<0>

95

DP_SDRVA_ML_R_N<0>

95

DP_SDRVA_ML_R_P<2>

95

DP_SDRVA_ML_R_N<2>

95

1

R9352

270

5% 1/20W MF 201

2

2 10% 16V

402

X5R 21 10%

16V

X5R

402

21 10%

16V

X5R 402

10%

16V

X5R

402

21 10% 16V

X5R 402 21 10% 16V

402X5R

GND_VOID=TRUE

(C9370/C9371)

T29_R2D_C_F_N<0> T29_R2D_C_F_P<0>

GND_VOID=TRUE

(C9380/C9381)

T29_R2D_C_F_N<1> T29_R2D_C_F_P<1>

R9392

51

5% 1/16W MF-LF

402

Port A MCU

PP3V3_SW_DPAPWR

84 85

CRITICAL

1

RESET#/PIO0_0

2

PIO0_1/CLKOUT

7

PIO0_2/SSEL/CT16B0_CAP0

8

PIO0_4/SCL

9

PIO0_5/SDA

10

PIO0_6/SCK

11

PIO0_7/CTS#

12

PIO0_8/MISO/CT16B0_MAT0

13

PIO0_9/MOSI/CT16B0_MAT1

14

SWCLK/PIO0_10/SCK/CT16B0_MAT2

15

R/PIO0_11/AD0

(OD) (OD)

Must be 3.3V DP A port power

5

22

VDD

U9330

LPC1112A

HVQFN25

(OD)

VSS

3

OMIT_TABLE

(IPU)

SWDIO/PIO1_3/AD4

PIO1_4/AD5/WAKEUP

PIO1_8/CT16B1_CAP0

(OD)

THRM

PAD

21

25

R/PIO1_0/AD1 R/PIO1_1/AD2 R/PIO1_2/AD3

PIO1_6/RXD PIO1_7/TXD

XTALIN

1

C9330

0.1UF

20% 10V

2

CERM 402

16 17 18 19 20

23 24

6

4

1

2

1

C9331

0.1UF

20% 10V

2

CERM 402

T29DPA_CONFIG1_RC T29DPA_CONFIG2_RC T29_A_HV_EN_R T29_A_UC_ADDR DP_A_EXT_HPD

T29_A_LSX_P2R T29_A_LSX_R2P T29_LSEO<1>

R9335

1K

5% 1/16W MF-LF 402

1

R9336

10K

5% 1/16W MF-LF 402

2

85

IN

85

IN

84

45 83 84

33

IN

I2C Addr: 0x26/0x27 (Wr/Rd)

T29 A High-Speed Signals

5%

1/20W

201

MF

2

1/20W

5%

201MF

2

5%

1/20W

201

MF

2

1/20W

5% MF

201

2

DP_A_BIAS

D9364

BAR90-02LRH

D9372

BAR90-02LRH

D9373

BAR90-02LRH

D9365

BAR90-02LRH

D9372/D9373: D9364/D9365:

D9360

BAR90-02LRH

D9382

BAR90-02LRH

D9383

BAR90-02LRH

D9361

BAR90-02LRH

R9361 R9360

R9365 R9364

Must be 3.3V DP A port power

31 30

27 26

19 18

17

25 24

23 22

15 14

13

NC

10 32 11

Note: U9390 ML/HPD defaults to T29 mode so that DP/T29 Display can detect host T29 support using I2C pull-ups on ML<3>. U9390 AUX defaults to DP mode because 100-ohm pull-downs would defeat DP Sink’s

detection of DP Source.

2 1

T29_D2R_C_P<0>

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

R9374

GND_VOID=TRUE

R9375

GND_VOID=TRUE

GND_VOID=TRUE GND_VOID=TRUE

GND_VOID=TRUE

R9384

GND_VOID=TRUE

R9385

8

VOLTAGE=3.3V

1/20W

201

1/20W

8

201

1/20W

201

1/20W

201

1

R9399

100K

5% 1/16W MF-LF 402

2

1

2

T29_D2R_C_N<0>

(D9364.2)

T29: TX_0 T29DPA_ML_C_P<0> T29DPA_ML_C_N<0>

(D9372/D9373) (D9365.2)

1.5K

T29_D2R_C_P<1> T29_D2R_C_N<1>

(D9360.2)

T29: TX_1 T29DPA_ML_C_P<2> T29DPA_ML_C_N<2>

(D9382/D9383) (D9361.2)

1.5K

DP_A_BIAS0

DP_A_BIAS2

VOLTAGE=3.3V

R9363

51

1/20W

201

T29DPA_ML_N<3> T29DPA_ML_P<3> T29: Unused

T29DPA_ML_N<1> T29DPA_ML_P<1> T29: LSX_A_R2P/P2R (P/N)

DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N T29: RX_1 Bias Sink

DP_A_EXT_HPD

R9398

100K

5% 1/16W MF-LF 402

21

CRITICAL

(All 4 D’s)

SIGNAL_MODEL=T29PIN

SIGNAL_MODEL=EMPTY

2

1

21

1 2

21

CRITICAL

(All 4 D’s)

SIGNAL_MODEL=T29PIN

(D9382/D9383)

SIGNAL_MODEL=EMPTY

(D9360/D9361)

TSLP-2-7

GND_VOID=TRUE

DP Path Biasing

1.5K

PP3V3_SW_DPAPWR

84 85

292016129

DIN1_0+ DIN1_0-

CBTL04DP081

DIN1_1+ DIN1_1-

AUX1+ AUX1-

HPD_1

DIN2_0+ DIN2_0-

DIN2_1+ DIN2_1-

AUX2+ AUX2-

HPD_2

OMIT_TABLE

GPU_SEL AUX_SEL NC

THMPAD

33

SYNC_MASTER=T29_REF

PAGE TITLE

2

1

VDD

U9390

HVQFN

21

2

21

3

DOUT_0+ DOUT_0-

5% MF

PLACE_NEAR=C9361.1:2mm

1 2

CRITICAL

4

DOUT_1+

5

DOUT_1-

6

AUX+

7

AUX-

8

HPD_IN

LO=Port A HI=Port B

GND

SIGNAL_MODEL=T29DP_MUX

28

21

DisplayPort/T29 A MUXing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

IN

OUT

1 2

1

2

1

5%

MF

2

C9390

0.1UF

20% 10V CERM 402

5%

1/20W

201

MF

21

1/20W

5% MF

201

IN

OUT

5%

1/20W

201

MF

21

1/20W

5% MF

201

PLACE_NEAR=C9361.1:2mm

1

R9362

51

5% 1/20W MF 201

2

1

C9391

0.1UF

20% 10V

2

CERM 402

OUT

BI

OUT

BI

IN

SYNC_DATE=10/16/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

93 OF 132

SHEET

84 OF 101

6

85 95

6

85 95

6

85 95

6

85 95

6

85 95

6

85 95

6

85 95

6

85 95

45 83 84

SIZE

D

C

B

A

D

36

345678

2 1

PP3V3_SW_DPAPWR

84

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

Port A HV Power Switch

Nominal Min Max IFLT 885mA 876mA 894mA (*)

(*) U9410 tolerance unknown

D

35

PP15V_T29

7 8

20V Max

R9416

470K

1/16W MF-LF

402

5%

1

2

OMIT_TABLE

1

2

C9410

0.1UF

DPAPWRSW_HVEN_L_R

DPAPWRSW_CT

C9412

0.47UF

10%

6.3V CERM-X5R 402

603-1

1

10% 50V

2

X7R

CRITICAL

1 2

VIN

3 4

SN1010017

16

EN*

(IPU-Weak!)

6

RTRY*

9

CT

5

U9410

QFN

GND

131714

VOUT

FLT*

ILIM

IFLT THRM

PAD

<CT>

IFLT = 200k / RFLT = 885mA

Q9415

SSM3K15FV

SOD-VESM-HF

ILIM = 201k / RLIM = 935mA

3

D

TFLT = CCT * 38900 TSD = CCT * 100000

1

G S

10%

X5R 201

1

2

OUT

1

R9499

2.2K

5% 1/20W MF 201

2

GND_VOID=TRUE

8

T29_D2R_C_P<0>

6

84 95

OUT

T29_D2R_C_N<0>

6

84 95

OUT

T29DPA_ML_P<3>

6

84 95

BI

T29DPA_ML_N<3>

6

84 95

BI

T29: Unused

D9498

BAR90-02LRH

D9499

BAR90-02LRH

DP_A_EXT_AUXCH_P

84 95

BI

DP_A_EXT_AUXCH_N

84 95

BI

SIGNAL_MODEL=T29PIN

C

T29_A_HV_EN

35 84 85

IN

T29_A_BIAS

84 85

IN

T29_A_BIAS_D2R_P1

8

B

IN

T29_A_BIAS_D2R_N1

8

IN

6

84 95

OUT

6

84 95

OUT

T29_D2R_C_P<1> T29_D2R_C_N<1>

C9490

1

R9490

51

5% 1/20W MF 201

2

T29_A_BIAS_R

VOLTAGE=3.3V

R9498

2.2K

1/20W

GND_VOID=TRUE

0.1UF

1 2

6.3V

PLACE_NEAR=C9490.1:2mm

5%

MF

201

Bleeder Resistor

2.5V / 249 ohm = 10mA

R9419

249

2

1

1% 1/16W MF-LF

402

Note: Bleeder active when DPAPWRSW_HV_DET is HIGH and T29_A_HV_EN is LOW.

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

21

TSLP-2-7

21

TSLP-2-7

CRITICAL

GND_VOID=TRUE

R9494

1/20W

1

1K

5%

MF

201

2

(Both L’s)

P = ~27mW

DPAPWR_BLDR_E

MIN_LINE_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM

GND_VOID=TRUE

1

R9495

1K

2

SIGNAL_MODEL=EMPTY

ILIM 935mA 925mA 944mA (*) TFLT 18.3ms 13.4ms 26.7ms TSD 470ms 235ms 724ms

10 11 12

15

7

8

5% 1/20W MF 201

C9498

PPHV_SW_DPAPWR

1

C9411

0.1UF

10% 50V

2

X7R 603-1

TP_DPAPWRSW_FLT_L

DPAPWRSW_ILIM

DPAPWRSW_IFLT

R9410

Q9419

DMB53D0UV

3

SOT-563

5

4

G

2

650NH-5%-0.430MA-0.052OHM

SIGNAL_MODEL=EMPTY

T29DPA_D2R1_AUXCH_P

6

95

T29DPA_D2R1_AUXCH_N

6

95

650NH-5%-0.430MA-0.052OHM

SIGNAL_MODEL=EMPTY

1

30PF

CERM

5%

50V

402

C9499

30PF

5% 50V

2

CERM 402

100K

1/16W MF-LF

402

6

D

S

1

CRITICAL

L9498

2 1

CRITICAL

L9499

2 1

CRITICAL

D9410

SM

2

1

STPS2L30AF

1

R9411

210K

5%

1% 1/16W MF-LF 402

2

DPAPWR_BLDR_B

Q9419

DMB53D0UV

SOT-563

C9400

0.01UF

0603

GND_VOID=TRUE

R9427

100K

1/16W MF-LF

402

R9428

21.5K

1/16W MF-LF

402

C9426

0.1UF

ZXRE060A REF range: 0.595-0.605V (0.600V nominal) Circuit threshold range: 3.363-3.439V (3.395V nominal)

PP3V3RHV_SW_DPAPWR_UF

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

1

10% 50V

2

X7R 402

R9403

R9404

R9402

0.01UF

1

10% 50V

2

X7R 402

C9402

3.3V/HV Power MUX

SI8409DB: Vds(max): -30V Vgs(max): +/-12V Vgs(th): -1.4V Rds(on): 65mOhm @ 2.5V Vgs Id(max): 3.7A @ 70C

3.3V/HV MUXed

Blocking FET, off

1

1%

2

1

1%

2

20% 10V

CERM

402

12

5% 1/16W MF-LF

402

12

5% 1/16W MF-LF

402

12

5% 1/16W MF-LF

402

1

C9401

0.01UF

10% 50V

2

X7R 402

DPAPWRSW_VREF

1

2

GND_VOID=TRUE

21

GND_VOID=TRUE

21

3

CRITICAL

IN

OUT

U9426

ZXRE060A

SOT353

FB

GND

PGND

12

T29 Dir

GND_DPACONN_8

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

GND_DPACONN_14

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

DP Dir

T29DPA_HPD_R

DPACONN_20_RC

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

1

R9425

4.7K

5

4

FERR-120-OHM-3A

when Source >3.4V or HV_EN high.

5% 1/16W MF-LF

402

2

DPAPWRSW_P3V3_ON_L DPAPWRSW_HV_DET_R_L

1

R9429

4.7K

5% 1/16W MF-LF 402

2

DPAPWRSW_HV_DET_L

NO STUFF

1

C9429

0.1UF

20% 10V

2

CERM 402

L9400

0603

R9401

12

5% 1/16W MF-LF

402

21

CRITICAL

D9425

POWERDI-123

12

DFLS1100

CRITICAL

Q9425

SI8409DB

BGA

C9424

0.47UF

6.3V

CERM-X5R

R9424

1/16W MF-LF

1

10%

2

402

1

22

5%

402

2

4

SGD

1

DPAPWRSW_ON_L_C

R9418

1/16W MF-LF

32

1K

5%

402

3.3V Always

1

R9426

1K

5% 1/16W MF-LF 402

2

Q9426

MMDT3946XG

21

DPAPWRSW_HV_DET

SOT363

6

DisplayPort/T29 A Connector

PP3V3RHV_SW_DPAPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=18V

For J9400 T29 SMT pads (3, 5, 17 & 19): GND_VOID=TRUEGND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

J9400

DSPLYPRT-M97-1

F-RT-THSM

BOT ROW TOP ROW

TH PINS SM PINS

2

HOT_PLUG_DETECT

4

CONFIG1

6

CONFIG2

8

GND

10

ML_LANE3P

12

ML_LANE3N

14 13

GND

16

AUX_CHP

18

AUX_CHN

20

DP_PWR

SHIELD PINS

ML_LANE0P ML_LANE0N

ML_LANE1P ML_LANE1N

ML_LANE2P ML_LANE2N

21

22

GND

RETURN

1

3

5

7

9

11

15

17

19

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

DP Dir

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

GND_DPACONN_19

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

Port A 3.3V Power Switch

CRITICAL

U9480

TPS2051B

SOT23

T29_A_HV_EN

35 84 85

1

R9430

4.7K

5% 1/16W MF-LF 402

2

5

2

1

3

4

DPAPWRSW_NPN_E

GND_VOID=TRUE

GND_DPACONN_1

T29 Dir

T29: TX_0

GND_VOID=TRUE

GND_DPACONN_7

T29: LSX_R2P/P2R (P/N)

GND_VOID=TRUE

GND_DPACONN_13

T29: TX_1

C9486

1

10UF

20%

6.3V 2

X5R 603

Q9430

SSM6N37FEAPE

1

R9433

220

5% 1/16W MF-LF

402

2

OMIT_TABLE

6

95

6

95

6

95

6

95

FERR-120-OHM-3A

Circuit threshold range: 2.877-2.941V (2.903V nominal)

R9405

12

1

5%

1/20W

MF

201

T29DPA_ML_P<0> T29DPA_ML_N<0>

OMIT_TABLE

R9406

12

15%2

1/20W

MF

201

R9407

12

15%2

1/20W

MF

201

T29DPA_ML_P<2> T29DPA_ML_N<2>

L9408

0603

R9408

12

1

5%

1/20W

MF

201

1

2

SOT563

2

1

OUT

3

OC*

C9485

0.1UF

20% 10V CERM 402

5

1

R9432

10K

5% 1/16W MF-LF 402

2

21

D

SG

3

4 1

5

IN

4

EN

GND

2

C9481

0.1UF

CERM

20% 10V

402

1

2

2 2

CRITICAL

C9480

22UF

20%

6.3V X5R-CERM-1 603

DPAPWRSW_P3V3_ON

6

D

Q9430

SSM6N37FEAPE

SOT563

S G

C9436

DPAPWRSW_ON_C

2

1UF

T29_A_HV_EN

R9437

1/16W MF-LF

GND_VOID=TRUE

(Both C’s)

C9470

C9471

GND_VOID=TRUE

1

R9470

470K

5% 1/20W MF 201

2

C9472

C9473

GND_VOID=TRUE

1

R9472

470K

5% 1/20W MF 201

2

470k R’s for ESD protection on AC-coupled signals.

1 2

0.47UF

1 2

0.47UF

GND_VOID=TRUE

(Both C’s)

1 2

0.47UF

1 2

0.47UF

20%

4V

CERM-X5R-1

201

20%

4V

CERM-X5R-1

201

GND_VOID=TRUE

1

R9471

470K

5% 1/20W MF 201

2

4V

20% CERM-X5R-1

201

20%

4V

CERM-X5R-1

201

GND_VOID=TRUE

1

R9473

470K

5% 1/20W MF 201

2

DP_PWR must be S4 to support wake from T29 devices.

PP3V3_S5

SMC_S4_WAKESRC_EN

CRITICAL

1

C9487

100UF

20%

6.3V POLY-TANT CASE-B2-SM

T29_A_BIAS

84 85

CRITICAL

1

10% 10V

2

X5R 402

85 35 84

1

82

5%

402

2

DPAPWR_FB_DIV

T29DPA_ML_C_P<0> T29DPA_ML_C_N<0>

T29DPA_ML_P<1> T29DPA_ML_N<1>

T29DPA_ML_C_P<2> T29DPA_ML_C_N<2>

5

OUT

U9435

ZXRE060A

SOT353

4

FB

PGND

T29_2V9_ENABLE

3

IN

GND

1 2

R9435

R9436

24.9K

100K

1/16W MF-LF

IN

1

1%

402

2

1

1%

402

2

1

2

IN

BI

IN

45 55 65 70 71 6 7 23 24 25 29 39 72 82 89 98

44 45 72

C9435

0.1UF

20% 10V CERM 402

84 95

6

84 95

6

84 95

17 19 20 22

D

C

B

T29DPA_HPD

84

A

8 7 5 4 2 1

OUT

T29DPA_CONFIG1_RC

84

OUT

T29DPA_CONFIG2_RC

84

OUT

R9452

1/16W MF-LF

402

SIZE

A

D

DP Source must pull down HPD input with greater than or equal

1

R9451

1M

5%

5% 1/16W MF-LF 402

2

C9494

330PF

CERM

1

C9495

10% 50V

402

330PF

10% 50V

2

CERM 402

to 100K (DPv1.1a).

Sink HPD range: High: 2.0 - 5.0V Low: 0 - 0.8V

1

R9441

100K

5% 1/16W MF-LF 402

2

PART NUMBER

116S0004

132S0121

QTY

1

DESCRIPTION

RES,0 OHM,5,1/16W,0402,SMD,LF

CAP,CER,0.1UF,10%,6.3V,X5R,0201,SMD

REFERENCE DES

C9412

R9405

R9406

CRITICAL

BOM OPTION

SYNC_MASTER=T29_REF

PAGE TITLE

DisplayPort/T29 A Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=10/16/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

94 OF 132

SHEET

85 OF 101

36

345678

2 1

D

PPVIN_S5_HS_GPU_ISNS

7

49 81

C

PP1V0_S0GPU

7

100

Vout = 1.003V

3.5A MAX OUTPUT

(Q9510 limit?)

f = 400 kHz

XW9515

SM

1 2

CRITICAL

1

C9515

10UF

20%

6.3V 2

X5R 603

P1V0S0_VSNS

<Ra>

1

R9520

B

8.66K

1% 1/16W MF-LF 402

2

<Rb>

1

R9521

20.0K

1% 1/16W MF-LF 402

2

C9516

1000PF

5%

25V

NP0-C0G

402

PLACE_NEAR=L9510.1:3mm

NO STUFF

C9520

100PF

5%

50V

CERM

402

1

2

1

2

Vout = 0.7V * (1 + Ra / Rb) (Rb should be between 10K and 100K)

CRITICAL

CASE-D2E-SM

2.2UH-8.0A

1 2

CRITICAL

1

C9510

330UF

20%

2.0V

2

POLY-TANT B2-SM

C9540

68UF

POLY-TANT

CRITICAL

L9510

PCMB065T-SM

1

20% 16V

2

C9545

1UF

10% 25V X5R 603-1

1

C9546

1000PF

5% 25V

2

NP0-C0G 402

CRITICAL

Q9510

SIZ700DT

POWERPAIR-6X3.7

CRITICAL

1

C9590

C9580

0.1UF

10% 50V X7R 603-1

1

R9562

78.7K

1% 1/16W MF-LF 402

2

GPUFB_VID_L

68UF

20% 16V

POLY-TANT

CASE-D2E-SM

P1V5FB_DRVH

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

DIDT=TRUE

P1V5FB_DRVL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

DIDT=TRUE

P1V5FB_LL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE

DIDT=TRUE

Vout = 2(Req/(Ra+Req))

R9500

4.7

12

PVIN_S0GPU_P1V0

5% 1/16W MF-LF

IN

8

OUT

8

OUT

IN

402

P1V0GPU_VFB P1V0GPU_TRIP

1

R9535

75K

1% 1/16W MF-LF 402

2

P1V0GPU_EN PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD P1V5FB_EN

CRITICAL

C9500

10UF

10% 25V X5R 805

C9501

1UF

402-1

PP5V_S0

1

10% 10V

2

X5R

1

2

PVCC

VIN

17 24

BOOT1

15 26

UGATE1

16 25

PHASE1

18 23

LGATE1

10 30

OUT1

14 27

EN1

9

BYP

11

FB1

12 31

ILIM1

29

SKIP*

4

EN_LDO

20

SECFB

2

TON

THRM_PAD

353S2312

GND_P1V0P1V5_SGND

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

19

U9500

33

(Internal 10-ohm path from PVCC to VCC)

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S0GPU_VREF

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

365

VREF3

VCC

CRITICAL

LDOREFIN

QFN2

ISL6236

GND

PGND

21

22

XW9500

1 2

UGATE2 PHASE2 LGATE2

REFIN2

PP5V_S0GPU_P1V0P1V5_VCC

C9504

1UF

10% 10V X5R

402-1

7

LDO

NC

8

BOOT2

OUT2

ILIM2

POK1 POK2

SM

EN2

REF

32

1

13

28

(=PP1V5FB_S0_REG)

GPU_P1V5_REFIN P1V5FB_TRIP

PP2V_S0GPU_P1V5_REF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=2V

1

2

6 7 8

22 41 46 51 53 64 67 68 69 71 72 88

101

C9503

1

2

402-1

1UF

10% 10V X5R

(SGND)

DIDT=TRUE

1

R9585

130K

1% 1/16W MF-LF

402

2

C9585

0.1UF

20% 10V CERM 402

1

2

P1V5FB_VBST

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

<Ra>

R9563

11.8K

1/16W MF-LF

<Rb>

R9564

35.7K

402

1/16W MF-LF

1

2

1

P1V5_GPU_VSNS

1%

2

1

C9561

1%

402

0.001UF

10% 50V

2

CERM 402

2

237

1

P1V0GPU_DRVH

MIN_LINE_WIDTH=0.6MM

45

MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

DIDT=TRUE

6

P1V0GPU_DRVL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

DIDT=TRUE

C9530

0.1UF

10% 50V X7R

603-1

1

2

P1V0GPU_VBST

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

P1V0GPU_LL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE

DIDT=TRUE

87 89

73 81 86 87 89

89

8

1

2

3

D

2

C9595

1UF

10% 25V X5R 603-1

CRITICAL

Q9565

SSM3K15FV

SOD-VESM-HF

GS

4

G

1

FBVDD_ALTVO

1

C9596

1000PF

5% 25V

2

NP0-C0G 402

4

D

S

1 23

G

5

D

S

1 23

CRITICAL

Q9561

SIS426DN

PWRPK-12128

GPIO7

1 0

CRITICAL

Q9560

SIS426DN

PWRPK-12128

FBVDDQ

1.35V

1.503V

78 79

IN

CRITICAL

L9560

1.0UH-13A-5.6MOHM

1 2

PCMB065T-SM

XW9565

SM

PLACE_NEAR=L9560.2:3mm

12

CRITICAL

C9560

220UF

POLY-TANT

CASE-B2-SM2

2.5V

PP1V5_GPU_REG

Vout = 1.503V 8A MAX OUTPUT F = 500 KHZ

CRITICAL

1

20%

2

C9565

10UF

20%

6.3V X5R 603

1

C9566

1000PF

5% 25V

2

NP0-C0G 402

D

C

7

100

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K91_ERIC SYNC_DATE=10/08/2010

PAGE TITLE

1V0 GPU / 1V5 FB Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

95 OF 132

SHEET

86 OF 101

SIZE

A

D

C

B

A

83 84 87 88 53 56 60 61 40 41 45 47 23 25 26 28

PP3V3_S0

6 7

12 16 17

18 19 20 22 32 35 36 39 48 49 50 51 71 72 79 82 89 98

25 70

PP1V8_S0

6 7

14

17 20 22 71

PP1V2_S0

6 7

70

88 89 98 72 79 82 51 53 56 41 45 47 28 32 35 19 20 22

PP3V3_S0

6 7

12

16 17 18 23 25 26 36 39 40 48 49 50 60 61 71 83 84 87

R9645

NO STUFF

R9646

GMUX_JTAG_CONN

345678

R9600

0

1 2

5% 1/16W MF-LF

402

10K

1/20W

1%

MF

201

1

C9610

0.1UF

20% 10V

2

CERM 402

1

2

R9610

1 2

R9640

10K

1/20W MF

1%

201

5% 1/16W MF-LF

402

1

C9621

0.1UF

20% 10V

2

CERM 402

0

1

2

1

2

1

2

C9600

1

4.7UF

20%

4V

2

X5R-1

402

C9622

0.1UF

20% 10V CERM 402

C9611

0.1UF

20% 10V CERM 402

1

C9604

0.1UF

20% 10V

2

CERM 402

1

C9623

0.1UF

20% 10V

2

CERM 402

1

C9612

0.1UF

20% 10V

2

CERM 402

1

C9605

0.1UF

20% 10V

2

CERM 402

1

C9624

0.1UF

20% 10V

2

CERM 402

1

C9613

0.1UF

20% 10V

2

CERM 402

1

C9625

0.1UF

20% 10V

2

CERM 402

1

C9614

0.1UF

20% 10V

2

CERM 402

1

C9606

0.1UF

20% 10V

2

CERM 402

JTAG_ISP_TCK

8

19 23 33 87

JTAG_GMUX_TDI

87

JTAG_GMUX_TDO

87

JTAG_GMUX_TMS

18 87

GMUX_TOE

1

C9607

0.1UF

20% 10V

2

CERM 402

1

C9626

0.1UF

20% 10V

2

CERM 402

1

C9615

0.1UF

20% 10V

2

CERM 402

GMUX_CFG0

10K

1/20W

1%

MF

201

NO STUFF

1

R9641

2

10K

1/20W MF

201

1

1%

2

CRITICAL

J9600

1909782

M-RT-SM

7

1

PP3V3_S0

2

JTAG_GMUX_TDO

3

JTAG_GMUX_TDI

4

JTAG_GMUX_TMS

5

6

JTAG_ISP_TCK

8

(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 88 89 98

PP3V3_T29

7

16 19 25 33 34 35

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89 98

87

18 87

8

19 23 33 87

NO STUFF

R9647

10K

1%

1/20W

MF

201

NO STUFF

1

R9670

10K

1% 1/20W MF 201

2

GMUX_VSYNC

R9605

1K

1 2

5%

1/20W

MF

201

1

2

8

87 88

T29_JTAG_FET

LCD_BKLT_EN

8

88

OUT

LCD_BKLT_PWM

6

87 88

OUT

LVDS_DDC_SEL_EG

83 87

OUT

LVDS_DDC_SEL_IG

83 87

OUT

DP_MUX_EN

83

OUT

DP_MUX_SEL_EG

83 87

OUT

EG_RESET_L

8

73 87

OUT

P3V3GPU_EN

71 87 89

OUT

GPUVCORE_EN

81 87 89

OUT

P1V0GPU_EN

86 87 89

OUT

P1V5FB1V8GPU_R_EN

87 89

OUT

PEG_CLKREQ_L

8

16

OUT

DP_CA_DET_EG

79

OUT

LCD_PWR_EN

82 87

OUT

LPC_AD<0>

6

16 44 46 93

BI

LPC_AD<1>

6

16 44 46 93

BI

LPC_AD<2>

6

16 44 46 93

BI

LPC_AD<3>

6

16 44 46 93

BI

LPC_FRAME_L

6

16 44 46

BI

93

LPCPLUS_RESET_L

6

25 46 93

IN

LPC_CLK33M_GMUX

25

IN

GMUX_INT

19

OUT

LVDS_IG_B_DATA_P<2>

18 87 92

IN

LVDS_IG_B_DATA_N<2>

18 87 92

IN

GMUX_PL6A

TP_GMUX_PL6B

6

LVDS_IG_A_DATA_P<0>

18 87 92

IN

LVDS_IG_A_DATA_N<0>

18 87 92

IN

LVDS_IG_A_DATA_P<1>

18 87 92

IN

LVDS_IG_A_DATA_N<1>

18 87 92

IN

LVDS_IG_A_DATA_P<2>

18 87 92

IN

LVDS_IG_A_DATA_N<2>

18 87 92

IN

LVDS_IG_B_DATA_P<0>

18 87 92

IN

LVDS_IG_B_DATA_N<0>

18 87 92

IN

LVDS_IG_B_DATA_P<1>

18 87 92

IN

LVDS_IG_B_DATA_N<1>

18 87 92

IN

LVDS_IG_A_CLK_P

18 87 92

IN

LVDS_IG_A_CLK_N

18 87 92

IN

TP_LVDS_MUX_SEL_EG

8

OUT

TP_GMUX_PL14B GMUX_RESET_L

25

IN

GMUX_VSYNC

8

87 88

PM_ALL_GPU_PGOOD

8

73 81 86 89

IN

PEX_CLKREQ_L

8

79

IN

SSM6N15FEAPE

JTAG_ISP_TDI

8

19 33

Q9605

SOT563

D

2

SG

1

C9627

0.1UF

20% 10V

2

CERM 402

1

C9616

0.1UF

20% 10V

2

CERM 402

1

C9608

0.1UF

20% 10V

2

CERM 402

K14 L13 K13 L12

K2

K1

P2 N2 P4 N4 N3 M4 P5 M5 P6 M6 P7 M7 N7 N8 P9

N9 P10 M10 P12 P13 N12 P14

B1

B2

C2

D3

D1

E1

D2

E3

F1

G1

F3

G2

H2

G3

H1

H3

L1

L3

K3

L2

N1

P1

JTAG_GMUX_TDI JTAG_GMUX_TDO

6

SSM6N15FEAPE

1

JTAG_ISP_TDO

8

19 33

GMUX CPLD

1

C9628

0.1UF

20% 10V

2

CERM 402

1

C9617

0.1UF

20% 10V

2

CERM 402

1

C9609

0.1UF

20% 10V

2

CERM 402

B11C4J3

J13

VCC

TCK TDI TDO TMS TOE

CFG0

PB7A PB7B

PB14A PB14B PB15A

(OD) PB15B PB16A PB16B PB17A PB17B PB18A PB18B PB19A PB19B PB20A PB20B

PB26A PB26B PB27A PB27B PB28A PB28B

PL2A PL2B

PL6A PL6B PL7A PL7B PL8A PL8B PL9A PL9B

PL10A PL10B PL11A PL11B PL12A PL12B PL14A PL14B PL15A PL15B

PL25A PL25B

BANK5 BANK7BANK4

(OD)

BANK6

87 87

Q9605

SOT563

5

1

2

PP1V8_S0_GMUX_R

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm

VOLTAGE=1.8V

N11P8C11J2J14M8B5B7A12

VCCAUX

GND

GNDIO0

J1B8C6

3

D

SG

4

C9629

0.1UF

20% 10V CERM 402

CRITICAL

GNDIO1

GNDIO2

C12

C13

E13

PP3V3_S0_GMUX_R

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm

VCCIO0

C14

F13

M12M9M3N5M1C3F2

VCCIO2

VCCIO1

VCCIO3

VOLTAGE=3.3V

VCCIO4

OMIT

U9600

XP25-5

CSBGA

GNDIO3

GNDIO4

GNDIO5

GNDIO6

GNDIO7

N6P3M2C1E2

M14

N10

VCCIO5

VCCIO6

LRC_GNDPLL

ULC_GNDPLL

B4

M11

PP3V3_S0_GMUX_ULC_VCCPLL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=3.3V

PP3V3_S0_GMUX_LRC_VCCPLL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=3.3V

P11

A4

K12

VCCJ

VCCIO7

LRC_VCCPLL

ULC_VCCPLL

A2

PT7A

A3

PT7B

A1

PT8A

B3

PT8B

C5

PT9A

A5

PT9B

B6

PT14A

C7

PT14B

A6

PT15A

A7

PT15B

C8

PT16A

C9

PT16B

A8

PT17A

B9

PT17B

A9

PT18A

C10

PT18B

B10

PT19A

A10

PT19B

A11

PT20A

B12

PT20B

B13

PT28A

A13

PT28B

A14

PR2A

B14

PR2B

D12

PR6A

D13

PR6B

D14

PR7A

E14

PR7B

E12

PR8A

F12

PR8B

F14

PR9A

BANK2 BANK0

BANK3 BANK1

PR9B

PR10A PR10B PR11A PR11B PR12A PR12B PR14A PR14B

PR24A PR24B

G14 G12 G13 H13 H12 H14 J12 L14 M13 N14 N13

18

53 54 71 72 6 7 8 19 24 25 29 30 31 32 47 48 49

23 44 72 89

IN

1

C9631

0.1UF

20% 10V

2

CERM 402

1

C9630

0.1UF

20% 10V

2

CERM 402

LVDS_B_DATA_P<0> LVDS_B_DATA_N<0> LVDS_B_DATA_P<1> LVDS_B_DATA_N<1> LVDS_B_DATA_P<2> LVDS_B_DATA_N<2> EG_PWRSEQ_EN GMUX_DEBUG_RESET_L LVDS_A_CLK_P LVDS_A_CLK_N LVDS_B_CLK_P LVDS_B_CLK_N LVDS_A_DATA_P<0> LVDS_A_DATA_N<0> LVDS_A_DATA_P<1> LVDS_A_DATA_N<1> LVDS_A_DATA_P<2> LVDS_A_DATA_N<2> GND GND GND GND

DP_A_CA_DET DP_HOTPLUG_DET LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_N<0> LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_N<1> LVDS_EG_A_DATA_P<2> LVDS_EG_A_DATA_N<2> LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<0> LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1> LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2> LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_IG_PANEL_PWR EG_LCD_PWR_EN LVDS_IG_BKL_ON EG_BKLT_EN

PP3V3_S3

ALL_SYS_PWRGD

L9621

FERR-220-OHM

1 2

0402

L9620

FERR-220-OHM

1 2

0402

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

87

IN

87

IN

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

83 97

OUT

84

IN

83

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

78 87 97

IN

8

IN

78 79

IN

8

IN

78 79

IN

1

2

SSM6N15FEAPE

R9676

100K

5% 1/20W MF 201

GMUX_S3_PD_EN

Q9607

SOT563

(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)

18

Q9607

SOT563

5

6

D

2

SG

1

8 7 5 4 2 1

LVDS Receiver Termination

LVDS_IG_A_CLK_P

18 87 92

LVDS_IG_A_DATA_P<0>

18 87 92

LVDS_IG_A_DATA_P<1>

18 87 92

LVDS_IG_A_DATA_P<2>

18 87 92

LVDS_IG_B_DATA_P<0>

18 87 92

LVDS_IG_B_DATA_P<1>

18 87 92

LVDS_IG_B_DATA_P<2>

18 87 92

LVDS_EG_A_CLK_P

78 87 97

LVDS_EG_A_DATA_P<0>

78 87 97

LVDS_EG_A_DATA_P<1>

78 87 97

LVDS_EG_A_DATA_P<2>

78 87 97

LVDS_EG_B_DATA_P<0>

78 87 97

LVDS_EG_B_DATA_P<1>

78 87 97

LVDS_EG_B_DATA_P<2>

78 87 97

R9650 R9651 R9652 R9653

R9654 R9655 R9656

R9660 R9661 R9662 R9663

R9664 R9665 R9666

100 100 100 100

100 100 100

100 100 100 100

100 100 100

SIGNAL_MODEL=EMPTY

Required Pullups

EG_PWRSEQ_EN

87

JTAG_GMUX_TDI

87

JTAG_GMUX_TDO

87

GMUX_DEBUG_RESET_L

87

SILK_PART=GMUX_RST

NO STUFF

R9679

10K

1/16W MF-LF

R9684

R9685

R9686

R9680

1

1%

402

2

1K

10K

1K

Required Pulldowns

1

R9671

4.7K

5% 1/20W MF 201

2

R9681

R9682

R9683

R9691

R9693

1

R9675

0

5% 1/16W MF-LF 402

2

1

2

NO STUFF

DP_MUX_SEL_EG

83 87

LVDS_DDC_SEL_IG

83 87

LVDS_DDC_SEL_EG

83 87

EG_RESET_L

8

73 87

LCD_BKLT_PWM

6

87 88

P1V5FB1V8GPU_R_EN

87 89

P1V0GPU_EN

86 87 89

GPUVCORE_EN

81 87 89

P3V3GPU_EN

71 87 89

LCD_PWR_EN

82 87

3

D

SG

4

36

R9678

1

4.7K

1/20W

201

2

5%

MF

2 1

1 2

R9672

4.7K

5% 1/20W MF 201

10K

100K

1 2

NO STUFF

1 2

PAGE TITLE

PLACE_NEAR=U9600.H3:5mm

1/20W

5% MF

5%

5% MF

5%

1

R9673

4.7K

5% 1/20W MF 201

2

MF

MF1%

MF

1/20W

1%

PLACE_NEAR=U9600.E1:5mm

1%

PLACE_NEAR=U9600.E3:5mm

1%

PLACE_NEAR=U9600.G1:5mm

1%

PLACE_NEAR=U9600.G2:5mm

1%

PLACE_NEAR=U9600.G3:5mm

1%

PLACE_NEAR=U9600.B2:5mm

1%

PLACE_NEAR=U9600.J12:5mm

1%

PLACE_NEAR=U9600.D13:5mm

PLACE_NEAR=U9600.E14:5mm

1%

PLACE_NEAR=U9600.F12:5mm

1%

PLACE_NEAR=U9600.G14:5mm

1%

PLACE_NEAR=U9600.G13:5mm

1%

PLACE_NEAR=U9600.H12:5mm

1%

5%

Graphics MUX (GMUX)

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

LVDS_IG_A_CLK_N

201

LVDS_IG_A_DATA_N<0>

201

LVDS_IG_A_DATA_N<1>

201

LVDS_IG_A_DATA_N<2>

201

LVDS_IG_B_DATA_N<0>

201

LVDS_IG_B_DATA_N<1>

201

LVDS_IG_B_DATA_N<2>

201

LVDS_EG_A_CLK_N

201

LVDS_EG_A_DATA_N<0>

201

LVDS_EG_A_DATA_N<1>

201

LVDS_EG_A_DATA_N<2>

201

LVDS_EG_B_DATA_N<0>

201

LVDS_EG_B_DATA_N<1>

201

LVDS_EG_B_DATA_N<2>

201

2015%

201

MF

1

R9674

4.7K

5% 1/20W MF 201

2

GMUX_S3_PD_GND

Apple Inc.

PP3V3_S0

201

SYNC_DATE=08/03/2010SYNC_MASTER=K91_MARY

DRAWING NUMBER

REVISION

BRANCH

PAGE

96 OF 132

SHEET

87 OF 101

18 87 92

78 87 97

SIZE

D

C

B

A

D

345678

2 1

PPBUS S0 LCDBkLT FET

MOSFET

CHANNEL

CRITICAL

Q9706

FDC638APZ_SBMS001

F9700

3AMP-32V-467

8

87

1 2

603-HF

BOTTOM

LCD_BKLT_EN

IN

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

1

R9788

301K

1% 1/16W MF-LF 402

2

LCDBKLT_EN_DIV

1

R9789

147K

1% 1/16W MF-LF 402

2

LCDBKLT_EN_L

Q9707

SSM6N15FEAPE

SOT563

D

5

SG

SSM6N15FEAPE

1

C9782

0.1UF

10% 16V

2

X5R 402

3

4

LCDBKLT_DISABLE

Q9707

SOT563

D

35 39

PPBUS_G3H

6 7 8 48 49 62 63

SSOT6-HF

4

3

6

D

RDS(ON)

LOADING

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

1 256

47 48 49 50 51 53 56 60 61 71

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 72 79 82 83 84 87 89 98

C

2

SG

25

IN

BKLT_PLT_RST_L

8

87

16 23 26 28 30 41 47 61 93

Addr: 0x58(Wr)/0x59(Rd)

88

100

1

GMUX_VSYNC

IN

SMBUS_PCH_CLK

IN

SMBUS_PCH_DATA

BI

PPBUS_SW_LCDBKLT_PWR

B

LCD_BKLT_PWM

6

87

IN

BKL_VSYNC_R

NO STUFF

1

R9754

0

5% 1/16W MF-LF 402

2

R9757

0

1 2

5% 1/16W MF-LF

402

R9704

33

1 2

5% 1/16W MF-LF

402

R9753

1 2

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.715 A (EDP)

88

THERE IS A SENSE RESISTOR BETWEEN PPBUS_SW_LCDBKLT_PWR AND PPBUS_SW_BKL ON THE SENSOR PAGE

PP5V_S0

6 7 8

22 41 46 51 53 64 67 68 69 71 72

86

101

PPBUS_SW_BKL

7

100

PLACE_NEAR=L9701.1:3mm

1

R9755

10K

5% 1/16W MF-LF 402

2

NO STUFF

C9740

10UF

1 2

20%

6.3V X5R 603

0

5% 1/16W MF-LF

402

1 2

R9731

301K

1/16W MF-LF

1

C9704

33PF

5% 50V

2

CERM 402

100

CRITICAL

C9712

1%

402

1

10UF

10% 25V

2

X5R 805

PLACE_NEAR=U9701.C4:4mm

MIN_NECK_WIDTH=0.075 mm

NO STUFF

C9741

1UF

1 2

10%

6.3V X5R 402

BKL_FLTR_R

R9741

10K

1 2

5% 1/16W MF-LF

402

MIN_NECK_WIDTH=0.075 mm MIN_NECK_WIDTH=0.075 mm

2

R9715

100K

1% 1/16W MF-LF 402

1

see spec for others

1

C9713

0.1UF

10% 25V

2

X5R 402

PLACE_NEAR=L9701.1:3mm

PLACE_NEAR=U9701.D1:5mm

C9711

0.1UF

NO STUFF

R9740

47.0K

1 2

MIN_NECK_WIDTH=0.075 mm

MIN_NECK_WIDTH=0.075 mm MIN_NECK_WIDTH=0.075 mm

C9710

1

10% 16V

2

X5R 402

1% 1/16W MF-LF

402

PLACE_SIDE=BOTTOM

R9716

Fpwm=9.62kHz

1

1UF

10% 25V

2

X5R

603-1

TP_BKL_FAULT

1

90.9K

1% 1/16W MF-LF

402

2

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

33UH-1.8A-110MOHM

PLACE_NEAR=U9701.D1:3mm

1

C9714

0.01UF

10% 16V

2

CERM 402

C4C1D1

VDDIO

VLDO

U9701

25-BUMP-MICRO

D2

VSYNC

BKL_FLTR BKL_ISET BKL_FSET BKL_SCL

BKL_SDA

BKL_PWM

BKL_EN

I_LED=22.7mA

1

R9714

16.2K

1% 1/16W MF-LF 402

2

GND_BKL_SGND

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

I_LED=369/Riset (EEPROM should set EN_I_RES=1)

C2

FILTER

B3

ISET

B4

FSET

D3

SCLK

D4

SDA

A4

PWM

A3

EN

C3

FAULT

CRITICAL

GND_S

E4B5A1

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

XW9710

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

CRITICAL

L9701

1 2

1217AS-2SM

VIN

B1

SW_0

B2

SW_1

A5

FB

OUT1 OUT2 OUT3 OUT4 OUT5 OUT6

GND_SW

E5

BKL_ISEN1

D5

BKL_ISEN2

C5

BKL_ISEN3

E3

BKL_ISEN4

E2

BKL_ISEN5

E1

BKL_ISEN6

LP8550

GND_L

A2

SM

1 2

PLACE_NEAR=L9701.2:3mm

CRITICAL

D9701

PPBUS_SW_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=50V SWITCH_NODE=TRUE DIDT=TRUE

SOD-123

RB160M-60G

XW9720

PPVOUT_SW_LCDBKLT_FB

VOLTAGE=50V

PLACE_NEAR=C9797.1:5mm

1 2

PLACE_NEAR=U9701.A5:3mm

1

2

SM

1 2

PLACE_NEAR=U9701.E5:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.D5:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.C5:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.E3:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.E2:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.E1:10mm

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

C9796

220PF

10% 50V X7R-CERM 402

CRITICAL

1

C9797

10UF

10% 50V

2

X5R 1210-1

PLACE_NEAR=D9701.2:3mm

BKLT:PROD

R9717

0

1 2

5% 1/16W MF-LF

BOTTOM

402

BKLT:PROD

R9718

0

1 2

5% 1/16W MF-LF

BOTTOM

402

BKLT:PROD

R9719

0

1 2

5% 1/16W MF-LF

BOTTOM

402

BKLT:PROD

R9720

0

1 2

5% 1/16W MF-LF

BOTTOM

402

BKLT:PROD

R9721

0

1 2

5% 1/16W MF-LF

BOTTOM

402

BKLT:PROD

R9722

0

1 2

5% 1/16W MF-LF

BOTTOM

402

PPVOUT_S0_LCDBKLT

CRITICAL

1

C9799

10UF

10% 50V

2

X5R 1210-1

PLACE_NEAR=D9701.2:5mm

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V

D

6 8

82

100

C

6

82

OUT

6

82

OUT

B

6

82

OUT

6

82

OUT

6

82

OUT

6

82

OUT

A

PART NUMBER

103S0198 103S0198

QTY

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

3 3

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

DESCRIPTION

8 7 5 4 2 1

REFERENCE DES

R9717,R9718,R9719

R9720,R9721,R9722

CRITICAL

BOM OPTION

BKLT:ENG BKLT:ENG

10.2 ohm resistors for current measurement on LED strings.

36

SYNC_MASTER=K90I_KIRANSYNC_DATE=06/25/2010

PAGE TITLE

LCD Backlight Driver

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

REVISION

BRANCH

PAGE

97 OF 132

SHEET

88 OF 101

SIZE

A

D

345678

2 1

GPU Rail Sequencing

Whistler GPU requires rails to come up in the following order:

D

P3V3GPU_EN

71 87 89

GPUVCORE_EN

81 87 89

P1V0GPU_EN

86 87 89

P1V5FB1V8GPU_R_EN

87 89

1) GPU_3.3V

2) GPUVcore

3) GPU_1.0V

4) GPU_1.8V;GDDR5 1.5/1.35V

P3V3GPU_EN

71 87 89

MAKE_BASE=TRUE

GPUVCORE_EN

81 87 89

MAKE_BASE=TRUE

P1V0GPU_EN

86 87 89

MAKE_BASE=TRUE

P1V5FB1V8GPU_R_EN

87 89

MAKE_BASE=TRUE

R9932

0

1 2

5% 1/16W MF-LF

PLACE_NEAR=U7880.2:7mm

402

P3V3GPU_EN

GPUVCORE_EN

P1V0GPU_EN

PLACE_NEAR=U9500.27:7mm

R9931

0

1 2

5% 1/16W MF-LF

402

1

C9932

0.47UF

10%

6.3V

2

CERM-X5R 402

NO STUFF

P1V5FB_EN

86 89

MAKE_BASE=TRUE

P1V8GPU_EN

71 89

MAKE_BASE=TRUE

1

C9931

0.47UF

10%

6.3V

2

CERM-X5R 402

NO STUFF

PP3V3_S5

6 7

17 19 20 22 23 24 25 29

39 45 55 65 70 71 72 82 85 98

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 47 48 49 50 51 53 56 60 61 71 72 79 82 83 84 87 88 89

71 87 89

OUT

81 87 89

OUT

86 87 89

OUT

P1V5FB_EN

P1V8GPU_EN

86 89

OUT

71 89

OUT

98

23 44 72 87

IN

CPUIMVP_PGOOD

67

IN

ALL_SYS_PWRGD

R9950

PLACE_NEAR=U1800.p12:7mm

C

PCH S0 PWRGD

1

1K

5% 1/16W MF-LF

402

2

74LVC2G08GT

8

1

A

U9950

2

08

B

4

SMC_DELAYED_PWRGD

35 44

1

C9950

0.1UF

20% 10V

2

CERM 402

SOT833

7

Y

PM_S0_PGOOD

5

A

U9950

6

B

74LVC2G08GT

8

08

4

SOT833

3

SYS_PWROK_R

Y

R9960

0

1 2

5% 1/16W MF-LF

402

NO STUFF

R9963

0

1 2

5% 1/16W MF-LF

402

R9962

1K

1 2

5% 1/16W MF-LF

402

PM_PCH_SYS_PWROK

NO STUFF

PLACE_NEAR=U1800.L22:5.54mm

1

R9961

0

5% 1/16W MF-LF 402

2

PM_PCH_PWROK

MAKE_BASE=TRUE

PM_PCH_PWROK

D

17 23

OUT

C

17 19 89

OUT

17 19 89

EXT GPU PWRGD Pullup

88 89 98

PP3V3_S0

47 48 49 50 51 53 56

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 60 61 71 72 79 82 83 84 87

1

B

PLACE_NEAR=U8000.AH16:7mm

PM_ALL_GPU_PGOOD

8

73 81 86 87 89

IN

PM_ALL_GPU_PGOOD

8

73 81 86 87 89

IN

PM_ALL_GPU_PGOOD

8

73 81 86 87 89

IN

R9990

100K

1/16W MF-LF

5%

402

2

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

OUT

8

73 81 86 87 89

A

8 7 5 4 2 1

Unused PGOOD signal

98 47 48 49 50 51 53 56 60 61

PP3V3_S0

6 7

12 16 17 18 19 20 22 23

25 26 28 32 35 36 39 40 41 45 71 72 79 82 83 84 87 88 89

66 89

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

71 89

MAKE_BASE=TRUE

NO STUFF

R9991

10K

1/16W MF-LF

1

5%

402

2

36

CPUIMVP_AXG_PGOOD

TP_DDRREG_PGOODTP_DDRREG_PGOOD

TP_P1V5S3RS0_RAMP_DONE

67

IN

66 89

IN

71 89

IN

PAGE TITLE

Power Sequencing EG/PCH S0

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=08/03/2010SYNC_MASTER=K91_MARY

DRAWING NUMBER

REVISION

BRANCH

PAGE

99 OF 132

SHEET

89 OF 101

SIZE

B

A

D

345678

2 1

CPU Signal Constraints

CPU_50S

CPU_55S

CPU_27P4S

LAYER

ALLOW ROUTE ON LAYER?

*

=27P4_OHM_SE

*

MINIMUM LINE WIDTH

=50_OHM_SE=50_OHM_SE

=55_OHM_SE=55_OHM_SE

=27P4_OHM_SE

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=50_OHM_SE =50_OHM_SE

=55_OHM_SE =55_OHM_SE

=27P4_OHM_SE =27P4_OHM_SE

DIFFPAIR PRIMARY GAP

7 MIL

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD*

=STANDARD=STANDARD

7 MIL

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

TABLE_SPACING_RULE_HEAD

*

LINE-TO-LINE SPACING

=STANDARD

8 MIL

20 MIL

=2:1_SPACING

25 MIL

WEIGHT

LAYER

D

SPACING_RULE_SET

CPU_AGTL

CPU_8MIL

CPU_COMP

CPU_ITP

CPU_VCCSENSE

Most CPU signals with impedance requirements are 50-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.

?

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

CPU_AGTL

CPU_VID

LAYER

TOP,BOTTOM

*

LINE-TO-LINE SPACING

=2x_DIELECTRIC

0.457 MM

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.8

PCI-Express

LAYER

PCIE_85D

ALLOW ROUTE ON LAYER?

=85_OHM_DIFF

CLK_PCIE_90D =90_OHM_DIFF

*

LINE-TO-LINE SPACING

=3X_DIELECTRIC

SPACING_RULE_SET

PCIE

CLK_PCIE

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=85_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

20 MIL

?

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

PCIE

MAXIMUM NECK LENGTH

=85_OHM_DIFF=85_OHM_DIFF

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF =85_OHM_DIFF*

=90_OHM_DIFF*

LINE-TO-LINE SPACING

=4X_DIELECTRIC

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=90_OHM_DIFF=90_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

C

B

A

8 7 5 4 2 1

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET

DMI_S2N DMI_S2N DMI_N2S DMI_N2S

FDI_DATA PCIE_85D

DMI_CLK100M

I125

I126

PM_SYNC

XDP_CPU_PWRGOOD XDP_BDRESET_L XDP_PRDY_L XDP_PREQ_l

CPU_SM_RCOMP CPU_COMP CPU_SM_RCOMP

I124

CPU_CATERR_L CPU_AGTL

I115

CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L

XDP_CLK_CPU XDP_CLK_CPU XDP_CLK_PCH XDP_CLK_PCH XDP_CLK_ITP XDP_CLK_ITP

PM_DPRSLPVR

CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP

XDP_TCK CPU_50S CPU_ITP XDP_TRST_L XDP_BPM XDP_BPM_L

(FSB_CPURST_L)

CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE

CPU_VCCSENSE CPU_VCCSENSE

I120

I121

I122

I123

PM_DPRSLPVR

PEG_R2D

PEG_D2R

NET_TYPE

PHYSICAL

PCIE_85D PCIE

PCIE_85D PCIE_85D PCIE

PCIE_85DFDI_DATA PCIE

CPU_50S CPU_50S

CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE

CPU_50S CPU_50S CPU_50S CPU_50S

CPU_27P4S CPU_27P4S CPU_27P4S CPU_50S CPU_ITPCPU_CFG CPU_50S CPU_ITPCPU_CFG CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S

CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE CPU_55S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S

CPU_50SXDP_TDI CPU_ITP CPU_50SXDP_TDO CPU_ITP CPU_50SXDP_TMS CPU_ITP

CPU_50S CPU_ITP CPU_50S CPU_ITP

CPU_55S CPU_50S

CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S

CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S

CPU_55S CPU_50S CPU_50S CPU_50S

PCIE_85D PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE

CPU_50S CPU_50S CPU_VID CPU_50S

SPACING

PCIEPCIE_85D PCIE

PCIE CPU_AGTL CPU_AGTL

CPU_AGTL PCIECPU_PECI CPU_AGTL CPU_AGTLPM_MEM_PWRGD

CPU_ITP CPU_ITP CPU_ITP CPU_ITP

CPU_COMP CPU_COMPCPU_SM_RCOMP

CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL

CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIECLK_PCIE_90D

CPU_8MIL CPU_AGTL CPU_COMP CPU_COMP CPU_COMPCPU_COMP CPU_COMP

CPU_ITPCPU_50S CPU_ITPCPU_50S

CPU_8MIL CPU_AGTL

CPU_VCCSENSE

CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE

CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL

PCIEPCIE_85D PCIEPCIE_85D PCIE

PCIEPCIE_85D CPU_VID

CPU_VID

DMI_S2N_P<3:0> DMI_S2N_N<3:0> DMI_N2S_P<3:0> DMI_N2S_N<3:0>

FDI_DATA_P<7:0> FDI_DATA_N<7:0>

FDI_FSYNC<1..0>

FDI_LSYNC<1..0>

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

FDI_INT CPU_PECI PM_SYNC PM_MEM_PWRGD

XDP_CPU_PWRGD XDP_DBRESET_L XDP_CPU_PRDY_L XDP_CPU_PREQ_L

CPU_SM_RCOMP0 CPU_SM_RCOMP1 CPU_SM_RCOMP2 CPU_CFG<11..0> CPU_CFG<17..16> CPU_CATERR_L CPU_PROC_SEL_L TP_CPU_VTT_SELECT

CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L

ITPCPU_CLK100M_P ITPCPU_CLK100M_N ITPXDP_CLK100M_P ITPXDP_CLK100M_N XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N CPU_PSI_L

PM_DPRSLPVR CPU_PEG_COMP CPU_PEG_RBIAS

CPU_COMP3

CPU_COMP2

CPU_COMP1

CPU_COMP0

XDP_CPU_TDI

XDP_CPU_TDO

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_BPM_L<3..0>

XDP_BPM_L<7..4>

XDP_CPURST_L

CPU_VID<6..0> CPUIMVP_IMON

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

CPU_VCC_VALSENSE_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_AXG_VALSENSE_N

GFX_VID<6..0>

GFX_DPRSLPVR GFX_VR_EN GFXIMVP_IMON

PEG_R2D_P<7..0>

PEG_R2D_N<7..0>

PEG_R2D_C_P<7..0>

PEG_R2D_C_N<7..0>

PEG_D2R_P<7..0>

PEG_D2R_N<7..0>

PEG_D2R_C_P<7..0>

PEG_D2R_C_N<7..0>

CPU_VIDSOUT

CPU_VIDSCLK

CPU_VIDALERT_L

36

6 9

17

6 9

17

9

17

9

17

6 9

17

6 9

17

6 9

17

6 9

17

10 16

6 9

17

10 19 44

10 17

10 17 29

23

10 23 25

10 23

9

23

9

23

10

10 17

8

10 45 67

10 19 23

10 19

10 16

16 23

23

9

10 23

23

8

12 67

12 69

12 67

12

8

73

8

73

8

73

8

73

8

73

12 67

SYNC_MASTER=K92_MLB

PAGE TITLE

CPU Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=08/09/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

100 OF 132

SHEET

90 OF 101

SIZE

D

C

B

A

D

345678

2 1

Memory Bus Constraints

LAYER

ALLOW ROUTE ON LAYER?

MEM_37S

MEM_40S

* =72_OHM_DIFF

=50_OHM_SE =50_OHM_SE =50_OHM_SE

* =85_OHM_DIFF

*

LINE-TO-LINE SPACING

=4:1_SPACING

=3:1_SPACING

=2.5:1_SPACING

=1.5:1_SPACING

=3:1_SPACING

=1.5:1_SPACING

=3:1_SPACING

LAYER

*

D

MEM_72D

MEM_50S

MEM_85D

SPACING_RULE_SET

MEM_CLK2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

MEM_CMD2CMD

MEM_CMD2MEM

MEM_DATA2DATA

MEM_DATA2MEM

MEM_DQS2MEM

MEM_2OTHER

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

C

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CTRL

MEM_CTRL MEM_CTRL

MEM_CTRL

MEM_CTRL MEM_DATA

MEM_CTRL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DQS

MEM_DQS MEM_CMD

MEM_DQS

DDR3:

DQ/DM signals should be matched within 0.508mm of associated DQS pair. DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement. DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm]. CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm. CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs.

B

A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs. DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric. Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm.

SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CMD

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_DATA

MEM_DQS

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=37_OHM_SE =37_OHM_SE =37_OHM_SE=37_OHM_SE

=40_OHM_SE=40_OHM_SE =40_OHM_SE=40_OHM_SE

=72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

=85_OHM_DIFF

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CMD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DATA

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

25 MILS

AREA_TYPE

=85_OHM_DIFF

*

WEIGHT

SPACING_RULE_SET

MEM_CLK2MEM

SPACING_RULE_SET

MEM_CTRL2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

SPACING_RULE_SET

MEM_DQS2MEM

Need to support MEM_*-style wildcards!

MAXIMUM NECK LENGTH

=50_OHM_SE

=85_OHM_DIFF

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

* *

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=72_OHM_DIFF =72_OHM_DIFF

=STANDARD* =STANDARD

=85_OHM_DIFF =85_OHM_DIFF

AREA_TYPE

*

**

SPACING_RULE_SET

MEM_CMD2MEM

MEM_CMD2CMD

MEM_CMD2MEM

SPACING_RULE_SET

MEM_DATA2MEM

MEM_DATA2DATA

MEM_DATA2MEM

SPACING_RULE_SET

MEM_2OTHER

**

MEM_2OTHER

**

=STANDARD=STANDARD*

=STANDARD* =STANDARD

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK MEM_A_CLK

MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL

MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD

MEM_A_DQ_BYTE0 MEM_50S MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_50S MEM_A_DQ_BYTE3 MEM_50S MEM_A_DQ_BYTE4 MEM_50S MEM_A_DQ_BYTE5 MEM_50S MEM_A_DQ_BYTE6 MEM_50S MEM_A_DQ_BYTE7 MEM_50S

MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7

MEM_B_CLK MEM_B_CLK

MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL

MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD

MEM_B_DQ_BYTE0 MEM_50S MEM_B_DQ_BYTE1 MEM_50S MEM_B_DQ_BYTE2 MEM_50S MEM_B_DQ_BYTE3 MEM_50S MEM_B_DQ_BYTE4 MEM_50S MEM_B_DQ_BYTE5 MEM_50S MEM_B_DQ_BYTE6 MEM_50S MEM_B_DQ_BYTE7 MEM_50S

NET_TYPE

PHYSICAL

MEM_72D MEM_CLK MEM_72D MEM_CLK

MEM_37S MEM_37S MEM_37S

MEM_40S MEM_CMD

MEM_40S MEM_40S MEM_40S

MEM_50S

MEM_85D MEM_85D MEM_85D MEM_85D

MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D

MEM_85D

MEM_85D MEM_85D MEM_85D

MEM_72D MEM_CLK MEM_72D MEM_CLK

MEM_37S MEM_37S MEM_37S

MEM_40S MEM_CMD

MEM_40S MEM_CMD MEM_40S MEM_CMD MEM_40S MEM_CMD

MEM_CTRL MEM_CTRL MEM_CTRL

MEM_CMDMEM_40S MEM_CMD MEM_CMD MEM_CMD

MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA

MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQSMEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQSMEM_85D MEM_DQS MEM_DQSMEM_85D MEM_DQS MEM_DQS MEM_DQS

MEM_CTRL MEM_CTRL MEM_CTRL

MEM_CMDMEM_40S

MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA

SPACING

MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0>

MEM_A_CKE<3..0> MEM_A_CS_L<3..0> MEM_A_ODT<3..0>

MEM_A_A<15..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56>

MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0>

MEM_B_CKE<3..0> MEM_B_CS_L<3..0> MEM_B_ODT<3..0>

MEM_B_A<15..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56>

6

11 26

6

11 26

6

11 26

6

11 26

6

11 26

6

11 26

6

11 26

6

11 26

6

11 26

6

11 26

6

11 27

6

11 27

6

11 27

6

11 27

6

11 26 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 26 27

6

11 26 27

6

11 27

6

11 27

6

11 28

6

11 28

6

11 28

6

11 28

6

11 28

6

11 28

6

11 28

6

11 28

6

11 28

6

11 28

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27 28

6

11 27

6

11 27

6

11 27

D

C

B

MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6

A

MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7

MEM_85D MEM_85D MEM_85D MEM_85D

MEM_85D MEM_85D

MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D

MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQSMEM_85D MEM_DQS MEM_DQS MEM_DQSMEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS

8 7 5 4 2 1

MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

36

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27

6

11 27 28

6

11 27 28

6

11 27

6

11 27

SYNC_MASTER=K18_MLB

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

101 OF 132

SHEET

91 OF 101

SIZE

A

D

Digital Video Signal Constraints

LAYER

DP_85D

ALLOW ROUTE ON LAYER?

=90_OHM_DIFF

*

LVDS_85D

SPACING_RULE_SET

DISPLAYPORT

LVDS

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

D

LAYER

ISL3,ISL4,ISL9,ISL10

LINE-TO-LINE SPACING

=4:1_SPACING

MINIMUM LINE WIDTH

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

=90_OHM_DIFF

SPACING_RULE_SET

DISPLAYPORT

LVDS

MAXIMUM NECK LENGTH

=90_OHM_DIFF

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=90_OHM_DIFF

=90_OHM_DIFF* =90_OHM_DIFF

LINE-TO-LINE SPACING

=4:1_SPACING

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=90_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

DP_AUX_CH DP_AUX_CH

LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3

NET_TYPE

PHYSICAL

DP_85D DP_85D

LVDS_85D LVDS LVDS_85D LVDS LVDS_85D LVDS LVDS_85D LVDS

SPACING

DISPLAYPORT DISPLAYPORT

LVDSLVDS_85D LVDSLVDS_85D

345678

DP_IG_AUX_CH_P DP_IG_AUX_CH_N

LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0> NC_LVDS_IG_A_DATAP<3> NC_LVDS_IG_A_DATAN<3>

8

18 87

8

17 83

18

2 1

D

SATA Interface Constraints

ALLOW ROUTE ON LAYER?

=90_OHM_DIFF

* =90_OHM_DIFF =90_OHM_DIFF

*

=37_OHM_SE

*

=50_OHM_SE

LINE-TO-LINE SPACING

=5:1_SPACING

*

SATA_90D

SATA_37SE

SATA_50SE

SPACING_RULE_SET

SATA

SATA_ICOMP

LAYER

ISL3,ISL4,ISL9,ISL10

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

MINIMUM LINE WIDTH

=90_OHM_DIFF =90_OHM_DIFF

=37_OHM_SE =37_OHM_SE

=50_OHM_SE =50_OHM_SE

15 MIL

C

USB 2.0 Interface Constraints

LAYER

PCH_USB_RBIAS

USB_85D

SPACING_RULE_SET

USB

USB_RBIAS

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

LAYER

ISL3,ISL4,ISL9,ISL10

*

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

=STANDARD

=85_OHM_DIFF

LINE-TO-LINE SPACING

=4:1_SPACING

15 MIL

=STANDARD

=85_OHM_DIFF

B

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

SPACING_RULE_SET

SATA

MINIMUM NECK WIDTH

=STANDARD

=85_OHM_DIFF

SPACING_RULE_SET

USB

MAXIMUM NECK LENGTH

=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

=STANDARD

=85_OHM_DIFF

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=37_OHM_SE

=50_OHM_SE =50_OHM_SE

LINE-TO-LINE SPACING

=5:1_SPACING

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

LINE-TO-LINE SPACING

=4:1_SPACING

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=37_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=85_OHM_DIFF=85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LVDS_IG_B_DATA LVDS_IG_B_DATA

SATA_HDD_R2D

I218

I219

SATA_HDD_D2R SATA

PCH_SATA3_ICOMP

I213

PCH_SATA_ICOMP USB_HUB1_UP

USB_HUB2_UP

USB_EXTA

USB_EXTB

USB_EXTC

USB_CAMERA

USB_BT

USB_TPAD

USB_IR

USB_T29A

I214

I215

SATA_90D SATASATA_HDD_R2D

SATA_90D SATA SATA_90D SATA

SATA_90D

SATA_90D SATA_90D SATA_90DSATA_HDD_D2R

SATA_50SE SATA_37SE USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D PCH_USB_RBIASPCH_USB_RBIAS USB_85D USB_85D

LVDSLVDS_85D LVDSLVDS_85D

SATASATA_90D

SATASATA_90D SATA

SATA SATA SATASATA_90D SATASATA_90DSATA_ODD_R2D SATASATA_90D SATASATA_90DSATA_ODD_R2D SATASATA_90D SATASATA_90DSATA_ODD_D2R SATASATA_90D SATASATA_90DSATA_ODD_D2R SATASATA_90D

SATA_ICOMP SATA_ICOMP USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB_RBIAS USB USB

LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_N<2..0> SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N

SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N

SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P

SATA_ODD_D2R_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N

PCH_SATA3COMP

PCH_SATAICOMP

USB_HUB1_UP_P

USB_HUB1_UP_N

USB_HUB2_UP_P

USB_HUB2_UP_N

USB_EXTA_P

USB_EXTA_N

USB_EXTB_P

USB_EXTB_N

USB_EXTC_P

USB_EXTC_N

USB_CAMERA_CONN_P

USB_CAMERA_CONN_N

USB_BT_P

USB_BT_N

USB_TPAD_P

USB_TPAD_N

USB_IR_P

USB_IR_N

PCH_USB_RBIAS

USB_T29A_P

USB_T29A_N

18 87

16 41

6

41

16 41

6

16 41

6

16 41

6

16

18 24

24 42

8

6

24 31

24 52

24 43

18

8

41

C

24

31

24

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K92_MLB

PAGE TITLE

PCH Constraints 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=08/09/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

102 OF 132

SHEET

92 OF 101

SIZE

A

D

LPC Bus Constraints

LAYER

LPC_50S

ALLOW ROUTE ON LAYER?

=50_OHM_SE

*

CLK_LPC_50S

*

LINE-TO-LINE SPACING

ALLOW ROUTE ON LAYER?

SPACING_RULE_SET

LAYER

LPC

CLK_LPC

D

SMBus Interface Constraints

LAYER

SMB_50S

*

LINE-TO-LINE SPACING

=2x_DIELECTRIC

SPACING_RULE_SET

SMB

LAYER

MINIMUM LINE WIDTH

=50_OHM_SE =50_OHM_SE=50_OHM_SE

WEIGHT

6 MIL

8 MIL

MINIMUM LINE WIDTH

WEIGHT

HD Audio Interface Constraints

HDA_50S

SPACING_RULE_SET

HDA

LAYER

ALLOW ROUTE ON LAYER?

=50_OHM_SE

* =STANDARD

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

MINIMUM LINE WIDTH

=50_OHM_SE =50_OHM_SE =50_OHM_SE

WEIGHT

SIO Signal Constraints

CLK_SLOW_55S

LAYER

ALLOW ROUTE ON LAYER?

* =STANDARD

MINIMUM LINE WIDTH

C

SPACING_RULE_SET

LAYER

CLK_SLOW

SPI Interface Constraints

LAYER

SPI_55S

SPACING_RULE_SET

SPI

LAYER

LINE-TO-LINE SPACING

*

* =STANDARD =STANDARD

*

8 MIL

ALLOW ROUTE ON LAYER?

=55_OHM_SE =55_OHM_SE =55_OHM_SE

LINE-TO-LINE SPACING

8 MIL

WEIGHT

MINIMUM LINE WIDTH

=55_OHM_SE

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

=50_OHM_SE=50_OHM_SE

=50_OHM_SE

MINIMUM NECK WIDTH

=50_OHM_SE

MINIMUM NECK WIDTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=50_OHM_SE

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE

MAXIMUM NECK LENGTH

=55_OHM_SE

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=STANDARD* =STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

LPC_AD LPC_FRAME_L LPC_RESET_L

PCH_LPC_CLK0

SMBUS_PCH_CLK SMBUS_PCH_DATA SMBUS_PCH_0_CLK SMBUS_PCH_0_DATA SMBUS_PCH_1_CLK SMBUS_PCH_1_DATA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

SPI_CLK

SPI_MOSI

SPI_MISO SPI_CS0

PCIE_ENET_R2D

PCIE_ENET_D2R

NET_TYPE

PHYSICAL

LPC_50S LPC_50S LPC_50S

CLK_LPC_50S CLK_LPC_50S CLK_LPC_50S

SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S

HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S

SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S

PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D PCIE PCIE_85D

PCIE_85D PCIE

PCIE_AP_R2D

PCIE_85D PCIE

PCIE_AP_D2R

PCIE_85D

PCIE_FW_R2D

PCIE_85D

PCIE_FW_D2R

PCIE_85D PCIE

SPACING

LPC LPC LPC

CLK_LPC CLK_LPC CLK_LPC

SMB SMB SMB SMB SMB SMB

HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA

SPI SPI SPI SPI SPI SPI SPI

PCIE PCIEPCIE_85D

PCIEPCIE_85D PCIEPCIE_85D PCIEPCIE_85D PCIEPCIE_85D

PCIE PCIEPCIE_85D PCIE PCIEPCIE_85D PCIEPCIE_85D PCIEPCIE_85D PCIEPCIE_85D

345678

LPC_AD<3..0> LPC_FRAME_L LPCPLUS_RESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS

SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA

HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 AUD_SDI_R HDA_SDOUT HDA_SDOUT_R

SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L

PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N

PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N

PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N

6

16 44 46 87

6

16 44 46 87

6

25 46 87

18 25

25 44

6

25 46

16 23 26 28 30 41 47 61 88

16 47

16 56

16

16 56

16

16 56

56

16 56

16

16 46

46

16 46

46

16 46

46

36

16 36

36

6

31

6

31

16 31

6

16 31

6

16 31

38

16 38

38

2 1

D

C

I253

B

I254

PCIE_CLK100M_T29_

I262

I261

I255

I257

I256

I259

I258

I260

PCIE_CLK100M_ENET

PCIE_CLK100M_AP

PCIE_CLK100M_FW

PCIE_CLK100M_EXCARD

PCIE_T29_R2D PCIE

I263

PCIE_T29_R2D PCIEPCIE_85D

I264

PCIE_T29_R2D PCIEPCIE_85D

I265

PCIE_T29_R2D PCIE_85D PCIE

I267

PCIE_T29_D2R PCIEPCIE_85D

A

I266

PCIE_T29_D2R PCIEPCIE_85D

I268

PCIE_T29_D2R PCIEPCIE_85D

I270

PCIE_T29_D2R PCIEPCIE_85D

I269

CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE

CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CPU_50S CPU_50S

CLK_PCIE_90D CLK_PCIEPCIE_CLK100M CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIECLK_PCIE_90D CLK_PCIE

CLK_PCIE CLK_PCIE

CLK_PCIE

CLK_PCIECLK_PCIE_90D CLK_PCIECLK_PCIE_90D CLK_PCIECLK_PCIE_90D

PCIE_85D

8 7 5 4 2 1

PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N PCIE_CLK100M_T29_P PCIE_CLK100M_T29_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK PCH_CLK33M_PCIIN

PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N NC_PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARD_N

PCIE_T29_R2D_C_P<3..0> PCIE_T29_R2D_C_N<3..0> PCIE_T29_R2D_P<3..0> PCIE_T29_R2D_N<3..0> PCIE_T29_D2R_P<3..0> PCIE_T29_D2R_N<3..0> PCIE_T29_D2R_C_P<3..0> PCIE_T29_D2R_C_N<3..0>

36

16

16 33

16

16 25

16 73

16 36

16 31

16 38

8 9

33

8 9

33

B

8

16

8

16

33

SYNC_MASTER=K92_MLB

PAGE TITLE

PCH Constraints 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=08/09/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

103 OF 132

SHEET

93 OF 101

SIZE

A

D

345678

2 1

CAESAR IV (Ethernet) Constraints

LAYER

ENET_50S

SPACING_RULE_SET

ENET_3X

LAYER

SOURCE: Broadcom 5764-DS04-RDS Page 38

SPACING_RULE_SET

LAYER

D

SOURCE: Attila Farkas Email - 8/2/10

ALLOW ROUTE ON LAYER?

*

LINE-TO-LINE SPACING

*

LINE-TO-LINE SPACING

* ?

MINIMUM LINE WIDTH

=3:1_SPACING

=3X_DIELECTRICENET_CR

CAESAR IV (Ethernet PHY) Constraints

ENET_100D

SPACING_RULE_SET

ENET_MDI

LAYER

*

ALLOW ROUTE ON LAYER?

=100_OHM_DIFF

LINE-TO-LINE SPACING

SOURCE: Broadcom 5764-DS04-RDS Page 38

C

FireWire Interface Constraints

LAYER

FW_110D

SPACING_RULE_SET

FW_TP

LAYER

*

ALLOW ROUTE ON LAYER?

=110_OHM_DIFF

LINE-TO-LINE SPACING

MINIMUM LINE WIDTH

=100_OHM_DIFF

0.6 MM

MINIMUM LINE WIDTH

=110_OHM_DIFF =110_OHM_DIFF

=3:1_SPACING

MINIMUM NECK WIDTH

=50_OHM_SE =50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

=50_OHM_SE

MINIMUM NECK WIDTH

=100_OHM_DIFF

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=100_OHM_DIFF

MAXIMUM NECK LENGTH

=110_OHM_DIFF

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF

DIFFPAIR PRIMARY GAP

=110_OHM_DIFF =110_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD=50_OHM_SE

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Ethernet Net Properties

ELECTRICAL_CONSTRAINT_SET

ENET_MDI

CR_DATA_A0

I166

CR_DATA_A0

I167

CR_CLK

I168

CR_DATA_A0

I169

CR_DATA_A0

I170

CR_CLK

I171

CR_CLK

I172

PHYSICAL

ENET_50S

ENET_100D

ENET_50S

FireWire Net Properties

FW_110D

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

FW_P0_TPA

I158

FW_P0_TPA

I159

FW_P0_TPB

I160

FW_P0_TPB

I161

FW_P1_TPA

I162

FW_P1_TPA

I163

FW_P1_TPB

I164

FW_P1_TPB

I165

NET_TYPE

SPACING

ENET_3X

ENET_MDI

ENET_CR

SPACING

FW_TP

BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALO

ENET_RESET_L

ENET_MDI_P<3..0> ENET_MDI_N<3..0>

SDCONN_DATA_R<7..0> SDCONN_CMD_R SDCONN_CLK_R SDCONN_DATA<7..0> SDCONN_CMD SDCONN_CLK SDCONN_CLK_R_L

NC_FW0_TPAP NC_FW0_TPAN NC_FW0_TPBP NC_FW0_TPBN FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N

32

32 36

36 37

32

32 36

6

38 40

6

38 40

D

C

Port 2 Not Used

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K91_ERIC SYNC_DATE=08/03/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Ethernet/FW Constraints

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

104 OF 132

SHEET

94 OF 101

DisplayPort Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

T29 I2C Signal Constraints

LAYER

ALLOW ROUTE ON LAYER?

T29_I2C_55S

SPACING_RULE_SET

LAYER

T29_I2C =2x_DIELECTRIC

D

T29 SPI Signal Constraints

LAYER

T29_SPI_55S

SPACING_RULE_SET

LAYER

T29_SPI =2x_DIELECTRIC

LINE-TO-LINE SPACING

*

ALLOW ROUTE ON LAYER?

=55_OHM_SE =55_OHM_SE

LINE-TO-LINE SPACING

*

MINIMUM LINE WIDTH

=55_OHM_SE

WEIGHT

?

MINIMUM LINE WIDTH

=55_OHM_SE

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

T29/DP Connector Signal Constraints

*

ALLOW ROUTE ON LAYER?

=80_OHM_DIFF

=100_OHM_DIFF

LINE-TO-LINE SPACING

=5x_DIELECTRIC

T29DP_80D

T29DP_100D

SPACING_RULE_SET

T29DP

LAYER

SOURCE: Bill Cornelius’s T29 Routing Notes

MINIMUM LINE WIDTH

=80_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

=80_OHM_DIFF

=100_OHM_DIFF

SPACING_RULE_SET

T29DP

MAXIMUM NECK LENGTH

TOP,BOTTOM

C

B

T29 IC Net Properties

ELECTRICAL_CONSTRAINT_SET

DP_T29SNK0_ML DP_T29SNK0_ML

DP_T29SNK0_AUXCH DP_T29SNK0_AUXCH

DP_T29SNK1_ML DP_T29SNK1_ML

DP_T29SNK1_AUXCH DP_T29SNK1_AUXCH

A

T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L

PHYSICAL

DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D

DP_85D DP_85D DP_85D DP_85D

T29_I2C_55S T29_I2C_55S

T29_SPI_55ST29_SPI_CLK T29_SPI_55S T29_SPI_55S T29_SPI_55S

T29DP_80D T29DP_80D T29DP_100D T29DP_100D

NET_TYPE

SPACING

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

T29_I2C T29_I2C

T29_SPI T29_SPI T29_SPI T29_SPI

T29DP T29DP T29DP T29DP

DP_T29SNK0_ML_C_P<3..0> DP_T29SNK0_ML_C_N<3..0> DP_T29SNK0_ML_P<3..0> DP_T29SNK0_ML_N<3..0> DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N

DP_T29SNK1_ML_C_P<3..0> DP_T29SNK1_ML_C_N<3..0> DP_T29SNK1_ML_P<3..0> DP_T29SNK1_ML_N<3..0> DP_T29SNK1_AUXCH_C_P DP_T29SNK1_AUXCH_C_N DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_N

DP_T29SRC_ML_C_P<3..0> DP_T29SRC_ML_C_N<3..0> DP_T29SRC_AUXCH_C_P DP_T29SRC_AUXCH_C_N

I2C_T29_SCL I2C_T29_SDA

T29_SPI_CLK T29_SPI_MOSI T29_SPI_MISO T29_SPI_CS_L

T29_R2D_C_P<3..0> T29_R2D_C_N<3..0> T29_D2R_P<3..0> T29_D2R_N<3..0>

8 7 5 4 2 1

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=55_OHM_SE

=80_OHM_DIFF

LAYER

6

33 47 84

33

6 8

=STANDARD

=STANDARD=STANDARD*

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

DIFFPAIR PRIMARY GAP

=STANDARD*

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=7x_DIELECTRIC

33 78

33

33 78

33

33 78

33

33 78

33

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=80_OHM_DIFF=80_OHM_DIFF*

=100_OHM_DIFF=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

Only used on hosts supporting T29 video-in

33 84

T29/DP Net Properties

ELECTRICAL_CONSTRAINT_SET

T29_R2D0 T29_R2D0 T29_R2D1 T29_R2D1

T29_D2R0 T29_D2R0 T29_D2R1 T29_D2R1

DP_SDRVA_ML_EVEN DP_SDRVA_ML_EVEN DP_SDRVA_ML_ODD DP_SDRVA_ML_ODD DP_SDRVA_AUXCH DP_SDRVA_AUXCH

T29_R2D2 T29_R2D2 T29_R2D3 T29_R2D3

T29_D2R2 T29_D2R2 T29_D2R3 T29_D2R3

DP_SDRVB_ML_EVEN DP_SDRVB_ML_EVEN DP_SDRVB_ML_ODD DP_SDRVB_ML_ODD DP_SDRVB_AUXCH DP_SDRVB_AUXCH

PHYSICAL

T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D

T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D

T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D

T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D T29DP_100D

T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D

T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D T29DP_80D

NET_TYPE

T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP

T29DP T29DP T29DP T29DP T29DP T29DP

T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP T29DP

T29DP T29DP T29DP T29DP T29DP T29DP

SPACING

345678

T29_R2D_P<0> T29_R2D_N<0> T29_R2D_P<1> T29_R2D_N<1> T29_R2D_C_F_P<1..0> T29_R2D_C_F_N<1..0> T29_D2R_C_P<0> T29_D2R_C_N<0> T29_D2R_C_P<1> T29_D2R_C_N<1> T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N

DP_SDRVA_ML_C_P<3..0> DP_SDRVA_ML_C_N<3..0> DP_SDRVA_ML_R_P<3..0> DP_SDRVA_ML_R_N<3..0> DP_SDRVA_ML_P<2..0:2> DP_SDRVA_ML_N<2..0:2> DP_SDRVA_ML_P<3..1:2> DP_SDRVA_ML_N<3..1:2> DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_N DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_N

T29DPA_ML_P<3..0> T29DPA_ML_N<3..0> T29DPA_ML_C_P<3..0> T29DPA_ML_C_N<3..0> DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_N

T29_R2D_P<2> T29_R2D_N<2> T29_R2D_P<3> T29_R2D_N<3> T29_R2D_C_F_P<3..2> T29_R2D_C_F_N<3..2> T29_D2R_C_P<2> T29_D2R_C_N<2> T29_D2R_C_P<3> T29_D2R_C_N<3> T29DPB_D2R3_AUXCH_P T29DPB_D2R3_AUXCH_N

DP_SDRVB_ML_C_P<3..0> DP_SDRVB_ML_C_N<3..0> DP_SDRVB_ML_R_P<3..0> DP_SDRVB_ML_R_N<3..0> DP_SDRVB_ML_P<2..0:2> DP_SDRVB_ML_N<2..0:2> DP_SDRVB_ML_P<3..1:2> DP_SDRVB_ML_N<3..1:2> DP_SDRVB_AUXCH_P DP_SDRVB_AUXCH_N DP_SDRVB_AUXCH_C_P DP_SDRVB_AUXCH_C_N

T29DPB_ML_P<3..0> T29DPB_ML_N<3..0> T29DPB_ML_C_P<3..0> T29DPB_ML_C_N<3..0> DP_B_EXT_AUXCH_P DP_B_EXT_AUXCH_N

36

6

84

6

84

6

84

6

84

6

84 85

6

84 85

6

84 85

6

84 85

6

85

6

85

6

84

6

84

6

84 95

6

84 95

84

6

84 85

6

84 85

Only used on dual-port hosts.

95

SYNC_MASTER=T29_REF

PAGE TITLE

2 1

SYNC_DATE=10/16/2010

T29 Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING NUMBER

REVISION

BRANCH

PAGE

105 OF 132

SHEET

95 OF 101

SIZE

D

C

B

A

D

345678

2 1

D

C

1TO1_DIFFPAIR

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

=STANDARD=STANDARD

MINIMUM NECK WIDTH

=STANDARD =STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

CHGR_CSI

CHGR_CSO

1TO1_DIFFPAIR 1TO1_DIFFPAIR

PHYSICAL

NET_TYPE

SPACING

SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB

SPACING

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

CHGR_CSI_P CHGR_CSI_N

CHGR_CSO_P CHGR_CSO_N

6

31 44 47 53 54

6

31 44 47 53 54

44 47 50

6

31 44 47 50 79

6

31 44 47 50 79

6

44 47 62 63

6

44 47 62 63

44 47

100

44 47

100

63

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=K18_MLB

PAGE TITLE

SMC Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

106 OF 132

SHEET

96 OF 101

GDDR5 Frame Buffer Signal Constraints

LAYER

GDDR5_45R50SE

GDDR5_45SE =45_OHM_SE

GDDR5_80D

SPACING_RULE_SET

LAYER

GDDR5_CLK

GDDR5_CMD

D

GDDR5_DATA

GDDR5_EDC

ALLOW ROUTE ON LAYER?

=50_OHM_SE

* =STANDARD

=45_OHM_SE

* =STANDARD =STANDARD

=80_OHM_DIFF

*

LINE-TO-LINE SPACING

=5x_DIELECTRIC

*

=2x_DIELECTRIC

=3x_DIELECTRIC

*

=7x_DIELECTRIC

*

MINIMUM LINE WIDTH

=50_OHM_SE

MINIMUM NECK WIDTH

=50_OHM_SE

MAXIMUM NECK LENGTH

12.7 MM

=45_OHM_SE =45_OHM_SE

WEIGHT

=80_OHM_DIFF=80_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

=80_OHM_DIFF

Digital Video Signal Constraints

*

ALLOW ROUTE ON LAYER?

=85_OHM_DIFF

LINE-TO-LINE SPACING

=3x_DIELECTRIC

LAYER

DP_85D

LVDS_85D

SPACING_RULE_SET

LAYER

DISPLAYPORT

LVDS

LVDS intra-pair matching should be 0.127 mm. Pairs should be within 0.508mm of entire channel. DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm. DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm. Max length of LVDS/DisplayPort/TMDS traces: 13 inches. SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

=85_OHM_DIFF

SPACING_RULE_SET

DISPLAYPORT

LVDS

LAYER

TOP,BOTTOM

LINE-TO-LINE SPACING

=4x_DIELECTRIC

C

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=80_OHM_DIFF

DIFFPAIR PRIMARY GAP

=80_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

GDDR5 FB A Net Properties

ELECTRICAL_CONSTRAINT_SET

FB_A0_CLK GDDR5_80D GDDR5_CLK FB_A0_CLK GDDR5_80D GDDR5_CLK FB_A1_CLK GDDR5_CLKGDDR5_80D FB_A1_CLK GDDR5_CLKGDDR5_80D FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD GDDR5_CMD FB_A1_CMD GDDR5_CMD FB_A0_CMD GDDR5_CMD FB_A1_CMD GDDR5_CMD FB_A0_CMD FB_A1_CMD FB_A0_CMD FB_A1_CMD FB_A0_EDC0 FB_A0_EDC1

I293

FB_A0_EDC2

I294

FB_A0_EDC3

I295

FB_A1_EDC0

I296

FB_A1_EDC1

I297

FB_A1_EDC2

I298

FB_A1_EDC3 FB_A0_DBI_L0 FB_A0_DBI_L1

I299

FB_A0_DBI_L2

I300

FB_A0_DBI_L3

I301

FB_A1_DBI_L0

I302

FB_A1_DBI_L1

I303

FB_A1_DBI_L2

I304

FB_A1_DBI_L3 FB_A0_WCLK0 FB_A0_WCLK0 FB_A0_WCLK1 FB_A0_WCLK1 FB_A1_WCLK0 FB_A1_WCLK0 FB_A1_WCLK1 FB_A1_WCLK1 FB_A0_DQ_BYTE0 FB_A0_DQ_BYTE1 FB_A0_DQ_BYTE2 FB_A0_DQ_BYTE3 FB_A1_DQ_BYTE0 FB_A1_DQ_BYTE1 FB_A1_DQ_BYTE2 FB_A1_DQ_BYTE3 FB_AB_RESET

PHYSICAL

GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_DATA

GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_45SE GDDR5_DATA GDDR5_80D GDDR5_80D GDDR5_CMD GDDR5_80D GDDR5_CMD GDDR5_80D GDDR5_CMD GDDR5_80D GDDR5_CMD GDDR5_80D GDDR5_CMD GDDR5_80D GDDR5_CMD GDDR5_80D GDDR5_CMD GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_DATA GDDR5_45R50SE

NET_TYPE

GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD

GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC

GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE

GDDR5_DATA

GDDR5_CMD

GDDR5_DATA GDDR5_DATA GDDR5_DATA GDDR5_DATA

GDDR5_CMD

FB_A0_CLK_P FB_A0_CLK_N FB_A1_CLK_P FB_A1_CLK_N FB_A0_A<8..0> FB_A1_A<8..0> FB_A0_ABI_L FB_A1_ABI_L FB_A0_RAS_L FB_A1_RAS_L FB_A0_CAS_L FB_A1_CAS_L FB_A0_WE_L FB_A1_WE_L FB_A0_CKE_L FB_A1_CKE_L FB_A0_CS_L FB_A1_CS_L FB_A0_EDC<0> FB_A0_EDC<1> FB_A0_EDC<2> FB_A0_EDC<3> FB_A1_EDC<0> FB_A1_EDC<1> FB_A1_EDC<2> FB_A1_EDC<3> FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<2> FB_A0_DBI_L<3> FB_A1_DBI_L<0> FB_A1_DBI_L<1> FB_A1_DBI_L<2> FB_A1_DBI_L<3> FB_A0_WCLK_P<0> FB_A0_WCLK_N<0> FB_A0_WCLK_P<1> FB_A0_WCLK_N<1> FB_A1_WCLK_P<0> FB_A1_WCLK_N<0> FB_A1_WCLK_P<1> FB_A1_WCLK_N<1> FB_A0_DQ<7..0> FB_A0_DQ<15..8> FB_A0_DQ<23..16> FB_A0_DQ<31..24> FB_A1_DQ<7..0> FB_A1_DQ<15..8> FB_A1_DQ<23..16> FB_A1_DQ<31..24> FB_RESET_L

345678

GDDR5 FB B Net Properties

ELECTRICAL_CONSTRAINT_SET

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

6

75 76

75 76 77

FB_B0_CLK GDDR5_CLKGDDR5_80D FB_B0_CLK FB_B1_CLK FB_B1_CLK FB_B0_CMD FB_B1_CMD GDDR5_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_CMD FB_B1_CMD FB_B0_EDC0 GDDR5_45SE FB_B0_EDC1

I305

FB_B0_EDC2

I306

FB_B0_EDC3

I307

FB_B1_EDC0 GDDR5_45SE

I310

FB_B1_EDC1 GDDR5_45SE

I309

FB_B1_EDC2

I308

FB_B1_EDC3 FB_B0_DBI_L0 FB_B0_DBI_L1

I311

FB_B0_DBI_L2

I312

FB_B0_DBI_L3

I313

FB_B1_DBI_L0

I316

FB_B1_DBI_L1

I315

FB_B1_DBI_L2

I314

FB_B1_DBI_L3 FB_B0_WCLK0 FB_B0_WCLK0 FB_B0_WCLK1 FB_B0_WCLK1 FB_B1_WCLK0 FB_B1_WCLK0 FB_B1_WCLK1 FB_B1_WCLK1 FB_B0_DQ_BYTE0 FB_B0_DQ_BYTE1 FB_B0_DQ_BYTE2 FB_B0_DQ_BYTE3 FB_B1_DQ_BYTE0 FB_B1_DQ_BYTE1 FB_B1_DQ_BYTE2 FB_B1_DQ_BYTE3

NET_TYPE

PHYSICAL

GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE GDDR5_45R50SE

GDDR5_45SE GDDR5_45SE GDDR5_45SE

GDDR5_45SE GDDR5_45SE GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_DATA GDDR5_45SE GDDR5_DATA

GDDR5_45SE GDDR5_DATA

GDDR5_80D GDDR5_80D

GDDR5_45SE GDDR5_45SE

SPACINGSPACING

GDDR5_CLKGDDR5_80D GDDR5_CLKGDDR5_80D GDDR5_CLKGDDR5_80D GDDR5_CMD

GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_CMD GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC GDDR5_EDC

GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE

GDDR5_DATAGDDR5_45SE GDDR5_CMD GDDR5_CMD GDDR5_CMDGDDR5_80D GDDR5_CMDGDDR5_80D GDDR5_CMDGDDR5_80D GDDR5_CMD GDDR5_CMD GDDR5_CMDGDDR5_80D GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE GDDR5_DATAGDDR5_45SE GDDR5_DATA GDDR5_DATA GDDR5_DATAGDDR5_45SE

2 1

FB_B0_CLK_P FB_B0_CLK_N FB_B1_CLK_P FB_B1_CLK_N FB_B0_A<8..0> FB_B1_A<8..0> FB_B0_ABI_L FB_B1_ABI_L FB_B0_RAS_L FB_B1_RAS_L FB_B0_CAS_L FB_B1_CAS_L FB_B0_WE_L FB_B1_WE_L FB_B0_CKE_L FB_B1_CKE_L FB_B0_CS_L FB_B1_CS_L FB_B0_EDC<0> FB_B0_EDC<1> FB_B0_EDC<2> FB_B0_EDC<3> FB_B1_EDC<0> FB_B1_EDC<1> FB_B1_EDC<2> FB_B1_EDC<3> FB_B0_DBI_L<0> FB_B0_DBI_L<1> FB_B0_DBI_L<2> FB_B0_DBI_L<3> FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3> FB_B0_WCLK_P<0> FB_B0_WCLK_N<0> FB_B0_WCLK_P<1> FB_B0_WCLK_N<1> FB_B1_WCLK_P<0> FB_B1_WCLK_N<0> FB_B1_WCLK_P<1> FB_B1_WCLK_N<1> FB_B0_DQ<7..0> FB_B0_DQ<15..8> FB_B0_DQ<23..16> FB_B0_DQ<31..24> FB_B1_DQ<7..0> FB_B1_DQ<15..8> FB_B1_DQ<23..16> FB_B1_DQ<31..24>

75 77

6

75 77

75 77 75 76

75 77

6

75 77

D

C

MUXGFX Net Properties

B

ELECTRICAL_CONSTRAINT_SET

LVDS_A_CLK LVDS_A_CLK LVDS_A_DATA LVDS_A_DATA LVDS_B_CLK LVDS_B_CLK LVDS_B_DATA LVDS_B_DATA

NET_TYPE

PHYSICAL

LVDS_85D LVDS LVDS_85D LVDS_85D LVDS LVDS_85D LVDS LVDS_85D LVDS LVDS_85D LVDS LVDS_85D LVDS

LVDS_85D LVDS

SPACING

LVDS

LVDSLVDS_85D

LVDSLVDS_85D LVDSLVDS_85D LVDSLVDS_85D LVDSLVDS_85D LVDSLVDS_85D LVDSLVDS_85D LVDSLVDS_85D LVDSLVDS_85D LVDSLVDS_85D LVDSLVDS_85D LVDSLVDS_85D

LVDS_A_CLK_P LVDS_A_CLK_N LVDS_A_DATA_P<2..0> LVDS_A_DATA_N<2..0> LVDS_B_CLK_P LVDS_B_CLK_N LVDS_B_DATA_P<2..0> LVDS_B_DATA_N<2..0>

LVDS_CONN_A_CLK_F_P LVDS_CONN_A_CLK_F_N LVDS_CONN_B_CLK_F_P LVDS_CONN_B_CLK_F_N LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_N LVDS_CONN_A_DATA_P<2..0> LVDS_CONN_A_DATA_N<2..0> LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_N LVDS_CONN_B_DATA_P<2..0> LVDS_CONN_B_DATA_N<2..0>

83 87

6

82 83

6

82 83

6

82

82 83

A

8 7 5 4 2 1

Whistler Net Properties

ELECTRICAL_CONSTRAINT_SET

GPU_CLK27M GPU_CLK100M LVDS_EG_A_CLK LVDS_EG_A_CLK LVDS_EG_A_DATA LVDS_EG_A_DATA LVDS_EG_A_DATA3 LVDS_EG_A_DATA3 LVDS_EG_B_DATA LVDS_EG_B_DATA LVDS_EG_B_DATA3 LVDS_EG_B_DATA3

DP_ML

DP_AUX_CH

36

NET_TYPE

PHYSICAL

CLK_SLOWCLK_SLOW_55S CLK_SLOW_55S LVDS_85D LVDS_85D LVDS LVDS_85D LVDS_85D LVDS LVDS_85D LVDS_85D LVDS_85D LVDS LVDS_85D LVDS_85D LVDS LVDS_85D LVDS

DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D

CLK_SLOW

LVDS

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

SPACING

GPU_CLK27M GPU_CLK100M LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_EG_A_DATA_P<2..0> LVDS_EG_A_DATA_N<2..0> NC_LVDS_EG_A_DATA_P<3> NC_LVDS_EG_A_DATA_N<3> LVDS_EG_B_DATA_P<2..0> LVDS_EG_B_DATA_N<2..0> NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_N<3>

DP_EXTA_ML_C_P<3..0> DP_EXTA_ML_C_N<3..0> DP_EXTA_AUXCH_C_P DP_EXTA_AUXCH_C_N DP_EG_AUXCH_P DP_EG_AUXCH_N

SYNC_MASTER=K92_MLB

PAGE TITLE

GPU (Whistler) CONSTRAINTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

78 79

78 87

78 79

78 87

78 79

78 84

83 84

8

78 83

8

78 83

SYNC_DATE=08/09/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

107 OF 132

97 OF 101

SIZE

B

A

D

345678

2 1

SENSE_1TO1_55S

THERM_1TO1_55S

DIFFPAIR

AUDIODIFF 0.1 MM

SPACING_RULE_SET

D

SENSE

THERM

AUDIO

SPACING_RULE_SET

ENETCONN

SPACING_RULE_SET

GND

SPACING_RULE_SET

GND_P2MM

PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

MEM_CMD

C

MEM_CTRL

MEM_DATA

MEM_DQS

MEM_40S 100 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

PCIE_85D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

CPU_27P4S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

B

*

ALLOW ROUTE ON LAYER?

=1:1_DIFFPAIR

LINE-TO-LINE SPACING

LAYER

* ?

*

LAYER

LINE-TO-LINE SPACING

*

LAYER

LINE-TO-LINE SPACING

*

LAYER

LINE-TO-LINE SPACING

*

GND

LAYER

ALLOW ROUTE ON LAYER?

*

=2:1_SPACING

25 MILS

=STANDARD

0.20 MM

AREA_TYPE

*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=55_OHM_SE =55_OHM_SE

=55_OHM_SE

0.1 MM

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

1000

TABLE_SPACING_RULE_ITEM

1000

GND_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.09 MM

0.09 MM 100 MILMEM_72D

0.09 MM

TOP 0.1 MM

BOTTOM

0.23 MM 100 MIL

MAXIMUM NECK LENGTH

=55_OHM_SE

=55_OHM_SE=55_OHM_SE

=1:1_DIFFPAIR

10 MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_COMP

CPU_VCCSENSE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

ENET_MDI

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_PCIE GND_P2MM

PCIE

SATA

USB

CLK_PCIE

SATA

USB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LVDS

MAXIMUM NECK LENGTH

GND

SB_POWER

GND

DIFFPAIR PRIMARY GAP

=1:1_DIFFPAIR

0.1 MM 0.1 MM

AREA_TYPE

*

AREA_TYPE

*

AREA_TYPE

*

AREA_TYPE

*

DIFFPAIR PRIMARY GAP

10 mm

500 MILUSB_85D

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR

SPACING_RULE_SET

GND_P2MM

SPACING_RULE_SET

GND_P2MM

SPACING_RULE_SET

GND_P2MM

PWR_P2MMSB_POWER

PWR_P2MM

PWR_P2MMSB_POWER

SPACING_RULE_SET

GND_P2MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

K91 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

SENSE_DIFFPAIR

SENSE_DIFFPAIR THERM_1TO1_55S

I287

I288

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_DIFFPAIR

I249

I250

I252

I251

SENSE_DIFFPAIR SENSE_1TO1_55S

I256

I255

SENSE_DIFFPAIR SENSE_1TO1_55S

I281

I282

SENSE_DIFFPAIR SENSE_1TO1_55S

I283

I284

SENSE_DIFFPAIR

I285

I286

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SENSE_DIFFPAIR

I292

I291

SENSE_DIFFPAIR

I299

I300

SENSE_DIFFPAIR

I301

I302

SENSE_DIFFPAIR

I303

I304

SENSE_DIFFPAIR

I305

I306

SENSE_DIFFPAIR

I308

I307

SENSE_DIFFPAIR

I329

I330

I337

I338

SENSE_DIFFPAIR

I331

I332

SENSE_DIFFPAIR

I333

I334

SENSE_DIFFPAIR SENSE_1TO1_55S

I335

I336

SENSE_DIFFPAIR

I342

I341

PHYSICAL

ENET_100D

THERM_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

NET_TYPE

SPACING

ENETCONN

THERM

SENSE

ENETCONN_P<3..0> ENETCONN_N<3..0>

CPUTHMSNS_D2_P CPUTHMSNS_D2_N

CPU_THERMD_P CPU_THERMD_N

GPUTHMSNS_D_P GPUTHMSNS_D_N GPU_TDIODE_P GPU_TDIODE_N

VCCSAS0_CS_P VCCSAS0_CS_N VCCSAISNS_R_P VCCSAISNS_R_N ISNS_1V5_S3_R_P ISNS_1V5_S3_R_N CPUVCCIOS0_CS_P

CPUVCCIOS0_CS_N CPUVCCIOISNS_R_P CPUVCCIOISNS_R_N GPUISENS_N GPUISENS_P

ISNS_1V5_S3_N ISNS_1V5_S3_P ISNS_AIRPORT_N ISNS_AIRPORT_N ISNS_AIRPORT_P ISNS_AIRPORT_P ISNS_AIRPORT_R_N ISNS_AIRPORT_R_P ISNS_HDD_N ISNS_HDD_P ISNS_HDD_R_N ISNS_HDD_R_P ISNS_LCDBKLT_N ISNS_LCDBKLT_P ISNS_ODD_N ISNS_ODD_P ISNS_ODD_R_N

ISNS_ODD_R_P ISNS_PP1V0_S0GPU_P ISNS_PP1V0_S0GPU_N

ISNS_PP1V0_S0GPU_R_P ISNS_PP1V0_S0GPU_R_N PP1V8_S0GPU_P PP1V8_S0GPU_N PP1V8_S0GPU_R_P PP1V8_S0GPU_R_N PP1V5_S0GPU_P PP1V5_S0GPU_N PP1V5_S0GPU_R_P PP1V5_S0GPU_R_N

CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N CPUIMVP_ISNS1G_R_P CPUIMVP_ISNS1G_R_N ISNS_HS_OTHER_P ISNS_HS_OTHER_N ISNS_HS_GPU_P ISNS_HS_GPU_N ISNS_HS_COMPUTING_P ISNS_HS_COMPUTING_N CPUIMVP_ISNS_P CPUIMVP_ISNS_N

37

50

9

50

50 78

48 64

48

48 69

48

48 66

98

100

49 68

49

K91 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

I324

I323

I326

I325

I328

I327

PCIE_CLK100M_AP

(USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA)

AUDIO_DIFFPAIR

50

NET_TYPE

PHYSICAL

1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR

USB_85D

AUDIODIFF

CLK_PCIECLK_PCIE_90D CLK_PCIECLK_PCIE_90D

SPACING

USB

AUDIO

PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N

CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N

USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N

USB2_LT1_P USB2_LT1_N

CONN_USB2_BT_P CONN_USB2_BT_N

USB_LT2_P USB_LT2_N

SSM2375L_P SSM2375L_N SSM2375R_P SSM2375R_N SSM2375S_P SSM2375S_N

63

49 63

6

31

6

31

D

42

6

42

6

42

6

42

6

42

59

C

SPK_OUT

DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR

USB_85D

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

USB

SB_POWER

GND

SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N

USB_TPAD_R_P USB_TPAD_R_N

PP3V3_S5 PP3V3_S0 PP1V5_S3RS0

GND

6

59 60

6

59 60

6

59 60

6

59 60

6

59 60

6

59 60

52

45 55 65 70 71 72 82 85 89 6 7

17 19 20 22 23 24 25 29 39

48 49 50 51 53 56 60 61 71 72 6 7

12 16 17 18 19 20 22 23 25 26 28 32 35 36 39 40 41 45 47 79 82 83 84 87 88 89

6

B

Graphics ,SATA Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

NET_PHYSICAL_TYPE

AREA_TYPE

DP_85D

SATA_90D

CLK_PCIE_90D 100_DIFF_BGA

Memory Constraint Relaxations

A

PHYSICAL_RULE_SET

BGA

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

LAYER

MEM_72D 6.35 MM

MEM_85D 6.35 MM

BOTTOM

LVDS_85DLVDS_85D

100_DIFF_BGA

ALLOW ROUTE ON LAYER?

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.127 MM

0.1 MMTOP

8 7 5 4 2 1

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

AUDIO_DIFFPAIR

I312

I311

AUDIO_DIFFPAIR

I314

I313

AUDIO_DIFFPAIR

I316

I315

AUDIO_DIFFPAIR

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

I317

I318

I319

I320

I321

I322

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO1_R_P AUD_LO1_R_N AUD_LO2_L_P AUD_LO2_L_N AUD_LO2_R_P AUD_LO2_R_N AUD_SPKRAMP_LIN_P AUD_SPKRAMP_LIN_N AUD_SPKRAMP_RIN_P AUD_SPKRAMP_RIN_N AUD_SPKRAMP_SUBIN_P AUD_SPKRAMP_SUBIN_N

56 59

59

SYNC_MASTER=K18_MLB

PAGE TITLE

Project Specific Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

BRANCH

PAGE

108 OF 132

SHEET

98 OF 101

SIZE

A

D

36

345678

2 1

K91 Board-Specific Spacing & Physical Constraints

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

LAYER

D

55_OHM_SE

TOP,BOTTOM

55_OHM_SE

LAYER

50_OHM_SE

TOP,BOTTOM

50_OHM_SE

LAYER

45_OHM_SE

TOP,BOTTOM

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

45_OHM_SE

LAYER

40_OHM_SE

TOP,BOTTOM

40_OHM_SE

LAYER

37_OHM_SE

TOP,BOTTOM

37_OHM_SE

C

27P4_OHM_SE

LAYER

TOP,BOTTOM

27P4_OHM_SE

LAYER

72_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

LAYER

80_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

LAYER

85_OHM_DIFF

B

85_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

ALLOW ROUTE ON LAYER?

* Y

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

Y

Y*

Y

Y*

Y

N

Y

N

Y

N

Y

MINIMUM LINE WIDTH

=50_OHM_SE

MINIMUM LINE WIDTH

0.090 MM 0.090 MM

0.076 MM

MINIMUM LINE WIDTH

0.110 MM

0.090 MM

MINIMUM LINE WIDTH

0.13 MM 0.13 MM

0.099 MM 0.099 MM

MINIMUM LINE WIDTH

0.135 MM

MINIMUM LINE WIDTH

0.185 MM 0.095 MM

0.155 MM

MINIMUM LINE WIDTH

0.250 MM

MINIMUM LINE WIDTH

=STANDARD

0.154 MM

0.175 MM

MINIMUM LINE WIDTH

=STANDARD

0.105 MM 0.105 MM

0.105 MM

0.135 MM

MINIMUM LINE WIDTH

=STANDARD

0.110 MM

0.110 MM 0.090 MM

0.125 MM

MINIMUM NECK WIDTH

=50_OHM_SE

=DEFAULT=DEFAULTSTANDARD

MINIMUM NECK WIDTH

0.076 MM

MINIMUM NECK WIDTH

0.095 MM

0.090 MM

MINIMUM NECK WIDTH

0.095 MM0.165 MM

0.090 MM

MINIMUM NECK WIDTH

0.090 MM

MINIMUM NECK WIDTH

0.095 MM0.310 MM

MINIMUM NECK WIDTH

=STANDARD

0.154 MM

0.175 MM

MINIMUM NECK WIDTH

0.105 MM

0.135 MM

MINIMUM NECK WIDTH

=STANDARD

0.090 MM

0.1 MM

BOARD AREAS

NO_TYPE,BGA

MAXIMUM NECK LENGTH

10 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

0 MM 0 MM

=DEFAULT

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

0.200 MM

DIFFPAIR PRIMARY GAP

=STANDARD

0.120 MM

DIFFPAIR PRIMARY GAP

=STANDARD

0.180 MM

0.190 MM

BOARD UNITS (MIL or MM)

MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=DEFAULT

=STANDARD

0.200 MM

=STANDARD

0.120 MM

0.160 MM0.160 MM

=STANDARD

0.180 MM

0.180 MM0.180 MM

0.190 MM

ALLEGRO VERSION

15.5.1

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

SPACING_RULE_SET

LAYER

DEFAULT

STANDARD

BGA_P1MM =DEFAULT

P072_SPACE

SPACING_RULE_SET

LAYER

1.5:1_SPACING

2:1_SPACING

2.5:1_SPACING

3:1_SPACING

4:1_SPACING

5:1_SPACING

LAYER

1:1_DIFFPAIR

*

LINE-TO-LINE SPACING

WEIGHT

0.1 MM

*

=DEFAULT

* ?

*

* ?

=DEFAULTBGA_P2MM

0.071 MM

LINE-TO-LINE SPACING

0.15 MM

* ?

0.2 MM

0.25 MM

0.3 MM

*

ALLOW ROUTE ON LAYER?

0.4 MM

0.5 MM

MINIMUM LINE WIDTH

Y

?*

?

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?*

?

SPACING_RULE_SET

TABLE_SPACING_RULE_HEAD

2X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

3X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

4X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

5X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

7X_DIELECTRIC

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

NET_SPACING_TYPE1 NET_SPACING_TYPE2

*

LAYER

*

LINE-TO-LINE SPACING

*

MAXIMUM NECK LENGTH

=STANDARD

=STANDARD=STANDARD

AREA_TYPE

BGA

0.140 MM

0.210 MM

0.280 MM

0.350 MM

0.490 MM

DIFFPAIR PRIMARY GAP

P072_SPACE

WEIGHT

?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

D

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.1 MM0.1 MM

C

B

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SYNC_MASTER=K18_MLB

PAGE TITLE

PCB Rule Definitions

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=04/27/2010

DRAWING NUMBER

REVISION

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SIZE

A

D

=STANDARD=STANDARD

0.220 MM

0.200 MM

0.220 MM

=STANDARD

0.2 MM

0.2 MM0.2 MM

0.330 MM0.330 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

100_DIFF_BGA

LAYER

ISL3,ISL4

ISL9,ISL10

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

LAYER

ALLOW ROUTE ON LAYER?

90_OHM_DIFF

100_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

LAYER

*

ISL3,ISL4,ISL9,ISL10

ALLOW ROUTE ON LAYER?

100_OHM_DIFF

A

110_OHM_DIFF

TOP,BOTTOM

LAYER

* N

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

ALLOW ROUTE ON LAYER?

N*

Y

N

Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

0.090 MM0.102 MM

0.102 MM

0.115 MM

MINIMUM LINE WIDTH

=STANDARD =STANDARD

0.080 MM

0.090 MM

MINIMUM NECK WIDTH

=STANDARD

0.080 MM

MAXIMUM NECK LENGTH

0.089 MM 0.089 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD =STANDARD=STANDARD

0.065 MM0.065 MM

0.075 MM0.075 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

0.220 MM

0.230 MM 0.230 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD

0.200 MM

0.200 MMISL2,ISL11

0.220 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

0.2 MM

8 7 5 4 2 1

ALLOW ROUTE ON LAYER?

=100_OHM_DIFF

*

Y

MINIMUM LINE WIDTH

=100_OHM_DIFF =100_OHM_DIFF

0.075 MM

MINIMUM NECK WIDTH

=100_OHM_DIFF

0.075 MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF =100_OHM_DIFF

0.125 MM 0.125 MM

36

345678

DEBUG_ADC

LCD BKLT Current Sense

PP5V_S3

6 7

XWD159

29 31 41 42 43 45 65 66 71 81

DEBUG_ADC

3 V+

UD120

INA214

5

SC70

IN-

4

IN+ REF

GND

2

OUT

GAIN: 100X

SM

1

TP_ISNS_LCDBKLT_N

TP_ISNS_LCDBKLT_P

2

6

LCDBKLT_IOUT

1

DEBUG_ADC

1

CD144

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=UD100.22:5mm

DEBUG_ADC

RD150

4.53K

1 2

1% 1/16W MF-LF

402

1

2

DEBUG_ADC

CD145

0.22UF

PLACE_NEAR=UD100.22:5mm

20%

6.3V X5R 402

ADC_CH0

100

EDP Current: 0.715A

PPBUS_SW_BKL

7

88

OUT

D

PPBUS_SW_LCDBKLT_PWR

88

IN

LCD BKLT Voltage Sense

PPVOUT_S0_LCDBKLT

6 8

82 88

100

XWD150

SM

21

VOUT_S0_LCDBKLT_XW

DEBUG_ADC

1

RD156

1M

1% 1/16W MF-LF 402

2

VOUT_S0_LCDBKLT_DIV DEBUG_ADC

1

RD157

46.4K

1% 1/16W MF-LF 402

2

100

DIVIDER: ~ 1/22

PP5V_S3

6 7

29 31 41 42 43 45 65 66 71 81

PLACE_NEAR=UD100.5:5mm

DEBUG_ADC

RD158

226K

1 2

1/16W MF-LF

ADC_CH7

1%

402

100

DEBUG_ADC

1

CD152

2.2UF

10%

6.3V

2

X5R 402

PLACE_NEAR=UD100.5:5mm

RD103

10

1 2

5% 1/16W MF-LF

402

I2C ADDRESS: 0X10 / 0X11

ADC RANGE: 0V TO 4.096V

LSB: 0.001V

PP5V_S5_DEBUG_ADC_AVDD_FILT

DEBUG_ADC

1

CD100

0.1UF

20% 10V

2

CERM 402

ADC_CH0

100

ADC_CH1

100

ADC_CH2

100

ADC_CH3

100 101

ADC_CH4

100

ADC_CH5

100

ADC_CH6

100

ADC_CH7

100

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

DEBUG_ADC

1

CD101

10UF

20%

6.3V

2

X5R 603

PP5V_S5_DEBUG_ADC_DVDD_FILT

MIN_LINE_WIDTH=0.3MM

12

13

21

DVDDAVDD

UD100

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

COM

9

LTC2309

QFN

DEBUG_ADC

GND

1011181920

VREF

REFCOMP

THRM

PAD

25

AD0 AD1

SDA SCL

22

23

24

1

2

3

4

5

6

2 1

DEBUG_ADC

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5V

14

15

17

16

7

8

1

2

ADC_SDA ADC_SCL

DEBUG_ADC

CD102

0.1UF

20% 10V CERM 402

DEBUG_ADC

ADC_VREF

ADC_REFCOMP DEBUG_ADC

1

CD104

0.1UF

20% 10V

2

CERM 402

1

2

RD101

33

1 2

5% 1/16W MF-LF

402

DEBUG_ADC

CD103

10UF

20%

6.3V X5R 603

PLACE_NEAR=U4900.F1:10mm

DEBUG_ADC

RD102

33

1 2

5% 1/16W MF-LF

402

DEBUG_ADC

1

CD105

10UF

20%

6.3V

2

X5R 603

RD104

10

PP5V_S3

1 2

5% 1/16W MF-LF

402

SMBUS_SMC_MGMT_SDA

PLACE_NEAR=U4900.E4:10mm

SMBUS_SMC_MGMT_SCL

DEBUG_ADC

1

CD106

2.2UF

20%

6.3V

2

CERM 402-LF

6 7

29 31 41 42 43 45 65 66

71 81

100

44 47 96

BI

44 47 96

IN

D

AIRPORT Current Sense

PP5V_S3

6 7

100

Sense Resistor 0.005 Ohm

EDP Current: 1.06A

TP_ISNS_AIRPORT_P

C

IN

TP_ISNS_AIRPORT_N

29 31 41 42 43 45 65 66 71 81

DEBUG_ADC

RD130

2.61K

2

1

1% 1/16W MF-LF

402

DEBUG_ADC

RD131

2.61K

1

1% 1/16W MF-LF

402

2

ISNS_AIRPORT_R_P

98

ISNS_AIRPORT_R_N

98

DEBUG_ADC

1

RD132

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

3

2

THRM

DEBUG_ADC

RD133

1M

1 2

1% 1/16W MF-LF

402

8

V+

V-

4

9

SIGNAL_MODEL=EMPTY

DEBUG_ADC

UD130

OPA2333

DFN

1

DEBUG_ADC

1

CD130

0.1UF

20% 10V

2

CERM 402

ISNS_AIRPORT_IOUT

GAIN: 383X

PLACE_NEAR=UD100.1:5mm

DEBUG_ADC

RD134

226K

1 2

1% 1/16W MF-LF

402

ADC_CH2

1

2

100

DEBUG_ADC

CD131

2.2UF

10%

6.3V X5R 402

PLACE_NEAR=UD100.24:5mm

Sense Resistor 0.005 Ohm

EDP Current: 1.8A

TP_ISNS_ODD_P

IN

TP_ISNS_ODD_N

IN

ODD Current Sense

DEBUG_ADC

RD151

4.42K

1 2

1/16W MF-LF

DEBUG_ADC

RD152

4.42K

1 2

1/16W MF-LF

98

1%

402

98

1%

402

100

ISNS_ODD_R_P

ISNS_ODD_R_N

DEBUG_ADC

6 7

29 31 41 42 43 45 65 66 71 81

1

RD153

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

PP5V_S3

DEBUG_ADC

RD154

1 2

3

2

1/16W MF-LF

402

DEBUG_ADC

1

CD151

0.1UF

20% 10V

2

CERM

ISNS_ODD_IOUT

GAIN: 226X

402

PLACE_NEAR=UD100.1:5mm

NOSTUFF

RD155

226K

1 2

1% 1/16W MF-LF

402

PLACE_NEAR=UD100.1:5mm

ADC_CH3

NOSTUFF

1

CD150

2.2UF

10%

6.3V

2

X5R 402

C

100 101

DEBUG_ADC

UD140

OPA2333

8

DFN

V+

1

V-

THRM

4

9

1M

SIGNAL_MODEL=EMPTY

1%

GPU 1.0V Current Sense

EDP Current: 2.846A

PP1V0_S0GPU

7

86

IN

TP_ISNS_PP1V0_S0GPU_P

XWD145

B

PP1V0_S0GPU_ISNS

7

73 74 78 80

OUT

2

SM

1

TP_ISNS_PP1V0_S0GPU_N

DEBUG_ADC

RD140

4.22K

1 2

1/16W MF-LF

DEBUG_ADC

RD141

4.22K

1 2

1% 1/16W MF-LF

402

ISNS_PP1V0_S0GPU_R_P

98

1%

402

ISNS_PP1V0_S0GPU_R_N

DEBUG_ADC

1

RD142

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

5

6

THRM

DEBUG_ADC

RD143

1M

1 2

1% 1/16W MF-LF

402

GAIN: 237X

8

V+

V-

4

9

SIGNAL_MODEL=EMPTY

UD130

OPA2333

DFN

7

PLACE_NEAR=UD100.2:8mm

1V0_GPU_IOUT

DEBUG_ADC

RD144

226K

1 2

1% 1/16W MF-LF

402

ADC_CH4

1

CD142

2.2UF

10%

DEBUG_ADC

6.3V

2

X5R 402

PLACE_NEAR=UD100.2:8mm

Sense Resistor 0.005 Ohm EDP Current: 1.2A

TP_ISNS_HDD_P

100

IN

TP_ISNS_HDD_N

HDD Current Sense

DEBUG_ADC

RD160

2.94K

1 2

1/16W MF-LF

402

98

1%

DEBUG_ADC

RD161

2.94K

1 2

1/16W MF-LF

402

98

1%

ISNS_HDD_R_P

ISNS_HDD_R_N

DEBUG_ADC

1

RD162

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

DEBUG_ADC

RD163

1 2

5

6

1/16W MF-LF

402

UD140

OPA2333

8

DFN

V+

7

V-

THRM

4

9

1M

SIGNAL_MODEL=EMPTY

1%

ISNS_HDD_IOUT

GAIN: 340X

PLACE_NEAR=UD100.3:5mm

DEBUG_ADC

RD164

226K

1 2

1% 1/16W MF-LF

402

PLACE_NEAR=UD100.3:5mm

ADC_CH5

DEBUG_ADC

1

CD140

2.2UF

10%

6.3V

2

X5R 402

B

100

A

EDP Current: 2.4065A

6 7

71

IN

7

74 78 80

OUT

PP5V_S3

6 7

100

29 31 41 42 43 45 65 66 71 81

PP1V8_GPUIFPX

1

XWD186

PP1V8_S0GPU_ISNS

TP_PP1V8_S0GPU_P

SM

2

TP_PP1V8_S0GPU_N

8 7 5 4 2 1

GPU 1.8V Current Sense

DEBUG_ADC

RD187

11.8K

1 2

1% 1/16W MF-LF

402

RD188

11.8K

1 2

1% 1/16W MF-LF

402

DEBUG_ADC

PP1V8_S0GPU_R_P

98

PP1V8_S0GPU_R_N

98

1

RD189

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

DEBUG_ADC

5

6

DEBUG_ADC

RD190

1M

1 2

1% 1/16W MF-LF

402

THRM

8

V+

V-

4

9

SIGNAL_MODEL=EMPTY

UD180

OPA2333

DFN

7

1

CD180

2

P1V8_S0GPU_IOUT

0.1UF

DEBUG_ADC

20% 10V

CERM

402

PLACE_NEAR=UD.23:5mm

RD191

4.53K

1 2

1%

1/16W

MF-LF

402

DEBUG_ADC

PLACE_NEAR=UD.23:5mm

1

2

CD182

0.22UF

20%

6.3V

X5R

402

ADC_CH1

DEBUG_ADC

EDP Current: 7.8A

PP1V5_GPU_REG

7

86

IN

100

OUT

7

74 75 76 77

OUT

XWD180

PP1V5_S0GPU_ISNS

SM

1

TP_PP1V5_S0GPU_P

2

TP_PP1V5_S0GPU_N

DEBUG_ADC

RD181

7.68K

1 2

1% 1/16W MF-LF

402

RD182

7.68K

1 2

1% 1/16W MF-LF

402

DEBUG_ADC

1.5V FB Current Sense

PP1V5_S0GPU_R_P

98

PP1V5_S0GPU_R_N

98

1

RD183

1M

1% 1/16W MF-LF 402

2

SIGNAL_MODEL=EMPTY

3

2

THRM

DEBUG_ADC

RD184

1M

1 2

1% 1/16W MF-LF

402

8

V+

V-

4

9

SIGNAL_MODEL=EMPTY

UD180

OPA2333

DFN

1

P1V5_S0GPU_IOUT

Gain: 130x

PLACE_NEAR=UD100.4:5mm

RD185

4.53K

1 2

1%

1/16W

MF-LF

402

DEBUG_ADC

1

2

ADC_CH6

CD181

0.22UF

20%

6.3V

X5R

402

DEBUG_ADC

100

OUT

SYNC_MASTER=K91_DINESH

PAGE TITLE

DEBUG SENSORS AND ADC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

36

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130 OF 132

SHEET

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SIZE

A

D

Apple Macbook Pro 15 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual