Apple MacBook Pro 13'' A1708 Schematics

8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7
6 5 4 3
DESIGN: X502/MLB_CATZ
LAST CHANGE: Tue Aug 9 17:02:57 2016
2 1
ECNREV DESCRIPTION OF REVISION
CK APPD
DATE
2016-08-1000067823291 ENGINEERING RELEASED
D
1 2 3 4 5 6 7 8 9 10 11
1 2 3 4 5 6 7 8 9 10 11
LAST_MODIFICATION=Tue Aug 9 17:03:06 2016
Table of Contents BOM Configuration BOM Configuration PD Parts CPU GFX CPU MISC/JTAG/CFG/RSVD CPU LPDDR3 Interface CPU & PCH Power CPU & PCH Grounds CPU Core Decoupling CPU GT Decoupling
DATESYNCCONTENTSCSAPAGE
PAULM
PAULM
PAULM
PAULM 06/15/2015
PAULM
PAULM
PAULM
PAULM
PAULM
06/15/2015
06/15/2015
06/15/2015
06/15/2015
06/15/2015
06/15/2015
06/15/2015
06/15/2015
41 42 43 44 45 46 47 48 49 50 51
52 53 54 55
58 61 62 63 64 66
LAST_MODIFICATION=Tue Aug 9 17:03:06 2016
SMC Project Support SMBus Connections Power Sensors High Side Power Sensors Load Side Power Sensors Extended56 Thermal Sensors SPI ROM & SWD Debug HDA BRIDGE JACK CODEC SPEAKER AMP JACK TRANSLATORS
PAULM
PAULM
PAULM
PAULM
PAULM
PAULM
PAULM
AHAAGE
AHAAGE
AHAAGE
D
DATESYNCCONTENTSCSAPAGE
06/15/2015
06/15/2015
06/15/2015
06/15/2015
06/15/2015
06/15/2015
06/15/2015
03/23/2016
09/22/2015
03/23/2016
C
12 13 14 15 16 17 18 19
21 22 23 24 25
12 13 14 15 16 18 19 20 22 23 24 25 26 27
PCH Decoupling PCH Audio/LPC/SPI/SMBus PCH Power Management PCH PCIE/USB/CLKS PCH SPI/UART/GPIO CPU/PCH Merged XDP Chipset Support 1 Chipset Support 2 LPDDR3 VREF Margining20 LPDDR3 DRAM Channel A (00-31) LPDDR3 DRAM Channel A (32-63) LPDDR3 DRAM Channel B (00-31) LPDDR3 DRAM Channel B (32-63) LPDDR3 DRAM Termination
52 53 54 55 56 57 58 59 60 61 62 63 64 65
69 70 71 72 73 74 76
DC-IN & BATTERY CONNECTORS PBUS Supply & Battery Charger VReg CPU VCC Cntl CPU IMVP VCC & VCCSA IMVP VCCSA GT IMVP VCCGT
VR - 5V S4, 3.3V S5 77 VR - OPC (EDRAM) 78 79 80 81
PMIC VCCPCH VCCIO 1.8V
PMIC 1.2V 1.0V 0.6V
RAIL DESENSE CAPS 82 Power FETs 84
LCD Backlight Driver
C
B
26 27 28 29 30 31 32 34 33 34 35
37 38 39 SMC
28 29
USB-C HIGH SPEED 1
USB-C HIGH SPEED 2 30 USB-C SUPPORT 31 32 33
USB-C CONNECTOR A
USB-C CONNECTOR B 35 37 38 39 40 48
USB-C SUPPORT 2
WIFI/BT MODULE
WIFI/BT Module Support
CAMERA 1 OF 236
CAMERA 2 OF 2
P1:KEYBOARD & TRACKPAD CONN 50
66 67 68 69 70
72 73
85 86 99 100 102 103 104
eDP Display Connector SSD MODULE DEVELOPMENT ONLY Power Aliases NC_ AND NO_TEST SIGNALS Memory Signal Swaps71 FCT, ICT PROPERTIES =LAST SCHEMATIC PAGE=
X362
PAULM
PAULM
X502-EXP
PAULM
X502-EXP
PAULM
MICHKLEE500
06/23/2015
06/15/2015
06/15/2015
12/03/2015
06/15/2015
12/03/2015
06/15/2015
06/23/2015
B
A
40
51
SMC Shared Support
DOCUMENTS / BOARDS / ASSEMBLIES
Table of Contents
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
DRAWING TITLE
SCH1051-02265 SCHEM,MLB_CATZ,X502
SCHEM,MLB-CATZ,X502
A
PCBF,MLB_CATZ,X502 MLB1 CRITICAL820-00875
639-03266 PCBA,MLB_CATZ,XXXXX,X502
SIZEDRAWING NUMBER
Apple Inc.
R
CBOM1 CMN_PARTS_BOM685-00125 COMMON PARTS,MLB_CATZ,X502
DEV11 DEVELOPMENT_LIST985-00239 DEV PARTS,MLB_CATZ,X502
BOM_COST_GROUP=NO COST ITEMS
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
3
051-02265
REVISION
1.0.0
BRANCH
PAGE
1 OF 500
SHEET
1 OF 73
1245678
D
345678
2 1
D
Major ICs
CPU
IC,CPU,SKL-ULT,2+3E,42X24MM,BGA1356
INTERPOSER,VTT ADAPTER,SKL-U,BGA1356
CPU,SKYU,QJ8N,D0,QS,2/2,2.3,15W,BGA1356
CPU,SKYU,QJ8K,D0,QS,2/2,2.6,15W,BGA1356
CPU,SKYU,QJ57,J0,ES0,2/3,1.6,15W,BGA1356
CPU,SKYU,QJ58,J0,ES0,2/3,1.6,28W,BGA1356
CPU,SKYU,QK2T,K1,SQS,1.8,15W,.95,BGA1356
CPU,SKYU,QKBY,K1,SQS,2.2,15W,1.05,BG1356
CPU,SKYU,QK33,K1,SQS,2.0,15W,1.0,BG1356
CPU,SKYU,QK32,K1,SQS,2.4,15W,BGA1356
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CPU_SKL:BASECRITICAL998-00235 1 U0500
CPU_SKL:VTT_INTERPOSERCRITICAL998-04195 1 U0500
CPU_SKL:2_2_QS_2.3CRITICAL337S00168 1 U0500
CPU_SKL:2_2_QS_2.6CRITICAL337S00170 1 U0500
CRITICAL337S00149 1 U0500 CPU_SKL:2_3_ES0_GD
CPU_SKL:2_3_ES0_BTCRITICAL337S00150 1 U0500
CPU_SKL:2_3_SQS_1G8CRITICAL337S00219 1 U0500
CRITICAL337S00220 1 U0500 CPU_SKL:2_3_SQS_2G2
CPU_SKL:2_3_SQS_2G0CRITICAL337S00222 1 U0500
CPU_SKL:2_3_SQS_2G4CRITICAL337S00233 1 U0500
Programmables (All Builds)
SMC
338S1231 SMC:BLANKCRITICAL1 U5000
341S00334 SMC:POCCRITICAL1 U5000
1 U5000
IC,SMC12,40MHZ/50DMIPS MCU,7X7,168BGA
IC,SMC-B1,EXT (V2.31A18) POC,X502
IC,SMC-B1,EXT (V2.35A4) PROTO 1,X502
IC,SMC-B1,EXT (V2.35A51) PROTO 2,X502
IC,SMC-B1,EXT (V2.36A2) EVT,X502
IC,SMC-B1,EXT (V2.36A33) PRE-DVT,X502
IC,SMC-B1,EXT (V2.36A48) DVT,X502
IC,SMC-B1,EXT (V2.36F58) PVT,X502
SMC:PROTO1CRITICAL341S00429
D
SMC:PROTO2CRITICAL341S00517 1 U5000
SMC:EVTCRITICAL341S00562 1 U5000
SMC:PREDVTCRITICAL341S00611 1 U5000
SMC:DVTCRITICAL341S00633 1 U5000
SMC:PVTCRITICAL341S00662 1 U5000
C
ACE
CPU,SKY,SR2JC,K1,PRQ,1.8,15W,BGA1356
CPU,SKY,SR2JM,K1,PRQ,2.0,15W,BGA1356
CPU,SKYU,SR2JL,K1,PRQ,2.4,15W,BGA1356
IC,CD3215,USB PWR SWITCH,A0,6X6MM,BGA96
IC,CD3215,ACE,A1,USB PWR SWITCH,BGA96
IC,CD3215,ACE,B0,USB PWR SWITCH,BGA96
IC,CD3215,ACE,B0,USB PWR SW,BLNK,BGA96
IC,CD3215,ACE,B0,USB PWR SW,OTP=2,BGA96
IC,CD3215,ACE,B03,USB PWR SW,BLNK,BGA96
IC,CD3215,ACE,C00,USB PWR SW,BLNK,BGA96
CPU_SKL:2_3_PRQ_1G8CRITICAL337S00232 1 U0500
CPU_SKL:2_3_PRQ_2G0CRITICAL337S00239 1 U0500
CPU_SKL:2_3_PRQ_2G4337S00234 1 U0500 CRITICAL
EFI ROM
IC,SPI SERIAL FLASH,64M BITS,3V,CSP,QE=1
TABLE_ALT_ITEM
335S0959335S00006
ALT_CMN MACRONIXALL
IC,EFI (V0072) PROTO 0,X502
IC,EFI (V0093) PROTO 0,X502
IC,EFI (V0114) PROTO 2,X502
IC,EFI (V0130) PROTO 2.2,X502
IC,EFI (V0143) EVT,X502
IC,EFI (V0173) PVT,X502
U61001341S00573 CRITICAL BOOTROM:EVT
CRITICAL1 U6100341S00673
BOOTROM:BLANKCRITICAL335S0959 1 U6100
BOOTROM:PROTO0CRITICAL341S00389 1 U6100
BOOTROM:PROTO1CRITICAL341S00452 1 U6100
BOOTROM:PROTO2CRITICAL341S00513 1 U6100
BOOTROM:PROTO2_2CRITICAL341S00543 1 U6100
BOOTROM:PVT
MICRON
C
BT ROM
1 BT_ROM:BLANKCRITICAL335S00024 U3770
ACE:A0CRITICAL353S00422 2 U3100,U3200
335S0837
335S00024
ACE:A1CRITICAL353S00660 2 U3100,U3200
ACE:B0CRITICAL353S00807 2 U3100,U3200
ACE:B0_BCRITICAL353S00887 2 U3100,U3200
ACE:B0_2CRITICAL353S00888 2 U3100,U3200
ACE:B0_3CRITICAL353S00926 2 U3100,U3200
(BOOT CODE: 0002.08.07)
(BOOT CODE: 0002.08.07)
(BOOT CODE: 0002.08.08)
WIFI ROM
ACE:C0CRITICAL353S00961 2 U3100,U3200
335S0956335S00145
IC,FLASH,USON8,512KBIT,75MHZ
ALT_CMN ALL
IC,BT ROM (V53) DVT,X261
IC,BT ROM (V53) PROTO0,X502
IC,BT ROM (V53) PROTO0,X502
IC,MEMORY,EEPROM,4K,1.7V-5.5V,UDFN8
ALTERNATE
ALT_CMN ALTERNATEALL
TABLE_ALT_ITEM
BT_ROM:X261CRITICAL341S00196 1 U3770
U37701341S00397 CRITICAL BT_ROM:PROTO0
BT_ROM:PVTCRITICAL341S00397 1 U3770
WIFI-ROM:BLANKCRITICAL335S0956 1 U3780
TABLE_ALT_ITEM
B
TBT ALPINE RIDGE
WIRELESS MODULE
IC,TBT,ALPINE RIDGE DP,QSJV,B1,6X6MM,BGA96
IC,TBT,ALP-RIDGE DP,SLL44-TRAY,B1,CSP337
IC,TBT,ALPN-RIDGE DP,SLL43-T&R,B1,CSP337
IC,TBT,ALPINE RIDGE,QSTY,QS,C0,CSP337
IC,TBT,ALPINE RIDGE,QT5S,QS,C1,CSP337
IC,TBT,ALPINE RIDGE,SLLSM,PRQ,C1,CSP337
MODULE,WIFI/BT,STELLA CIDRE,MUR,LGA80
MODULE,WIFI/BT,STELLA CIDRE,USI,LGA80
WIFI ROM (P175) PRE-DVT,WW1,X502
TBT_AR:B1_QSCRITICAL338S00160 1 U2800
TBT_AR:B1_PRQ_TRAYCRITICAL998-04160 1 U2800
TBT_AR:B1_PRQCRITICAL338S00176 1 U2800
TBT_AR:C0_QSCRITICAL338S00229 1 U2800
TBT_AR:C1_QSCRITICAL338S00249 1 U2800
TBT_AR:C1_PRQCRITICAL338S00254 1 U2800
WIFI ROM (P175) PRE-DVT,WW2,X502
WIFI ROM (P175) PRE-DVT,WW3,X502
WIFI ROM (P175) PRE-DVT,IND,X502
WIFI ROM (P177) USI-WW1,X502
WIFI ROM (P177) USI-WW2,X502
WIFI ROM (P177) USI-WW3,X502
WIFI ROM (P177) USI-IND,X502
WIFI-ROM:MURATA-FCCCRITICAL341S00607 1 U3780
WIFI-ROM:MURATA-ETSICRITICAL341S00608 1 U3780
WIFI-ROM:MURATA-APACCRITICAL341S00609 1 U3780
WIFI-ROM:MURATA-INDCRITICAL341S00610 1 U3780
WIFI-ROM:USI-FCCCRITICAL341S00636 1 U3780
WIFI-ROM:USI-ETSICRITICAL341S00637 1 U3780
WIFI-ROM:USI-APACCRITICAL341S00638 1 U3780
B
WIFI-ROM:USI-INDCRITICAL341S00639 1 U3780
WIRELESS:MURATACRITICAL339S0250 1 U3700
WIRELESS:USICRITICAL339S0251 1 U3700
TBT ROM
IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8
IC,NVM / AR (V0.8.15.E1) PROTO 1,X502
IC,NVM (VB1-10.11-E2.6.3) PROTO 2,X502
AR_ROM:BLANKCRITICAL335S00133 1 U2890
AR_ROM:PROTO1CRITICAL341S00451 1 U2890
AR_ROM:PROTO2CRITICAL341S00512 1 U2890
A
合肥怡飞苹果维修qq:82669515 qq群: 241000
IC,NVM (V16.8) EVT,X502
IC,NVM (V1.5) PRE-DVT,X502
IC, NVM (V3.8), DVT, X502
IC, NVM (VTBD), PVT, X502
AR_ROM:EVTCRITICAL341S00559 1 U2890
AR_ROM:PREDVTCRITICAL341S00606 1 U2890
AR_ROM:DVTCRITICAL341S00628 1 U2890
AR_ROM:PVTCRITICAL341S00661 1 U2890
BOM_COST_GROUP=NO COST ITEMS
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
PAGE TITLE
BOM Configuration
DRAWING NUMBER SIZE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
051-02265
REVISION
1.0.0
BRANCH
PAGE
2 OF 500
SHEET
2 OF 73
D
A
8 7 5 4 2 1
36
Main DRAM Parts
345678
2 1
D
C
B
333S00101
IC,LPDDR3-1866,16GB,512MX32,25NM,BGA178 U2300,U2400,U2500,U2600
333S0784
333S00097
333S00098
333S00099
333S00049
4
4 CRITICAL
4 DRAM:SAMSUNG_8GB_1866
IC,LPDDR3-1866,16GB,512MX32,20NM,BGA178
IC,LPDDR3-1866,32GB,1GX32,20NM,BGA178
IC,LPDDR3-1866,16GB,512MX32,20NM,BGA178 U2300,U2400,U2500,U2600
IC,SDRAM,LPDDR3-1866,32GBIT,20NM,BGA1784 U2300,U2400,U2500,U2600 CRITICAL DRAM:SAMSUNG_16GB_1866
U2300,U2400,U2500,U2600
U2300,U2400,U2500,U2600
Main DRAM SPD Straps
PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V.
RAMCFG1
HYNIX 0 (STUFF R)
MICRON
SAMSUNG
-RESERVED-
1 (OPEN)
1 (OPEN)
4117S0006
117S0006
3
3117S0006
117S0006
2
3117S0006
117S0006 2
RAMCFG0
0 (STUFF R) 8GB 0 (STUFF R) 2133
1 (OPEN)
0 (STUFF R)
1 (OPEN)
16GB 1867
RES,MF,1/20W,1K OHM,5,0201,SMD
RES,MF,1/20W,1K OHM,5,0201,SMD
RAMCFG2
R1330,R1331,R1332,R1334RES,MF,1/20W,1K OHM,5,0201,SMD
R1330,R1331,R1334
R1331,R1332,R1334
R1331,R1334
R1330,R1332,R1334
R1330,R1334 DRAM:SAMSUNG_16GB_1866RES,MF,1/20W,1K OHM,5,0201,SMD
MLB VERSION ID STRAPS
PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V.
PART# DESCRIPTIONQTY
RES,MF,1/20W/1K OHM,5,0201,SMD0117S0006 BOARD_ID:POC
RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PROTO0R16901117S0006
117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD1 R1691 BOARD_ID:PRE_PROTO1
RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PROTO1117S0006 2 R1691,R1690
R16921117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PROTO2
RES,MF,1/20W/1K OHM,5,0201,SMD2 R1692,R1690 BOARD_ID:PROTO2_2117S0006
RES,MF,1/20W/1K OHM,5,0201,SMD2117S0006 R1692,R1691 BOARD_ID:EVT
RES,MF,1/20W/1K OHM,5,0201,SMD117S0006 3 BOARD_ID:PREDVTR1692,R1691,R1690
1 BOARD_ID:DVTRES,MF,1/20W/1K OHM,5,0201,SMD117S0006 R1693
RES,MF,1/20W/1K OHM,5,0201,SMD117S0006 R1693,R16902 BOARD_ID:DVT3
2117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PVTR1693,R1691
2117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:PRQ1R1693,R1691,R1690
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
DRAM:HYNIX_8GB_18664 CRITICAL
CRITICAL4 IC,LPDDR3-1866,32GBIT,25NM,BGA178 U2300,U2400,U2500,U2600
CRITICAL
DRAM:HYNIX_16GB_1866
DRAM:MICRON_8GB_1866
DRAM:MICRON_16GB_1866
CRITICAL
RAMCFG3
0 (STUFF R)
1 (OPEN)1 (OPEN)0 (STUFF R)
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
DRAM:HYNIX_8GB_1866
DRAM:HYNIX_16GB_1866
DRAM:MICRON_8GB_1866RES,MF,1/20W,1K OHM,5,0201,SMD
DRAM:MICRON_16GB_1866
DRAM:SAMSUNG_8GB_1866RES,MF,1/20W,1K OHM,5,0201,SMD
CODE
<11111>
<11110>
<11101>
<11100>
<11011>
<11010>
<11001>
<11000> <00111>
<10110> <01001>
<10100> <01011>
INVERT TO VALUE
<00000>
<00001>
<00010>
<00011>
<00100>
<00101>
<00110>
<01000><10111>
<01010><10101>
DIE A
DIE B
RAMCFG4
0 (STUFF R)
1 (OPEN)
Alternate Parts
PART NUMBER
107S00015
107S00087
107S00033 107S00034
107S00071
107S0248 107S0250
128S00009 128S00015
128S00070 128S00015
128S00010
128S00026
128S00031
128S00058 128S00018
128S00069
128S00062 128S00067
128S0364
128S0311 128S0329
128S0325 128S0397
131S00134 131S00041
132S00064
138S00084 138S00060
138S0703
138S0700
138S0689
138S0706
138S00106
138S00015
138S0846 138S0811
138S0775
138S00086
152S00381 152S1129
152S00343
152S00358
152S00367
152S00403
152S1872
155S0659
155S0694 155S0387
155S00155 155S0441
155S0660 155S0513
155S00007 155S0667
155S00034 155S0706
155S00203 155S0894
155S00115 155S00114
107S00011
107S00029
107S00053
107S00076107S00044
107S0085107S00070
107S0251107S0249
128S00011
128S00011
128S00011
128S00067
128S0264
132S0409
138S00035138S00077
138S0648
138S0641
138S0701
138S0709138S0864
138S0719138S1103
138S0739
138S0754
138S0777
138S0831138S00032
138S0831138S00049
138S0860
138S0884
138S1101138S0738
152S1682
152S00048152S00363
152S00208
152S00266
152S00322
152S00361
155S0382
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
ALT_CMN
ALT_CMN
TFTALL
TABLE_ALT_ITEM
YAGEOALL
TABLE_ALT_ITEM
ALT_CMN TFTALL
TABLE_ALT_ITEM
ALT_CMN ALL
YAGEO
TABLE_ALT_ITEM
ALT_CMN ALL CYNTEC
TABLE_ALT_ITEM
ALT_CMN TDKALL
TABLE_ALT_ITEM
ALT_CMN ALL TFT
TABLE_ALT_ITEM
ALL TFTALT_CMN
TABLE_ALT_ITEM
ALT_CMN KEMETALL
TABLE_ALT_ITEM
PANASONICALLALT_CMN
TABLE_ALT_ITEM
PANASONICALLALT_CMN
TABLE_ALT_ITEM
ALT_CMN
ALT_CMN
ALL
ALL ROHM
NEC
TABLE_ALT_ITEM
TABLE_ALT_ITEM
ALT_CMN ROHMALL
TABLE_ALT_ITEM
ALT_CMN ALL ROHM
TABLE_ALT_ITEM
NECALT_CMN ALL
TABLE_ALT_ITEM
ALT_CMN ALL
SANYO 2ND FACTORY
TABLE_ALT_ITEM
NEC ALT TO SANYOALT_CMN ALL
TABLE_ALT_ITEM
ALT_CMN
ALL PANASONIC
TABLE_ALT_ITEM
ALT_CMN ALL TAIYO YUDEN
TABLE_ALT_ITEM
ALT_CMN
ALL MURATA
TABLE_ALT_ITEM
TAIYO YUDENALT_CMN ALL
TABLE_ALT_ITEM
ALL KYOCERAALT_CMN138S00093 138S00035
TABLE_ALT_ITEM
TAIYO YUDENALLALT_CMN
TABLE_ALT_ITEM
ALT_CMN MURATA
ALL
TABLE_ALT_ITEM
ALT_CMN ALL MURATA
TABLE_ALT_ITEM
ALT_CMN ALL
MURATA
TABLE_ALT_ITEM
ALT_CMN MULTIPLEALL
TABLE_ALT_ITEM
ALLALT_CMN
ALT_CMN
ALL
ALLALT_CMN
ALT_CMN ALL
ALT_CMN ALL
ALT_CMN TAIYO YUDEN
ALT_CMN
ALL
ALL KYOCERA
ALL
ALT_CMN
ALL TAIYO YUDEN
ALLALT_CMN
ALT_CMN
ALLALT_CMN
ALT_CMN
ALT_CMN
ALL NEC
ALL CHILISIN
TAIYO YUDEN
TABLE_ALT_ITEM TABLE_ALT_ITEM
TABLE_ALT_ITEM
KYOCERA
TABLE_ALT_ITEM
MULTIPLE
TABLE_ALT_ITEM
SAMSUNG
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
SAMSUNGALT_CMN
TABLE_ALT_ITEM
TABLE_ALT_ITEM
SAMSUNG
TABLE_ALT_ITEM
CHILISINALL
TABLE_ALT_ITEM
MURATA
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
ALL NECALT_CMN
TABLE_ALT_ITEM
ALT_CMN CHILISIN
ALT_CMN
ALL
TABLE_ALT_ITEM
ALL MURATA
TABLE_ALT_ITEM
MURATAALLALT_CMN
TABLE_ALT_ITEM
ALL MURATAALT_CMN
TABLE_ALT_ITEM
ALLALT_CMN
ALLALT_CMN
ALT_CMN
ALT_CMN ALL
ALT_CMN ALL
TDK
TABLE_ALT_ITEM
MURATA
TABLE_ALT_ITEM
TAIYO YUDENALL
TABLE_ALT_ITEM
MURATA
TABLE_ALT_ITEM
TAIYO YUDEN
TABLE_ALT_ITEM
MURATAALLALT_CMN
More Alternate Parts
PART NUMBER
197S00046 197S00036
197S00047
197S00048
197S00053
197S00036
197S00036
197S00050
197S00050197S00054
197S00055 197S00050
311S0271311S00008
311S00060
311S0273
311S00004 311S0370
311S0508311S00013
311S0543311S00122
311S0596
311S00097
353S00711
353S00712
311S0593
311S00036
353S2073
353S2216
353S3239353S00107
353S00854
353S4342
353S4398353S00769
353S4471353S00525
371S0558371S0713
371S0602 INFINEONALT_CMN ALL371S00074
371S00077371S0704
371S00089 371S00085
372S0186
372S00016
376S1053
372S0185
372S00015
376S0604
376S0678376S1106
376S00014
376S0761
376S0761376S00086
376S1080
376S0820
376S00074 376S0855
376S00146 376S1061
376S1128376S1089
377S00031 377S0178
377S00017377S00048
377S0155
377S00011
740S0144 740S0118
740S00028 740S0118
740S00003
740S0135
740S0159740S00027
740S00002740S00033
740S00007
740S00019
ALT_CMN EPSON
ALT_CMN
ALT_CMN
ALT_CMN ALL
ALT_CMN DIODES INC
ALT_CMN ALL
ALT_CMN
ALT_CMN ALL
ALT_CMN
ALT_CMN
ALT_CMN
ALT_CMN
ALT_CMN
ALT_CMN
ALT_CMN ALL
ALT_CMN ALLMURATA
ALT_CMN ALL
ALT_CMN ALL
ALT_CMN ALL
ALT_CMN ALL BUSSMANN
ALT_CMN
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
ALL
TABLE_ALT_ITEM
ALL
KYOCERA
TABLE_ALT_ITEM
MURATAALL
TABLE_ALT_ITEM
ALLALT_CMN
KYOCERA
TABLE_ALT_ITEM
NDK
TABLE_ALT_ITEM
MURATAALLALT_CMN
TABLE_ALT_ITEM
ALL
TABLE_ALT_ITEM
ALLALT_CMN DIODES INC
TABLE_ALT_ITEM
ON SEMI
TABLE_ALT_ITEM
ALLALT_CMN DIODES INC
TABLE_ALT_ITEM
DIODES INCALT_CMN ALL
TABLE_ALT_ITEM
TIALL
TABLE_ALT_ITEM
DIODES INC
TABLE_ALT_ITEM
ALL ON SEMI
TABLE_ALT_ITEM
ALL ON SEMI
TABLE_ALT_ITEM
ON SEMIALL
TABLE_ALT_ITEM
ALL
ST MICRO
TABLE_ALT_ITEM
DIODES INCALL
TABLE_ALT_ITEM
VISHAYALT_CMN ALL
TABLE_ALT_ITEM
ALL
DIODES INCALT_CMN
TABLE_ALT_ITEM
TABLE_ALT_ITEM
NXPALL
TABLE_ALT_ITEM
ALLALT_CMN
DIODES INC
TABLE_ALT_ITEM
NXPALLALT_CMN
TABLE_ALT_ITEM
ALLALT_CMN
DIODES INC
TABLE_ALT_ITEM
DIODES INC
TABLE_ALT_ITEM
FAIRCHILDALLALT_CMN
TOSHIBA
TABLE_ALT_ITEM
DIODES INC.ALLALT_CMN
TABLE_ALT_ITEM
ALLALT_CMN DIODES INC
TABLE_ALT_ITEM
ALLALT_CMN TOSHIBA
TABLE_ALT_ITEM
ALL ROHMALT_CMN
TABLE_ALT_ITEM
NXP
TABLE_ALT_ITEM
ON SEMIALT_CMN ALL
TABLE_ALT_ITEM
ST MICRO
TABLE_ALT_ITEM
ALL
ON SEMIALT_CMN
TABLE_ALT_ITEM
LITTELFUSE
TABLE_ALT_ITEM
TABLE_ALT_ITEM
ALLALT_CMN
AEM, INC.
TABLE_ALT_ITEM
BOURNSALL
TABLE_ALT_ITEM
ALLALT_CMN
THINKING
TABLE_ALT_ITEM
BOURNSALT_CMN ALL
D
C
B
A
DESIGN: X502/MLB_CATZ
合肥怡飞苹果维修qq:82669515 qq群: 241000
LAST CHANGE: Fri Aug 5 13:34:33 2016
PAGE TITLE
BOM Configuration
DRAWING NUMBER SIZE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=NO COST ITEMS
8 7 5 4 2 1
36
IV ALL RIGHTS RESERVED
REVISION
BRANCH
PAGE
SHEET
051-02265
1.0.0
3 OF 500
3 OF 73
D
A
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
345678
2 1
D
MOUNTING HOLES
998-03850
SH0400
4.0R3.6-NSP
1
SH0401
4.0R3.6-NSP
1
SH0430
POGO-2.3OD-4.1H-SM
SM
1
SH0434
POGO-2.3OD-4.1H-SM
SM
1
POGO PINS
870-01680
SH0431
POGO-2.3OD-4.1H-SM
SM
1
SH0435
POGO-2.3OD-4.1H-SM
SM
1
SH0437
POGO-2.3OD-4.1H-SM
SM
1
SH0436
POGO-2.3OD-4.1H-SM
SM
1
870-02068
SH0432
POGO-2.0OD-2.95H-SM-1
SM
1
SH0433
POGO-2.0OD-2.95H-SM-1
SM
1
D
C
FAN MOUNTING HOLE
998-03850
SH0410
TH-NSP
1
SL-2.6X2.0-4.7X4.1
SH0450
2.8OD1.2ID-1.44H-SM
1
2
TOP STANDOFFS
SH0451
2.8OD1.2ID-1.44H-SM
1
2
SH0455
2.8OD1.2ID-1.44H-SM
1
2
860-00385
SH0452
2.8OD1.2ID-1.44H-SM
1
2
SH0453
2.8OD1.2ID-1.44H-SM
1
2
SH0457
2.8OD1.2ID-1.44H-SM
1
2
C
B
PLATED HOLES
SH0420
TH-NSP
1
SL-3.38X2.1-5.88X4.6
998-06494
SH0421
TH-NSP
1
SL-3.36X2.1-5.86X4.6
998-03823
LARGER SLOT, NEAR ANTENNA
SHIELD CANS
MEMORY CAN - TOP
SH0460
2.8OD1.2ID-3.0H-SM
1
2
BOTTOM STANDOFFS
860-00468
SH0461
2.8OD1.2ID-3.0H-SM
1
2
B
A
SH0425
TH-NSP
1
SL-3.36X2.1-5.86X4.6
SH0426
TH-NSP
1
SL-3.36X2.1-5.86X4.6
998-03823
SHIELD CAN FENCE,DRAM,MN,X520
MEMORY CAN - BOTTOM
SHIELD FENCE,BOT DRAM,SUS,PRE-MN,X520
WIRELESS CAN
合肥怡飞苹果维修qq:82669515 qq群: 241000
SHIELD CAN,EMI,WIFI,SYM,MN,TALL,X520
USB-C CAN
SHIELD CAN,AR,USB-C,THRU,X520
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
SHLD41806-07887 CRITICAL SHIELD_CAN_MEMORY_TOP
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
SHLD11806-08894 CRITICAL SHIELD_CAN_MEMORY_BOT
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
SHLD21806-07886 CRITICAL SHIELD_CAN_WIFI
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
SHLD31806-07885 CRITICAL SHIELD_CAN_USBC
BOM_COST_GROUP=MECHANICALS
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
PAGE TITLE
PD Parts
DRAWING NUMBER SIZE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
051-02265
REVISION
1.0.0
BRANCH
PAGE
4 OF 500
SHEET
4 OF 73
D
A
8 7 5 4 2 1
36
345678
2 1
D
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DP_DDI1_ML_C_N<0> DP_DDI1_ML_C_P<0> DP_DDI1_ML_C_N<1> DP_DDI1_ML_C_P<1> DP_DDI1_ML_C_N<2> DP_DDI1_ML_C_P<2> DP_DDI1_ML_C_N<3> DP_DDI1_ML_C_P<3>
DP_DDI2_ML_C_N<0> DP_DDI2_ML_C_P<0> DP_DDI2_ML_C_N<1> DP_DDI2_ML_C_P<1> DP_DDI2_ML_C_N<2> DP_DDI2_ML_C_P<2> DP_DDI2_ML_C_N<3> DP_DDI2_ML_C_P<3>
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
CRITICAL
OMIT_TABLE
U0500
SKL-ULT-2+3E
TBD BGA
SYM 1 OF 20
EDP
DDI
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
EDP_ML_C_N<0> EDP_ML_C_P<0> EDP_ML_C_N<1> EDP_ML_C_P<1> EDP_ML_C_N<2> EDP_ML_C_P<2> EDP_ML_C_N<3> EDP_ML_C_P<3>
EDP_AUXCH_C_N EDP_AUXCH_C_P
NC
DP_DDI1_AUXCH_C_N DP_DDI1_AUXCH_C_P DP_DDI2_AUXCH_C_N DP_DDI2_AUXCH_C_P
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
D
72 66
72 66
72 66
72 66
72 66
72 66
72 66
72 66
66
66
28
28
28
28
C
69 10 8
=PP0V95_S0_CPU_VCCIO
PLACE_NEAR=U0500.E52:15.24MM
1
R0530
24.9
1% 1/20W MF 201
2
17 5
28
28
28 5
72 66
IN
IN
IN
OUT
IN
XDP_USB_EXTD_OC_L DP_DDPB_HPD
DP_DDPC_HPD TP_PCH_GPP_E15
70
JTAG_ISP_TDO DP_INT_HPD
EDP_COMP
DISPLAY SIDEBANDS
B9
GPP_E12/USB2_OC3*
L9
GPP_E13/DDPB_HPD0
L7
GPP_E14/DDPC_HPD1
L6
GPP_E15/DDPD_HPD2
N9
GPP_E16/DDPE_HPD3
L10
GPP_E17/EDP_HPD
E52
EDP_RCOMP
GPP_E7/CPU_GP1
GPP_E8/SATALED*
GPP_E9/USB2_OC0*
GPP_E10/USB2_OC1*
GPP_E11/USB2_OC2*
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
A7
H1
A9
C9
D9
R12
R11
U13
XDP_PCH_OBSDATA_A3 XDP_PCH_OBSDATA_B0
XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L
EDP_BKLT_EN EDP_BKLT_PWM EDP_PANEL_PWR_EN
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
17
17
17 5
17 5
17 5
68 65
72 66
72 66
C
B
12
12
FOR FUTURE PRODUCT PER PDG
=PP1V8_SUS_PCH_VCC1P8_U12 =PP1V8_SUS_PCH_VCC1P8_U11
NC NC NC NC NC
NC NC
AW69
AW68
AU56
AW48
C7
U12
U11
H11
G46
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
OMIT_TABLE
U0500
SKL-ULT-2+3E
TBD BGA
SYM 20 OF 20
SPARE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVDRSVD
RSVDRSVD
F6
E3
C11
B11
A11
D12
C12
F52
F46
NC NC NC NC NC NC NC NC NC
B
A
=PP3V3_SUS_PCH_VCCPRIM
R0550 R0551 R0552 R0553
100K 100K 100K 100K
=PP3V3_S0_PCH
R0554
10K
69 12 8
21
21
21
21
69 60 19 16 14 13
201MF1/20W5%
201MF1/20W5%
201MF1/20W5%
201MF1/20W5%
XDP_USB_EXTA_OC_L XDP_USB_EXTB_OC_L XDP_USB_EXTC_OC_L XDP_USB_EXTD_OC_L
17 5
17 5
17 5
17 5
合肥怡飞苹果维修qq:82669515 qq群: 241000
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
PAGE TITLE
A
CPU GFX
21
201MF1/20W5%
JTAG_ISP_TDO
28 5
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
IV ALL RIGHTS RESERVED
DRAWING NUMBER SIZE
051-02265
REVISION
D
1.0.0
BRANCH
PAGE
5 OF 500
SHEET
5 OF 73
8 7 5 4 2 1
36
345678
2 1
D
69 17 10 8
68 54 40 39
69 59 54 19 14 10 8
=PP1V_S0SW_CPU_VCCSTG
PLACE_NEAR=R0611:1MM
R0610
BI
CPU_PROCHOT_L
PLACE_NEAR=U0500.C65:25.4MM
=PP1V_S3_CPU_VCCST
1
1K
5%
1/20W
MF
201
2
R0611
499
2 1
1%
1/20W
MF
201
40 39
OUT
PLACE_NEAR=U0500.C63:254MM
1
R0612
1K
5% 1/20W MF 201
2
39 19
68
40
OUT
BI
CPU_CATERR_L CPU_PECI
CPU_PROCHOT_R_L
PM_THRMTRIP_L
19
19
19
19
13
17
13
13
BI
BI
BI
BI
XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3>
MLB_RAMCFG4
IN
XDP_PCH_OBSDATA_D2
OUT
BT_PWRRST_L
OUT
BT_TIMESTAMP
OUT
PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP
OPC_RCOMP
NC
D63
A54
C65
C63
A65
C55
D55
B54
C56
V1
H3
BA5
AY5
AT16
AU16
H66
H65
OMIT_TABLE
U0500
SKL-ULT-2+3E
TBD BGA
CATERR*
PECI
PROCHOT*
THERMTRIP*
SKTOCC*
BPM[0]*
BPM[1]*
BPM[2]*
BPM[3]*
GPP_D21/SPI1_IO2
GPP_E1/SATAXPCIE1/SATAGP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
SYM 4 OF 20
CPU MISC
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST*
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST*
JTAGX
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
XDP_CPU_TCK XDP_CPU_TDI XDP_CPU_TDO XDP_CPU_TMS XDP_CPU_TRST_L
XDP_PCH_TCK XDP_PCH_TDI XDP_PCH_TDO XDP_PCH_TMS XDP_PCH_TRST_L PCH_JTAGX
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
BI
D
72 17
72 17
72 17
72 17
72 17
72 17
72 17
72 17
72 17
72 17
17
C
B
A
CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CPU_CFG<4>
17 6
EDP_ENABLE
1
R0634
1K
5% 1/20W MF 201
2
R0681
49.9
1%
1/20W
MF
201
1
R0682
49.9
2
PLACE_NEAR=U0500.AT16:12.7MM
R0680
49.9
1
R0683
49.9
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
1%
1/20W
MF
201
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
70
70
1%
1/20W
MF
201
2
PLACE_NEAR=U0500.AU16:12.7MM
72 17
17 6
72 17
1
1%
1/20W
MF
201
2
合肥怡飞苹果维修qq:82669515 qq群: 241000
1
R0684
49.9
2
PLACE_NEAR=U0500.H66:12.7MM
1
1%
1/20W
MF
201
2
PLACE_NEAR=U0500.H65:12.7MM
CPU_CFG<0> CPU_CFG<1> CPU_CFG<2> CPU_CFG<3> CPU_CFG<4> CPU_CFG<5> CPU_CFG<6> CPU_CFG<7> CPU_CFG<8> CPU_CFG<9> CPU_CFG<10> CPU_CFG<11> CPU_CFG<12> CPU_CFG<13> CPU_CFG<14> CPU_CFG<15>
CPU_CFG<16> CPU_CFG<17>
CPU_CFG<18> CPU_CFG<19>
CPU_CFG_RCOMP
ITP_PMODE
TP_CPU_RSVD_BA70 TP_CPU_RSVD_BA68
NC NC
NC NC
NC NC
NC NC
NC NC
NC
NC
NC NC
NC
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
J71
J68
F65
G65
F61
E61
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
RSVD
RSVD
VSS
VSS
RSVD
RSVD
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
OMIT_TABLE
U0500
SKL-ULT-2+3E
TBD BGA
SYM 19 OF 20
RESERVED
PROC_SELECT*
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
TP5
TP6
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TP4
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TP1
TP2
VSS
ZVM*
RSVD_TP
RSVD_TP
MSM*
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
TP_CPU_RSVD_BB68 TP_CPU_RSVD_BB69
TP_CPU_RSVD_AK13 TP_CPU_RSVD_AK12
NC NC
TP_CPU_AU5 TP_CPU_AT5
NC NC NC NC
NC NC
NC
NC NC
NC NC
NC NC
TP_CPU_BB5
NC NC
NC
NC NC
NC NC
TP_CPU_AY4 TP_CPU_BB3
CPU_ZVM_L
TP_CPU_RSVD_AW71 TP_CPU_RSVD_AW70
CPU_MSM_L
NCNC
70
70
19
70
70
70
70
70
70
CONNECT TO OPC VRS
CONNECT TO OPC VRS
70
70
OUT
OUT
59
59
BOM_COST_GROUP=CPU & CHIPSET
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
PAGE TITLE
CPU MISC/JTAG/CFG/RSVD
DRAWING NUMBER SIZE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
051-02265
REVISION
1.0.0
BRANCH
PAGE
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SHEET
6 OF 73
D
C
B
A
8 7 5 4 2 1
36
合肥怡飞苹果维修qq:82669515 qq群: 241000
7 OF 73
7 OF 500
1.0.0
051-02265
MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQS_P<5>
MEM_B_DQ<55>
MEM_B_DQ<52>
MEM_A_DQ<49> MEM_A_DQS_P<3>
MEM_B_DQ<40>
MEM_B_DQ<36>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<6>
MEM_B_DQ<10>
MEM_B_DQS_P<3>
MEM_B_DQS_P<2>
CPU_DIMMB_VREFDQ
CPU_DIMMA_VREFDQ
MEM_A_DQS_P<7>
MEM_A_DQS_P<4>
MEM_A_DQ<15>
MEM_A_DQ<47>
MEM_A_DQ<51> MEM_A_DQ<52>
MEM_A_DQ<55> MEM_A_DQ<56>
MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>
MEM_A_DQ<10>
MEM_A_DQ<5>
MEM_A_DQ<42>
MEM_A_DQ<17>
MEM_A_DQ<54>
MEM_A_CKE<0>
MEM_A_DQ<23>
MEM_A_DQ<8>
MEM_A_DQ<31>
MEM_A_DQ<14>
MEM_A_DQ<12>
MEM_A_DQ<29> MEM_A_DQ<30>
MEM_A_DQ<21>
MEM_A_CKE<2> MEM_A_CKE<3>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<22>
MEM_A_DQ<3>
MEM_A_DQ<20>
MEM_A_DQ<40>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<16>
MEM_A_DQ<27> MEM_A_DQ<28>
MEM_A_DQ<37>
MEM_A_CAB<0>
MEM_A_DQ<58>
MEM_A_DQ<50>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<36>
MEM_A_DQ<41>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<57>
MEM_A_DQ<53>
MEM_A_DQ<45>
MEM_A_DQ<43>
MEM_A_DQS_N<0>
MEM_A_CAB<7>
MEM_A_CAB<1>
MEM_A_CAA<9>
MEM_A_CAA<8>
MEM_A_CAA<7>
MEM_A_CAA<6>
MEM_A_CAA<2>
MEM_A_CAB<2>
MEM_A_CAB<4>
MEM_A_CAB<9>
MEM_A_CAA<1>
MEM_A_CAA<5>
MEM_A_CAA<4>
MEM_A_CAB<6>
MEM_A_CAB<5>
MEM_A_CKE<1>
MEM_A_CS_L<0> MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_CLK_P<1> MEM_A_CLK_N<1>
MEM_A_CLK_P<0>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_N<3>
MEM_A_DQS_P<1>
MEM_A_DQS_N<4>
MEM_A_DQS_N<2>
MEM_A_DQS_N<1>
MEM_A_DQS_N<7>
MEM_A_DQS_P<5>
MEM_A_DQS_P<0>
MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3>
MEM_B_DQS_P<6> MEM_B_DQS_P<7>
MEM_B_DQS_P<4>
MEM_B_DQS_P<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>
MEM_B_DQS_N<4>
MEM_B_DQS_N<3>
MEM_B_DQS_N<2>
MEM_B_DQS_N<1>
MEM_B_DQS_N<0>
MEM_B_CAB<9>
MEM_B_CAB<8>
MEM_B_CAB<7>
MEM_B_CAB<6>
MEM_B_CAB<5>
MEM_B_CAB<4>
MEM_B_CAB<3>
MEM_B_CAB<2>
MEM_B_CAB<1>
MEM_B_CAB<0>
MEM_B_CAA<9>
MEM_B_CAA<8>
MEM_B_CAA<7>
MEM_B_CAA<6>
MEM_B_CAA<5>
MEM_B_CAA<4>
MEM_B_CAA<3>
MEM_B_CAA<2>
MEM_B_CAA<1>
MEM_B_CAA<0>
MEM_B_ODT<0>
MEM_B_DQ<29>
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_CKE<3>
MEM_B_CKE<2>
MEM_B_CKE<1>
MEM_B_CKE<0>
MEM_B_CLK_P<0>
MEM_B_CLK_P<1> MEM_B_CLK_N<1>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<23>
MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22>
MEM_B_DQ<24>
MEM_B_DQ<27> MEM_B_DQ<28>
MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32>
MEM_B_DQ<35>
MEM_B_DQ<37>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<60>
MEM_B_DQ<56>
MEM_B_DQ<59>
MEM_B_DQ<62>
MEM_A_DQ<0>
MEM_A_DQS_N<5>
MEM_A_DQS_P<2>
MEM_B_DQ<58>
MEM_B_DQ<51>
MEM_A_DQ<1> MEM_A_DQ<2>
MEM_A_CAA<3>
MEM_B_DQ<7> MEM_B_DQ<8>
MEM_A_CAB<3>
MEM_A_DQ<26>
MEM_A_DQ<6>
MEM_A_DQ<44>
MEM_A_DQ<46>
MEM_A_DQ<48>
MEM_B_DQ<57>
MEM_B_DQ<38>
MEM_A_CAB<8>
MEM_A_DQ<13>
MEM_A_DQ<11>
MEM_A_DQ<9>
MEM_A_CAA<0>
MEM_B_DQ<11>
MEM_B_DQ<9>
MEM_B_DQ<14> MEM_B_DQ<15>
MEM_A_CLK_N<0> MEM_B_CLK_N<0>
CPU_DDR_RCOMP<2>
CPU_DDR_RCOMP<1>
CPU_DDR_RCOMP<0>
MEM_B_DQ<63>
MEM_B_DQ<61>
MEM_B_DQ<39>
CPU_DIMM_VREFCA
MEM_A_DQ<7>
MEM_A_DQ<4>
PM_MEMVTT_EN
BOM_COST_GROUP=CPU & CHIPSET
CPU LPDDR3 Interface
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
201
MF
1/20W
1%
PLACE_NEAR=U0500.AR18:6MM
200
2
1
R0702
201
MF
1/20W
1%
PLACE_NEAR=U0500.AT18:6MM
80.6
2
1
R0701
201
MF
1/20W
1%
PLACE_NEAR=U0500.AU18:6MM
162
2
1
R0700
62
72 25 23
72 25 23
72 25 24
72 25 24
72 25 21
72 25 21
72 25 22
72 25 22
72 25 22 21
72 25 22 21
72 25 21
72 25 21
72 25 22
72 25 22
72 25 22 21
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72
71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
AT13
AU18
AT18
AR18
AP43
AW42
BA42
BA47
BB46
AR21
AR27
BA26
AY30
AR32
AR38
BA34
AY38
AR22
AR25
AY26
BA30
AT32
AT38
AY34
BA38
AN21
AP21
AP22
AN22
AT21
AU21
AU22
AT22
AP25
AN25
AN27
AP27
AU25
AT25
AT27
AU27
BB25
BA25
BA27
BB27
AW25
AY25
AW27
AY27
BB29
BA29
BA31
BB31
AW29
AY29
AW31
AY31
AP30
AR30
AP33
AR33
AT30
AU30
AU33
AT33
AR37
AP37
AP40
AR40
AU37
AT37
AT40
AU40
BB33
BA33
BA35
BB35
AW33
AY33
AW35
AY35
BB37
BA37
BA39
BB39
AW37
AY37
AW39
AY39
AY42
BB42
AP46
AP45
AN46
AN45
AP53
AN55
AP55
AN56
BA46
AY46
AW46
BA44
AY47
BB44
AW44
AY44
AY43
BA43
AN52
AN53
AN48
AN50
AP52
AP48
BB48
BA48
AP50
AY48
AN43
U0500
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
AW67
AY67
BA67
AY68
AT52
AT43
AT45
BB52
BA50
AR60
AR65
BA60
AY64
AG70
AH65
AT70
AM69
AR61
AR66
AY60
BA64
AG69
AH66
AT69
AM70
AU60
AT60
AP61
AN61
AN60
AP60
AU61
AT61
AU65
AT65
AP66
AN66
AN65
AP65
AU66
AT66
AY59
BA59
AY61
BB61
AW59
BB59
AW61
BA61
BB63
BA63
AY65
BA65
AY63
AW63
AW65
BB65
AH69
AH70
AF69
AF71
AH68
AH71
AF68
AF70
AK66
AK67
AF67
AF66
AK64
AK65
AF64
AF65
AU69
AU70
AR69
AR71
AU68
AU71
AR68
AR70
AN71
AN70
AL69
AL70
AN69
AN68
AL68
AL71
AU43
AU45
AT55
AT53
AU55
AU53
AY56
AW56
BB56
BA56
AY50
BB50
AT50
AT48
AY51
AU52
AU50
AT46
AU48
AU46
AY54
BA55
BA54
AW54
AY55
AW52
AY52
BA52
BB54
BA51
AW50
U0500
72 25 24
72 25 24
72 25 24
72 25 24
72 25 24
72 25 24
72 25 24
72 25 24
72 25 24
72 25 23
72 25 24
72 25 23
72 25 23
72 25 23
72 25 23
72 25 23
72 25 23
72 25 23
72 25 23
72 25 23
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 25 22
72 25 22
72 25 22
72 25 22
72 25 22
72 25
22
72 25 22
72 25 22
72 25 22
72 25 22
72 25 21
72 25 21
72 25 21
72 25 21
72 25 21
72 25 21
72 25 21
72 25 21
72 25 21
72 25 21
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 25 24 23
72 25 24 23
72 25 24 23
72 25 24
72 25 24
72 25 23
72 25 23
20
20
20
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
72 71
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
NC
NC
NC
NC
NC
NCNC
OUT
OUT
OUT
OUT
NCNC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
LPDDR3 NON-INTERLEAVED
SYM 3 OF 20
DDR1_DQ[0]
DDR1_DQ[1]
DDR1_DQ[2]
DDR1_DQ[3]
DDR1_MA[3]
DDR1_MA[4]
DRAM_RESET*
DDR_RCOMP[2]
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR1_PAR
DDR1_ALERT*
DDR1_DQSP[6]
DDR1_DQSP[7]
DDR1_DQSP[5]
DDR1_DQSP[4]
DDR1_DQSP[3]
DDR1_DQSP[2]
DDR1_DQSP[1]
DDR1_DQSP[0]
DDR1_DQSN[7]
DDR1_DQSN[6]
DDR1_DQSN[5]
DDR1_DQSN[4]
DDR1_DQSN[3]
DDR1_DQSN[2]
DDR1_DQSN[1]
DDR1_DQSN[0]
DDR1_CAB[9]
DDR1_CAB[8]
DDR1_CAB[7]
DDR1_CAB[6]
DDR1_CAB[5]
DDR1_CAB[4]
DDR1_CAB[3]
DDR1_CAB[2]
DDR1_CAB[1]
DDR1_CAB[0]
DDR1_CAA[9]
DDR1_CAA[8]
DDR1_CAA[7]
DDR1_CAA[6]
DDR1_CAA[5]
DDR1_CAA[4]
DDR1_CAA[3]
DDR1_CAA[2]
DDR1_CAA[1]
DDR1_CAA[0]
DDR1_ODT[1]
DDR1_ODT[0]
DDR1_DQ[33]
DDR1_DQ[29]
DDR1_CS[1]*
DDR1_CS[0]*
DDR1_CKE[3]
DDR1_CKE[2]
DDR1_CKE[1]
DDR1_CKE[0]
DDR1_CKN[0]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKN[1]
DDR1_DQ[8]
DDR1_DQ[6]
DDR1_DQ[5]
DDR1_DQ[4]
DDR1_DQ[7]
DDR1_DQ[9]
DDR1_DQ[19]
DDR1_DQ[18]
DDR1_DQ[17]
DDR1_DQ[16]
DDR1_DQ[15]
DDR1_DQ[14]
DDR1_DQ[10]
DDR1_DQ[13]
DDR1_DQ[12]
DDR1_DQ[11]
DDR1_DQ[23]
DDR1_DQ[20]
DDR1_DQ[21]
DDR1_DQ[22]
DDR1_DQ[24]
DDR1_DQ[25]
DDR1_DQ[26]
DDR1_DQ[27]
DDR1_DQ[28]
DDR1_DQ[30]
DDR1_DQ[31]
DDR1_DQ[32]
DDR1_DQ[34]
DDR1_DQ[35]
DDR1_DQ[36]
DDR1_DQ[37]
DDR1_DQ[38]
DDR1_DQ[39]
DDR1_DQ[40]
DDR1_DQ[46]
DDR1_DQ[47]
DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[42]
DDR1_DQ[41]
DDR1_DQ[45]
DDR1_DQ[44]
DDR1_DQ[43]
DDR1_DQ[60]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]
SYM 2 OF 20
LPDDR3 NON-INTERLEAVED0
DDR0_PAR
DDR0_ALERT*
DDR0_DQSP[7]
DDR0_DQSP[4]
DDR0_DQSP[1]
DDR0_DQSP[0]
DDR0_DQSN[7]
DDR0_DQSN[6]
DDR0_DQSN[5]
DDR0_DQSN[4]
DDR0_DQSN[3]
DDR0_DQSN[2]
DDR0_DQSN[1]
DDR0_DQSN[0]
DDR0_MA[3]
DDR0_DQ[49]
DDR_VTT_CNTL
DDR1_VREF_DQ
DDR0_VREF_DQ
DDR_VREF_CA
DDR0_MA[4]
DDR0_DQSP[6]
DDR0_DQSP[5]
DDR0_DQSP[3]
DDR0_DQSP[2]
DDR0_CAB[9]
DDR0_CAB[8]
DDR0_CAB[7]
DDR0_CAB[6]
DDR0_CAB[4]
DDR0_CAB[5]
DDR0_CAB[3]
DDR0_CAB[2]
DDR0_CAB[1]
DDR0_CAB[0]
DDR0_DQ[24]
DDR0_CAA[9]
DDR0_CAA[8]
DDR0_CAA[7]
DDR0_CAA[6]
DDR0_CAA[5]
DDR0_CAA[4]
DDR0_CAA[3]
DDR0_CAA[2]
DDR0_CAA[1]
DDR0_CAA[0]
DDR0_ODT[1]
DDR0_ODT[0]
DDR0_CKN[1]
DDR0_CKP[0]
DDR0_CKE[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_CS[0]*
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKN[0]
DDR0_DQ[3]
DDR0_DQ[61]
DDR0_DQ[62]
DDR0_DQ[60]
DDR0_DQ[59]
DDR0_DQ[58]
DDR0_DQ[57]
DDR0_DQ[56]
DDR0_DQ[53]
DDR0_DQ[54]
DDR0_DQ[55]
DDR0_DQ[51]
DDR0_DQ[52]
DDR0_DQ[48]
DDR0_DQ[50]
DDR0_DQ[47]
DDR0_DQ[46]
DDR0_DQ[45]
DDR0_DQ[43]
DDR0_DQ[44]
DDR0_DQ[41]
DDR0_DQ[42]
DDR0_DQ[40]
DDR0_DQ[39]
DDR0_DQ[38]
DDR0_DQ[36]
DDR0_DQ[37]
DDR0_DQ[35]
DDR0_DQ[34]
DDR0_DQ[33]
DDR0_DQ[32]
DDR0_DQ[31]
DDR0_DQ[30]
DDR0_DQ[28]
DDR0_DQ[29]
DDR0_DQ[25]
DDR0_DQ[26]
DDR0_DQ[27]
DDR0_DQ[21]
DDR0_DQ[20]
DDR0_DQ[19]
DDR0_DQ[18]
DDR0_DQ[17]
DDR0_DQ[16]
DDR0_DQ[15]
DDR0_DQ[14]
DDR0_DQ[13]
DDR0_DQ[12]
DDR0_DQ[11]
DDR0_DQ[10]
DDR0_DQ[9]
DDR0_DQ[8]
DDR0_DQ[7]
DDR0_DQ[6]
DDR0_DQ[2]
DDR0_DQ[1]
DDR0_DQ[0]
DDR0_CS[1]*
DDR0_CKE[0]
DDR0_CKP[1]
DDR0_DQ[63]
DDR0_DQ[23]
DDR0_DQ[22]
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
合肥怡飞苹果维修qq:82669515 qq群: 241000
R0829:
R0831:
R0830:
8 OF 73
1.0.0
8 OF 500
051-02265
CPU_VCCGTSENSE_N
CPU_VCCSASENSE_N
CPU_VCCEOPIOSENSE_N
CPU_VCCIOSENSE_N
CPU_VCCGTXSENSE_P
CPU_VIDSOUT_R
CPU_VIDSOUT
CPU_VIDSCLK_R
CPU_VIDSCLK
CPU_VIDALERT_R_L CPU_VIDALERT_L
=PP1V_S3_CPU_VCCST
CPU_VCCIOSENSE_P
CPU_VCCSASENSE_P
=PPVCCGT_S0_CPU CPU_VCCGTSENSE_P
CPU_VCCGTXSENSE_P
=PP1V_S0_CPU_VCCOPC_AB62 CPU_VCCOPCSENSE_P
=PP1V_S0_CPU_VCCEOPIO_AE62 CPU_VCCEOPIOSENSE_P
CPU_VCCGTXSENSE_N
CPU_VCCSENSE_N
CPU_VCCEOPIOSENSE_N
=PP1V_S0_CPU_VCCEOPIO_AG62
=PP1V_S0_CPU_VCCEOPIO_AE62
=PP1V_S0_CPU_VCCOPC_V62
=PP1V2_S0SW_CPU_VCCPLLOC
CPU_VCCGTSENSE_P CPU_VCCGTSENSE_N
CPU_VCCEOPIOSENSE_P
=PP0V95_S0_CPU_VCCIO
=PPVCCGTX_S0_CPU
=PP1V_S0SW_CPU_VCCSTG
=PP1V8_SUS_CPU_VCCOPC_H63
CPU_VCCOPCSENSE_P
CPU_VCCSENSE_N
CPU_VCCSENSE_P
CPU_VCCGTXSENSE_N
=PP1V_SUSSW_PCH_VCCAPLLEBB
=PP1V_SUSSW_PCH_VCCAMPHYPLL
=PP1V_SUSSW_PCH_VCCSRAM
=PP3V3_SUS_PCH_VCCSPI
=PP1V8_S0_PCH_VCCHDA_F
=PP3V3_S5_PCH_VCCDSW
=PP1V_SUSSW_PCH_VCCMPHYGT
=PPVCCPRIMECORE_SUS_PCH
=PP1V8_SUS_PCH_VCCATS
=PP3V_G3H_PCH_VCCRTC
=PP1V_SUS_PCH_VCCCLK1
=PP1V_SUS_PCH_VCCCLK2
=PP1V_SUS_PCH_VCCAPLL_F
=PP1V_S0_CPU_VCCOPC_AB62 =PP1V_S0_CPU_VCCOPC_P62
=PP1V_SUS_PCH_VCCCLK6
=PP1V_SUS_PCH_VCCCLK3
=PP3V3_SUS_PCH_VCCPRIM
=PP3V3_SUS_PCH_VCCPGPPC
=PP3V3_SUS_PCH_VCCRTCPRIM
PPDCPRTC_PCH
CPU_VCCOPCSENSE_N
=PP1V8_SUS_CPU_VCCOPC_G61
=PP1V_SUS_PCH_VCCPRIM
=PP1V_SUS_PCH_VCCPRIM
=PP1V_S0SW_CPU_VCCSTG
=PP1V_S3_CPU_VCCPLL
=PP3V3_SUS_PCH_VCCPGPPD
=PP1V8_SUS_PCH_VCCPGPPF
=PP1V_SUS_PCH_VCCPRIM
=PP3V3_SUS_PCH_VCCPRIM
CPU_VCCOPCSENSE_N
=PP1V2_S3_CPU_VDDQC
=PP1V_S3_CPU_VCCST
=PP1V_SUS_PCH_VCCMPHYAON
PP1V_S5_PCH_DCPDSW
=PP3V3_SUS_PCH_VCCPGPPB
=PP3V3_SUS_PCH_VCCPGPPA
=PP3V3_SUS_PCH_VCCPGPPE
=PP3V3_SUS_PCH_VCCPGPPG
=PPVCCSA_S0_CPU
=PP1V2_S3_CPU_VDDQ
=PPVCC_S0_CPU
CPU_VCCIOSENSE_P
CPU_VCCSASENSE_N CPU_VCCSASENSE_P
=PP1V_SUS_PCH_VCCCLK4
VCCPRIM_CORE_VID0 VCCPRIM_CORE_VID1
=PP1V_SUS_PCH_VCCCLK5
=PPVCC_S0_CPU
=PPVCCGT_S0_CPU
CPU_VCCSENSE_P
=PP1V_SUS_PCH_FUSE
=PPVCCGTX_S0_CPU
=PPVCCSA_S0_CPU
=PP0V95_S0_CPU_VCCIO
CPU_VCCIOSENSE_N
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
CPU & PCH Power
BOM_COST_GROUP=CPU & CHIPSET
54
201
MF
1/20W
1%
100
2
1
R0828
201
MF
1/20W
1%
56
2
1
R0827
201
MF
1/20W
1%
PLACE_NEAR=U0500.B63:12.7MM
220
21
R0829
201MF1/20W5%
PLACE_NEAR=U0500.E33:50.8MM
100
2 1
R0826
201MF1/20W5%
PLACE_NEAR=U0500.AJ62:50.8MM
100
2 1
R0824
201MF1/20W5%
PLACE_NEAR=U0500.AE63:50.8MM
100
2 1
R0822
201MF1/20W5%
PLACE_NEAR=U0500.AL61:50.8MM
100
2 1
R0814
201MF1/20W5%
PLACE_NEAR=U0500.J69:50.8MM
100
2 1
R0812
201MF1/20W5%
PLACE_NEAR=U0500.H21:50.8MM
100
2 1
R0803
201MF1/20W5%
PLACE_NEAR=U0500.AM22:50.8MM
100
2 1
R0802
0201
MF
1/20W
5%
PLACE_NEAR=U0500.D64:12.7MM
0
21
R0831
0201
MF
1/20W
5%
PLACE_NEAR=U0500.A63:12.7MM
0
21
R0830
201MF1/20W5%
PLACE_NEAR=U0500.E32:50.8MM
100
21
R0825
201MF1/20W5%
PLACE_NEAR=U0500.AL63:50.8MM
100
21
R0823
201MF1/20W5%
PLACE_NEAR=U0500.AC63:50.8MM
100
21
R0821
201MF1/20W5%
PLACE_NEAR=U0500.AK62:50.8MM
100
21
R0813
201MF1/20W5%
PLACE_NEAR=U0500.J70:50.8MM
100
21
R0811
201MF1/20W5%
PLACE_NEAR=U0500.H20:50.8MM
100
21
R0804
201MF1/20W5%
PLACE_NEAR=U0500.AM23:50.8MM
100
21
R0801
70
70
59 8
59 8
59 8
59 8
54 8
54 8
61 8
61 8
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
T20
T19
AF21
AF20
AJ16
AK17
BB14
AK19
V21
V20
AF19
AF18
V19
AJ21
Y18
T1
P18
AK20
AB20
AB19
AB17
AD15
AF16
T16
Y15
Y16
AG15
AK15
P16
P15
N17
N16
N15
L1
K17
AJ19
AJ17
AD18
AD17
A10
L19
N20
L21
K19
A14
AA1
N18
V15
L15
K15
AN13
AN11
BB10
AL1
U0500
72 54 8
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
AL61J69
AK62
BB66
BB57
AU63
AU58
AM58
AM56
AM53
AM52
AM50
AM48
AL60
AL56
AL53
AL50
AL46
AL43
AK70
AK60
AK58
AK56
AK55
AK53
AK52
AK50
AK48
AK46
AK45
AK43
AK42
Y62
W71
W70
W69
W68
W67
W66
W65
W64
W63
U71
U68
U65
T62
J70
R71
R70
R69
R68
R67
R66
R65
R64
R63
N71
N70
N69
N67
N66
N64
N63
M62
L71
L70
L69
L68
L67
L66
L65
L64
L63
L62
K60
K58
K56
K55
K53
K52
K50
K48
J60
J58
J56
J55
J53
J52
J50
J48
J46
J45
J43
AC71
AC70
AC69
AC68
AC67
AC66
AC65
AC64
AA71
AA70
AA69
AA67
AA66
AA64
AA63
A66
A62
A58
A53
A48
U0500
54 8
69 8
69 8
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
AE63
AJ62
E33
D64
A63
B63
G20
V62
AC63
P62
AB62
AL63
AG62
AE62
E32
H63
G61
K43
K42
K40
K38
K37
K35
K33
J40
J37
J33
J30
G42
G40
G38
G37
G35
G33
G32
G30
AM38
AM37
AM35
AM33
AM32
AL40
AL37
AL33
AK40
AK38
AK37
AK35
AK33
A44
A39
A34
A30
K32
AK32
U0500
54 8
54
8
54
54
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
H21
AM22
AM40
BB51
BB47
BB41
BB32
BB23
AU42
AU35
AU28
AU23
A22
A18
H20
K30
K28
K27
K25
K23
J27
J23
J22
G28
G27
G25
G23
AK25
AK23
AL23
K21
K20
AM23
AM42
AM30
AM28
AL42
AL30
AK30
AK28
U0500
72 54 8
54 8
59 8
61 8
69 59 54 19 14 10 8 6
61 8
54 8
69 11 8 54 8
69 8
59 8 59 8
59 8 59 8
69 8
54 8
59
59 8
59
69 10
69 10 8 5
69 11 8
69 17
10 8 6
59
69 12
12
69 12
69 47 13
12
69 14
69 12
69 12
69 12
69 15 14 12
69
12
12
59 8
59
69 12
69
69 12 8 5
69 12
69 12
12
59
69 12 8
69 12 8
69 17 10 8 6
69 10
69
69 14
69 12 8
69 12 8 5
59 8
69 10
69 59 54 19 14 10 8 6
69 12
12
69 19 12
69 16 15 14 13
69 12
69
69 10 8
69 10
69 10 8
12
12
69 10 8
69 11 8
54 8
64 12
69 11 8
69 10 8
69 10 8 5
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
NC
OUT
OUT
OUT
OUT
OUT
NC
OUT
OUT
OUT
OUT
OUT
CPU POWER 4
SYM 15 OF 20
VCCSRAM_1P0
VCCPRIM_3P3
VCCPRIM_1P0
VCCAPLLEBB_1P0
VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSPI
VCCHDA
VCCDSW_3P3
VCCDSW_3P3
VCCDSW_3P3
VCCPRIM_1P0
VCCPRIM_1P0
VCCAPLL_1P0
VCCMPHYGT_1P0
VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCMPHYAON_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCMPHYGT_1P0
VCCPRIM_CORE
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3
VCCPRIM_1P0
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC
VCCRTC
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
OUT
SYM 13 OF 20
CPU POWER 2
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX_SENSE
VSSGTX_SENSE
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
OUT
OUT
OUT
SYM 12 OF 20
CPU POWER 1
VCCSTG
VCC
VCC
VCC
VCC
VIDSOUT
VIDSCK
VIDALERT*
VSS_SENSE
VCC_SENSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
VCCOPC
VCCOPC
VCCOPC
VCC_OPC_1P8
VSSOPC_SENSE
VCCEOPIO
VCC_OPC_1P8
VCCOPC_SENSE
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
OUT
OUT
BI
OUT
SYM 14 OF 20
CPU POWER 3
VCCSA_SENSE
VSSSA_SENSE
VSSIO_SENSE
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQC
VCCST
VDDQ
VDDQ
VDDQ
VCCSTG
VCCPLL_OC
VCCPLL
VCCPLL
合肥怡飞苹果维修qq:82669515 qq群: 241000
9 OF 500
051-02265
1.0.0
9 OF 73
TP_CPU_NCTFVSS_BB70 TP_CPU_NCTFVSS_C1
TP_CPU_NCTFVSS_BA71
TP_CPU_NCTFVSS_B71 TP_CPU_NCTFVSS_BA1
TP_CPU_NCTFVSS_AV1
TP_CPU_NCTFVSS_A5
TP_CPU_NCTFVSS_A70
CPU & PCH Grounds
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
Y21
Y20
Y19
Y17
W13
W9
W6
V18
V17
V16
U70
U69
U67
U66
U64
U63
U10
T21
T18
T17
T15
T4
T2
R13
R6
P21
P20
P19
P17
N68
N65
N21
N19
N13
N10
N6
L20
L18
L17
L16
L11
L8
L4
L2
K71
K70
K68
K67
K66
K65
K64
K63
K61
K22
K18
K16
J42
J38
J35
J32
J28
J25
J13
J11
J8
H71
H18
H15
G66
G63
G60
G58
G55
G52
G48
G45
G43
G22
G10
G6
G5
F8
U0500
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
F68
F42
F40
F38
F37
F35
F33
F32
F28
F27
F23
F22
F13
F4
F2
F1
E71
E65
E56
E53
E50
E46
E21
E18
E15
E11
E6
D69
D66
D62
D58
D53
D48
D47
D45
D44
D39
D34
D30
D26
D25
D22
D18
D14
D11
D10
D6
C25
C5
C1
BB70
BB67
BB64
BB60
BB55
BB43
BB38
BB34
BB30
BB26
BB18
BB6
BA71
BA66
BA62
BA57
BA53
BA49
BA45
BA41
BA36
BA32
BA28
BA23
BA18
BA14
BA10
BA6
BA2
BA1
B71
B66
B62
B58
B53
B48
B44
B39
B34
B30
B22
B18
B14
B10
AY66
AW66
AW64
AW62
AW60
AW57
AW55
AW53
AW51
AW49
AW47
AW45
AW43
AW41
AW38
AW36
AW34
AW32
AW30
AW28
AW26
AW23
AW21
AW18
AW16
AW14
AW12
AW10
AW8
AW6
AV71
AV70
AV69
AV68
AV1
AU38
AU32
AU20
AU15
AU10
AT71
AT68
AT63
U0500
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
AT58
AT56
AT42
AT35
AT28
AT23
AT20
AT4
AT2
AR63
AR58
AR55
AR53
AR52
AR50
AR48
AR46
AR45
AR43
AR42
AR35
AR28
AR23
AR20
AR16
AR15
AR11
AR8
AR5
AP70
AP68
AP63
AP58
AP42
AP38
AP35
AP32
AP28
AP23
AP20
AP18
AP10
AN63
AN58
AN42
AN40
AN38
AN37
AN35
AN33
AN32
AN30
AN28
AN23
AN20
AM71
AM68
AM61
AM60
AM55
AM46
AM45
AM43
AM27
AM25
AM21
AM13
AM8
AL66
AL65
AL64
AL58
AL55
AL52
AL48
AL45
AL38
AL35
AL32
AL28
AL4
AL2
AK69
AK68
AK63
AK27
AK22
AK21
AK18
AK16
AK11
AK8
AJ20
AJ18
AJ15
AJ4
AH67
AH64
AH63
AH13
AH6
AG71
AG21
AG20
AG19
AG18
AG17
AG16
AF63
AF17
AF15
AF10
AF4
AF2
AF1
AE69
AE68
AE67
AE66
AE65
AE64
AD62
AD21
AD20
AD19
AD16
AD13
AD8
AB21
AB18
AB16
AB15
AB8
AA68
AA65
AA4
AA2
A70
A67
A5
U0500
70
70
70
70
70
70
70
70
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
GND 3
SYM 18 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND2
SYM 17 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SYM 16 OF 20
GND1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
合肥怡飞苹果维修qq:82669515 qq群: 241000
051-02265
1.0.0
10 OF 500
10 OF 73
=PPVCCSA_S0_CPU
=PP1V2_S3_CPU_VDDQ
=PP1V_S3_CPU_VCCPLL
=PP1V_S0_CPU_VCCEOPIO
=PP1V2_S0SW_CPU_VCCPLLOC =PP1V_S3_CPU_VCCST =PP1V_S0SW_CPU_VCCSTG
=PP1V_S0_CPU_VCCOPC
=PP0V95_S0_CPU_VCCIO
=PP1V2_S3_CPU_VDDQC
=PPVCC_S0_CPU
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
CPU Core Decoupling
BOM_COST_GROUP=CPU & CHIPSET
0402
X6S
4V
20%
10UF
CRITICAL NOSTUFF
2
1
C1094
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10F3
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10F2
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10F1
0201
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6.3V
20%
1UF
2
1
C10F0
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C10E1
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C10E0
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10D1
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10D2
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10D3
0402
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4V
20%
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CRITICAL
2
1
C10D0
0201
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6.3V
20%
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2
1
C10D4
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6.3V
20%
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2
1
C10D5
0201
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6.3V
20%
1UF
2
1
C10D6
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C1091
0402
X6S
4V
20%
10UF
CRITICAL NOSTUFF
2
1
C1092
0402
X6S
4V
20%
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CRITICAL NOSTUFF
2
1
C1093
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C1090
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C1080
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C1081
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1082
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1083
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1084
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1085
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C1070
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1071
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1066
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C1065
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1064
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1055
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1054
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1063
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1062
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C1060
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C1061
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1053
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1052
0402
X6S
4V
20%
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CRITICAL
2
1
C1051
0402
X6S
4V
20%
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CRITICAL
2
1
C1050
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20%
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CRITICAL
3 2
1
C10G1
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CRITICAL
3 2
1
C10G0
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1010
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100I
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100J
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100K
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100L
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100M
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100N
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100O
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100P
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100Q
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100R
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100S
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100T
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100U
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100V
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100W
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100X
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100Y
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100C
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100D
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100E
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100F
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100G
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100H
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1006
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1007
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1008
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1009
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100A
0201
X6S-CERM
6.3V
20%
1UF
2
1
C100B
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1005
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1004
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1003
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1002
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1001
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1000
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10CA
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10BA
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10C6
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10B6
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10C7
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10B7
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10C8
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10B8
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10C9
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10B9
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101K
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101L
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C101A
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C101B
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101C
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101D
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101E
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101F
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101G
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101H
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101I
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C101J
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C10G4
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL NOSTUFF
3 2
1
C10H1
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C10H0
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C10C0
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10C1
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10C2
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C10C3
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10C4
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C10C5
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10B5
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C10B4
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10B3
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10B2
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10B1
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10A0
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10A1
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10A2
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10A3
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10A4
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10A5
0201
X6S-CERM
6.3V
20%
1UF
2
1
C10A6
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C10B0
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1020
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1021
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1022
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1023
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1024
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1029
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1028
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1027
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1026
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1025
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1015
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1016
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1017
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1018
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1019
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1014
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1013
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1012
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1011
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C10G3
0402
X6S
4V
20%
10UF
CRITICAL NOSTUFF
2
1
C1095
69 8
69 8
69 8
59
69 8
69
59 54 19 14 8 6 69 17 8 6
59
69 8 5
69 8
69 8
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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NOTICE OF PROPRIETARY PROPERTY:
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PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
合肥怡飞苹果维修qq:82669515 qq群: 241000
051-02265
1.0.0
11 OF 500
11 OF 73
=PPVCCGTX_S0_CPU
=PPVCCGT_S0_CPU
CPU GT Decoupling
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110L
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110K
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1105
X6S-CERM 0201
6.3V
20%
1UF
2
1
C110J
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1104
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110I
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1103
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110H
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1102
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110G
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1101
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110F
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1100
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110E
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C1161
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1157
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1156
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1150
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1194
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1195
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1151
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1196
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1152
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1197
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1153
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1198
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1154
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1199
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1155
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1140
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1130
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1141
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1131
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1142
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1132
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1143
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1133
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1144
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1134
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1145
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1135
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1146
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1147
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1136
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1137
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1148
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1138
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1149
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1139
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL NOSTUFF
3 2
1
C1164
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C1191
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1180
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1181
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1182
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1183
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1184
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1185
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1186
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1187
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1177
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1176
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1175
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1174
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1173
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1172
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1171
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1170
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1120
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1121
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1122
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1123
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1124
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1129
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1128
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1127
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1126
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1125
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1115
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C1116
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1117
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1118
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1119
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1114
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1113
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1112
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1111
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL NOSTUFF
2
1
C1110
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL NOSTUFF
3 2
1
C1190
CRITICAL
SM-COMBO
ELEC
2V
20%
220UF
3 2
1
C1163
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C1162
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C1160
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110V
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110W
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110X
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110U
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110T
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110S
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110D
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110C
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110R
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110Q
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110B
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110A
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110P
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110O
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1109
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1108
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110N
0201
X6S-CERM
6.3V
20%
1UF
2
1
C110M
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1107
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1106
69 8
69 8
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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NOTICE OF PROPRIETARY PROPERTY:
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C
345678
D
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8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
合肥怡飞苹果维修qq:82669515 qq群: 241000
FILTER PLACEHOLDERS ONLY
PCH SIDERAIL SIDE
FOR FUTURE PRODUCT PER PDG
CPU CIRCUITS GENERATE NOISE AT WIFI BAND FREQUENCIES.
USE SPECIFIC 3PF CAPS FOR BEST FILTERING OF THOSE FREQUNCIES.
12 OF 73
12 OF 500
1.0.0
051-02265
=PP1V_SUS_PCH_VCCCLK5_SRC
=PP1V_SUSSW_PCH_VCCAPLLEBB
=PP3V3_SUS_PCH_VCCPRIM
MAKE_BASE=TRUE
PP1V_SUS_PCH_VCCCLK5_F=PP3V3_SUS_PCH_VCCPGPPC
=PP1V_SUS_PCH_VCCCLK4_SRC
MAKE_BASE=TRUE
PP1V8_SUS_PCH_VCC1P8
=PP1V8_SUS_PCH_VCC1P8_SRC
=PP3V3_SUS_PCH_VCCRTCPRIM
=PP1V_SUS_PCH_VCCCLK2=PP1V_SUS_PCH_VCCCLK2_SRC
=PP1V8_SUS_PCH_VCCATS
MAKE_BASE=TRUE
PP1V8_S0_PCH_VCCHDA_F
MAKE_BASE=TRUE
PP1V_SUS_PCH_VCCAPLL_F
MAKE_BASE=TRUE
PP1V_SUS_PCH_VCCCLK4_F
=PP1V_SUS_PCH_VCCCLK4
=PP3V3_SUS_PCH_VCCPGPPE
=PP1V8_SUS_PCH_VCC1P8_U12
=PP1V_SUSSW_PCH_VCCAMPHYPLL_SRC
MAKE_BASE=TRUE
PP1V_SUS_PCH_VCCCLK2_F
=PP1V_SUS_PCH_VCCCLK5
=PP1V_SUS_PCH_VCCCLK6
=PP1V_SUSSW_PCH_VCCSRAM
=PP3V3_SUS_PCH_VCCPGPPB
MAKE_BASE=TRUE
PP1V_SUSSW_PCH_VCCAMPHYPLL_F
=PP1V_SUSSW_PCH_VCCAMPHYPLL
=PP1V8_SUS_PCH_VCC1P8_U11
=PP1V8_S0_PCH_VCCHDA_F
PP1V_S5_PCH_DCPDSW
=PP1V8_S0_PCH_VCCHDA
=PPVCCPRIMECORE_SUS_PCH
=PP1V_SUS_PCH_VCCAPLL
=PP1V_SUS_PCH_VCCMPHYAON
=PP3V_G3H_PCH_VCCRTC
=PP1V_SUS_PCH_VCCAPLL_F
PPDCPRTC_PCH
=PP1V_SUS_PCH_VCCPRIM
=PP1V_SUS_PCH_FUSE
=PP1V_SUSSW_PCH_VCCMPHYGT
L1250,L1252,L1253,L1254RES,MF,1A MAX,0OHM,5%,06034113S0022
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
PCH Decoupling
BOM_COST_GROUP=CPU & CHIPSET
0201
X7R
25V
10%
BYPASS=U0500.AK20::10MM
1000PF
2
1
C1208
0201
C0G-CERM
25V
+/-0.05PF
2.9PF
CRITICAL
2
1
C1267
0201
CERM
25V
5%
12PF
2
1
C1264
0201
C0G-CERM
25V
+/-0.05PF
2.9PF
CRITICAL
2
1
C1265
0201
MF
1/20W
5%
0
21
R1261
0201
X7R
25V
10%
BYPASS=U0500.V15::10MM
1000PF
2
1
C1261
0201
C0G-CERM
25V
+/-0.05PF
BYPASS=U0500.V15::10MM
2.9PF
CRITICAL
2
1
C1262
0201
MF
1/20W
5%
0
21
R1260
0201
X7R
25V
10%
BYPASS=U0500.AJ19::10MM
1000PF
2
1
C1226
0201
MF
1/20W
5%
0
NOSTUFF
21
R1251
0201
X6S-CERM
6.3V
20%
BYPASS=U0500.U11::10MM
1UF
NOSTUFF
2
1
C1251
0603
2.2UH-240MA-0.221OHM
OMIT_TABLE
21
L1254
0805
POLY-TANT
6.3V
20%
47UF
CRITICAL NOSTUFF
2
1
C1254
0603
2.2UH-240MA-0.221OHM
OMIT_TABLE
21
L1253
0805
POLY-TANT
6.3V
20%
47UF
CRITICAL NOSTUFF
2
1
C1253
0603
2.2UH-240MA-0.221OHM
OMIT_TABLE
21
L1252
0805
POLY-TANT
6.3V
20%
47UF
CRITICAL NOSTUFF
2
1
C1252
0805
POLY-TANT
6.3V
20%
BYPASS=U0500.K15::3MM
47UF
CRITICAL NOSTUFF
2
1
C1250
0603
2.2UH-240MA-0.221OHM
OMIT_TABLE
21
L1250
0201
X6S-CERM
6.3V
20%
BYPASS=U0500.AL1::3MM
1UF
2
1
C1232
0201
X5R-CERM
10V
10%
BYPASS=U0500.BB10::3MM
0.1UF
2
1
C1231
0201
X5R-CERM
10V
10%
BYPASS=U0500.AK19::3MM
0.1UF
2
1
C1228
0201
X5R-CERM
10V
10%
BYPASS=U0500.AK17::3MM
0.1UF
2
1
C1222
0805
POLY-TANT
6.3V
20%
BYPASS=U0500.N15::10MM
47UF
CRITICAL NOSTUFF
2
1
C1203
0201
X6S-CERM
6.3V
20%
BYPASS=U0500.AA1::10MM
1UF
2
1
C1230
0201
X6S-CERM
6.3V
20%
BYPASS=U0500.AK19::3MM
1UF
2
1
C1227
0201
C0G-CERM
25V
+/-0.05PF
BYPASS=U0500.AJ19::10MM
2.9PF
CRITICAL
2
1
C1260
0201
X7R
25V
10%
BYPASS=U0500.Y16::10MM
1000PF
2
1
C1225
0201
X7R
25V
10%
BYPASS=U0500.V19::10MM
1000PF
2
1
C1224
0201
X7R
25V
10%
BYPASS=U0500.AG15::3MM
1000PF
2
1
C1223
0201
X6S-CERM
6.3V
20%
BYPASS=U0500.AK17::3MM
1UF
2
1
C1221
0201
X7R
25V
10%
BYPASS=U0500.T16::3MM
1000PF
2
1
C1220
0201
X7R
25V
10%
BYPASS=U0500.AF18::10MM
1000PF
2
1
C1210
0201
X7R
25V
10%
BYPASS=U0500.A10::3MM
1000PF
2
1
C1207
0201
X6S-CERM
6.3V
20%
BYPASS=U0500.N18::3MM
1UF
2
1
C1206
0201
X7R
25V
10%
BYPASS=U0500.AF20::10MM
1000PF
2
1
C1205
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1204
0201
X6S-CERM
6.3V
20%
BYPASS=U0500.N15::3MM
1UF
2
1
C1202
0201
X6S-CERM
6.3V
20%
BYPASS=U0500.K17::3MM
1UF
2
1
C1201
0201
X7R
25V
10%
BYPASS=U0500.AB19::10MM
1000PF
2
1
C1200
69
69 8
69 8 5
69 8
69
69
69 8
8 69
69 8
72
72
8
69 8
5
69
8
69 8
69 8
69 19 8
8
5
8
8
69
69 8
69 15
69 8
69 15 14 8
8
8
69 8
64 8
69 8
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
合肥怡飞苹果维修qq:82669515 qq群: 241000
(STRAP)
PCH INTERNAL PULL-UPS ARE TO 3.3V.
IO1
IO0
(STRAP)
(STRAP)
(STRAP)
(STRAP)
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
(1.8V)
(STRAP)
(BSSB_DATA_IN)
(BSSB_CLK)
(1.8V)
MEMORY CONFIGURATION STRAPS.
ALL GPP_F* PINS ARE 1.8V ONLY!
13 OF 73
13 OF 500
1.0.0
051-02265
=PP3V3_SUS_PCH_VCCPGPPA
=PP3V3_S0_PCH
HDA_SYNC_R
HDA_SDOUT_R
HDA_RST_R_L
XDP_PCH_OBSDATA_C0
SML_PCH_1_DATA
HDA_BIT_CLK_R
HDA_SDIN0
LPC_AD_R<1>
=USBC_TMS_X_SWD_CLK_X
MLB_RAMCFG1
SPI_IO<2>
MLB_RAMCFG2
BT_PWRRST_L
SPI_CS0_R_L
LPC_SERIRQ
SOC_ALS_UART_D2R
PCH_BSSB_CLK
MLB_RAMCFG3
PCH_UART2_CTS_L
LCD_PSR_EN
TBT_X_CIO_PWR_EN
HDA_SDOUT
HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
LPC_SERIRQ
TP_SPI_CS2_L
SPI_IO<3>
SPI_CLK_R
PU_PCH_RCIN_L
=USBC_TMS_T_SWD_DATA_X
TP_SPI_CS1_L
SPI_CS0_R_L
SPI_MISO
PCH_DDPC_CTRLDATA
MLB_RAMCFG0
PCH_BSSB_DATA
MLB_RAMCFG3
MLB_RAMCFG2
MLB_RAMCFG1
LPC_AD_R<0>
LPC_AD_R<2> LPC_AD_R<3> LPC_FRAME_R_L
LPC_CLK24M_SMC_R
SSD_PWR_EN_L
LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L
LPC_CLK24M_SMC
LPC_AD<0>
PCH_DDPB_CTRLDATA
PCH_STRP_TOPBLK_SWP_L
CAMERA_PWR_EN_PCH
CAMERA_RESET_L
SOC_ALS_UART_D2R
SOC_ALS_UART_R2D
SOC_ALS_UART_R2D PCH_UART2_CTS_L
PCH_SOC_WDOG
SD_RCOMP
PCH_STRP_BSSB_SEL_GPIO
TP_PCH_STRP_TLSCONF
TP_PCH_STRP_ESPI
SMBUS_PCH_CLK SMBUS_PCH_DATA
SML_PCH_0_CLK SML_PCH_0_DATA
LPC_PWRDWN_L
TP_PCH_CLKOUT_LPC1 LPC_CLKRUN_L
LCD_PSR_EN
MLB_RAMCFG4
MLB_RAMCFG0
SPI_MOSI_R
=USBC_TMS_T_SWD_DATA_X
TBT_X_CIO_PWR_EN
SOC_S2R_ACK_L
PCH_SOC_DFU_STATUS
TBT_X_USB_PWR_EN
SOC_PANIC_L
=USBC_TMS_X_SWD_CLK_X
SML_PCH_1_CLK
DEBUGUART_SEL_SOC
SOC_SLEEP_L
TBT_X_USB_PWR_EN
CAMERA_PWR_EN
BT_TIMESTAMP
=PP3V3_SUS_PCH_VCCSPI
LPC_CLKRUN_L
PU_PCH_RCIN_L
RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG1_L,RAMCFG0_LRAMCFG_SLOT
SYNC_DATE=06/15/2015
PCH Audio/LPC/SPI/SMBus
SYNC_MASTER=PAULM
BOM_COST_GROUP=CPU & CHIPSET
201MF1/20W5%
10K
21
R1344
201MF1/20W5%
1K
21
R1343
70
70
67
201MF1/20W5%
PLACE_NEAR=U0500.AW9:38MM
22
21
R1327 39
201MF1/20W5%
10K
21
R1342
201MF1/20W5%
100K
21
R1359
201MF1/20W5%
100K
21
R1340
201MF1/20W5%
100K
21
R1341
39 13
201
MF
1/20W
5%
1K
RAMCFG4_L
2
1
R1334
201
MF
1/20W
5%
1K
RAMCFG3_L
2
1
R1333
201
MF
1/20W
5%
1K
RAMCFG2_L
2
1
R1332
201
MF
1/20W
5%
1K
RAMCFG1_L
2
1
R1331
201
MF
1/20W
5%
1K
RAMCFG0_L
2
1
R1330
201MF1/20W5%
100K
21
R1358
201MF1/20W5%
10K
21
R1356
201MF1/20W5%
100K
21
R1357
201MF1/20W5%
10K
21
R1355
201MF1/20W5%
47K
21
R1354
201MF1/20W5%
47K
21
R1353
201MF1/20W5%
47K
21
R1352
201MF1/20W5%
100K
CAMERA_PWR_EN:S0
21
R1351
201MF1/20W5%
10K
21
R1350
42
42
19 13
19 13
19 13
19 13
19
36 19
28 13
28 13
40
17
201
MF
1/20W
1%
PLACE_NEAR=U0500.AB7:12.7MM
200
2
1
R1370
70
70
47 13
47
47 17
47
47
47
39
201MF1/20W5%
33
21
R1325
42
42
42
42
201MF1/20W5%
33
21
R1320
201MF1/20W5%
33
21
R1322
201MF1/20W5%
33
21
R1321
201MF1/20W5%
33
21
R1323
39
39
39
39
39
39 13
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
AV3
AW3
AU4
AW2
AU1
AU2
AU3
AV2
U4
U3
AD4
AD3
AD2
AD1
V3
W3
W1
W2
R9
R10
R8
R7
AM7
BA11
AY9
AW9
AW11AY11
BA12
AY12
BB13
BA13
AY13
AW13
G1
G2
G3
U0500
19
28 13
28 13
19
48
201MF1/20W5%
PLACE_NEAR=U0500.AY22:14MM
33
21
R1301
201MF1/20W5%
PLACE_NEAR=U0500.BA22:14MM
33
21
R1300
48
201MF1/20W5%
PLACE_NEAR=U0500.AW22:14MM
33
21
R1303
201MF1/20W5%
PLACE_NEAR=U0500.BB22:14MM
33
21
R1302
48
48
48
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
AB7
AW20
AY20
BA22
BB22
AY21
BA21
AW22
AY22
AB13
AB11
AF13
AM3
AM2
AM1
AM4
AN2
AN1
N8
N7
L12
L13
D8
U2
U1
P1
P4
AW5
BA9
BB9
U0500
69 16 15 14 8
69 60 19 16 14 5
18
13
13
6
47 13
39 13
13
28 13
70
13
70
13
13
13
13
19 13
19 13
19 13
19
70
70
70
19 13
6
13
28 13
70
70
70
28 13
70
28 13
36 19
6
69 47 8
39 13
13
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
IN
OUT
OUT
OUT
IN
BI
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
NC
NC
NC
IN
IN
OUT
BI
BI
BI
BI
OUT
OUT
BI
OUT
BI
OUT
OUT
BI
BI
BI
BI
BI
LPC
SPI-TOUCH
SPI-FLASH
SMBUS,SMLINK
SYM 5 OF 20
C LINK
SML0BALERT*
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A14/SUS_STAT*/ESPI_RESET*
GPP_B23/SML1ALERT*/PCHHOT*
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME*/ESPI_CS*
GPP_A3/LAD2/ESPI_IO2
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_C5/SML0ALERT*
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT*
GPP_A8/CLKRUN*
GPP_A10/CLKOUT_LPC1
SPI0_CS0*
SPI0_MISO
SPI0_CLK
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS1*
CL_CLK
SPI0_CS2*
GPP_C21/UART2_TXD
GPP_C20/UART2_RXD
GPP_D16/ISH_UART0_CTS*/
GPP_C22/UART2_RTS*
GPP_C23/UART2_CTS*
GPP_D15/ISH_UART0_RTS*
CL_DATA
CL_RST*
GPP_A0/RCIN*
GPP_A6/SERIRQ
IN
BI
OUT
IN
NC
NC
OUT
NC
IN
OUT
OUT
OUT
AUDIO
SML0BDATA/I2C4B_SDA
SML0BCLK/I2C4B_SCL
SDIO/SDXC
SYM 7 OF 20
SD_RCOMP
GPP_F17/EMMC_DATA4
GPP_A16/SD_1P8_SEL
GPP_A17/SD_PWR_EN*/ISH_GP7
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_F22/EMMC_CLK
GPP_F23
GPP_F19/EMMC_DATA6
GPP_F21/EMMC_RCLK
GPP_F20/EMMC_DATA7
GPP_F18/EMMC_DATA5HDA_SDI1/I2S1_RXD
HDA_SDI0/I2S0_RXD
HDA_SDO/I2S0_TXD
HDA_BLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
I2S1_TXD
I2S1_SFRM
GPP_D17/DMIC_CLK1
GPP_E21/DDPC_CTRLDATA
GPP_E18/DDPB_CTRLCLK
HDA_RST*/I2S1_SCLK
GPP_E19/DDPB_CTRLDATA
GPP_E20/DDPC_CTRLCLK
GPP_D11
GPP_D12
GPP_B14/SPKR
GPP_D13/ISH_UART0_RXD/
GPP_D14/ISH_UART0_TXD/
合肥怡飞苹果维修qq:82669515 qq群: 241000
NOTE: PM_SLP_S0_L HAS INTERNAL PULL-UP BEFORE RSMRST_L IS RELEASED.
THE SIGNAL IS DRIVEN HI AFTER RSMRST_L IS RELEASED.
PCH Reset Button
R1400 kept for debug purposes.
VCCST_PWRGD 1V TOLERANT
(1.8V)
LAST CHANGE: Thu Aug 4 21:00:42 2016
DESIGN: X502/MLB_CATZ
ALL GPP_F* PINS ARE 1.8V ONLY!
(1V ONLY)
THIS CAUSES A VOLTAGE DIVIDER WITH THE PULL-DOWN HERE.
14 OF 73
14 OF 500
1.0.0
051-02265
PCH_SWD_CLK
SSD_SR_EN_L
PCIE_WAKE_L
PCH_PWRBTN_L
SMC_WAKE_SCI_L
PM_SLP_S4_L
PM_SLP_SUS_L
PCIE_WAKE_L
PCH_SOC_FORCE_DFU
TP_PCH_GPP_F8
TP_PCH_PME_L
TP_PCH_SLP_WLAN_L
PCH_SUSWARN_L
PCH_INTRUDER_L
BT_LOW_PWR_L
PCH_SWD_MUX_SEL
PM_SLP_S4_L PM_SLP_S5_L
PM_PCH_SYS_PWROK =PP3V_G3H_PCH_VCCRTC
PM_SLP_SUS_L
=PP1V_S3_CPU_VCCST
TP_PCH_GPP_F9
TP_PCH_GPP_D0
SMC_WAKE_SCI_L
SSD_BOOT_L
EMMC_RCOMP
SSD_SR_EN_L
TP_PCH_SLP_A_L
PM_SLP_S3_L
PM_SLP_S0_L
PCH_PWRBTN_L
PM_BATLOW_L
TP_CPU_PWRGD
PM_SLP_S0_L
TP_PCH_GPD7
PCH_HSIO_PWR_ENTP_PCH_LANPHYPC
UPC_I2C_INT_L
SOC_S2R_L
CSI2_COMP
TP_PCH_GPP_F10
PCH_SWD_CLK
PCH_SWD_IO
PCH_BT_ROM_BOOT
CPU_VCCST_PWRGD
=PP3V3_S0_PCH
PCH_SUSACK_L
=PP3V3_SUS_PCH_VCCPGPPA
PCH_SWD_IO
BT_LOW_PWR_L
=PP1V8_SUS_PCH_VCCPGPPF
PM_SLP_S3_L
=PP3V3_S4_PCH
SOC_S2R_L
=PP3V3_S0_PCH
=PP3V3_S5_PCH_VCCDSW
CPU_VCCST_PWRGD_R
PM_PCH_PWROK
PM_DSW_PWRGD
PM_RSMRST_L
PM_SYSRST_L
PLT_RST_L
PM_SLP_S5_L
PM_BATLOW_L
SSD_BOOT_L
PCH_SWD_MUX_SEL
BOM_COST_GROUP=CPU & CHIPSET
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
PCH Power Management
41
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
AN3
AP3
AP1
AP2
AP4
AD12
AD11
AF12
AF11
AH12
AH11
M1
AT1D27
B27
D28
B29
B33
B31
D33
D31
B38
D36
D38
B36
C27
A27
C28
A29
A33
A31
C33
C31
A38
C36
C38
A36
E13
A26
D29
D32
D37
B26
C29
C32
C37
U0500
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
BB15
B65
B5
B6
AN15
AW15
AY17
A68
BA20
AP16
AN10
AT11
AM10
AM11
AP11
AR13
AU11
AW17
AY16
BB17
AT15
AN16
BA16
AP15
BA15
AM15
AY15
AU13
BB20
U0500
201
MF
1/20W
5%
2.2K
2
1
R1408
201MF1/20W5%
10K
21
R1441
70
60
72 60 39 14
201MF1/20W5%
100K
21
R1446
100K
201MF1/20W5%
21
R1445
100K
5% 1/20W MF 201
21
R1444
NOSTUFF
100K
2015% MF1/20W
21
R1443
201MF1/20W5%
100K
21
R1442
MF 2011/20W5%
100K
21
R1440
19 14
19 14
19 14
NOSTUFF
201
MF
1/20W
5%
2.2K
2
1
R1407
201 MF 1/20W
1%
PLACE_NEAR=U0500.B65:38mm
60.4
21
R1406
201
MF
1/20W
5%
1K
2
1
R1405
MF 2011/20W5%
100K
21
R1458
MF 2011/20W5%
100K
21
R1456
201MF1/20W5%
220K
21
R1457
MF 2011/20W5%
100K
21
R1454
201MF1/20W5%
100K
21
R1455
201MF1/20W5%
10K
21
R1452
10K
201MF1/20W5%
21
R1451
201MF1/20W5%
1K
21
R1450
5% 201MF1/20W
100K
21
R1453
70
67 14
35 34 14
39 14
201
MF
1/20W
1%
PLACE_NEAR=U0500.AT1:12.7MM
200
2
1
R1481
201
MF
1/20W
1%
PLACE_NEAR=U0500.E13:12.7MM
100
2
1
R1480
201
MF
1/20W
5%
1M
2
1
R1401
39 28 14
67 14
72 60 14
72 60 39 14
72 68 60 39 14
72 66
60 59 39 26 14
18 14
68 39
201
MF
1/20W
5%
100K
2
1
R1403
60
68 35 19
68 39 17
41 14
68 60 39 17
60 19
60 59 39
41
0201
MF
1/20W
5%
0
NO STUFF
1
2
R1400
19 14
67 14
18 14
41 14
39 14
72 68 60 39 14
72 60 14
70
70
70
69 15 12 8
69 59 54 19 10 8 6
70
70
72
72 60 39 14
70
70
19 14
70
70
69 60 19 16 14 13 5
69 16 15 13 8
19 14
35 34 14
69 8
72 66 60 59 39 26 14
69
19 14
69 60 19 16 14 13 5
69 8
72
72 60 39 14
39 28 14
67 14
19 14
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
EMMC
CSI-2
SYM 9 OF 20
CSI2_COMP
GPP_D0/SPI1_CS*
GPP_F7/I2C3_SCL
CSI2_DN8
CSI2_DP11
CSI2_DN11
CSI2_DP10
CSI2_DN10
CSI2_DP9
CSI2_DN9
CSI2_DP8
CSI2_DP7
CSI2_DN7
CSI2_DP6
CSI2_DN6
CSI2_DP5
CSI2_DN5
CSI2_DP4
CSI2_DN4
CSI2_DP3
CSI2_DN3
CSI2_DP2
CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
EMMC_RCOMP
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_F12/EMMC_CMD
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F6/I2C3_SDA
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
CSI2_CLKN3
CSI2_CLKP3
CSI2_CLKP2
CSI2_CLKN2
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKP1
CSI2_CLKN1
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
SYSTEM POWER MANAGEMENT
SYM 11 OF 20
GPP_B12/SLP_S0*
GPD5/SLP_S4*
GPD4/SLP_S3*
GPD10/SLP_S5*
SLP_SUS*
GPD9/SLP_WLAN*
GPD6/SLP_A*
SLP_LAN*
GPD3/PWRBTN*
GPD1/ACPRESENT
GPD0/BATLOW*
GPP_A11/PME*
INTRUDER*
GPP_B11/EXT_PWR_GATE*
GPP_B2/VRALERT*
GPP_B13/PLTRST*
SYS_RESET*
RSMRST*
PROCPWRGD
SYS_PWROK
VCCST_PWRGD
DSW_PWROK
PCH_PWROK
GPP_A15/SUSACK*
GPP_A13/SUSWARN*/SUSPWRDNACK
WAKE*
GPD2/LAN_WAKE*
GPD11/LANPHYPC
GPD7/RSVD
OUT
OUT
OUT
BI
OUT
OUT
IN
OUT
NC
OUT
IN
NC
NC
NC NC
NC
NC
NC
NC
NC
NC
NC NC
NC
NC
NC
NC
NC NC NC NC NC NC NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
EXT B (LS/FS/HS)
ANY CLKREQ CAN MAP TO ANY CLK. ANY CLKREQ OR CLK CAN MAP TO ANY PCIE PORT. UNUSED CLKREQS AND CLKS SHOULD BE DISABLED.
PCIe Port Assignments:
PER SKYLAKE PDG, SKYLAKE PCH EDS.
EXT A (LS/FS/HS)
EXT B (SS)
SSD LANE 3
SSD LANE 1
LAST CHANGE: Thu Aug 4 21:00:42 2016
DESIGN: X502/MLB_CATZ
EXT A (SS,DCI)
GROUNDED PER SKYLAKE MOW 2015WW10.
Thunderbolt X lane 0
Thunderbolt X lane 1
Thunderbolt X lane 3
Thunderbolt T lane 1
Thunderbolt T lane 0
AirPort
CAMERA
SSD LANE 2
SSD LANE 0
Thunderbolt X lane 2
15 OF 73
15 OF 500
1.0.0
051-02265
USB_EXTA_N USB_EXTA_P
USB3_EXTB_R2D_C_P
TP_USB3_03_R2DP
TP_USB3_04_D2RN TP_USB3_04_D2RP
NC_USB2_07P
NC_USB2_09P
NC_USB2_06P
NC_USB2_06N
PCH_USB2_COMP
TP_USB3_04_R2DP
PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_N<3>
PCIE_TBT_X_R2D_C_P<1>
TP_USB3_04_R2DN
PCIE_SSD_D2R_P<0>
XDP_PCH_OBSFN_C1
USB3_EXTB_D2R_P
NC_USB2_10P
USB3_EXTB_D2R_N
TP_USB_TESTERN
PCH_USB2_VBUSSENSE
NC_USB2_09N
NC_USB2_08N
=PP3V_G3H_PCH_VCCRTC
PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_R2D_C_P<3>
PCIE_AP_R2D_C_P
PCH_PCIE_RCOMP_P
PCIE_AP_R2D_C_N
PCIE_CAMERA_D2R_P
PCIE_CAMERA_R2D_C_N
PCH_DIFFCLK_BIASREF
PCH_SRTCRST_L RTC_RESET_L=PP3V3_SUS_PCH_VCCPGPPA
PCH_CLK24M_XTALOUT
PCIE_SSD_D2R_N<1> PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_N<2>
PCIE_SSD_D2R_P<3>
PCIE_TBT_X_D2R_N<2>
PCIE_TBT_X_R2D_C_N<3>
PCIE_SSD_R2D_C_P<3>
NC_USB2_08P
NC_USB2_07N
USB_CAMERA_DFR_N
NC_USB2_05N
TP_USB3_03_D2RN TP_USB3_03_D2RP
SMC_RUNTIME_SCI_L
PCIE_SSD_R2D_C_P<0>
SPKR_ID0
PCIE_TBT_T_D2R_N<1> PCIE_TBT_T_D2R_P<1> PCIE_TBT_T_R2D_C_N<1>
PCIE_SSD_R2D_C_P<1>
PCIE_TBT_X_D2R_P<0>
PCIE_TBT_X_D2R_P<2>
XDP_CPU_PRDY_L
XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_C1
NC_USB2_10N
PCH_PCIE_RCOMP_N
PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
=PP1V_SUS_PCH_VCCAPLL
PCIE_TBT_X_R2D_C_N<0> PCIE_TBT_X_R2D_C_P<0>
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_TBT_X_D2R_P<3>
PCIE_TBT_X_D2R_N<3>
PCIE_TBT_X_R2D_C_P<2>
XDP_PCH_OBSDATA_D0 XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_C3
XDP_PCH_OBSDATA_D3
PCIE_TBT_X_D2R_N<0>
USB_EXTB_N
PCIE_TBT_X_R2D_C_N<1>
PCIE_TBT_X_D2R_P<1>
PCIE_SSD_D2R_N<3>
PCIE_SSD_R2D_C_P<2>
PCIE_SSD_R2D_C_N<2>
PCIE_SSD_D2R_P<2>
PCIE_SSD_D2R_N<0>
PCIE_CLK100M_TBT_X_N
=TBT_X_CLKREQ_L
TP_PCH_CLKREQ5_L
TP_PCIE_CLK100M5P
TP_PCIE_CLK100M5N
PCIE_CLK100M_CAMERA_N
PCIE_CLK100M_AP_N
PCIE_CLK100M_TBT_T_N
=CAMERA_CLKREQ_L
PCIE_CLK100M_CAMERA_P
XDP_PCH_OBSDATA_C2
USB_CAMERA_DFR_P
TP_USB_TESTERP
NC_USB2_05P
USB_EXTB_P
USB3_EXTA_D2R_N USB3_EXTA_D2R_P USB3_EXTA_R2D_C_N USB3_EXTA_R2D_C_P
USB3_EXTB_R2D_C_N
TP_USB3_03_R2DN
PCIE_TBT_X_R2D_C_N<2>
=AP_CLKREQ_L
PCIE_CLK100M_AP_P
=TBT_T_CLKREQ_L
PCIE_CLK100M_TBT_T_P
=SSD_CLKREQ_L
PCIE_CLK100M_TBT_X_P
XDP_JTAG_ISP_TDI
XDP_JTAG_ISP_TCK
PCIE_CAMERA_D2R_N
PCIE_CAMERA_R2D_C_P
PCH_CLK24M_XTALIN
PCH_CLK32K_RTCX2
PCH_CLK32K_RTCX1
XDP_CPU_PREQ_L
SMC_RUNTIME_SCI_L
PCIE_TBT_T_D2R_N<0> PCIE_TBT_T_D2R_P<0> PCIE_TBT_T_R2D_C_N<0> PCIE_TBT_T_R2D_C_P<0>
PCIE_TBT_T_R2D_C_P<1>
TP_ITPXDP_CLK100MN
PM_CLK32K_SUSCLK_R
TP_ITPXDP_CLK100MP
BOM_COST_GROUP=CPU & CHIPSET
PCH PCIE/USB/CLKS
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
19
19
19
201MF1/20W5%
100K
21
R1550
70
70
70
70
70
70
70
70
28
28
28
28
28
28
28
28
28
28
28
28
28 19
28 19
28
28
70
70
70
26
19
26
19
67
67
19
35
35
37
19
37
17
17
17
17
17
17
17
17
17
17
72 67
72 67
72 67
72 67
72 67
72 67
72 67
72 67
72 67
72 67
72 67
72 67
72 67
72 67
72 67
72 67
37
37
37
37
72 35
72 35
72 35
72 35
39 15
70
70
201
MF
1/20W
1%
PLACE_NEAR=U0500.F5:12.7mm
100
2
1
R1504
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
E35
E37
E42
AN18
AM20
AM18
AM16
AU7
AU8
AT10
AT8
AT7
AR10
BA17
E38
A40
C40
C41
A42
C42
E40
B40
D40
D41
B42
D42
E43
F43
U0500
201
MF
1/20W
1%
20K
2
1
R1531
201
MF
1/20W
1%
20K
2
1
R1530
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1531
0201
X6S-CERM
6.3V
20%
1UF
2
1
C1530
201
MF
1/20W
1%
PLACE_NEAR=U0500.E42:2.54mm
2.7K
2
1
R1520
19
19
40
201
MF
1/20W
5%
PLACE_NEAR=U0500.AG4:12.7MM
1K
2
1
R1503
28
28
201
MF
1/20W
1%
PLACE_NEAR=U0500.AB6:12.7MM
113
2
1
R1501
70
70
28
28
28
28
70
70
70
70
72 17
72 17
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
D15
C15
F10
E10
A15
B15
H10
J10
A13
B13
H6
J6
D13
C13
G8
H8
AH8
AG2
AF9
AH2
AF7
AJ2
AD10
AJ3
AD7
AB10
AH7
AG1
AF8
AH1
AF6
AJ1
AD9
AH3
AD6
AB9
AG4
AG3
AB6
D61
D56
E5
F5
B25
A25
F30
E30
C24
D24
E27
E28
C23
D23
E25
F25
A23
B23
E23
E22
C21
D21
F21
G21
A21
B21
E20
F20
C20
D20
F18
G18
D19
C19
E16
F16
A19
B19
F15
G15
C17
D17
G16
H16
C16
D16
F11
G11
A17
B17
G13
H13
J3
J2
J1
A6
G4
H2
J5
V2
D7
H5
C8
BB11
U0500
70
70
70
70
70
70
70
70
70
70
72
70
28
69 14 12 8
69 16 14 13 8
28
70
70
70
70
39 15
70
69 12
70
70
70
72
70
70
70
70
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
OUT
IN
IN
BI
BI
SYM 10 OF 20
CLOCK SIGNALS
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5*
CLKOUT_PCIE_N5
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4*
GPP_B8/SRCCLKREQ3*
CLKOUT_PCIE_N4
CLKOUT_PCIE_P3
CLKOUT_PCIE_N3
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2*
GPP_B6/SRCCLKREQ1*
CLKOUT_PCIE_N2
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
CLKOUT_PCIE_N0
GPP_B5/SRCCLKREQ0*
CLKOUT_PCIE_P0
CLKOUT_ITPXDP_N
GPD8/SUSCLK
CLKOUT_ITPXDP_P
XTAL24_OUT
XTAL24_IN
RTCX2
XCLK_BIASREF
RTCX1
SRTCRST*
RTCRST*
IN
IN
OUT
BI
BI
BI
BI
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
SYM 8 OF 20
USB2
PCIE/USB3/SATA
SSIC/USB3
PCIE6_TXP
PCIE6_RXP
PCIE6_TXN
PCIE6_RXN
PCIE1_RXP/USB3_5_RXP
PCIE1_TXN/USB3_5_TXN
PCIE1_TXP/USB3_5_TXP
PCIE2_RXN/USB3_6_RXN
USB2N_2
USB2P_2
PCIE5_RXN
GPP_E2/SATAXPCIE2/SATAGP2
GPP_D20/DMIC_DATA0
GPP_D18/DMIC_DATA1
GPP_D19/DMIC_CLK0
GPP_E0/SATAXPCIE0/SATAGP0
GPP_D23/I2S_MCLK
GPP_E6/DEVSLP2
GPP_D22/SPI1_IO3
GPP_E4/DEVSLP0
GPP_E3/CPU_GP0
GPP_E5/DEVSLP1
USB2_ID
USB2_VBUSSENSE
USB2_COMP
USB2P_10
USB2P_9
USB2N_10
USB2N_9
USB2P_8
USB2P_7
USB2N_8
USB2N_7
USB2P_6
USB2P_5
USB2N_6
USB2N_5
USB2P_4
USB2P_3
USB2N_4
USB2N_3
USB2P_1
USB2N_1
USB3_4_TXP
USB3_4_TXN
USB3_4_RXN
USB3_4_RXP
USB3_1_TXP
USB3_1_TXN
USB3_1_RXP
USB3_1_RXNPCIE1_RXN/USB3_5_RXN
PCIE3_RXP
PCIE3_RXN
PCIE4_RXP
PCIE4_RXN
PCIE3_TXN
PCIE3_TXP
PCIE2_TXP/USB3_6_TXP
PCIE2_TXN/USB3_6_TXN
PCIE2_RXP/USB3_6_RXP
PCIE4_TXN
PCIE5_RXP
PCIE4_TXP
PCIE7_RXN/SATA0_RXN
PCIE7_RXP/SATA0_RXP
PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP
PCIE8_RXN/SATA1A_RXN
PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
PCIE8_TXP/SATA1A_TXP
PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP
PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP
PCIE_RCOMPN
PCIE_RCOMPP
PROC_PRDY*
PROC_PREQ*
GPP_A7/PIRQA*
PCIE12_RXP/SATA2_RXP
PCIE12_RXN/SATA2_RXN
PCIE11_TXP/SATA1B_TXP
PCIE11_RXN/SATA1B_RXN
PCIE11_RXP/SATA1B_RXP
PCIE11_TXN/SATA1B_TXN
PCIE12_TXP/SATA2_TXP
PCIE12_TXN/SATA2_TXN
PCIE5_TXP
PCIE5_TXN
USB3_2_RXN/SSIC_RXN
USB3_2_RXP/SSIC_RXP
USB3_2_TXN/SSIC_TXN
USB3_2_TXP/SSIC_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
合肥怡飞苹果维修qq:82669515 qq群: 241000
<11011>
<10110>
<11010>
<11001>
<11000>
MLB ID STRAPS.
<10101>
LAST CHANGE: Thu Aug 4 21:00:42 2016
<10111>
<11111>
<11110>
<11100>
CODE
ALL GPP_F* PINS ARE 1.8V ONLY!
(STRAP)
(1.8V)
(1.8V)
(1.8V)
(STRAP)
DESIGN: X502/MLB_CATZ
<11101>
PCH INTERNAL PULL-UPS ARE TO VCCGPPD = 3.3V.
<10100>
<01111>
DRIVEN PUSH PULL FROM SWITCHED RAIL.
16 OF 73
16 OF 500
1.0.0
051-02265
TPAD_SPI_CS_L TPAD_SPI_CLK TPAD_SPI_MISO TPAD_SPI_MOSI
AUD_SPI_MISO
AUD_SPI_CS_L
I2C_UPC_SDA
MLB_DEV_L
AUD_SPI_CLK
MLB_BOARD_ID3
TBT_X_PCI_RESET_L
I2C_UPC_SCL
TP_PCH_GPP_D1
SPKR_ID1
TP_PCH_GPP_D3 TP_PCH_GPP_D4
TBT_T_CIO_PWR_EN
AP_RESET_L
SPIROM_USE_MLB
TBT_T_USB_PWR_EN
AP_DEV_WAKE
AP_S0IX_WAKE_SEL
MLB_BOARD_ID2
MLB_BOARD_ID1
MLB_BOARD_ID4
LCD_IRQ_L
PCH_BT_UART_CTS_L
SPIROM_USE_MLB
SOC_UART_CTS_L
TP_BT_I2S_SYNC
TBT_T_PLUG_EVENT_L
TBT_POC_RESET
SOC_UART_R2D
SOC_UART_D2R
TBT_T_PLUG_EVENT_L
TBT_X_PLUG_EVENT_L
PCH_BT_UART_D2R
AUD_SPI_MOSI
AUD_SPI_CS_L
AUD_SPI_MOSI
TPAD_SPI_MOSI
TPAD_SPI_INT_L
TBT_X_PLUG_EVENT_L
LCD_IRQ_L
SOC_UART_RTS_L
TP_BT_I2S_R2D
TP_BT_I2S_CLK
SSD_RESET_L
MLB_BOARD_ID4
MLB_BOARD_ID0
MLB_BOARD_ID3
MLB_BOARD_ID2
MLB_BOARD_ID1
MLB_BOARD_ID0
TPAD_SPI_IF_EN TPAD_SPI_INT_L
AUD_PWR_EN
AUD_PWR_EN
TPAD_SPI_IF_EN
PCH_BT_UART_RTS_L
PCH_BT_UART_R2D
TBT_POC_RESET
PCH_BT_UART_CTS_L
TBT_X_DPMUX_SEL TBT_T_DPMUX_SEL
PCH_BT_UART_D2R
TP_BT_I2S_D2R
=PP3V3_SUS_PCH_VCCPGPPA
AUD_SPI_CLK AUD_SPI_MISO
TPAD_SPI_MISO
AP_S0IX_WAKE_L
AP_S0IX_WAKE_SEL
SOC_UART_CTS_L
SOC_UART_D2R SOC_UART_R2D SOC_UART_RTS_L
=PP3V3_S0_PCH
TPAD_SPI_CS_L TPAD_SPI_CLK
PCH_BT_UART_R2D PCH_BT_UART_RTS_L
AP_S0IX_WAKE_L AP_DEV_WAKE
TBT_T_PCI_RESET_L
BOM_COST_GROUP=CPU & CHIPSET
PCH SPI/UART/GPIO
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
0117S0006 RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:0
2117S0006 R1691,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:3
3117S0006 R1693,R1691,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:11
1117S0006 R1694RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:16
2117S0006 R1693,R1691RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:10
1117S0006 R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:1
1117S0006 R1691RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:2
2117S0006 R1693,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:9
1117S0006 R1692RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:4
1117S0006 R1693RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:8
3117S0006 R1692,R1691,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:7
2117S0006 R1692,R1691RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:6
2117S0006 R1692,R1690RES,MF,1/20W/1K OHM,5,0201,SMD BOARD_ID:5
201MF1/20W5%
100K
21
R1674
201MF1/20W5%
100K
21
R1673
201MF1/20W5%
100K
21
R1669
201
MF
1/20W
5%
1K
OMIT_TABLE
2
1
R1694
201
MF
1/20W
5%
1K
OMIT_TABLE
2
1
R1693
201
MF
1/20W
5%
1K
OMIT_TABLE
2
1
R1692
201
MF
1/20W
5%
1K
OMIT_TABLE
2
1
R1691
201
MF
1/20W
5%
1K
OMIT_TABLE
2
1
R1690
201MF1/20W5%
100K
21
R1672
201MF1/20W5%
47K
21
R1642
201MF1/20W5%
47K
21
R1641
201MF1/20W5%
47K
21
R1640
201MF1/20W5%
47K
21
R1643
70
72 38 16
201MF1/20W5%
100K
21
R1671
201MF1/20W5%
100K
21
R1668
201MF1/20W5%
100K
21
R1667
201MF1/20W5%
100K
21
R1666
201MF1/20W5%
100K
21
R1665
201MF1/20W5%
47K
21
R1664
201MF1/20W5%
47K
21
R1663
201MF1/20W5%
47K
21
R1662
201MF1/20W5%
47K
21
R1661
201MF1/20W5%
150K
21
R1660
201MF1/20W5%
47K
21
R1659
201MF1/20W5%
47K
21
R1658
201MF1/20W5%
47K
21
R1657
201MF1/20W5%
47K
21
R1655
201MF1/20W5%
1K
21
R1656
201MF1/20W5%
47K
21
R1654
201MF1/20W5%
47K
21
R1653
201MF1/20W5%
100K
AUD_PWR_EN:S0
21
R1652
201MF1/20W5%
100K
21
R1650
70
49 19 16
72 38 16
70
70
70
72 47 16
72 66 16
28 19
70
70
70
35 34 16
35 34 19
28 16
67 19
19 16
19 16
19 16
19 16
19 16
28 16
18 16
18 16
35 16
35 16
35 16
35 16
72 38 16
72 38 16
72 38 16
38 16
19 16
19 16
19 16
19 16
BGA
TBD
SKL-ULT-2+3E
OMIT_TABLE
AP13
W7
W8
W10
W11
W12
AB12
AH10
AH9
AK10
AK9
AK7
AK6
N12
N11
P3
P2
N2
N1
N3
M4
B7
J4
M3
M2
U9
U8
U6
U7
AB4
AC3
AC2
AC1
AB3
W4
AB2
AB1
AN5
AP5
AN7
AM5
AR7
AP8
AP7
AN8
AW7
AY7
BA7
BB7
BA8
AY8
U0500
16
70
19
70
70
18 16
16
16
16
35 16
72 47 16
70
19 16
28 16
19 16
19 16
72 38 16
72 38 16
28 16
72 66 16
70
70
16
16
16
16
16
16
49 19 16
72 38 16
35 16
70
69 15 14 13 8
19 16
19 16
72 38 16
19 16
19 16
19 16
19 16
69 60 19 14 13 5
38 16
72 38 16
35 16
35 16
18 16
35 34 16
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART# DESCRIPTIONQTY
TABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
BI
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
SYM 6 OF 20
LPSS ISH
BM_BUSY*/ISH_GP6
GPP_A18/ISH_GP0
GPP_C19/I2C1_SCL
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_D3/SPI1_MOSI
GPP_D4/FLASHTRIG
GPP_F2/I2S2_TXD
GPP_F0/I2S2_SCLK
GPP_C15/UART1_CTS*/ISH_UART1_CTS*
GPP_C14/UART1_RTS*/ISH_UART1_RTS*
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_F3/I2S2_RXD
GPP_F1/I2S2_SFRM
GPP_C11/UART0_CTS*
GPP_C10/UART0_RTS*
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C18/I2C1_SDA
GPP_C17/I2C0_SCL
GPP_C16/I2C0_SDA
GPP_C9/UART0_TXD
GPP_B19/GSPI1_CS*
GPP_B20/GSPI1_CLK
GPP_B15/GSPI0_CS*
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_G6/SD_CLK
GPP_D9
GPP_G7/SD_WP
GPP_D10
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD*
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
SX_EXIT_HOLDOFF*/GPP_A12/
GPP_E22
GPP_E23
合肥怡飞苹果维修qq:82669515 qq群: 241000
OBSDATA_D1
OBSDATA_B0
PULL CFG<3> LOW
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.
NEED TO CONNECT TO VCCST, *STG POWER LOGIC
(UNDOCUMENTED STRAP FUNCTION)
PULL STRAP LOW WHEN XDP IS PLUGGED IN.
TDO
XDP_PRESENT#
(OD)
OBSDATA_D2
OBSDATA_D3
(STRAP TO PCH)
RESET#/HOOK6
TDI
These signals do not connect to the Primary (Merged) XDP connector in this architecture.
OBSDATA_D0
WHEN XDP PRESENT
OBSFN_D0
OBSDATA_A0
OBSFN_A1
OBSFN_A0
OBSDATA_B3
support chipset debug.
OBSDATA_A3
OBSFN_B0
OBSFN_B1
OBSDATA_A2
SCL
Unused GPIOs have TPs.
Non-XDP Signals
SDA
DBR#/HOOK7
TMS
ITPCLK/HOOK4
DESIGN: X502/MLB_CATZ
PCH/XDP Signals
PCH XDP Signals
OBSFN_C0
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
HOOK2
VCC_OBS_CD
ITPCLK#/HOOK5
TCK0
TCK1
XDP_PIN_1
NOTE: This is not the standard XDP pinout.
518S0847
OBSDATA_B2
OBSDATA_B1
OBSFN_C1
OBSFN_D1
HOOK1
HOOK3
HOOK0
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation.
OBSDATA_C3
OBSDATA_C2
OBSDATA_C1
OBSDATA_C0
ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.
Use with 921-0133 Adapter Flex to
OBSDATA_A1
Primary / Merged (CPU/PCH) Micro2-XDP
LAST CHANGE: Thu Aug 4 21:00:42 2016
TRSTn
VCC_OBS_AB
17 OF 73
18 OF 500
1.0.0
051-02265
SPI_IO<2>SPI_IO2_STRAP_L
CPU_CFG<12> CPU_CFG<13>
XDP_PM_RSMRST_L
XDP_PRESENT_CPU
XDP_CPU_PRDY_L
XDP_PCH_TCK
CPU_CFG<4>
USB_EXTA_OC_L
CPU_CFG<3>
XDP_USB_EXTA_OC_L
MAKE_BASE=TRUEMAKE_BASE=TRUE
XDP_USB_EXTB_OC_L
MAKE_BASE=TRUE
XDP_CPU_TDI
XDP_CPU_TRST_L
JTAG_ISP_TDI
XDP_PCH_OBSFN_C1
XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D0
XDP_PCH_OBSDATA_C1
XDP_JTAG_ISP_TCK
MAKE_BASE=TRUE
XDP_PCH_OBSDATA_B0
XDP_JTAG_ISP_TDI
MAKE_BASE=TRUE
XDP_PCH_TDI
XDP_PCH_TMS
XDP_CPU_TDO
USB_EXTC_OC_L
JTAG_ISP_TCK
XDP_PCH_OBSDATA_C3
PM_PWRBTN_L
XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_A3
PM_SYSRST_L
XDP_USB_EXTD_OC_L
MAKE_BASE=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUE
XDP_USB_EXTC_OC_L
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_C0
USB_EXTD_OC_L
XDP_PCH_OBSDATA_D3
XDP_PCH_OBSDATA_C2
CPU_CFG<2>
CPU_CFG<8>
=PP1V_S0SW_CPU_VCCSTG
XDP_PCH_TDO
CPU_CFG<11>
XDP_CPU_TMS
XDP_CPU_TDO
CPU_CFG<9>
CPU_CFG<18>
CPU_CFG<19>
CPU_CFG<10>
XDP_PCH_TCK
XDP_CPU_TCK
XDP_DBRESET_L
XDP_PCH_TDO
CPU_CFG<15>
XDP_PCH_TRST_L
ITP_PMODE
CPU_CFG<14>
=PP3V3_SUS_XDP
=PP3V3_SUS_XDP
CPU_CFG<17> CPU_CFG<16>
CPU_CFG<1>
PCH_JTAGX
CPU_CFG<6>
XDP_PRESENT_L
XDP_PCH_TMS
PM_RSMRST_L
XDP_CPU_PREQ_L
CPU_CFG<0>
XDP_CPU_TCK
USB_EXTB_OC_L
XDP_CPU_PWRBTN_L
CPU_CFG<7>
XDP_PCH_TDI
=PP1V_SUS_XDP
CPU_CFG<5>
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
BOM_COST_GROUP=DEBUG
CPU/PCH Merged XDP
6
6
6
6
72 17 6
6
0.1UF
10% 10V X5R-CERM 0201
XDP_STRAP
2
1
C1830
74AUP1G07GF
SOT891
XDP_STRAP
4
6
5
1
3
2
U1830
47 13
72 6
XDP:YES
0
5%
1/20W
MF
0201
21
R1806
68 39 14
5
5
5
15
15
6
15
15
15
15
15
13
TP-P6
1
TP1880
TP-P6
1
TP1879
TP-P6
1
TP1878
TP-P6
1
TP1877
TP-P6
1
TP1881
TP-P6
1
TP1876
TP-P6
1
TP1875
TP-P6
1
TP1874
TP-P6
1
TP1873
TP-P6
1
TP1872
TP-P6
1
TP1871
28 19
28 19
TP-P6
1
TP1870
19
19
28
28
72 60
XDP:YES
100K
5%
1/20W
MF
201
2
1
R1850
XDP:YES
10
PLACE_NEAR=U0500.BA15:2.54MM
5% 1/20W MF 201
21
R1802
1K
PLACE_NEAR=U0500.E8:2.54MM
5% 1/20W MF 201
2
1
R1830
72 6
72 6
1.5K
NO_XNET_CONNECTION=1
PLACE_NEAR=U0500.AW2:10MM
5%
1/20W
MF
201
XDP_STRAP
21
R1831
XDP:YES
0
PLACE_NEAR=J1800.57:2.54MM
5% 1/20W MF 0201
21
R1824
XDP:YES
0
PLACE_NEAR=J1800.55:2.54MM
5% 1/20W MF 0201
21
R1823
XDP:YES
0
PLACE_NEAR=J1800.53:2.54MM
5% 1/20W MF 0201
21
R1822
XDP:YES
0
PLACE_NEAR=J1800.51:2.54MM
5% 1/20W MF 0201
21
R1821
68 60 39 14
XDP:YES
1K
NO_XNET_CONNECTION
PLACE_NEAR=U0500.D67:2.54MM
5%
1/20W
MF
201
2
1
R1801
6
XDP_CONN:YES
DF40RC-60DP-0.4V
M-ST-SM1
64 63
62
61
60 59
58 57
56 55
54 53
52 51
50 49
48 47
46 45
44 43
42 41
40 39
38 37
36 35
34 33
32 31
30
29
28 27
26 25
24 23
22 21
20 19
18 17
16 15
14 13
12 11
10 9
8 7
6 5
4 3
2 1
J1800
NOSTUFF
51
PLACE_NEAR=U0500.C61:28MM 5% 1/20W MF 201
12
R1897
XDP:YES
0.1UF
PLACE_NEAR=J1800.47:28MM
10% 10V X5R-CERM 0201
2
1
C1806
XDP:YES
0.1UF
PLACE_NEAR=J1800.42:28MM
10% 10V
X5R-CERM
0201
2
1
C1804
5
72 15
72 15
XDP:YES
0.1UF
PLACE_NEAR=J1800.44:28MM
10% 10V
X5R-CERM
0201
2
1
C1800
5
15
15
6
15
5
XDP:YES
0.1UF
PLACE_NEAR=J1800.43:28MM
10% 10V X5R-CERM 0201
2
1
C1801
72 17 6
72 6
72 6
6
XDP:YES
0
PLACE_NEAR=J1800.58:28MM
5% 1/20W MF 0201
21
R1835
XDP:YES
51
PLACE_NEAR=U0500.A56:28MM 5% 1/20W MF 201
12
R1890
XDP:YES
51
PLACE_NEAR=U0500.D59:28MM 5% 1/20W MF 201
12
R1891
XDP:YES
51
PLACE_NEAR=U0500.C59:28MM 5% 1/20W MF 201
12
R1892
XDP:YES
51
PLACE_NEAR=U0500.A61:28MM 5% 1/20W MF 201
12
R1810
72 17 6
6
6
6
6
6
XDP:YES
1K
PLACE_NEAR=U0500.AY17:19MM
5% 1/20W MF 201
21
R1800
XDP:YES
51
PLACE_NEAR=U0500.B61:28MM 5% 1/20W MF 201
12
R1813
72 17 6
72 17 6
6
72 17 6
72 41 39
6
6
6
6
72 6
6
6
72
72
72 17 6
72 17 6
72 17 6
69 10 8 6
72 17 6
72 17 6
72 17 6
72
69 60 17
69 60 17
72
69
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
OUT
IN
GND
VCC
NCNC
YA
NC NC
NC NC
NC
NC NC
NC
NC
NC
OUT
IN
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
OUT
OUT
TP
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN
BI
BI
IN
IN
IN
BI
BI
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
System 32kHz / 12MHz / 24MHz Clock Generator
359S00006
NOTE: 30 PPM or better required for SKL PCH
H AP_S0IX_WAKE_L (B1)
PCH ME Disable Strap
SEL OUTPUT
PCH IPD = 9-50k
L PCIE_WAKE_L (B0)
PCIe Wake Muxing
If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting.
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
***** Circuit does not support HDA voltage >3.3V.
18 OF 73
VOLTAGE=2.9V
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1500
19 OF 500
1.0.0
051-02265
PP2V9_SYSCLK
=PPVIO_CAMERA_BT_AP_32CLK =PPVIOE_PCHCLK
SYSCLK_CLK24M_X1
SYSCLK_CLK24M_X2
SPI_DESCRIPTOR_OVERRIDE
HDA_SDOUT_R
SPI_DESCRIPTOR_OVERRIDE_L
=PP3V3_S5_WIRELESS
AP_S0IX_WAKE_L
AP_PCIE_WAKE_L PCIE_WAKE_L
AP_S0IX_WAKE_SEL
=PPVIOE_CAMCLK
SYSCLK_CLK24M_X2_R
=PPVIOE_SSDCLK
SYSCLK_CLK24M_PCH
SYSCLK_CLK32K_CAMERA_BT_AP
SYSCLK_CLK32K_PCH
SYSCLK_CLK24M_SSD
SYSCLK_CLK24M_CAMERA
SYSCLK_CLK12M_SMC
=PP1V8R1V5_S0_PCH_VCCHDA
=PP3V3_G3H_SYSCLK
SMC_CLK12M_EN
SYNC_DATE=06/17/2015SYNC_MASTER=X362
BOM_COST_GROUP=CPU & CHIPSET
Chipset Support 1
19
19
19
19
2.5X2.0MM-SM
24MHZ-10PPM-8PF-40OHM
CRITICAL
31
42
Y1900
DFN
PI5A3157B
1
6
5
2
43
U1910
16
16
14
0201
X5R-CERM
10V
10%
0.1UF
2
1
C1910
201
MF
1/20W
5%
100K
2
1
R1910
35 34
DFN1006H4-3
DMP31D0UFB4
2
1
3
Q1930
69
0201
X5R-CERM
6.3V
20%
BYPASS=U1900.17:18:5MM
2.2UF
2
1
C1900
STQFN
SLG3AP3444
CRITICAL
19
20
11
17
15
5
2
12
1
8
18
14
9
4
13
10
16
6
3
7
U1900
0201-1
X5R
6.3V
20%
BYPASS=U1900.11:18:5MM
1.0UF
2
1
C1901
39
201
MF
1/20W
5%
1M
NOSTUFF
2
1
R1901
0201
MF
1/20W
5%
0
21
R1900
0201
C0G
50V
5%
10PF
2 1
C1907
0201
C0G
50V
5%
10PF
2 1
C1908
39
13
201
MF
1/20W
5%
1K
2
1
R1930
69
19
19
19
19
19
39 19
19
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
SEL
0
VER 1
A
VCC
1
B1
GND
B0
IN
OUT
OUTIN
D
S
G
IN
VIO_32K_B
VIOE_24M_A
VIOE_24M_B
X2
X1
VDD
VIOE_24M_C
VRTC
12M
VOUT
GND
OE_12M
32.768K_A
24M_A
24M_B
24M_C
32.768K_B
IN
IN
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
PROBE POINTS
GREENCLK CLOCK CONNECTIONS.
SERIES R FOR VOLTAGE DIVIDER WHEN PCH IS DRIVING IN L1 SUB-STATE.
LAST CHANGE: Thu Aug 4 21:00:42 2016
DESIGN: X502/MLB_CATZ
NOSTUFF / DELETE TO ALLOW INTERNAL PULL-DOWN FOR BSSB ON USB-SS.
UNUSED GPIO SIGNALS
IFDIM TRIGGERS USING R2055 & R2056 PADS
STUFF PULL-UP TO ENABLE BSSB (DCI) CLK/DI ON GPP_D11, _D12.
(STRAP-OPTION)
NOSTUFF / DELETE TO ALLOW INTERNAL PULL-DOWNS TO DISABLE.
UNUSED PCH XDP SIGNALS NEED TEST POINTS.
S3X SSD CONTROL
S3X SSD DOWN
(STRAP-OPTION)
PCH
PROJECT DEPENDANT
UNUSED GPIO SIGNALS
ASK DC/DC GROUP FOR DETAILS.
(STRAP-OPTION)
RESETS
STUFF PULL-UPS TO ENABLE INTERNAL GPU DP PORTS.
OPTION STRAPS
PCH 24MHz VIOE Options
EXTRA BPM TESTPOINTS
19 OF 73
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800
VOLTAGE=1V
MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800
VOLTAGE=1V
MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800
VOLTAGE=1V
MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0800
20 OF 500
1.0.0
051-02265
SOC_ALS_UART_D2R
=TBT_X_CLKREQ_L
SOC_UART_D2R
PCH_SWD_IO PCH_SWD_MUX_SEL
USB_EXTD_OC_L
XDP_BPM_L<2>
=PP3V3_S0_PCH
=SSD_CLKREQ_L
AUD_SPI_CS_L AUD_SPI_CLK
MAKE_BASE=TRUE
TP_SPKR_ID0
MAKE_BASE=TRUE
TP_SPKR_ID1
CAMERA_PWR_EN
AUD_PWR_EN
SOC_UART_RTS_L SOC_UART_CTS_L
MAKE_BASE=TRUE
PD_LCD_PSR_EN
CAMERA_PWR_EN_PCH
SPKR_ID1
SPKR_ID0
AUD_SPI_MISO
LCD_PSR_EN
PM_PCH_PWROK_BUF
=PP3V3_S0_PCH
MAKE_BASE=TRUE
PD_AUD_SPI_CLK
SOC_UART_R2D
AUD_SPI_MOSI
CAMERA_PWR_EN
DP_X_SNK1_ML_C_P<0> DP_X_SNK1_ML_C_N<0>
SOC_S2R_L
MAKE_BASE=TRUE
SOC_WAKE_L
CPU_CATERR_L
=PP1V_S3_CPU_VCCST
MAKE_BASE=TRUE
CPU_RSVD_AK13
PCH_DDPC_CTRLDATA
PCH_STRP_BSSB_SEL_GPIO
PCH_SWD_CLK
CAMERA_CLKREQ_L
MAKE_BASE=TRUE
PU_PCH_SWD_CLK
XDP_BPM_L<1>
XDP_BPM_L<0>
MAKE_BASE=TRUE
PD_SOC_UART_CTS_L
MAKE_BASE=TRUE
PD_PCH_SWD_MUX_SEL
MAKE_BASE=TRUE
PU_SOC_UART_D2R
MAKE_BASE=TRUE
PU_SOC_UART_R2D
MAKE_BASE=TRUE
PU_SOC_UART_RTS_L
MAKE_BASE=TRUE
PU_TBT_T_PLUG_EVENT_LTBT_T_PLUG_EVENT_L
MAKE_BASE=TRUE
TP_XDP_BPM_L<2>
JTAG_ISP_TCK
TP_CPU_RSVD_AK13
=PP3V3_S0_PCH
SYSCLK_CLK12M_SMC
MAKE_BASE=TRUE
PD_AUD_SPI_MISO
MAKE_BASE=TRUE
PU_AUD_SPI_CS_L
USB_EXTC_OC_L
MAKE_BASE=TRUE
PD_SSD_UART_CTS_L
MAKE_BASE=TRUE
PU_SSD_UART_D2R
MAKE_BASE=TRUE
PU_SSD_UART_R2D
PCIE_TBT_X_R2D_C_P<0> PCIE_TBT_X_R2D_C_N<0>
TBTXR2DP0
DPX1P0
MAKE_BASE=TRUE
TBT_X_PCI_RESET_LPM_PLT_RST_TBT_X_L
MAKE_BASE=TRUE
TBT_X_CLKREQ_R_L
SMC_LRESET_L
TBT_X_PCI_RESET_L
SSD_RESET_L
AP_RESET_L
=PP3V3_SUS_PCH_VCCPGPPB
JTAG_ISP_TDI
PCH_CLK24M_XTALIN
MAKE_BASE=TRUE
TP_SYSCLK_CLK24M_SSD
MAKE_BASE=TRUE
SSD_PWR_REQ STORAGE_LATCH
SSD_CLKREQ_L
SSD_CLKREQ_L
MAKE_BASE=TRUE
AP_CLKREQ_R_L=AP_CLKREQ_L
=CAMERA_CLKREQ_L
MAKE_BASE=TRUE
CAMERA_CLKREQ_R_L
TBT_X_CLKREQ_L
MAKE_BASE=TRUE
TP_XDP_BPM_L<3>
MAKE_BASE=TRUE
TP_XDP_BPM_L<1>
AP_CLKREQ_L
MAKE_BASE=TRUE
SSD_CLKREQ_R_L
CAMERA_RESET_LCAMERA_CLKREQ_L
SOC_ALS_UART_R2D
XDP_BPM_L<3>
MAKE_BASE=TRUE
PU_PCH_SWD_IO
MAKE_BASE=TRUE
PU_AUD_SPI_MOSI
PCH_DDPB_CTRLDATA
MAKE_BASE=TRUE
SYSCLK_CLK24M_PCH
MAKE_BASE=TRUE
SYSCLK_CLK24M_CAMERA
SYSCLK_CLK24M_SSD
AP_CLKREQ_L
TBT_X_CLKREQ_L
PLT_RST_L
=PP3V3_G3H_SYSCLK PP3V3_G3H
=PPVIO_CAMERA_BT_AP_32CLK
CLK25M_CAM_CLKP
PCH_CLK24M_XTALOUT
MAKE_BASE=TRUE
TP_PCH_CLK24M_XTALOUT
=PP3V3_S4_WLAN
MAKE_BASE=TRUE
PPVIO_BT_AP_32CLK
=PPVIOE_CAMCLK
=PPVIOE_PCHCLK
=PPVIOE_SSDCLK
MAKE_BASE=TRUE
PD_PPVIOE_SSDCLK
=PPVDDIO_S0_CAMCLK
MAKE_BASE=TRUE
PPVIOE_CAMCLK
PM_SLP_S0S3_L
PP1V_S5G
MAKE_BASE=TRUE
TP_PCH_CLK32K_RTCX2 PCH_CLK32K_RTCX2
MAKE_BASE=TRUE
SYSCLK_CLK32K_PCH PCH_CLK32K_RTCX1
=PPVIOE_PCHCLK
=PPVIOE_CAMCLK
SYSCLK_CLK32K_BT_AP
MAKE_BASE=TRUE
SYSCLK_CLK32K_BT_AP_R
SYSCLK_CLK32K_CAMERA_BT_AP
=PPVIO_CAMERA_BT_AP_32CLK
PM_PCH_PWROK
PCH_UART2_CTS_L
MAKE_BASE=TRUE
PP1V_SUSRS0SW_PCHCLK
PP1V_S5G_PCHCLK
PP1V_S0SW_PCHCLK
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
Chipset Support 2
201
MF
1/20W
5%
100K
2
1
R2041
201
MF
1/20W
5%
100K
2
1
R2040
60 14
SOT891
74LVC1G08
CRITICAL
4
6
5 3
1
2
U2040
0201
X5R-CERM
10V
10%
0.1UF
2
1
C2040
0201
MF
1/20W
5%
0
BT_CLK32K:YES
21
R2032
34
201
MF
1/20W
5%
100K
BT_CLK32K:NO
2
1
R2031
0201
MF
1/20W
5%
0
BT_CLK32K:YES
21
R2030
201
MF
1/20W
5%
470K
2
1
R2014
14
16
16
16
16
28 26
28 26
28 15
28 15
0201
X5R-CERM
16V
10%
PLACE_NEAR=C3040.1:1MM
NO_XNET_CONNECTION=1
0.1UF
NOSTUFF
2
1
C2093
0201
X5R-CERM
16V
10%
PLACE_NEAR=C3040.1:1MM
NO_XNET_CONNECTION=1
0.1UF
NOSTUFF
2
1
C2092
0201
X5R
6.3V
20%
PLACE_NEAR=C3040.1:1MM
NO_XNET_CONNECTION=1
0.22UF
NOSTUFF
2
1
C2091
0201
X5R
6.3V
20%
PLACE_NEAR=C3040.1:1MM
NO_XNET_CONNECTION=1
0.22UF
NOSTUFF
2
1
C2090
201
MF
1/20W
5%
PLACE_NEAR=C2090.2:5MM
51
DPX1N0
NOSTUFF
2
1
R2093
201
MF
1/20W
5%
PLACE_NEAR=C2090.2:6MM
51
NOSTUFF
2
1
R2092
201
MF
1/20W
5%
PLACE_NEAR=C3040.1:1MM
51
TBTXR2DN0
NOSTUFF
2
1
R2091
201
MF
1/20W
5%
PLACE_NEAR=C2090.2:1MM
51
NOSTUFF
2
1
R2090
6
6
6
15
201 MF
1/20W 5%
1K
21
R2004
26 19
201MF1/20W5%
47K
21
R2072
201MF1/20W5%
100K
21
R2013
201MF1/20W5%
33
21
R2015
39
SM
21
XW2002
SM
2 1
XW2065
0201
X5R-CERM
10V
10%
BYPASS=U1900.05:18:5MM
0.1UF
2
1
C2004
0201
X5R-CERM
10V
10%
BYPASS=U1900.02:18:5MM
0.1UF
2
1
C2005
0201
X5R-CERM
10V
10%
BYPASS=U1900.12:18:5MM
0.1UF
2
1
C2006
13
DFN1006H4-3
DMN32D2LFB4
CRITICAL
PCH24M:S0SW
2
1
3
Q2065
72 68 60
0201
MF
1/20W
5%
0
PCH24M:S0SW
21
R2066
0201
MF
1/20W
5%
0
PCH24M:SUS
21
R2065
16
16
16
16
SM
21
XW2000
15
201 MF
1/20W 5%
1K
21
R2003
36 19
15
201 MF
1/20W 5%
1K
21
R2002
35 34 19
201 MF
1/20W 5%
1K
21
R2001
15 67 19
36 13
35 34 16
67 16
28 19 16
201MF1/20W5%
47K
21
R2075
201MF1/20W5%
47K
21
R2074
201MF1/20W5%
47K
21
R2071
17
TP-P6
1
TP2073
68 39 6
201
MF
1/20W
5%
51
2
1
R2061
6
6
402
MF-LF
1/16W
5%
100K
NOSTUFF
21
R2056
402
MF-LF
1/16W
5%
100K
NOSTUFF
21
R2055
14
14
14
15
16
13
TP-P6
1
TP2072
TP-P6
1
TP2071
17
28 17
28 17
TP-P6
1
TP2070
13
0201
MF
1/20W
5%
0
21
R2060
36 19 13
13
13
16
60 67
39 18 39 18
18 36
18
18
18
18
15
15
15
15
68 35 14
201MF1/20W5%
1K
BSSB_ON_GPIOS
21
R2022
201MF1/20W5%
2.2K
IG_DDI2_EN
21
R2021
201MF1/20W5%
2.2K
IG_DDI1_EN
21
R2020
201MF1/20W5%
100K
21
R2012
201MF1/20W5%
100K
21
R2010
201MF1/20W5%
100K
21
R2011
69 60 19 16 14 13 5
70
36 19 13
49 16
69 60 19 16 14 13 5
69 59 54 14 10 8 6
13
13
70
69 60 19 16 14 13 5
28 19 16
26
69 12 8
70
67 19
70
70
35 34 19
36 19
13
26 19
18
72
69 68 60 53 52 51 47 42 41 28
19 18
70
69 34
19 18
19 18
18
36
72 69 64 63 62
70
19 18
19 18
19 18
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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PAGE TITLE
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NOTICE OF PROPRIETARY PROPERTY:
A
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C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
NC
08
NC
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT IN
OUT
IN
G S
SYM_VER_3
D
IN
IN
OUT
IN
IN
OUT IN
OUT IN
OUT IN
OUT
OUT
OUT
OUT
IN
TP
OUT
IN
IN
IN
BI
IN
OUT
IN
IN
TP
TP
IN
IN
IN
TP
IN OUT
OUT
IN
OUT
OUT IN
IN OUT
IN OUT
IN
IN
IN
IN
IN
OUT
IN
OUT
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
CPU-Based Margining
VREFCA. Connected to 4 DRAMs.
VRef Dividers
NOTE: CPU has single output for VREFCA.
051-02265
1.0.0
20 OF 73
22 OF 500
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1800
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1800
MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000
PPVREF_S3_MEM_VREFDQ_A
PPVREF_S3_MEM_VREFDQ_B
PPVREF_S3_MEM_VREFCACPU_DIMM_VREFCA
=PPDDR_S3_MEMVREF
MEM_VREFDQ_B_RC
CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ
MEM_VREFCA_RC
MEM_VREFDQ_A_RC
SYNC_DATE=12/03/2015SYNC_MASTER=X502-EXP
BOM_COST_GROUP=CPU & CHIPSET
LPDDR3 VREF Margining
201
MF
1/20W
1%
8.2K
2
1
R2221
201
MF
1/20W
1%
8.2K
2
1
R2241
201
MF
1/20W
1%
PLACE_NEAR=R2221.2:1mm
8.2K
2
1
R2222
201
MF
1/20W
1%
24.9
21
R2220
201
MF
1/20W
1%
8.2K
2
1
R2261
201
MF
1/20W
1%
PLACE_NEAR=R2241.2:1mm
8.2K
2
1
R2242
201
MF
1/20W
1%
24.9
21
R2240
201
MF
1/20W
1%
PLACE_NEAR=R2261.2:1mm
8.2K
2
1
R2262
201
MF
1/20W
1%
24.9
21
R2260
201
MF
1/20W
1%
10
21
R2223
0201
X5R-CERM
6.3V
10%
0.022UF
2
1
C2220
201
MF
1/20W
1%
10
21
R2243
0201
X5R-CERM
6.3V
10%
0.022UF
2
1
C2240
0201
MF
1/20W
1%
5.1
21
R2263
0201
X5R-CERM
6.3V
10%
0.022UF
2
1
C2260
7
7
7
69
69
69
69
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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REVISION
DRAWING NUMBER SIZE
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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A
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2 1
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NOTICE OF PROPRIETARY PROPERTY:
A
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C
345678
D
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8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
LPDDR3 CHANNEL A (0-31)
Distribute evenly.
10uF caps are shared between DRAM.
PLACEMENT_NOTE:
23 OF 500
051-02265
1.0.0
21 OF 73
=PP1V2_S3_MEM_VDDQ
=MEM_A_DQ<26>
=MEM_A_DQ<30> =MEM_A_DQ<31>
MEM_A_CS_L<0> MEM_A_CS_L<1>
MEM_A_CKE<0>
=MEM_A_DQS_N<2> =MEM_A_DQS_N<3>
=MEM_A_DQ<21>
=MEM_A_DQS_P<0>
MEM_A_CAA<2>
MEM_A_ODT<0>
=MEM_A_DQS_N<0> =MEM_A_DQS_N<1>
=MEM_A_DQ<25>
MEM_A_CLK_N<0>
MEM_A_CAA<6>
MEM_A_CAA<0> MEM_A_CAA<1>
MEM_A_CAA<5>
=MEM_A_DQ<0>
=MEM_A_DQ<10> =MEM_A_DQ<11> =MEM_A_DQ<12>
=MEM_A_DQ<15> =MEM_A_DQ<16> =MEM_A_DQ<17> =MEM_A_DQ<18> =MEM_A_DQ<19>
=MEM_A_DQ<2>
=MEM_A_DQ<20>
=MEM_A_DQ<23> =MEM_A_DQ<24>
=MEM_A_DQ<27> =MEM_A_DQ<28> =MEM_A_DQ<29>
=MEM_A_DQ<3>
=MEM_A_DQ<7> =MEM_A_DQ<8> =MEM_A_DQ<9>
PP0V6_S3_MEM_VREFDQ_A
MEM_A_CAA<7>
=MEM_A_DQ<22>
=MEM_A_DQ<1>
MEM_A_ZQ<0> MEM_A_ZQ<1>
=MEM_A_DQ<14>
MEM_A_CAA<4>
MEM_A_CAA<3>
=PP1V2_S3_MEM_VDDCA
=PP1V2_S3_MEM_VDD2
=MEM_A_DQ<5>
=MEM_A_DQ<4>
=MEM_A_DQ<6>
=PP1V8_S3_MEM
MEM_A_CAA<9>
MEM_A_CAA<8>
=PP1V2_S3_MEM_VDDQ
=MEM_A_DQ<13>
PP0V6_S3_MEM_VREFCA_A
=PP1V8_S3_MEM
=PP1V2_S3_MEM_VDD2
=PP1V2_S3_MEM_VDDCA
=MEM_A_DQS_P<1> =MEM_A_DQS_P<2> =MEM_A_DQS_P<3>
MEM_A_CLK_P<0>
MEM_A_CKE<1>
SYNC_DATE=12/03/2015SYNC_MASTER=X502-EXP
LPDDR3 DRAM Channel A (00-31)
BOM_COST_GROUP=DRAM
71
243
1%
1/20W
MF
201
2
1
R2301
243
1%
1/20W
MF
201
2
1
R2300
71
72 25 22 7
72 25 22 7
72 25 22 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
71
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
3PF
+/-0.1PF 25V C0G 0201
2
1
C2380
12PF
5% 25V CERM 0201
2
1
C2381
3PF
+/-0.1PF 25V C0G 0201
2
1
C2382
71
12PF
5% 25V CERM 0201
2
1
C2383
1.0UF
20%
6.3V X5R 0201-1
2
1
C2313
OMIT_TABLE
CRITICAL
LPDDR3-1600-32GB
EDFB232A1MA
FBGA
B4
B3
J11
H4
J8
U13
U12
U2
U1
T13
T1
B13
B1
A13
A12
A2
A1
R3
K9
C4
D10
D11
P10
P11
G10
G11
L10
L11
B8
B9
B10
B11
C8
C9
C10
C11
R11
R10
R9
R8
T11
T10
T9
T8
D9
E9
E10
E11
F8
F9
F10
F11
M11
M10
M9
M8
N11
N10
N9
P9
D8
P8
G8
L8
L4
L3
K4
K3
J3
J2
C2
D2
E2
E3
F3
M3
N3
N2
P2
R2
U2300
OMIT_TABLE
CRITICAL
LPDDR3-1600-32GB
EDFB232A1MA
FBGA
T12
T6
R6
P12
N6
M12
M6
L9
K10
H10
G9
G6
F12
F6
E6
D12
C6
B12
B6
J4
M4
P3
G4
G3
F4
D3
C3
H2
T5
T4
T3
T2
R5
R4
N5
N4
M5
L6
K2
J12
F5
E5
E4
C5
B5
B2
U11
R12
N12
N8
L12
K11
K8
J10
J9
H11
H9
H8
G12
E12
E8
C12
A11
M2
L2
H3
G2
F2
U9
U8
P6
P5
P4
L5
K12
K6
K5
J6
J5
H12
H6
H5
G5
D6
D5
D4
A9
A8
U10
U6
U5
U4
U3
A10
A6
A5
A4
A3
U2300
0.047UF
10%
6.3V X5R 201
2
1
C2340
0.047UF
10%
6.3V X5R 201
2
1
C2341
71
1.0UF
20%
6.3V X5R 0201-1
2
1
C2330
1.0UF
20%
6.3V X5R 0201-1
2
1
C2331
CRITICAL
10UF
20%
6.3V CERM 0402
2
1
C2332
CRITICAL
10UF
20%
6.3V CERM 0402
2
1
C2333
CRITICAL
10UF
20%
6.3V CERM 0402
2
1
C2323
CRITICAL
10UF
20%
6.3V CERM 0402
2
1
C2324
71
1.0UF
20%
6.3V X5R 0201-1
2
1
C2322
1.0UF
20%
6.3V X5R 0201-1
2
1
C2321
1.0UF
20%
6.3V X5R 0201-1
2
1
C2320
CRITICAL
10UF
20%
6.3V CERM 0402
2
1
C2312
1.0UF
20%
6.3V X5R 0201-1
2
1
C2311
1.0UF
20%
6.3V X5R 0201-1
2
1
C2310
71
1.0UF
20%
6.3V X5R 0201-1
2
1
C2305
0.1UF
10% 16V X5R-CERM 0201
2
1
C2301
1.0UF
20%
6.3V X5R 0201-1
2
1
C2304
1.0UF
20%
6.3V X5R 0201-1
2
1
C2303
0.1UF
10% 16V X5R-CERM 0201
2
1
C2300
71
1.0UF
20%
6.3V X5R 0201-1
2
1
C2302
CRITICAL
10UF
20%
6.3V CERM 0402
2
1
C2307
CRITICAL
10UF
20%
6.3V CERM 0402
2
1
C2306
71
71
69 24 23 22 21
69 22
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 22
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
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A
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2 1
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
NC NC NC NC NC NC NC NC NC NC NC NC
NC NC NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
SYM 1 OF 2
DQ13
CS0*
DM2
DM1
DM0
CS1*
DM3
CA8
CKE0
CK_T
DQS2_C
DQS3_C
DQ21
CA9
DQS0_T
DQS2_T
CA2
ODT
DQS0_C
DQS1_C
DQ25
CK_C
CA6
CA0
CA1
CA3
CA4
CA5
CKE1
DQ0
DQ10
DQ11
DQ12
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ2
DQ20
DQ23
DQ24
DQ26
DQ27
DQ28
DQ29
DQ3
DQ30
DQ31
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQS1_T
DQS3_T
VREFCA
VREFDQ
CA7
NU
DQ22
DQ1
NC
ZQ0
ZQ1
SYM 2 OF 2
VSSCA
VDD1
VDD2
VDDCA
VDDQ
VSS
VSSQ
BI
BI
BI
BI
BI
BI
合肥怡飞苹果维修qq:82669515 qq群: 241000
LPDDR3 CHANNEL A (32-63)
Distribute evenly.
PLACEMENT_NOTE:
10uF caps are shared between DRAM.
24 OF 500
22 OF 73
051-02265
1.0.0
MEM_A_CAB<6>
MEM_A_CKE<3>
=PP1V2_S3_MEM_VDDQ
=MEM_A_DQ<33>
=MEM_A_DQ<35>
=MEM_A_DQ<34>
=MEM_A_DQ<36>
=MEM_A_DQ<56>
=MEM_A_DQ<32>
MEM_A_CS_L<0>
MEM_A_CLK_N<1>
MEM_A_CS_L<1>
MEM_A_ZQ<2>
=PP1V2_S3_MEM_VDDCA
=PP1V2_S3_MEM_VDD2
=PP1V8_S3_MEM
=MEM_A_DQ<39>
=MEM_A_DQS_P<5>
=MEM_A_DQS_N<7>
=MEM_A_DQS_N<6>
=MEM_A_DQS_N<5>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DQ<46>
=MEM_A_DQS_P<7>
=MEM_A_DQ<45>
=MEM_A_DQ<50>
=MEM_A_DQ<38>
=MEM_A_DQ<41>
=MEM_A_DQ<62> =MEM_A_DQ<63>
=MEM_A_DQ<61>
=MEM_A_DQ<59> =MEM_A_DQ<60>
=MEM_A_DQ<57> =MEM_A_DQ<58>
=MEM_A_DQ<54> =MEM_A_DQ<55>
=MEM_A_DQ<52> =MEM_A_DQ<53>
=MEM_A_DQ<51>
=MEM_A_DQ<47> =MEM_A_DQ<48>
=MEM_A_DQ<44>
=MEM_A_DQ<42> =MEM_A_DQ<43>
=MEM_A_DQ<40>
MEM_A_CAB<7>
PP0V6_S3_MEM_VREFDQ_A
PP0V6_S3_MEM_VREFCA_A
MEM_A_CAB<5>
MEM_A_CAB<4>
MEM_A_CAB<3>
MEM_A_CAB<1>
MEM_A_CAB<0>
MEM_A_ODT<0>
MEM_A_CAB<2>
MEM_A_CAB<9>
MEM_A_CLK_P<1>
MEM_A_CKE<2>
MEM_A_CAB<8>
MEM_A_ZQ<3>
=PP1V2_S3_MEM_VDDQ
=MEM_A_DQS_P<6>
=PP1V2_S3_MEM_VDDCA
=MEM_A_DQ<49>
=PP1V8_S3_MEM
=PP1V2_S3_MEM_VDD2
=MEM_A_DQ<37>
SYNC_DATE=12/03/2015SYNC_MASTER=X502-EXP
BOM_COST_GROUP=DRAM
LPDDR3 DRAM Channel A (32-63)
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2402
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2422
0201
X5R-CERM
16V
10%
0.1UF
2
1
C2401
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2421
0201
X5R-CERM
16V
10%
0.1UF
2
1
C2400
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2420
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2432
71
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2411
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2410
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2431
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2430
71
72 25 21 7
72 25 21 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
71
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
0201
C0G
25V
+/-0.1PF
3PF
2
1
C2480
0201
CERM
25V
5%
12PF
2
1
C2481
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2413
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2412
0201
C0G
25V
+/-0.1PF
3PF
2
1
C2482
0201
CERM
25V
5%
12PF
2
1
C2483
71
FBGA
EDFB232A1MA
LPDDR3-1600-32GB
CRITICAL
OMIT_TABLE
T12
T6
R6
P12
N6
M12
M6
L9
K10
H10
G9
G6
F12
F6
E6
D12
C6
B12
B6
J4
M4
P3
G4
G3
F4
D3
C3
H2
T5
T4
T3
T2
R5
R4
N5
N4
M5
L6
K2
J12
F5
E5
E4
C5
B5
B2
U11
R12
N12
N8
L12
K11
K8
J10
J9
H11
H9
H8
G12
E12
E8
C12
A11
M2
L2
H3
G2
F2
U9
U8
P6
P5
P4
L5
K12
K6
K5
J6
J5
H12
H6
H5
G5
D6
D5
D4
A9
A8
U10
U6
U5
U4
U3
A10
A6
A5
A4
A3
U2400
FBGA
EDFB232A1MA
LPDDR3-1600-32GB
CRITICAL
OMIT_TABLE
B4
B3
J11
H4
J8
U13
U12
U2
U1
T13
T1
B13
B1
A13
A12
A2
A1
R3
K9
C4
D10
D11
P10
P11
G10
G11
L10
L11
B8
B9
B10
B11
C8
C9
C10
C11
R11
R10
R9
R8
T11
T10
T9
T8
D9
E9
E10
E11
F8
F9
F10
F11
M11
M10
M9
M8
N11
N10
N9
P9
D8
P8
G8
L8
L4
L3
K4
K3
J3
J2
C2
D2
E2
E3
F3
M3
N3
N2
P2
R2
U2400
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2424
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2407
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2433
201
X5R
6.3V
10%
0.047UF
2
1
C2441
71
201
X5R
6.3V
10%
0.047UF
2
1
C2440
201
MF
1/20W
1%
243
2
1
R2401
201
MF
1/20W
1%
243
2
1
R2400
72 25 21 7
71
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2406
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2405
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2404
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2403
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2423
71
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 21
69 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
NC NC NC NC NC NC NC NC NC NC NC NC
NC NC NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
SYM 2 OF 2
VSSCA
VDD1
VDD2
VDDCA
VDDQ
VSS
VSSQ
SYM 1 OF 2
DQ13
CS0*
DM2
DM1
DM0
CS1*
DM3
CA8
CKE0
CK_T
DQS2_C
DQS3_C
DQ21
CA9
DQS0_T
DQS2_T
CA2
ODT
DQS0_C
DQS1_C
DQ25
CK_C
CA6
CA0
CA1
CA3
CA4
CA5
CKE1
DQ0
DQ10
DQ11
DQ12
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ2
DQ20
DQ23
DQ24
DQ26
DQ27
DQ28
DQ29
DQ3
DQ30
DQ31
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQS1_T
DQS3_T
VREFCA
VREFDQ
CA7
NU
DQ22
DQ1
NC
ZQ0
ZQ1
BI
IN
BI
BI
合肥怡飞苹果维修qq:82669515 qq群: 241000
PLACEMENT_NOTE:
10uF caps are shared between DRAM. Distribute evenly.
LPDDR3 CHANNEL B (0-31)
051-02265
1.0.0
25 OF 500
23 OF 73
MEM_B_CS_L<1>
MEM_B_CKE<0>
MEM_B_CAA<9>
MEM_B_CAA<6>
MEM_B_CAA<3>
MEM_B_CAA<5>
MEM_B_CAA<7>
MEM_B_ZQ<0>
=MEM_B_DQ<0> =MEM_B_DQ<1> =MEM_B_DQ<2> =MEM_B_DQ<3> =MEM_B_DQ<4> =MEM_B_DQ<5> =MEM_B_DQ<6>
=MEM_B_DQ<8> =MEM_B_DQ<9>
=MEM_B_DQ<13>
=MEM_B_DQ<15>
=MEM_B_DQ<24> =MEM_B_DQ<25>
=MEM_B_DQ<27>
=MEM_B_DQ<31>
=MEM_B_DQS_N<0> =MEM_B_DQS_N<1> =MEM_B_DQS_N<2>
=MEM_B_DQS_P<0> =MEM_B_DQS_P<1> =MEM_B_DQS_P<2> =MEM_B_DQS_P<3>
=MEM_B_DQ<11> =MEM_B_DQ<12>
=MEM_B_DQ<28>
=MEM_B_DQ<23>
=MEM_B_DQ<26>
=MEM_B_DQ<29>
=MEM_B_DQS_N<3>
=MEM_B_DQ<16> =MEM_B_DQ<17> =MEM_B_DQ<18> =MEM_B_DQ<19>
=MEM_B_DQ<14>
=MEM_B_DQ<10>
=PP1V8_S3_MEM
=PP1V2_S3_MEM_VDD2
=PP1V2_S3_MEM_VDDQ
MEM_B_ODT<0>
MEM_B_CS_L<0>
=PP1V2_S3_MEM_VDDQ
=MEM_B_DQ<22>
=MEM_B_DQ<21>
=MEM_B_DQ<20>
=MEM_B_DQ<30>
MEM_B_ZQ<1>
MEM_B_CLK_N<0>
PP0V6_S3_MEM_VREFDQ_B
PP0V6_S3_MEM_VREFCA_B
MEM_B_CAA<8>
MEM_B_CAA<4>
=PP1V2_S3_MEM_VDDCA
=PP1V2_S3_MEM_VDDCA
MEM_B_CAA<2>
MEM_B_CAA<0>
=PP1V8_S3_MEM
=PP1V2_S3_MEM_VDD2
=MEM_B_DQ<7>
MEM_B_CKE<1>
MEM_B_CAA<1>
MEM_B_CLK_P<0>
SYNC_DATE=12/03/2015SYNC_MASTER=X502-EXP
LPDDR3 DRAM Channel B (00-31)
BOM_COST_GROUP=DRAM
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2502
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2522
0201
X5R-CERM
16V
10%
0.1UF
2
1
C2501
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2521
0201
X5R-CERM
16V
10%
0.1UF
2
1
C2500
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2520
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2532
71
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2511
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2510
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2531
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2530
71
72 25 24 7
72 25 24 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
71
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
0201
C0G
25V
+/-0.1PF
3PF
2
1
C2580
0201
CERM
25V
5%
12PF
2
1
C2581
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2513
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2512
0201
C0G
25V
+/-0.1PF
3PF
2
1
C2582
71
0201
CERM
25V
5%
12PF
2
1
C2583
FBGA
EDFB232A1MA
LPDDR3-1600-32GB
CRITICAL
OMIT_TABLE
T12
T6
R6
P12
N6
M12
M6
L9
K10
H10
G9
G6
F12
F6
E6
D12
C6
B12
B6
J4
M4
P3
G4
G3
F4
D3
C3
H2
T5
T4
T3
T2
R5
R4
N5
N4
M5
L6
K2
J12
F5
E5
E4
C5
B5
B2
U11
R12
N12
N8
L12
K11
K8
J10
J9
H11
H9
H8
G12
E12
E8
C12
A11
M2
L2
H3
G2
F2
U9
U8
P6
P5
P4
L5
K12
K6
K5
J6
J5
H12
H6
H5
G5
D6
D5
D4
A9
A8
U10
U6
U5
U4
U3
A10
A6
A5
A4
A3
U2500
FBGA
EDFB232A1MA
LPDDR3-1600-32GB
CRITICAL
OMIT_TABLE
B4
B3
J11
H4
J8
U13
U12
U2
U1
T13
T1
B13
B1
A13
A12
A2
A1
R3
K9
C4
D10
D11
P10
P11
G10
G11
L10
L11
B8
B9
B10
B11
C8
C9
C10
C11
R11
R10
R9
R8
T11
T10
T9
T8
D9
E9
E10
E11
F8
F9
F10
F11
M11
M10
M9
M8
N11
N10
N9
P9
D8
P8
G8
L8
L4
L3
K4
K3
J3
J2
C2
D2
E2
E3
F3
M3
N3
N2
P2
R2
U2500
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2524
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2507
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2533
71
201
X5R
6.3V
10%
0.047UF
2
1
C2541
201
X5R
6.3V
10%
0.047UF
2
1
C2540
201
MF
1/20W
1%
243
2
1
R2501
201
MF
1/20W
1%
243
2
1
R2500
72 25 24 7
71
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2506
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2505
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2504
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2503
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2523
71
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24
69 24
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
NC NC NC NC NC NC NC NC NC NC NC NC
NC NC NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
SYM 2 OF 2
VSSCA
VDD1
VDD2
VDDCA
VDDQ
VSS
VSSQ
SYM 1 OF 2
DQ13
CS0*
DM2
DM1
DM0
CS1*
DM3
CA8
CKE0
CK_T
DQS2_C
DQS3_C
DQ21
CA9
DQS0_T
DQS2_T
CA2
ODT
DQS0_C
DQS1_C
DQ25
CK_C
CA6
CA0
CA1
CA3
CA4
CA5
CKE1
DQ0
DQ10
DQ11
DQ12
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ2
DQ20
DQ23
DQ24
DQ26
DQ27
DQ28
DQ29
DQ3
DQ30
DQ31
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQS1_T
DQS3_T
VREFCA
VREFDQ
CA7
NU
DQ22
DQ1
NC
ZQ0
ZQ1
BI
IN
BI
BI
合肥怡飞苹果维修qq:82669515 qq群: 241000
10uF caps are shared between DRAM.
PLACEMENT_NOTE:
Distribute evenly.
LPDDR3 CHANNEL B (32-63)
26 OF 500
051-02265
1.0.0
24 OF 73
=PP1V2_S3_MEM_VDDCA
=MEM_B_DQ<46>
MEM_B_CS_L<0> MEM_B_CS_L<1>
MEM_B_CAB<8> MEM_B_CAB<9>
MEM_B_CAB<2>
MEM_B_CLK_N<1>
MEM_B_CAB<6>
MEM_B_CAB<1>
MEM_B_CAB<3> MEM_B_CAB<4> MEM_B_CAB<5>
PP0V6_S3_MEM_VREFCA_B PP0V6_S3_MEM_VREFDQ_B
MEM_B_CAB<7>
=MEM_B_DQ<32> =MEM_B_DQ<33> =MEM_B_DQ<34> =MEM_B_DQ<35> =MEM_B_DQ<36>
=MEM_B_DQ<38> =MEM_B_DQ<39> =MEM_B_DQ<40> =MEM_B_DQ<41> =MEM_B_DQ<42> =MEM_B_DQ<43> =MEM_B_DQ<44> =MEM_B_DQ<45>
=MEM_B_DQ<47> =MEM_B_DQ<48> =MEM_B_DQ<49> =MEM_B_DQ<50>
=MEM_B_DQ<52> =MEM_B_DQ<53> =MEM_B_DQ<54> =MEM_B_DQ<55> =MEM_B_DQ<56> =MEM_B_DQ<57> =MEM_B_DQ<58> =MEM_B_DQ<59> =MEM_B_DQ<60> =MEM_B_DQ<61> =MEM_B_DQ<62> =MEM_B_DQ<63>
=MEM_B_DQS_N<4>
=MEM_B_DQS_N<7>
=MEM_B_DQS_P<4> =MEM_B_DQS_P<5> =MEM_B_DQS_P<6> =MEM_B_DQS_P<7>
=MEM_B_DQ<51>
=PP1V8_S3_MEM
=PP1V2_S3_MEM_VDDQ
MEM_B_ZQ<3>
MEM_B_ZQ<2>
MEM_B_ODT<0>
=PP1V2_S3_MEM_VDDQ
=PP1V2_S3_MEM_VDD2
MEM_B_CKE<3>
MEM_B_CKE<2>
=MEM_B_DQS_N<5> =MEM_B_DQS_N<6>
=PP1V2_S3_MEM_VDDCA
=MEM_B_DQ<37>
=PP1V8_S3_MEM
=PP1V2_S3_MEM_VDD2
MEM_B_CLK_P<1>
MEM_B_CAB<0>
LPDDR3 DRAM Channel B (32-63)
BOM_COST_GROUP=DRAM
SYNC_MASTER=X502-EXP SYNC_DATE=12/03/2015
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2602
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2622
0201
X5R-CERM
16V
10%
0.1UF
2
1
C2601
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2621
0201
X5R-CERM
16V
10%
0.1UF
2
1
C2600
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2620
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2632
71
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2611
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2610
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2631
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2630
71
72 25 23 7
72 25 23 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
71
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
72 25 7
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
0201
C0G
25V
+/-0.1PF
3PF
2
1
C2680
0201
CERM
25V
5%
12PF
2
1
C2681
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2613
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2612
0201
C0G
25V
+/-0.1PF
3PF
2
1
C2682
0201
CERM
25V
5%
12PF
2
1
C2683
71
FBGA
EDFB232A1MA
LPDDR3-1600-32GB
CRITICAL
OMIT_TABLE
T12
T6
R6
P12
N6
M12
M6
L9
K10
H10
G9
G6
F12
F6
E6
D12
C6
B12
B6
J4
M4
P3
G4
G3
F4
D3
C3
H2
T5
T4
T3
T2
R5
R4
N5
N4
M5
L6
K2
J12
F5
E5
E4
C5
B5
B2
U11
R12
N12
N8
L12
K11
K8
J10
J9
H11
H9
H8
G12
E12
E8
C12
A11
M2
L2
H3
G2
F2
U9
U8
P6
P5
P4
L5
K12
K6
K5
J6
J5
H12
H6
H5
G5
D6
D5
D4
A9
A8
U10
U6
U5
U4
U3
A10
A6
A5
A4
A3
U2600
FBGA
EDFB232A1MA
LPDDR3-1600-32GB
CRITICAL
OMIT_TABLE
B4
B3
J11
H4
J8
U13
U12
U2
U1
T13
T1
B13
B1
A13
A12
A2
A1
R3
K9
C4
D10
D11
P10
P11
G10
G11
L10
L11
B8
B9
B10
B11
C8
C9
C10
C11
R11
R10
R9
R8
T11
T10
T9
T8
D9
E9
E10
E11
F8
F9
F10
F11
M11
M10
M9
M8
N11
N10
N9
P9
D8
P8
G8
L8
L4
L3
K4
K3
J3
J2
C2
D2
E2
E3
F3
M3
N3
N2
P2
R2
U2600
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2624
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2607
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2633
71
201
X5R
6.3V
10%
0.047UF
2
1
C2641
201
X5R
6.3V
10%
0.047UF
2
1
C2640
201
MF
1/20W
1%
243
2
1
R2601
201
MF
1/20W
1%
243
2
1
R2600
71
72 25 23 7
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2606
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2605
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2604
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2603
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2623
71
69 24 23 22 21
69 23
69 23
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
69 24 23 22 21
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
NC NC NC NC NC NC NC NC NC NC NC NC
NC NC NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
SYM 2 OF 2
VSSCA
VDD1
VDD2
VDDCA
VDDQ
VSS
VSSQ
SYM 1 OF 2
DQ13
CS0*
DM2
DM1
DM0
CS1*
DM3
CA8
CKE0
CK_T
DQS2_C
DQS3_C
DQ21
CA9
DQS0_T
DQS2_T
CA2
ODT
DQS0_C
DQS1_C
DQ25
CK_C
CA6
CA0
CA1
CA3
CA4
CA5
CKE1
DQ0
DQ10
DQ11
DQ12
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ2
DQ20
DQ23
DQ24
DQ26
DQ27
DQ28
DQ29
DQ3
DQ30
DQ31
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQS1_T
DQS3_T
VREFCA
VREFDQ
CA7
NU
DQ22
DQ1
NC
ZQ0
ZQ1
BI
BI
IN
BI
合肥怡飞苹果维修qq:82669515 qq群: 241000
Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK
25 OF 73
27 OF 500
1.0.0
051-02265
MEM_A_CAB<3>
MEM_A_CAB<0>
MEM_A_CAA<3>
MEM_A_CAB<1>
MEM_A_CLK_N<1>
MEM_A_CAB<5>
MEM_A_CAA<1>
MEM_A_CAA<2>
MEM_A_ODT<0>
MEM_A_CKE<3>
MEM_A_CS_L<1>
MEM_A_CS_L<0>
MEM_A_CLK_P<0>
MEM_A_CAA<8>
MEM_A_CAA<7>
MEM_A_CAA<9>
MEM_A_CAA<4>
MEM_A_CKE<1> MEM_A_CKE<0>
MEM_A_CAB<2>
MEM_A_CLK_N<0>
MEM_A_CAB<9>
MEM_A_CAA<0>
MEM_A_CAB<6>
MEM_B_CAA<0>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAB<6> MEM_B_CAB<5>
MEM_B_CKE<3>
MEM_B_CAA<2>
MEM_B_CAA<9> MEM_B_CAA<8> MEM_B_CAA<7>
MEM_B_CKE<0>
MEM_B_CLK_N<0> MEM_B_CKE<1>
MEM_B_CAA<3>
MEM_B_CLK_P<0>
MEM_A_CKE<2>
MEM_A_CLK_P<1>
MEM_A_CAA<5>
=PP0V6_S0_MEM_VTT_A
MEM_B_CAA<1>
MEM_A_CAA<6>
MEM_B_CS_L<0>
MEM_B_CAB<1>
MEM_B_CAB<3>
MEM_A_CAB<7>
MEM_B_CAB<7>
MEM_B_CAB<0>
MEM_B_CAB<2>
MEM_B_CAB<4>MEM_A_CAB<4>
MEM_B_CS_L<1>
MEM_B_CKE<2>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CAB<9> MEM_B_CAB<8>MEM_A_CAB<8>
MEM_B_ODT<0>
=PP0V6_S0_MEM_VTT_B
LPDDR3 DRAM Termination
BOM_COST_GROUP=DRAM
SYNC_MASTER=X502-EXP SYNC_DATE=12/03/2015
0402
CERM-X5R
6.3V
20%
20UF
CRITICAL
NOSTUFF
2
1
C2721
0402
CERM-X5R
6.3V
20%
20UF
CRITICAL
NOSTUFF
2
1
C2741
0201
C0G
25V
+/-0.1PF
3PF
2
1
C2742
0201
C0G
25V
+/-0.1PF
3PF
2
1
C2722
0201
CERM
25V
5%
12PF
2
1
C2731
0201
CERM
25V
5%
12PF
2
1
C2730
201 MF1/20W1%
68 21R2767
201 MF1/20W1%
68 21R2766
201 MF1/20W1%
68 21R2765
201 MF1/20W1%
68 21R2764
201 MF1/20W1%
68 21R2758
201 MF1/20W1%
68 21R2757
201 MF1/20W1%
68 21R2756
201 MF1/20W1%
68 21R2755
201 MF1/20W1%
68 21R2753
201 MF1/20W1%
68 21R2752
201 MF1/20W1%
68 21R2751
201 MF1/20W1%
68 21R2743
201 MF1/20W1%
68 21R2742
201 MF1/20W1%
68 21R2741
201 MF1/20W1%
68 21R2740
201 MF1/20W1%
68 21R2727
201 MF1/20W1%
68 21R2726
201 MF1/20W1%
68 21R2725
201 MF1/20W1%
68 21R2724
201 MF1/20W1%
68 21R2715
201 MF1/20W1%
68 21R2716
201 MF1/20W1%
68 21R2717
201 MF1/20W1%
68 21R2718
201 MF1/20W1%
68 21R2711
201 MF1/20W1%
68 21R2713
201 MF1/20W1%
68 21R2712
201 MF1/20W1%
68 21R2703
201 MF1/20W1%
68 21R2702
201 MF1/20W1%
68 21R2701
201 MF1/20W1%
68 21R2700
0402
CERM-X5R
6.3V
20%
20UF
CRITICAL
2
1
C2740
0402
CERM-X5R
6.3V
20%
20UF
CRITICAL
2
1
C2720
201 MF1/20W1%
68 21R2754
201 MF1/20W1%
68 21R2714
201 MF1/20W1%
82 21R2770
201 MF1/20W1%
82 21R2769
201 MF1/20W1%
82 21R2768
201 MF1/20W1%
68 21R2763
201 MF1/20W1%
82 21R2762
201 MF1/20W1%
82 21R2761
201 MF1/20W1%
39 21R2760
201 MF1/20W1%
39 21R2759
201 MF1/20W1%
68 21R2750
201 MF1/20W1%
68 21R2749
201 MF1/20W1%
82 21R2748
201 MF1/20W1%
82 21R2747
201 MF1/20W1%
39 21R2746
201 MF1/20W1%
39 21R2745
201 MF1/20W1%
68 21R2744
201 MF1/20W1%
82 21R2730
201 MF1/20W1%
82 21R2729
201 MF1/20W1%
82 21R2728
68
201 MF1/20W1%
21R2723
201 MF1/20W1%
82 21R2722
201 MF1/20W1%
82 21R2721
201 MF1/20W1%
39 21R2720
201 MF1/20W1%
39 21R2719
201 MF1/20W1%
68 21R2710
201 MF1/20W1%
68 21R2709
201 MF1/20W1%
82 21R2708
201 MF1/20W1%
82 21R2707
201 MF1/20W1%
39 21R2706
201 MF1/20W1%
39 21R2705
201 MF1/20W1%
68 21R2704
72 22 21 7
72 22 21 7
72 22 21 7
72 21 7
72 24 23 7
72 24 23 7
72 24 23 7
72 24 7
72 22 7
72 22 7
72 22 7
72 24 7
72 24 7
72 24 7
72 24 7
72 24 7
72 24 7
72 24 7
72 24 7
72 24 7
72 24 7
72 24 7
72 24 7
72 24 7
72 23 7
72 23 7
72 23 7
72 23 7
72 23 7
72 23 7
72 23 7
72 23 7
72 23 7
72 23 7
72 23 7
72 23 7
72 23 7
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2710
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2711
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2713
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2715
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2717
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2719
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2718
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2716
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2714
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2712
72 23 7
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2708
72 22 7
72 22 7
72 21 7
72 21 7
72 22 7
72 22 7
72 22 7
72 22 7
72 21 7
72 22 7
72 21 7
72 21 7
72 21 7
72 21 7
72 22 7
72 22 7
72 22 7
72 22 7
72 21 7
72 21 7
72 21 7
72 21 7
72 21 7
72 21 7
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2709
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2707
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2705
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2706
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2703
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2701
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2700
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2704
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C2702
69 69
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
PLACE_NEAR=
PU at PCH
PU at PCH
To SPI Flash
USE NEAREST GND BALL
(AC22) FOR THERM_D_N
10K PU ON CLOCKS PAGE
SNK0 AC Coupling
not used
SNK1 AC Coupling
26 OF 73
28 OF 500
1.0.0
051-02265
TBT_X_RTD3_USB_PWR_EN
TBT_X_HDMI_DDC_CLK =TBT_X_GPIO_8
=DP_X_SRC_AUX_N
DP_XA_AUXCH_C_N
TBT_XA_LSTX
DP_X_SNK0_ML_C_N<2>
DP_X_SNK0_ML_P<2>
DP_X_SNK1_AUXCH_C_P
DP_X_SNK1_ML_C_P<3>
DP_X_SNK1_ML_C_N<1>
DP_X_SNK0_ML_C_P<3>
DP_X_SNK0_ML_C_P<0>
DP_X_SNK0_ML_C_N<0>
PCIE_TBT_X_D2R_C_N<0>
TBT_WAKE_L
TBT_X_ROM_WP_L
DP_X_SNK1_AUXCH_N
DP_X_SNK1_AUXCH_P
DP_X_SNK1_ML_N<1>
DP_X_SNK0_ML_P<1>
PCIE_TBT_X_D2R_C_N<2>
=UPC_X_SPI_CS_L
USBC_X_RESET_L
TBT_X_CLKREQ_L
PCIE_TBT_X_R2D_N<2>
=DP_X_SRC_ML_N<1>
=DP_X_SRC_ML_N<2>
PCIE_CLK100M_TBT_X_P
DP_X_SNK0_ML_N<2>
DP_X_SNK0_ML_P<2>
PCIE_TBT_X_R2D_N<1>
PCIE_TBT_X_R2D_P<1>
TBT_X_THERM_D_P
TBT_XA_USB2_RBIAS
DP_XA_HPD
TBT_XA_LSRX
TBT_XB_USB2_RBIAS
DP_XB_HPD
TBT_XB_LSRX
USB_UPC_XA_P
USBC_XA_D2R_N<1>
DP_XA_AUXCH_C_P
USBC_XA_R2D_C_N<1>
USBC_XA_D2R_P<1>
USBC_XA_R2D_C_N<2>
USBC_XA_R2D_C_P<1>
USBC_XA_D2R_N<2>
USBC_XA_R2D_C_P<2>
JTAG_TBT_TDO
TBT_X_RBIAS
JTAG_TBT_TCK
JTAG_TBT_X_TMS
JTAG_TBT_TDI
DP_X_SNK_RBIAS
=DP_X_SNK1_DDC_DATA
=DP_X_SNK1_DDC_CLK
DP_X_SNK1_HPD
DP_X_SNK1_ML_N<3>
DP_X_SNK1_ML_P<3>
DP_X_SNK1_ML_N<2>
DP_X_SNK1_ML_P<1>
USB_UPC_XB_N
TBT_XB_LSTX
DP_XB_AUXCH_C_N
USB_UPC_XB_P
USBC_XB_D2R_N<1>
DP_XB_AUXCH_C_P
USBC_XB_D2R_P<1>
USBC_XB_R2D_C_N<1>
USBC_XB_R2D_C_N<2>
USBC_XB_R2D_C_P<1>
USBC_XB_D2R_N<2>
USBC_XB_R2D_C_P<2>
=UPC_X_SPI_CLK
USBC_XB_D2R_P<2>
=UPC_X_SPI_MISO
=UPC_X_SPI_MOSI
TBT_X_XTAL25M_OUT
TBT_X_XTAL25M_IN
TBT_X_TEST_EN
TBT_X_TEST_PWR_GOOD
TBT_X_RTD3_CIO_PWR_EN
PM_SLP_S3_L
=TBT_X_BATLOW_L
TBT_X_FORCE_PWR
I2C_TBT_XA_INT_L I2C_TBT_XB_INT_L
TBT_X_HDMI_DDC_DATA
=TBT_X_TMU_CLK_OUT
TBT_X_CIO_PLUG_EVENT_L
DP_X_SNK1_ML_N<0>
DP_X_SNK1_ML_P<0>
=DP_X_SNK0_DDC_CLK =DP_X_SNK0_DDC_DATA
DP_X_SNK0_AUXCH_N
DP_X_SNK0_ML_N<3>
DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_N<1>
DP_X_SNK0_ML_N<0>
TBT_X_ROM_WP_L
I2C_TBT_X_SCL
I2C_TBT_X_SDA
DP_X_SRC_RBIAS
DP_X_SRC_HPD
=DP_X_SRC_ML_N<3>
=DP_X_SRC_AUX_P
=DP_X_SRC_ML_P<2>
=DP_X_SRC_ML_N<0>
=DP_X_SRC_ML_P<1>
DP_X_SNK0_ML_P<0>
PCIE_TBT_X_R2D_N<3>
PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_D2R_C_N<1>
PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_D2R_C_P<3>
PCIE_TBT_X_R2D_P<0> PCIE_TBT_X_R2D_N<0>
PCIE_TBT_X_R2D_P<3>
DP_X_SNK0_HPD
DP_X_SNK0_AUXCH_P
DP_X_SNK1_ML_P<2>
PCIE_TBT_X_D2R_C_N<3>
=DP_X_SRC_ML_P<3>
TBT_X_PCIE_BIAS
PCIE_CLK100M_TBT_X_N
PCIE_TBT_X_R2D_P<2>
USBC_XA_D2R_P<2>
TBT_X_RSENSE
USB_UPC_XA_N
DP_X_SNK1_ML_P<0>
DP_X_SNK1_AUXCH_N
DP_X_SNK0_ML_C_N<1>
DP_X_SNK0_AUXCH_P
DP_X_SNK0_ML_N<3>
DP_X_SNK1_ML_P<3>
DP_X_SNK1_AUXCH_P
DP_X_SNK0_ML_N<2>
DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_P<0>
DP_X_SNK0_ML_N<1>
DP_X_SNK0_ML_P<1>
DP_X_SNK0_ML_N<0>
DP_X_SNK0_AUXCH_N
DP_X_SNK1_ML_N<1>
DP_X_SNK1_ML_P<2>
DP_X_SNK1_ML_N<2>
DP_X_SNK1_ML_N<3>
DP_X_SNK1_ML_C_N<2>
DP_X_SNK0_ML_C_N<3>
DP_X_SNK0_AUXCH_C_P
DP_X_SNK0_AUXCH_C_N
DP_X_SNK1_ML_C_N<0>
DP_X_SNK1_ML_C_P<1>
DP_X_SNK1_ML_C_P<2>
DP_X_SNK1_ML_C_P<0>
DP_X_SNK0_ML_C_P<2>
DP_X_SNK0_ML_C_P<1>
=PP3V3_TBT_X_SX
=PP3V3_TBT_X_SX
TBT_X_SPI_CLK
=PP3V3_TBT_X_FLASH
TBT_X_SPI_MOSI
TBT_XB_LSTX
TBT_XA_LSTX
DP_XA_AUXCH_N
DP_XB_AUXCH_N
DP_XB_AUXCH_P
DP_XB_HPD
TBT_XA_LSRX
DP_XA_AUXCH_P
TBT_XB_LSRX
DP_XA_HPD
TBT_X_SPI_MISO
TBT_X_ROM_HOLD_L
TBT_X_SPI_CS_L
DP_X_SNK1_ML_P<1>
DP_X_SNK1_ML_N<0>
DP_X_SNK1_AUXCH_C_N
DP_X_SNK1_ML_C_N<3>
=DP_X_SRC_ML_P<0>
PM_PLT_RST_TBT_X_L
USB-C HIGH SPEED 1
BOM_COST_GROUP=TBT
SYNC_MASTER=X362 SYNC_DATE=07/29/2015
72 32
72 32
72 32
72 32
0201
X5R-CERM
16V10%
0.1UF
21
C2835
0201
X5R-CERM
16V10%
0.1UF
21
C2820
0201
X5R-CERM
16V10%
0.1UF
21
C2821
0201
X5R-CERM
16V10%
0.1UF
21
C2822
0201
X5R-CERM
16V10%
0.1UF
21
C2823
0201
X5R-CERM
16V10%
0.1UF
21
C2825
0201
X5R-CERM
16V10%
0.1UF
21
C2824
0201
X5R-CERM
16V10%
0.1UF
21
C2826
0201
X5R-CERM
16V10%
0.1UF
21
C2827
0201
X5R-CERM
16V10%
0.1UF
21
C2829
0201
X5R-CERM
16V10%
0.1UF
21
C2828
0201
X5R-CERM
16V10%
0.1UF
21
C2831
0201
X5R-CERM
16V10%
0.1UF
21
C2830
0201
X5R-CERM
16V10%
0.1UF
21
C2832
0201
X5R-CERM
16V10%
0.1UF
21
C2833
0201
X5R-CERM
16V10%
0.1UF
21
C2834
0201
X5R-CERM
16V10%
0.1UF
21
C2836
0201
X5R-CERM
16V10%
0.1UF
21
C2838
0201
X5R-CERM
16V10%
0.1UF
21
C2837
0201
X5R-CERM
16V10%
0.1UF
21
C2839
28
28
28
28
28
28
28
28
28
28
28 19
28 19
28
28
28
28
28
28
28
28
201
MF
1/20W
5%
2.2K
2
1
R2837
201
MF
1/20W
5%
2.2K
2
1
R2836
201
MF
1/20W
5%
2.2K
2
1
R2835
201
MF
1/20W
5%
2.2K
2
1
R2834
FCBGA
TBT-AR-4C-CNTRL
CRITICAL
OMIT_TABLE
D23
D22
E18
V4
AB23
AC23
AB5
E1
AC1
W4
Y4
T4
J6
F4
H6
F1
D2
F2
H4
D4
E2
J4
L4
F23
F22
K23
K22
P23
P22
V23
V22
H23
H22
M23
M22
T23
T22
Y23
Y22
V19
T19
N16AC5
V18
F19
E19
D19
A9
B9
A11
B11
B7
A7
A13
B13
B4
B5
G2
Y16
W16
H19
E20
D20
A17
B17
A19
B19
A15
B15
B21
A21
A5
A4
M4
Y15
W15
D6
AB2
W18
W13
C22
C23
AA1
Y2
Y1
W2
W1
V2
V1
U2
U1
N15
L15
AC4
AB3
AC3
AB4
N6
J2
J1
L2
L1
N2
N1
R2
R1
G1
W19
Y19
Y18
AB21
AC21
AB19
AC19
AB17
AC17
AB15
AC15
Y6
N4
Y8
Y12
W12
AB13
AC13
AB11
AC11
AB9
AC9
AB7
AC7
AA2
R4
Y5
Y11
W11
A23
B23
U2800
28
28
28
28
28
28
28
28
28
30
30
0201
X5R-CERM
16V10%
GND_VOID=TRUE
0.1UF
21
C2813
0201
X5R-CERM
16V10%
GND_VOID=TRUE
0.1UF
21
C2812
29
29
0201
X5R-CERM
16V 10%
GND_VOID=TRUE
0.1UF
2 1
C2811
0201
X5R-CERM
16V 10%
GND_VOID=TRUE
0.1UF
2 1
C2810
201
MF
1/20W
5%
3.3K
2
1
R2890
201
MF
1/20W
5%
3.3K
2
1
R2892
201
MF
1/20W
5%
3.3K
2
1
R2893
201
MF
1/20W
5%
3.3K
2
1
R2891
28
28
28
28
29 28 26
201
MF
1/20W
5%
100
2
1
R2829
201
MF
1/20W
5%
100
2
1
R2825
0201
TF 1/20W
0.5%
PLACE_NEAR=U2800.J6:2MM
PLACE_NEAR=U2800.H6:2MM
4.75K
21
R2855
33 28 27
28
70
70
70
70
70
70
70
70
70
70
28
28
201MF1/20W5%
100K
21
R2872
201MF1/20W5%
100K
21
R2862
402-1
X5R
10V
10%
1UF
2
1
C2890
USON
W25Q80DVUXIE
8MBIT-3.0V
CRITICAL
OMIT_TABLE
3
8
9
7
4
2
5
1
6
U2890
28
28
28
28
28
28
28
28
30 29 28
72 66 60 59 39 14
30 29
28
28
28
28
41
28
19
15
15
28
72 28
72 28
72 28
29 26
28
28
28
28
29 26
201
MF
1/20W
5%
100K
2
1
R2831
72 31
28
28
28
28
201
MF
1/20W
1%
PLACE_NEAR=U2800.H19:2MM
499
2
1
R2854
201
MF
1/20W
1%
PLACE_NEAR=U2800.F19:2MM
499
2
1
R2853
72 31
72 32
201MF1/20W
1%
U2800.N6:3.8MM
14K
21
R2852
201
MF
1/20W
1%
PLACE_NEAR=U2800.N16:2MM
3.01K
21
R2851
28
28
72 31
201 MF
1/20W
1%
PLACE_NEAR=U2800.Y18:2MM
14K
2 1
R2850
72 31
201MF1/20W5%
1M
21
R2861
201MF1/20W5%
1M
21
R2860
201MF1/20W5%
1M
21
R2870
201MF1/20W5%
1M
21
R2871
72 31
46
72 31
72 31
201
MF
1/20W
5%
100K
2
1
R2827
72 32
30 26
72 31
201
MF
1/20W
5%
100K
2
1
R2830
19
72 32
30 26
30 26
72 32
26
26
26
26
26
26
28
26
26
26
26
26
26
28
28
28
72
26
26
26
26
26
26
26
26
28
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
33 26
33 26
28
28
28
30 26
29 26
30 26
29 26
30 26
29 28 26
28
28
26
26
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
SOURCE PORT 0
PCIE GEN3
DEBUG
PORT A
TBT PORTS
MISC
SINK PORT 1
PORT B POC GPIO LC GPIO
SINK PORT 0
SYM 1 OF 2
PA_USB2_D_N
RSENSE
PA_RX1_P
PCIE_RX2_P
GPIO_8
PCIE_REFCLK_100_IN_N
PCIE_RBIAS
DPSRC_ML0_P
DPSRC_ML3_P
PCIE_TX3_N
DPSNK1_ML1_N
DPSNK1_ML2_P
USB2_ATEST
DPSNK0_AUX_P
DPSNK0_HPD
PCIE_RX3_P
PCIE_RX0_N
PCIE_RX0_P
PCIE_TX3_P
PCIE_TX2_N
PCIE_TX2_P
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX0_N
PCIE_TX0_P
PCIE_RX3_N
DPSNK0_ML0_P
DPSRC_ML1_P
DPSRC_ML0_N
DPSRC_ML2_P
DPSRC_AUX_P
DPSRC_ML3_N
DPSRC_HPD
DPSRC_AUX_N
DPSRC_RBIAS
GPIO_0
GPIO_1
GPIO_2
DPSNK0_ML0_N
DPSNK0_ML1_P
DPSNK0_ML1_N
DPSNK0_ML3_P
DPSNK0_ML3_N
DPSNK0_AUX_N
DPSNK0_DDC_DATA
DPSNK0_DDC_CLK
DPSNK1_ML0_P
DPSNK1_ML0_N
GPIO_5
GPIO_3
GPIO_4
GPIO_6
GPIO_7
POC_GPIO_1
POC_GPIO_0
POC_GPIO_2
POC_GPIO_3
POC_GPIO_4
POC_GPIO_5
POC_GPIO_6
TEST_PWR_GOOD
TEST_EN
XTAL_25_IN
XTAL_25_OUT
EE_DI
EE_DO
PB_RX1_P
EE_CLK
PB_TX1_P
PB_RX1_N
PB_TX0_P
PB_TX1_N
PB_TX0_N
PB_RX0_P
PB_DPSRC_AUX_P
PB_RX0_N
PB_USB2_D_P
PB_DPSRC_AUX_N
PB_LSTX
PB_USB2_D_N
DPSNK1_ML1_P
DPSNK1_ML2_N
DPSNK1_ML3_P
DPSNK1_ML3_N
DPSNK1_AUX_P
DPSNK1_AUX_N
DPSNK1_HPD
DPSNK1_DDC_CLK
DPSNK1_DDC_DATA
DPSNK_RBIAS
TDI
TMS
TCK
RBIAS
TDO
PA_TX1_P
PA_RX1_N
PA_TX0_P
PA_TX1_N
PA_RX0_P
PA_TX0_N
PA_DPSRC_AUX_P
PA_RX0_N
PA_USB2_D_P
PA_DPSRC_AUX_N
PA_LSTX
PB_LSRX
PB_DPSRC_HPD
MONDC_SVR
PB_USB2_RBIAS
ATEST_P
ATEST_N
MONDC_DPSNK_0
MONDC_DPSNK_1
MONDC_DPSRC
PA_LSRX
PA_DPSRC_HPD
PA_USB2_RBIAS
THERMDA
THERMDA
PCIE_ATEST
FUSE_VQPS_64
TEST_EDM
MONDC_CIO_0
FUSE_VQPS_128
MONDC_CIO_1
PCIE_RX1_P
PCIE_RX1_N
DPSNK0_ML2_P
DPSNK0_ML2_N
PCIE_REFCLK_100_IN_P
DPSRC_ML2_N
DPSRC_ML1_N
PCIE_RX2_N
PERST*
PCIE_CLKREQ*
RESET*
EE_CS*
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
BI
BI
BI
BI
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
VCC
DI(IO0)
DO(IO1)
CS*
HOLD*(IO3)
WP*(IO2)
CLK
GND EPAD
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
IN
IN
IN
IN
NC
NC
BI
BI
IN
IN
OUT
NC
NC
IN
BI
BI
BI
BI
IN
IN
BI
BI
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
IN
OUT
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
SOURCED BY INTERNAL SWITCH
PRECHARGE RAIL AFTER SX RAIL TURNS ON
BUT RESET IS STILL ASSERTED.
2x 10uF outside BGA area
INTERNAL SWITCH
INTERNAL SWITCH
SOURCED BY
SOURCED BY
ISOLATE GND OF SVR_IND CAPS
INTERNAL SWITCHING VR OUTPUT
SOURCED BY INTERNAL SWITCH
CONTROLLER (UPC)
AND GND OF VCC3P3_SVR CAPS
(SEE INTEL LAYOUT GUIDELINES)
SOURCED BY INTERNAL SWITCH
SOURCED BY INTERNAL SWITCH
FROM USB-C PORT
FROM SYSTEM GND IN LAYOUT
SOURCED BY INTERNAL SWITCH
WORKAROUND TO LIMIT INRUSH
CURRENT AT LVR TURN ON.
SOURCED BY INTERNAL SWITCH
27 OF 73
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.2000
VOLTAGE=0.9V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.2000
VOLTAGE=0.9V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=0.9V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1800
VOLTAGE=0.9V
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=0V
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.1800 MIN_NECK_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1800
VOLTAGE=0.9V
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.2000
VOLTAGE=0.9V
29 OF 500
1.0.0
051-02265
PP0V9_TBT_X_USB
PP3V3_TBT_X_ANA_USB2
PP3V3_TBT_X_SX
WA_P0V9TBTXLVR_D
PP3V3_TBT_X_SX
USBC_X_RESET_L
PP0V9_TBT_X_LVR
WA_P0V9TBTXLVR_Q
PP3V3_TBT_X_SX
PP0V9_TBT_X_CIO
PP3V3_TBT_X_ANA_PCIE
PP0V9_TBT_X_LVR
PP0V9_TBT_X_SVR
VR0V9_IND_TBT_X
TBT_X_THERM_D_N
PP3V3_TBT_X_F
=PP3V3_TBT_X_S0
P0V9_TBT_X_SVR_AGND
PP3V3_TBT_X_LC
PP0V9_TBT_X_DP
PP0V9_TBT_X_PCIE
SYNC_DATE=07/29/2015SYNC_MASTER=X362
BOM_COST_GROUP=TBT
USB-C HIGH SPEED 2
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2936
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2935
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2934
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2947
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2933
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2932
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2931
46
SM
PLACE_NEAR=U2800.AC22:2MM
NO_XNET_CONNECTION=1
21
XW2900
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2921
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2978
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2977
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2976
0402
CERM
6.3V
20%
BYPASS=U2800.A2:A1:3MM
10UF
CRITICAL
2
1
C2975
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2991
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2990
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2920
FCBGA
TBT-AR-4C-CNTRL
CRITICAL
OMIT_TABLE
AC22
AC20
AC18
AC16
AC14
AC12
AC10
AC8
AC6
AB22
AB20
AB18
AB16
AB14
AB12
AB10
AB8
AB6
AA23
AA22
Y20
Y13
Y9
W23
W22
W20
W9
W8
W6
W5
V20
V16
V15
V9
V8
V6
V5
U22
U23
T20
T5
T2
T1
R23
R22
R20
R19
R18
R5
P2
P1
N23
N22
N20
N5
M20
M19
M5
M2
M1
L23
L22
L20
L5
K2
K1
J23
J22
J18
J20
J19
J5
H20
H16
H15
H13
H12
H2
H1
G23
G22
F16
F20
F9
E23
E22
E16
E15
E11
E9
E8
D18
D16
D15
D13
D12
D11
D9
D8
B22
B20
B18
B16
B14
B12
B10
B8
B6
A22
A20
A18
A16
A14
A12
A10
A8
A6
M11
AC2
AB1
T18
T16
T15
T13
T9
T8
T6
N13
N12
N11
N9
N8
M12
L13
J15
J13
J12
J8
H8
H5
F6
F5
E6
E5
E4
D5
H9
F8
B3
A3
A2
R13
R6
J16
L16
R16
R15
J9
F15
F13
F12
F11
E13
E12
M9
L9
M16
M15
M13
H11
J11
H18
F18
T12
T11
M8
L12
L11
L8
R12
R11
R9
R8
N18
M18
L18
N19
L19
M6
L6
V13
V12
V11
B2
B1
A1
D1
C2
C1
U2800
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2914
0201
X5R-CERM
6.3V
20%
2.2UF
2
1
C2981
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2930
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2910
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2911
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2912
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2913
201
MF
1/20W
5%
1K
TBT_LVR_WA
2
1
R2988
DFN1006
1N4448HLP-7
TBT_LVR_WA
K A
D2988
0201
X5R-CERM
10V
10%
0.1UF
TBT_LVR_WA
2
1
C2988
SOT891
74AUP1G07GF
TBT_LVR_WA
4
6
5
1
3
2
U2988
DFN1006H4-3
DMP210DUFB4
TBT_LVR_WA
2
1
3
Q2988
1210
0.68UH-20%-6.1A-0.020OHM
CRITICAL
21
L2950
0201
CERM
25V
5%
12PF
2
1
C2917
0603
CER-X5R
6.3V
20%
47UF
CRITICAL
2
1
C2995
0603
CER-X5R
6.3V
20%
47UF
CRITICAL
2
1
C2994
0603
CER-X5R
6.3V
20%
47UF
CRITICAL
2
1
C2952
0603
CER-X5R
6.3V
20%
47UF
CRITICAL
2
1
C2951
0603
CER-X5R
6.3V
20%
47UF
CRITICAL
2
1
C2950
SM
PLACE_NEAR=U2800.A1:5MM
NO_XNET_CONNECTION=1
21
XW2901
0603
1.0UH-20%-2.1A-0.128OHM
CRITICAL
21
L2990
0201
X5R-CERM
10V
10%
0.1UF
2
1
C2980
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2916
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2915
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2954
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C2955
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2992
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2945
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2993
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2984
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2985
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2967
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2964
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2965
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2966
0201-1
X5R
6.3V
20%
1.0UF
2
1
C2946
28
33 28 27
33 28 27
33 28 26
27
33 28 27
28
27
63
72
69 28
28
63 28
28
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
GND
VCC
SYM 2 OF 2
VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC3P3_SX
VCC0P9_ANA_DPSRC
VCC0P9_ANA_DPSRC
VCC0P9_ANA_DPSNK
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR
VCC0P9_SVR
VCC3P3_SVR
VSS_ANAVSS_ANA
VCC0P9_DP
VCC0P9_ANA_DPSNK
VCC3P3_LC
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_USB
VCC0P9_USB
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_1
VCC0P9_PCIE
VCC0P9_PCIE
VCC0P9_ANA_DPSNK
VCC0P9_LVR
VCC0P9_LVR
VCC3P3_SVR
VCC0P9_SVR_ANA
VCC3P3A
VSS_ANA
VSS_ANA
VSS_ANA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC3P3_S0
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
SVR_VSS
SVR_VSS
SVR_VSS
VSS_ANA
VSS_ANA
VSS_ANA
SVR_IND
SVR_IND
VCC0P9_SVR_SENSE
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC3P3_ANA_PCIE
VCC3P3_ANA_USB2
VCC0P9_ANA_PCIE_1
VCC0P9_PCIE
VCC0P9_DP
VCC0P9_DP
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
SVR_IND
VCC3P3_SVR
VCC0P9_LVR
VCC0P9_LVR_SENSE
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
GND
VCC
NCNC
YA
NC NC
D
S
G
合肥怡飞苹果维修qq:82669515 qq群: 241000
XPD JTAG ISOLATION
TBT - MASTER
CONNECT G1/G2 TO CC1/CC2 TO RECEIVE POWER UNDER DB CASE
ACE BUSPOWERZ STRAPPING
ACE DEBUG CONN
CONNECT G1/G2 TO GND TO NOT RECEIVE POWER UNDER DB CASE
ACE RPD STRAPPING
DP / USB SOURCE ALIASES
MISC ALIASES
UPC XA - U3100
(WRITE: 0X70 READ: 0X71)
PD WHEN NOT USED
VBUS TO SYS UNDER DB CASE
PU BUSPOWERZ TO LDO_3V3 TO NOT PASS
516S00115
VBUS TO SYS UNDER DB CASE
USES EXT POWER PATH
VBUS TO SYS UNDER DB CASE
DESIGN: X502/MLB_CATZ
D2R
R2D
USES INT POWER PATH
GND BUSPOWERZ TO PASS
516S00115
PU BUSPOWERZ TO 1V8D TO PASS
UPC XB - U3200
ALPINE RIDGE - U2800 (WRITE: 0X7E READ: 0X7F)
LAST CHANGE: Fri Aug 5 13:34:33 2016
RIDGE DEBUG CONN
POWER ALIASES
LOCAL BULK CAP
RIDGE AC COUPLING
28 OF 73
051-02265
1.0.0
30 OF 500
VOLTAGE=0V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000
PP3V3_G3H
PP3V3_UPC_XA_LDO
MAKE_BASE=TRUE
PCIE_TBT_X_R2D_N<2>
PCIE_TBT_X_R2D_P<2>
MAKE_BASE=TRUE
PP3V3_G3H_UPC_XB
=PP3V3_G3H_UPC_XA
MAKE_BASE=TRUE
PP3V3_G3H_UPC_XA
=PP3V3_TBT_X_FLASH =PP3V3R1V8_UPC_XB
PP3V3_UPC_XB_LDO
MAKE_BASE=TRUE
=PPHV_INT_G3H
=PP3V3_TBT_X_S0
=USBC_XA_RESET_L
JTAG_TBT_TDO
=USBC_TMS_T_SWD_DATA_X
=USBC_TMS_X_SWD_CLK_X
=TBT_X_BATLOW_L
TBT_X_PLUG_EVENT_L TBT_X_CIO_PLUG_EVENT_L
MAKE_BASE=TRUE
TBT_X_USB_PWR_EN
MAKE_BASE=TRUE
TBT_X_RTD3_CIO_PWR_EN
MAKE_BASE=TRUE
TBT_X_CIO_PWR_EN
USBC_X_POC_RESET
MAKE_BASE=TRUE
UPC_X_SPI_MISO
MAKE_BASE=TRUE
UPC_X_SPI_CS_L
=UPC_X_SPI_CLK
USBC_XB_RPD_G2
PCIE_TBT_X_R2D_C_P<1>
UPC_XA_SPI_CLK
PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_D2R_N<2>
PCIE_TBT_X_D2R_C_N<3>
PCIE_TBT_X_D2R_C_N<2>
PCIE_TBT_X_D2R_C_N<1>
TBT_X_SPI_CLK
UPC_XB_SPI_CS_L
TBT_X_SPI_CLK_DBG
=I2C_UPC_XB_SCL1
=I2C_UPC_XB_SDA1
=I2C_UPC_XA_SCL1
UPC_XB_SPI_MISO
TBT_X_SPI_MOSI
UPC_XA_SPI_MISO
=UPC_X_SPI_CS_L
=UPC_X_SPI_CLK
UPC_XB_RESET
=I2C_UPC_XA_SDA1
UPC_XA_SPI_CS_L
=I2C_UPC_XB_INT1_L
UPC_XB_SPI_MOSI
I2C_TBT_XB_INT_L
MAKE_BASE=TRUE
I2C_TBT_XA_INT_L
MAKE_BASE=TRUE
PCIE_TBT_X_R2D_C_P<0>
PCIE_TBT_X_D2R_P<0>
=UPC_X_SPI_MISO
TSP_UPC_XB_SWD_CLK
MAKE_BASE=TRUE
PCIE_TBT_X_R2D_N<0>
PCIE_TBT_X_D2R_N<3>
PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_R2D_C_P<2>
PCIE_TBT_X_R2D_C_N<3>
I2C_TBT_X_SCL
I2C_UPC_XA_DBG_CTL_SCL
PP3V3_TBT_X_SX
I2C_TBT_X_SDA
I2C_TBT_XA_INT_L
PP0V9_TBT_X_CIO
PP0V9_TBT_X_USB
PP0V9_TBT_X_PCIE
ARKANOID_P7
PCIE_TBT_X_R2D_C_N<2>
PCIE_TBT_X_D2R_N<0>PCIE_TBT_X_D2R_C_N<0>
PCIE_TBT_X_R2D_C_P<3>
P0V9_TBT_X_SVR_AGNDPCIE_TBT_X_D2R_P<3>PCIE_TBT_X_D2R_C_P<3>
UPC_XB_SPI_CLK
UPC_XA_SPI_MOSI
PP20V_USBC_XB_VBUS_F
PP20V_USBC_XA_VBUS_F=PP20V_USBC_XA_VBUS
USBC_XB_CC2
UPC_XA_BUSPOWERZ
UPC_XB_BUSPOWERZ
TBT_X_PCI_RESET_L
USBC_X_RESET_L
TBT_X_SPI_CLK_DBG
TBT_X_CIO_PLUG_EVENT_L DP_X_SNK0_HPD ARKANOID_P5
TBT_POC_RESET PP3V3_TBT_X_LC
I2C_TBT_XB_INT_L
USBC_XA_RPD_G2
PCIE_TBT_X_R2D_N<3>
PCIE_TBT_X_R2D_P<3>
PCIE_TBT_X_R2D_N<1>
USBC_XA_CC2
=PP20V_USBC_XA_VBUS
JTAG_ISP_TCK
JTAG_ISP_TDI
=DP_X_SNK0_DDC_DATA
=DP_X_SNK0_DDC_CLK
=DP_X_SNK1_DDC_CLK
=DP_X_SNK1_DDC_DATA
UPC_XA_HPD_RX
TBT_X_HDMI_DDC_CLK
JTAG_TBT_TCK
JTAG_TBT_TDI
UPC_XA_DBG4
TBT_X_HDMI_DDC_DATA
MAKE_BASE=TRUE
DP_X_SNK0_DDC_DATA
MAKE_BASE=TRUE
DP_X_SNK0_DDC_CLK
MAKE_BASE=TRUE
DP_X_SNK1_DDC_CLK
MAKE_BASE=TRUE
DP_X_SNK1_DDC_DATA
MAKE_BASE=TRUE
PD_UPC_XA_GPIO5
UPC_XB_HPD_RX
UPC_XB_5V_EN
UPC_XA_5V_EN
=TBT_X_TMU_CLK_OUT
=TBT_X_GPIO_8
MAKE_BASE=TRUE
PD_UPC_XB_GPIO5
MAKE_BASE=TRUE
PD_UPC_XA_GPIO6
MAKE_BASE=TRUE
PD_UPC_XB_GPIO6
MAKE_BASE=TRUE
PD_TBT_X_TMU_CLK_OUT
MAKE_BASE=TRUE
PD_TBT_X_GPIO_8
DP_X_SRC_HPD
PP3V3_TBT_X_LC
=PP3V3R1V8_UPC_XA
=I2C_UPC_XA_INT1_L
MAKE_BASE=TRUE
PP20V_USBC_XB_VBUS
=UPC_XA_I2C_STRAP
=PP20V_USBC_XB_VBUS
MAKE_BASE=TRUE
JTAG_ISP_TDO
TBT_X_RTD3_USB_PWR_EN
USBC_XB_RPD_G1
PCIE_TBT_X_R2D_P<1>
MAKE_BASE=TRUE
DP_X_SNK1_AUXCH_C_P
MAKE_BASE=TRUE
DP_X_SNK1_ML_C_N<3..0>
=USB_UPC_XA_P =USB_UPC_XA_N
PP3V3_G3H
=PP5V_USBC
=UPC_XB_I2C_STRAP
DP_DDI1_ML_C_N<3..0>
PCIE_TBT_X_R2D_C_N<1>
=PP3V3_G3H_UPC_XB
=USB_UPC_XB_N
USB_EXTB_OC_L
DP_DDI2_ML_C_N<3..0>
MAKE_BASE=TRUE
DP_X_SNK0_AUXCH_C_PDP_DDI2_AUXCH_C_P
MAKE_BASE=TRUE
DP_X_SNK0_ML_C_P<3..0>
MAKE_BASE=TRUE
DP_X_SNK0_ML_C_N<3..0>
MAKE_BASE=TRUE
DP_X_SNK1_HPD
MAKE_BASE=TRUE
TBT_POC_RESET
=UPC_X_SPI_MISO
=UPC_X_SPI_CS_L
MAKE_BASE=TRUE
DP_X_SNK1_AUXCH_C_N
DP_DDI2_ML_C_P<3..0>
MAKE_BASE=TRUE
USB_UPC_PCH_XA_P
MAKE_BASE=TRUE
DP_X_SNK0_HPDDP_DDPC_HPD
DP_DDPB_HPD
DP_DDI1_AUXCH_C_N
MAKE_BASE=TRUE
DP_X_SNK0_AUXCH_C_N
USB_UPC_XB_N
UPC_XB_FAULT_L
USB_UPC_XB_P
NC_USB2_08N
USB_EXTB_P
USB_UPC_PCH_XA_N
MAKE_BASE=TRUE
USB_EXTB_N
USB_UPC_XA_P
MAKE_BASE=TRUE
DP_X_SNK1_ML_C_P<3..0>DP_DDI1_ML_C_P<3..0>
NC_USB2_08P
DP_DDI1_AUXCH_C_P
DP_DDI2_AUXCH_C_N
=USB_UPC_XB_P
USB_EXTA_OC_L
MAKE_BASE=TRUE
USB_UPC_PCH_XB_N
MAKE_BASE=TRUE
USB_UPC_PCH_XB_P
UPC_XA_FAULT_L
USB_UPC_XA_N
=UPC_X_SPI_MOSI
MAKE_BASE=TRUE
PU_USBC_TMS_T_SWD_DATA_X
JTAG_TBT_X_TMS
MAKE_BASE=TRUE
PM_BATLOW_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
UPC_X_SPI_MOSI
MAKE_BASE=TRUE
UPC_X_SPI_CLK
MAKE_BASE=TRUE
PP3V3_TBT_X_S0
MAKE_BASE=TRUE
PP20V_USBC_XA_VBUS
USB3_EXTA_R2D_C_P USB3_EXTA_R2D_P
USB3_EXTA_R2D_C_N USB3_EXTA_R2D_N
PCIE_TBT_X_R2D_C_N<0>
ARKANOID_P7
=PP20V_USBC_XB_VBUS
USBC_XA_RPD_G1
UPC_XA_UART_TX
DP_X_SNK1_HPD
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
DP_XA_HPD
SMC_USBC_INT_L
=I2C_UPC_XA_SDA2
=I2C_UPC_XA_SCL2
ARKANOID_P5
UPC_XA_UART_RX
I2C_UPC_XA_DBG_CTL_SDA
PCIE_TBT_X_R2D_P<0>
USBC_XB_CC1
USBC_XA_CC1
PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_P<2>
PCIE_TBT_X_D2R_P<1>
UPC_XA_DBG3
MAKE_BASE=TRUE
TP_USBC_XA_RESET_L
I2C_TBT_X_SDA
MAKE_BASE=TRUE
I2C_TBT_X_SCL
MAKE_BASE=TRUE
UPC_XA_RESET
=USB_UPC_XA_F_P
=USB_UPC_XA_F_N
MAKE_BASE=TRUE
USB_UPC_XA_F_P
MAKE_BASE=TRUE
USB_UPC_XA_F_N
USBC_XA_USB_DBG_TOP_N
USBC_XA_USB_DBG_BOT_P USBC_XA_USB_DBG_BOT_N
USBC_XA_USB_TOP_N
MAKE_BASE=TRUE
USBC_XA_USB_BOT_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_DEBUGPRT_TX_L
MAKE_BASE=TRUE
SMC_DEBUGPRT_RX_L
UPC_XB_DBG3 UPC_XB_DBG4
UPC_XB_DBG2
UPC_XB_DBG1 SSD_JTAG_TCK
MAKE_BASE=TRUE
SSD_JTAG_TMS
MAKE_BASE=TRUE
SMC_TMS
MAKE_BASE=TRUE
SMC_TCK
MAKE_BASE=TRUE
UPC_XA_DBG1 UPC_XA_DBG2
USBC_XA_USB_TOP_P
MAKE_BASE=TRUE
USBC_XA_USB_DBG_TOP_P
TBT_X_XTAL25M_OUT
USB3_EXTA_D2R_P
USB3_EXTA_D2R_N
USBC_XA_USB_BOT_P
MAKE_BASE=TRUE
=USB_UPC_XA_P
=USB_UPC_XA_N
TP_UPC_XB_SWD_CLK
TBT_X_XTAL25M_IN
=UPC_X_SPI_MOSI
TBT_X_SPI_MISO
TBT_X_SPI_CS_L
MAKE_BASE=TRUE
USB-C SUPPORT
BOM_COST_GROUP=USB-C
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
29
29 72 47 40 39
72 47 40 39
72 29
72 29
SM-TPP3
1
TP3094
SM-TPP3
1
TP3093
SM-TPP3
1
TP3092
SM-TPP3
1
TP3091
0201MF1/20W5%
0
21
R3014
0201MF1/20W5%
0
21
R3015
0201MF1/20W5%
0
21
R3013
0201MF1/20W5%
0
21
R3012
26
26
30
15
15
0201MF1/20W5%
0
21
R3018
17
30
30
28
28
17
0201MF1/20W5%
0
21
R3008
15
15
26
26
SM-TPP3
1
TP3090
30
30
67
67
0201MF1/20W5%
0
ARKANOID:MOJO
21
R3083
0201MF1/20W5%
0
ARKANOID:HPD
21
R3082
0201MF1/20W5%
0
ARKANOID:MOJO
21
R3081
0201MF1/20W5%
0
ARKANOID:HPD
21
R3080
72 40 39 28
72 40 39 28
29 26
28 26
PLACE_NEAR=U2800.A1:5MM
SM
NO_XNET_CONNECTION=1
21
XW3001
30 72 40 39 28
30 72 40 39 28
201MF1/20W5%
1M
21
R3020
201MF1/20W5%
100K
21
R3035
100K
5% 201MF1/20W
21
R3036
201
MF
1/20W
5%
1M
NOSTUFF
2
1
R3006
0201C0G
25V5%
20PF
21
C3003
C0G
25V5%
20PF
0201
21
C3002
25MHZ-25PPM-20PF-50OHM
2.00X1.60-SM
CRITICAL
31
42
Y3000
201MF1/20W5%
100K
21
R3050
201MF1/20W5%
100K
21
R3049
26
26
201MF1/20W5%
100K
21
R3074
201MF1/20W5%
100K
21
R3073
201MF1/20W5%
100K
21
R3072
201MF1/20W5%
100K
21
R3071
201MF1/20W5%
100K
21
R3066
26
0201MF1/20W5%
0
21
R3019
201MF1/20W5%
100K
21
R3070
201MF1/20W5%
100K
21
R3069
201MF1/20W5%
100K
21
R3067
26
26
26
0201MF1/20W5%
0
21
R3034
0201MF1/20W5%
0
21
R3033
201MF1/20W5%
100
21
R3098
15
201MF1/20W5%
21
R3097
201MF1/20W5%
15
21
R3096
201MF1/20W5%
15
21
R3095
201MF1/20W5%
15
21
R3094
201MF1/20W5%
15
21
R3093
201MF1/20W5%
15
21
R3092
MF 2011/20W5%
15
21
R3091
201MF1/20W5%
15
21
R3090
42 29
42 29
42 39
30 29
28 26
505070-1220 UPC_DBG_HDR
M-ST-SM
16
15
1413
1211
109
87
65
43
21
J3098
30 29
29
28 26
28 26
28 26
29
29
15
15
0201 16V10%
0.1UF
X5R-CERM
21
C3021
0.1UF
10% 16VX5R-CERM0201
21
C3020
PLACE_NEAR=U3100.K5:5MM
PLACE_NEAR=U3100.L5:5MM
EXCX4CE
90-OHM-0.1A
CRITICAL
4
32
1
L3000
72 29
72 29
31
31
31
31
15
15
0201MF1/20W5%
0
21
R3024
0201MF1/20W5%
0
21
R3011
0201MF1/20W5%
0
21
R3022
26
26
26
26
15
15
15
15
15
15
15
15
26
26
26
26
26
26
26
26
0201 X5R 6.3V20%
0.22UF
TBT_PCIE_4LANES
21C3054
0201 X5R 6.3V20%
0.22UF
TBT_PCIE_4LANES
21C3057
0201 6.3V20%
0.22UF
TBT_PCIE_4LANES
X5R
21C3056
0201 X5R 6.3V20%
0.22UF
TBT_PCIE_4LANES
21C3055
X5R 6.3V20%
0.22UF
0201
21C3053
X5R 6.3V20%
0.22UF
0201
21C3052
0201 X5R 6.3V20%
0.22UF
21C3051
0201 X5R 6.3V20%
0.22UF
21C3050
0201 X5R 6.3V20%
0.22UF
TBT_PCIE_4LANES
21C3047
0201 X5R 6.3V20%
0.22UF
TBT_PCIE_4LANES
21C3046
0201 X5R 6.3V20%
0.22UF
TBT_PCIE_4LANES
21C3045
0201 X5R 6.3V20%
0.22UF
TBT_PCIE_4LANES
21C3044
0201 X5R 6.3V20%
0.22UF
21C3043
0201 X5R 6.3V20%
0.22UF
21C3042
0201 X5R 6.3V20%
0.22UF
21C3041
0201 X5R 6.3V20%
0.22UF
21C3040
26
26
26
26
15
15
15
15
15
15
19 15
19 15
28 16
19 16 28 26
28 26
63 28 27
33 27 26
M-ST-SM
505070-1220 UPC_DBG_HDR
16
15
1413
1211
109
87
65
43
21
J3099
0201MF1/20W5%
0
21
R3001
0201MF1/20W5%
0
21
R3000
0603
6AMP-32V-0.0095OHM
CRITICAL
21
F3010
0603
6AMP-32V-0.0095OHM
CRITICAL
21
F3000
201MF1/20W5%
100K
21
R3042
29
201MF1/20W5%
100K
21
R3040
29
201MF1/20W5%
100K
21
R3041
30
201MF1/20W5%
100K
21
R3043
30
5
5
26
26
26 19
26 19 5
5
5
5
5
5
26
26
26
26
5
5 28 26
28 26
29
POLY-TANT
6.3V
20%
220UF-35MOHM
CRITICAL
CASE-B2-SM1
2
1
C3000
0201MF1/20W5%
0
21
R3017
0201MF1/20W5%
0
21
R3026
72 69
68 60 53 52 51 47 42 41 28 19
69 29
29
26
30
69 63 30
30 29
69 27
29
26
13
13
26
16
28 26
13
30 29 26
13
30 29
28 26
30
29
26
30
28
30
30
29
30
26
29
28 26
28 26
30
29
29
30
30
28 26
28 26
28 26
29
33 27
27
27
27 28
27
30
29
30
29 29 28
32 30
29
30
28
28
29 31 29
29 28
19 17
19 17
26
72 26
72 26
29
26
26
63 28 27
29
29
72 32
29
30 28
5
30 29 26
30
72 69
68 60 53 52 51 47 42 41 28 19
69
30
30
28 16
28 26
28 26
28 26
72 26
39 14
63
72 31
28
30 28
29
28
32 30
31 29
29
28 26
28 26
29
26
28
28
30
26
28 26
26
26
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
IN IN
OUT
BI
BI
TP
TP
TP
TP
BI
BI
IN
BI
BI
OUT
BI
BI
BI
BI
OUT
BI
BI
BI
BI
TP
IN
OUT
IN
OUT
BI
BI
BI
BI
OUT OUT
IN IN
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
IN
OUT
OUT
OUT
BI
BI
OUT
OUT
OUT
BI
BI
SYM_VER-1
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
OUTOUT
BI
IN
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BIBI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT IN
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
PRIMARY ACE USB-C PORT CONTROLLER (UPC)
PRIMARY ONLY
PRIMARY ONLY
PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES
PRESENT FOR GPIO0, GPIO1
USE GPIO3 FOR POWER_GATE_EN
FRONT PORT:
NEED 0.1%
CONNECT UPC SPI TO ROM
REAR PORT:
GROUND UPC SPI
CMC
Add on support page
FUSE
ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR
for layout.
NC or GND to dissipate heat
PIN D6 IS UNDOCUMENTED RESET CAN GROUND PIN D6 IN PRODUCTION
CAP FOR PP_5V0 ON VR PAGE
TO SMC
Otherwise PU to PP3V3_UPC_XA_LDO
PU to PP3V3_S4 if convenient
MAX 100uF TOTAL ON RAIL
PRIMARY ONLY
GND I2C_ADDR
USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT
Add CMC on support page
for ridgeless design
PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
TESTPOINTS MUST BE
VOUT_3V3 FOR RIDGE,
(EVEN IN PRODUCTION)
OR FLOAT IF UNUSED
ON BANSURI DESIGNS
29 OF 73
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.0180
MIN_NECK_WIDTH=0.2000
VOLTAGE=20V
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.1V
31 OF 500
1.0.0
051-02265
PP3V3_UPC_XA_LDO
PP20V_USBC_XA_VBUS_F
=PP20V_USBC_XA_VBUS
=PP5V_XA_USBC
USBC_X_POC_RESET
UPC_XA_GATE2
=PPHV_EXT_G3H
PP1V8_UPC_XA_LDOD
=PP3V3R1V8_UPC_XA
UPC_XA_GATE1
DP_XA_HPD
TBT_X_RTD3_USB_PWR_EN
TBT_X_RTD3_CIO_PWR_EN
UPC_XA_UART_RX
=UPC_XA_I2C_STRAP
UPC_XA_5V_EN
DP_XA_AUXCH_N
PP1V8_UPC_XA_LDOA
=I2C_UPC_XA_INT1_L
TP_UPC_XA_SWD_CLK
TP_UPC_XA_SWD_DATA
=PP3V3_G3H_UPC_XA
UPC_XA_SPI_CS_L
UPC_XA_SPI_MISO
I2C_UPC_XA_DBG_CTL_SDA
=I2C_UPC_XA_SDA1
I2C_UPC_XA_DBG_CTL_SDA
USBC_XA_CC2
USBC_XA_CC1
PP1V1_UPC_XA_LDO_BMC
=PP3V3_UPC_XA_AUX
UPC_XA_FAULT_L
=I2C_UPC_XA_INT2_L
UPC_XA_I2C_ADDR
UPC_XA_DBG1
UPC_XA_DBG2
=I2C_UPC_XA_SCL1
I2C_UPC_XA_DBG_CTL_SCL
UPC_XA_HPD_RX
=PPHV_INT_G3H
UPC_XA_RESET
USBC_XA_SBU2
USBC_XA_SBU1
USBC_XA_USB_BOT_P
USBC_XA_USB_TOP_N
USBC_XA_USB_TOP_P
USBC_XA_RPD_G2
USBC_XA_RPD_G1
=USBC_XA_RESET_L
USBC_XA_USB_BOT_N
TP_UPC_XA_DBG_UART_TX
UPC_XA_UART_RX
TBT_XA_LSRX
UPC_XA_UART_TX
TBT_XA_LSTX
=USB_UPC_XA_F_P
UPC_XA_DBG4
I2C_UPC_XA_DBG_CTL_SCL
UPC_XA_SS
UPC_XA_SPI_CLK UPC_XA_SPI_MOSI
UPC_XA_DBG3
UPC_XA_BUSPOWERZ
TP_UPC_XA_DBG_UART_RX
=PP3V3_UPC_XA_SX
DP_XA_AUXCH_P
=USB_UPC_XA_F_N
=UPC_WAKE_L
=I2C_UPC_XA_SCL2
=I2C_UPC_XA_SDA2
UPC_XA_R_OSC
SYNC_DATE=06/17/2015SYNC_MASTER=E85-REF
BOM_COST_GROUP=USB-C
USB-C PORT CONTROLLER A
CAP,CER,X5R,0.22UF,20%,6.3V,0201 C3109,C32092132S0304 ACE_SS_CAP:A_B
CAP,CER,X5R,0.47UF,10%,6.3V,0201 C3109,C32092132S0390 ACE_SS_CAP:C0
26
26
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C3108
0201
X5R-CERM
6.3V
20%
2.2UF
2
1
C3104
0402
X5R
35V
10%
1UF
2
1
C3101
0201
CER-X5R
25V
10%
4700PF
NOSTUFF
2
1
C3120
0201
CER-X5R
25V
10%
4700PF
NOSTUFF
2
1
C3121
201MF1/20W5%
1M
21
R3108
201MF1/20W5%
1M
21
R3109
28
28
30 28 26
30 28 26
28
28
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C3106
0201
TF-LF
1/20W
0.1%
15K
CRITICAL
2
1
R3103
0201
X5R
6.3V
20%
0.22UF
OMIT_TABLE
2
1
C3109
0201
C0G
50V
2%
220PF
2
1
C3113
0201
C0G
50V
2%
220PF
2
1
C3114
BGA
CD3215A10
CRITICAL OMIT_TABLE
GROUND
H2
H1
B1
K11
J11
J10
H11
L5 K5
E2
F2
F4
G4
H7
B3
B4
A4
A3
B10
A10
K10
K9
F11
G2
B7
A8
A7
A6
H10
D11
C11
B11
A11
L11
E11
L4
K4
E1
G1
A2
K1
A5
D1
B5
D2
B6
C1
F1
A9
B9
H6
D7
G10
E10
C10
G11
D10
C2
B2
G7
G6
F8
F7
F6
E8
D8
B8
L1
H8
G8
H5
H4
G5
F5
E7
E6
E5
D6
A1
D5
E4
K3
L3
K2
L2
K6
L6
K7
L7
L8
K8
L10
L9
F10
J1
J2
U3100
0201
MF
1/20W
5%
0
2
1
R3102
201
MF
1/20W
5%
100K
2
1
R3111
201
MF
1/20W
5%
100K
2
1
R3110
201MF1/20W5%
1M
21
R3105
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C3100
28
28
28
0201-1
X5R
6.3V
20%
1.0UF
2
1
C3105
31 28
31 28
28
28
72 28
72 28
72 28
72 28
31
31
28
28
30 28
28
28
28
28
42 28
42 28
42
28
28
41 30
28
28 26
28
30 28
PWR-CLIP-33
FDPC4044
CRITICAL
5
8
4
1
3
2
Q3100
26
26
69 28
28
28
69
69 30
28
30 29 28
28
70
70
28
29 28
29 28
69
29 28
28
30 28
28
72
30 29 28
29 28
72
33
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
IN
NC
BI
BI
BI
BI
BI
BI
HV FET/SENSE
PORT MUX DIGITAL CORE I/O AND CONTROL
TYPE-C
HV_GATE2
PP_5V0
C_USB_BP
GPIO3
RESET*
DEBUG_CTL1
I2C_SDA1
I2C_IRQ1*
I2C_SDA2
LSX_R2P
LSX_P2R
C_SBU2
C_SBU1
C_USB_BN
C_USB_TN
C_USB_TP
RPD_G2
RPD_G1
UART_TX
USB_RP_P
SENSEP
SENSEN
UART_RX
SWD_CLK
SWD_DATA
SPI_SSZ
SPI_CLK
SPI_MOSI
I2C_SCL2
I2C_IRQ2*
I2C_SCL1
DEBUG_CTL2
BUSPOWERZ
C_CC2
C_CC1
SPI_MISO
NC
AUX_P
AUX_N
USB_RP_N
SS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DEBUG1
DEBUG3
DEBUG2
DEBUG4
GPIO1
GPIO2
GPIO5
GPIO4
GPIO6
MRESET
VBUS
VBUS
VBUS
VBUS
PP_HV
PP_HV
PP_HV
PP_5V0
PP_5V0
PP_HV
PP_5V0
LDO_BMC
LDO_1V8D
LDO_1V8A
VOUT_3V3
PP_CABLE
LDO_3V3
VIN_3V3
VDDIO
HV_GATE1
I2C_ADDR
R_OSC
GPIO0
GPIO8
GPIO7
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
OUT
OUT
BI
BI
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
G1
G2
S2
S1
BI
BI
NC
合肥怡飞苹果维修qq:82669515 qq群: 241000
SECONDARY ACE USB-C PORT CONTROLLER (UPC)
OR FLOAT IF UNUSED
VOUT_3V3 FOR RIDGE,
GROUND UPC SPI
CONNECT UPC SPI TO ROM
MAX 100uF TOTAL ON RAIL
NC or GND to dissipate heat
CAN GROUND PIN D6 IN PRODUCTION
PIN D6 IS UNDOCUMENTED RESET
for layout.
Add on
PU to PP3V3_S4 if convenient
FRONT PORT:
TO SMC
PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
REAR PORT:
ON BANSURI DESIGNS
USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT
NEED 0.1%
ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR
CAP FOR PP_5V0 ON VR PAGE
PRESENT FOR GPIO0, GPIO1
TESTPOINTS MUST BE
USE GPIO3 FOR POWER_GATE_EN
(EVEN IN PRODUCTION)
support page
Otherwise PU to PP3V3_UPC_XA_LDO
PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES
FUSE
32 OF 500
30 OF 73
1.0.0
051-02265
MIN_LINE_WIDTH=0.0180
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=20V
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.1V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.3500
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.3500
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
PP3V3_UPC_XB_LDO
PP20V_USBC_XB_VBUS_F
USBC_XB_USB_BOT_P
=PP5V_XB_USBC
=PP3V3R1V8_UPC_XB
TP_UPC_XB_SWD_CLK
I2C_UPC_XB_DBG_CTL_SCL
I2C_UPC_XB_DBG_CTL_SDA
USBC_XB_USB_TOP_N
USBC_XB_USB_BOT_N
USBC_XB_RPD_G2
=I2C_UPC_XB_INT1_L
TBT_XB_LSRX
UPC_XB_DBG3
UPC_XB_DBG2
UPC_XB_DBG1
DP_XB_AUXCH_N
DP_XB_AUXCH_P
USB_UPC_XB_F_P
=UPC_XB_I2C_STRAP
UPC_XB_5V_EN
UPC_XB_DBG4
UPC_XA_UART_TX
UPC_XB_SPI_MOSI
=I2C_UPC_XB_INT2_L
UPC_XB_SPI_MISO
UPC_XB_SPI_CLK
UPC_XA_UART_RX
USBC_XB_USB_TOP_P
USB_UPC_XB_F_N
=PP3V3_UPC_XB_AUX
UPC_XB_RESET
=I2C_UPC_XB_SCL1
=I2C_UPC_XB_SDA2
TBT_XB_LSTX
UPC_XB_SS
USBC_XB_SBU2
USBC_XB_SBU1
TP_UPC_XB_SWD_DATA
UPC_XA_UART_TX
=UPC_WAKE_L
=I2C_UPC_XB_SCL2
UPC_XB_HPD_RX
I2C_UPC_XB_DBG_CTL_SCL
NC_UPC_XB_I2C_ADDR
=PP3V3_UPC_XB_SX
TP_UPC_XB_DBG_UART_TX
USBC_X_POC_RESET
UPC_XB_BUSPOWERZ
UPC_XB_FAULT_L
DP_XB_HPD
=USBC_XB_RESET_L
TP_UPC_XB_DBG_UART_RX
TBT_X_RTD3_CIO_PWR_EN TBT_X_RTD3_USB_PWR_EN
=PPHV_INT_G3H
=PP3V3_G3H_UPC_XB
PP1V8_UPC_XB_LDOD
=USB_UPC_XB_P
=USB_UPC_XB_N
PP1V1_UPC_XB_LDO_BMC
UPC_XB_SPI_CS_L
=I2C_UPC_XB_SDA1
I2C_UPC_XB_DBG_CTL_SDA
UPC_XB_GATE1
=PP20V_USBC_XB_VBUS
UPC_XB_R_OSC
USBC_XB_RPD_G1
USBC_XB_CC1
USBC_XB_CC2
PP1V8_UPC_XB_LDOA
UPC_XB_GATE2
=PPHV_EXT_G3H
USB-C PORT CONTROLLER B
BOM_COST_GROUP=USB-C
SYNC_MASTER=E85-REF SYNC_DATE=06/17/2015
28
28
72 32
72 32
72 32
72 32
32
32
29 28
26
42
42
42
28
28
41 29
28
26
PWR-CLIP-33
FDPC4044
CRITICAL
5
8
4
1
3
2
Q3200
26
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C3208
0201
X5R-CERM
6.3V
20%
2.2UF
2
1
C3204
26
0201
CER-X5R
25V
10%
4700PF
NOSTUFF
2
1
C3220
0201
CER-X5R
25V
10%
4700PF
NOSTUFF
2
1
C3221
29 28 26
29 28 26
201MF1/20W5%
1M
21
R3208
201MF1/20W5%
1M
21
R3209
28
28
28
28
28
28
EXCX4CE
PLACE_NEAR=U3200.K5:5mm
PLACE_NEAR=U3200.L5:5mm
90-OHM-0.1A
CRITICAL
4
32
1
L3200
28
28
28
28
201
CERM-X5R-1
4V
20%
0.47UF
2
1
C3206
0402
X5R
35V
10%
1UF
2
1
C3201
0201
X5R
6.3V
20%
0.22UF
OMIT_TABLE
2
1
C3209
0201
TF-LF
1/20W
0.1%
15K
CRITICAL
2
1
R3203
0201
C0G
50V
2%
220PF
2
1
C3213
0201
C0G
50V
2%
220PF
2
1
C3214
BGA
CD3215A10
CRITICAL OMIT_TABLE
GROUND
H2
H1
B1
K11
J11
J10
H11
L5
K5
E2
F2
F4
G4
H7
B3
B4
A4
A3
B10
A10
K10
K9
F11
G2
B7
A8
A7
A6
H10
D11
C11
B11
A11
L11
E11
L4
K4
E1
G1
A2
K1
A5
D1
B5
D2
B6
C1
F1
A9
B9
H6
D7
G10
E10
C10
G11
D10
C2
B2
G7
G6
F8
F7
F6
E8
D8
B8
L1
H8
G8
H5
H4
G5
F5
E7
E6
E5
D6
A1
D5
E4
K3
L3
K2
L2
K6
L6
K7
L7
L8
K8
L10
L9
F10
J1
J2
U3200
201
MF
1/20W
5%
100K
2
1
R3211
201
MF
1/20W
5%
100K
2
1
R3210
201MF1/20W5%
1M
21
R3205
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C3200
28
28
28
32 28
32 28
0201-1
X5R
6.3V
20%
1.0UF
2
1
C3205
26
69 63 28
28
69
28
28
30
30
72
28
30 29 28
72
69
28
70
30 29 28
28
30
70
33
72
29 28
33
72
29 28
28
30
28
69 29
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
BI
BI
IN
OUT
OUT
OUT
OUT
NCNC
G1
G2
S2
S1
BI
BI
BI
BI
OUT
IN
OUT
OUT
BI
BI
SYM_VER-1
BI
BI
BI
BI
HV FET/SENSE
PORT MUX DIGITAL CORE I/O AND CONTROL
TYPE-C
HV_GATE2
PP_5V0
C_USB_BP
GPIO3
RESET*
DEBUG_CTL1
I2C_SDA1
I2C_IRQ1*
I2C_SDA2
LSX_R2P
LSX_P2R
C_SBU2
C_SBU1
C_USB_BN
C_USB_TN
C_USB_TP
RPD_G2
RPD_G1
UART_TX
USB_RP_P
SENSEP
SENSEN
UART_RX
SWD_CLK
SWD_DATA
SPI_SSZ
SPI_CLK
SPI_MOSI
I2C_SCL2
I2C_IRQ2*
I2C_SCL1
DEBUG_CTL2
BUSPOWERZ
C_CC2
C_CC1
SPI_MISO
NC
AUX_P
AUX_N
USB_RP_N
SS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DEBUG1
DEBUG3
DEBUG2
DEBUG4
GPIO1
GPIO2
GPIO5
GPIO4
GPIO6
MRESET
VBUS
VBUS
VBUS
VBUS
PP_HV
PP_HV
PP_HV
PP_5V0
PP_5V0
PP_HV
PP_5V0
LDO_BMC
LDO_1V8D
LDO_1V8A
VOUT_3V3
PP_CABLE
LDO_3V3
VIN_3V3
VDDIO
HV_GATE1
I2C_ADDR
R_OSC
GPIO0
GPIO8
GPIO7
OUT
BI
BI
BI
BI
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
TBT_TX0
CC2
DP_HPD
MAX DCR = 12 MOHM
CC1
PLACE VBUS CAP NEAR EACH VBUS PIN
DESIGN: X502/MLB_CATZ
TBT_RX0
LAST CHANGE: Mon Aug 8 12:54:34 2016
(NO LANE REVERSALS ALLOWED.)
5.6V
TBT_TX1
BOTTOM
D+/D-
SBU2 (RFU2)
TBT_RX1
D+/D- TOP
SBU1 (RFU1)
DP_AUX_P
514-00062
FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK
31 OF 73
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.1200
33 OF 500
1.0.0
051-02265
PP20V_USBC_XA_VBUS
PP20V_USBC_XA_VBUS_CONN
USBC_XA_CC1_CONN
USBC_XA_CC2_CONN
USBC_XA_USB_DBG_BOT_N
USBC_XA_CC2
USBC_XA_D2R_CONN_P<2>
USBC_XA_D2R_N<2> USBC_XA_D2R_P<2>
USBC_XA_D2R_CONN_N<2>
USBC_XA_SBU2
USBC_XA_R2D_P<2>
USBC_XA_D2R_P<1>
USBC_XA_R2D_C_P<2>
USBC_XA_R2D_C_N<2>
USBC_XA_R2D_N<2>
SAVE_CC1A_B
USBC_XA_CC2_CONNUSBC_XA_CC1
SAVE_CC2A_B
SAVE_CC1A_G
USBC_XA_CC1_CONN
USBC_XA_D2R_CONN_P<1> USBC_XA_D2R_CONN_N<1>
SAVE_CC1A_Z
=PPBUS_G3H
USBC_XA_R2D_N<1>
USBC_XA_R2D_P<1>
USBC_XA_SBU1
USBC_XA_D2R_N<1>
SAVE_CC2A_Z
=PPBUS_G3H
USBC_XA_R2D_C_P<1> USBC_XA_R2D_C_N<1>
SAVE_CC2A_G
USBC_XA_USB_DBG_TOP_P USBC_XA_USB_DBG_TOP_NUSBC_XA_USB_DBG_BOT_P
BOM_COST_GROUP=USB-C
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
USB-C CONNECTOR A
CRITICALTVS DIODE,1LINE,BIDIR,3.5PF,24V,0201377S00017 4 D3308,D3309,D3408,D3409
CRITICAL
GDZ5V6LP3
DFN0201
K
A
D3362
CRITICAL
GDZ5V6LP3
DFN0201
K
A
D3352
NSS60101DMT
WDFN6
4
8 3
5
Q3351
NSS60101DMT
WDFN6
1
7 6
2
Q3351
0
GND_VOID=TRUE
5% 1/20W MF 0201
21
R3375
0
GND_VOID=TRUE
5% 1/20W MF 0201
21
R3374
0
GND_VOID=TRUE
5% 1/20W MF 0201
21
R3376
0
GND_VOID=TRUE
5% 1/20W MF 0201
21
R3377
1UF
10% 25V X5R 402
2
1
C3309
680PF
10% 25V
X7R-CERM
0201
2
1
C3362
4.99K
1%
1/20W
MF
201
2
1
R3363
10K
5%
1/20W
MF
201
21
R3361
4.02K
1%
1/20W
MF
201
2
1
R3362
CRITICAL
DMT5015LFDF
UDFN202-6
84
3
76521
Q3360
CRITICAL
100OHM-20%-24V-0.3A
0603
21
R3360
29 28
CRITICAL
DMT5015LFDF
UDFN202-6
84
3
76521
Q3350
680PF
10% 25V
X7R-CERM
0201
2
1
C3352
4.99K
1%
1/20W
MF
201
2
1
R3353
4.02K
1%
1/20W
MF
201
2
1
R3352
10K
5%
1/20W
MF
201
21
R3351
CRITICAL
100OHM-20%-24V-0.3A
0603
21
R3350
29 28
CRITICAL
0.01UF
BYPASS=J3300.A67::2MM
10% 25V X5R-CERM 0201
2
1
C3305
CRITICAL
ESD112-B1-02ELS
0201-THICKSTNCL
2
1
D3312
CRITICAL
ESD112-B1-02ELS
0201-THICKSTNCL
2
1
D3313
CRITICAL
ESD112-B1-02ELS
0201-THICKSTNCL
2
1
D3305
CRITICAL
ESD112-B1-02ELS
0201-THICKSTNCL
2
1
D3304
CRITICAL
RCPT-USBC-POR-J130
M-RT-TH
676665
64
63
62
61
60
59
58
57
56
55
54
53
10
7
6
3
2
37
27
26
23
22
19
20
21
25
24
4
5
9
8
41
40
38
39 43
42
1
36
J3300
CRITICAL
5.5V-6.2PF
0201-THICKSTNCL
2
1
D3316
OMIT_TABLE
CRITICAL
5.5V-6.2PF
0201-THICKSTNCL
2
1
D3309
OMIT_TABLE
CRITICAL
5.5V-6.2PF
0201-THICKSTNCL
2
1
D3308
CRITICAL
5.5V-6.2PF
0201-THICKSTNCL
2
1
D3301
CRITICAL
0.01UF
BYPASS=J3300.A68::2MM
10% 25V X5R-CERM 0201
2
1
C3306
NOSTUFF
1UF
10% 25V X5R 402
2
1
C3304
OMIT
SHORT
NONE NONE NONE
603
2 1
L3300
CRITICAL
NSR20F40NX_G
DSN2
K
A
D3300
CRITICAL
0.01UF
BYPASS=J3300.A58::2MM
10% 25V X5R-CERM 0201
2
1
C3300
CRITICAL
0.01UF
BYPASS=J3300.A58::2MM
10% 25V X5R-CERM 0201
2
1
C3301
CRITICAL
0.01UF
BYPASS=J3300.A68::2MM
10% 25V X5R-CERM 0201
2
1
C3307
CRITICAL
0.01UF
BYPASS=J3300.A69::2MM
10% 25V X5R-CERM 0201
2
1
C3308
CRITICAL
0.01UF
BYPASS=J3300.A59::2MM
10% 25V X5R-CERM 0201
2
1
C3302
CRITICAL
0.01UF
BYPASS=J3300.A59::2MM
10% 25V X5R-CERM 0201
2
1
C3303
29
28
28
29
28
28
0.22UF
GND_VOID=TRUE
10%6.3V
X5R-CERM
0201
21 C3371
0.22UF
GND_VOID=TRUE
10%6.3V
X5R-CERM
0201
21 C3370
72 26
72 26
CRITICAL
ESD101-B1-02ELS
GND_VOID=TRUE
0201-THICKSTNCL
2
1
D3310
CRITICAL
ESD101-B1-02ELS
GND_VOID=TRUE
0201-THICKSTNCL
2
1
D3311
CRITICAL
ESD101-B1-02ELS
GND_VOID=TRUE
0201-THICKSTNCL
2
1
D3314
CRITICAL
ESD101-B1-02ELS
GND_VOID=TRUE
0201-THICKSTNCL
2
1
D3315
72 26
72 26
72 26
72 26
CRITICAL
ESD101-B1-02ELS
GND_VOID=TRUE
0201-THICKSTNCL
2
1
D3302
CRITICAL
ESD101-B1-02ELS
GND_VOID=TRUE
0201-THICKSTNCL
2
1
D3303
72 26
72 26
0.22UF
GND_VOID=TRUE
10% 6.3V
X5R-CERM
0201
2 1C3373
0.22UF
GND_VOID=TRUE
10% 6.3V
X5R-CERM
0201
2 1C3372
CRITICAL
ESD101-B1-02ELS
GND_VOID=TRUE
0201-THICKSTNCL
2
1
D3306
CRITICAL
ESD101-B1-02ELS
GND_VOID=TRUE
0201-THICKSTNCL
2
1
D3307
72 28
31
31
72
31
31
69 52 32 31
72
72
69 52 32 31
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
D
S
G
BI
D
S
G
BI
PORT A
SYM 1 OF 2
CONN1_VBUS3
CONN1_TX1+
CONN1_TX1-
CONN1_VBUS4
CONN1_RFU1
CONN1_D1+
CONN1_D1-
CONN1_CC1
CONN1_VBUS5
CONN1_RX2-
CONN1_RX2+
SHLD
GND
CONN1_VBUS0
CONN1_RX1-
CONN1_RX1+
CONN1_CC2
CONN1_RFU2
CONN1_VBUS1
CONN1_D2+
CONN1_D2-
CONN1_TX2-
CONN1_TX2+
CONN1_VBUS2
BI
BI
BI
BI
BI
BI
IN
IN
OUT
OUT
OUT
OUT
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
(NO LANE REVERSALS ALLOWED.)
TBT_RX1
TBT_RX0
TBT_TX0
SBU1 (RFU1)
CC1
DP_AUX_P
D+/D- TOP
ESD DIODES PRESENT)
DP_HPD
BOTTOM
CC2
D+/D-
SBU2 (RFU2)
.
DESIGN: X502/MLB_CATZ LAST CHANGE: Fri Aug 5 13:34:33 2016
TBT_TX1
DC PATH TO GND
470K PD PROVIDES
(NEEDED EVEN IF
514-00062
MAX DCR = 12 MOHM
PLACE VBUS CAP NEAR EACH VBUS PIN
FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK
32 OF 73
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.2000
34 OF 500
1.0.0
051-02265
USBC_XB_D2R_CONN_P<2>
USBC_XB_D2R_CONN_N<2>USBC_XB_R2D_C_N<2>
USBC_XB_D2R_CONN_P<1>
USBC_XB_D2R_N<1>
USBC_XB_D2R_P<1>
PP20V_USBC_XB_VBUS
USBC_XB_SBU1
USBC_XB_CC1_CONN
SAVE_CC1B_B
SAVE_CC1B_Z
SAVE_CC2B_B
SAVE_CC2B_Z
USBC_XB_R2D_C_P<2>
USBC_XB_R2D_N<2>
SAVE_CC2B_G
USBC_XB_R2D_P<2>
USBC_XB_CC1 USBC_XB_CC2
=PPBUS_G3H
USBC_XB_D2R_CONN_N<1>
USBC_XB_CC2_CONN
USBC_XB_D2R_P<2>
USBC_XB_D2R_N<2>
USBC_XB_R2D_C_P<1> USBC_XB_R2D_C_N<1>USBC_XB_R2D_N<1>
=PPBUS_G3H
SAVE_CC1B_G
USBC_XB_CC1_CONN
USBC_XB_R2D_P<1>
PP20V_USBC_XB_VBUS_CONN
USBC_XB_CC2_CONN
USBC_XB_SBU2
USBC_XB_USB_TOP_P
USBC_XB_USB_BOT_N
USBC_XB_USB_TOP_NUSBC_XB_USB_BOT_P
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
USB-C CONNECTOR B
BOM_COST_GROUP=USB-C
0201-THICKSTNCL
ESD112-B1-02ELS
CRITICAL
2
1
D3413
M-RT-TH
RCPT-USBC-POR-J130
84
83
82
81
80
79
76
75
74
73
72
71
70
69
68
44
18
15
14
11
35
34
31
30
28
29
17
16
12
13
33
32
48
49
46
47 51
50
45
52
J3300
0201-THICKSTNCL
5.5V-6.2PF
CRITICAL
2
1
D3416
0201-THICKSTNCL
5.5V-6.2PF
CRITICAL
OMIT_TABLE
2
1
D3409
0201-THICKSTNCL
5.5V-6.2PF
CRITICAL
OMIT_TABLE
2
1
D3408
0201-THICKSTNCL
5.5V-6.2PF
CRITICAL
2
1
D3401
0.22UF0201
X5R-CERM
6.3V 10%
GND_VOID=TRUE
21
C3471
72 26
72 26
72 30
72 30
30
72 26
72 26
0201
X5R-CERM
6.3V10%
GND_VOID=TRUE
0.22UF
2 1C3472
0201
X5R-CERM
6.3V10%
GND_VOID=TRUE
0.22UF
2 1C3473
72 26
0201-THICKSTNCL
GND_VOID=TRUE
ESD101-B1-02ELS
CRITICAL
2
1
D3406
0201-THICKSTNCL
GND_VOID=TRUE
ESD101-B1-02ELS
CRITICAL
2
1
D3407
72 26
0201-THICKSTNCL
GND_VOID=TRUE
ESD101-B1-02ELS
CRITICAL
2
1
D3402
0201-THICKSTNCL
GND_VOID=TRUE
ESD101-B1-02ELS
CRITICAL
2
1
D3403
30
603
NONE
NONE
NONE
SHORT
OMIT
2 1
L3400
0201-THICKSTNCL
GND_VOID=TRUE
ESD101-B1-02ELS
CRITICAL
2
1
D3414
72 30
0201
X5R-CERM
25V
10%
BYPASS=J3300.A68::2MM
0.01UF
CRITICAL
2
1
C3406
BYPASS=J3300.A68::2MM
0201
X5R-CERM
25V
10%
0.01UF
CRITICAL
2
1
C3407
0201
X5R-CERM
25V
10%
BYPASS=J3300.A69::2MM
0.01UF
CRITICAL
2
1
C3408
0201-THICKSTNCL
ESD101-B1-02ELS
CRITICAL
GND_VOID=TRUE
2
1
D3410
72 30
0201-THICKSTNCL
GND_VOID=TRUE
ESD101-B1-02ELS
CRITICAL
2
1
D3415
ESD101-B1-02ELS
0201-THICKSTNCL
GND_VOID=TRUE
CRITICAL
2
1
D3411
0201
X5R-CERM
25V
10%
BYPASS=J3300.A58::2MM
0.01UF
CRITICAL
2
1
C3400
0201
X5R-CERM
25V
10%
0.01UF
BYPASS=J3300.A58::2MM
CRITICAL
2
1
C3401
0201
X5R-CERM
25V
10%
BYPASS=J3300.A59::2MM
CRITICAL
0.01UF
2
1
C3402
BYPASS=J3300.A59::2MM
0201
X5R-CERM
25V
10%
CRITICAL
0.01UF
2
1
C3403
72 26
DFN0201
GDZ5V6LP3
CRITICAL K
A
D3452
DFN0201
GDZ5V6LP3
CRITICAL K
A
D3462
WDFN6
NSS60101DMT
1
7 6
2
Q3451
WDFN6
NSS60101DMT
4
8 3
5
Q3451
0201MF1/20W5%
GND_VOID=TRUE
0
21
R3477
0201MF1/20W5%
GND_VOID=TRUE
0
21
R3476
0201MF1/20W5%
GND_VOID=TRUE
0
21
R3475
0201MF1/20W5%
GND_VOID=TRUE
0
21
R3474
402
X5R
25V
10%
1UF
2
1
C3409
DSN2
NSR20F40NX_G
CRITICAL
K
A
D3400
402
X5R
25V
10%
1UF
NOSTUFF
2
1
C3404
0201
X7R-CERM
25V
10%
680PF
2
1
C3452
201
MF
1/20W
1%
4.99K
2
1
R3453
201
MF
1/20W
5%
10K
21
R3451
201
MF
1/20W
1%
4.02K
2
1
R3452
UDFN202-6
DMT5015LFDF
CRITICAL
84
3
76521
Q3450
0603
100OHM-20%-24V-0.3A
CRITICAL
21
R3450
30 28
201
MF
1/20W
1%
4.99K
2
1
R3463
0201
X7R-CERM
25V
10%
680PF
2
1
C3462
201
MF
1/20W
1%
4.02K
2
1
R3462
UDFN202-6
DMT5015LFDF
CRITICAL
84
3
76521
Q3460
100OHM-20%-24V-0.3A
0603
CRITICAL
21
R3460
201
MF
1/20W
5%
10K
21
R3461
30 28
0201
X5R-CERM
25V
10%
BYPASS=J3300.A67::2MM
0.01UF
CRITICAL
2
1
C3405
0201-THICKSTNCL
ESD112-B1-02ELS
CRITICAL
2
1
D3404
0201-THICKSTNCL
ESD112-B1-02ELS
CRITICAL
2
1
D3405
0201-THICKSTNCL
ESD112-B1-02ELS
CRITICAL
2
1
D3412
0201
X5R-CERM
6.3V 10%
GND_VOID=TRUE
0.22UF
21 C3470
72 26
72 28
32
72
69 52 32 31
32
72
69 52 32 31
32
72
32
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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IV ALL RIGHTS RESERVED
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PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
SYM 2 OF 2
PORT B
CONN2_RX2+
CONN2_RX2-
CONN2_VBUS3
CONN2_RFU1
CONN2_D1-
CONN2_D1+
CONN2_CC1
CONN2_VBUS2
CONN2_TX1-
CONN2_TX1+
GND
CONN2_RX1+
CONN2_RX1-
CONN2_VBUS0
CONN2_RFU2
CONN2_D2-
CONN2_D2+
CONN2_CC2
CONN2_VBUS1
CONN2_TX2+
CONN2_TX2-
IN
IN
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
IN
D
S
G
BI
D
S
G
BI
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
TBT T "POC" Power-up Reset
UB601
Output
Delay
Vth 2.508V nominal
Push-pull
440us +/- 20us
.
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
33 OF 73
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
VOLTAGE=3.3V
35 OF 500
1.0.0
051-02265
=PP3V3_S5_TBT_X
MAKE_BASE=TRUE
PP3V3_S5_TBT_X_SW
=PP3V3_UPC_XB_SX
=PP3V3_UPC_XA_SX
=USBC_XB_RESET_L
P3V3_TBT_X_SX_EN
TBTXPOCRST_SNS TBTXPOCRST_CT
=PP3V3_TBT_X_SX
PP3V3_TBT_X_SX
MAKE_BASE=TRUE
P3V3_TBT_X_SX_EN_R
MAKE_BASE=TRUE
USBC_X_RESET_L_R USBC_X_RESET_L
BOM_COST_GROUP=USB-C
SYNC_MASTER=J79_GREG SYNC_DATE=03/24/2016
STDFN
SLG5AP1449V
CRITICAL
3
1
4
2
U3500
30
201
MF
1/20W
5%
100K
2
1
R3505
0201
C0G
25V
5%
100PF
2
1
C3500
30
29
0201
MF
1/20W
5%
0
21
R3501
0201
MF
1/20W
5%
0
NOSTUFF
21
R3504
USON
TPS3895ADRY
CRITICAL
6
4
3
2
1
5
U3501
201
MF
1/20W
1%
100K
2
1
R3502
201
MF
1/20W
1%
24.9K
2
1
R3503
28 27 26
402
MF-LF 1/16W
5%
0
NOSTUFF
21
R3500
69
26
28 27
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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REVISION
DRAWING NUMBER SIZE
D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
ON
S
D
GND
IN
IN
IN
VCC
CT
SENSE_OUTENABLE
SENSE
GND
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
2X 518S0867
(GPIO12)
(GPIO13)
(GPIO14)
(GPIO0)
(GPIO1)
(GPIO7)
(GPIO8)
(GPIO6)
(GPIO3)
(GPIO2)
(GPIO10)
(GPIO4) (GPIO5)
(GPIO9)
(GPIO11)
(FW changed to BT HOST WAKE)
(FW changed to BT DEVICE WAKE)
(GPIO15)
BT ROM
WIFI ROM
RF Diplexers & Matching
1.0.0
051-02265
37 OF 500
34 OF 73
WLAN_UART_RX WLAN_UART_TX WLAN_ROM_CLK WLAN_ROM_CS
SYSCLK_CLK32K_BT_AP
=PP3V3_S4_WLAN
JTAG_WLAN_SEL
RF_G_0_DIPLEXER
PCIE_CLK100M_AP_C_P
PCIE_AP_D2R_C_N
PCIE_AP_D2R_C_P
PCIE_AP_R2D_P
RF_A_0_MATCHRF_0_ANT
BT_DEV_WAKE
RF_1_ANT
SMC_BT_PWR_EN
RF_A_0_DIPLEXER
BT_GPIO4
BT_UART_CTS_L
BT_SPI_CLK
WLAN_ROM_MISO
AP_CLKREQ_L
TP_JTAG_WLAN_TCK
RF_A_1_DIPLEXER
=PP3V3_S4_WLAN
BT_SPI_MISO
BT_SPI_MOSI BT_SPI_CLK
BT_SPI_CS_L BTROM_WP_L BTROM_HOLD_L
RF_A_1_MATCH
RF_G_1_MATCH
RF_1_ANT_MATCH_T
RF_G_1_DIPLEXER
WLAN_ROM_MOSI
BT_LOW_PWR_L
AP_DEV_WAKE
NC_USB_BTP NC_USB_BTN
AP_PCIE_WAKE_L
BT_UART_R2D
AP_RESET_L
SMC_WIFI_EVENT_L
BT_WAKE_L
RF_G_0_MATCH
TP_JTAG_WLAN_TMS TP_JTAG_WLAN_TRST JTAG_WLAN_TDI TP_JTAG_WLAN_TDO
BT_SPI_MOSI
PCIE_CLK100M_AP_C_N
WLAN_ROM_MOSI WLAN_ROM_CS
PCIE_AP_R2D_N
WLAN_ROM_CLK
=PP3V3_S4_WLAN
WLAN_ROM_ORG
WLAN_ROM_MISO
SMC_WIFI_PWR_EN
BT_SPI_MISO
BT_SPI_CS_L
BT_UART_RTS_L
BT_UART_D2R
RF_0_ANT_MATCH_T
WIFI/BT MODULE
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
19
35
35
72 35
72 35
72 35
72 35
35
35
0201
CERM
25V
5%
12PF
2
1
C3711
0201
CERM
25V
5%
12PF
2
1
C3710
0201
CERM
25V
5%
12PF
2
1
C3709
0201
CERM
25V
5%
12PF
2
1
C3708
USON
W25X20CLUXIG
2MBIT-3V
CRITICAL
OMIT_TABLE
3
8
9
7
4
2
5
1
6
U3770
0201
X5R-CERM
10V
10%
0.1UF
2
1
C3770
201
MF
1/20W
5%
4.7K
2
1
R3773
201
MF
1/20W
5%
100K
2
1
R3771
201
MF
1/20W
5%
100K
2
1
R3772
0805
DPX205950DT-9062A1SJ
CRITICAL
6
4
5
3
1
2
U3720
0201
C0G-CERM
25V
+/-0.1PF
2.0PF
NOSTUFF
2
1
C3728
0201
MF
1/20W
5%
0
CRITICAL
21
R3724
0201
C0G-CERM
25V
+/-0.05PF
0.3PF
CRITICAL
NOSTUFF
2
1
C3725
0201
C0G-CERM
25V
+/-0.1PF
2.0PF
NOSTUFF
2
1
C3723
0201
MF
1/20W
5%
0
CRITICAL
21
R3725
0201
C0G-CERM
25V
+/-0.1PF
2.0PF
NOSTUFF
2
1
C3724
0201
C0G-CERM
25V
+/-0.1PF
2.0PF
NOSTUFF
2
1
C3720
0201
MF
1/20W
5%
0
CRITICAL
21
R3712
0201
C0G-CERM
25V
+/-0.1PF
2.0PF
NOSTUFF
2
1
C3730
0201
C0G-CERM
25V
+/-0.1PF
2.0PF
NOSTUFF
2
1
C3729
0201
MF
1/20W
5%
0
CRITICAL
21
R3714
0201
C0G-CERM
25V
+/-0.1PF
2.0PF
NOSTUFF
2
1
C3721
F-ST-SM
20449-001E-03
CRITICAL
1
4
3
2
J3720
F-ST-SM
20449-001E-03
CRITICAL
1
4
3
2
J3710
201
C0G
25V
+/-0.05PF
0.4PF
2
1
C3727
0201
MF
1/20W
5%
0
CRITICAL
21
R3723
0201
C0G-CERM
25V
+/-0.05PF
0.3PF
2
1
C3718
0201
MF
1/20W
5%
0
CRITICAL
21
R3710
0201
COG-CERM
25V
+/-0.05PF
0.2PF
NOSTUFF
2
1
C3726
0201
COG-CERM
25V
+/-0.05PF
0.2PF
NOSTUFF
2
1
C3719
0805
DPX205950DT-9062A1SJ
CRITICAL
6
4
5
3
1
2
U3710
35 18
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3704
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3707
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3706
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3705
35 14
LGA
LBEE5UA1BL-717
CRITICAL
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
78
75
72
69
67
64
59
57
40
38
37
36
34
33
32
30
29
27
26
24
23
19
15
U3700
LGA
LBEE5UA1BL-717
CRITICAL
OMIT_TABLE
60
1
73
74
71
70
77
76
79
80
49
50
55
51
52
53
11
42
43
41
44
63
45
65
66
62
61
47
17
54
48
46
68
16
3
4
12
13
8
9
56
18
14
7
6
21
10
20
58
35
25
2
5
39
28
31
22
U3700
201
MF
1/20W
5%
10K
2
1
R3704
201
MF
1/20W
5%
10K
2
1
R3703
201
MF
1/20W
5%
10K
2
1
R3702
201
MF
1/20W
5%
10K
2
1
R3701
35 16
0201
X5R-CERM
10V
10%
0.1UF
2
1
C3780
201
MF
1/20W
5%
10K
2
1
R3780
UDFN
AT93C66B-MAHM
CRITICAL
OMIT_TABLE
8
9
2
6
7
5
43
1
U3780
41
DFN1006H4-3
NO_XNET_CONNECTION=1
DMN32D2LFB4
2
1
3
Q3730
201
MF
1/20W
1%
100K
2
1
R3730
40 39 35
35 19 16
35 19
35
35
35
35 39 35
201
MF
1/20W
5%
10K
2
1
R3700
603
X5R
6.3V
20%
10UF
CRITICAL
2
1
C3702
603
X5R
6.3V
20%
10UF
CRITICAL
2
1
C3703
402
X5R
6.3V
20%
4.7UF
CRITICAL
2
1
C3701
402
X5R
6.3V
20%
4.7UF
CRITICAL
2
1
C3700
41 39 35
34
34
69 34 19
72
72
72 72
72
72
34
34 72
72
69 34 19
34
34 34
34
72
72
72
72
34
72
72
72
72
72
34
34
34
34
69 34 19
34
34
34
72
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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REVISION
DRAWING NUMBER SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
IN
OUT
OUT
OUT
IN
VCC
DO(IO1)
DI(IO0)
THRM_PAD GND
CLK
HOLD*
WP*
CS*
GND
COM
LO
HI
GND
COM
LO
HI
OUT
IN
NC
NC
(2 OF 2)
THRM_PAD
GND
THRM_PAD
SYM 1 OF 2
HSIC_WLAN_DATA
HSIC_HOST_READY/PCIE_DEV_WAKE
VDDIO_1P8
CLK32K_AP
BT_GPIO4
ANT_SWITCH_CORE0
ANT_SWITCH_CORE1
BT_WAKE
BATT_RF_VCC
BATT_VCC
BT_UART_RTS*
BT_PCM_CLK
BT_PCM_SYNC
BT_PCM_OUT
BT_UART_CTS*
BT_UART_RXD
BT_UART_TXD
BT_USB_DP
BT_USB_DN
BT_PCM_IN
WLAN_PCIE_REFCLKN
WLAN_PERST
WL_UART_RX
WL_GPIO_13
WL_HOST_WAKE
WLAN_PCIE_REFCLKP
WLAN_PCIE_TDP0
WLAN_PCIE_TDN0
WLAN_PCIE_CLKREQ
WLAN_PCIE_PME
WLAN_PCIE_RDP0
WLAN_PCIE_RDN0
WL_GPIO_9
WL_UART_TX
FAST_RTS_OUT
FAST_UART_RX
WL_GPIO_8
FAST_UART_TX
WLAN_REG_ON
JTAG_SEL
HSIC_DEV_RDY
BT_REG_ON
HSIC_WLAN_STROBE
JTAG_TMS
SEC_IN/JTAG_TDI
JTAG_TRST
SEC_OUT/JTAG_TDO
HOST_WAKE_BT
BT_GPIO3
5G_CORE1_ANT
2G_CORE1_ANT
5G_CORE0_ANT
2G_CORE0_ANT
HSIC_RESUME_FAST_CTS_IN/JTAG_TCK
BT_GPIO5
NC
NC
IN
NC
VCC
PAD
THRM
GND
CS
DI
NC
ORG
DO
SK
OUT
D
SG
SYM_VER_2
BI
NC
NC
IN
OUT
OUT
IN
OUT
IN
NC
NCNC
NC
NC
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
WIFI UART ISOLATION
BT UART Isolation
35 OF 73
38 OF 500
051-02265
1.0.0
AP_DEV_WAKE
PCH_BT_UART_D2R
WLAN_UART_RX
WLAN_UART_TX
=PP3V3_S0_BT_UART
AP_PCIE_WAKE_L
AP_CLKREQ_L
AP_RESET_L
BT_LOW_PWR_L
SMC_WIFI_PWR_EN
SMC_WIFI_EVENT_L
SMC_BT_PWR_EN
BT_UART_RTS_L
=PP3V3_S4_BT_UART
BT_UART_D2R
PLT_RST_L
PCH_BT_UART_CTS_L PCH_BT_UART_RTS_L
PCH_BT_UART_R2D
PLT_RST_L
=PP3V3_S0_BT_UART
BT_UART_R2D
BT_UART_CTS_L
=PP3V3_S4_BT_UART
MAKE_BASE=TRUE
TP_WLAN_UART_R2D
MAKE_BASE=TRUE
PD_WLAN_UART_D2R
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
PCIE_CLK100M_AP_CC_P
PCIE_CLK100M_AP_CC_N
PCIE_AP_D2R_CC_N
PCIE_AP_D2R_CC_P
PCIE_AP_R2D_CC_N
PCIE_AP_R2D_CC_P
PCIE_CLK100M_AP_C_N
PCIE_CLK100M_AP_C_P
PCIE_AP_D2R_C_N
PCIE_AP_D2R_C_P
PCIE_AP_R2D_N
PCIE_AP_R2D_P
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
WIFI/BT Module Support
0201
CERM
25V
5%
12PF
2
1
C3836
0201
CERM
25V
5%
12PF
2
1
C3832
0201
CERM
25V
5%
12PF
2
1
C3826
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3837
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3833
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3827
0201
CERM
25V
5%
12PF
2
1
C3822
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3823
0201
CERM
25V
5%
12PF
2
1
C3834
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3835
0201
CERM
25V
5%
12PF
2
1
C3830
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3831
0201
CERM
25V
5%
12PF
2
1
C3824
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3825
0201
CERM
25V
5%
12PF
2
1
C3820
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3821
41 39 34
39 34
34 16 34 14
40 39 34
34 18
34 19 16
34 19
0201
CERM
25V
5%
12PF
2
1
C3896
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3897
0201
CERM
25V
5%
12PF
2
1
C3891
0201
C0G
25V
+/-0.1PF
3PF
2
1
C3892
EXCX4CE
90-OHM-0.1A
CRITICAL
4
32
1
L3858
0.65X0.5X0.3MM-SM
2.4GHZ
CRITICAL
4
32
1
L3852
0.65X0.5X0.3MM-SM
2.4GHZ
CRITICAL
4
32
1
L3854
72 34
72 34
34
34
72 34
72 34
15
15
72 15
72 15
72 15
72 15
0201C0G25V5%
100PF
21
C3859
0201C0G25V5%
100PF
21
C3858
0201X5R-CERM16V10%
0.1UF
21
C3853
0201X5R-CERM16V10%
0.1UF
21
C3852
0201X5R-CERM16V10%
0.1UF
21
C3854
0201X5R-CERM16V10%
0.1UF
21
C3857
201
MF
1/20W
5%
100K
2
1
R3893
201
MF
1/20W
5%
100K
2
1
R3894
201
MF
1/20W
5%
10K
NOSTUFF
2
1
R3840
34
34
201
MF
1/20W
5%
100K
2
1
R3895
68 35 19 14
0201
X5R-CERM
10V
10%
BYPASS=U3895::5mm
0.1UF
2
1
C3895
16 34
34 16
0201
X5R-CERM
10V
10%
BYPASS=U3890::5mm
0.1UF
2
1
C3890
68 35 19 14
34 16
16 34
XSON
74LVC2G126GN
CRITICAL
3
6
8
7
1
4
5
2
U3895
XSON
74LVC2G126GN
CRITICAL
3
6
8
7
1
4
5
2
U3890
69 35
69 35
69 35
69 35
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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REVISION
DRAWING NUMBER SIZE
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
ININ
BI
OUT
IN
OUT
SYM_VER-1
SYM_VER-1
SYM_VER-1
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
OUT
IN
OUT OUT
OUTOUT
IN
IN IN
ININ
GND
VCC
2OE
A2
1OE
Y2
Y1A1
GND
VCC
2OE
A2
1OE
Y2
Y1A1
合肥怡飞苹果维修qq:82669515 qq群: 241000
(CAM_XTAL:NO)
(CAM_XTAL:NO)
(=PP3V3_S0_CAMERA)
L3902:1
(=PP3V3_S0_CAMERA)
PU on PCH page
PD = 1.35V
L3901:1
PD = 24MHz
PU = 25MHz
36 OF 73
VOLTAGE=0V
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1500
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
DIDT=TRUE
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000
VOLTAGE=0V
39 OF 500
1.0.0
051-02265
GND_CAM_PVSSC
PP1V35_CAM
CAM_TEST_MODE
PP1V8_CAM
MIPI_CLK_P MIPI_CLK_N
MIPI_DATA_P MIPI_DATA_N
PCIE_CAMERA_R2D_P PCIE_CAMERA_R2D_N
PCIE_CLK100M_CAMERA_C_P PCIE_CLK100M_CAMERA_C_N
PCIE_CAMERA_D2R_C_P PCIE_CAMERA_D2R_C_N
CLK25M_CAM_CLKP CLK25M_CAM_CLKN
I2C_CAM_SMBDBG_CLK I2C_CAM_SCL I2C_CAM_SMBDBG_DAT I2C_CAM_SDA
TP_CAM_JTAG_TCK TP_CAM_JTAG_TDI TP_CAM_JTAG_TDO TP_CAM_JTAG_TMS TP_CAM_JTAG_TRST_L TP_CAM_JTAG_SRST_L
CAMERA_CLKREQ_L
TP_CAM_PCIE_WAKE_L
CAMERA_RESET_L
CAM_PWR_SEL
CAM_DEBUG_RESET_L
CAM_SENSOR_WAKE_L CAMERA_PWR_EN
TP_CAM_GPIO3
TP_CAM_RAMCFG2
TP_CAM_RAMCFG1
TP_CAM_RAMCFG0
TP_CAM_LV_JTAG_TRSTN
TP_CAM_LV_JTAG_TMS
TP_CAM_LV_JTAG_TDO
TP_CAM_LV_JTAG_TDI
TP_CAM_LV_JTAG_TCK
TP_CAM_TEST_MODE2
TP_CAM_TEST_MODE1
TP_CAM_TEST_MODE0
CAM_XTAL_SEL
CAM_XTAL_FREQ
TP_CAM_UARTTXD
CAM_TEST_OUT
CAM_UARTRXD
TP_CAM_UARTRTS
CAM_UARTCTS
CAM_TEST_MODE
GND_CAM_PVSSC
=PP3V3_S0_CAMERA
PP1V2_CAM
PP1V35_DDR_CLK
PP0V675_CAM_VREF
PP1V2_CAM_PCIE_VDD_FLT
PP1V2_CAM_PCIE_PVDD_FLT
P1V2_CAM_SRVLXC_PHASE
P1V35_CAM_SRVLXD_PHASE
PP1V35_CAM
PP1V2_CAM_XTALPCIEVDD
PP1V8_CAM
PP1V2_CAM PP1V35_CAM
PP1V2_CAM_XTALPCIEVDD
MAKE_BASE=TRUE
GND_CAM_PVSSD
MEM_CAM_CKE
MEM_CAM_A<0> MEM_CAM_A<1> MEM_CAM_A<2> MEM_CAM_A<3> MEM_CAM_A<4> MEM_CAM_A<5>
MEM_CAM_A<7> MEM_CAM_A<8> MEM_CAM_A<9> MEM_CAM_A<10> MEM_CAM_A<11> MEM_CAM_A<12> MEM_CAM_A<13> MEM_CAM_A<14>
MEM_CAM_BA<0> MEM_CAM_BA<1>
MEM_CAM_DM<0> MEM_CAM_DM<1>
MEM_CAM_A<6>
MEM_CAM_BA<2>
MEM_CAM_CLK_P MEM_CAM_CLK_N
MEM_CAM_CAS_L
MEM_CAM_RAS_L MEM_CAM_WE_L
MEM_CAM_RESET_L
MEM_CAM_DQS_P<1>
MEM_CAM_DQS_P<0>
MEM_CAM_DQS_N<1>
MEM_CAM_DQS_N<0>
MEM_CAM_DQ<15>
MEM_CAM_DQ<14>
MEM_CAM_DQ<13>
MEM_CAM_DQ<12>
MEM_CAM_DQ<7> MEM_CAM_DQ<8>
MEM_CAM_DQ<11>
MEM_CAM_DQ<10>
MEM_CAM_DQ<9>
MEM_CAM_DQ<2> MEM_CAM_DQ<3> MEM_CAM_DQ<4> MEM_CAM_DQ<5> MEM_CAM_DQ<6>
MEM_CAM_DQ<1>
MEM_CAM_DQ<0>
MEM_CAM_ZQ_S2
MEM_CAM_CS_L
PP1V2_CAM_XTALPCIEVDD
GND_CAM_PVSSD
PP1V8_CAM
PP1V2_CAM
I2C_CAM_SMBDBG_CLK
CAM_XTAL_FREQ CAM_XTAL_SEL
I2C_CAM_SMBDBG_DAT
CAM_UARTCTS
CAM_UARTRXD
=PPVDDIO_S0_CAMCLK
CAM_TEST_OUT
GND_CAM_PVSSC
P1V2_CAM_SRVLXC_PHASE
P1V35_CAM_SRVLXD_PHASE
PP1V8_CAM
PP1V8_CAM
PP1V8_CAM
GND_CAM_PVSSD
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
BOM_COST_GROUP=CAMERA
CAMERA 1 OF 2
CAM_FREQ:24M
100K
5% 1/20W MF 201
2
1
R3905
CRITICAL
BCM15700A2KRFBG
FCBGA
G3
J2
R3
H3
A2
E2
A3
D2
B3
B2
C5
A5
B4
B1
C3
B5
F2
F4
F1
F3
D3
E4
E3
C2
C4
C1
L4
J3
H2
G2
H4
K2
L2
K3
R4
P1
L1
R2
J4
P2
P3
N2
P4
M2
M1
M3
N3
M4
L3
U3900
CRITICAL
BCM15700A2KRFBG
FCBGA
B12
B13
E9
R5
R1
P5
N1
M9
A14
K9
K8
K7
K6
K5
K1
J9
J8
J7
J6
J5
H9
H8
H7
H6
H5
G9
G8
G7
G6
G1
E5
D5
D1
B6
A6
A1
K12
M11
R11
B15
L9
L8
L5
L6
F9
F8
F7
F6
J11
F14
G15
F15
K14
K13
N14
M13
J15
J14
J13
H15
H14
N15
M15
M14
L15
L14
L13
L12
K15
R15
P15
P14
N13
M12
G14
D6
C8
D9
C7
C10
D7
L7
N6
N8
N7
N5
G5
N4
K4
G4
D4
A4
J1
U3900
CRITICAL
BCM15700A2KRFBG
FCBGA
A13
A12
E14
E13
D14
D13
J12
M10
C12
C13
H12
R13
E15
G12
N12
B9
C9
A8
B8
R14
B10
A10
B7
A7
P13
P6
P8
R6
R8
P7
R7
D11
D12
F12
E12
F13
C11
R9
C15
R10
D15
N9
N10
N11
P9
P10
P11
P12
R12
L10
L11
K10
K11
J10
H10
H11
G10
G11
F10
F11
E10
E11
A15
B14
C14
B11
U3900
100PF
5% 25V C0G
0201
2
1
C3901
100K
5%
1/20W
MF
201
2
1
R3991
72 37
100K
5% 1/20W MF 201
2
1
R3921
100K
5% 1/20W MF 201
2
1
R3920
51K
5% 1/20W MF 201
2
1
R3976
51K
5% 1/20W MF 201
2
1
R3975
0.1UF
BYPASS=U3900.F6::2.54MM
10% 10V X5R-CERM 0201
2
1
C3970
1000PF
BYPASS=U3900.F6::2.54MM
10% 16V X7R-1 0201
2
1
C3971
0.1UF
BYPASS=U3900.F9::2.54MM
10% 10V X5R-CERM 0201
2
1
C3972
1000PF
BYPASS=U3900.F9::2.54MM
10% 16V X7R-1 0201
2
1
C3973
0.1UF
BYPASS=U3900.L9::2.54MM
10% 10V X5R-CERM 0201
2
1
C3974
0.1UF
BYPASS=U3900.L9::2.54MM
10% 10V X5R-CERM 0201
2
1
C3975
220-OHM-1.4A
0603
21
L3904
220-OHM-1.4A
0603
21
L3903
CRITICAL
4.7UF
BYPASS=U3900.K13:K15:2.54MM
20%
6.3V X5R 402
2
1
C3913
CRITICAL
4.7UF
20%
6.3V X5R 402
2
1
C3914
CRITICAL
10UF
20%
6.3V CERM 0402
2
1
C3933
CRITICAL
10UF
20%
6.3V CERM 0402
2
1
C3931
1.0UF
20%
6.3V X5R 0201-1
2
1
C3932
37
1.0UF
20%
6.3V X5R 0201-1
2
1
C3930
0.1UF
10% 10V X5R-CERM 0201
2
1
C3927
100K
5%
1/20W
MF
201
2
1
R3990
SM
21
XW3901
SM
21
XW3900
37
1K
5%
1/20W
MF
201
2
1
R3914
1K
5%
1/20W
MF
201
2
1
R3913
240
1%
1/20W
MF
201
21
R3912
100K
5% 1/20W MF 201
2
1
R3911
NOSTUFF
100K
5% 1/20W MF 201
2
1
R3910
37
37
37
37
37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
37
37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
72 37
37
37
72 37
72 37
1000PF
BYPASS=U3900.D7::2.54MM
10% 16V X7R-1 0201
2
1
C3938
1000PF
BYPASS=U3900::3mm
10% 16V X7R-1 0201
2
1
C3936
1000PF
BYPASS=U3900.L7::2.54MM
10% 16V X7R-1 0201
2
1
C3917
1000PF
BYPASS=U3900::3mm
10% 16V X7R-1 0201
2
1
C3934
1000PF
BYPASS=U3900.J1::2.54MM
10% 16V X7R-1 0201
2
1
C3918
0.1UF
10% 10V X5R-CERM 0201
2
1
C3960
1UF
BYPASS=U3900.G15::2.54MM
10% 10V X5R 402-1
2
1
C3939
2.2UF
BYPASS=U3900.F15::2.54MM
20%
6.3V CERM 402-LF
2
1
C3941
CRITICAL
4.7UF
BYPASS=U3900::7mm
20%
6.3V X5R 402
2
1
C3942
0.1UF
BYPASS=U3900::5mm
10% 10V X5R-CERM 0201
2
1
C3940
0.1UF
BYPASS=U3900::5mm
10% 10V X5R-CERM 0201
2
1
C3935
0.1UF
BYPASS=U3900::5mm
10% 10V X5R-CERM 0201
2
1
C3937
0.1UF
BYPASS=U3900.J1::2.54MM
10% 10V X5R-CERM 0201
2
1
C3919
CRITICAL
4.7UF
PLACE_NEAR=U3900.M14:2.54MM
20%
6.3V X5R 402
2
1
C3926
CRITICAL
4.7UF
20%
6.3V X5R 402
2
1
C3928
0.1UF
BYPASS=U3900.L7::2.54MM
10% 10V X5R-CERM 0201
2
1
C3916
22NH
0402
21
L3906
CRITICAL
4.7UF
PLACE_NEAR=U3900.M13:3.2MM
20%
6.3V X5R 402
2
1
C3915
CRITICAL
4.7UF
20%
6.3V X5R 402
2
1
C3912
CRITICAL
1.0UH-1.6A-55MOHM
PLACE_NEAR=U3900.K13:4MM
1008
21
L3902
CRITICAL
1.0UH-1.6A-55MOHM
PLACE_NEAR=U3900.M13:4MM
1008
21
L3901
CAM_FREQ:25M
100K
5% 1/20W MF 201
2
1
R3904
100K
5% 1/20W MF 201
2
1
R3907
NOSTUFF
100K
5% 1/20W MF 201
2
1
R3906
37
37
37
37
37
37
19
100K
5% 1/20W MF 201
2
1
R3901
0.1UF
BYPASS=U3900.D6::2.54MM
10% 10V X5R-CERM 0201
2
1
C3951
0.1UF
BYPASS=U3900.D6::2.54MM
10% 10V X5R-CERM 0201
2
1
C3910
1.0UF
20%
6.3V X5R 0201-1
2
1
C3921
0.1UF
10% 10V X5R-CERM 0201
2
1
C3922
1.0UF
20%
6.3V X5R 0201-1
2
1
C3923
0.1UF
10% 10V X5R-CERM 0201
2
1
C3924
0.1UF
10% 10V X5R-CERM 0201
2
1
C3900
19 13
19 13
66
66
19
36
37 36
72 36
36
36
36
70
72
72
72
72
72
72
72
72
36
36
36
36
36
72 36
36
69
36
37
36
36
37 36
36
36
36
37 36
36
36
36
36
36
36
36
36 36
36
36
36
19
36
36
36
36
36
36
36
36
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
NC
NC
NC
NC
NC
NC
NC NC
NC
NC
NC
NC
SYM 2 OF 3
DDR_CS*
DDR_ZQ
DDR_DQ00
DDR_DQ01
DDR_DQ06
DDR_DQ05
DDR_DQ04
DDR_DQ03
DDR_DQ02
DDR_DQ09
DDR_DQ10
DDR_DQ11
DDR_DQ08
DDR_DQ07
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQS_N0
DDR_DQS_N1
DDR_DQS_P0
DDR_DQS_P1
DDR_RESET*
DDR_WE*
DDR_RAS*
DDR_CAS*
DDR_CK_N0
DDR_CK_P0
DDR_BA2
DDR_AD06
DDR_DM1
DDR_DM0
DDR_BA1
DDR_BA0
DDR_AD14
DDR_AD13
DDR_AD12
DDR_AD11
DDR_AD10
DDR_AD09
DDR_AD08
DDR_AD07
DDR_AD05
DDR_AD04
DDR_AD03
DDR_AD02
DDR_AD01
DDR_AD00
DDR_CKE
SYM 3 OF 3
SR_PVSSD
PMU_AVSS
PCIE_GND
MIPI_AGND
XTAL_AVSS
XTAL_AVDD1P2
VSENSE_D
VSENSE_C
VDDO18
VDDC
VDD1P8_O
VDD1P2_O
VDD_3P3A
VDD_1P35A
SR_VLXD_O
SR_VLXC_O
SR_VDD_3P3D
SR_VDD_3P3C
OTP_VDD3P3
PLL_VDD1P8
MIPI_AVDD1P8
DDR_AVDD1P8
PCIE_PVDD1P2
PCIE_VDD1P2
DDR_VREF
DDR_VDDO_CK
DDR_VDDO
DDR_VDDIO
SR_PVSSC
VSSC
SYM 1 OF 3
GPIO_05 GPIO_06 GPIO_07
TEST_MODE
UARTCTS UARTRTS
UARTRXD
TEST_OUT
UARTTXD
STRAP_XTAL_FREQ
STRAP_XTAL_SEL
DEBUG_00 DEBUG_01 DEBUG_02 DEBUG_03 DEBUG_04 DEBUG_05 DEBUG_06 DEBUG_07 DEBUG_08 DEBUG_09 DEBUG_10 DEBUG_11
DEBUG_16
DEBUG_12 DEBUG_13 DEBUG_14 DEBUG_15
GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04
SHUTDOWN*
SENSOR_WAKE*
RESET*
PWR_MODE
PCIE_RST* PCIE_WAKE*
PCIE_CLKREQ*
JTAG_SRST*
JTAG_TRST*
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
I2C_DATA_SENSOR
I2C_DATA_DBG
I2C_CLK_SENSOR
I2C_CLK_DBG
XTAL_N
XTAL_P
PCIE_TESTN
PCIE_TESTP
PCIE_TDN0
PCIE_TDP0
PCIE_REFCLKN
PCIE_REFCLKP
PCIE_RDN0
PCIE_RDP0
MIPI_DM1
MIPI_DP1
MIPI_DM0
MIPI_DP0
MIPI_CM_CLK
MIPI_CP_CLK
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
IN
IN
BI
OUT
OUT
NC
NC
NC
NC
合肥怡飞苹果维修qq:82669515 qq群: 241000
CAMERA SENSOR
S2 DRAM Parts
96.2 mA peak
77.2 mA nominal max
FROM CONNECTOR
37 OF 73
VOLTAGE=0.675V
MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1500
VOLTAGE=5V
MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1500
VOLTAGE=0.675V
MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.1500
40 OF 500
1.0.0
051-02265
MIPI_CLK_N
MIPI_DATA_N
MIPI_CLK_F_P
MIPI_DATA_F_PMIPI_DATA_CONN_P
MIPI_DATA_CONN_N
MIPI_CLK_CONN_P
MIPI_CLK_CONN_N
MIPI_DATA_P
MIPI_CLK_P
PP0V675_MEM_CAM_VREFCA
PCIE_CLK100M_CAMERA_N
PP5V_S0_ALSCAM_F =PP5V_S0_ALSCAM
PCIE_CAMERA_R2D_C_P PCIE_CAMERA_R2D_P
PCIE_CAMERA_D2R_N
PCIE_CAMERA_R2D_C_N
PCIE_CAMERA_D2R_C_N
PCIE_CLK100M_CAMERA_C_N
PP0V675_CAM_VREF
MEM_CAM_DQ<7>
MEM_CAM_DQ<6>
MEM_CAM_DQ<5>
MEM_CAM_DQ<4>
MEM_CAM_DQ<3>
MEM_CAM_DQ<2>
MEM_CAM_DQ<1>
MEM_CAM_DQ<0>
MEM_CAM_A<14>
MEM_CAM_A<2> MEM_CAM_A<3>
MEM_CAM_A<1>
MEM_CAM_A<0>
MEM_CAM_A<6>
MEM_CAM_CAS_L
MEM_CAM_RAS_L
MEM_CAM_BA<2>
MEM_CAM_BA<0> MEM_CAM_BA<1>
MEM_CAM_A<13>
MEM_CAM_A<11>
MEM_CAM_A<10>
MEM_CAM_A<8>
MEM_CAM_A<4> MEM_CAM_A<5>
MEM_CAM_CLK_P
MEM_CAM_WE_L
MEM_CAM_A<12>
MEM_CAM_DQ<8> MEM_CAM_DQ<9> MEM_CAM_DQ<10> MEM_CAM_DQ<11> MEM_CAM_DQ<12> MEM_CAM_DQ<13> MEM_CAM_DQ<14> MEM_CAM_DQ<15>
MEM_CAM_DQS_P<0>
MEM_CAM_DM<0>
MEM_CAM_DQS_N<0>
PCIE_CAMERA_R2D_N
PCIE_CAMERA_D2R_P
PCIE_CLK100M_CAMERA_C_P
MEM_CAM_DQS_P<1> MEM_CAM_DQS_N<1>
MIPI_DATA_F_N
MIPI_CLK_F_N
MEM_CAM_CS_L
MEM_CAM_CKE
MEM_CAM_ODT
MEM_CAM_CLK_N
MEM_CAM_DM<1>
MEM_CAM_RESET_L
MEM_CAM_ZQ_DDR
MEM_CAM_A<9>
MEM_CAM_A<7>
PP0V675_MEM_CAM_VREFDQ
PCIE_CLK100M_CAMERA_P
PCIE_CAMERA_D2R_C_P
PP1V35_CAM
333S00016 MICRON 20NM FOR S2 CAMERA DDR3 MEMORY333S00084 ALL
333S00016 HYNIX ALT TO MICRON FOR S2 CAMERA DDR3 MEMORY333S00030 ALL
CRITICALIC,SDRAM,25NM 4GB,DDR3L-1866,96B FBGA333S00016 1 U4000
SYNC_DATE=06/15/2015
SYNC_MASTER=PAULM
BOM_COST_GROUP=CAMERA
CAMERA 2 OF 2
15
15
36
36
72 66
72 66
72 66
72 66
7PF
+/-0.1PF 25V CERM 0201
2
1
C4086
7PF
+/-0.1PF 25V CERM 0201
2
1
C4087
7PF
+/-0.1PF 25V CERM 0201
2
1
C4082
7PF
+/-0.1PF 25V CERM 0201
2
1
C4083
7PF
+/-0.1PF 25V CERM 0201
2
1
C4084
7PF
+/-0.1PF 25V CERM 0201
2
1
C4085
7PF
+/-0.1PF 25V CERM 0201
2
1
C4080
7PF
+/-0.1PF 25V CERM 0201
2
1
C4081
27NH-3%-0.140A-2.3OHM
0201
21
L4085
27NH-3%-0.140A-2.3OHM
0201
21
L4084
27NH-3%-0.140A-2.3OHM
0201
21
L4081
27NH-3%-0.140A-2.3OHM
0201
21
L4080
3PF
+/-0.1PF 25V C0G 0201
2
1
C4012
3PF
+/-0.1PF 25V C0G 0201
2
1
C4014
3PF
+/-0.1PF 25V C0G 0201
2
1
C4015
3PF
+/-0.1PF 25V C0G 0201
2
1
C4016
OMIT_TABLE
CRITICAL
4GB-DDR3L-1866-256MX16
MT41K256M16LY-107-N
FBGA
L8
L3
G9
G1
F9
E8
E2
D8
D1
B9
B1
T9
T1
P9
P1
M9
M1
J8
J2
G8
E1
B3
A9
H1
M8
H9
H2
F1
E9
D2
C9
C1
A8
A1
R9
R1
N9
N1
K8
K2
G7
D9
B2
B7
C7
D3
T2
J3
K1
M7
L9
L1
J9
J1
G3
F3
E7
A3
B8
A2
A7
C2
C8
C3
D7
H7
G2
H8
H3
F8
F2
F7
E3
L2
K9
K7
J7
K3
M3
N8
M2
T7
T3
N7
R7
L7
R3
T8
R2
R8
P2
P8
N2
P3
P7
N3
U4000
12PF
5% 25V CERM 0201
2
1
C4017
12PF
5% 25V CERM 0201
2
1
C4018
12PF
5% 25V CERM 0201
2
1
C4019
12PF
5% 25V CERM 0201
2
1
C4020
CRITICAL
2.4GHZ
PLACE_NEAR=J8500.33:2.54MM
0.65X0.5X0.3MM-SM
4
32
1
L4007
CRITICAL
2.4GHZ
PLACE_NEAR=J8500.37:2.54MM
0.65X0.5X0.3MM-SM
4
32
1
L4009
72 36
0.1UF
10% 16V X5R-CERM 0201
21
C4062
0.1UF
10% 16V X5R-CERM 0201
21
C4061
240
1% 1/20W MF 201
2
1
R4004
NOSTUFF
1K
5%
1/20W
MF
201
2
1
R4003
1K
5%
1/20W
MF
201
2
1
R4002
36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
36
36
84.5
1% 1/20W MF 201
2
1
R4020
36
36
36
36
36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
0.1UF
10% 10V
X5R-CERM
0201
2
1
C4010
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
72 36
0.1UF
10% 10V X5R-CERM 0201
2
1
C4011
72 36
72 36
1K
1%
1/20W
MF
201
2
1
R4023
1K
1%
1/20W
MF
201
2
1
R4022
CRITICAL
10UF
BYPASS=U4000.A1::4mm
20%
6.3V CERM 0402
2
1
C4002
CRITICAL
10UF
BYPASS=U4000.B2::4mm
20%
6.3V CERM 0402
2
1
C4003
CRITICAL
FERR-120-OHM-1.5A
0402A
2 1
L4010
36
36
36
36
0.1UF
10% 10V X5R-CERM 0201
2
1
C4005
0.1UF
10% 16V
X7R-CERM
0402
2
1
C4013
0.1UF
BYPASS=U4000.R9::4mm
10% 10V X5R-CERM 0201
2
1
C4007
0.1UF
10% 10V X5R-CERM 0201
2
1
C4009
CRITICAL
2.2UF
BYPASS=U4000.D2::4mm
20% 10V X5R-CERM 402
2
1
C4006
CRITICAL
2.2UF
BYPASS=U4000.K2::4mm
20% 10V X5R-CERM 402
2
1
C4008
0.47UF
BYPASS=U4000.H9::4mm
20% 4V CERM-X5R-1 201
2
1
C4004
0
5%
1/20W
MF0201
21
R4000
36
36
15
15
0.1UF
10% 16V X5R-CERM 0201
21
C4030
0.1UF
10% 16V X5R-CERM 0201
21
C4031
0.1UF
10% 16V X5R-CERM 0201
21
C4032
0.1UF
10% 16V X5R-CERM 0201
21
C4033
15
15
36
36
72 66 69
36
36
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
TABLE_ALT_ITEM
TABLE_ALT_ITEM
IN
IN
OUT
OUT
IN
IN
IN
IN
NC
UDQS
UDQS*
LDQS*
LDQS
DQ15
DQ14
DQ13
DQ10
DQ12
DQ11
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
UDM
LDM
A14
VDD
A2
A3
A1
A0
A6
ODT
RESET*
VSSQ VSS
CAS*
RAS*
BA2
BA0
BA1
ZQ
CS*
CKE
A13
A11
A10/AP
A8
A4
A5
A9
CK
VREFCA
VREFDQ
CK*
WE*
A12/BC*
A7
VDDQ
SYM_VER-1
SYM_VER-1
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
NC
NC
NC
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
CS ISOLATION
TPAD CONNECTOR
516S00187, MATE WITH 516S00188
518S0884
COWLING BOSES
860-00381
ESD DIODES
377S0184
POR KEYBOARD CONNECTOR
ACTUATOR GND ACTUATOR GND
FAN SUPPORT
FAN GND
KEYBOARD CONNECTOR
1.0.0
051-02265
38 OF 73
48 OF 500
VOLTAGE=13.1V
TPAD_VIBE_L
SMC_LSOC_RST
FAN_LT_PWM
=PP3V3_G3H_KBD
=PP3V3_S4_KBD
=PP5V_S0_KBD
TPAD_SPI_INT_L
KBD_BLC_GSLAT
LID_OPEN
KBD_BLC_GSSCK
TPAD_SPI_INT_L
KBD_INT_L KBD_I2C_SDA
TPAD_SPI_MOSI TPAD_SPI_CS_CONN_L TPAD_SPI_MISO
=PP3V3_S4_TPAD
TPAD_VIBE_L
KBD_BLC_GSSOUT
KBD_I2C_SCL
TPAD_SPI_IF_EN
=PP5V_S4_TPAD
ACT_THERM_TRIP_L
=I2C_TPAD_SCL
TPAD_SMC_WAKE_L
KBD_BLC_GSSIN
=PP5V_S0_FAN
TPAD_SPI_MOSI
ACT_THERM_TRIP_L
TPAD_SPI_CLK
TPAD_SPI_MISO
FAN_LT_TACH
FAN_LT_PWM
KBD_I2C_SCL
KBD_I2C_SDA
TPAD_SPI_CS_CONN_L
KBD_INT_L
SMC_LSOC_RST
FAN_LT_PWM
=PPBUS_S4_TPAD
LID_OPEN
=I2C_TPAD_SDA
TPAD_SMC_WAKE_L
TPAD_SPI_IF_EN
=I2C_TPAD_SCL
SMC_VIBE_L
SMC_FAN_0_TACH FAN_LT_TACH
SMC_FAN_0_CTL
PP3V3_S0
KBD_I2C_SDA
FAN_LT_TACH
KBD_INT_L
KBD_BLC_GSSIN
SMC_ONOFF_L
KBD_BLC_GSLAT KBD_BLC_GSSCK KBD_BLC_GSSOUT
KBD_I2C_SCL
KBD_BLC_XBLANK
=PP3V3_S0_TPAD
=PP3V3_S4_TPAD
=I2C_TPAD_SDA
TPAD_SPI_CS_L
TPAD_SPI_CS_CONN_L
=PP5V_S0_FAN
PPVIN_S4_TPAD_FUSE
=PP3V3_S0_TPAD
PP5V_S4_TPAD_CONN
TPAD_SPI_CLK
KBD_BLC_XBLANK
P1:KEYBOARD & TRACKPAD CONN
BOM_COST_GROUP=KEYBOARD
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
0201
5.5V-0.28PF
CRITICAL
2
1
DZ4821
0201
C0G
25V
+/-0.1PF
3PF
2
1
C4802
0201
MF
1/20W
5%
0
NOSTUFF
21
R4830
16
SOT891
74LVC1G08
CRITICAL
4
6
5 3
1
2
U4830
69 38
0201
X5R-CERM
10V
10%
0.1UF
2
1
C4830
41 38
41 38
72 39 38
72 38 16
72 38 16
72 38 16
42 38
42 38
0201
C0G
25V
+/-0.1PF
3PF
2
1
C4878
0201
CERM
25V
5%
12PF
2
1
C4877
0201
C0G
25V
+/-0.1PF
3PF
2
1
C4876
0201
CERM
25V
5%
12PF
2
1
C4875
0201
CERM
25V
5%
12PF
2
1
C4873
0201
C0G
25V
+/-0.1PF
3PF
2
1
C4874
0201
CERM
25V
5%
12PF
2
1
C4871
0201
C0G
25V
+/-0.1PF
3PF
2
1
C4872
39
0201
MF
1/20W
5%
0
TPAD_VIBE:GND
2
1
R4821
0201
MF
1/20W
5%
0
TPAD_VIBE:SMC
21
R4820
3.5OD1.85ID-1.41H-SM
1
SH4802
3.5OD1.85ID-1.41H-SM
1
SH4801
72 38 16
72 38 16
1812-1
2.6A-16V-0.05OHM
CRITICAL
21
F4800
F-ST-SM
DF40C-50DS-0.4V-51
CRITICAL
50 49
48 47
46 45
44 43
42 41
40 39
38 37
36 35
34 33
32 31
30 29
28 27
26 25
24 23
22 21
20 19
18 17
16 15
14 13
12 11
10 9
8 7
6 5
4 3
2 1
J4801
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4809
0201
5.5V-0.28PF
CRITICAL
21
DZ4807
0201
5.5V-0.28PF
CRITICAL
21
DZ4805
0201
5.5V-0.28PF
CRITICAL
21
DZ4801
0201
5.5V-0.28PF
CRITICAL
21
DZ4803
0201
5.5V-0.28PF
CRITICAL
21
DZ4804
0201
5.5V-0.28PF
CRITICAL
21
DZ4802
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4818
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4816
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4814
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4819
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4817
0201
5.5V-0.28PF
CRITICAL
NOSTUFF
21
DZ4815
402
X5R
25V
10%
0.1UF
2
1
C4800
0402A
FERR-120-OHM-1.5A
CRITICAL
21
L4800
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4813
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4811
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4812
0201
5.5V-0.28PF
CRITICALNOSTUFF
21
DZ4810
0402
X7R-CERM
16V
10%
0.1UF
2
1
C4870
72 68 40 39
39
39
201
MF
1/20W
5%
100K
2
1
R4801
DFN1006H4-3
DMN32D2LFB4
2
1
3
Q4800
201
MF
1/20W
5%
47K
21
R4805
201
MF
1/20W
5%
47K
2
1
R4800
F-RT-SM-1
TF13BS-20S-0.4SH
CRITICAL
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
21
22
J4810
201
MF
1/20W
5%
100K
2
1
R4870
72 41 38
72 38
72 38
69
69
69
72
38 16
72 38
72 38
72 38
72 38
72 38
69 38
72 38
72 38
72 38
69
72 38
69 38
72 38 16
72 39 38
72 38 16
72
38
16
72 38
72 38
72 38
72 38
72 38
72 38
72 41 38
72 38
69
41 38
42 38
41 38
72 38 16
42 38
72 38
69 64 63 60 59 54 49 46 45 42
72 38
72 38
72 38
72 38
72 38
72 38
72 38
72 38
72 38
69 38
72 38
69 38
72
69 38
72 38
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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REVISION
DRAWING NUMBER SIZE
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R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
08
NC
IN
NC
IN
OUT
BI
IN
IN
IN
BI
IN
IN
OUT
OUTOUT
IN
OUT
GS
SYM_VER_3
D
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
(IPU)
(OD)
(OD)
(IPD when sampling)
NOTE:
(OD)
(OD)
(OD)
(OD)
(OD)
NOTE:
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(IPU)
(IPD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(IPD)
SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.
39 OF 73
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
NO_TEST=1
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
NO_TEST=1
NO_TEST=1
50 OF 500
1.0.0
051-02265
SMC_FAN_1_CTL
SMC_CHGR_INT_L
PP3V3_S5_SMC_VDDA
=PP3V3_S5_SMC
GND_SMC_AVSS
BUF_SMC_RESET_L
SMC_WIFI_EVENT_L SMC_WAKE_L NC_SMC_HIB_L
SMC_TDI
SMC_ADC13
PM_THRMTRIP_L
SMC_DEBUGPRT_RX_L
SPI_SMC_CS_L
SPI_SMC_MOSI
SMC_DEBUGPRT_TX_L
SMC_PROCHOT
SPI_DESCRIPTOR_OVERRIDE_L CPU_CATERR_L
SMBUS_SMC_3_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMC_RUNTIME_SCI_L
LPC_CLKRUN_L
SMC_LRESET_L
LPC_AD<3>
LPC_AD<2>
LPC_SERIRQ
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_2_SDA
SMBUS_SMC_3_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_4_G3_SDA
PM_RSMRST_L
SMC_TCON_BKLT_PWM
SMC_CLK12M_EN
PP3V0_S5_AVREF_SMC
PP1V2_S5_SMC_VDDC
SMC_VIBE_L SMC_LID_LEFT
SMC_PCH_SUSWARN_L SMC_USBC_INT_L SMC_BC_ACOK
PM_SLP_S4_L PM_SLP_S5_L SMC_ONOFF_L
SMC_GFX_SELF_THROTTLE
SMC_FAN_1_TACH
SMC_ADC9
SMC_ADC4
SMC_ADC3
SMC_ADC2
SMC_ADC1
ACT_THERM_TRIP_L
SYS_ONEWIRE
SMC_PCH_SUSACK_L
SMC_DP_HPD_L
SMBUS_SMC_2_SCL
SMC_LID_RIGHT
SMC_PECI_L
SMC_SENSOR_PWR_EN
SMC_ADC8
PM_BATLOW_L
SMC_ADC19
SMC_ADC6
SMC_ADC14
SMC_ADC16
SMC_ADC20
LPC_AD<1>
SMC_ADC23
SMC_VCCIO_CPU_DIV2
SMC_ADC0
SMC_ADC7
SMC_TCK
SMC_TDO
SMC_ADC10
SMC_ADC12
SMC_ADC11
SMC_ADC15
SMC_MIKEYBUS_SEL_LEFT
SMC_ADC22
SMC_ADC18
SMC_ADC5
LPC_AD<0>
LPC_FRAME_L
SMC_WAKE_SCI_L
SMC_ADC17
CPU_PROCHOT_L
SPI_SMC_MISO
SMC_DELAYED_PWRGD
PM_DSW_PWRGD
SMC_OOB1_R2D_L
SMC_PME_S4_WAKE_L SMC_PME_S4_DARK_L SMC_PMIC_INT_L
PM_SLP_S0_L PM_SLP_S3_L
SMC_PM_G2_EN
SMC_THRMTRIP
SMC_ADC21
SMC_OOB1_D2R_L
SMC_SOC_POR
CPU_PECI_R
SMC_SENSOR_ALERT_L
SMC_ADAPTER_EN
PM_PWRBTN_L PM_SYSRST_L
NC_SMC_XOSC1
NC_SMC_OSC1
SYSCLK_CLK12M_SMC
SMC_CLK32K
SMC_TOPBLK_SWP_L
SMC_RX_L SMC_TX_L
SMC_WIFI_PWR_EN
SMC_BT_PWR_EN
SMBUS_SMC_5_G3_SDA
SMC_FAN_0_CTL
ALL_SYS_PWRGD
S5_PWRGD PM_PCH_SYS_PWROK
SMC_CBC_ON SMC_GFX_OVERTEMP
SPI_SMC_CLK
SMC_GFX_THROTTLE_L
SMC_TMS
SMC_DEV_SUPPLY_R_L
SMC_FAN_0_TACH
SMBUS_SMC_4_G3_SCL
SMBUS_SMC_1_S0_SCL
LPC_PWRDWN_L
LPC_CLK24M_SMC
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
SMC
41
40 35 34
38
41
40
40
41
41 35 34
41
66 41
BGA
TM4EA231H6ZXRI
CRITICAL
OMIT_TABLE
K12
K11
M13
E1
E2
J13
J9
J1
H9
D7
F3
H7
H6
G8
G7
G6
F8
F7
F6
E7
E6
K13
F11
A11 C10
B10
C9
B9
F12
F13
B7
L13
F4
F2
K9
J8
J7
J6
J5
H8
H5
G9
G5
F9
F5
E10
E9
E8
E5
D9
D6
D5
A10
U5000
BGA
TM4EA231H6ZXRI
CRITICAL
OMIT_TABLE
N7
M7
L7
N6
M6
F1
D1
D2
L6
A7
K7
J12
J11
K6
H12
J10
L11
N13
M12
L12
A9
K4
B5
A5
H11
H13
H10
G10
G13
G11
G12
F10
E13
E12
C13
C12
D10
B13
C11
A13
B12
A12
B11
H2
H1
H3
H4
C6
C7
B6
A6
C8
B8
A8
D8
J4
J2
J3
K1
K2
K3
L1
L2
M5
N5
N8
M8
L8
L9
M9
N9
K8
N10
M10
K10
M11
N12
N11
L10
C4
C5
A3
B3
G4
G3
G2
G1
C2
C3
A1
A2
D4
D3
C1
B1
M1
N1
M2
M3
E4
E3
B4
A4
D12
D13
D11
E11
L5
N4
M4
L4
N3
N2
K5
L3
U5000
19 18
41
40 6
40
41 40
0201-1
X5R
6.3V
20%
BYPASS=U5000.H9::5MM
1.0UF
2
1
C5017
0201-1
X5R
6.3V
20%
BYPASS=U5000.J9::5MM
1.0UF
2
1
C5014
0201
X5R-CERM
10V
10%
BYPASS=U5000.J1::5MM
0.1UF
2
1
C5012
0201
X5R-CERM
10V
10%
BYPASS=U5000.J13::5MM
0.1UF
2
1
C5011
41
0201
X7R-CERM
10V
10%
BYPASS=U5000.E1:F2:1MM
0.01UF
2
1
C5020
0201-1
X5R
6.3V
20%
BYPASS=U5000.E1:F2:1MM
1.0UF
2
1
C5021
72 38
41
0201-1
X5R
6.3V
20%
BYPASS=U5000.E6::5MM
1.0UF
2
1
C5002
0201
X5R-CERM
10V
10%
0.1UF
2
1
C5001
0201-1
X5R
6.3V
20%
BYPASS=U5000.D7::5MM
1.0UF
2
1
C5010
0201
X5R-CERM
10V
10%
BYPASS=U5000.J9::5MM
0.1UF
2
1
C5013
0201
X5R-CERM
10V
10%
BYPASS=U5000.D7::5MM
0.1UF
2
1
C5015
0201
X5R-CERM
10V
10%
BYPASS=U5000.H9::5MM
0.1UF
2
1
C5016
41
35 34
68 19 6
60 59 14
41
67
67
68 54 40 6
0402
30-OHM-1.7A
21
L5001
18
60
41
53 41
41
18
28 14
60 40
41 40
72 68 40 38
72 60 14
72 68 60 14
72 66 60 59 26 14
72 60 14
40
42 28
72 41 40
41
38
38
41
40
41
41
40
40
14
40
68 17 14
72 41 17
40
72 60
41
53 41
41
41
41
41
68 60 17 14
72 40 28
72 40 28
40
40
68 14
60 40
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
42
42
42
42
42
42
42
42
42
42
42
42
15
13
13
13
19
13
13
13
13
13
13
0201
X5R-CERM
10V
10%
BYPASS=U5000.G8::5MM
0.1UF
2
1
C5007
0201
X5R-CERM
10V
10%
BYPASS=U5000.E6::5MM
0.1UF
2
1
C5003
0201
X5R-CERM
10V
10%
BYPASS=U5000.F6::5MM
0.1UF
2
1
C5004
0201
X5R-CERM
10V
10%
BYPASS=U5000.H6::5MM
0.1UF
2
1
C5008
0201
X5R-CERM
10V
10%
BYPASS=U5000.H7::5MM
0.1UF
2
1
C5009
0201
X5R-CERM
10V
10%
BYPASS=U5000.F8::5MM
0.1UF
2
1
C5005
0201
X5R-CERM
10V
10%
BYPASS=U5000.G6::5MM
0.1UF
2
1
C5006
201
MF
1/20W
5%
1M
2
1
R5002
40
SM
PLACE_NEAR=U5000.A10:4MM
2 1
XW5000
69 40
45 44 43 41 40
72 40
40
72 47 40 28
72 40
72 47 40 28
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
BI
IN
OUT
OUT
IN
IN
OUT
IN
NC
IN
SYM 2 OF 2
VREFA-
GNDA
GNDA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDA
VDDC
VDDC
XOSC1
XOSC0
OSC0
OSC1
VBAT
VDDC
VDDC
VDDC
RST*
WAKE*
HIB*
PK4
NC
VREFA+
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
PC0/SWCLK/TCK
PC1/SWDIO/TMS
PC3/SWO/TDO
PC2/TDI
SYM 1 OF 2
PL3
PM2
PM0
PM1
PG0
PA2/SSI0CLK
PJ7
PH2
PN7
PJ6
PN4
PN5
PH3
PN2
PK7
PM7
PM6
PK6
PN3
PN0
PK5
PL1
PL0
PM5
PL4
PL5
PM4
PB2/I2C0SCL
PB3/I2C0SDA
PA6
PA7
PF6
PF7
PG1
PG2
PG3
PG7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PQ0
PQ1
PQ2
PQ3
PQ4
PQ5
PQ6
PQ7
PA0/U0RX
PA1/U0TX
PL7
PL6
PE2
PE1
PD6
PD5
PD4
PE5
PE4
PB4
PD2
PD0
PK0
PK1
PK2
PA3/SSI0FSS
PA4/SSI0RX
PA5/SSI0TX
PF0
PF1
PF2
PF3
PF4
PF5
PG4
PG5
PH0
PH1
PH4
PH5
PH6
PH7
PJ0
PJ1
PJ2
PJ3
PM3
PG6
PB5
PD3
PD1
PB7
PB6
PK3
PE7
PE6
PN1
PC7
PB1
PB0
PJ4
PJ5
PC5
PC4
PC6
PD7
PE0
PE3
PL2
PN6
IN
OUT
IN
IN
IN
BI
BI
OUT
OUT
OUT
IN
IN
BI
OUT
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
IN
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
BI
IN
IN
IN
BI
BI
BI
BI
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
To SMC
PROCHOT/THRMTRIP Support
From SMC
PECI Support
From/To CPU/PCH
Top-Block Swap
SMC AVREF Supply
Place near CPU
40 OF 73
VOLTAGE=0V
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1500
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1500
51 OF 500
1.0.0
051-02265
=PP3V3R1V8_S0_PCH_VCCPGPPB
=PP3V3_S0_SMC
SMC_PME_S4_DARK_L
SMC_ONOFF_L
SMC_DEBUGPRT_TX_L
SMC_TDO
SMC_TCK
SMC_THRMTRIP
SMC_VCCIO_CPU_DIV2
MAKE_BASE=TRUE
SMC_BC_ACOK
=PP1V_S0_SMC_VCCST
SMC_THRMTRIP
PM_THRMTRIP_L
CPU_PROCHOT_L SMC_PROCHOT_L
SMC_PROCHOT
SMC_PECI_L
CPU_PECI
SMC_TOPBLK_SWP_L
PM_CLK32K_SUSCLK_R
PCH_STRP_TOPBLK_SWP_L
SMC_WIFI_EVENT_L
SMC_SENSOR_ALERT_L
SMC_DEBUGPRT_RX_L
SMC_TX_L
SMC_TDI
SMC_BC_ACOK
=PP1V_S0_SMC_VCCST
SMC_PMIC_INT_L
=PPVIN_S5_SMCVREF
GND_SMC_AVSS
=CHGR_ACOK
SMC_DELAYED_PWRGD
SMC_ADAPTER_EN
SMC_TMS
SMC_RX_L
SMC_PME_S4_WAKE_L
PP3V0_S5_AVREF_SMC
SMC_THRMTRIP_L
SMC_CLK32K
=PP3V3_S5_SMC =PP3V3_S4_SMC
SMC_PM_G2_EN SMC_PROCHOT
CPU_PECI_R
SMC Shared Support
BOM_COST_GROUP=SMC
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
201MF1/20W5%
100K
21
R5199
201MF1/20W5%
100K
21
R5198
13
201
MF
1/20W
5%
1K
2
1
R5182
201
MF
1/20W
5%
1K
21
R5183
39
0201
X5R-CERM
10V
10%
0.1UF
2
1
C5167
0402
CERM
6.3V
20%
10UF
CRITICAL
2
1
C5166
QFN
REF3330-COMBO
CRITICAL
8
7
6
3
2
1
5
4
U5165
0201-1
X5R
6.3V
20%
1.0UF
2
1
C5165
201MF1/20W5%
10K
21
R5186
201MF1/20W5%
100K
21
R5191
201MF1/20W5%
100K
21
R5185
201MF1/20W5%
100K
21
R5166
39 6
201
MF
1/20W
1%
PLACE_NEAR=Q5159.3:5MM
100
21
R5159
68 54 39 6
201
MF
1/20W
1%
PLACE_NEAR=Q5159.6:5MM
100
21
R5158
SOT563
DMN5L06VK-7
1
2
6
Q5159
SOT563
DMN5L06VK-7
4
5
3
Q5159
201MF1/20W5%
100K
21
R5169
201MF1/20W5%
100K
21
R5168
0201
C0G
25V
5%
PLACE_NEAR=Q5150.2:5MM
47PF
NOSTUFF
2
1
C5134
201MF1/20W5%
10K
21
R5172
DFN1006H4-3
DMN32D2LFB4
CRITICAL
2
1
3
Q5150
201
MF
1/20W
5%
43
21
R5134
39 6
201MF1/20W5%
100K
21
R5167
201
MF
1/20W
5%
330
2
1
R5151
39
201
MF
1/20W
1%
100K
2
1
R5196
201
MF
1/20W
1%
100K
2
1
R5197
201MF1/20W5%
20K
21
R5176
201MF1/20W5%
20K
21
R5175
39
201
MF
1/20W
5%
22
21
R5112
15
201MF1/20W5%
100K
21
R5187
40 39
40 39
201MF1/20W5%
10K
21
R5180
201MF1/20W5%
10K
21
R5179
201MF1/20W5%
10K
21
R5178
201MF1/20W5%
10K
21
R5177
201MF1/20W5%
100K
21
R5174
201MF1/20W5%
10K
21
R5173
201MF1/20W5%
10K
21
R5170
69
69
41 39
72 68 39 38
72 39 28
72 39
72 47
39 28
40 39
39
40 39
69 40
39 35 34
41 39
72 39 28
39
72 39
40 39
69 40
60 39
69
45 44 43 41 39
53
39
39
72 47 39 28
39
72 41 39
39
69 39
69
60 39
40 39
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUTIN
NC NC NC NC NC
NC4
NC2
NC3
NC0
NC1
IN OUT
GND
OUT
BI
GS
D
VER 3
GS
D
VER 3
D
SG
SYM_VER_2
OUT BI
IN
OUTIN
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
OR gate ensures that both sensors detect that the lid is closed.
S4 SMC Wake Sources
RIGHT SENSOR IS ON AUDIO FLEX.
CLAMSHELL CLOSED = LOW
(FROM KEYBOARD)
Thermal Alerts
This prevents a a stray magnet from tripping the detect.
CLAMSHELL OPEN = HIGH
(TO CHARGER)
SMC ANALOG INPUTS
(INV)
FOOTPRINT APN: 998-05495
LAST CHANGE: Thu Aug 4 21:00:42 2016
DESIGN: X502/MLB_CATZ
Magnet present = Clamshell closed = low
41 OF 73
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
52 OF 500
1.0.0
051-02265
MAKE_BASE=TRUE
SMC_SSD_ISENSE
MAKE_BASE=TRUE
NC_SPI_SMC_CLK
MAKE_BASE=TRUE
NC_SMC_MIKEYBUS_SEL_LEFT
SMC_TCON_BKLT_PWM
PBUSVSENSE_EN
SMC_LSOC_RST
SMC_LID_RIGHT
MAKE_BASE=TRUE
SMC_TBT_ISENSE
MAKE_BASE=TRUE
SMC_3V3S5_ISENSE
MAKE_BASE=TRUE
SMC_5VS4_ISENSE
MAKE_BASE=TRUE
SMC_SA_IMON_ISENSE
MAKE_BASE=TRUE
SMC_LCDBKLT_ISENSE
MAKE_BASE=TRUE
SMC_3V3WLS_ISENSE
MAKE_BASE=TRUE
SMC_3V3LCD_ISENSE
MAKE_BASE=TRUE
SMC_GT_IMON_ISENSE
MAKE_BASE=TRUE
SMC_CPU_IMON_ISENSE
MAKE_BASE=TRUE
SMC_1V2S3_ISENSE
MAKE_BASE=TRUE
SMC_3V3SSD_ISENSE
MAKE_BASE=TRUE
SMC_SA_ISENSE
MAKE_BASE=TRUE
NC_SMC_GFX_OVERTEMP
MAKE_BASE=TRUE
SMC_SENSOR_PWR_EN
MAKE_BASE=TRUE
NC_SYS_ONEWIRE
MAKE_BASE=TRUE
NC_SPI_SMC_CS_L
MAKE_BASE=TRUE
NC_SMC_GFX_SELF_THROTTLE
MAKE_BASE=TRUE
NC_SMC_SOC_POR
TBT_WAKE_L
MAKE_BASE=TRUE
NC_SPI_SMC_MOSI
TPAD_SMC_WAKE_L
PCH_SUSWARN_L
MAKE_BASE=TRUE
SMC_PCH_SUSWARN_L
HALL_SENSOR_RIGHT
SMC_LID_LEFT_R
PP3V3_G3H
SMC_RST_BTN_L
MAKE_BASE=TRUE
NC_SMC_GFX_THROTTLE_L
SMC_RST_IN
HALL_SENSOR_LEFT
LID_OPEN_R
MAKE_BASE=TRUE
PD_SMC_CBC_ON
LID_OPEN
MAKE_BASE=TRUE
NC_SPI_SMC_MISO
PP3V3_S4
CPUTHMSNS_ALERT_L
MAKE_BASE=TRUE
SMC_CPU_HI_ISENSE
TCON_BKLT_PWM
PP3V3_G3H
HALL_SENSOR_LEFT
SMC_LID_LEFT
SMC_CHGR_INT_L
SMC_DP_HPD_L
SMC_CBC_ON
SMC_SENSOR_PWR_EN
SMC_ADC6
SMC_ADC9
SMC_ADC12
SMC_ADC10
MAKE_BASE=TRUE
SMC_PCH_SUSACK_L PCH_SUSACK_L
SPI_SMC_MISO
SMC_SENSOR_ALERT_L
SMC_ADC16
SMC_ADC7
SMC_ADC5
SMC_ADC4
SMC_ADC2
SMC_ADC1
SMC_ADC3
SMC_ADC0
SMC_ADC11
SMC_ADC8
MAKE_BASE=TRUE
SMC_CPU_VSENSE
SMC_ADC20
SMC_ADC19
SMC_ADC18
SMC_ADC17
SMC_ADC22
DCINVSENSE_EN
PCH_PWRBTN_L
MAKE_BASE=TRUE
PM_PWRBTN_L
BT_WAKE_L
=UPC_WAKE_L
SMC_ADC21
SMC_GFX_OVERTEMP
SPI_SMC_CS_L
SPI_SMC_CLK
GND_SMC_AVSS
BUF_SMC_RESET_L
SMC_GFX_SELF_THROTTLE
SPI_SMC_MOSI
SMC_MIKEYBUS_SEL_LEFT
SYS_ONEWIRE
SMC_ADC23
MAKE_BASE=TRUE
SMC_PME_S4_DARK_L
MAKE_BASE=TRUE
SMC_PME_S4_WAKE_L
SMC_ADC13 SMC_ADC14 SMC_ADC15
SMC_GFX_THROTTLE_L
SMC_FAN_1_CTL
SMC_FAN_1_TACH
SMC_SOC_POR
MAKE_BASE=TRUE
SMC_DCIN_ISENSE
MAKE_BASE=TRUE
SMC_TPAD_ISENSE
MAKE_BASE=TRUE
SMC_GT_VSENSE
MAKE_BASE=TRUE
SMC_BMON_ISENSE
MAKE_BASE=TRUE
SMC_DCIN_VSENSE
PP3V3_G3H
PP3V3_G3H
SMC_DEV_SUPPLY_LSMC_DEV_SUPPLY_R_L
SMC_WIFI_PWR_EN
MAKE_BASE=TRUE
NC_SMC_FAN_1_TACH
MAKE_BASE=TRUE
NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
SMC_1VS5G_ISENSE
MAKE_BASE=TRUE
SMC_GT_ISENSE
MAKE_BASE=TRUE
SMC_CPU_ISENSE
MAKE_BASE=TRUE
SMC_PBUS_VSENSE
PP3V3_G3H
SYNC_MASTER=PAULM
BOM_COST_GROUP=SMC
SMC Project Support
SYNC_DATE=06/15/2015
SUBASSY (T&R) PCBA,HES INTERPOSER 45,X502 J52501677-05143 CRITICAL
39 72 66
0201
X5R-CERM
10V
10%
0.1UF
NOSTUFF
2
1
C5234
0201
MF
1/20W
5%
0
21
R5233
201
MF
1/20W
5%
1K
21
R5297
39
0201
MF
1/20W
5%
0
NOSTUFF
2
1
R5259
0201
MF
1/20W
5%
0
21
R5258
201
MF
1/20W
5%
10K
21
R5252
201
MF
1/20W
5%
10K
21
R5257
39
201
MF
1/20W
5%
1M
1
2
R5253
SM
AMR-MLB-45DEG-X502
OMIT_TABLE
8
7
6
5 4
3
2
1
J5250
39
0201
X7R
25V
10%
1000PF
NOSTUFF
2
1
C5270
45
26
201
MF
1/20W
5%
100K
DEV_RST_BUTTONS:YES
2
1
R5276
72 38
68
0201
MF
1/20W
5%
0
DEV_RST_BUTTONS:NO
21
R5275
0201
X5R-CERM
10V
10%
0.1UF
DEV_RST_BUTTONS:YES
2
1
C5274
53
SOT886
74AUP1T97GM
DEV_RST_BUTTONS:YES
4
561
3
2
U5274
201
MF
1/20W
5%
100K
DEV_RST_BUTTONS:YES
2
1
R5274
30 29
39
39
39
39
39
39
44
44
44
43
44
44
45
44
45
72 40 39
45
45
44
45
45
45
45
43
43
43
43
43
43
43
201
MF
1/20W
5%
100K
1
2
R5299
201MF1/20W5%
100K
NOSTUFF
21
R5298
39
39
39
39
39
201MF1/20W5%
100K
21
R5296
72 39 17 14
38
SOT891
74LVC1G32
4
6
5 3
1
2
U5255
201
MF
1/20W
5%
1M
2
1
R5254
38
201
MF
1/20W
5%
10K
21
R5255
72 51
0201
X5R-CERM
10V
10%
0.1UF
2
1
C5255
0201
X7R
25V
10%
1000PF
2
1
C5251
43
43
41 39
34 40 39
46
201MF1/20W5%
20K
NOSTUFF
21
R5201
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
0201
MF
1/20W
5%
0
21
R5230
14
14
0201
MF
1/20W
5%
0
21
R5231
39
39
201MF1/20W5%
10K
NOSTUFF
21
R5294
201MF1/20W5%
10K
NOSTUFF
21
R5295
40 39
201
MF
1/20W
5%
100
CPUTHRM_ALRT:SMC
21
R5214
72 69 68
60 53 52 51 47 42 41 28 19
41
72 69 67 64 63 45 44 43
72 69
68 60 53 52 51 47 42 41 28 19
41
53 39
39
53 39
41 39
45 44 43 40 39
66 39
72 69
68 60 53 52 51 47 42 41 28 19
72 69
68 60 53 52 51 47 42 41 28 19
72
39
39 35 34
72 69
68 60 53 52 51 47 42 41 28 19
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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DRAWING NUMBER SIZE
D
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SHEET
PAGE TITLE
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PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUTIN
OUT
OUT
NC
NC
NC
NC
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN OUT
IN
NC
OUT
IN
NC
OUT
OUT
IN
IN OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
SKYLAKE PCH S0 "SMBUS 0" CONNECTIONS SMC SMBus "5" G3H Connections
(MASTER)
U0500
SKYLAKE PCH
USB-C PORT CONTROLLER XB
SMC SMBus "2" S3 Connections
LYNX POINT LP
J8300
TMP513: U5870
U5000
SMC SMBus "3" S0 Connections
SMC
CD3215A (ACE) - U3100
USB-C PORT CONTROLLER XA
SMC
U7600
BANJO PMIC
(WRITE: 0X__ READ: 0X__)
SMC
U5000
J4802
(Write: 0x90 Read: 0x91)
Trackpad
(Write: 0x12 Read: 0x13)
(See Table)
Battery
Battery Charger
J7050
U5000
(MASTER)
LYNX POINT LP S0 "SMLink 0" Connections
(MASTER)
LYNX POINT LP
(MASTER)
(Write: 0x88 Read: 0x89)
U0500
U0500
U5000
SMC
Battery Manager - (Write: 0x16 Read: 0x17)
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
Internal DP
(MASTER)
(MASTER)
(WRITE: 0X__ READ: 0X__)
(WRITE: 0X__ READ: 0X__)
LYNX POINT LP S0 "SMLink 1" Connections
SMLink 1 is slave port to access PCH.
SMC SMBUS "4" G3H CONNECTIONS
CD3215A (ACE) - U3200
(Write: 0x72 Read 0x73)
(Write: 0x98 Read: 0x99)
Finstack Prox
CPU, Mem, Ambient,
J8500
ALS
SMC SMBus "1" S0 Connections
(MASTER)
U5000
SMC
TEMP SENSOR
(WRITE: 0X54 READ 0X55)
Charger, WIFI
TEMP SENSOR
TMP421: U5800
TMP421: U5810
TBT, I/O
(WRITE: 0X3C READ 0X3D)
SMC
ISL6259 - U7000
U5000
(MASTER)
Battery
(See Table)
SMC SMBus "0" S0 Connections
42 OF 73
53 OF 500
1.0.0
051-02265
NO_TEST=1
NO_TEST=1
MAKE_BASE=TRUE
SMBUS_PCH_DATA
=I2C_UPC_XA_SCL2
PP3V3_S0
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
=I2C_TCON_SCL
MAKE_BASE=TRUE
SMBUS_SMC_5_G3H_SDA=I2C_TCON_SDA
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SCL
=I2C_THMSNS_SDA
SMBUS_SMC_1_S0_SDA
MAKE_BASE=TRUE
=I2C_THMSNS_SCL
=I2C_THMSNS_SDA
=I2C_THMSNS_SCL
I2C_ALS_SDA
I2C_ALS_SCL
=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
PP3V3_S0
PP3V3_G3H
SMBUS_SMC_4_G3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_4_G3_SDA
MAKE_BASE=TRUE
=I2C_UPC_XA_INT2_L
=I2C_UPC_XB_SCL2
MAKE_BASE=TRUE
SMBUS_SMC_5_G3H_SCL
=SMBUS_SMC_PMIC_SDA
=SMBUS_SMC_PMIC_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_3_SCL
=I2C_UPC_XA_SDA2
=I2C_UPC_XB_SDA2
=I2C_UPC_XB_INT2_L
=I2C_TPAD_SCL
MAKE_BASE=TRUE
SMBUS_SMC_3_S0_SCL
=SMBUS_BATT_SCL
=SMB_SMC_CHGR_SDA
=SMB_SMC_CHGR_SCL
=SMBUS_BATT_SDA
PP3V3_S0
SML_PCH_1_CLK
PP3V3_G3H
SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SDA
SML_PCH_1_DATA
PP3V3_S0
MAKE_BASE=TRUE
SMBUS_PCH_CLK
MAKE_BASE=TRUE
SML_PCH_0_CLK
MAKE_BASE=TRUE
SML_PCH_0_DATA
PP3V3_S0
=I2C_TPAD_SDA
MAKE_BASE=TRUE
SMBUS_SMC_3_S0_SDA
SMC_USBC_INT_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SMBUS_SMC_2_SDA
SMBUS_SMC_2_SCL SMBUS_SMC_2_SDA
MAKE_BASE=TRUE
NC_SMBUS_SMC_2_SCL
SMBus Connections
BOM_COST_GROUP=SMC
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
402
MF-LF
1/16W
5%
10k
2
1
R5322
201
MF
1/20W
5%
2.0K
2
1
R5320
201
MF
1/20W
5%
2.0K
2
1
R5321
201
MF
1/20W
5%
2.0K
2
1
R5350
201
MF
1/20W
5%
2.0K
2
1
R5351
201
MF
1/20W
5%
2.0K
2
1
R5390
201
MF
1/20W
5%
2.0K
2
1
R5391
201
MF
1/20W
5%
1K
2
1
R5300
201
MF
1/20W
5%
1K
2
1
R5301
201
MF
1/20W
5%
8.2K
2
1
R5311
201
MF
1/20W
5%
8.2K
2
1
R5310
201
MF
1/20W
5%
2.0K
2
1
R5381
201
MF
1/20W
5%
2.0K
2
1
R5380
201
MF
1/20W
5%
2.0K
2
1
R5360
201
MF
1/20W
5%
2.0K
2
1
R5361
13
29 28
69
64 63 60 59 54 49 46 45 42 38
39
66
66
39
39
46 42
39
46 42
46 42
46 42
66
66
46
46
69
64 63 60 59 54 49 46 45 42 38
72 69
68 60 53 52 51 47 42 41 28 19
39
39
29
30
72
60
60
39
39
29 28
30
30
38
52
53
53
52
69
64 63 60 59 54 49 46 45 42 38
13
72 69
68 60 53 52 51 47 42 41 28 19
39
39
13
69
64 63 60 59 54 49 46 45 42 38
13
13
13
69
64 63 60 59 54 49 46 45 42 38
38
39 28
39
39
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
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C
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8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
合肥怡飞苹果维修qq:82669515 qq群: 241000
GAIN: 50X, EDP: 9.5 A
SMC ADC: 05
GAIN: 100X. EDP: 0.9 A
CPU High Side Current Sense (IC0R)
VSENSE: 28.5 MV, RANGE: 21.3 A
RSENSE: 0.002 (R5460)
Enables DC-In VSense divider when AC present.
SHORT RSENSE
SIGNAL PUMP-UP.
VSENSE: 22.5 MV, RANGE: 1.42 A
VSENSE: 22.5 MV, RANGE: 0.55 A
SMC AD: 4
SMC AD: 19
Rsense: 0.025 (R7700)
SMC ADC: 2
SMC ADC: 01 SMC ADC: 03
Gain: 0.148x
500X
RSENSE: 0.010 (R7120)
Vnominal: 12.6 V, Range: 19.7 V
Gain: 0.167x
divider when in S0.
LAST CHANGE: Thu Aug 4 21:00:42 2016
DESIGN: X502/MLB_CATZ
Charger Gain: 20x, EDP: 4.6 A
Rthevenin = 4573 Ohms
RSENSE: 0.005 (R7160)
Charger (BMON) Current Sense (IPBR)
Charger Gain: 36x, EDP: 8 A
DC-IN (AMON) Current Sense (ID0R)
100X
SMC AD: 12
RSENSE: 0.005 (R5420)
GAIN: 500X. EDP: 0.9 A
500X
Rsense: 0.003 (R5400)
Enables PBUS VSense
Rthevenin = 4573 Ohms
SMC ADC: 0
VSENSE: 22.5 MV, RANGE: 2.6 A
GAIN: 200X. EDP: 0.9 A
TRACKPAD ACTUATOR X239 CURRENT SENSE (ITAR)
50X
DC In Voltage Sense & Enable (VD0R)
Vnominal: 16.5 V, Range: 22.29 V
PULL-DOWN RESISTERS ON INA OUTPUTS BLEED OFF THE LEAKAGE CURRENT TO PREVENT
INA21X PARTS HAVE MINOR LEAKAGE PATH FROM INPUTS TO OUTPUT WHEN UNPOWERED.
SSD NAND CURRENT SENSE (IHNC)
LCD BACKLIGHT CURRENT SENSE (IBLR)
PBUS Voltage Sense & Enable (VP0R)
43 OF 73
54 OF 500
1.0.0
051-02265
SMC_SSD_ISENSE
PP3V3_S4
ISNS_SSD_IOUT
ISNS_LCDBKLT_IOUT
ISNS_HS_SSD_P
ISNS_HS_SSD_N
PPBUS_G3H_CPU
=PPDCIN_G3H_SNS
SMC_CPU_HI_ISENSEISNS_HS_COMPUTING_N
ISNS_LCDBKLT_P
ISNS_LCDBKLT_N
ISNS_HS_COMPUTING_P
PBUSVSENSE_EN
GND_SMC_AVSS
PPBUS_G3H
GND_SMC_AVSS
PP3V3_S4
PPBUS_G3H_SSD
SMC_LCDBKLT_ISENSE
CHGR_BMON
PP3V3_S4
ISNS_HS_TPAD_P
ISNS_HS_TPAD_N
PPBUS_G3H_TPAD
GND_SMC_AVSS
GND_SMC_AVSS
GND_SMC_AVSS
SMC_TPAD_ISENSE
GND_SMC_AVSS
ISNS_TPAD_IOUT
SMC_DCIN_VSENSE
GND_SMC_AVSS
PPDCIN_G3H_VSNS_IN
DCIN_S5_VSENSE
PDCINVSENS_EN_L_DIV
DCINVSENS_EN_L
PBUSVSENS_EN_L_DIV
PBUSVSENS_EN_L
SMC_PBUS_VSENSE
PBUS_S0_VSENSE
PBUS_S0_VSENSE_IN
CHGR_AMON SMC_DCIN_ISENSE
GND_SMC_AVSS
SMC_BMON_ISENSE
PP3V3_S4
PPBUS_G3H
DCINVSENSE_EN
PPBUS_G3H
PPBUS_G3H
CPUHI_IOUT
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C54291117S0008 SNS_I_SSD:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C54591117S0008 SNS_I_BLC:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C54691117S0008 SNS_I_TPAD:NO
BOM_COST_GROUP=SENSORS
Power Sensors High Side
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
201
MF
1/20W
1%
PLACE_NEAR=U5000.G1:5MM
300K
21
R5438
41
41
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.H2:5MM
0.22UF
SNS_I_BLC:YES
2
1
C5459
201
MF
1/20W
1%
PLACE_NEAR=U5000.H2:5MM
4.53K
SNS_I_BLC:YES
21
R5459
0201
X5R-CERM
10V
10%
BYPASS=U5450.3:2:5MM
0.1UF
SNS_I_BLC:YES
2
1
C5450
0201
X7R-CERM
10V
10%
PLACE_NEAR=U5000.G3:5MM
2200PF
2
1
C5439
201
MF
1/20W
1%
PLACE_NEAR=U5000.G3:5MM
45.3K
21
R5439
41
SM
21
XW5480
41
41
201
MF
1/20W
1%
PLACE_NEAR=U5000.G2:5MM
27.4K
2
1
R5488
201
MF
1/20W
1%
100K
2
1
R5482
SOT-963
NTUD3169CZ
CRITICAL
4
1
5
2
3
6
Q5480
41
41
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.G2:5.1MM
0.22UF
2
1
C5489
201
MF
1/20W
1%
PLACE_NEAR=U5000.G2:5.7MM
5.49K
2
1
R5489
201
MF
1/20W
1%
200K
2
1
R5492
SOT-963
NTUD3169CZ
CRITICAL
4
1
5
2
3
6
Q5490
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.G4:5MM
0.22UF
2
1
C5499
201
MF
1/20W
1%
PLACE_NEAR=U5000.G4:5MM
27.4K
2
1
R5498
201
MF
1/20W
1%
PLACE_NEAR=U5000.G4:5MM
4.53K
2
1
R5499
201
MF
1/20W
1%
100K
2
1
R5481
201
MF
1/20W
1%
69.8K
2
1
R5491
1K
201
MF
1/20W
1%
PLACE_NEAR=U5000.C3:5.2MM
21
R5409
0201
X5R-CERM
10V
10%
PLACE_NEAR=U5000.C3:6.2MM
0.1UF
2
1
C5409
0201
X5R-CERM
10V
10%
BYPASS=U5400.3:2:5MM
0.1UF
2
1
C5401
53
0201
C0G
25V
+/-0.25PF
3.5PF
CRITICAL
2
1
C5451
0201
C0G
25V
+/-0.25PF
3.5PF
CRITICAL
2
1
C5452
0201
C0G
25V
+/-0.25PF
3.5PF
CRITICAL
SNS_I_BLC:YES
2
1
C5455
0612-5
MF
1W
1%
PLACE_NEAR=U5420.4:10MM
PLACE_NEAR=U5420.5:10MM
NO_XNET_CONNECTION=1
0.005
CRITICAL
432
1
R5420
SC70
INA211
CRITICAL
SNS_I_SSD:YES
3
1
6
4
5
2
U5420
0612
CYN
1W
1%
PLACE_NEAR=U5400.4:10MM
PLACE_NEAR=U5400.5:10MM
NO_XNET_CONNECTION=1
0.003
CRITICAL
341
2
R5400
0201
X5R-CERM
10V
10%
BYPASS=U5420.3:2:5MM
0.1UF
SNS_I_SSD:YES
2
1
C5420
201
MF
1/20W
1%
PLACE_NEAR=U5420.6:5MM
15K
SNS_I_SSD:YES
2
1
R5425
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.D4:5MM
0.22UF
SNS_I_SSD:YES
2
1
C5429
201
MF
1/20W
1%
PLACE_NEAR=U5000.D4:5MM
4.53K
SNS_I_SSD:YES
21
R5429
41
0612-SHORT-1
CYN
1W
1%
PLACE_NEAR=U5460.4:10MM
PLACE_NEAR=U5460.5:10MM
NO_XNET_CONNECTION=1
0.003
CRITICAL
OMIT
341
2
R5460
SC70
INA211
CRITICAL
SNS_I_TPAD:YES
3
1
6
4
5
2
U5460
201
MF
1/20W
1%
PLACE_NEAR=U5460.6:5MM
15K
SNS_I_TPAD:YES
2
1
R5465
0201
X5R-CERM
10V
10%
BYPASS=U5460.3:2:5MM
0.1UF
SNS_I_TPAD:YES
2
1
C5460
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.C2:5MM
0.22UF
SNS_I_TPAD:YES
2
1
C5469
201
MF
1/20W
1%
PLACE_NEAR=U5000.C2:5MM
4.53K
SNS_I_TPAD:YES
21
R5469
41
SC70
INA214
CRITICAL
SNS_I_BLC:YES
3
1
6
4
5
2
U5450
SC70
INA213
CRITICAL
3
1
6
4
5
2
U5400
SM
21
XW5490
201
MF
1/20W
5%
PLACE_NEAR=U5400.6:5MM
15K
2
1
R5405
201
MF
1/20W
1%
PLACE_NEAR=U5450.6:5MM
15K
SNS_I_BLC:YES
2
1
R5455
41
65
65
0201
X7R-CERM
10V
10%
PLACE_NEAR=U5000.G1:5MM
3300PF
2
1
C5438
53
72 69 67 64 63 45 44 43 41
63 62 61
59 57 56 55 54
69
46
46
45 44 43 41 40 39
72 69 68 63
60 58 53 50 43
45 44 43 41 40 39
72 69 67 64 63 45 44 43 41
67
72 69 67 64 63 45 44 43 41
69
45 44 43 41 40 39
45 44 43 41 40 39
45 44 43 41 40 39
45 44 43 41 40 39
45 44 43 41 40 39
45 44 43 41 40 39
72 69 67 64 63 45 44 43 41
72 69 68 63 60 58 53 50 43
72 69 68
63 60 58 53 50 43
72 69 68 63
60 58 53 50 43
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
OUT
IN
OUT
OUT
D
S
S
P-CHANNEL
G
D
G
N-CHANNEL
IN
OUT
D
S
S
P-CHANNEL
G
D
G
N-CHANNEL
IN
GND
OUT
IN-
IN+ REF
V+
OUT
GND
OUT
IN-
IN+ REF
V+
OUT
GND
V+
REFIN+
IN-
OUT
GND
OUT
IN-
IN+ REF
V+
OUT
IN
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
3V3_S4 WIRELESS CURRENT SENSE (IAPC)
RSENSE: 0.010 (R7700)
SMC AD: 18
SHORT RSENSE
5V_S4 CURRENT SENSE (IO5R)
VSENSE: 22.5 MV, RANGE: 1.22 A
3V3_SSD CURRENT SENSE (IHCC)
VSENSE: 22.5 MV, RANGE: 3.61 A
GAIN: 200X. EDP: 0.9 A
1V2_S3 CURRENT SENSE (IM0C)
VSENSE: 22.5 MV, RANGE: 7.67 A
200X
SMC AD: 14
200X
200X
GAIN: 500X. EDP: 0.9 A
VSENSE: 22.5 MV, RANGE: 1.6 A
RSENSE: 0.005 (R8520)
SMC AD: 17
VSENSE: 22.5 MV, RANGE: 1.6 A
RSENSE: 0.005 (R5525)
SMC AD: 17
GAIN: 200X. EDP: 0.9 A
500X
GAIN: 200X. EDP: 0.9 A
200X
SMC AD: 22
VSENSE: 22.5 MV ?, RANGE: 4 A
GAIN: 200X. EDP: 0.9 A
RSENSE: 0.003 (R7710)
SMC AD: 13
RSENSE: 0.003 (R5515)
GAIN: 200X. EDP: 0.9 A
3V3_S5 CURRENT SENSE (IO3R)
200X
(HIGH-SIDE)
GAIN: 200X. EDP: ?? A
VSENSE: 22.5 MV ?, RANGE: 6.8 A
SMC AD: 21
RSENSE: 0.003 (R7900)
(HIGH-SIDE)
200X
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
SMC AD: 11
VSENSE: 22.5 MV, RANGE: 3.0 A
RSENSE: 0.003 (R7700)
GAIN: 200X. EDP: 0.9 A
3V3_S0 LCD CURRENT SENSE (ILDC)
5V_S0 LCD CURRENT SENSE (I___)
RSENSE: 0.002 (R7700)
1V_S5G CURRENT SENSE (ISIC)
44 OF 73
55 OF 500
1.0.0
051-02265
ISNS_1VS5G_IOUT
ISNS_3V3SSD_N
PP3V3_S4
GND_SMC_AVSS
PP3V3_S4
PP3V3_S4
ISNS_3V3WLS_P
SMC_3V3WLS_ISENSE
ISNS_1V2S3_N
ISNS_1V2S3_P
PP3V3_S4
ISNS_1V2S3_IOUT
GND_SMC_AVSS
SMC_1V2S3_ISENSE
ISNS_1VS5G_P
ISNS_1VS5G_N SMC_1VS5G_ISENSE
ISNS_LCDPANEL_P
ISNS_LCDPANEL_N
PP3V3_S4
ISNS_3V3LCD_IOUT
GND_SMC_AVSS
SMC_3V3LCD_ISENSE
GND_SMC_AVSS
SMC_5VS4_ISENSE
PP3V3_S4
ISNS_3V3WLS_IOUT
GND_SMC_AVSS
PP3V3_S5_SSD
PP3V3_S5
ISNS_3V3SSD_P
ISNS_3V3S5_N
ISNS_3V3S5_P
PP3V3_S4
ISNS_3V3S5_IOUT
GND_SMC_AVSS
SMC_3V3S5_ISENSE
ISNS_3V3SSD_IOUT
GND_SMC_AVSS
PP3V3_S4
ISNS_5VS4_N
ISNS_5VS4_P
ISNS_5VS4_IOUT
PP3V3_S4_WLS
SMC_3V3SSD_ISENSE
ISNS_3V3WLS_N
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
Power Sensors Load Side
BOM_COST_GROUP=SENSORS
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C55031117S0008 SNS_I_1VS5G:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C55081117S0008 SNS_I_1V2S3:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C55231117S0008 SNS_I_3V3S5:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C55181117S0008 SNS_I_3V3SSD:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C55281117S0008 SNS_I_3V3LCD:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C55431117S0008 SNS_I_5VS4:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C55331117S0008 SNS_I_3V3WLS:NO
SC70
INA210
CRITICAL
SNS_I_3V3SSD:YES
3
1
6
4
5
2
U5515
SC70
INA210
CRITICAL
SNS_I_3V3S5:YES
3
1
6
4
5
2
U5520
66
66
62
0612
CYN
1W
1%
PLACE_NEAR=U5515.5:10MM
PLACE_NEAR=U5515.4:10MM
NO_XNET_CONNECTION=1
0.003
CRITICAL
432
1
R5515
58
58
SC70
INA210
CRITICAL
SNS_I_5VS4:YES
3
1
6
4
5
2
U5540
201
MF
1/20W
1%
PLACE_NEAR=U5540.6:5MM
15K
SNS_I_5VS4:YES
2
1
R5542
0201
X5R-CERM
10V
10%
BYPASS=U5540.3:2:5MM
0.1UF
SNS_I_5VS4:YES
2
1
C5540
201
MF
1/20W
1%
PLACE_NEAR=U5000.C5:5MM
4.53K
SNS_I_5VS4:YES
21
R5543
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.C5:5MM
0.22UF
SNS_I_5VS4:YES
2
1
C5543
41
58
58
0612-SHORT-1
CYN
1W
1%
PLACE_NEAR=U5530.4:10MM
PLACE_NEAR=U5530.5:10MM
NO_XNET_CONNECTION=1
0.003
CRITICAL
OMIT
432
1
R5530
SC70
INA210
CRITICAL
SNS_I_1VS5G:YES
3
1
6
4
5
2
U5500
SC70
INA210
CRITICAL
SNS_I_3V3WLS:YES
3
1
6
4
5
2
U5530
201
MF
1/20W
1%
PLACE_NEAR=U5530.6:5MM
15K
SNS_I_3V3WLS:YES
2
1
R5532
0201
X5R-CERM
10V
10%
BYPASS=U5530.3:2:5MM
0.1UF
SNS_I_3V3WLS:YES
2
1
C5530
201
MF
1/20W
1%
PLACE_NEAR=U5000.H1:5MM
4.53K
SNS_I_3V3WLS:YES
21
R5533
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.H1:5MM
0.22UF
SNS_I_3V3WLS:YES
2
1
C5533
41
201
MF
1/20W
1%
PLACE_NEAR=U5500.6:5MM
15K
SNS_I_1VS5G:YES
2
1
R5502
201
MF
1/20W
1%
PLACE_NEAR=U5520.6:5MM
15K
SNS_I_3V3S5:YES
2
1
R5522
0201
X5R-CERM
10V
10%
BYPASS=U5520.3:2:5MM
0.1UF
SNS_I_3V3S5:YES
2
1
C5520
201
MF
1/20W
1%
PLACE_NEAR=U5000.B5:5MM
4.53K
SNS_I_3V3S5:YES
21
R5523
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.B5:5MM
0.22UF
SNS_I_3V3S5:YES
2
1
C5523
41
SNS_I_1VS5G:YES
0201
X5R-CERM
10V
10%
BYPASS=U5500.3:2:5MM
0.1UF
2
1
C5500
201
MF
1/20W
1%
PLACE_NEAR=U5515.6:5MM
15K
SNS_I_3V3SSD:YES
2
1
R5517
0201
X5R-CERM
10V
10%
BYPASS=U5515.3:2:5MM
0.1UF
SNS_I_3V3SSD:YES
2
1
C5515
201
MF
1/20W
1%
PLACE_NEAR=U5000.D3:5MM
4.53K
SNS_I_3V3SSD:YES
21
R5518
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.D3:6.2MM
0.22UF
SNS_I_3V3SSD:YES
2
1
C5518
41
0.22UF
PLACE_NEAR=U5000.B4:5MM
0201
X5R
6.3V
20%
SNS_I_1VS5G:YES
2
1
C5503
62
201
MF
1/20W
1%
PLACE_NEAR=U5000.B4:5MM
4.53K
SNS_I_1VS5G:YES
21
R5503
62
0201
X5R-CERM
10V
10%
BYPASS=U5505.3:2:5MM
0.1UF
SNS_I_1V2S3:YES
2
1
C5505
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.C1:5MM
0.22UF
SNS_I_1V2S3:YES
2
1
C5508
201
MF
1/20W
1%
PLACE_NEAR=U5000.C1:5MM
4.53K
SNS_I_1V2S3:YES
21
R5508
41
SC70
INA210
CRITICAL
SNS_I_1V2S3:YES
3
1
6
4
5
2
U5505
PLACE_NEAR=U5505.6:5MM
201
MF
1/20W
1%
15K
SNS_I_1V2S3:YES
2
1
R5507
SC70
INA211
CRITICAL
SNS_I_3V3LCD:YES
3
1
6
4
5
2
U5525
201
MF
1/20W
1%
PLACE_NEAR=U5525.6:5MM
15K
SNS_I_3V3LCD:YES
2
1
R5527
0201
X5R-CERM
10V
10%
BYPASS=U5525.3:2:5MM
0.1UF
SNS_I_3V3LCD:YES
2
1
C5525
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.H3:5.5MM
0.22UF
SNS_I_3V3LCD:YES
2
1
C5528
201
MF
1/20W
1%
PLACE_NEAR=U5000.H3:5MM
4.53K
SNS_I_3V3LCD:YES
21
R5528
41
62
41
72 69 67 64 63 45 44 43 41
45 44 43 41 40 39
72 69 67 64 63 45 44 43 41
72 69 67 64 63 45 44 43 41
72 69 67 64 63 45 44 43 41
45 44 43 41 40 39
72 69 67 64 63 45 44 43 41
45 44 43 41 40 39
45 44 43 41 40 39
72 69 67 64 63 45 44 43 41
45 44 43 41 40 39
69 67
72 69
68 64 63 61 60 58
72 69 67 64 63 45 44 43 41
45 44
43 41 40 39
45 44 43 41 40 39
72 69 67 64 63 45 44 43 41
72 69 63
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
GND
OUT
IN-
IN+ REF
V+
GND
OUT
IN-
IN+ REF
V+
IN
IN
IN
IN
IN
GND
OUT
IN-
IN+ REF
V+
OUT
IN
IN
GND
OUT
IN-
IN+ REF
V+
GND
OUT
IN-
IN+ REF
V+
OUT
OUT
OUT
IN
IN
OUT
GND
OUT
IN-
IN+ REF
V+
GND
OUT
IN-
IN+ REF
V+
OUT
IN
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
then 1A of Io gives 28.273mV at the Vimon.
SMC AD: 23
CPU SA CURRENT SENSE (ICSC)
500X
SMC AD: 10
RSENSE: 0.002 (R7700)
GAIN: 200X. EDP: 0.9 A
VSENSE: 22.5 MV, RANGE: 7.67 A
SMC AD: 9
VSENSE: 22.5 MV, RANGE: 2.27 A
GAIN: 200X. EDP: 0.9 A
RSENSE: 0.005 (R7700)
CPU GT CURRENT SENSE (ICGC)
SMC AD: 7
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
With R7210 (Ri) set to 316 Ohm,
Num Phases (N) is 2, and Io (ICCmax) is 40A,
R7230 set to 95.3 kOhm,
SMC ADC: 6
CPU CORE VOLTAGE SENSE (VCAC)
SMC ADC: 15
RSENSE: 0.005 (R5640)
GAIN: 500X. EDP: A
VSENSE: MV, RANGE: A
R7310 (Rsen) set to 0.75 mOhm,
VSENSE: 22.5 MV, RANGE: 2.27 A
RSENSE: 0.005 (R7700)
GAIN: 200X. EDP: 0.9 A
TBT CURRENT SENSE (IULC)
Gain: 1 A / 28.273 mV, Range: 40 A.
CPU VCC CURRENT SENSE (ICAC)
200X
CPU CORE IMON CURRENT SENSE (ICAM)
SMC ADC: 20
R7230 set to 95.3 kOhm,
CPU SA IMON CURRENT SENSE (ICSM)
With R7210 (Ri) set to 316 Ohm,
Num Phases (N) is 2, and Io (ICCmax) is 40A,
R7310 (Rsen) set to 0.75 mOhm,
Gain: 1 A / 28.273 mV, Range: 40 A.
then 1A of Io gives 28.273mV at the Vimon.
Gain: 1 A / 28.273 mV, Range: 40 A.
CPU GT IMON CURRENT SENSE (ICGM)
Num Phases (N) is 2, and Io (ICCmax) is 40A,
With R7210 (Ri) set to 316 Ohm,
R7310 (Rsen) set to 0.75 mOhm,
then 1A of Io gives 28.273mV at the Vimon.
CPU GT VOLTAGE SENSE (VCGC)
SMC ADC: 8
SMC ADC: 16
R7230 set to 95.3 kOhm,
45 OF 73
56 OF 500
1.0.0
051-02265
CPUVR_IMON SMC_CPU_IMON_ISENSE
CPUVSENSE_INPPVCCCPU_S0G SMC_CPU_VSENSE
GND_SMC_AVSS
GND_SMC_AVSS
CPUVR_ISNS_P
SMC_CPU_ISENSE
CPUVR_ISNS1_P
CPUVR_ISNS2_P
CPUVR_ISNS1_N
GND_SMC_AVSS
PP3V3_S0
GTVR_ISNS_P
SMC_GT_ISENSE
SAVR_ISNS_IOUT SMC_SA_ISENSE
GTVR_ISNS3_P
GTVR_ISNS1_P
GTVR_ISNS2_P
GTVR_ISNS1_N
GTVR_ISNS2_N
GTVR_ISNS3_N
SAVR_ISNS_N
SAVR_ISNS_P
ISNS_HS_TBT_P
GND_SMC_AVSS
SMC_TBT_ISENSEISNS_TBT_IOUTISNS_HS_TBT_N
GND_SMC_AVSS
PP3V3_S4
=PP3V3_S0_TBT_X_SNS
GTVR_ISNS_R_P
GTVR_ISUM_IOUT
GTVR_ISNS_R_N
PP3V3_S0
GND_SMC_AVSS
CPUVR_ISNS_R_N
PP3V3_S0
GTVR_ISNS_N
CPUVR_ISNS2_N
CPUVR_ISNS_N
CPUVR_ISNS_R_P
GND_SMC_AVSS
SAVR_IMON SMC_SA_IMON_ISENSE
GND_SMC_AVSS
GND_SMC_AVSS
SMC_GT_VSENSE
SMC_GT_IMON_ISENSE
PPVCCGT_S0G GTVSENSE_IN
GTVR_IMON
CPUVR_ISUM_IOUT
PP3V3_S0
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C56901117S0008 SNS_I_IMNVCC:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C56921117S0008 SNS_I_IMNVGT:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C56911117S0008 SNS_I_IMNVSA:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C56151117S0008 SNS_I_CPUVGT:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C56311117S0008 SNS_I_CPUVSA:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C56491117S0008 SNS_I_TBT:NO
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C56051117S0008 SNS_I_CPUVCC:NO
BOM_COST_GROUP=SENSORS
Power Sensors Extended
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
0612-5
MF
1W
1%
PLACE_NEAR=U5640.5:10MM
PLACE_NEAR=U5640.4:10MM
NO_XNET_CONNECTION=1
0.005
CRITICAL
341
2
R5640
SC70
INA211
CRITICAL
SNS_I_TBT:YES
3
1
6
4
5
2
U5640
201
MF
1/20W
1%
PLACE_NEAR=U5640.6:5MM
15K
SNS_I_TBT:YES
2
1
R5645
0201
X5R-CERM
10V
10%
BYPASS=U5640.3:2:5MM
0.1UF
SNS_I_TBT:YES
2
1
C5640
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.A5:5MM
0.22UF
SNS_I_TBT:YES
2
1
C5649
201
MF
1/20W
1%
PLACE_NEAR=U5000.A5:5MM
4.53K
SNS_I_TBT:YES
21
R5649
41
56
56
SC70
INA210
CRITICAL
SNS_I_CPUVSA:YES
3
1
6
4
5
2
U5630
201
MF
1/20W
1%
PLACE_NEAR=U5630.6:5MM
15K
SNS_I_CPUVSA:YES
2
1
R5630
0201
X5R-CERM
10V
10%
BYPASS=U5630.3:2:5MM
0.1UF
SNS_I_CPUVSA:YES
2
1
C5630
201
MF
1/20W
1%
PLACE_NEAR=U5000.A4:5MM
4.53K
SNS_I_CPUVSA:YES
21
R5631
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.A4:5MM
0.22UF
SNS_I_CPUVSA:YES
2
1
C5631
41
57
57
57
402
MF
1/16W
0.1%
PLACE_NEAR=R7420.3:5MM
NO_XNET_CONNECTION=1
8.66K
SNS_I_CPUVGT:YES
21
R5619
0402
MF
1/16W
0.1%
715K
SNS_I_CPUVGT:YES
2
1
R5614
57
72 57
57
402
MF
1/16W
0.1%
PLACE_NEAR=R7410.3:5MM
NO_XNET_CONNECTION=1
8.66K
SNS_I_CPUVGT:YES
21
R5617
402
MF
1/16W
0.1%
PLACE_NEAR=R7420.4:5MM
NO_XNET_CONNECTION=1
8.66K
SNS_I_CPUVGT:YES
21
R5618
402
MF
1/16W
0.1%
PLACE_NEAR=R7410.4:5MM
NO_XNET_CONNECTION=1
8.66K
SNS_I_CPUVGT:YES
21
R5616
201
MF
1/20W
1%
1.05K
SNS_I_CPUVGT:YES
21
R5613
201
MF
1/20W
1%
1.05K
SNS_I_CPUVGT:YES
21
R5612
0402
MF
1/16W
0.1%
NO_XNET_CONNECTION=1
715K
SNS_I_CPUVGT:YES
21
R5611
SC70-5
ISL28133
CRITICAL
SNS_I_CPUVGT:YES
5
2
4
1
3
U5610
201
MF
1/20W
5%
PLACE_NEAR=U5610.4:5MM
20K
SNS_I_CPUVGT:YES
2
1
R5610
0201
X5R-CERM
10V
10%
BYPASS=U5610.3:2:5MM
0.1UF
SNS_I_CPUVGT:YES
2
1
C5610
201
MF
1/20W
1%
PLACE_NEAR=U5000.B3:5MM
4.53K
SNS_I_CPUVGT:YES
21
R5615
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.B3:5.2MM
0.22UF
SNS_I_CPUVGT:YES
2
1
C5615
41
72 55
55
72 55
55
41
0201
X5R-CERM
10V
10%
BYPASS=U5600.3:2:5MM
0.1UF
SNS_I_CPUVCC:YES
2
1
C5600
402
MF
1/16W
0.1%
PLACE_NEAR=R7430.3:5MM
NO_XNET_CONNECTION=1
8.66K
SNS_I_CPUVGT:YES
21
R5621
402
MF
1/16W
0.1%
PLACE_NEAR=R7430.4:5MM
NO_XNET_CONNECTION=1
8.66K
SNS_I_CPUVGT:YES
21
R5620
402
MF-LF
1/16W
0.1%
PLACE_NEAR=R7220.3:5MM
NO_XNET_CONNECTION=1
3.32K
SNS_I_CPUVCC:YES
21
R5609
402
MF-LF
1/16W
0.1%
PLACE_NEAR=R7210.3:5MM
NO_XNET_CONNECTION=1
3.32K
SNS_I_CPUVCC:YES
21
R5607
402
MF-LF
1/16W
0.1%
PLACE_NEAR=R7220.4:5MM
NO_XNET_CONNECTION=1
3.32K
SNS_I_CPUVCC:YES
21
R5608
402
MF-LF
1/16W
0.1%
PLACE_NEAR=R7210.4:5MM
NO_XNET_CONNECTION=1
3.32K
SNS_I_CPUVCC:YES
21
R5606
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.A2:5MM
0.22UF
SNS_I_CPUVCC:YES
2
1
C5605
201
MF
1/20W
1%
PLACE_NEAR=U5000.A2:5MM
4.53K
SNS_I_CPUVCC:YES
21
R5605
SNS_I_CPUVCC:YES
201
MF
1/20W
5%
PLACE_NEAR=U5600.4:5MM
20K
2
1
R5600
0402
MF
1/16W
0.1%
NO_XNET_CONNECTION=1
715K
SNS_I_CPUVCC:YES
21
R5601
0402
MF
1/16W
0.1%
715K
SNS_I_CPUVCC:YES
2
1
R5604
201
MF
1/20W
1%
1.05K
SNS_I_CPUVCC:YES
21
R5603
201
MF
1/20W
1%
1.05K
SNS_I_CPUVCC:YES
21
R5602
SC70-5
ISL28133
CRITICAL
SNS_I_CPUVCC:YES
5
2
4
1
3
U5600
SM
PLACE_NEAR=R7410.1:13 MM
21
XW5682
201
MF
1/20W
1%
PLACE_NEAR=U5000.A3:5MM
4.53K
21
R5682
0201
MF
1/20W
5%
PLACE_NEAR=U5000.H4:5MM
0
SNS_I_IMNVGT:YES
21
R5692
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.H4:5MM
0.22UF
NOSTUFF
2
1
C5692
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.A3:5MM
0.22UF
2
1
C5682
41
41
0201
MF
1/20W
5%
PLACE_NEAR=U5000.C4:5MM
0
SNS_I_IMNVSA:YES
21
R5691
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.C4:5.5MM
0.22UF
NOSTUFF
2
1
C5691
41
41
41
201
MF
1/20W
1%
PLACE_NEAR=U5000.A1:5MM
4.53K
21
R5680
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.A1:5MM
0.22UF
2
1
C5680
0201
MF
1/20W
5%
PLACE_NEAR=U5000.B1:5MM
0
SNS_I_IMNVCC:YES
21
R5690
0201
X5R
6.3V
20%
PLACE_NEAR=U5000.B1:5MM
0.22UF
NOSTUFF
2
1
C5690
SM
PLACE_NEAR=R7210.1:7 MM
21
XW5680
54
72 69 63 55
45 44 43 41 40 39
45 44 43 41 40 39
45 44 43 41 40 39
69
64 63 60 59 54 49 46 45 42 38
45 44 43 41 40 39
45 44 43 41 40 39
72 69 67 64 63 44 43 41
69
69 64 63 60 59
54 49 46 45 42 38
45 44 43 41 40 39
69
64 63 60 59 54 49 46 45 42 38
45 44 43 41 40 39
54
45 44 43 41 40 39
45 44 43 41 40 39
72 69 63 57
54
69
64 63 60 59 54 49 46 45 42 38
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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PAGE TITLE
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A
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
GND
OUT
IN-
IN+ REF
V+
OUT
IN
IN
GND
OUT
IN-
IN+ REF
V+
OUT
IN
IN
IN
IN
IN
IN
V-
V+
OUT
IN
IN
IN
IN
OUT
V-
V+
OUT
OUT
OUT
OUT
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
0XB9 (READ)
0XB8 (WRITE)
(TH1H)
DESIGN: X502/MLB_CATZ LAST CHANGE: Mon Aug 8 12:54:34 2016
AMBIENT AIR SENSOR
ON BOTTOM SIDE.
CENTERED BETWEEN DRAM
DRAM SENSOR
BOTTOM SIDE NEAR REAR AIR VENT
(TM0p)
CPU SENSOR
(TC0p)
I2C ADDRESS (U5870):
RIGHT EDGE, TOP NEAR FINSTACK.
FIN STACK PROXIMITY
0X55 (READ)
I2C ADDRESS (U5800):
WILL BE USED AS I/O SENSOR
INTERNAL SENSOR OF U5800
0X54 (WRITE)
WILL BE USED AS WIRELESS SENSOR.
PLACED NEAR WIFI IC ON BOTTOM.
(TW0P)
I2C ADDRESS (U5810):
0X3C (WRITE) 0X3D (READ)
PLACED ON BOTTOM SIDE.
INTERNAL SENSOR OF U5810
NOTE:
NOTE:
(Tm0p)
MLB SENSOR
NEAR CHARGER, BOTTOM SIDE.
INTERNAL (U2800)
ALPINE RIDGE SENSOR
Thermal Sensor B & CPU High Peak Detection:
I2C Write: 0x98, I2C Read: 0x99
CPU Proximity, Memory Proximity, Airflow, Fin Stack Proximity
UNDER CPU ON TOP SIDE.
(TLUD)
(TLUP)
(TaLC)
46 OF 73
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.2500
58 OF 500
1.0.0
051-02265
PP3V3_S0_CPUTHMSNS_R
TSNS_1_P
TSNS_3_P
CPUTHMSNS_FILT
CPUTHMSNS_GPIO
CPUTHMSNS_ADDR_SEL
CPUTHMSNS_D2_N
CPUTHMSNS_ALERT_L
CPUTHMSNS_D2_P
PP3V3_S0
TBT_X_THERM_D_P
TBT_X_THERM_D_N
TBT_X_THERM_D_P
=I2C_THMSNS_SDA
=I2C_THMSNS_SCL
TSNS_1_N
TSNS_1_P
=I2C_THMSNS_SDA
=I2C_THMSNS_SCL
TBT_X_THERM_D_N
TSNS_1_N
TSNS_2_A1
TSNS_2_A0
PP3V3_S0
TSNS_1_A1
TSNS_1_A0
PP3V3_S0
=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
ISNS_HS_COMPUTING_R_N
ISNS_HS_COMPUTING_R_P
TSNS_3_N
TSNS_3_P
CPUTHMSNS_D1_N
CPUTHMSNS_D1_P
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
ISNS_HS_COMPUTING_R_N
ISNS_HS_COMPUTING_R_P
TSNS_3_N
CPUTHMSNS_D2_N
CPUTHMSNS_D2_P
CPUTHMSNS_D1_P
CPUTHMSNS_D1_N
Thermal Sensors
BOM_COST_GROUP=SENSORS
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
43
43
0
PLACE_NEAR=R5400.4:10MM
5%
1/20W
MF
0201
21
R5869
0
PLACE_NEAR=R5400.3:10MM
5%
1/20W
MF
0201
21
R5867
0.0022uF
NO_XNET_CONNECTION=1
PLACE_NEAR=U5870.7:5MM
PLACE_NEAR=U5870.6:5MM
10% 50V
CERM
402
2
1
C5871
THRM_SNS_ARIDGE_IO
CRITICAL
TMP421
SOT23-8
8
6
7
5
1
2
3
4
U5810
THRM_SNS_CHGR_WIFI
CRITICAL
TMP421
SOT23-8
8
6
7
5
1
2
3
4
U5800
0.0022uF
NO_XNET_CONNECTION=1 PLACE_NEAR=U5870.8:5MM
PLACE_NEAR=U5870.9:5MM
10% 50V
CERM
402
2
1
C5872
NOSTUFF
100
1% 1/20W MF 201
2
1
R5800
NOSTUFF
100
1% 1/20W MF 201
2
1
R5801
NOSTUFF
100K
1% 1/20W MF 201
2
1
R5811
THRM_SNS_ARIDGE_IO
100
1% 1/20W MF 201
2
1
R5810
DFN1006H4-3
BC846BLP
CRITICAL2
3
1
Q5872
THRM_SNS_CHGR_WIFI
CRITICAL
BC846BLP
DFN1006H4-3
2
3
1
Q5873
THRM_SNS_CHGR_WIFI
0.0022uF
NO_XNET_CONNECTION=1 PLACE_NEAR=U5800.1:5MM
PLACE_NEAR=U5800.2:5MM
10% 50V
CERM
402
2
1
C5873
46 42
46 42
46 42
46 42
THRM_SNS_ARIDGE_IO
1UF
10% 10V X5R 402-1
2
1
C5810
THRM_SNS_CHGR_WIFI
1UF
10% 10V X5R 402-1
2
1
C5800
0.47UF
10% 10V X5R 0402
2
1
C5875
CRITICAL
BC846BLP
DFN1006H4-3
2
3
1
Q5871
47
5% 1/16W MF-LF
402
21
R5870
0.1UF
10% 16V X7R-CERM 0402
2
1
C5870
100
1% 1/20W MF 201
2
1
R5871
CPUTHRM_ALRT:PU
100K
1% 1/20W MF 201
2
1
R5872
46 27
46 26
THRM_SNS_ARIDGE_IO
0.0022UF
NO_XNET_CONNECTION=1 PLACE_NEAR=U5810.1:5MM
PLACE_NEAR=U5810.2:5MM
10% 50V
CERM
402
2
1
C5825
10K
5% 1/16W MF-LF 402
2
1
R5873
42
42
CRITICAL
TMP513AISAR
QFN
1
2
16
17
3
4
12
14
15
10
8
6
11
9
7
13
5
U5870
CRITICAL
BC846BLP
DFN1006H4-3
2
3
1
Q5805
0.0022UF
NO_XNET_CONNECTION=1 PLACE_NEAR=U5870.10:5MM
PLACE_NEAR=U5870.11:5MM
10% 50V
CERM
402
2
1
C5805
46
46
46
41
46
69
64 63 60 59 54 49 46 45 42 38
46 27
46 26
46
46
46
69
64 63 60 59 54 49 46 45 42 38
69
64 63 60 59 54 49 46 45 42 38
46
46
46
46
46
46
46
46
46
46
46
46
46
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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PAGE TITLE
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
A0
DXN
DXP
SDA
SCL
A1
GND
VDD
A0
DXN
DXP
SDA
SCL
A1
GND
VDD
BI
IN
BI
IN
IN
IN
BI
IN
PAD
SCL
FILTER C
GPIO
ALERT
SDA
A0
DXN2
GND
VIN-
VIN+
DXN3
DXP3
DXP2
DXN1
DXP1
V+
THRM
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SPI ROM - Combo BGA Footprint (3 vendors)
SPI Frequency: 50MHz for CPU, 20MHz for SMC.
(SPI_IO<0>)
CPU Master
Sam Card ROM Slave
BootROM SPI Bus Series Termination
(SPI_IO<1>)
(SPI_IO<0>)
(SPI_IO<1>)
(SPI_IO<1>)
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
SPI ROM Slave
SPI+SWD SAM Connector
(SPI_IO<0>)
(SWDIO)
(SWCLK)
516s00024
Quad-IO Mode (Mode 0 & 3) supported.
47 OF 73
61 OF 500
1.0.0
051-02265
PLACE_NEAR=U6100.5:12MM
SPI_MLBROM_CS_L
SPI_MLB_MISO
SPI_MLB_MOSI
SPI_MLB_IO<3>
SPI_MOSI_R
SPI_MISO
SPI_IO<3>
SPI_MLB_CS_L
SPI_MLB_CLK
SPI_MLB_MOSI
SPI_MLB_MISO
SPI_MLB_IO<2>
SPI_MLB_IO<3>
SPI_IO<2>
SPI_CLK_R
SPI_CS0_R_L
SPI_MLB_CS_L
SPI_ALT_CLK
SMC_RESET_L
SPIROM_USE_MLB
SPI_ALT_MOSI
PP3V3_G3H
SPI_ALT_CS_L
SPI_ALT_IO<2>
SPI_ALT_MISO
SPI_ALT_CS_L
SPI_ALT_MISO
SPI_ALT_CLK
SPIROM_USE_MLB
SPI_ALT_IO<3>
SPI_ALT_IO<3>
SPI_ALT_MOSI
SPI_ALT_IO<2>
SMC_TMS SMC_TCK
SPI_MLB_IO<2>
SPI_MLB_CLK
=PP3V3_SUS_PCH_VCCSPI
SPI ROM & SWD Debug
BOM_COST_GROUP=CPU SUPPORT
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
201
MF
1/20W
5%
PLACE_NEAR=U6100.6:12MM
33
21
R6121
201
MF
1/20W
5%
PLACE_NEAR=U6101.3:3MM
33
21
R6120
13
201
MF
1/20W
5%
PLACE_NEAR=U6100.2:12MM
33
21
R6123
13
13
WSON
N25Q064A13EF640
64MBIT
CRITICAL
OMIT_TABLE
3
489
1
7
2
5
6
U6100
M-ST-SM
DF40PC-12DP-0.4V-51
CRITICAL
16
15
14 13
12 11
10 9
8 7
6 5
4 3
2 1
J6100
68 66 53
72 47 16
72 40 39 28
72 40 39 28
0201
X5R-CERM
10V
10%
BYPASS=U6101::3mm
0.1UF
2
1
C6101
SOT833
PLACE_NEAR=U6100.1:12MM
74LVC1G99
CRITICAL
7
8
1
4
6
5
3
2
U6101
0201
X5R-CERM
10V
10%
BYPASS=U6100::3mm
0.1UF
2
1
C6100
0201
MF
1/20W
5%
PLACE_NEAR=J6100.12:5MM
0
2
1
R6125
0201
MF
1/20W
5%
PLACE_NEAR=J6100.11:5MM
0
2
1
R6126
0201
MF
1/20W
5%
PLACE_NEAR=J6100.3:5MM
0
2
1
R6127
0201
MF
1/20W
5%
PLACE_NEAR=J6100.5:5MM
0
2
1
R6128
0201
MF
1/20W
5%
PLACE_NEAR=J6100.7:5MM
0
2
1
R6132
0201
MF
1/20W
5%
PLACE_NEAR=J6100.9:5MM
0
2
1
R6133
13
17 13
201
MF
1/20W
5%
PLACE_NEAR=U6100.7:12MM
33
21
R6131
201
MF
1/20W
5%
PLACE_NEAR=U6100.3:12MM
33
21
R6130
13
201
MF
1/20W
5%
33
21
R6122
72
72 47
72 47
72 47
72 47
72 47
72 47
72 47
72 47
72 47
72 47
47
47
72
69 68 60 53 52 51 42 41 28 19
47
47
47
47
47
47
72 47 16
47
47
47
47
72 47
72 47
69 13 8
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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PAGE TITLE
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
IN
IN
HOLD/DQ3
S*
W*/VPP/DQ2
C
VSS THRM_PAD
DQ0
DQ1
VCC
OUT
BI
OUT
BI
GND
C
OE*
YA
B
D
VCC
BI
BI
BI
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HELP BLOCK PHYSICAL DAMAGE TO U6200
TO LEFT AMPS
TO RIGHT AMPS
TO CLIFDEN
LAST CHANGE: Thu Aug 4 21:00:42 2016
DESIGN: X502/MLB_CATZ
48 OF 73
CRITICAL
CRITICAL
CRITICAL CRITICAL
CRITICAL
62 OF 500
1.0.0
051-02265
AUD_ASP1B_LRCLK
AUD_I2C_SCL
HDA_SYNC
8409_SPKR_ID1
8409_SPKR_ID0
HDA_BIT_CLK
AUD_ASP2_SDOUT
AUD_ASP2_SCLK
AUD_ASP1A_LRCLK
8409_DMIC1_DATA
HDA_SDOUT
HDA_RST_L
8409_HDA_SDIN0_R
AUD_ASP1B_SCLK
AUD_ASP1B_SDOUT
8409_DMIC1_CLK_R
DMIC1_DATA
DMIC1_CLK
AUD_ASP1A_SCLK
AUD_I2C_SDA
HDA_SDIN0
AUD_ASP1A_SDOUT
AUD_ASP2_LRCLK
PP1V8_S0
8409_ASP1_SCLK_R
8409_ASP2_SDOUT_R
8409_ASP2_LRCLK_R
8409_ASP1_SDOUT_R
8409_ASP2_SCLK_R
8409_ASP1_LRCLK_R
AUD_ASP2_SDIN
8409_I2C_SCL 8409_I2C_SDA
PP1V8_S0
CODEC_RESET_L
CODEC_INT_L
PP1V8_S0
CS8409_VA_PLL
HDA BRIDGE
BOM_COST_GROUP=AUDIO
SYNC_MASTER=AHAAGE SYNC_DATE=03/23/2016
72 51
72 51
13
13
13
13
402
CERM
10V
10%
BYPASS=U6200.B2:A1:5 MM
0.22UF
2
1
C6201
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6206
0201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
0
21
R6205
WLCSP
CS8409
C4
B2
E2
A6
B3
E6
A2
C1
A3
B4
D3
D4
A4
F1
F6
F5
D5
E5
C3A1A5
C2
D1
D2
E1
B1
F4
E3
F2
F3
E4
C6
B5
C5
B6
D6
U6200
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6204
0201
X5R
25V
10%
BYPASS=U6200.E2:C3:5 MM
0.1UF
2
1
C6202
0201
X5R
25V
10%
BYPASS=U6200.C4:C3:3 MM
0.1UF
2
1
C6203
603-1
X5R
25V
10%
BYPASS=U6200.A6:A5:3 MM
1UF
2
1
C6200
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6224
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6225
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6223
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6221
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6222
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6220
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6219
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6216
201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
33
21
R6217
49
49
0201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
0
21
R6229
0201
MF
1/20W
5%
PLACE_NEAR=U6200:10MM
0
21
R6228
50
50
50 49
50 49
50
50
50
50
402
X5R
6.3V
20%
CKPLUS_WAIVE=TERMSHORTED
4.7UF
2
1
C6299
72 51
49
72 51
201
MF
1/20W
5%
1.5K
2
1
R6227
201
MF
1/20W
5%
1.5K
2
1
R6226
0201
C0G
25V
5%
47PF
NOSTUFF
21
C6210
49
0201
C0G
25V
5%
47PF
NOSTUFF
21
C6209
0201
NP0-C0G
25V
5%
39PF
21
C6208
0201
C0G
25V
5%
47PF
NOSTUFF
21
C6207
0201
C0G
25V
5%
47PF
NOSTUFF
21
C6206
13
201
MF
1/20W
5%
47K
2
1
R6233
49
49
72 69 67 64 63 60 51 50 48
72 69 67 64 63 60 51 50 48
72 69 67 64 63 60 51 50 48
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
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PAGE TITLE
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A
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2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
IN
IN
IN
IN
IN
VL_SP
VL_HD
VA_PLL
VL_DM
ASP1_LRCK/FSYNC
GPIO2/CS2*
GPIO1/CS1*
GPIO0/MISO1
ASP2_LRCK/FSYNC
GPIO3/MISO2
ASP2_SDIN
ASP2_MCLK
ASP2_SCLK
ASP2_SDOUT
ASP1_SCLK
ASP1_MCLK
ASP1_SDIN
ASP1_SDOUT
SPI_SCLK
MOSI
GPIO6/SCL
GPIO7/SDA
GPIO4
GPIO5
GNDD
GND_PLL
GNDL
SYNC
BCLK
SDO
SDI
RST*
DMIC2_DATA
DMIC2_CLK
DMIC1_DATA
DMIC1_CLK
NC NC
NC NC
OUT
IN
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
NC
NC
NC
OUT
OUT
OUT
NC
NC
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
0X48 <--
I2C ADDR
0X49
1.8V
0X4B
AD0
1.8V1.8V
NOISE ISSUE SEEN ON EARLY HEADSETS
R/C6350 FILTER TO ADDRESS OUT-OF-BAND
(SEE RADAR # 6210118)
0X4A
APN:338S00142
GND
1.8V
LAST CHANGE: Mon Aug 8 12:54:34 2016
DESIGN: X502/MLB_CATZ
GND
GND
GND
AD1
49 OF 73
MIN_LINE_WIDTH=0.6000
63 OF 500
1.0.0
051-02265
GND_AUDIO_CODEC
L83_VP
AUD_HP_PORT_L
L83_1V8
L83_VCP
AUD_RING_SENSE
PP3V3_S0 L83_1V8
GND_AUDIO_CODEC
L83_GNDCP
L83_FLYC
L83_FLYP
L83_FLYN
L83_FILTP
L83_ASP_SDOUT_R
AUD_HP_PORT_CH_GND
AUD_PWR_EN
PP3V3_S0
GND_AUDIO_CODEC
AUD_ASP2_SDIN
L83_1V8
AUD_3V3_S0
HS_MIC_P
AUD_HP_PORT_R
GND_AUDIO_CODEC
L83_VCP_FILTP
L83_LDO_EN
L83_VL
L83_VCP_FILTN
AUD_HP_PORT_US_GND
AUD_HS_MIC_N
AUD_TIP_SENSE
L83_HSBIAS_FILT
AUD_ASP2_SCLK
L83_HSBIAS_FILT_REF
AUD_I2C_SCL
PP3V3_S0
CODEC_INT_L CODEC_WAKE_L CODEC_RESET_L
AUD_I2C_SDA
AUD_ASP2_LRCLK
HS_MIC_N
AUD_HS_MIC_P AUD_ASP2_SDOUT
JACK CODEC
BOM_COST_GROUP=AUDIO
SYNC_MASTER=AHAAGE SYNC_DATE=09/22/2015
51
51
WLCSP-SKT
CS42L83A
CRITICAL
C6
D7C4A3
A7
D6
B1
E4
D3
A5
B4
A6
A1
A2
G3
C5
E6
G6
B7
E1
D1
E3
F3
E2
F2
F4
F1
G4
G2
F5
D5
G5
E5
B3
G1
C7
B6
F6
D2
C2
E7
G7
F7
C1
D4
A4
B5
B2
C3
U6300
SM
PLACE_NEAR=U6300.F6:5MM
21
XW6302
0201
C0G
25V
5%
100PF
NOSTUFF
2
1
C6322
0201
C0G
25V
5%
100PF
NOSTUFF
2
1
C6321
402
X5R-CERM
10V
20%
BYPASS=U6300.G7:F7:3MM
2.2UF CRITICAL
21
C6307
402
X5R-CERM
10V
20%
BYPASS=U6300.E7:F7:3MM
2.2UF CRITICAL
21
C6306
0201
X7R-1
16V
10%
1000PF
2
1
C6320
50 48
201
MF
1/20W
5%
47K
2
1
R6300
201
MF
1/20W
5%
47K
2
1
R6301
0201
FERR-22-OHM-1A-0.055OHM
21
L6360
0201
FERR-470-OHM
CRITICAL
21
L6361
0201
FERR-22-OHM-1A-0.055OHM
21
L6302
0201
FERR-22-OHM-1A-0.055OHM
21
L6300
0201
FERR-22-OHM-1A-0.055OHM
21
L6301
402
X5R-CERM
10V
20%
BYPASS=U6300.D6:F6:5MM
2.2UF CRITICAL
21
C6301
0201
X5R
25V
10%
BYPASS=U6300.A3:B3:3 MM
0.1UF
CRITICAL
2
1
C6302
201
MF
1/20W
1%
1K
2
1
R6306
201
MF
1/20W
1%
1K
2
1
R6307
201
MF
1/20W
1%
2.2K
21
R6352
201
MF
1/20W
1%
2.2K
21
R6351
SM
PLACE_NEAR=U6360.B2:5MM
21
XW6301
50 48
48
48
48
48
48
48
201
MF
1/20W
5%
100K
NOSTUFF
2
1
R6360
51
51
0201
X7R-CERM
10V
10%
3300PF
CRITICAL
2
1
C6350
51
51
0201
C0G
25V
5%
27PF
CRITICAL
2
1
C6351
201
MF
1/20W
5%
100K
2
1
R6350
10UF
0402-7
X5R-CERM
10V
20%
BYPASS=U6300.D7:C7:3 MM
CRITICAL
2
1
C6303
0402
X5R-CERM
10V
20%
BYPASS=U6300.G6:F6:5MM
4.7UF CRITICAL
21
C6305
0402
X5R-CERM
10V
20%
BYPASS=U6300.E6:F6:5MM
4.7UF CRITICAL
21
C6304
0603-1
X5R
10V
20%
BYPASS=U6300.C1:C2:6MM
10UF
CRITICAL
2
1
C6308
402
X5R-CERM
10V
20%
BYPASS=U6300.B1:C2:5MM
2.2UF
CRITICAL
2
1
C6300
AUD_HP_SENSE_L
51
AUD_HP_SENSE_R
51
0201
X5R
10V
20%
BYPASS=U6360.A2:B2:3 MM
1UF
CRITICAL
2
1
C6361
0201
X5R
10V
20%
BYPASS=U6360.A1:B2:3 MM
1UF
CRITICAL
2
1
C6360
DSBGA
LP5907UVX-1.8
CRITICAL
A2A1
B1
B2
U6360
201
MF
1/20W
5%
PLACE_NEAR=U6300.A4:10MM
33
21
R6304
51
402
X5R
6.3V
20%
BYPASS=U6300.F3:E3:5MM
4.7UF
CRITICAL
21
C6309
51
49
49
69
64 63 60 59 54 49 46 45 42 38 49
49
19 16
69
64 63 60 59 54 49 46 45 42 38
49
49
49
69
64 63 60 59 54 49 46 45 42 38
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
HS4_REF
HPSENSB
HPOUTB
HPOUTA
HPSENSA
HSIN-
HS_CLAMP1
HSIN+
HS3
HS4
HS_CLAMP2
VD_FILT
-VCP_FILT
+VCP_FILT
FLYC
FLYN
FLYP
VP
ASP_LRCK/FSYNC
VL VA VCP
VL_SEL
RESET*
WAKE*
INT*
DIGLDO_PDN*
GNDCP
GNDHS GNDAGNDD
SPDIF_TX
SWIRE_SEL
SWIRE_SD/ASP_SDIN
ASP_SDOUT
SWIRE_CLK/ASP_SCLK
AD0
AD1
SDA
SCL
FILT_P
HS3_REF
RING_SENSE
TIP_SENSE
HSBIAS_FILT
HSBIAS_FILT_REF
GNDL
IN
BI
IN
IN
IN
OUT
IN
OUT
NC
OUT
OUT
IN
IN
IN
IN
GND
VOUT
VEN
VIN
NC
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
4X MONO SPEAKER AMPLIFIERS
GAIN: 0DBFS = 7VRMS
RIGHT BULK CAPACITANCE
FRONT LEFT AMPLIFIER
DESIGN: X502/MLB_CATZ LAST CHANGE: Mon Aug 8 19:33:56 2016
TDM SLOT
1 2
FRONT LEFT
3 4
0X2C
DVDD
PULL-UP
OPEN
LEFT BULK CAPACITANCE
REAR LEFT AMPLIFIER
I2C ADDR
0X28 0X2A
0X2E
REAR LEFT FRONT RIGHT REAR RIGHT
PULL-DOWN
FRONT RIGHT AMPLIFIER
APN: 353S00685
REAR RIGHT AMPLIFIER
50 OF 73
CRITICALCRITICAL
CRITICAL
CRITICALCRITICALCRITICAL
CRITICALCRITICAL
CRITICAL
CRITICAL
CRITICALCRITICAL
CRITICAL
CRITICALCRITICALCRITICAL
CRITICALCRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL CRITICAL
CRITICAL CRITICAL CRITICAL
CRITICAL
CRITICAL CRITICALCRITICAL CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICALCRITICAL
CRITICALCRITICAL
CRITICAL
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
DIFFERENTIAL_PAIR=DP_FR_SPK_OUT
DIDT=TRUE
DIFFERENTIAL_PAIR=DP_FR_SPK_OUT
DIDT=TRUE
DIFFERENTIAL_PAIR=DP_RR_SPK_OUT
DIDT=TRUE
DIFFERENTIAL_PAIR=DP_RR_SPK_OUT
DIDT=TRUE
DIFFERENTIAL_PAIR=DP_FL_SPK_OUT
DIDT=TRUE
DIFFERENTIAL_PAIR=DP_FL_SPK_OUT
DIDT=TRUE
DIDT=TRUE
DIFFERENTIAL_PAIR=DP_RL_SPK_OUT
DIDT=TRUE
DIFFERENTIAL_PAIR=DP_RL_SPK_OUT
DIDT=TRUE
DIDT=TRUE
64 OF 500
1.0.0
051-02265
AUD_ASP1B_SCLK AMP_FR_SCLK
AUD_ASP1A_SCLK AMP_RL_SCLK
PPBUS_G3H_SPKRL
PPBUS_G3H
TP_ISNS_SKPRLN
TP_ISNS_SKPRLP
PPBUS_G3H_SPKRL
SPKRAMP_FL_OUT_P
PPBUS_G3H
PPBUS_G3H
AUD_ASP1B_SDOUT
AUD_ASP1B_LRCLK
AMP_RR_LRCLK
PP1V8_S0
AUD_ASP1B_LRCLK
AUD_ASP1B_SDOUT
AMP_FR_SDOUT
AMP_FR_LRCLK
AUD_I2C_SCL AUD_I2C_SDA
AUD_I2C_SCL AUD_I2C_SDA
ADDR_RR
SPKRAMP_BSTN_4
SPKRAMP_RR_OUT_N
SPKRAMP_5V_4
SPKRAMP_RR_OUT_P
PPBUS_G3H
ADDR_FR
SPKRAMP_FR_OUT_P
SPKRAMP_FR_OUT_N
SPKRAMP_BSTP_4
SPKRAMP_BSTN_3
PP1V8_S0
SPKRAMP_5V_3
SPKRAMP_BSTP_3
SPKRCONN_FR_OUT_P
SPKRCONN_FR_OUT_N
SPKRCONN_RR_OUT_N
SPKRCONN_RR_OUT_P
PP1V8_S0
ADDR_FL
SPKRCONN_FL_OUT_N
AUD_I2C_SCL
AMP_FL_SDOUT
SPKRCONN_FL_OUT_P
SPKRAMP_5V_2
PP1V8_S0
SPKRAMP_RL_OUT_N
AUD_I2C_SCL
AMP_RL_SDOUT
ADDR_RL
SPKRAMP_BSTP_2
SPKRAMP_BSTN_2
AUD_I2C_SDA
SPKRAMP_5V_1
SPKRAMP_BSTP_1
SPKRAMP_BSTN_1
AUD_I2C_SDA
SPKRCONN_RL_OUT_P
SPKRCONN_RL_OUT_N
ADDR_FL
ADDR_FR
AUD_ASP1A_SDOUT
AUD_ASP1A_LRCLK
AUD_ASP1A_LRCLK
PP1V8_S0
ADDR_RL
ADDR_RR
PPBUS_G3H_SPKRL
AMP_FL_SCLKAUD_ASP1A_SCLK
AMP_RR_SCLKAUD_ASP1B_SCLK
SPKRAMP_RL_OUT_P
AMP_FL_LRCLK
AMP_RL_LRCLK
AMP_RR_SDOUT
SPKRAMP_FL_OUT_N
AUD_ASP1A_SDOUT
PPBUS_G3H_SPKRL
SYNC_DATE=03/23/2016SYNC_MASTER=AHAAGE
SPEAKER AMP
BOM_COST_GROUP=AUDIO
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6499
0612-6
MF
1W
0.5%
NO_XNET_CONNECTION=1
0.01
CRITICAL
43
21
R6499
50 49 48
50 49 48
50 49 48
50 49 48
50 49 48
50 49 48
50 49 48
50 49 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
201
MF
1/20W
5%
47K
21
R6482
201
MF
1/20W
5%
47K
21
R6480
0201
MF
1/20W
5%
0
21
R6441
201
MF
1/20W
5%
100
21
R6440
0201
MF
1/20W
5%
0
21
R6442
0201
MF
1/20W
5%
0
21
R6461
201
MF
1/20W
5%
100
21
R6460
0201
MF
1/20W
5%
0
21
R6462
0201
MF
1/20W
5%
0
21
R6422
201
MF
1/20W
5%
100
21
R6420
0201
MF
1/20W
5%
0
21
R6421
0201
MF
1/20W
5%
0
21
R6402
0201
MF
1/20W
5%
0
21
R6401
201
MF
1/20W
5%
100
21
R6400
603
X5R
25V
20%
NO_XNET_CONNECTION=1
BYPASS=U6440.A4:B4:3 MM
0.22UF
21
C6448
603
X5R
25V
20%
NO_XNET_CONNECTION=1
BYPASS=U6440.E4:D4:3 MM
0.22UF
21
C6447
603
X5R
25V
20%
NO_XNET_CONNECTION=1
BYPASS=U6460.A4:B4:3 MM
0.22UF
21
C6468
603
X5R
25V
20%
NO_XNET_CONNECTION=1
BYPASS=U6460.E4:D4:3 MM
0.22UF
21
C6467
603
X5R
25V
20%
NO_XNET_CONNECTION=1
BYPASS=U6420.A4:B4:3 MM
0.22UF
21
C6428
603
X5R
25V
20%
NO_XNET_CONNECTION=1
BYPASS=U6420.E4:D4:3 MM
0.22UF
21
C6427
603
X5R
25V
20%
NO_XNET_CONNECTION=1
BYPASS=U6400.A4:B4:3 MM
0.22UF
21
C6408
603
X5R
25V
20%
NO_XNET_CONNECTION=1
BYPASS=U6400.E4:D4:3 MM
0.22UF
21
C6407
0201
MF
1/20W
5%
0
NOSTUFF
21
R6481
0201
MF
1/20W
5%
0
21
R6483
72 51
72 51
0402
C0G-CERM
25V
5%
220PF
2
1
C6470
0402
C0G-CERM
25V
5%
220PF
2
1
C6469
0806
PLACE_NEAR=U6460.D4:5 MM
180OHM-3.4A
21
L6460
0805-1
X5R-CERM
25V
20%
PLACE_NEAR=U6460.C4:5.4 MM
22UF
CRITICAL
2
1
C6465
603-1
X5R
25V
10%
PLACE_NEAR=U6460.C4:3 MM
1UF
2
1
C6464
0402
X7R-CERM
16V
10%
PLACE_NEAR=U6460.C4:3 MM
0.1UF
2
1
C6463
402
X5R-CERM
10V
20%
BYPASS=U6460.A1:A2:5 MM
2.2UF
CRITICAL
2
1
C6462
0402
X7R-CERM
16V
10%
0.1UF
2
1
C6461
402-1
X5R
10V
10%
PLACE_NEAR=U6460.D1:3 MM
1UF
2
1
C6460
0806
PLACE_NEAR=U6460.D4:5 MM
180OHM-3.4A
21
L6461
WLCSP
SSM3515B
A1
D1
E1
B1
C1
C2
C4
C3
E3
A3
D4
D3
B4
B3
D2
E4
A4
E2
A2
B2
U6460
72 51
72 51
0402
C0G-CERM
25V
5%
220PF
2
1
C6430
0402
C0G-CERM
25V
5%
220PF
2
1
C6429
0806
PLACE_NEAR=U6420.D4:5 MM
180OHM-3.4A
21
L6420
0805-1
X5R-CERM
25V
20%
PLACE_NEAR=U6420.C4:3.6 MM
22UF
CRITICAL
2
1
C6425
603-1
X5R
25V
10%
PLACE_NEAR=U6420.C4:3 MM
1UF
2
1
C6424
0402
X7R-CERM
16V
10%
PLACE_NEAR=U6420.C4:3 MM
0.1UF
2
1
C6423
402
X5R-CERM
10V
20%
BYPASS=U6420.A1:A2:5 MM
2.2UF
CRITICAL
2
1
C6422
0402
X7R-CERM
16V
10%
0.1UF
2
1
C6421
402-1
X5R
10V
10%
PLACE_NEAR=U6420.D1:3 MM
1UF
2
1
C6420
0806
PLACE_NEAR=U6420.B4:5 MM
180OHM-3.4A
21
L6421
WLCSP
SSM3515B
A1
D1
E1
B1
C1
C2
C4
C3
E3
A3
D4
D3
B4
B3
D2
E4
A4
E2
A2
B2
U6420
WLCSP
SSM3515B
A1
D1
E1
B1
C1
C2
C4
C3
E3
A3
D4
D3
B4
B3
D2
E4
A4
E2
A2
B2
U6440
0806
PLACE_NEAR=U6440.B4:5 MM
180OHM-3.4A
21
L6441
402-1
X5R
10V
10%
PLACE_NEAR=U6440.D1:3 MM
1UF
2
1
C6440
0402
X7R-CERM
16V
10%
0.1UF
2
1
C6441
402
X5R-CERM
10V
20%
BYPASS=U6440.A1:A2:5 MM
2.2UF
CRITICAL
2
1
C6442
0402
X7R-CERM
16V
10%
PLACE_NEAR=U6440.C4:3 MM
0.1UF
2
1
C6443
603-1
X5R
25V
10%
PLACE_NEAR=U6440.C4:3 MM
1UF
2
1
C6444
0805-1
X5R-CERM
25V
20%
PLACE_NEAR=U6440.C4:4 MM
22UF
CRITICAL
2
1
C6445
0806
PLACE_NEAR=U6440.D4:5 MM
180OHM-3.4A
21
L6440
0402
C0G-CERM
25V
5%
220PF
2
1
C6449
0402
C0G-CERM
25V
5%
220PF
2
1
C6450
72 51
72 51
0402
C0G-CERM
25V
5%
220PF
2
1
C6409
0402
C0G-CERM
25V
5%
220PF
2
1
C6410
72 51
72 51
0806
PLACE_NEAR=U6400.B4:5 MM
180OHM-3.4A
21
L6401
0806
PLACE_NEAR=U6400.D4:5 MM
180OHM-3.4A
21
L6400
402
X5R-CERM
10V
20%
BYPASS=U6400.A1:A2:5 MM
2.2UF
CRITICAL
2
1
C6402
0402
X7R-CERM
16V
10%
PLACE_NEAR=U6400.D1:3 MM
0.1UF
2
1
C6401
402-1
X5R
10V
10%
PLACE_NEAR=U6400.D1:3 MM
1UF
2
1
C6400
603-1
X5R
25V
10%
PLACE_NEAR=U6400.C4:3 MM
1UF
2
1
C6404
0402
X7R-CERM
16V
10%
PLACE_NEAR=U6400.C4:3 MM
0.1UF
2
1
C6403
0805-1
X5R-CERM
25V
20%
PLACE_NEAR=U6400.C4:3 MM
22UF
CRITICAL
2
1
C6405
WLCSP
SSM3515B
A1
D1
E1
B1
C1
C2
C4
C3
E3
A3
D4
D3
B4
B3
D2
E4
A4
E2
A2
B2
U6400
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6494
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6493
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6492
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6491
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6490
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6495
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6485
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6484
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6483
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6482
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C6481
CRITICAL
CASE-B1S
TANT
16V
20%
33UF
2
1
C6480
50
72 69 68 63 60 58 53 50 43
50
72 69 68
63 60 58 53 50 43
72 69 68 63 60 58 53 50 43
72 69 67 64 63 60 51 50 48
50
72 69 68 63 60 58 53 50 43
50
72 69 67 64 63 60 51 50 48 72 69 67 64 63 60 51 50 48
50
72 69 67 64 63 60 51 50 48
50
50
50
72 69 67 64 63 60 51 50 48
50
50
50
50
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
IN
BI
IN
BI
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
SDA
BST-
BST+
ADDR
PVDD
BCLK
FSYNC
REG_EN
SDATA
SCL
OUT-
OUT-
OUT+
OUT+
VREG18/DVDD
AGND
PGND
PGND
VREG50/AVDD
PVDD
OUT
OUT
SDA
BST-
BST+
ADDR
PVDD
BCLK
FSYNC
REG_EN
SDATA
SCL
OUT-
OUT-
OUT+
OUT+
VREG18/DVDD
AGND
PGND
PGND
VREG50/AVDD
PVDD
SDA
BST-
BST+
ADDR
PVDD
BCLK
FSYNC
REG_EN
SDATA
SCL
OUT-
OUT-
OUT+
OUT+
VREG18/DVDD
AGND
PGND
PGND
VREG50/AVDD
PVDD
OUT
OUTOUT
OUT
SDA
BST-
BST+
ADDR
PVDD
BCLK
FSYNC
REG_EN
SDATA
SCL
OUT-
OUT-
OUT+
OUT+
VREG18/DVDD
AGND
PGND
PGND
VREG50/AVDD
PVDD
合肥怡飞苹果维修qq:82669515 qq群: 241000
RIGHT SPEAKER CONNECTOR
LAST CHANGE: Mon Aug 8 12:54:34 2016
DESIGN: X502/MLB_CATZ
APN: 516S1064
860-00382
COWLING BOSSES
AUDIO FLEX CONNECTOR
LEFT SPEAKER CONNECTOR
APN: 518S00019
APN: 518S00019
51 OF 73
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.4000
66 OF 500
1.0.0
051-02265
AUD_CONN_SLEEVE_XW
SPKRCONN_RL_OUT_P
SPKRCONN_RL_OUT_N
8409_SPKR_ID0
SPKRCONN_FL_OUT_P
SPKRCONN_FL_OUT_N
AUD_CONN_HP_RIGHT
SPKRCONN_RR_OUT_N
SPKRCONN_RR_OUT_P
SPKRCONN_FR_OUT_N
SPKRCONN_FR_OUT_P
8409_SPKR_ID1
PP1V8_S0
PP1V8_S0
AUD_CONN_SLEEVE
PP3V3_G3H
AUD_CONN_HP_LEFT
AUD_CONN_SLEEVE
AUD_CONN_RING2
AUD_CONN_SLEEVE
AUD_CONN_HP_RIGHT
AUD_CONN_RING2
AUD_CONN_SLEEVE_XW
DMIC1_DATA
HALL_SENSOR_RIGHT
AUD_CONN_RING2_XW
DMIC1_CLK
AUD_CONN_HP_SENSE_R
AUD_CONN_TIP_SENSE
AUD_CONN_HP_SENSE_L
AUD_CONN_RING2
AUD_CONN_RING2_XW
AUD_CONN_HP_SENSE_L
AUD_CONN_HP_SENSE_R
AUD_CONN_HP_LEFT
AUD_CONN_TIP_SENSE
AUD_HS_MIC_P
AUD_HP_PORT_US_GND
AUD_HS_MIC_N
AUD_HP_SENSE_L
AUD_HP_SENSE_R
AUD_HP_PORT_L
AUD_TIP_SENSE
AUD_RING_SENSE
AUD_HP_PORT_CH_GND
AUD_HP_PORT_R
AUD_CONN_HP_RIGHT
AUD_CONN_HP_LEFT
PP1V8_S0
SYNC_DATE=07/21/2015SYNC_MASTER=AHAAGE
JACK TRANSLATORS
BOM_COST_GROUP=AUDIO
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6620
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6621
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6622
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6623
72 48
201
MF
1/20W
5%
47K
2
1
R6630
72 48
201
MF
1/20W
5%
47K
2
1
R6620
0201
CERM
25V
5%
12PF
2
1
C6612
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6613
0201
CERM
25V
5%
12PF
2
1
C6616
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6617
0201
X5R-CERM
10V
10%
0.1UF
2
1
C6601
0201
CERM
25V
5%
12PF
2
1
C6602
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6603
0201
X5R-CERM
10V
10%
0.1UF
2
1
C6605
0201
CERM
25V
5%
12PF
2
1
C6606
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6607
F-RT-SM1
FF14A-14C-R11DL-B-3H
CRITICAL
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
15
J6603
F-RT-SM1
FF14A-14C-R11DL-B-3H
CRITICAL
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
15
J6602
3.5OD1.85ID-1.92H-SM
1
SH6600
0201
MF
1/20W
5%
0
2
1
R6610
201
MF
1/20W
1%
2K
21
R6611
F-ST-SM
51338-0374
CRITICAL
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
J6600
72 50
72 50
72 50
72 50
49
49
0402
120-OHM-25%-1.3A
CRITICAL
21
L6605
0402
120-OHM-25%-1.3A
CRITICAL
21
L6604
0402
120-OHM-25%-1.3A
CRITICAL
21
L6603
0402
120-OHM-25%-1.3A
CRITICAL
21
L6602
0402
120-OHM-25%-1.3A
CRITICAL
21
L6601
0402
120-OHM-25%-1.3A
CRITICAL
21
L6600
49
49
0402
120-OHM-25%-1.3A
CRITICAL
21
L6606
0402
120-OHM-25%-1.3A
CRITICAL
21
L6608
49
49
49
49
49
49
72 50
72 50
72 50
72 50
72 51
72 51
72 69 67 64 63 60 51 50 48
72 69 67 64 63 60 51 50 48
72 51
72
69 68 60 53 52 47 42 41 28 19
72 51
72 51
72 51
72 51
72 51
72 51
72 51
72 48
72 41
72 51
72 48
72 51
72 51
72 51
72 51
72 51
72 51
72 51
72 51
72 51
72 51
72 51
72 69 67 64 63 60 51 50 48
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
POR BMU LOGIC CONNECTOR
152S1872
<Rb>
<Ra>
(Switcher limit)
300MA MAX OUTPUT
3.3V "G3HOT" SUPPLY
BMU power flex is soldered to MLB.998-03828
VOUT = 1.0V * (1 + RA / RB)
POR BATTERY (BMU) FLEX SOLDER PADS.
518S00014
VOUT = 3.373V
52 OF 73
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1500MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
69 OF 500
1.0.0
051-02265
=SMBUS_BATT_SCL =SMBUS_BATT_SDA
PPDCIN_G3H_CHGR PPDCIN_G3H_CHGR_R
=PPBUS_G3H
V3V3G3H_SW PP3V3_G3H
AGND_P3V3G3H
V3V3G3H_FB_R2
V3V3G3H_BIAS
V3V3G3H_FB_R
V3V3G3H_BST_R
AGND_P3V3G3H
PM_EN_P3V3_G3H_R
PM_EN_P3V3_G3H
PPVIN_G3H_P3V3G3H
PP3V3_G3H_VR
V3V3G3H_FB
V3V3G3H_BOOST
SYS_DETECT_L
PPBUS_G3H_R
PPVBAT_G3H_CONN
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
BOM_COST_GROUP=PLATFORM POWER
DC-IN & BATTERY CONNECTORS
J69501632-00731 PCBA,FLEX,BMU PWR,X502 CRITICAL
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6962
0201
C0G
25V
+/-0.1PF
3PF
2
1
C6961
402
MF-LF
1/16W
5%
0
21
R6906
PIYA25201B-SM
10UH-20%-1.4A-0.399OHM
CRITICAL
21
L6995
402
MF-LF
1/16W
5%
0
21
R6999
HB-SM
PWR-MLB-X520
CRITICAL
12
11 10
9
8
7
6
54
3
2
1
J6950
F-RT-SM-A
FF18-10A-R11AD-B-3H
CRITICAL
10
9
8
7
6
5
4
3
2
1
12
11
J6951
0201
MF
1/20W
5%
0
2 1
R6991
SLP1006N3T
RCLAMP3552T
CRITICAL
2
1
3
D6950
53
0402-7
X5R-CERM
10V
20%
10UF
CRITICAL
2
1
C6988
0402-7
X5R-CERM
10V
20%
10UF
CRITICAL
2
1
C6989
201
MF
1/20W
1%
1.47K
2
1
R6993
SOT-323
BAT30CWFILM
CRITICAL
3
2
1
D6905
0201
C0G
25V
+/-0.1PF
5.6PF
2
1
C6992
201
MF
1/20W
5%
10
V3V3G3H_FB_XW
2
1
R6997
SM
2
1
XW6995
SM
21
XW6990
0402
X5R-CERM
35V
20%
2.2UF
CRITICAL
2
1
C6990
0402
X5R-CERM
35V
20%
2.2UF
CRITICAL
2
1
C6991
TDFN
MAX77596
CRITICAL
11
2
6
4
9
7
3
10
1
8
5
U6990
603
CERM-X7R
16V
10%
0.33UF
2
1
C6993
0201
MF
1/20W
5%
0
2
1
R6994
0201
X5R-CERM
16V
10%
0.1UF
2
1
C6994
0201
MF
1/20W
0.1%
47K
CRITICAL
2
1
R6996
0201
MF
1/20W
0.1%
115K
CRITICAL
2
1
R6995
0402-7
X5R-CERM
10V
20%
10UF
CRITICAL
2
1
C6997
0402-7
X5R-CERM
10V
20%
10UF
CRITICAL
2
1
C6996
0402-7
X5R-CERM
10V
20%
10UF
CRITICAL
2
1
C6998
0402-7
X5R-CERM
10V
20%
10UF
CRITICAL
2
1
C6995
402
MF-LF
1/16W
5%
10K
2
1
R6950
603-1
X5R
25V
10%
1UF
2
1
C6960
402
X5R
25V
10%
0.1UF
2
1
C6950
805
MF-LF
1/8W
5%
2.2
21
R6905
42
42
72 53
69 32 31
72
69 68 60 53 51 47 42 41 28 19
52
53
72
63 53
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
NC
NC
NC
NC
IN
EPAD
AGND
PGND
EN
MODE
SUP
RESET* BIAS
OUT/FB
LX
BST
合肥怡飞苹果维修qq:82669515 qq群: 241000
FROM USB-C SOURCE
353S01016
LAST CHANGE: Mon Aug 8 12:54:34 2016
(AMON)
L: 2-CELL
H: 3-CELL
DESIGN: X502/MLB_CATZ
(BMON)
TO/FROM BATTERY
TO SYSTEM
(PBUS)
53 OF 73
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.4000
DIDT=TRUE GATE_NODE=TRUE
DIDT=TRUE GATE_NODE=TRUE
DIDT=TRUE GATE_NODE=TRUE
DIDT=TRUE GATE_NODE=TRUE
SWITCH_NODE=TRUEDIDT=TRUE
SWITCH_NODE=TRUEDIDT=TRUE
DIDT=TRUE SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1500
DIDT=TRUE SWITCH_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE SWITCH_NODE=TRUE SWITCH_NODE=TRUE
DIDT=TRUE
DIDT=TRUE SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1800
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1500
70 OF 500
1.0.0
051-02265
PPDCIN_G3H
TBA_CSI_P
TBA_GATE_Q1
TBA_GATE_Q2
TBA_BGATE
PD_TBA_MPM_DET
PD_TBA_SGATE
TBA_GATE_Q3
TBA_CSI_N
TBA_GATE_Q4
TBA_BOOT1
PPVIN_G3H_P3V3G3H
TBA_AUX_DET
=SMB_SMC_CHGR_SDA
TBA_LX1
SMC_RST_IN
TBA_LX2
SMC_RESET_R_L
SMC_MPM_OK
=CHGR_ACOK
SMC_CHGR_INT_L
PPVBAT_G3H_CONN
PM_EN_P3V3_G3H
TBA_COMP
TBA_BOOT1_RC TBA_BOOT2_RC
PPBUS_G3H
SMC_CBC_ON
CHGR_AMON CHGR_BMON
SMC_RESET_L
=SMB_SMC_CHGR_SCL
TBA_VDDA
PP3V3_G3H
TBA_CSIR_P
TBA_CSOR_NTBA_CSOR_P
TBA_PHASE1 TBA_PHASE2
SMC_AUX_OK
TBA_BOOT2
TBA_VDDA TBA_VDDP
TBA_CSO_NTBA_CSO_P
PPVBAT_G3H_CHGR_REG
PPDCIN_G3H_CHGR
TBA_HPWR_EN_L
PP3V3_G3H
PD_TBA_AGATE
TBA_CSIR_N
PPVBAT_G3H_CHGR_R
BOM_COST_GROUP=PLATFORM POWER
PBUS Supply & Battery Charger
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
IND,MLD,2.7UH,19.6MO,12.5A,10.9X10X2.4MM L70301152S00198 CRITICAL
0201
C0G
25V
+/-0.1PF
3PF
2
1
C7069
0201
C0G
25V
+/-0.1PF
3PF
2
1
C7029
201
MF
1/20W
5%
10K
2
1
R7076
201
MF
1/20W
5%
10K
2
1
R7077
201
MF
1/20W
5%
100K
21
R7073
201
5%
1K
21
R7072
40
0201
0
21
R7071
0201
0
NOSTUFF
21
R7070
0402
X5R-CERM
35V
20%
2.2UF
CRITICAL
2
1
C7078
0201
X7R
25V
10%
1000PF
2
1
C7055
0402-1
X5R-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7054
0201
X5R
25V
10%
0.1UF
2
1
C7060
201
CERM-X5R-1
4V
20%
NO_XNET_CONNECTION=1
0.47UF
21
C7020
201
CERM-X5R-1
4V
20%
NO_XNET_CONNECTION=1
0.47UF
21
C7023
0201
X7R
25V
10%
1000PF
2
1
C7064
201
MF
1/20W
5%
4.7
21
R7075
43
43
WCSP-4
ISL9239
CRITICAL
G2
H4
F5
D2
A2
C3
B2
G5
H5
E2
A3
B5
A5
F4
E4
B1
G1
H3
G3
A1
D1
E1
H1
F2
A4
B4
D5
C5
E5
G4
H2
C1
F1
C4
B3
F3
D3
D4
E3
C2
U7000
CASE-D2E-SM
POLY-TANT
16V
20%
68UF
CRITICAL
2
1
C7051
41
41 39
41 39
68 66 47
42
42
52
402
CERM-X5R
10.0V
10%
0.12UF
2
1
C7071
0201
X5R
10V
20%
1UF
CRITICAL
2
1
C7080
0603-1
X5R
10V
20%
10UF
CRITICAL
2
1
C7077
0402-1
X5R-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7075
402
CERM-X5R
10.0V
10%
0.12UF
NOSTUFF
2
1
C7070
0201
X5R-CERM
25V
10%
0.01UF
NOSTUFF
2
1
C7016
201
MF
1/20W
1%
255K
2
1
R7016
201
MF
1/20W
1%
750K
2
1
R7015
0201
CER-X5R
25V
10%
4700PF
2
1
C7063
0402
CER-X7R
50V
10%
0.047UF
2
1
C7061
0402
CER-X7R
50V
10%
0.047UF
2
1
C7062
0201
MF-LF
1/20W
1%
1.00
2
1
R7061
0201
MF-LF
1/20W
1%
1.00
2
1
R7062
0402-1
X5R-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7065
0402-1
X5R-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7066
0201
X5R
25V
10%
0.1UF
CRITICAL
2
1
C7067
0201
X5R-CERM
25V
10%
0.01UF
CRITICAL
2
1
C7068
0612-5
MF
1W
1%
0.005
CRITICAL
43
21
R7060
SO-8
SI7137DP
CRITICAL
3
2
1
4
5
Q7065
402
MF-LF
1/16W
5%
0
2
1
R7040
0402
X7R-CERM-1
25V
10%
0.1UF
CRITICAL
2
1
C7040
402
MF-LF
1/16W
5%
0
2
1
R7030
0402
X7R-CERM-1
25V
10%
0.1UF
CRITICAL
2
1
C7030
1206
12AMP-32V
CRITICAL
21
F7000
CASE-D2E-SM
POLY-TANT
16V
20%
68UF
CRITICAL
2
1
C7050
0402-1
X5R-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7053
0402
X5R-CERM
35V
20%
2.2UF
CRITICAL
2
1
C7035
0402
X5R-CERM
35V
20%
PLACE_NEAR=Q7030.2:2MM
2.2UF
CRITICAL
2
1
C7036
0402
X5R-CERM
35V
20%
PLACE_NEAR=C7036.1:3MM
2.2UF
CRITICAL
2
1
C7037
CASE-B1-2-SM
POLY-TANT
35V-0.09OHM
20%
6.8UF
CRITICAL
2
1
C7025
CASE-B1-2-SM
POLY-TANT
35V-0.09OHM
20%
6.8UF
CRITICAL
2
1
C7026
CASE-B1-2-SM
POLY-TANT
35V-0.09OHM
20%
6.8UF
CRITICAL
2
1
C7027
CASE-B1-2-SM
POLY-TANT
35V-0.09OHM
20%
6.8UF
CRITICAL
2
1
C7028
CASE-B1-2-SM
POLY-TANT
35V-0.09OHM
20%
6.8UF
CRITICAL
2
1
C7032
CASE-B1-2-SM
POLY-TANT
35V-0.09OHM
20%
PLACE_NEAR=Q7030.2:3MM
6.8UF
CRITICAL
2
1
C7033
0402
X5R-CERM
35V
20%
PLACE_NEAR=C7036.1:3MM
2.2UF
CRITICAL
2
1
C7034
0402
CER-X7R
50V
10%
0.047UF
2
1
C7022
0402
CER-X7R
50V
10%
0.047UF
2
1
C7021
0201
MF-LF
1/20W
1%
1.00
2
1
R7022
0201
MF-LF
1/20W
1%
1.00
2
1
R7021
201
MF
1/20W
5%
10K
2
1
R7008
DFN
FDMD8800
CRITICAL
1465
1098
7
4
11
12
1332
1
Q7040
DFN
FDMD8800
CRITICAL
14
6
5
10
9
8
7
4
11
12
13
3
2
1
Q7030
0306
MF
0.5W
0.5%
0.01
CRITICAL
34
12
R7020
IHLP4040BD-PIMA102D-COMBO
2.7UH-0.0196OHM-13.5A
CRITICAL
OMIT_TABLE
21
L7030
72 69 68 63
52
63 52
72 69 68 63 60 58 50 43
53
72 69
68 60 53 52 51 47 42 41 28 19
53
72 52
72
72 69
68 60 53 52 51 47 42 41 28 19
63
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
OUT
OUT
SGATE
PGND
AGND
VDDP
VDDA
BMON
AMON
AUX_OK
MPM_OK
CBC_ON
IRQ*
VBAT
EN_VR1
SMC_RST*
BGATE
CSON
CSOP
BOOT2
LX2
GATE_Q3
GATE_Q2
LX1
BOOT1
GATE_Q1
CELL
MPM_DET
AGATE
AUX_DET
MPM_PBUS
CSIP
VR1_3P3
SDA
SCL
SMC_RST_IN
HPWR_EN*
COMP
P_IN
GATE_Q4
PBUS
CSIN
IN
OUT
OUT
OUT
BI
IN
OUT
S
SYM-VER-2
D
G
S1/D2
D1
S2
G1
G1R
G2
S1/D2
D1
S2
G1
G1R
G2
合肥怡飞苹果维修qq:82669515 qq群: 241000
LAST CHANGE: Thu Aug 4 21:00:42 2016
(GTVR_IMON)(CPUVR_IMON)
DESIGN: X502/MLB_CATZ
353S00444
54 OF 73
71 OF 500
1.0.0
051-02265
CPUVR_ISUM_N
CPUVR_ISUM_P
SAVR_RTN
CPUVR_COMP
GTVR_ISEN3
CPUVR_FB
PM_PGOOD_CPUVCC
GTVR_ISEN1
GTVR_ISEN2
SAVR_FCCM
CPU_VCCSENSE_P
PM_PGOOD_CPUVCC
GTVR_ISUM_P
GTVR_RTN
PROG5
PROG3
PM_EN_CPUVCC_R
CPUVR_AGND
CPU_VCCSENSE_N
CPUVR_FB_R_1
CPUVR_FB_R_2
CPUVR_FB_R_3
PROG4
GTVR_COMP
CPU_VCCGTSENSE_N
CPUVR_AGND
GTVR_FB_L_2
GTVR_FB_L_3
CPU_VCCSASENSE_P
SAVR_RTN
VR_HOT_L
PROG1
CPUVR_FB
CPU_VCCSASENSE_N
CPUVR_COMP
GTVR_RTN
CPUVR_AGND
CPUVR_AGND
=PP1V_S3_CPU_VCCST
SAVR_ISUM_N
CPUVR_AGND
GTVR_FCCM
GTVR_PWM1
CPU_PROCHOT_L
PM_EN_CPUVCC
GTVR_PWM2
CPUVR_AGND
CPUVR_PWM1
GTVR_ISUMN_R
GTVR_FB_L_1
GTVR_FB
GTVR_ISUM_P
CPUVR_AGND
GTVR_NTC_R
CPUVR_AGND
PP3V3_S0
ISUMN_B_L_1
SAVR_COMP_L
GTVR_COMP_L
SAVR_COMP
CPUVR_ISUMN_R
CPUVR_AGND
CPUVR_AGND
CPUVR_AGND
CPUVR_AGND
CPUVR_AGND
CPUVR_AGND
CPUVR_AGND
SAVR_FB_L_1
SAVR_FB_L_2
CPUVR_AGND
CPUVR_COMP_R
SAVR_FB_L_3
SAVR_ISUMN_R
CPU_VIDSCLK
CPU_VIDSOUT
CPU_VIDALERT_L
ISUMN_C_L_1
GTVR_FB
GTVR_ISUM_N
CPUVR_AGND
PROG2
SAVR_FB
MAKE_BASE=TRUE
GND
GTVR_ISEN3
CPU_VCCGTSENSE_P
SAVR_PWM
CPUVR_FCCM
ISUMN_A_R
CPUVR_AGND
CPUVR_AGND
CPUVR_RTN
GTVR_IMON
CPUVR_IMON
CPUVR_NTC_L
CPUVR_NTC
CPUVR_AGND
SAVR_COMP
SAVR_ISUM_P
GTVR_ISEN1
GTVR_PWM3
CPUVR_VCC
PPBUS_G3H_CPU
PP5V_S4
PP5V_S0
CPUVR_VIN
CPUVR_RTN
CPUVR_AGND
CPUVR_AGND
SCLK
PSYS
SDA
SAVR_ISUM_P
CPUVR_ISUM_P
CPUVR_ISUMN_R
CPUVR_PWM2
CPUVR_AGND
GTVR_ISUMN_R
GTVR_ISEN2
GTVR_COMP
GTVR_NTC
ALERT_L
CPUVR_ISEN1
CPUVR_ISEN2
CPUVR_ISEN1
SAVR_ISUMN_R
SAVR_IMON
SAVR_FB
CPUVR_ISEN2
BOM_COST_GROUP=CPU & CHIPSET
VReg CPU VCC Cntl
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
201
MF
1/20W
5%
1
2
1
R7192
201
MF
1/20W
1%
1K
21
R7154
0201
X7R-CERM
10V
10%
NO_XNET_CONNECTION=1
0.01UF
2
1
C7105
57 54
SM
2 1
XW7121
SM
21
XW7133
SM
21
XW7116
57
0201
X7R-CERM
10V
10%
0.01UF
2
1
C7139
0201
X7R-CERM
10V
10%
NO_XNET_CONNECTION=1
0.01UF
2
1
C7137
0201
X7R-CERM
10V
10%
NO_XNET_CONNECTION=1
0.01UF
2
1
C7138
0201
X7R-CERM
10V
10%
3300PF
21
C7136
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
1K
21
R7160
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
226
21
R7161
201
X7R-CERM
25V
10%
NO_XNET_CONNECTION=1
220PF
2
1
C7141
55 54
55 54
55
55 54
0201
X7R-CERM
10V
10%
3300PF
21
C7123
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
1K
21
R7129
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
422
21
R7127
0201
X7R-CERM
10V
10%
0.01UF
2
1
C7124
201
X7R-CERM
25V
10%
NO_XNET_CONNECTION=1
220PF
2
1
C7125
56
56 54
0201
X7R-CERM
10V
10%
0.01UF
2
1
C7106
0201
X7R-CERM
10V
10%
NO_XNET_CONNECTION=1
0.01UF
2
1
C7110
0201
X7R-CERM
10V
10%
NO_XNET_CONNECTION=1
0.01UF
2
1
C7109
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
1K
2 1
R7108
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
332
2 1
R7105
0201
X7R-CERM
10V
10%
3300PF
2 1
C7103
201
X7R-CERM
25V
10%
NO_XNET_CONNECTION=1
220PF
2
1
C7104
57 54
57 54
57
57 54
201
MF
1/20W
1%
4.99K
21
R7158
0201
X7R-CERM
10V
10%
6800PF
21
C7134
0201
C0G
25V
5%
68PF
2
1
C7119
201
MF
1/20W
1%
147K
2
1
R7122
0201
X7R-CERM
25V
10%
150PF
2
1
C7111
201
MF
1/20W
1%
86.6K
2
1
R7111
201
MF
1/20W
1%
95.3K
2
1
R7151
0201
X7R-CERM
25V
10%
150PF
2
1
C7129
60
60 54
0201
X7R-CERM
10V
10%
6800PF
21
C7114
0201
X7R-CERM
25V
10%
150PF
21
C7115
56
0201
C0G
25V
5%
68PF
21
C7135
201
MF
1/20W
1%
4.99K
21
R7117
0201
100KOHM
CRITICAL
21
RT7101
0201
X7R
25V
10%
1000PF
2
1
C7130
201
MF
1/20W
1%
560
2
1
R7152
0201
X7R-CERM
25V
10%
680PF
2
1
C7112
201
MF
1/20W
1%
453
2
1
R7110
0201
X7R-CERM
25V
10%
820PF
2
1
C7120
201
MF
1/20W
1%
560
2
1
R7121
201
MF
1/20W
5%
10K
2
1
R7140
0201
X7R-CERM
10V
10%
6800PF
21
C7108
0201
C0G
25V
5%
68PF
21
C7107
0201
X7R
16V
10%
330PF
2
1
C7117
201
MF
1/20W
1%
1K
2 1
R7113
201
MF
1/20W
1%
49.9
21
R7139
201
MF
1/20W
5%
10
21
R7145
0201
MF
1/20W
5%
0
21
R7142
0201
X7R
16V
10%
330PF
2
1
C7121
8
55
55
8
0201
X7R
16V
10%
330PF
2
1
C7133
72 8
0201
X7R
16V
10%
330PF
2
1
C7116
68 40 39 6
8
8
0402-1
X7R
25V
10%
0.22UF
2
1
C7101
201
MF
1/20W
1%
100K
2
1
R7136
201
MF
1/20W
1%
182K
2
1
R7135
201
MF
1/20W
1%
1.87K
2
1
R7134
201
MF
1/20W
1%
63.4K
2
1
R7133
201
MF
1/20W
1%
78.7K
2
1
R7132
201
MF
1/20W
1%
2.15K
21
R7123
201
MF
1/20W
1%
2.67K
2 1
R7112
201
MF
1/20W
1%
2.49K
21
R7109
57
57
57
56
55
8
0201
MF
1/20W
5%
0
21
R7148
0201
MF
1/20W
5%
0
21
R7147
201
MF
1/20W
5%
10
2
1
R7101
8
8
8
201
MF
1/20W
1%
PLACE_NEAR=U7100.45:12.7MM
45.3
2
1
R7138
201
MF
1/20W
1%
PLACE_NEAR=U7100.44:12.7MM
100
NOSTUFF
2
1
R7141
201
MF
1/20W
1%
PLACE_NEAR=U7100.43:12.7MM
100
2
1
R7144
0402
X6S
25V
10%
1.0UF
CRITICAL
2
1
C7102
201
MF
1/20W
5%
1
NOSTUFF
2
1
R7102
0201
X7R
16V
10%
330PF
2
1
C7122
0201
X7R-CERM
10V
10%
3300PF
2 1
C7118
201
MF
1/20W
1%
2.15K
21
R7120
0201
MF
1/20W
5%
0
21
R7124
0201
X7R
16V
10%
330PF
2
1
C7132
0201
MF
1/20W
5%
0
2 1
R7155
0201
X7R-CERM
10V
10%
3300PF
21
C7131
201
MF
1/20W
1%
1.43K
2 1
R7153
201
MF
1/20W
1%
13.7K
21
R7150
0201
MF
1/20W
5%
0
2 1
R7114
0201
X7R-CERM
25V
10%
680PF
21
C7113
0201
100KOHM
CRITICAL
21
RT7100
201
MF
1/20W
1%
13.7K
21
R7116
201
MF
1/20W
1%
12.1K
21
R7137
201
X7R
10V
10%
4700PF
2
1
C7127
LLP
ISL95828HRTZ
CRITICAL
35 47
46
48
41
42
49
43
4531
6 18
27
13 26
12 25
1
36
37
38
39
40
3 15
32
7 19
33
8 20
23
10 22
9 21
28
2 14
34
11 24
30
5 17
29
4 16
44
U7100
54
54
54
60 54
57 54
54
54
54
54
54
54
54
54
54
54
69 59 19 14 10 8 6
54
54
54
54
54
54
69 64 63 60 59 49 46 45 42 38
54
54
54
54
54
54
54
54
54
54
54
54
54
54
57 54
54
54
54
45
45
54
54
56 54
57 54
63 62 61 59 57 56 55 43
72 69 64 63 60 58
72 69 64 59 57 56 55
54
54
54
55 54
54
54
54
57 54
54
55 54
55 54
54
45
54
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUTOUT
IN
OUT
OUT
IN
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
BI
OUT
IN
PWM3_A
PROG4
PROG3
PROG5
PROG2
PROG1
IMON_C
THRM_PAD
PSYS
RTN_C
FB_C
COMP_C
ISUMN_C
ISUMP_C
FCCM_C
PWM_C
NTC_B
IMON_B
RTN_B
FB_B
COMP_B
ISEN2_B
ISEN1_B
ISUMN_B
ISUMP_B
PWM2_B
PWM1_B
FCCM_B
SCLK
SDA
ALERT*
VR_ENABLE
VR_READY
VR_HOT*
NTC_A
IMON_A
RTN_A
FB_A
COMP_A
ISEN3_A
ISEN1_A
ISEN2_A
ISUMP_A
ISUMN_A
PWM1_A
PWM2_A
FCCM_A
VIN
VCC
合肥怡飞苹果维修qq:82669515 qq群: 241000
CPU VCC Phase 1
LAST CHANGE: Thu Aug 4 21:00:42 2016
DESIGN: X502/MLB_CATZ
CPU VCC Phase 2
55 OF 73
DIDT=TRUE
MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
DIDT=TRUE
MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000
DIDT=TRUE
MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000
DIDT=TRUE
MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.2000
DIDT=TRUE
MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
DIDT=TRUE
MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000
DIDT=TRUE
MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.2000
DIDT=TRUE
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000
72 OF 500
1.0.0
051-02265
PPBUS_G3H_CPU
PPBUS_G3H_CPU
CPUVR_ISUM_N
AGND_U7320
CPUVR_PHASE1
CPUVR_ISNS1_N
PPVCCCPU_S0G
PPVCCCPU_S0G_PH1
CPUVR_SNB1
AGND_U7310
TP_CPUVR_GH1
TP_CPUVR_GL1
TP_CPUVR_GH2
TP_CPUVR_GL2
CPUVR_BP1
CPUVR_ISNS2_N
CPUVR_BP2 CPUVR_SNB2
PPVCCCPU_S0G_PH2
CPUVR_ISUM_P
CPUVR_ISUM_N
CPUVR_ISNS1_N
CPUVR_ISNS2_N
CPUVR_ISEN1
CPUVR_ISEN2
CPUVR_ISNS2_P
CPUVR_PHASE2
CPUVR_BOOT2
CPUVR_PWM1
CPUVR_FCCM
VCINP_P5V_U7310
PP5V_S0
CPUVR_PWM2
CPUVR_FCCM
VCINP_P5V_U7320
CPUVR_ISUM_P
CPUVR_ISNS1_P
CPUVR_SW2
PP5V_S0
CPUVR_SW1
CPUVR_BOOT1
BOM_COST_GROUP=CPU & CHIPSET
CPU IMVP VCC & VCCSA
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
IC,SIC635,DR MOS,IMVP-8,40A,PQFN31,5X5 U7210,U7220,U7410,U7420,U74305353S00497 CRITICAL
0402
X7R-CERM-1
25V
10%
0.1UF
CRITICAL
2
1
C7218
402
MF-LF
1/16W
1%
4.99
NOSTUFF
2
1
R7215
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7222
PQFN-COMBO
FDMF5808A
CRITICAL
OMIT_TABLE
9
8
3
24
16
1
29
7
28
12
31
30 33
27
6
2
5
32
4
U7220
PQFN-COMBO
FDMF5808A
CRITICAL
OMIT_TABLE
9
8
3
24
16
1
29
7
28
12
31
30 33
27
6
2
5
32
4
U7210
SM
21
XW7210
SM
21
XW7220
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7224
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7224
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7214
402
MF-LF
1/16W
1%
4.99
NOSTUFF
2
1
R7214
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7226
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7227
402
MF-LF
1/16W
5%
1
2 1
R7226
402
MF-LF
1/16W
5%
1
2 1
R7216
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7212
54
55 54
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
21
R7227
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
21
R7217
0201
X7R
25V
10%
1000PF
2
1
C7215
0201
X7R
25V
10%
1000PF
2
1
C7225
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7230
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7231
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7240
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7241
0612-1
MF
1W
1%
NO_XNET_CONNECTION
0.00075
CRITICAL
3 4
1 2
R7220
201
MF
1/20W
1%
NO_XNET_CONNECTION
1K
2
1
R7222
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
2
1
R7223
55 54
54
201
MF
1/20W
1%
NO_XNET_CONNECTION
2.2
2
1
R7221
55 54
72 55 45
72 45
45
55 45
0402-1
X7R
25V
10%
0.22UF
2
1
C7229
402
MF-LF
1/16W
5%
0
2
1
R7229
402
MF-LF
1/16W
5%
0
2
1
R7219
0402-1
X7R
25V
10%
0.22UF
2
1
C7219
54
55 54
PILS062D-IHLP2525BD-SM-COMBO
0.22UH-35A-0.00255OHM
CRITICAL
21
L7220
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
2
1
R7213
201
MF
1/20W
1%
NO_XNET_CONNECTION
1K
2
1
R7212
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7216
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7217
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7221
CRITICAL
CASE-B1S
TANT
16V
20%
33UF
2
1
C7220
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7211
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7210
PILS062D-IHLP2525BD-SM-COMBO
0.22UH-35A-0.00255OHM
CRITICAL
21
L7210
55 54
55 54
54
201
MF
1/20W
1%
NO_XNET_CONNECTION
2.2
2
1
R7211
0612-1
MF
1W
1%
NO_XNET_CONNECTION
0.00075
CRITICAL
4 3
2 1
R7210
63 62 61
59 57 56 55 54 43
63 62 61
59 57 56 55 54 43
72
72
72
69 63 45
72
72
70
72
72 55 45
72
72
55 45
72
72
72 69
64 59 57 56 55 54
72
72 69
64 59 57 56 55 54
72
72
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
SW
VCC
SW
GL1
GL0
NC
GH
FCCM
PWM
VIN
VIN
AGND
AGND
PGND
PGND
PHASE
BOOT
PVCC
NC
SW
VCC
SW
GL1
GL0
NC
GH
FCCM
PWM
VIN
VIN
AGND
AGND
PGND
PGND
PHASE
BOOT
PVCC
NC
NC
NC NC
IN
IN
NC
NC NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
CPU VCCSA
LAST CHANGE: Mon Aug 8 12:54:34 2016
DESIGN: X502/MLB_CATZ
56 OF 73
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
73 OF 500
1.0.0
051-02265
PPVCCSA_S0G_R
SAVR_BOOT
PPBUS_G3H_CPU
PPVCCSA_S0G
SAVR_PWM
SAVR_FCCM
AGND_U7470
SAVR_PHASE
SAVR_SW
SAVR_ISUM_N SAVR_ISUM_P
SAVR_ISNSR_P SAVR_ISNS_P
SAVR_ISNSR_N SAVR_ISNS_N
SAVR_SNB1SAVR_BP
TP_SAVR_GH TP_SAVR_GL
VCINP_P5V_U7470
PP5V_S0
IND,MLD,0.47UH,4.9MO,17.5A,5.4X5.2X2.4MM L73701152S00241 CRITICAL
BOM_COST_GROUP=CPU & CHIPSET
IMVP VCCSA
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
201
MF
1/20W
5%
10
SNS_I_CPUVSA:YES
21
R7381
201
MF
1/20W
5%
10
SNS_I_CPUVSA:YES
21
R7380
SM
21
XW7370
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7374
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7374
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7376
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7377
402
MF-LF
1/16W
5%
1
2 1
R7376
MLP4535
SIC535CD
CRITICAL
1
8
6
11
2
12
5
10
7
3
14
9
13
4
U7370
54
54
0402-1
X7R
25V
10%
0.22UF
2
1
C7379
402
MF-LF
1/16W
5%
0
2
1
R7379
IHLP2020BD-SM
0.47UH-20A-0.00494OHM
CRITICAL
OMIT_TABLE
21
L7370
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
1K
2
1
R7372
0612
CYN
1W
1%
NO_XNET_CONNECTION=1
0.002
CRITICAL
34
12
R7370
0201
MF
1/20W
5%
NO_XNET_CONNECTION=1
0
2
1
R7371
54
54
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7370
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7371
45
45
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7380
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7381
0201
X7R
25V
10%
1000PF
2
1
C7375
72
63 62 61 59 57 55 54 43
72 69
72
72
72
72 69 64 59 57 55 54
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
PGND
PGND
CGND
GL
GL
VSWH
PHASE
VIN
PWM
NC
ZCD_EN*
VCIN
BOOT
VDRV
IN
IN
NC
OUT
OUT
OUT
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
CPU VCCGT Phase 1
LAST CHANGE: Mon Aug 8 12:54:34 2016
DESIGN: X502/MLB_CATZ
CPU VCCGT Phase 2
CPU VCCGT PHASE 3
57 OF 73
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1500
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
VOLTAGE=1.8VSWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
VOLTAGE=1.8V
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
DIDT=TRUE
74 OF 500
1.0.0
051-02265
PPVCCGT_S0G_PH1
PPBUS_G3H_CPU
PPBUS_G3H_CPU
GTVR_BP3 GTVR_SNB3
PPVCCGT_S0G_PH3
GTVR_ISUM_N
GTVR_ISNS1_N
GTVR_ISNS2_N
PPVCCGT_S0G
GTVR_ISUM_P
GTVR_ISNS3_N
GTVR_SW3
GTVR_ISEN3
GTVR_ISNS3_P
GTVR_PHASE3
GTVR_BOOT3
GTVR_ISEN1
GTVR_ISUM_N
TP_GTVR_GH3
TP_GTVR_GL3
TP_GTVR_GH2
TP_GTVR_GL2
TP_GTVR_GL1
TP_GTVR_GH1
PPBUS_G3H_CPU
GTVR_BP1 GTVR_SNB1
GTVR_ISNS2_N
GTVR_ISNS3_N
GTVR_ISUM_P
GTVR_ISNS1_N
GTVR_BP2 GTVR_SNB2
PPVCCGT_S0G_PH2
GTVR_ISUM_P
GTVR_ISUM_N
GTVR_ISNS1_N
GTVR_ISNS3_N
GTVR_ISNS2_N
GTVR_SW1
GTVR_ISNS1_P
GTVR_SW2
GTVR_ISEN2
GTVR_ISNS2_P
GTVR_PHASE1
GTVR_BOOT1
GTVR_PHASE2
GTVR_BOOT2
GTVR_FCCM
PP5V_S0
PP5V_S0
AGND_U7530
GTVR_PWM3
GTVR_FCCM
VCINP_P5V_U7530
PP5V_S0
AGND_U7520
GTVR_PWM2
GTVR_FCCM
VCINP_P5V_U7520
AGND_U7510
GTVR_PWM1
VCINP_P5V_U7510
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
BOM_COST_GROUP=CPU & CHIPSET
GT IMVP VCCGT
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
21
R7437
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
21
R7438
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
21
R7427
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
21
R7428
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
21
R7418
SM
21
XW7430
SM
21
XW7420
SM
21
XW7410
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7434
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7434
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7424
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7424
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7414
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7414
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7436
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7437
402
MF-LF
1/16W
5%
1
2 1
R7436
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7426
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7427
402
MF-LF
1/16W
5%
1
2 1
R7426
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7416
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7417
402
MF-LF
1/16W
5%
1
2 1
R7416
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7412
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7422
54
57 54
54
57 54
PQFN-COMBO
FDMF5808A
CRITICAL
OMIT_TABLE
9
8
3
24
16
1
29
7
28
12
31
30 33
27
6
2
5
32
4
U7430
PQFN-COMBO
FDMF5808A
CRITICAL
OMIT_TABLE
9
8
3
24
16
1
29
7
28
12
31
30 33
27
6
2
5
32
4
U7420
54
57 54
PQFN-COMBO
FDMF5808A
CRITICAL
OMIT_TABLE
9
8
3
24
16
1
29
7
28
12
31
30 33
27
6
2
5
32
4
U7410
0402-1
X7R
25V
10%
0.22UF
2
1
C7439
402
MF-LF
1/16W
5%
0
2
1
R7439
PILA082D-SM
0.22UH-20%-44A-0.0019OHM
CRITICAL
21
L7430
57 54
54
201
MF
1/20W
1%
NO_XNET_CONNECTION
1K
2
1
R7432
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
2
1
R7433
0612-1
MF
1W
1%
NO_XNET_CONNECTION
0.00075
CRITICAL
34
12
R7430
201
MF
1/20W
1%
NO_XNET_CONNECTION
2.2
2
1
R7431
57 54
57 45
45
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7430
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7431
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7470
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7471
0201
X7R
25V
10%
1000PF
2
1
C7435
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
21
R7417
0201
X7R
25V
10%
1000PF
2
1
C7415
0201
X7R
25V
10%
1000PF
2
1
C7425
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7450
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7451
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7460
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7461
0612-1
MF
1W
1%
NO_XNET_CONNECTION
0.00075
CRITICAL
4 3
2 1
R7410
201
MF
1/20W
1%
NO_XNET_CONNECTION
1K
2
1
R7422
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
2
1
R7423
57 54
54
201
MF
1/20W
1%
NO_XNET_CONNECTION
2.2
2
1
R7421
57 54
57 45
72 45
45
57 45
57 54
201
MF
1/20W
1%
NO_XNET_CONNECTION
2.2
2
1
R7411
54
57 54
201
MF
1/20W
1%
NO_XNET_CONNECTION
200K
2
1
R7413
201
MF
1/20W
1%
NO_XNET_CONNECTION
1K
2
1
R7412
0612-1
MF
1W
1%
NO_XNET_CONNECTION
0.00075
CRITICAL
4 3
2 1
R7420
PILA082D-SM
0.22UH-20%-44A-0.0019OHM
CRITICAL
21
L7420
PILA082D-SM
0.22UH-20%-44A-0.0019OHM
CRITICAL
21
L7410
402
MF-LF
1/16W
5%
0
2
1
R7419
0402-1
X7R
25V
10%
0.22UF
2
1
C7419
402
MF-LF
1/16W
5%
0
2
1
R7429
0402-1
X7R
25V
10%
0.22UF
2
1
C7429
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7420
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7421
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7411
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7410
63 62 61
59 57 56 55 54 43
63 62 61
59 57 56 55 54 43
57 45
57 45
72 69 63 45
63 62 61
59 57 56 55 54 43
72
57 45
57 45
57 45
57 45
72
72
72 69
64 59 57 56 55 54
72 69
64 59 57 56 55 54
72 69
64 59 57 56 55 54
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
NC
NC
NC
SW
VCC
SW
GL1
GL0
NC
GH
FCCM
PWM
VIN
VIN
AGND
AGND
PGND
PGND
PHASE
BOOT
PVCC
NC
NC
NC
NC
SW
VCC
SW
GL1
GL0
NC
GH
FCCM
PWM
VIN
VIN
AGND
AGND
PGND
PGND
PHASE
BOOT
PVCC
NC
IN
IN
NC
NC
NC
SW
VCC
SW
GL1
GL0
NC
GH
FCCM
PWM
VIN
VIN
AGND
AGND
PGND
PGND
PHASE
BOOT
PVCC
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
SHORT RSENSE
(P5VP3V3_VREF2)
152S00329
353S3905
7.33A MAX OUTPUT
152S00328
F = 600 KHZ
LAST CHANGE: Mon Aug 8 12:54:34 2016
DESIGN: X502/MLB_CATZ
(P5VP3V3_VREF2)
VOUT = 3.3V
V6 (3.3V S5 (DSW))
376S1038376S1038
INAUDIBLE SKIPPING
F = 600 KHZ
AUDIBLE SKIPPING
VOUT = 5V
100MA MAX OUTPUT
VOUT = 5.1V
6.67A MAX OUTPUT
5V S4
SHORT RSENSE
58 OF 73
VOLTAGE=0V
MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500
DIDT=TRUEGATE_NODE=TRUEMIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.1160
DIDT=TRUE
MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
DIDT=TRUE
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000
DIDT=TRUEGATE_NODE=TRUEMIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.2000
76 OF 500
1.0.0
051-02265
GND_5V3V3_AGND
P5VP3V3_VREG3
=PP5V_S5_LDO
P5VS4_DRVH_R
SWITCH_NODE=TRUE
DIDT=TRUE
P5VS4_SNUBR
P3V3S5_COMP2_R
P5VS4_CSP1
P5VS4_COMP1_R
PPBUS_G3H
P5VS4_VFB1_R
P5VS4_VFB1_R2
SWITCH_NODE=TRUEDIDT=TRUE
P5VS4_VBST
PPBUS_G3H
ISNS_5VS4_N
P3V3S5_VBST
P5VS4_VFB1_RR
P5VS4_EN
P3V3S5_VFB2_RR
P3V3S5_SNUBR
P3V3S5_DRVH
P3V3S5_VFB2_R2
P3V3S5_VFB2_R
P3V3S5_VSW
ISNS_3V3S5_N
P3V3S5_CS2_L_P
P3V3S5_CSP2
P3V3S5_DRVH_R
P5VS4_CS1_L_P
P3V3S5_RF
P3V3S5_CS2_L_N
ISNS_3V3S5_P
P5VS4_DRVL
DIDT=TRUE
GATE_NODE=TRUE
SWITCH_NODE=TRUEDIDT=TRUE
P3V3S5_SW
P3V3S5_DRVL_R P3V3S5_DRVL
P5VS4_COMP1
P5VS4_VSW
ISNS_5VS4_P
P5VP3V3_SKIPSEL
GATE_NODE=TRUE DIDT=TRUE
P5VS4_DRVH
PM_PGOOD_P5VS4
SWITCH_NODE=TRUE DIDT=TRUE
P5VS4_SW
PPBUS_G3H_P5VS4
P5VS4_DRVL_R
PP5V_S4
SWITCH_NODE=TRUEDIDT=TRUE
P3V3S5_VBST_R
P5VXX_EN
PPBUS_G3H_P3V3S5
P5VXX_ENPM_EN_P5VS5
PM_EN_P5VS4
P5VS4_EN_D
P5VS4_EN P3V3S5_EN
P3V3S5_EN_D
PM_EN_P3V3S5
PM_PGOOD_P3V3S5
P3V3S5_COMP2
P3V3S5_VFB2
PP3V3_S5
P3V3S5_EN
P5VP3V3_VREF2
PP5V_S4
P5VS4_VFB1
SWITCH_NODE=TRUE
DIDT=TRUE
P5VS4_VBST_R
P5VS4_CS1_L_N
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
BOM_COST_GROUP=PLATFORM POWER
VR - 5V S4, 3.3V S5
0201
RB521ES-30
NOSTUFF
K A
D7668
201
MF
1/20W
5%
33
NOSTUFF
21
R7668
0201
X6S-CERM
6.3V
20%
1UF
NOSTUFF
2
1
C7668
0201
X6S-CERM
6.3V
20%
1UF
NOSTUFF
2
1
C7663
201
MF
1/20W
5%
33
NOSTUFF
21
R7663
0201
RB521ES-30
NOSTUFF
K A
D7663
402
MF-LF
1/16W
5%
0
2 1
R7684
402
MF-LF
1/16W
5%
0
2 1
R7664
201
MF
1/20W
5%
10
2
1
R7671
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7613
201
MF
1/20W
5%
10
2
1
R7691
0612-SHORT-1
CYN
1W
1%
PLACE_NEAR=U5520.5:10MM
PLACE_NEAR=U5520.4:10MM
NO_XNET_CONNECTION=1
0.003
CRITICAL
OMIT
432
1
R7620
44
44
44
44
0612-SHORT-1
CYN
1W
1%
PLACE_NEAR=U5540.4:10MM
PLACE_NEAR=U5540.5:10MM
NO_XNET_CONNECTION=1
0.003
CRITICAL
OMIT
341
2
R7610
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7612
402
MF-LF
1/16W
5%
1
2 1
R7686
402
MF-LF
1/16W
5%
0
2 1
R7666
201
MF
1/20W
1%
2.2K
2
1
R7697
201
MF
1/20W
1%
6.34K
2
1
R7677
0603
X6S-CERM
16V
20%
10UF
CRITICAL
2
1
C7651
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7611
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7601
0201
MF
1/20W
5%
0
21
R7662
0201
MF
1/20W
5%
0
21
R7661
0201
MF
1/20W
5%
0
21
R7660
60
60 60
Q3D
CSD58873Q3D
CRITICAL
8
7
6
1
4
3
9
5
Q7660
Q3D
CSD58873Q3D
CRITICAL
8
7
6
1
4
3
9
5
Q7680
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7697
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7695
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7677
0201
X7R
25V
10%
1000PF
2
1
C7672
0201-1
MF
1/20W
0.1%
10K
CRITICAL
2
1
R7679
0201-1
MF
1/20W
0.1%
34.8K
CRITICAL
2
1
R7678
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7676
SM
PLACE_NEAR=L7670.1:3MM
NO_XNET_CONNECTION=1
2
1
XW7671
SM
PLACE_NEAR=C7675.1:5.3MM
2
1
XW7675
SM
PLACE_NEAR=L7670.2:3MM
NO_XNET_CONNECTION=1
2
1
XW7670
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7671
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7674
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7674
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
4.02K
2 1
R7672
201
X7R-CERM
25V
10%
220PF
2
1
C7678
201
X7R
10V
10%
4700PF
2
1
C7679
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
2.67K
21
R7673
0201
X7R
6.3V
10%
NO_XNET_CONNECTION=1
0.1UF
21
C7673
201
MF
1/20W
1%
10K
NOSTUFF
2
1
R7676
68 60
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7675
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7670
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7665
PIMA082D-COMBO
1.5UH-20%-12.5A-0.01OHM
CRITICAL
21
L7670
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7666
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7667
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7660
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7661
0402
X7R-CERM-1
25V
10%
0.1UF
CRITICAL
2
1
C7669
0201
X7R
25V
10%
1000PF
2
1
C7662
402
MF-LF
1/16W
5%
2.2
2
1
R7665
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7650
SM
PLACE_NEAR=U7650.28:1MM
2
1
XW7650
201
MF
1/20W
1%
11.3K
2
1
R7675
QFN
TPS51980A
CRITICAL
29
22
13
23
16
9
26
31
2
33
25
32
19
6
3
20
5
14
11
28
21
4
12
27
30
24
1
18
7
17
8
15
10
U7650
201
X7R
10V
10%
4700PF
2
1
C7699
201
MF
1/20W
1%
7.5K
2
1
R7695
201
MF
1/20W
1%
10K
NOSTUFF
2
1
R7696
60
0201
X7R
25V
10%
1000PF
2
1
C7692
0201
X7R
16V
10%
330PF
2
1
C7698
201
MF
1/20W
1%
165K
2
1
R7655
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
3.16K
21
R7693
201
MF
1/20W
1%
NO_XNET_CONNECTION=1
3.16K
21
R7692
0201
X7R
6.3V
10%
NO_XNET_CONNECTION=1
0.1UF
21
C7693
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7694
SM
PLACE_NEAR=L7690.2:3MM
NO_XNET_CONNECTION=1
2
1
XW7690
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7694
0201
MF
1/20W
5%
0
2
1
R7651
0201
MF
1/20W
5%
0
NOSTUFF
2
1
R7650
402
CERM
16V
10%
0.22UF
2
1
C7652
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7653
402
MF-LF
1/16W
5%
2.2
2
1
R7685
0402
X7R-CERM-1
25V
10%
0.1UF
CRITICAL
2
1
C7689
0201
X7R
25V
10%
1000PF
2
1
C7682
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7685
PIMA082D-COMBO
1UH-20%-16A-0.0067OHM
CRITICAL
2 1
L7690
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7686
0201-1
MF
1/20W
0.1%
10K
CRITICAL
2
1
R7699
0201
MF
1/20W
0.1%
21K
CRITICAL
2
1
R7698
SM
PLACE_NEAR=L7690.1:3MM
NO_XNET_CONNECTION=1
2
1
XW7691
SM
PLACE_NEAR=C7695.1:6.6MM
2
1
XW7695
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7691
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7696
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7687
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7680
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7681
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7690
69
72
72 69 68 63 60 58 53 50 43
72 69 68 63 60 58 53 50 43
58
72
72 69 64 63 60 58 54
58
58
58 58
72 69 68
64 63 61 60 44
58
72 69
64 63 60 58 54
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
OUT
OUT
OUT
IN
ININ
VSW
VIN
PGND
TG
TGR
BG
VSW
VIN
PGND
TG
TGR
BG
OUT
CSP1
MODE
OCSEL
VFB2VFB1
VREG3
COMP1 COMP2
CSN1 CSN2
CSP2
DRVH1 DRVH2
GND
PGOOD1 PGOOD2
RF
SW1 SW2
THRM_PAD
VIN
VREF2
VREG5
VBST1 VBST2
V5SW
DRVL1
SKIPSEL2
SKIPSEL1
DRVL2
EN1 EN2
EN
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
- LOAD SWITCHES ARE USED TO MEET THE TURN-ON TIMING.(<240US)
LEVEL SHIFT
F = 500 KHZ
5.2A MAX OUTPUT
VOUT = 1.01V
1V S0 REGULATOR FOR EDRAM (ON-PACKAGE CACHE)
(OD)
Scrub S3 & S5 pins connections!
THE FOLLOWING SHORTCUTS ARE USED FOR POC:
- MSM# IS NOT USED.
- OPC (EDRAM) IS POWERED FROM ONE VR.
59 OF 73
MIN_NECK_WIDTH=0.2000 DIDT=TRUE
MIN_LINE_WIDTH=0.2500
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.1160
DIDT=TRUE
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.1160
GATE_NODE=TRUE DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
DIDT=TRUE
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
GATE_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
GATE_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
GATE_NODE=TRUE DIDT=TRUE
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.1160
MIN_NECK_WIDTH=0.0600
MIN_LINE_WIDTH=0.1160
DIDT=TRUE
DIDT=TRUE
77 OF 500
1.0.0
051-02265
P1VOPC_VBST
P1VOPC_MODE
MAKE_BASE=TRUE
PPVCCOPC_S0G
PP1V_OPC_S0
SWOPC_G
PP3V3_S0
=PP1V_S0_CPU_VCCOPC_V62
=PP1V_S0_CPU_VCCEOPIO_AE62
=PP1V_S0_CPU_VCCEOPIO
P1VOPC_VSW
=PP1V8_SUS_CPU_VCCOPC_H63
PM_SLP_S3_L
PP1V_OPC_S0
P1VOPC_AGND
MAKE_BASE=TRUE
PU_VSNS_CPU_VCCEOPIO_TP
PM_OPC_ZVM_L
P1VOPC_REFIN
PP5V_S0
P1VOPC_DRVH_R
P1VOPC_SW
P1VOPC_SNS
=PP1V8_SUS_CPU_VCCOPC_G61
PP1V_OPC_S0
CPU_VCCOPCSENSE_N
=PP1V_S0_CPU_VCCOPC
P1VOPC_DRVH
P1VOPC_PGND
P1VOPC_DRVLP1VOPC_DRVL_R
=PP1V_S0_CPU_VCCOPC_P62
PP5V_S0_P1VOPC
PM_SLP_S3_L
P1VOPC_VTTREF
P1VOPC_VREF
P1VOPC_REFIN_R
P1VOPC_SNS_R
PPBUS_G3H_CPU
PM_PGOOD_EDRAM_R
P1VOPC_BOOT_RC
MAKE_BASE=TRUE
TP_CPU_MSM_LCPU_MSM_L
P1VOPC_TRIP
PP5V_S0
=PP1V_S0_CPU_VCCEOPIO_AG62
=PP1V_S0_CPU_VCCOPC_AB62
=PP1V_S3_CPU_VCCST
SWOPC_CNFG
CPU_VCCOPCSENSE_P
CPU_VCCEOPIOSENSE_N
CPU_VCCEOPIOSENSE_P
MAKE_BASE=TRUE
PD_VSNS_CPU_VCCEOPIO_TN
P1VOPC_LL_SNUB
MAKE_BASE=TRUE
PP1V8_S5G
CPU_ZVM_L
MAKE_BASE=TRUE
PU_VSNS_CPU_VCCOPC_TP
MAKE_BASE=TRUE
PD_VSNS_CPU_VCCOPC_TN
PM_OPC_ZVM_L
PM_PCH_SYS_PWROK
P1VOPC_VTT
P1VOPC_ENS3 P1VOPC_EN
VR - OPC (EDRAM)
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
BOM_COST_GROUP=CPU & CHIPSET
POWER33
FDMC7570S
CRITICAL
321
4
5
Q7750
0201
X5R-CERM
16V
10%
0.1UF
2
1
C7750
TDFN
SLG5AP031
CRITICAL
1
9
6
4
7
2
8
5
3
U7750
72 66 60 59 39 26 14
0201
X7R
25V
10%
1000PF
2
1
C7720
201
MF
1/20W
5%
10
21
R7741
SM
PLACE_NEAR=Q7750.5:1MM 2
1
XW7710
201
MF
1/20W
1%
1K
2
1
R7710
0402
X7R-CERM
16V
10%
BYPASS=U7700.6::6MM
0.1UF
2
1
C7715
0201
MF
1/20W
0.1%
PLACE_NEAR=U7700.8:5MM
48.7K
CRITICAL
2
1
R7712
0201
MF
0.05W
0.1%
PLACE_NEAR=U7700.8:5MM
30.9K
CRITICAL
2
1
R7711
0201
X7R-CERM
10V
10%
BYPASS=U7700.8::4MM
0.01UF
2
1
C7716
201
MF
1/20W
1%
PLACE_NEAR=U7700.19:3MM
33K
2
1
R7713
0402
X6S-CERM
25V
20%
BYPASS=U7700.12::6MM
2.2UF
CRITICAL
2
1
C7700
201
MF
1/20W
1%
PLACE_NEAR=U7700.18:3MM
35.7K
2
1
R7714
QFN
TPS51916
CRITICAL
1
5
4
3
6
2
9
1512
18
21
13
16
17
8
20
10
19
7
11
14
U7700
0402
X6S
4V
20%
BYPASS=U7700.2::6MM
10UF
CRITICAL
2
1
C7701
SM
PLACE_NEAR=U7700.21:1MM
21
XW7700
402
CERM
16V
10%
0.22UF
2
1
C7740
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7732
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7732
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7724
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7719
IHLP2020BD-PIHA052D-COMBO
1UH-20%-11A-0.0127OHM
CRITICAL
21
L7730
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C7749
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C7748
201
MF
1/20W
5%
2.2
2
1
R7730
0402
X6S-CERM
25V
20%
PLACE_NEAR=Q7730.8:2.7MM
2.2UF
CRITICAL
2
1
C7722
0201
X7R
25V
10%
PLACE_NEAR=L7730.2:6MM
1000PF
2
1
C7723
0402
X7R-CERM
16V
10%
0.1UF
2
1
C7730
402
MF-LF
1/16W
5%
1
21
R7733
72 66 60 59 39 26 14
201
MF
1/20W
5%
100K
2
1
R7791
201
MF
1/20W
1%
3.09K
2
1
R7715
402
MF-LF
1/16W
5%
10K
2
1
R7751
CASE-B
TANT
2V
20%
270UF
CRITICAL
2
1
C7754
60 39 14
201
MF
1/20W
5%
100
EDRAM_RAIL:ENABLE
21
R7745
201
MF
1/20W
5%
1
21
R7731
CASE-B
TANT
2V
20%
270UF
CRITICAL
2
1
C7753
CASE-B
TANT
2V
20%
270UF
CRITICAL
2
1
C7752
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7721
201
MF
1/20W
5%
100K
NOSTUFF
2
1
R7790
0201
X5R-CERM
10V
10%
0.1UF
2
1
C7790
SOT891
74AUP1G07GF
4
6
5
1
3
2
U7790
0201
MF
1/20W
5%
0
EDRAM_RAIL:DISABLE
21
R7719
402
MF-LF
1/16W
5%
2.2
21
R7700
0201
MF
1/20W
5%
0
EDRAM_RAIL:ENABLE
21
R7718
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C7751
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C7761
SM
PLACE_NEAR=Q7730.9:1MM
21
XW7730
Q3D
CSD58873Q3D
CRITICAL
8
7
6
1
4
3
9
5
Q7730
6 6
8 8
8 8
POWER33
FDMC7570S
CRITICAL
321
4
5
Q7760
201
MF
1/20W
5%
2.2M
2
1
R7750
72
72 59
69 64 63 60 54 49 46 45 42 38
8
8
10
8
72 59
72
59
72 69 64 59 57 56 55 54
72
8
72 59
10
8
72
72
63 62 61 57 56 55 54 43
72
70
72 69 64 59 57 56 55 54
8
8
69 54 19 14 10 8 6
72
72 69 67 64 61
72
72
59
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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D
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
S
D
G
PAD
CNFG
EN
S
THRM
GND
G
DONE
D
VCC
IN
GND PAD
PGND GND
VTT THRM
VLDOIN
VBST
DRVH
VTTREF
VTTSNS
VTT
VDDQSNS
PGOOD
DRVL
SW
TRIP
MODE
S3
VREF
S5
REFIN
V5IN
IN
OUT
NC NC
GND
VCC
NCNC
YA
VSW
VIN
PGND
TG
TGR
BG
ININ
ININ
ININ
S
D
G
NC
合肥怡飞苹果维修qq:82669515 qq群: 241000
CREATE VERSION THAT IS HIGH ONLY IN S0.
MINIMUM OFF TIME < 0.5V.
RC DELAY. TPAD REQUIRES 10US
SLP_S0# Isolation
(PGVR2)
LAST CHANGE: Thu Aug 4 21:00:42 2016
FOR REPROGRAMMING OTP CONTENTS.
SLP_S0# IS DRIVEN HIGH OUTSIDE OF S0.
3.3V => 0X32/33
CAP AT D1
0V => 0X30/31
(INV)
0V = HIGH FSW (2 CELL)
3.3V = LOW FSW (3 CELL)
(INV)
(PU AT PCH)
DESIGN: X502/MLB_CATZ
DELAY > 1.5MS
WIRE-ORED WITH
PMIC PCHPWROK OUTPUT
(TO SMC)
(ENVR1)
(ENVR2)
(ENVR4)
(ENVR5)
(BUFFERED PM_SLP_S3_L)
(PGVR5)
(PGVR1)
(ENVR3)
(PGVR4)
I2C BUS ADDRESS
(PGVR3)
(S3# AND S0# OR XDP)
(SMC DRIVES DPWROK TO PCH)
FLOAT => 0X34/35
2.4UA CURRENT
SOURCE AT VR
(S4# OR XDP)
KEEP THESE RAILS ON WHEN USING XDP
DELAY > 5MS
(PULL-UP AT SMC)
OPTIONAL: DIVIDE 1.8V FOR 1.5V INPUT.
USE BANJO AS BUFFER AND PULL-UP TO SLP_S3# TO
SOME DEVICES CARE ABOUT THIS.
60 OF 73
78 OF 500
1.0.0
051-02265
PP3V3_S5
PMIC_PGC
PP1V8_S0
PM_EN_P3V3S5G
PM_PGOOD_P3V3S5
PM_PGOOD_PVDDQ
PM_EN_P1V8S0
PP3V3_S5
PM_SLP_SUS_L
PM_EN_P3V3S0_RC
MAKE_BASE=TRUE
PCH_HSIO_PWR_EN
PM_SLP_S3_L
PM_PGOOD_PVDDQ
PM_EN_PVCCIO
=PP3V3_S0_PCH
PM_PGOOD_PVCCIO PM_PGOOD_P1V00
MAKE_BASE=TRUE
TP_PGOOD_P1V00
MAKE_BASE=TRUE
TP_PGOOD_PVCCIO
PM_PGOOD_P3V3S5
MAKE_BASE=TRUE
PM_PGOOD_PVCCPCH
PM_SLP_S0_L
PM_PGOOD_CPUVCC
PM_SLP_S3_L
SMC_PM_G2_EN
PM_PGOOD_P1V8
PM_EN_P1V2S0GPM_SLP_S0S3_L
MAKE_BASE=TRUE
S5_PWRGD
PMIC_ENLVA
PMIC_ENH
MAKE_BASE=TRUE
PM_EN_S0_SW PM_EN_P5VS0
PM_EN_P1VS5GTD
PM_EN_PVCCPCH
PM_EN_PVDDQ
PM_EN_P1V8
PM_EN_P1V00
PM_EN_S0_SW
PM_PGOOD_P5VS4
PMIC_VSD
PMIC_VSCPP3V3_LDO3V
PMIC_VSAPP3V3_S5G
PMIC_PGH
PM_PCH_PWROK
PM_EN_S0_SW
PM_SLP_S0S3_L
PMIC_SHUTDOWN_L
PM_SLP_S0_OD_L
PM_EN_P3V3S0
PM_SLP_S3_L
PM_EN_P1V8S0_RC
PM_EN_P1V8S0
PP3V3_S5
SSD_PWR_REQ
PM_SLP_S3_L
PP5V_LDO5V
PP5VR7V_VPROGOTP
PM_RSMRST_L
PP3V3_S0
PP3V3_S5G
AGND_PMIC
PM_PCH_PWROK ALL_SYS_PWRGD PM_RSMRST_L
PMIC_SYSPWROK
PPBUS_G3H
=SMBUS_SMC_PMIC_SDA
CPU_VCCST_PWRGD
PPBUS_PMIC
PM_SLP_S0S3_L
AGND_PMIC
PM_EN_P3V3S5
PM_EN_CPUVCC
PP3V3_LDO3V
PMIC_INT_L
PMIC_RSMRST_L
PPBUS_G3H
PP3V3_LDO3V
PP3V3_LDO3V
AGND_PMIC
AGND_PMIC
MAKE_BASE=TRUE
GND
PP5V_LDO5V
PP5V_S4
PMIC_EN5VSWPM_PGOOD_P5VS4
PP3V3_LDO3V
AGND_PMIC
PMIC_SLVADDR
SMB_PMIC_SCL=SMBUS_SMC_PMIC_SCL
SMB_PMIC_SDA
PMIC_EN3V3SW
AGND_PMIC
PMIC_VSE PMIC_VSF
PMIC_VDCSNS
PMIC_EN_P3V3S5
PMIC_VSG
PM_SLP_S3_L
PM_PGOOD_P5VS4
MAKE_BASE=TRUE
PM_SLP_S4_L
PM_SLP_S3_L
PM_PGOOD_P3V3S5
MAKE_BASE=TRUE
TP_PMIC_PGC
PM_EN_P1V8S3
PM_SLP_S4_L
PP3V3_G3H
PMIC_ENA
PP1V8_S3
AGND_PMIC
PM_EN_P3V3S4
PM_EN_P5VS4
PMIC_VCCST_PGD
PMIC_VSB
PMIC_EN_P3V3S5
PM_SLP_S4_L
PMIC_PGB
PMIC_PGD
PP3V3_LDO3V
PP3V3_S5
PM_SLP_S3_L
PM_SLP_S5_L
PP3V3_S0
SMC_PM_G2_EN
PM_SLP_S0_L
PP3V3_LDO3V
PMIC_VSF
PMIC_EN_P3V3S5
MAKE_BASE=TRUE
PM_SLP_SUS_L
MAKE_BASE=TRUE
PM_PGOOD_P3V3S5G
PM_PCH_SYS_PWROK
PM_PCH_PWROKPMIC_PCH_PWROK
SMC_PM_G2_EN
PMIC_ALLSYSPGD
SMC_PMIC_INT_L
XDP_PRESENT_L
=PP3V3_SUS_XDP
XDP_PRESENT_L
PM_EN_P5VS5
MAKE_BASE=TRUE
PM_EN_PVXS5
PM_PGOOD_P3V3S5G
PM_EN_P1VS0G
PM_EN_P3V3S0
PM_EN_P1VS3
=PP3V3_SUS_XDP
PP1V25_VREF
PM_PCH_SYS_PWROK
AGND_PMIC
PMIC_PGE
MAKE_BASE=TRUE
ALL_SYS_PWRGD
PPBUS_PMIC
PMIC IC & Power Control
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
BOM_COST_GROUP=PLATFORM POWER
2015%
100K
21
R7841
2015%
100K
21
R7842
2015%
10K
21
R7846
2015%
4.7K
21
R7847
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7824
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7843
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7844
201
MF
1/20W
1%
150K
2
1
R7813
201
MF
1/20W
1%
1M
NOSTUFF
21
R7812
0201
MF
1/20W
5%
0
21
R7830
0201
0
21
R7875
60 40 39
72 39 14
0201
0
21
R7867
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7805
BGA
CKPLUS_WAIVE=PWRTERM2GND
SN650839ZAJ
CRITICAL
H9
K11
E5
G3
E4
H11
J11
H2
D12
E11
K2
L1
J3
K4
K13
K12
G2
G1
F2
F1
G11
J2
D11
E2
U7800
BGA
SN650839ZAJ
CRITICAL
B1
M7
M8
N5
N6
M13E1D3
L2
L3
H1
J1
N7
N8
M5
K3
D13
L13
K1
C1
U7800
BGA
SN650839ZAJ
CRITICAL
F5
J10
E8
F4
E6
K8
K9
E7
D1
L8
D9
C7 C8
M6
F3
H4
C4
H3
C6
C5
D6
L10
L12
L6
L11
B10
J12
F10
J13
C12
C11
B12
U7800
201
MF
1/20W
1%
6.04K
2
1
R7886
201
MF
1/20W
1%
174K
NOSTUFF
2
1
R7869
0201
MF
1/20W
0.1%
2.55K
NOSTUFF
2
1
R7868
0201
MF
1/20W
5%
0
21
R7865
72 68 60 19
72 60 39 14
0201
0
2 1
R7883
72 66 60 59 39 26 14
201
MF
1/20W
5%
100K
2
1
R7882
0201
MF
1/20W
5%
0
2 1
R7887
14 64
201
100K
21
R7833
201
MF
1/20W
5%
3.3K
NOSTUFF
2
1
R7839
201
MF
1/20W
5%
3.3K
NOSTUFF
2
1
R7838
64 60
72 66 60 59 39 26 14
201
MF
1/20W
1%
59K
21
R7853
0201
X5R-CERM
10V
10%
0.1UF
2
1
C7853
SOT886
74AUP1T97GM
4
5
6
132
U7852
0201
X5R-CERM
10V
10%
0.1UF
2
1
C7852
201
MF
1/20W
5%
100K
2
1
R7852
64 60
0201
X5R-CERM
10V
10%
0.1UF
2
1
C7851
201
MF
1/20W
1%
36.5K
21
R7851
64 60
72 66 60 59 39 26 14
0201
X5R-CERM
10V
10%
0.1UF
2
1
C7850
64 60
SOT886
74AUP1T97GM
4
5
6
1
3
2
U7850
201
MF
1/20W
5%
100K
2
1
R7850
64
0201
X7R-CERM
10V
10%
0.01UF
2
1
C7886
0201
0
21
R7837
0201
0
21
R7836
58
201100K
21
R7827
201
4.7K
21
R7834
68 60 58
60 58
60 40 39
0201
0
2 1
R7889
72 66 60 59 39 26 14
0201
0
21
R7888
58
54
64
0201
0
2 1
R7808
14
40 39
0201
0
2 1
R7806
72 60 39
0201
0
2 1
R7804
60 59 39 14
0201
0
2 1
R7807
68 60 39 17 14
0201
0
2 1
R7805
60 40 39 201100K
BANJO_SHUTDOWN:SMC
21
R7829
201100K
BANJO_SHUTDOWN:NO
21
R7828
201100K
21
R7825
201100K
21
R7821
201100K
21
R7820
62
61
72 66 60 59 39 26 14
68 62 60
SOT891
74LVC1G08
CRITICAL
4
6
5 3
1
2
U7896
0201
X5R-CERM
10V
10%
0.1UF
2
1
C7896
201
MF
1/20W
5%
100K
2
1
R7896
61
0201
MF
1/20W
5%
0
XDP_PWR:NO
21
R7895
201
MF
1/20W
5%
100K
XDP_PWR:YES
2
1
R7894
0201
MF
1/20W
5%
0
XDP_PWR:NO
21
R7893
72 60 17
SOT886
74AUP1T97GM
XDP_PWR:YES
4
561
3
2
U7894
0201
X5R-CERM
10V
10%
0.1UF
XDP_PWR:YES
2
1
C7894
64
201
MF
1/20W
5%
100K
XDP_PWR:YES
2
1
R7892
201
MF
1/20W
5%
47K
2
1
R7890
72 68 60 39 14
72 60 17
0201
X5R-CERM
10V
10%
0.1UF
XDP_PWR:YES
2
1
C7892
SOT886
74AUP1T97GM
XDP_PWR:YES
4
561
3
2
U7892
19
0201
X5R-CERM
10V
10%
0.1UF
2
1
C7890
SOT891
74LVC1G32
4
6
5 3
1
2
U7890
68 60 58
60 58
64
64
61
72 68 60 39 14 62
72 60 14 61
61 64 62
72 60 39 14
58
64
64
0201
0
2 1
R7884
0201
0
2 1
R7881
0201
0
21
R7866
0201
0
21
R7864
0201
0
21
R7863
0201
0
21
R7862
0201
0
21
R7860
0201
0
21
R7861
60 19 14
54
72 66 60 59 39 26 14
72 60 14
72 66 60 59 39 26 14
0201
0
21
R7874
72 68 60 39 14
61
60 19 14
0201
0
21
R7835
42
42
0201
MF
1/20W
5%
0
NOSTUFF
2
1
R7832
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7840
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7839
0402
X7R
10V
10%
0.47UF
CRITICAL
2
1
C7838
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7837
0201
MF
1/20W
5%
0
21
R7803
72 69 68 64 63 61 60 58 44
72 69
67 64 63 51 50 48
60 58
68 62 60
72 69 68 64 63 61 60 58 44
69 19 16 14 13 5
70
70
72 68 60 19
39
72
60
60
68 60 58
60
72 69 64 60
60
72 69 68 64 63 61 60 58 44
62 61 60
69
64 63 60 59 54 49 46 45 42 38
72 69 64 60
62 61 60
60 19 14
72 60 39
68 60 39 17 14
72 69 68
63 60 58 53 50 43
60
72 68 60 19
62 61 60
60
72 69 68 63 60 58 53 50 43
60
60
62 61 60
62 61 60
62 61 60
72 69 64 63 58 54
60
62 61 60
62 61 60
60
60
70
72
69 68 53 52 51 47 42 41 28 19
69 64 63
62 61 60
60
60
72 69 68 64 63 61 60 58 44
69
64 63 60 59 54 49 46 45 42 38
60
60
60
60
69 60 17
60
69 60 17
60 59 39 14
62 61 60
60
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
(8 OF 10)
DS3_VREN
ALL_SYS_PWRGD
RSMRST_L_PWRGD
VCCST_PWRGD
ECVCC
1HZ
PMIC_INT*
BAT2SWON*
ACSWON*
BAT1SWON*
DPWROK
PCH_PWRBTN*
EC_RST*
ACOK
PWRBTNIN
VINPP
VDCSNS
EC_ONOFF*
NVDC*
ACIN
SYS_PWROK
PCH_PWROKBAT1
BAT2
(7 OF 10)
VDDIO1
VDD5_VPROGOTP
VDDIO0
LDO3V
VOUT3V3SW
TEMP_ALERT*
VREF1V25
LDO5V
AGND2
AGND3
AGND4
AGND1
SCLK
SDA
EN5VSW
VIN5VSW
EN3V3SW
SLAVEADDR
VINLDO3
VIN
(1 OF 10)
VDDPG
VDDLV
RESET*
PGB
PGD
LVA
PGH
PGF
PGE
PGG
PGC
PGA
LVB
STANDBY*
SHUTDOWN*
VSB
VSD
VSC
VSE
VSA
VSG
VSF
VSH
ENA
ENB
ENC
END
ENE
ENF
ENG
ENLVA
ENH
OUT
IN
IN
IN OUT
IN
IN
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
08
NC
NC
OUT
IN
OUT
IN
IN
IN
NC
NC
IN
IN
OUT
OUT
OUT
IN OUT
IN OUT
IN OUT
IN
OUT
OUT
OUT
NC
NC
NC
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
V4 (0.95V VCCIO) (BANJO VR3)
HIGHSIDE OCP DISABLED IN OTP
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
V8 (1.8V) (Banjo VR2)
(VR2)
(VR3)
HIGHSIDE OCP DISABLED IN OTP
(VR5)
V12 (VCCPCH (1V / 0.7V PRIM_CORE)) (BANJO VR5)
61 OF 73
SWITCH_NODE=TRUE DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUEDIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUEDIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUEDIDT=TRUE
79 OF 500
1.0.0
051-02265
PP5V_LDO5V
AGND_PMIC
AGND_PMIC
PM_PGOOD_P1V8
BANJO_SWVR3
BANJO_ENVR2
BANJO_DRVHVR5_R
BANJO_SWVR2
PP3V3_S5
PPVCCPCH_S5G
BANJO_FBVR2R_P
BANJO_FBVR2_RCBANJO_FBVR2_P
BANJO_FBVR2_N
BANJO_FBVR2R_N
BANJO_FBVR5PBANJO_FBVR5_P
PM_PGOOD_PVCCIO
BANJO_ENVR3
BANJO_ILIMVR5LS
PPBUS_G3H_CPU
BANJO_DRVHVR3
BANJO_SWVR5
BANJO_DRVLVR5_R
PPBUS_G3H_CPU
CPU_VCCIOSENSE_P
BANJO_VBSTVR3
BANJO_ILIMVR3LS
PP3V1_RTC
AGND_PMIC
BANJO_SWVR2_SNUB
BANJO_ENVR5
AGND_PMIC
PM_PGOOD_PVCCPCH
PM_EN_PVCCPCH
BANJO_VBSTVR5
BANJO_VBSTVR5_R
BANJO_SWVR5_SNUB
BANJO_DRVLVR5
AGND_PMIC
PM_EN_PVCCIO
PM_EN_P1V8
CPU_VCCIOSENSE_N
BANJO_FBVR3RP
BANJO_SWVR3_SNUB
BANJO_DRVHVR3_R
BANJO_DRVLVR3_R
BANJO_DRVLVR3
PPVCCIO_S0G
BANJO_SWVR3RAGND_PMIC
BANJO_DRVHVR5
BANJO_FBVR5_N
PP1V8_S5G
BANJO_VBSTVR3_R
BANJO_PGNDVR3
PPBUS_G3H_CPU
BANJO_SWVR5R
PPBUS_G3H_CPU
BANJO_PGNDVR5
BOM_COST_GROUP=PLATFORM POWER
PMIC VCCPCH VCCIO 1.8V
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
0201
X7R-CERM
10V
10%
0.01UF
2
1
C7931
201
MF
1/20W
1%
100
2
1
R7931
402
MF-LF
1/16W
5%
0
21
R7969
402
MF-LF
1/16W
5%
0
21
R7968
402
MF-LF
1/16W
5%
0
21
R7909
402
MF-LF
1/16W
5%
0
21
R7908
402
MF-LF
1/16W
5%
2.2
NOSTUFF
2
1
R7945
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7945
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7975
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7975
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R7915
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C7915
0201
X6S-CERM
10V
20%
1UF
2
1
C7922
BGA
SN650839ZAJ
CRITICAL
J4
B13
C13
H10
N13
N1
A13
A1
K7
K6
J8
J7
J6
J5
H8
H7
H6
H5
G8
G7
G6
G5
F8
F7
F6
U7800
CASE-A3-LLP
TANT-POLY
6.3V
20%
100UF
CRITICAL
2
1
C7937
CASE-A3-LLP
TANT-POLY
6.3V
20%
100UF
CRITICAL
2
1
C7935
SHORT-12L-1.25MM-SM
21
XW7961
SHORT-12L-1.25MM-SM
21
XW7901
PIFE25201B-SM
0.47UH-20%-4.0A-28MOHM
CRITICAL
21
L7930
CASE-B1S-1
TANT-POLY
6.3V
20%
150UF
CRITICAL
2
1
C7932
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C7911
8
8
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C7910
60
0201
MF
1/20W
5%
0
21
R7903
60
201
MF
1/20W
1%
7.68K
21
R7902
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C7966
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C7965
Q3D
CSD58889Q3D
CRITICAL
8
7
6
1
4
3
9
5
Q7900
Q3D
CSD58889Q3D
CRITICAL
8
7
6
1
4
3
9
5
Q7960
0201
X7R
25V
10%
1000PF
2
1
C7908
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C7906
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C7909
0201
X7R
25V
10%
1000PF
2
1
C7970
0201
X7R
25V
10%
1000PF
2
1
C7936
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C7939
0402
CERM-X6S
6.3V
20%
10UF
CRITICAL
2
1
C7930
0201
X7R
25V
10%
1000PF
2
1
C7903
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7902
201
MF
1/20W
5%
NO_XNET_CONNECTION=1
10
21
R7910
SM
21
XW7911
SM
21
XW7910
201
MF
1/20W
5%
1
2
1
R7907
0201
X6S-CERM
16V
20%
0.1UF
CRITICAL
2
1
C7907
0201
X7R
25V
10%
1000PF
2
1
C7962
0201
X6S-CERM
16V
20%
0.1UF
CRITICAL
2
1
C7967
201
MF
1/20W
5%
1
2
1
R7967
201
MF
1/20W
5%
10
21
R7970
60
60
0201
MF
1/20W
5%
0
21
R7963
201
MF
1/20W
1%
6.04K
21
R7962
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7934
201
MF
1/20W
1%
100
21
R7936
201
MF
1/20W
5%
10
21
R7935
SM
21
XW7936
SM
21
XW7935
60
60
0201
MF
1/20W
5%
0
21
R7932
BGA
SN650839ZAJ
CRITICAL
E13
F13
F12
H13
H12
E12
G13
G12
G10
E10F11
U7800
BGA
SN650839ZAJ
CRITICAL
G9 B11
A11
B9
A10
C9
D10
C10
D7E9
A9
A12
U7800
BGA
SN650839ZAJ
CRITICAL
L7 M3
N2
M4
N3
L5
K5
G4
L4
M2
N4
M1
U7800
0402
CERM-X6S
6.3V
20%
10UF
CRITICAL
2
1
C7933
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7901
IHLP2020BD-PIHA052D-COMBO
1UH-20%-11A-0.0127OHM
CRITICAL
21
L7960
IHLP2020BD-PIHA052D-COMBO
1UH-20%-11A-0.0127OHM
CRITICAL
21
L7900
0402
X6S-CERM
2.5V
20%
20UF
CRITICAL
2
1
C7938
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7900
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C7968
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C7969
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7964
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C7963
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C7960
62 60
62
61 60
62 61 60
72
72 69 68 64 63 60 58 44
72 69 63
72
63 62 61 59 57 56 55 54 43
63 62 61 59 57 56 55 54 43
72
69
62 61 60
72
62 61 60
72
72
62 61 60
72
72 69 63
72
62 61 60
72 69 67 64 59
72
63 62 61 59 57 56 55
54 43
63 62 61 59 57 56 55 54 43
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
(10 OF 10)
V3P3A_RTC
TRIP*
NC1
NC0
NC2
NC3
AGND
VBATTBKUP
VCOMP
IN
IN
IN
OUT
VSW
VIN
PGND
TG
TGR
BG
VSW
VIN
PGND
TG
TGR
BG
IN
OUT
IN
OUT
(3 OF 10)
SWVR2_1
SWVR2_0
FBVR2-
FBVR2+
PGNDVR2_0
PGNDVR2_1
VINVR2_0
VREGVR2
VINVR2_1
PGVR2
ENVR2
(4 OF 10)
ENVR3
PGVR3
ILIMVR3LS
ILIMVR3HS
VINVR3
PGNDVR3
FBVR3+
FBVR3-
DRVLVR3
DRVHVR3
SWVR3
VBSTVR3
(6 OF 10)
VBSTVR5
SWVR5
DRVHVR5
DRVLVR5
FBVR5-
FBVR5+
PGNDVR5
VINVR5
ILIMVR5HS
ILIMVR5LS
ENVR5
PGVR5
合肥怡飞苹果维修qq:82669515 qq群: 241000
SHORT RSENSE
V11 (1V) (Banjo VR1)
SHORT RSENSE
V13 (0.6V) (Banjo LDO1)
(VR4)
LAST CHANGE: Thu Aug 4 21:00:42 2016
DESIGN: X502/MLB_CATZ
(VR1)
V10 (1.2V VDDQ) (Banjo VR4)
0V = 1.2V LPDDR3
(1V INPUT, 3.3V TOLERANT)
62 OF 73
SWITCH_NODE=TRUEDIDT=TRUE
SWITCH_NODE=TRUEDIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUEDIDT=TRUE
DIDT=TRUE GATE_NODE=TRUE
GATE_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
DIDT=TRUE GATE_NODE=TRUE
DIDT=TRUE GATE_NODE=TRUE SWITCH_NODE=TRUEDIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
GATE_NODE=TRUE
DIDT=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
80 OF 500
1.0.0
051-02265
PP1V_S5G
ISNS_1VS5G_P
BANJO_SWVR1R
BANJO_FBVR1_P
ISNS_1VS5G_N
BANJO_ENVR1
BANJO_SWVR4R
PM_MEMVTT_EN
AGND_PMIC
BANJO_DRVHVR4_R
ISNS_1V2S3_N
PP5V_LDO5V
PM_EN_PVDDQ
PPVTT_S0
BANJO_FBVR1_N
BANJO_SWVR1_SNUB
BANJO_FBVR4_P BANJO_FBVR4P
BANJO_FBVR1P
BANJO_DRVHVR4
PP1V2_S3
BANJO_FBVR4_N
PP1V2_S3
BANJO_FBLDO1
PP5V_LDO5V
AGND_PMIC
BANJO_ILIMVR4
AGND_PMIC
BANJO_PGNDVR4
BANJO_DRVHVR1_R
BANJO_DRVLVR4_R
BANJO_SWVR4
BANJO_VBSTVR1
BANJO_DRVLVR1
PP1V2_S3_REG
BANJO_DRVLVR4 BANJO_SWVR4_SNUB
BANJO_VBSTVR4_R
BANJO_VBSTVR4
BANJO_DRVLVR1_R
BANJO_DRVHVR1
BANJO_VBSTVR1_R
AGND_PMIC
PM_PGOOD_P1V00
AGND_PMIC
BANJO_ILIMVR1
BANJO_FBLDO1_R
ISNS_1V2S3_P
PP1V2_S3
BANJO_VINLDO1S
BANJO_SWVR1 PP1V_S5G_REG
PPBUS_G3H_CPU
AGND_PMIC
PMIC_VTT_CTRL
BANJO_ENVR4
PM_PGOOD_PVDDQ
PPBUS_G3H_CPU
PM_EN_P1V00 BANJO_PGNDVR1
BOM_COST_GROUP=PLATFORM POWER
PMIC 1.2V 1.0V 0.6V
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
IHLP2020BD-PIHA052D-COMBO
1UH-20%-11A-0.0127OHM
CRITICAL
21
L8060
PILA062D-SM-COMBO
0.56UH-20%-19A-0.0065OHM
CRITICAL
21
L8030
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C8075
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C8076
0201
MF
1/20W
5%
0
21
R8034
7
402
MF-LF
1/16W
5%
0
21
R8039
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C8043
0201
X7R
25V
10%
1000PF
2
1
C8047
402
MF-LF
1/16W
5%
0
21
R8036
402
MF-LF
1/16W
5%
0
21
R8063
402
MF-LF
1/16W
5%
0
21
R8062
201
MF
1/20W
5%
100K
1
2
R8032
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R8038
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C8038
603
MF-LF
1/10W
5%
2.2
NOSTUFF
2
1
R8069
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C8069
0402
X6S
2V
20%
15UF
CRITICAL
2
1
C8099
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C8046
0402
X6S
2V
20%
15UF
CRITICAL
2
1
C8094
0402
X6S
2V
20%
15UF
CRITICAL
2
1
C8097
0402
X6S
2V
20%
15UF
CRITICAL
2
1
C8098
SHORT-12L-1.25MM-SM
21
XW8031
SHORT-12L-1.25MM-SM
21
XW8061
0612-SHORT-1
CYN
1W
1%
NO_XNET_CONNECTION=1
0.003
CRITICAL
OMIT
43
21
R8030
44
44
44
44
0612-SHORT-1
CYN
1W
1%
NO_XNET_CONNECTION=1
0.003
CRITICAL
OMIT
43
21
R8060
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C8070
Q3D
CSD58873Q3D
CRITICAL
8
7
6
1
4
3
9
5
Q8030
GATE_NODE=TRUE
Q3D
CSD58889Q3D
CRITICAL
8
7
6
1
4
3
9
5
Q8060
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C8044
0201
X7R
25V
10%
1000PF
2
1
C8077
0402
X6S
2V
20%
15UF
CRITICAL
2
1
C8096
0402
X6S
2V
20%
15UF
CRITICAL
2
1
C8095
SHORT-12L-0.1MM-SM
21
XW8090
201
MF
1/20W
5%
10
21
R8095
SM
21
XW8095
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C8091
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C8090
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C8045
CASE-B
TANT
2V
20%
270UF
CRITICAL
2
1
C8040
CASE-B
TANT
2V
20%
270UF
CRITICAL
2
1
C8041
CASE-B
TANT
2V
20%
270UF
CRITICAL NOSTUFF
2
1
C8042
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C8030
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C8035
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C8033
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C8034
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C8031
0201
X7R
25V
10%
1000PF
2
1
C8036
0201
X6S-CERM
16V
20%
0.1UF
CRITICAL
2
1
C8037
201
MF
1/20W
5%
1
2
1
R8037
60
0201
MF
1/20W
5%
0
21
R8033
68 60
201
MF
1/20W
1%
11K
21
R8031
201
MF
1/20W
5%
NO_XNET_CONNECTION=1
10
21
R8040
SM
21
XW8041
SM
21
XW8040
60
64 60
SM
21
XW8071
SM
21
XW8070
0201
X7R
25V
10%
1000PF
2
1
C8063
201
MF
1/20W
5%
1
2
1
R8067
0201
X6S-CERM
16V
20%
0.1UF
CRITICAL
2
1
C8067
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C8065
201
MF
1/20W
1%
6.04K
21
R8066
BGA
SN650839ZAJ
CRITICAL
B4 B3
A3
B5
A4
D2
C3
D5C2
A5
A2
D4
E3
U7800
BGA
SN650839ZAJ
CRITICAL
M10 M11
N11
M9
N10
L9
K10
J9M12
N9
N12
U7800
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C8062
0402
X6S-CERM
25V
20%
2.2UF
CRITICAL
2
1
C8061
CASE-B1S
TANT
16V
20%
33UF
CRITICAL
2
1
C8060
BGA
SN650839ZAJ
CRITICAL
B8
A8
F9
B6
A6
B7
A7
D8
U7800
0201
MF
1/20W
5%
0
21
R8068
201
MF
1/20W
5%
NO_XNET_CONNECTION=1
10
21
R8070
SM-COMBO
ELEC
2V
20%
220UF
CRITICAL
3 2
1
C8071
72 69 64 63 19
62 61 60
62 61 60
72 69
69 64 63 62
69 64 63 62
62 61 60
62 61 60
62 61 60
72
72
72
72
62 61 60
62 61 60
69 64 63 62
63 62 61 59 57 56 55 54 43
62 61 60
63 62 61 59 57 56 55 54 43
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
OUT
OUT
OUT
OUT
VSW
VIN
PGND
TG
TGR
BG
VSW
VIN
PGND
TG
TGR
BG
IN
OUT
OUT
IN
(5 OF 10)
DRVHVR4
SWVR4
VBSTVR4
DRVLVR4
FBVR4-
FBVR4+
PGNDVR4
VREGVR4
ILIMVR4
DDRID
DDR_VTT_CTRL
PGVR4
ENVR4
(2 OF 10)
VBSTVR1
DRVLVR1
SWVR1
DRVHVR1
FBVR1-
FBVR1+
PGNDVR1
ILIMVR1
VREGVR1
PGVR1
ENVR1
(9 OF 10)
VOUTLDO1_1
VOUTLDO1_0
FBLDO1
PGNDLDO1_1
VINLDO1_1
VINLDO1_0
VINLDO1S
PGNDLDO1_0
合肥怡飞苹果维修qq:82669515 qq群: 241000
FREQUENCY SPECIFIC
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
63 OF 73
81 OF 500
1.0.0
051-02265
PPBUS_G3H_CPU
PPVCCGT_S0G
PP3V3_TBT_X_LC
PPVCCPCH_S5G
PPVBAT_G3H_CONN
PP1V8_S3
PP3V3_S4
PPVCCGT_S0G
PP3V3_TBT_X_LC
PP1V2_S3
PPVCCCPU_S0G
PP1V2_S3
PPBUS_G3H_CPU
PP1V2_S3
PPDCIN_G3H
PP5V_S4
PP1V2_S3
PP5V_S4
PPVBAT_G3H_CHGR_R
PP1V8_S0
PP1V2_S3
PP1V8_S3
PP3V3_S4
PPVCCIO_S0G
PP1V2_S3
PP5V_S4 PP5V_S4
PPBUS_G3H
PP3V3_UPC_XB_LDO
PP3V3_S4
PP1V2_S3
PP1V_S5G
PPBUS_SSD_FLT
PP5V_S5
PP0V9_TBT_X_SVR
PP3V3_TBT_X_S0
PP3V3_S5
PP1V_S5G
PPBUS_G3H_CPU
PPBUS_G3H_CPU
PP3V3_S4
PPVBAT_G3H_CHGR_R
PP5V_S4
PP1V8_S3
PPBUS_G3H_CPU
PPVBAT_G3H_CONN
PP3V3_S4
PP5V_S4
PP5V_S5
PP3V3_S5
PP3V3_S5_SSD_SNS
PP3V3_S4
PP5V_S5
PP1V8_S0 PP3V3_S0PP1V8_S0 PP3V3_S4 PP3V3_S4_WLS
PP5V_S4
PP3V3_S5
PP1V2_S3
PP1V2_S3
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
RAIL DESENSE CAPS
BOM_COST_GROUP=PLATFORM POWER
0201
CERM
25V
5%
12PF
NOSTUFF
2
1
C8140
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8141
0201
CERM
25V
5%
12PF
NOSTUFF
2
1
C8142
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8143
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8137
0201
CERM
25V
5%
12PF
2
1
C8134
0201
NP0-C0G
25V
+/-0.1PF
3.0PF
CRITICAL
2
1
C8135
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8108
0201
C0G
25V
+/-0.25PF
3.5PF
2
1
C8109
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8102
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8130
0201
CERM
25V
5%
12PF
2
1
C8122
0201
C0G
25V
+/-0.25PF
3.5PF
2
1
C8114
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8131
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8129
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8123
0201
C0G
25V
+/-0.25PF
3.5PF
2
1
C8115
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8104
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8105
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8132
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8124
0201
CERM
25V
5%
12PF
2
1
C8116
0201
C0G
25V
+/-0.25PF
3.5PF
2
1
C8121
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8106
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8133
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8125
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8117
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8107
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8126
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8118
0201
CERM
25V
5%
12PF
2
1
C8110
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8127
0201
C0G
25V
+/-0.25PF
3.5PF
2
1
C8113
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8119
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8111
0201
C0G-CERM
25V
+/-0.05PF
2.9PF
CRITICAL
2
1
C81A0
0201
C0G-CERM
25V
+/-0.05PF
2.9PF
CRITICAL
2
1
C81A1
0201
C0G-CERM
25V
+/-0.05PF
2.9PF
2
1
C81A3
0201
C0G
25V
+/-0.25PF
3.5PF
2
1
C81A5
0201
CERM
25V
5%
12PF
CRITICAL
2
1
C8100
0201
C0G
25V
+/-0.1PF
3PF
2
1
C81A7
0201
C0G
25V
+/-0.1PF
3PF
NOSTUFF
2
1
C81A8
0201
C0G
25V
+/-0.1PF
3PF
NOSTUFF
2
1
C81A9
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8180
0201
C0G
25V
+/-0.25PF
3.5PF
2
1
C8174
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8156
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8154
0201
C0G
25V
+/-0.1PF
3PF
NOSTUFF
2
1
C8139
0201
C0G
25V
+/-0.1PF
3PF
CRITICAL
2
1
C8101
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8136
0201
CERM
25V
5%
12PF
2
1
C8196
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8198
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8199
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8197
0201
CERM
25V
5%
12PF
2
1
C8194
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8195
0201
CERM
25V
5%
12PF
2
1
C8192
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8193
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8191
0201
CERM
25V
5%
12PF
2
1
C8188
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8189
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8187
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8185
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8182
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8183
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8153
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8164
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8181
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8172
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8170
0201
C0G
25V
+/-0.25PF
3.5PF
2
1
C8157
0201
CERM
25V
5%
12PF
2
1
C8178
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8179
0201
CERM
25V
5%
12PF
2
1
C8176
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8177
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8171
0201
CERM
25V
5%
12PF
2
1
C8128
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8173
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8175
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8158
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8152
0201
CERM
25V
5%
12PF
2
1
C8168
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8169
0201
CERM
25V
5%
12PF
2
1
C8166
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8167
0201
CERM
25V
5%
12PF
2
1
C8160
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8120
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8161
0201
CERM
25V
5%
12PF
2
1
C8162
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8163
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8165
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8159
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8155
0201
CERM
25V
5%
12PF
2
1
C8112
0201
CERM
25V
5%
12PF
2
1
C8148
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8149
0201
CERM
25V
5%
12PF
NOSTUFF
2
1
C8150
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8151
0201
C0G
25V
+/-0.1PF
3PF
NOSTUFF
2
1
C8138
0201
CERM
25V
5%
12PF
NOSTUFF
2
1
C8144
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8145
0201
CERM
25V
5%
12PF
NOSTUFF
2
1
C8146
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8147
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8103
63 62 61 59 57 56 55 54 43
72 69 63 57 45
63 28 27
72 69 61
63 53 52
69 64 63 60
72 69 67 64 63 45 44 43 41
72 69 63 57 45
63 28 27
69 64 63 62
72 69 55 45
69 64 63 62
63 62 61 59 57 56 55 54 43
69 64 63 62
72 69 68 53
72 69 64 63 60 58 54
69 64 63 62
72 69 64 63 60 58 54
63 53
72 69 67 64 63 60 51 50 48
69 64 63 62
69 64 63 60
72 69 67 64 63 45 44 43 41
72 69 61
69 64 63 62
72 69 64 63 60 58 54 72 69 64 63 60 58 54
72 69 68 60 58 53 50 43
69 30 28
72 69 67 64 63 45 44 43 41
69 64 63 62
72 69 64 63 62 19
67
69 64 63
27
28
72 69 68 64 63 61 60 58 44
72 69 64 63 62 19
63 62 61 59 57 56 55 54 43
63 62 61 59 57 56 55 54 43
72 69 67 64 63 45 44 43 41
63 53
72 69 64 63 60 58 54
69 64 63 60
63 62 61 59 57 56 55 54 43
63 53 52
72 69 67 64 63 45 44 43 41
72 69 64 63 60 58 54
69 64 63
72 69 68 64 63 61 60 58 44
69
72 69
67 64 63 45 44 43 41
69 64 63
72 69 67 64 63 60 51 50 48 69 64 60 59 54 49 46 45 42 38 72 69 67 64 63 60 51 50 48 72 69 67 64 63 45 44 43 41 72 69 44
72 69 64 63 60 58 54
72 69 68 64 63 61 60 58 44
69 64 63 62
69 64 63 62
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
合肥怡飞苹果维修qq:82669515 qq群: 241000
1.2V MINUS 0.2V.
1V S5G FUSE (FOR FAST TURN OFF)
@ 1.8V
TPS22968
U8200
LOAD SWITCH - DUAL
Part
TON-TOTAL
1V S0G CPU SWITCH (VCCSTG)
EDP: TBD
1V S5GTD SWITCH (VCCMPHYGT,VCCSRAM,VCCAPLLEBB)
SLG5AP1643V
7.4 MOHM TYP
10.6 MOHM MAX
Part
Type
R(on)
Current
@ 25C
28 MOHM MAX
SLG5AP1635V
Load Switch
20 MOHM TYP
U8230
2.5A MAX
39US MAX @ 1V
@ 1.2V
Type
Part
R(on)
Current
TON-TOTAL
185 MOHM MAX
135 MOHM TYP
U8240
TPS22904
Load Switch
0.5A MAX
1V2 S0G SWITCH (VCCPLL_OC)
SEE <RDAR://PROBLEM/21555505>
EDP: 0.24A
20US MAX @ 1.2V
Current
TON-TOTAL
R(on)
Type
Part
@ 25C
2.5A MAX
U8250
39US MAX @ 1V
28 MOHM MAX
Load Switch
20 MOHM TYP
SLG5AP1635V
FAST TURN ON: < 64US
EDP: 0.04A
EDP: 0.24A
TON-TOTAL
Current
Part
Type
R(on)
2.5A MAX
28 MOHM MAX
39US MAX @ 1V
SLG5AP1635V
Load Switch
20 MOHM TYP@ 25C
U8230
EDP: 2.1A
R(on)
R(on)
Type
TON-TOTAL
Current
@ 70C
@ 25C
Part
U8260
6A MAX
Load Switch
65US MAX @ 1V
U8220
@ 5V VBIAS
Load Switch
Part
Type
R(on)
1.3MS MAX @ 3.6V
Current
(IBIAS <70UA MAX)
4A MAX
9.8 MOHM MAX
5.3 MOHM TYP
@ 3.6V
TPS22920
U8205
@ 5V VBIAS
TPS22968
R(on)
(IBIAS <70UA MAX)
Current
TON-TOTAL
LOAD SWITCH - DUAL
1MS MAX
27 MOHM MAX
38 MOHM MAX
@ 3.3V
LOAD SWITCH - DUAL
38 MOHM MAX
Type
Part
R(on)
Type
6A MAX
Part
25 MOHM TYP
18 MOHM TYP
Current
4A MAXRISE TIME: 3.3V, 1000PF ==> 930US
25 MOHM TYP
U8210
@ 5V VBIAS
Current
1.4MS MAX
TPS22966
RISE TIME: 1.8V, 1000PF ==> 540US
2.4MS MAX @ 5V
TON-TOTAL 1.7MS MAX @ 3,3V
TON-TOTAL
LAST CHANGE: Mon Aug 8 12:54:34 2016
DESIGN: X502/MLB_CATZ
R(on)
4A MAX
Type
RISE TIME: 3.3V, 1000PF ==> 1200US
TON-TOTAL
ENSURE 1.8V RAIL IS ALWAYS ABOVE
RISE TIME: 5V, 1000PF ==> 1700US
(IBIAS <120UA MAX)
SHORT RSENSE
1V S3 SWITCH (VCCST, VCCPLL)
64 OF 73
MIN_NECK_WIDTH=0.1500
VOLTAGE=1V
MIN_LINE_WIDTH=0.1200
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.5000
82 OF 500
1.0.0
051-02265
PP1V_S5GTD
PM_EN_P5VS0
P5VS0SW_CT2
PP5V_S4
TP_ISNS_3V3S0N
PP5V_S0
PM_EN_P3V3S0
TP_ISNS_3V3S0P
PP3V3_S5 PP3V3_S5_S0R
P3V3S4SW_CT1
PP3V3_S0
P1V8S3SW_CT1
P3V3S0SW_CT2
P3V3S5GSW_CT1
PP3V3_S5G
P1V8S0SW_CT2
PP3V3_S4
PP3V3_S5
PP3V3_S5
PP5V_S5
PP5V_S5
PM_EN_P1V8S3
PM_EN_P3V3S5G
PM_EN_P3V3S4
PP5V_S5
P1VS5GFUSE_RAMP
PP1V_S5G
PP5V_S5
P1VS3CPUSW_RAMP
PP1V_S3PM_EN_P1VS3
PP1V_S3
PP5V_S5
P1VS0GCPUSW_RAMP
PP1V_S0GPM_EN_P1VS0G
PP1V2_S0GPP1V2_S3
PM_EN_P1V2S0G
PP1V8_S5G
PM_EN_P1V00
MAKE_BASE=TRUE
PP1V_S5G_FUSE
=PP1V_SUS_PCH_FUSE
PP1V8_S0
PP1V2_S3
PP1V8_S3
PP5V_S5
PM_EN_P1VS5GTD
PP1V_S5G
PP5V_S5
PM_EN_P1V8S0
PP1V_S5G
BOM_COST_GROUP=PLATFORM POWER
Power FETs
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
SOD523
PMEG3010EB/S500
K A
D8231
0201
MF
1/20W
5%
0
NOSTUFF
2
1
R8280
STDFN
SLG5AP1635V
CRITICAL
1
52
8
37
U8230
0201
C0G
25V
5%
100PF
2
1
C8232
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C8233
0201
X5R-CERM
10V
10%
0.1UF
2
1
C8230
60
0306-SHORT
MF
1/3W
1%
0.005
OMIT
43
21
R8220
60
0201-1
X5R
6.3V
20%
1.0UF
2
1
C8220
CSP
TPS22920
CRITICAL
C1
B1
A1
C2
B2
A2
D2
D1
U8220
62 60
0201
C0G
25V
5%
100PF
2
1
C8282
0201
X5R-CERM
10V
10%
0.1UF
2
1
C8280
STDFN
SLG5AP1635V
CRITICAL
1
52
8
37
U8280
0201
MF
1/20W
5%
0
VCCPLLOC:S3
21
R8240
60
SOD523
PMEG3010EB/S500
K A
D8230
60
0201
MF
1/20W
5%
0
VMPHY:EQUAL_SUS
2
1
R8262
0201
MF
1/20W
5%
0
VMPHY:EQUAL_SUS
2
1
R8261
0201
MF
1/20W
5%
0
VMPHY:EQUAL_SUS
2
1
R8260
60
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C8263
0201
X5R-CERM
10V
10%
0.1UF
VMPHY:SWITCHED
2
1
C8260
TDFN
SLG5AP1643V
CRITICAL
VMPHY:SWITCHED
1
7
59
8
3
2
U8260
STDFN
SLG5AP1635V
CRITICAL
1
52
8
37
U8250
0402
X6S
4V
20%
10UF
CRITICAL
2
1
C8253
60
0201
C0G
25V
5%
100PF
2
1
C8252
0201
X5R-CERM
10V
10%
0.1UF
2
1
C8250
CSP
TPS22904
CRITICAL
VCCPLLOC:S0G
A2
A1
B1
B2
U8240
60
0201-1
X5R
6.3V
20%
1.0UF
VCCPLLOC:S0G
2
1
C8240
DPU-THICKSTNCL
TPS22966
CRITICAL
8
13
6
1
4
15
5
3
11
10
12
U8210
60
60
0201
X5R-CERM
10V
10%
0.1UF
2
1
C8210
0201
X7R
25V
10%
1000PF
2
1
C8212
0201
X7R
25V
10%
1000PF
2
1
C8213
0201
X7R
25V
10%
1000PF
2
1
C8202
0201
X7R
25V
10%
1000PF
2
1
C8203
0201
X5R-CERM
10V
10%
0.1UF
2
1
C8205
0201
C0G
25V
5%
27PF
2
1
C8207
0201
X7R
25V
10%
1000PF
2
1
C8208
DPU-THICKSTNCL
TPS22968
CRITICAL
8
13
6
1
4
15
5
3
11
10
12
U8205
60
0201
X5R-CERM
10V
10%
0.1UF
2
1
C8200
DPU-THICKSTNCL
TPS22968
CRITICAL
8
13
6
1
4
15
5
3
11
10
12
U8200
69
72 69 63 60 58 54 72 69 59 57 56 55 54
72 69 68 64 63 61 60 58 44 69 63 60 59 54 49 46 45 42 38
72 69 60
72 69 67 63 45 44 43 41
72 69 68 64 63 61 60 58 44
72 69 68 64 63 61 60 58 44
69 64 63
69 64 63
72 69 64 63 62 19
69 64 63
69 64
69 64
69 64 63
69
69 69 64 63 62
72 69 67 61 59
12 8
72 69 67 63 60 51 50 48
69 64 63 62
69 63 60
69 64 63
72 69 64 63 62 19
69 64 63
72 69 64 63 62 19
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
VDD
D
S
GND
CAP
ON
IN
NC
IN
VIN
ON
GND
VOUT
IN
VDD
D
S
GND
CAP
ON
IN
IN
IN
VDD
D
S
D
S
GND
ON
VDD
D
S
GND
CAP
ON
IN
VOUT
GND
ON
VIN
IN
PAD
VOUT2
VOUT1
GND
THRM
ON1
VIN1
VIN2
CT1
VBIAS
CT2
ON2
IN
IN
PAD
VOUT2
CT2
ON2
VIN2
CT1
VBIAS
ON1
VIN1 VOUT1
THRM
GND
IN
PAD
VOUT2
CT2
ON2
VIN2
CT1
VBIAS
ON1
VIN1 VOUT1
THRM
GND
合肥怡飞苹果维修qq:82669515 qq群: 241000
PBUS LINE WIDTHS
- =PPVIN_S0SW_LCDBKLTFET (9-12.6V LCD BACKLIGHT INPUT)
- =PP5V_S0_BKLT (5V BACKLIGHT DRIVER INPUT)
353S4160
Page Notes
Power aliases required by this page:
PLACEMENT_NOTE:
LINE WIDTHS
I2C ID DEDICATED.ONLY CONNECTS TO JERRY
740S0159
107S00034 371S0704
(IPU)
(IPU)
LCD BKLT LINE WIDTHS
Fs = 625kHz Typ (+/- 7%)
Iout = 0.12A Typ, 0.15A Max
Vout = 46V Typ, 55V Max
152S00253
PLATFORM_RESET NO LONGER GATES THE BKLT_EN AS BOTH COME FROM PCH NOW
65 OF 73
84 OF 500
1.0.0
051-02265
MIN_NECK_WIDTH=0.2000
VOLTAGE=55V
MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000
VOLTAGE=12.9V
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=2.0000
DIDT=TRUE
VOLTAGE=55V
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000
DIDT=TRUE
VOLTAGE=55V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000
VOLTAGE=12.9V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000
VOLTAGE=12.9V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000
VOLTAGE=12.9V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.6000
GATE_NODE=TRUE
DIDT=TRUE
VOLTAGE=5V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000
VOLTAGE=5V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000
VOLTAGE=5V
GATE_NODE=TRUE DIDT=TRUE
GATE_NODE=TRUE DIDT=TRUE
PPVOUT_S0_LCDBKLT
GND_BKLT_SGND
MAKE_BASE=TRUE
PPVIN_S0SW_LCDBKLT
LCDBKLT_EN_L
PPVOUT_S0_LCDBKLT
LCDBKLT_SWBKLT_SD
PPVIN_SW_LCDBKLT_SW
PPVIN_SW_LCDBKLT_SW
PPVIN_S0SW_LCDBKLT
PPVIN_S0SW_LCDBKLT_R
PPVIN_S0SW_LCDBKLT_F
=PP5V_S0_BKLT
LCDBKLT_TB_XWR
LCDBKLT_FET_DRV
BKLT_EN_R
=I2C_BKLT_SCL
PP5V_S0_BKLT_A
PP5V_S0_BKLT_D
PP5V_S0_BKLT_A
=I2C_BKLT_SDA
=PP5V_S0_BKLT
PPVIN_S0SW_LCDBKLT_F
=PPVIN_S0SW_LCDBKLTFET
GND_BKLT_SGND
LCDBKLT_FB
BKLT_SDA
BKLT_SCL
BKLT_PWM_KEYB
PP5V_S0_BKLT_D
GND_BKLT_SGND
BKLT_SENSE_OUT
EDP_BKLT_EN
ISNS_LCDBKLT_P
ISNS_LCDBKLT_N
LCDBKLT_FET_DRV
LCDBKLT_FET_DRV_RGND_BKLT_SGND
PPVIN_S0SW_LCDBKLT_R
BOM_COST_GROUP=DISPLAY
LCD Backlight Driver
SYNC_MASTER=X362 SYNC_DATE=06/25/2015
0201
C0G
100V
+/-0.1PF
3PF
2
1
C8478
0201
C0G
100V
5%
12PF
2
1
C8479
0201
C0G
100V
+/-0.1PF
3PF
2
1
C8476
0201
C0G
100V
5%
12PF
2
1
C8477
0201
CERM
25V
5%
12PF
2
1
C8413
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8414
402
MF-LF
1/16W
5%
10
21
R8410
0612-1
MF
1W
1%
0.025
3 4
1 2
R8400
0402
CERM
100V
5%
PLACE_NEAR=D8410.K:6.1MM
12PF
2
1
C8475
0402
CERM
100V
5%
PLACE_NEAR=D8410.K:6.1MM
12PF
2
1
C8474
0603
C0G-CERM
100V
5%
100PF
NOSTUFF
2
1
C8432
LLP
LP8548B1SQ_-04
CRITICAL
10
9
5
18
25
2
1
6
19
16
11
15
12
14
13
20
3
22
24
23
7
4
8
21
17
U8400
201
MF
1/20W
5%
10K
2
1
R8447
PIME062D-SM
PLACE_NEAR=Q8401.5:3MM
15UH-20%-1.9A-0.24OHM
CRITICAL
21
L8410
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8464
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8463
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5.1MM
2.2UF
CRITICAL
2
1
C8469
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5.1MM
2.2UF
CRITICAL
2
1
C8468
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8462
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8461
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8467
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8466
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8460
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8465
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8473
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8472
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8471
1206
X5R
100V
10%
PLACE_NEAR=D8410.K:5MM
2.2UF
CRITICAL
2
1
C8470
402
MF-LF
1/16W
5%
0
2
1
R8445
402
MF-LF
1/16W
5%
0
2
1
R8444
43
43
402
MF-LF
1/16W
1%
150K
2
1
R8432
402
MF-LF
1/16W
1%
18.2K
2
1
R8431
PWRPK-1212-8
PLACE_NEAR=U8400.1:3MM
SI7812DN
CRITICAL
321
4
5
Q8401
0201
NP0-C0G
25V
5%
33PF
NO STUFF
2
1
C8442
SM
PLACE_NEAR=D8410::2MM
2
1
XW8410
0603
X6S-CERM
25V
10%
PLACE_NEAR=L8410.1:5MM
4.7UF
SANDWICH C8410 AND C8411
CRITICAL
2
1
C8411
0603
X6S-CERM
25V
10%
PLACE_NEAR=L8410.1:5MM
4.7UF
SANDWICH C8410 AND C8411
CRITICAL
2
1
C8410
402
CERM
50V
10%
0.001UF
NOSTUFF
2
1
C8401
70
70
68 5
402
X5R
25V
10%
PLACE_NEAR=L8410.1:5MM
0.1UF
2
1
C8412
SM
21
XW8400
201
MF
1/20W
5%
1M
2
1
R8440
201
MF
1/20W
5%
1.8K
2
1
R8453
201
MF
1/20W
5%
1.8K
2
1
R8452
402-1
X5R
10V
10%
PLACE_NEAR=U8400.18:5MM
1UF
2
1
C8441
402-1
X5R
10V
10%
PLACE_NEAR=U8400.5:5MM
1UF
2
1
C8440
0201
MF
1/20W
5%
0
21
R8442
0201
MF
1/20W
5%
PLACE_NEAR=U8400.16:10MM
0
21
R8451
0201
MF
1/20W
5%
PLACE_NEAR=U8400.15:10MM
0
21
R8450
SOD123-COMBO
PLACE_NEAR=L8410.2:3MM
PMEG10020ELR-DFLS2100
CRITICAL
KA
D8410
SSOT6-HF
FDC638APZ_SBMS001
CRITICAL
4
3
6
5
2
1
Q8400
402
MF-LF
1/16W
1%
63.4K
2
1
R8402
0201
X7R-1
16V
10%
1000PF
2
1
C8400
402
MF-LF
1/16W
1%
80.6K
2
1
R8401
0603
3AMP-32V
CRITICAL
21
F8400
72 66 65
65
65
72 66 65
65
65
65
65
65
69 65
65
65
65
65
69 65
65 69
65
65
65
65
65
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
NC
NC
NC
NC
PAD
VSENSE_P
EN
ISET_KEYB
GND_SW
GND_SW
SW2
FB2
KEYB1
KEYB2
SDA
SCL
PWM_KEYB
SENSE_OUT
FB
THRM
GNDA
GNDD
GND_SW2
SD
VSENSE_N
SW
GD
VDDA
VDDD
SW
OUT
OUT
BI
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
LCD PANEL INTERFACE (eDP) + Camera (MIPI)
LCD Panel HPD & AUX strapping
U8510 BYPASS
860-00469
COWLING BOSES
516S00228
SHORT RSENSE
051-02265
1.0.0
66 OF 73
85 OF 500
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
VOLTAGE=5V
VOLTAGE=3.3V
PP3V3_S0SW_LCD
PANEL_P3V3_EN_DLY
PANEL_P3V3_EN
PP3V3_S0SW_LCD_R1
PPVOUT_S0_LCDBKLT
EDP_INT_AUX_N
EDP_INT_ML_P<1>
EDP_INT_ML_P<0>
EDP_INT_AUX_NEDP_AUXCH_C_N
EDP_AUXCH_C_P
EDP_ML_C_N<2>
TCON_BKLT_PWM
PP5V_S0SW_LCD
=PP3V3_G3H_SMC
=PP5V_S0_LCD
BUF_EDP_PANEL_PWR_EN
TCON_BKLT_PWM
I2C_TCON_SCL_CONN
I2C_CAM_SCL_CONN
LCD_PWR_SLEW
LCD_IRQ_L
ISNS_LCDPANEL_N
EDP_PANEL_PWR_EN
PM_SLP_S3_L
SMC_RESET_L
LCD_PWR_SLEW_3V3
PPVOUT_S0_LCDBKLT
EDP_INT_AUX_P
=I2C_TCON_SCL
=I2C_TCON_SDA
I2C_CAM_SCL
I2C_CAM_SDA
I2C_ALS_SDA
EDP_ML_C_P<1>
EDP_INT_ML_P<3>
EDP_ML_C_N<1>
MIPI_CLK_CONN_P
EDP_INT_ML_N<2>
EDP_INT_ML_N<1>
BUF_SMC_RESET_L
BUF_EDP_PANEL_PWR_EN
PANEL_P3V3_EN PANEL_P3V3_EN_DLY
PP3V3_S0SW_LCD
EDP_INT_ML_P<2>
DP_INT_HPD
I2C_BKLT_SDA I2C_BKLT_SCL
BUF_EDP_PANEL_PWR_EN
EDP_INT_ML_N<3>
=PP3V3_S0_LCD
EDP_INT_ML_P<0>
EDP_INT_ML_P<2>
EDP_INT_ML_N<2>
EDP_INT_ML_P<3>
EDP_INT_ML_N<3>
EDP_INT_AUX_P
EDP_ML_C_N<0>
EDP_ML_C_P<2>
EDP_ML_C_P<3>
EDP_ML_C_N<3>
SMC_RESET_L
EDP_INT_ML_P<1>
EDP_INT_ML_N<0>
PP5V_S0_ALSCAM_F
I2C_CAM_SDA_CONN
I2C_ALS_SDA_CONN
I2C_TCON_SCL_CONN
I2C_TCON_SDA_CONN
I2C_CAM_SCL_CONNMIPI_CLK_CONN_N
MIPI_DATA_CONN_P
EDP_INT_ML_N<0>
I2C_TCON_SDA_CONN
PANEL_P3V3_EN_D
MIPI_DATA_CONN_N
PPVOUT_S0_LCDBKLT
BUF_SMC_RESET_L
I2C_CAM_SDA_CONN
I2C_ALS_SDA_CONN
I2C_ALS_SCL_CONN
EDP_ML_C_P<0>
EDP_INT_AUX_N EDP_INT_AUX_P
I2C_ALS_SCL_CONNI2C_ALS_SCL
ISNS_LCDPANEL_P
BUF_EDP_PANEL_PWR_EN
PP3V3_S0SW_LCD_R
=PP3V3_S5_LCD
PANEL_P5V_ENPANEL_P5V_EN_D
EDP_INT_ML_N<1>
PP5V_S0SW_LCD
I2C_BKLT_SDA
DP_INT_HPD
EDP_BKLT_PWM
LCD_IRQ_L
BOM_COST_GROUP=DISPLAY
SYNC_MASTER=X362 SYNC_DATE=06/23/2015
eDP Display Connector
0201
CERM
25V
5%
12PF
2
1
C8573
201
MF
1/20W
5%
100K
2
1
R8510
0201
C0G
100V
+/-0.1PF
3PF
2
1
C8504
0201
C0G
100V
5%
12PF
2
1
C8503
0201
CERM
25V
5%
12PF
2
1
C8570
0201
CERM
25V
5%
12PF
2
1
C8571
0201
CERM
25V
5%
12PF
2
1
C8572
0201
CERM
25V
5%
12PF
2
1
C8551
0201
CERM
25V
5%
12PF
2
1
C8564
0201
CERM
25V
5%
12PF
2
1
C8562
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8563
0201
CERM
25V
5%
12PF
2
1
C8560
0201
C0G
25V
+/-0.1PF
3PF
2
1
C8561
0201
C0G
100V
+/-0.1PF
PLACE_NEAR=J8500:5MM
3PF
2
1
C8502
0201
C0G
100V
5%
PLACE_NEAR=J8500:5MM
12PF
2
1
C8501
0201
CERM
25V
5%
12PF
2
1
C8553
0201
CERM
25V
5%
12PF
2
1
C8554
0201
CERM
25V
5%
12PF
2
1
C8555
0201
CERM
25V
5%
12PF
2
1
C8552
0201
CERM
25V
5%
12PF
2
1
C8550
2.7X1.8R-1.4ID-0.91H-SM
1
SH8502
2.7X1.8R-1.4ID-0.91H-SM
1
SH8501
72 5
F-ST-SM
20759-042E-02
CRITICAL
6867
6665
6463
6261
6059
5857
5655
5453
5251
5049
4847
4645
4443
4241
4039
3837
3635
3433
3231
3029
2827
2625
2423
2221
2019
1817
1615
1413
1211
109
87
65
43
21
J8500
0201MF1/20W5%
0
NOSTUFF
21
R8590
0201MF1/20W5%
0
NOSTUFF
21
R8591
0201MF1/20W5%
0
NOSTUFF
21
R8592
66 41 39
68
66 53 47
68 66 53 47
72 60 59 39 26 14
66 41 39
STQFN
SLG4AP4998
CRITICAL
10
6
1
912
4 8
3
11
5
7
2
U8510
72 37
72 37
72 66 41
72 66 5
72 37
72 37
72 5
72 66 16
72 70 66
72 70
42
42
36
42
36
42
201
MF
1/20W
1%
200K
21
R8516
201
MF
1/20W
1%
330
21
R8517
201
MF
1/20W
1%
150K
21
R8515
201
MF
1/20W
1%
330
21
R8518
402
MF-LF
1/16W
5%
0
21
R8554
TDFN
SLG5AP1443V
CRITICAL
1
52
8
37
U8501
0201
X7R-CERM
10V
10%
2200PF
2
1
C8513
201MF
1/20W5%
PLACE_NEAR=J8500:5MM
33
21
R8568
201MF
1/20W5%
PLACE_NEAR=J8500:5MM
33
21
R8572
201 MF
1/20W 5%
PLACE_NEAR=J8500:5MM
33
2 1
R8562
201 MF
1/20W 5%
PLACE_NEAR=J8500:5MM
33
2 1
R8560
201 MF
1/20W 5%
PLACE_NEAR=J8500:5MM
33
2 1
R8556
201 MF
1/20W 5%
PLACE_NEAR=J8500:5MM
33
2 1
R8558
0306-SHORT
MF
1/3W
1%
0.005
OMIT
43
21
R8520
0201
X5R-CERM
10V
10%
0.1UF
2
1
C8515
SC2
DSF01S30SCAP
KA
D8517
TDFN
SLG5AP1443V
CRITICAL
1
52
8
37
U8500
SC2
DSF01S30SCAP
K A
D8518
0201
CERM-X5R
6.3V
10%
0.47UF
2
1
C8516
0603
X7R-CERM
100V
10%
PLACE_NEAR=J8500:5MM
1000PF
2
1
C8500
5
5
72 5
72 5
72 5
72 5
72 5
72 5
72 5
72 5
0201X5R-CERM
16V10%
0.1UF
21
C8529
0201X5R-CERM
16V10%
0.1UF
21
C8528
0201X5R-CERM
16V10%
0.1UF
21
C8527
0201X5R-CERM
16V10%
0.1UF
21
C8525
0201X5R-CERM
16V10%
0.1UF
21
C8526
0201X5R-CERM
16V10%
0.1UF
21
C8524
0201X5R-CERM
16V10%
0.1UF
21
C8523
0201X5R-CERM
16V10%
0.1UF
21
C8522
0201X5R-CERM
16V10%
0.1UF
21
C8521
0201X5R-CERM
16V10%
0.1UF
21
C8520
0201-1
X5R
6.3V
20%
1.0UF
2
1
C8510
201
MF
1/20W
5%
1M
2
1
R8501
201
MF
1/20W
5%
NO_XNET_CONNECTION=1
1M
2
1
R8503
201
MF
1/20W
5%
NO_XNET_CONNECTION=1
1M
2
1
R8502
0402-7
X5R-CERM
10V
20%
10UF
CRITICAL
2
1
C8512
0201
X5R-CERM
10V
10%
0.1UF
2
1
C8511
0201
X7R-CERM
10V
10%
2200PF
2
1
C8509
72 66
66
72 66 65
72 66
72 66
72 66
72 66
72 66
69
69
66
72 66 41
72 66
72 66
72 66 16
44
72 66 65
72 66
72 66
72 66
72 66 66
66 66
72 66
72 66
66
72 66
69
72 66
72 66
72 66
72 66
72 66
72 66
72 66
72 66
72 37
72 66
72 66
72 66
72 66
72 66
72 66
72 66
72 66 65
72 66
72 66
72 66
72 66
72 66
72 66
44
66
69
72 66
72 66
72 70 66
72 66 5
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
GND
SIGNAL
PWR
PWR
OUTIN
IN
IN
OUT
NC
NC
NC
NC
VDD
X604_DISP_SMC_RST_L
X604_DISP_PWR_EN
SMC_RESET_OUTPUT_L
PANEL_PWR_EN_CONN
PANEL_FET_EN_DLY
NC0
NC1
GND
SMC_RESET_INPUT_L
PM_SLP_S3_L
EDP_PANEL_PWR_EN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
CAP
ON S
D
VDD
GND
CAP
ON S
D
VDD
GND
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
(WORST CASE ??A)
ACT LIKE OPEN DRAIN
PUSH-PULL
AC CAPS FOR PCIE GEN 3
Per PCIe spec, only TX side should have AC cap
(4.7K PULLUP AT CLOCK CHIP)
(STORAGE_EN)
(BFH#)
(3.3V TOLERANT INPUT)
(OC)
FREQUENCY SPECIFIC
SSD STANDOFFS
860-00380
20A - 20MS, 2% DUTY CYCLE
514S00081
LAST CHANGE: Thu Aug 4 21:00:42 2016
DESIGN: X502/MLB_CATZ
NOTES:
9A - 5MIN
(RX)
(TX)
(PIN 47, PP3V3_EN, IS NOT USED BY SAMSUNG UAX AND SANDISK SSD.)
(3.3V)
(WORST CASE ??A)
(LPSR#)
(STORAGE_RST_L)
4. OOB SIGNALS: UART 3.3V, 115.2 KBAUD, 8B, NO PARITY, 1 STOP BIT.
1. POWER-ON TO PERST_L DE-ASSERTION = 10MS MINIMUM
3. PCIE CLK100M ARE 2.5V SIGNALS.
2. PP3V3_EN: PROVIDE 10MS EARLY WARNING TO SSD THAT POWER WILL BE OFF.
10A - 100MS, 10% DUTY CYCLE
VENDOR FERRITE DATA:
67 OF 73
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
86 OF 500
1.0.0
051-02265
SSD_PWR_EN_L SSD_PWR_EN_CONN_L
SSD_BOOT_CONN_L
PP1V8_S0
SSD_BOOT_L
PCIE_SSD_R2D_N<2>
AC_SHIELD_SSD SSD_PWR_EN_CONN_L
PP3V3_SSD_FLT
PCIE_SSD_R2D_N<0>
SSD_JTAG_TCK
PCIE_SSD_R2D_N<1>
PCIE_SSD_R2D_P<2>
PCIE_SSD_D2R_N<1>
SMC_OOB1_R2D_L
SSD_SR_EN_L
SSD_CLKREQ_L
AC_SHIELD_SSD
AC_SHIELD_SSD_RC
SSD_RESET_L SMC_OOB1_D2R_L
PCIE_SSD_R2D_N<1>
PCIE_SSD_R2D_P<2>
PCIE_SSD_R2D_N<0>
PCIE_SSD_R2D_P<1>
PCIE_CLK100M_SSD_C_N PCIE_CLK100M_SSD_C_P
PCIE_SSD_R2D_P<0>
PCIE_SSD_R2D_P<3>
PCIE_SSD_R2D_N<2>
SSD_EN
PCIE_SSD_R2D_N<3>
PCIE_SSD_D2R_P<0>
PCIE_SSD_D2R_N<0>
PCIE_SSD_D2R_N<2> PCIE_SSD_D2R_P<2>
PCIE_SSD_D2R_N<3>
SSD_JTAG_TMS
PCIE_SSD_R2D_C_N<0>
PCIE_SSD_R2D_C_P<0> PCIE_SSD_R2D_P<0>
PCIE_SSD_R2D_P<1>
PCIE_SSD_R2D_C_P<2>
PCIE_SSD_R2D_P<3>
PCIE_SSD_R2D_N<3>
PCIE_SSD_R2D_C_N<2>
PCIE_SSD_R2D_C_P<1>
PCIE_SSD_R2D_C_N<1>
PCIE_CLK100M_SSD_C_N
PCIE_CLK100M_SSD_C_P
PCIE_CLK100M_SSD_N
PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_P<3>
PPBUS_SSD_FLT
SMC_OOB1_D2R_L
STORAGE_LATCH
SSD_BOOT_CONN_L
PCIE_CLK100M_SSD_P
PCIE_SSD_R2D_C_P<3>
PP3V3_S5_SSD
SSD_SR_EN_L
SSD_CLKREQ_L
PPBUS_G3H_SSD
PP3V3_S5_SSD
PCIE_SSD_R2D_C_N<3>
SSD_EN
STORAGE_LATCH
PP3V3_S4
SSD_RESET_L
SSD_BOOT_CONN_L
SSD_PWR_EN_CONN_L
PP1V8_S5G
SMC_OOB1_R2D_L
SSD MODULE
BOM_COST_GROUP=SSD
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
NOSTUFF
0
5%
1/20W
MF
0201
2 1
R8642
NOSTUFF
0
5%
1/20W
MF
0201
2 1
R8641
100K
5% 1/20W MF 201
2
1
R8645
14
13
100K
5%
1/20W
MF
201
2
1
R8640
CRITICAL
74LVC2G125GN
SOT1116
3
6
8
7
1
4
5
2
U8640
0.1UF
10% 10V X5R-CERM 0201
2
1
C8640
12PF
5%
25V CERM 0201
2
1
C8673
3PF
+/-0.1PF 25V C0G 0201
2
1
C8674
12PF
5%
25V CERM 0201
2
1
C8675
2.9PF
+/-0.05PF 25V C0G-CERM 0201
2
1
C8676
2.9PF
+/-0.05PF
25V
C0G-CERM
0201
2
1
C8677
3.5PF
+/-0.25PF
25V C0G
0201
2
1
C8672
28
28
CRITICAL
90-OHM-0.1A
EXCX4CE
4
32
1
L8630
12PF
5%
25V CERM 0201
2
1
C8670
0.1UF
10% 10V X5R-CERM 0201
2
1
C8601
CRITICAL
3.5PF
+/-0.25PF 25V C0G 0201
2
1
C8671
72 15
72 15
72 15
72 15
72 15
72 15
72 15
72 15
3.5PF
+/-0.25PF 25V C0G 0201
2
1
C8607
3.5PF
+/-0.25PF 25V C0G 0201
2
1
C8606
100K
5% 1/16W MF-LF
402
2
1
R8610
100K
5% 1/16W MF-LF
402
2
1
R8611
67 39
67 39
4.0OD1.6ID-0.85H-TH
1
SH8600
4.0OD1.6ID-0.85H-TH
1
SH8601
CRITICAL
22UF
20%
6.3V
X5R-CERM-1
603
2
1
C8602
CRITICAL
SSD-MIDMOUNT-J130
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
F-RT-SM
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
J8600
10
5% 1/20W MF 201
2
1
R8661
0.1UF
10% 25V X5R
0201
2
1
C8660
0.1UF
10% 25V X5R 0201
2
1
C8661
CRITICAL
FERR-10-OHM-8A
0603
2 1
L8600
67 14
CRITICAL
4.7UF
10% 35V
X5R-CERM
0603
2
1
C8604
CRITICAL
FERR-10-OHM-8A
0603
2 1
L8602
0.1UF
10% 25V X5R 0201
2
1
C8603
67 19
67 19
15
15
72 15
72 15
72 15
72 15
72 15
72 15
72 15
72 15
NOSTUFF
470K
5% 1/16W MF-LF
402
2
1
R8620
100K
5% 1/16W MF-LF
402
2
1
R8621
NOSTUFF
100K
5% 1/16W MF-LF
402
2
1
R8637
67 19 16
0.22UF
20% 6.3VX5R0201
21C8617
0.22UF
20% 6.3VX5R0201
21C8616
0.22UF
20% 6.3VX5R0201
21C8615
0.22UF
20% 6.3VX5R0201
21C8614
0.22UF
20% 6.3VX5R0201
21C8611
0.22UF
20% 6.3VX5R0201
21C8610
0.22UF
20% 6.3VX5R0201
21C8613
0.22UF
20% 6.3VX5R0201
21C8612
67
72 67
72 69 64 63 60 51 50 48
72 67
67
67
72 67
72 67
72 67
67 39
67 14
67 19
67
67 19 16
67 39
72 67
72 67
72 67
72 67
67
67
72 67
72 67
72 67
67
72 67
72 67
72 67
72 67
72 67
67
67
63
67 19
72 67 69 67 44
43
69 67 44
67
72 69 64 63 45 44 43 41
72 67
67
72 69 64 61 59
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
VCC
A1
1OE*
A2
2OE*
Y2
Y1
GND
BI
IN
SYM_VER-1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
NC
NC
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
合肥怡飞苹果维修qq:82669515 qq群: 241000
VF = 2V
IF = 1MA
SYSTEM RESET BUTTON
PROCHOT IS ONLY VALID IN FULL S0, NOT S0I OR LOWER.
SMC_RESET BUTTON
(1V SIGNALS)
STUFF TO ALWAYS ENABLE LEDS.
DIAG LED BUTTON
PRESS TO ENABLE DIAG LEDS.
AS DIAG LEDS.
PLACE ON SAME SIDE
ON-BOARD POWER BUTTON
68 OF 73
99 OF 500
1.0.0
051-02265
DIAG_LED_EN_R_L
CPU_CATERR_L CATERR_LED_L
CATERR_LED
PM_SLP_S4_L
PROCHOT_LED
PM_SLP_S0S3_BUFFLED_LPM_SLP_S0S3_L
PP3V3_S5
LED_S5
LED_PLTRST_R
LED_BKLT_R
LED_G3H_R
LED_S5_R
LED_DS5_R
LED_G3H
LED_DCIN
LED_CATERR
LED_PBUS_R
DIV_PPBUS_G3H
LED_PBUS
PP3V3_G3H
LED_S0I_RLED_S0I
LED_S4_R
PM_PGOOD_P5VS4
PM_PGOOD_PVDDQ
PM_SLP_S0S3_L
LED_BKLT
LED_PROCHOT
LED_S3_R
SMC_RESET_L
PPDCIN_G3H
LED_S4
DIV_PPDCIN
LED_S3
LED_DCIN_R
LED_PROCHOT_R
LED_PLTRST
PM_SYSRST_L
EDP_BKLT_EN
PLTRST_LED_L
SYSRST_R_L
PM_RSMRST_L
PLT_RST_L
SMC_RST_BTN_R_L SMC_RST_BTN_L
PPBUS_G3H
LED_CATERR_R
SMC_ONOFF_L
PROCHOT_LED_LCPU_PROCHOT_L
SMC_ONOFF_R_L
DIAG_LED_ENABLE_L
PP3V3_S5
LED_DS5
PM_DSW_PWRGD
DEVELOPMENT ONLY
BOM_COST_GROUP=DEBUG
SYNC_MASTER=PAULM SYNC_DATE=06/15/2015
SOT563
DMN5L06VK-7
DEV_LEDS
1
2
6
Q9910
SML-P11-SM
RED-621NM-2.5MCD-1MA
DEV_LEDS
K
A
LED9910
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9910
201
MF
1/20W
5%
470K
DEV_LEDS
2 1
R9921
201
MF
1/20W
5%
470K
DEV_LEDS
2 1
R9920
66 53 47
54 40 39 6
39 19 6
65 5
35 19 14
72 68 60 19
62 60
60 39 17 14
60 58
39 14
72 69 63 53
SOT563
DMN5L06VK-7
DEV_LEDS
4
5
3
Q9900
SML-P11-SM
YELLOW-586NM-7.6MCD-1MA
DEV_LEDS
K
A
LED9901
0201
X7R
25V
10%
1000PF
NOSTUFF
2
1
C9988
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9901
SOT563
DMN5L06VK-7
DEV_LEDS
1
2
6
Q9902
SML-P11-SM
GREEN-569NM-2.1MCD-1MA
DEV_LEDS
K
A
LED9902
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9902
SOT563
DMN5L06VK-7
DEV_LEDS
4
5
3
Q9902
SML-P11-SM
GREEN-569NM-2.1MCD-1MA
DEV_LEDS
K
A
LED9903
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9903
0201
MF
1/20W
5%
0
DEV_POWER_BUTTON
2 1
R9988
SOT563
DMN5L06VK-7
DEV_LEDS
1
2
6
Q9904
SML-P11-SM
GREEN-569NM-2.1MCD-1MA
DEV_LEDS
K
A
LED9904
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9904
SOT563
DMN5L06VK-7
DEV_LEDS
4
5
3
Q9904
SML-P11-SM
YELLOW-586NM-7.6MCD-1MA
DEV_LEDS
K
A
LED9905
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9905
SOT563
DMN5L06VK-7
DEV_LEDS
1
2
6
Q9906
SML-P11-SM
GREEN-569NM-2.1MCD-1MA
DEV_LEDS
K
A
LED9906
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9906
SOT563
DMN5L06VK-7
DEV_LEDS
4
5
3
Q9906
SML-P11-SM
GREEN-569NM-2.1MCD-1MA
DEV_LEDS
K
A
LED9907
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9907
SOT563
DMN5L06VK-7
DEV_LEDS
1
2
6
Q9908
SML-P11-SM
GREEN-569NM-2.1MCD-1MA
DEV_LEDS
K
A
LED9908
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9908
SOT563
DMN5L06VK-7
DEV_LEDS
4
5
3
Q9908
SML-P11-SM
GREEN-569NM-2.1MCD-1MA
DEV_LEDS
K
A
LED9909
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9909
SML-P11-SM
YELLOW-586NM-7.6MCD-1MA
DEV_LEDS
K
A
LED9900
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9900
SOT563
DMN5L06VK-7
DEV_LEDS
1
2
6
Q9900
72 69 63 60 58 53 50 43
SM
SOX-152HNT
SILK_PART=SMC_RST
DEV_RST_BUTTONS:YES
2 1
SW9999
0201
X7R
25V
10%
1000PF
NOSTUFF
2
1
C9999
0201
MF
1/20W
5%
0
DEV_RST_BUTTONS:YES
2 1
R9999
39 17 14
SM
SOX-152HNT
SILK_PART=SMC_RST
DEV_RST_BUTTONS:YES
2 1
SW9998
0201
X7R
25V
10%
1000PF
NOSTUFF
2
1
C9998
0201
MF
1/20W
5%
0
DEV_RST_BUTTONS:YES
2 1
R9998
41
0201
X6S-CERM
6.3V
20%
1UF
2
1
C9933
201
MF
1/20W
5%
20
DEV_LEDS
2 1
R9933
SM
PLACE_SIDE=BOTTOM
SOX-152HNT
SILK_PART=PWR_BTN
DEV_POWER_BUTTON
2 1
SW9989
72 68 60 19
SOT891
74LVC1G08
CRITICAL
DEV_LEDS
4
6
5 3
1
2
U9911
0201
X5R-CERM
10V
10%
0.1UF
2
1
C9911
0201
MF
1/20W
5%
0
NOSTUFF
2 1
R9930
SM
SOX-152HNT
SILK_PART=DIAG_LED
DEV_LEDS
2 1
SW9930
GDZ-0201
GDZT2R8.2
DEV_LEDS
K A
DZ9927
201
MF
1/20W
5%
470K
DEV_LEDS
2 1
R9928
201
MF
1/20W
5%
10K
DEV_LEDS
2 1
R9922
201
MF
1/20W
5%
470K
DEV_LEDS
2
1
R9924
201
MF
1/20W
5%
470K
DEV_LEDS
2
1
R9923
SM
PLACE_SIDE=TOP
SOX-152HNT
SILK_PART=PWR_BTN
DEV_POWER_BUTTON
2 1
SW9988
201
MF
1/20W
5%
100K
DEV_LEDS
2 1
R9926
201
MF
1/20W
5%
100K
DEV_LEDS
2 1
R9925
SOT963
DST3904DJ
DEV_LEDS
4
3
5
Q9922
SOT963
DST3904DJ
DEV_LEDS
1
6
2
Q9922
SOT563
DMN5L06VK-7
DEV_LEDS
4
5
3
Q9910
SML-P11-SM
RED-621NM-2.5MCD-1MA
DEV_LEDS
K
A
LED9911
201
MF
1/20W
5%
1.3K
DEV_LEDS
2 1
R9911
72 40 39 38
72 60 39 14
72 69 68 64 63 61 60 58 44
72
69 60 53 52 51 47 42 41 28 19
72 69 68 64 63 61 60 58 44
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
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IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
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2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
DS
VER 5
G
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DS
VER 5
G
DS
VER 5
G
DS
VER 5
G
DS
VER 5
G
DS
VER 5
G
DS
VER 5
G
DS
VER 5
G
DS
VER 5
G
DS
VER 5
G
DS
VER 5
G
IN
OUT
OUT
IN
08
NC
NC
DS
VER 5
G
OUT
合肥怡飞苹果维修qq:82669515 qq群: 241000
USB-C GLOBAL POWER ALIASES
Digital Ground
DESIGN: X502/MLB_CATZ
CPU RAILS
LAST CHANGE: Mon Aug 8 19:33:56 2016
PCH RAILS
SSD RAILS
69 OF 73
MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.0850
VOLTAGE=0V
100 OF 500
1.0.0
051-02265
=PP3V3_UPC_XB_AUX
MAKE_BASE=TRUE
PP3V3_UPC_XB_LDO
=PP3V3_UPC_XA_AUX
MAKE_BASE=TRUE
PP3V3_UPC_XA_LDO
=PPHV_EXT_G3H
MAKE_BASE=TRUE
PPDCIN_G3H
=PP5V_USBC
=PP5V_XA_USBC =PP5V_XB_USBC
=PP3V3_S5_TBT_X
MAKE_BASE=TRUE
PP3V3_S5
MAKE_BASE=TRUE
PP5V_S4
=PP3V3_SUS_PCH_VCCPGPPC
=PPVCC_S0_CPU
=PP1V2_S3_CPU_VDDQ
PP1V_S0G
MAKE_BASE=TRUE
PP3V1_RTC
MAKE_BASE=TRUE
PP3V3_S4
MAKE_BASE=TRUE
PP5V_S0
MAKE_BASE=TRUE
PP3V3_S0
MAKE_BASE=TRUE
=PP3V3_S0_CAMERA
=PP5V_S0_ALSCAM
=PP3V3_S4_WLAN PP3V3_S4_WLS
MAKE_BASE=TRUE
=PP3V3_S5_WIRELESS PP3V3_S5
MAKE_BASE=TRUE
=PP5V_S0_LCD PP5V_S0
MAKE_BASE=TRUE
=PP3V3_S0_LCD PP3V3_S0
MAKE_BASE=TRUE
=PP3V3_S5_LCD PP3V3_S5
MAKE_BASE=TRUE
=PPBUS_S4_TPAD PPBUS_G3H_TPAD
MAKE_BASE=TRUE
=PP3V3_S0_TPAD PP3V3_S0
MAKE_BASE=TRUE
=PP3V3_S4_TPAD PP3V3_S4
MAKE_BASE=TRUE
=PP5V_S0_KBD PP5V_S0
MAKE_BASE=TRUE
=PP3V3_G3H_KBD PP3V3_G3H
MAKE_BASE=TRUE
=PP3V3_G3H_SMC PP3V3_G3H
MAKE_BASE=TRUE
PP3V3_G3H
MAKE_BASE=TRUE
=PP3V3_S5_SMC
=PP3V3R1V8_S0_PCH_VCCPGPPB
PPVREF_S3_MEM_VREFCA
=PPDDR_S3_MEMVREF
=PP0V6_S0_MEM_VTT_B
=PPVIN_S5_SMCVREF
PP0V6_S3_MEM_VREFDQ_B
MAKE_BASE=TRUE
PPVREF_S3_MEM_VREFCA
PPVREF_S3_MEM_VREFDQ_B
PP0V6_S3_MEM_VREFCA_B
MAKE_BASE=TRUE
PPVREF_S3_MEM_VREFDQ_A PP0V6_S3_MEM_VREFDQ_A
MAKE_BASE=TRUE
PP0V6_S3_MEM_VREFCA_A
MAKE_BASE=TRUE
PPVTT_S0
MAKE_BASE=TRUE
PPVTT_S0
MAKE_BASE=TRUE
=PP0V6_S0_MEM_VTT_A
=PPVIN_S0SW_LCDBKLTFET
PP3V3_S4
MAKE_BASE=TRUE
PP1V2_S3
MAKE_BASE=TRUE
PP1V2_S3
MAKE_BASE=TRUE
=PP5V_S5_LDO
=PP1V_SUS_PCH_VCCCLK5_SRC
=PP1V_SUS_PCH_VCCPRIM
PP3V3_S5G
MAKE_BASE=TRUE
PP3V3_S5G
MAKE_BASE=TRUE
PP3V3_S5G
MAKE_BASE=TRUE
PP3V3_S0
MAKE_BASE=TRUE
=PP3V3_S0_SMC
PP1V2_S3
MAKE_BASE=TRUE
=PP1V2_S3_MEM_VDDQ
PP5V_S5
MAKE_BASE=TRUE
=PPBUS_G3H
=PP1V2_S3_MEM_VDDCA PP1V2_S3
MAKE_BASE=TRUE
=PP1V2_S3_MEM_VDD2
=PP1V8_S3_MEM PP1V8_S3
MAKE_BASE=TRUE
PP3V3_G3H
MAKE_BASE=TRUE
=PP3V3_S4_BT_UART
PPVCCGT_S0G
MAKE_BASE=TRUE
PPVCCCPU_S0G
MAKE_BASE=TRUE
=PP3V3_TBT_X_S0=PP3V3_S0_TBT_X_SNS
PP3V3_S5G
MAKE_BASE=TRUE
=PP3V3_SUS_XDP
PP5V_S0
MAKE_BASE=TRUE
=PP3V3_S0_BT_UART
PP3V3_S4
MAKE_BASE=TRUE
PP3V3_S0
MAKE_BASE=TRUE
=PP5V_S0_FAN
=PP1V_SUS_PCH_VCCPRIM
PP1V_S5GTD
MAKE_BASE=TRUE
=PP1V_SUSSW_PCH_VCCAPLLEBB
=PP1V8R1V5_S0_PCH_VCCHDA
PP3V3_S4
MAKE_BASE=TRUE
CPU_VCCGTXSENSE_P CPU_VCCGTXSENSE_N
PP3V3_S5_SSD_SNS
MAKE_BASE=TRUE
PP3V3_S5G
MAKE_BASE=TRUE
PP3V3_S5G
MAKE_BASE=TRUE
=PP1V_SUS_XDP
=PPDCIN_G3H_SNS PPDCIN_G3H
MAKE_BASE=TRUE
PPBUS_G3H
MAKE_BASE=TRUE
=PP1V_SUS_PCH_VCCCLK3
=PPVCCPRIMECORE_SUS_PCH
=PP1V_S0SW_CPU_VCCSTG =PP1V_S3_CPU_VCCPLL
PP1V_S5G
MAKE_BASE=TRUE
PPVCCPCH_S5G
MAKE_BASE=TRUE
=PP3V3_S4_KBD
PPVCCSA_S0G
MAKE_BASE=TRUE
=PP5V_S4_TPAD
PP1V2_S3
MAKE_BASE=TRUE
PPVCCIO_S0G
MAKE_BASE=TRUE
PPBUS_G3H
MAKE_BASE=TRUE
PP5V_S0
MAKE_BASE=TRUE
=PP5V_S0_BKLT
PP1V8_S0
MAKE_BASE=TRUE
=PP3V3_SUS_PCH_VCCPGPPD
PP1V_S3
MAKE_BASE=TRUE
PP1V_S3
MAKE_BASE=TRUE
=PP3V3_SUS_PCH_VCCPGPPB
PP1V_S5G
MAKE_BASE=TRUE
=PP1V2_S3_CPU_VDDQC
=PP1V_S3_CPU_VCCST =PP1V_S0_SMC_VCCST
=PP3V3_SUS_PCH_VCCSPI
PP3V3_S5
MAKE_BASE=TRUE
=PP3V3_S5_PCH_VCCDSW
=PP1V8_SUS_PCH_VCCATS
=PP1V_SUSSW_PCH_VCCMPHYGT
=PP3V3_S4_PCH
=PP3V3_S0_PCH
=PP0V95_S0_CPU_VCCIO
=PPVCCSA_S0_CPU =PPVCCGT_S0_CPU
PP1V8_S5G
MAKE_BASE=TRUE
PP3V3_S0
MAKE_BASE=TRUE
PP3V3_S0
MAKE_BASE=TRUE
PP3V3_S5G
MAKE_BASE=TRUE
=PP1V8_SUS_PCH_VCCPGPPF
=PP3V3_SUS_PCH_VCCPGPPG
PP1V_S5G
MAKE_BASE=TRUE
PP1V_S5G
MAKE_BASE=TRUE
PP1V_S5G
MAKE_BASE=TRUE
PP1V_S5G
MAKE_BASE=TRUE
PP1V_S5G
MAKE_BASE=TRUE
=PP1V_SUS_PCH_VCCCLK4_SRC
=PP1V_SUSSW_PCH_VCCSRAM
PP1V_S5G
MAKE_BASE=TRUE
PP1V8_S5G
MAKE_BASE=TRUE
PP1V_S5G
MAKE_BASE=TRUE
=PP1V8_S0_PCH_VCCHDA
=PP1V_SUS_PCH_VCCAPLL
=PP1V8_SUS_PCH_VCC1P8_SRC
=PP1V_SUSSW_PCH_VCCAMPHYPLL_SRC
=PP1V_SUS_PCH_VCCCLK2_SRC
PP3V3_S5G
MAKE_BASE=TRUE
=PP1V2_S0SW_CPU_VCCPLLOC
=PP3V3_SUS_PCH_VCCPGPPE
=PP3V3_SUS_PCH_VCCPRIM
=PP3V3_SUS_PCH_VCCPGPPA
PD_VSNS_CPU_VCCGTX_TN
MAKE_BASE=TRUE
PU_VSNS_CPU_VCCGTX_TP
MAKE_BASE=TRUE
PPVCCGT_S0G
MAKE_BASE=TRUE
=PP3V3_S4_SMC
PP3V3_S5G
MAKE_BASE=TRUE
=PP3V_G3H_PCH_VCCRTC
PP3V3_S5_SSD
PP5V_S4
MAKE_BASE=TRUE
PP3V3_S5G
MAKE_BASE=TRUE
=PP1V_SUS_PCH_VCCCLK6
=PP1V2_S3_CPU_VDDQ
PP1V2_S0G
MAKE_BASE=TRUE
=PPVCCGTX_S0_CPU
PP1V_S5GTD
MAKE_BASE=TRUE
PP1V_S5GTD
MAKE_BASE=TRUE
PP1V_S5GTD
MAKE_BASE=TRUE
PP1V8_S5G
MAKE_BASE=TRUE
=PP1V_SUS_PCH_VCCCLK1
=PP1V_SUS_PCH_VCCMPHYAON
=PP3V3_SUS_PCH_VCCRTCPRIM
GND
Power Aliases
BOM_COST_GROUP=NO COST ITEMS
SYNC_MASTER=X502-EXP SYNC_DATE=12/03/2015
30 63 30 28
29 29 28
30 29 72 69 68 63 53
28
29
30
33 72 69 68 64 63 61 60 58 44
72 69 64 63 60 58 54
12 8
10 8
69 10 8
64
61
72 69 67 64 63 45 44 43 41
72 69 64 59 57 56 55 54
69
64 63 60 59 54 49 46 45 42 38 36
37
34 19 72 63 44
18 72 69 68 64 63 61 60 58 44
66 72 69 64 59 57 56 55 54
66
69
64 63 60 59 54
49 46 45 42 38
66 72 69 68 64 63 61 60 58 44
38 43
38
69
64 63 60 59 54 49 46 45 42 38
38 72 69 67 64 63 45 44 43 41
38 72 69 64 59 57 56 55 54
38
72 69
68 60 53 52 51 47 42 41 28 19
66
72 69
68 60 53 52 51 47 42 41 28 19
72 69
68 60 53 52 51 47 42 41 28 19
40 39
40
69 20
20
25
40
24 23
69 20
20
24 23
20 22 21
22 21
72 69 62
72 69 62 25
65
72 69 67 64 63 45 44 43 41
69 64 63 62
69 64 63 62
58
12
69 12 8
72 69 64 60
72 69 64 60
72 69 64 60
69
64 63 60 59 54 49 46 45 42 38 40
69 64 63 62
24 23 22 21
64 63
52 32 31
24 23 22 21 69 64 63 62
24 23 22 21
24 23 22 21 64 63 60
72 69
68 60 53 52 51 47 42 41 28 19
35
72 69 63 57 45
72 63 55 45
28 27 45
72 69 64 60 60 17
72 69 64 59 57 56 55 54
35
72 69 67 64 63 45 44 43 41
69
64 63 60 59 54 49 46 45 42 38
38
69 12 8
69 64
12 8
18
72 69 67 64 63 45 44 43 41
8
8
63
72 69 64 60
72 69 64 60
17
43 72 69 68 63 53
72 69 68 63 60 58 53 50 43
8
12 8
17 10 8 6
10 8
72 69 64 63 62 19
72 63 61
38
72 56
38
69 64 63 62
72 63 61
72 69 68 63 60 58 53 50 43
72 69 64 59 57 56 55 54 65
72 67 64 63 60 51 50 48
8
69 64
69 64
19 12 8
72 69 64 63 62 19
10 8
59 54 19 14 10 8 6
40
47 13 8
72 69 68 64 63 61 60 58 44 14 8
12 8
12 8
14
60 19 16 14 13
5
10 8 5
10 8
11 8
72 69 67 64 61 59
69
64 63 60 59 54 49 46 45 42 38
69
64 63 60 59 54 49 46 45 42 38
72 69 64 60
14 8
8
72 69 64 63 62 19
72 69 64 63 62 19
72 69 64 63 62 19
72 69 64 63 62 19
72 69 64 63 62 19
12
12 8
72 69 64 63 62 19
72 69 67 64 61 59
72 69 64 63 62 19
12
15 12
12
12
12
72 69 64 60
10 8
12 8
12 8 5
16 15 14 13 8
72 69 63 57 45
40
72 69 64 60
15 14 12 8
67 44
72 69 64 63 60 58 54
72 69 64 60
12 8
69 10 8
64
11 8
69 64
69 64
69 64
72 69 67 64 61 59
8
12 8
12 8
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
合肥怡飞苹果维修qq:82669515 qq群: 241000
Digital Ground
DESIGN: X502/MLB_CATZ LAST CHANGE: Mon Aug 8 12:54:34 2016
MAKE_BASE
UNUSED GPIOS, HSIO
70 OF 73
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
MIN_NECK_WIDTH=0.0850
MIN_LINE_WIDTH=0.3000
VOLTAGE=0V
102 OF 500
1.0.0
051-02265
USB_EXTA_P
NC_USB2_07N NC_USB2_07P
PCIE_TBT_T_R2D_C_N<0>
USB_CAMERA_DFR_P
USB3_EXTB_D2R_N
TP_USB3_03_D2RN
MAKE_BASE=TRUE
NC_PMIC_PGC
MAKE_BASE=TRUE
NC_USB3_04_D2RP
NC_PCH_SOC_FORCE_DFU
MAKE_BASE=TRUE
NC_PCH_SOC_WDOG
MAKE_BASE=TRUE
NC_UPC_XA_SWD_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_UPC_XA_SWD_DATA
TP_USB3_03_R2DN
MAKE_BASE=TRUE
NC_USB3_03_R2DP
TP_USB3_04_D2RP TP_USB3_04_R2DN
MAKE_BASE=TRUE
NC_USB3_04_R2DN NC_USB3_04_R2DP
MAKE_BASE=TRUE
NC_UPC_I2C_INT_L
MAKE_BASE=TRUE
NC_UPC_XB_SWD_DATA
MAKE_BASE=TRUE
NC_CPU_RSVD_AW70
MAKE_BASE=TRUE
NC_PCH_CLK24M_XTALOUT
MAKE_BASE=TRUE
NC_PCH_CLK32K_RTCX2
MAKE_BASE=TRUE
NC_PGOOD_P1V00
MAKE_BASE=TRUE
NC_PGOOD_PVCCIO
MAKE_BASE=TRUE
NC_SPKR_ID0
MAKE_BASE=TRUE
NC_CPU_RSVD_AK12
MAKE_BASE=TRUE
NC_CPU_RSVD_AW71
MAKE_BASE=TRUE
NC_CPU_RSVD_BA68
MAKE_BASE=TRUE
NC_CPU_RSVD_BA70
MAKE_BASE=TRUE
NC_CPU_RSVD_BB68
MAKE_BASE=TRUE
NC_CPU_RSVD_BB69
MAKE_BASE=TRUE
NC_CPUVR_GH1
MAKE_BASE=TRUE
NC_ITPXDP_CLK100MN
MAKE_BASE=TRUE
NC_ITPXDP_CLK100MP
MAKE_BASE=TRUE
NC_PCH_CLKREQ5_L
MAKE_BASE=TRUE
NC_PCIE_CLK100M5N
MAKE_BASE=TRUE
NC_PCIE_CLK100M5P
MAKE_BASE=TRUE
NC_XDP_BPM_L<2>
MAKE_BASE=TRUE
NC_XDP_BPM_L<3>
MAKE_BASE=TRUE
TP_PGOOD_PVCCIO
TP_SPKR_ID0
TP_CPU_RSVD_BA68
TP_CPUVR_GH1
PCH_SOC_WDOG
PCH_SOC_FORCE_DFU
TP_USB3_04_R2DP
TP_USB3_04_D2RN
MAKE_BASE=TRUE
NC_USB3_04_D2RN
MAKE_BASE=TRUE
NC_USB3_03_R2DN
MAKE_BASE=TRUE
NC_USB3_03_D2RP
TP_CPU_RSVD_BA70
TP_CPU_RSVD_AW70
TP_CPU_RSVD_AW71
TP_CPU_RSVD_BB68
TP_CPU_RSVD_BB69
TP_ITPXDP_CLK100MN
TP_UPC_XA_SWD_CLK
TP_UPC_XA_SWD_DATA
TP_PCIE_CLK100M5N
TP_PCIE_CLK100M5P
UPC_I2C_INT_L
TP_UPC_XB_SWD_DATA
PCIE_TBT_T_D2R_N<0> PCIE_TBT_T_D2R_P<0>
USB_CAMERA_DFR_N
MAKE_BASE=TRUE
NC_DEBUGUART_SEL_SOC
MAKE_BASE=TRUE
NC_USB3_EXTB_R2DCP
PCIE_TBT_T_D2R_N<1>
PCIE_CLK100M_TBT_T_N
=TBT_T_CLKREQ_L
TBT_T_CIO_PWR_EN
NC_USB2_06P
NC_USB2_09N
VCCPRIM_CORE_VID0
MLB_DEV_L
TBT_X_DPMUX_SEL
PCIE_CLK100M_TBT_T_P
MAKE_BASE=TRUE
NC_TBT_X_DPMUX_SEL
MAKE_BASE=TRUE
NC_TBT_T_USB_PWR_EN
MAKE_BASE=TRUE
NC_TBT_T_PCI_RESET_L
TBT_T_USB_PWR_EN
TBT_T_DPMUX_SEL
MAKE_BASE=TRUE
NC_PCIE_CLK100M_TBT_TP
MAKE_BASE=TRUE
NC_TBT_T_CIO_PWR_EN
PCIE_TBT_T_D2R_P<1>
NC_USB2_05N
NC_USB2_06N
NC_USB2_09P
NC_USB2_10P
TRUE
I2C_BKLT_SCL
TRUE
I2C_BKLT_SDA
=I2C_BKLT_SCL =I2C_BKLT_SDA
MAKE_BASE=TRUE
NC_PCIE_TBT_T_D2RN0
I2C_UPC_SCL
USB3_EXTB_R2D_C_N USB3_EXTB_R2D_C_P
PCIE_TBT_T_R2D_C_P<0>
VCCPRIM_CORE_VID1
NC_USB2_10N
I2C_UPC_SDA
NO_TEST=1MAKE_BASE=TRUE
NC_DP_X_SRC_ML_CP<3..0>
NC_UPC_XB_I2C_ADDR
MAKE_BASE=TRUE
NC_DP_X_SRC_AUXCHN
MAKE_BASE=TRUE
NC_PCIE_TBT_T_D2RP0
MAKE_BASE=TRUE
NC_PCIE_TBT_T_D2RN1
MAKE_BASE=TRUE
NC_PCIE_TBT_T_R2D_CN1
TBT_T_PCI_RESET_L
MAKE_BASE=TRUE
NC_PCIE_TBT_T_R2D_CP0
MAKE_BASE=TRUE
NC_PCIE_TBT_T_R2D_CN0
=DP_X_SRC_AUX_N
=DP_X_SRC_AUX_P
MAKE_BASE=TRUE
NC_DP_X_SRC_AUXCHP
=DP_X_SRC_ML_N<3..0>
=DP_X_SRC_ML_P<3..0>
MAKE_BASE=TRUE
NC_USB3_EXTB_R2DCN
NO_TEST=1MAKE_BASE=TRUE
NC_DP_X_SRC_ML_CN<3..0>
NC_USB2_05P
PCIE_TBT_T_R2D_C_N<1>
DEBUGUART_SEL_SOC
MAKE_BASE=TRUE
NC_BT_I2S_CLK
MAKE_BASE=TRUE
NC_BT_I2S_R2D
MAKE_BASE=TRUE
NC_BT_I2S_D2R
MAKE_BASE=TRUE
NC_BT_I2S_SYNC
MAKE_BASE=TRUE
NC_CAM_GPIO3
MAKE_BASE=TRUE
NC_CPU_AT5
TP_BT_I2S_R2D TP_BT_I2S_SYNC
TP_CPU_AT5
TP_CAM_GPIO3
MAKE_BASE=TRUE
NC_CPU_AU5
MAKE_BASE=TRUE
NC_CPU_BB3
MAKE_BASE=TRUE
NC_CPU_AY4
MAKE_BASE=TRUE
NC_CPU_BB5
MAKE_BASE=TRUE
NC_CPU_MSM_L
MAKE_BASE=TRUE
NC_CPU_NCTFVSS_A5
MAKE_BASE=TRUE
NC_CPU_NCTFVSS_A70
MAKE_BASE=TRUE
NC_CPU_NCTFVSS_AV1
MAKE_BASE=TRUE
NC_CPU_NCTFVSS_B71
MAKE_BASE=TRUE
NC_CPU_NCTFVSS_BA1
MAKE_BASE=TRUE
NC_CPU_NCTFVSS_BA71
MAKE_BASE=TRUE
NC_CPU_NCTFVSS_BB70
MAKE_BASE=TRUE
NC_CPU_NCTFVSS_C1
MAKE_BASE=TRUE
NC_PCH_CLKOUT_LPC1
MAKE_BASE=TRUE
NC_PCH_GPD7
MAKE_BASE=TRUE
NC_PCH_GPP_D1
MAKE_BASE=TRUE
NC_PCH_GPP_D3
MAKE_BASE=TRUE
NC_PCH_GPP_D4
MAKE_BASE=TRUE
NC_PCH_GPP_E15
MAKE_BASE=TRUE
NC_PCH_GPP_F8
MAKE_BASE=TRUE
NC_PCH_GPP_F9
MAKE_BASE=TRUE
NC_PCH_GPP_F10 NC_PCH_GPP_F11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_GPP_F18
MAKE_BASE=TRUE
NC_PCH_GPP_F19
MAKE_BASE=TRUE
NC_PCH_GPP_F20
MAKE_BASE=TRUE
NC_PCH_GPP_F21
MAKE_BASE=TRUE
NC_PCH_LANPHYPC
MAKE_BASE=TRUE
NC_PCH_PME_L
MAKE_BASE=TRUE
NC_PCH_SLP_WLAN_L
MAKE_BASE=TRUE
NC_PCH_STRP_ESPI
MAKE_BASE=TRUE
NC_PCH_STRP_TLSCONF
MAKE_BASE=TRUE
NC_SPI_CS1_L
MAKE_BASE=TRUE
NC_SPI_CS2_L NC_SYSCLK_CLK24M_SSD
MAKE_BASE=TRUE
TP_CPU_AU5 TP_CPU_AY4 TP_CPU_BB3 TP_CPU_BB5 TP_CPU_MSM_L TP_CPU_NCTFVSS_A5
TP_CPU_NCTFVSS_AV1
TP_CPU_NCTFVSS_A70
TP_CPU_NCTFVSS_BA71
TP_CPU_NCTFVSS_BA1
TP_CPU_NCTFVSS_B71
TP_CPU_NCTFVSS_BB70 TP_CPU_NCTFVSS_C1
TP_PCH_CLKOUT_LPC1 TP_PCH_GPD7
TP_PCH_GPP_D0
TP_PCH_GPP_D3
TP_PCH_GPP_D1
TP_PCH_GPP_D4 TP_PCH_GPP_E15 TP_PCH_GPP_F8
TP_PCH_GPP_F10
TP_PCH_GPP_F9
PCH_SOC_DFU_STATUS
PCH_BT_ROM_BOOT
SOC_PANIC_L
SOC_SLEEP_L
SOC_S2R_ACK_L
TP_PCH_LANPHYPC TP_PCH_PME_L
TP_PCH_SLP_WLAN_L TP_PCH_STRP_ESPI
TP_PMIC_PGC
TP_SYSCLK_CLK24M_SSD
NC_USB3_03_D2RN
MAKE_BASE=TRUE
TP_USB3_03_D2RP
TP_USB3_03_R2DP
TP_PCH_CLKREQ5_L TP_ITPXDP_CLK100MP
TP_CPU_RSVD_AK12
NC_XDP_BPM_L<1>
MAKE_BASE=TRUE
TP_PGOOD_P1V00 TP_PCH_CLK32K_RTCX2 TP_PCH_CLK24M_XTALOUT TP_XDP_BPM_L<3> TP_XDP_BPM_L<2> TP_XDP_BPM_L<1>
MAKE_BASE=TRUE
NC_VCCPRIM_CORE_VID1
PCH_BSSB_CLK
MAKE_BASE=TRUE
NC_I2C_UPC_SCL
TP_BT_I2S_CLK TP_BT_I2S_D2R
MAKE_BASE=TRUE
NC_PCH_GPP_D0
MAKE_BASE=TRUE
NC_TBT_T_DPMUX_SEL
TP_SPI_CS2_L
TP_SPI_CS1_L
TP_PCH_STRP_TLSCONF
MAKE_BASE=TRUE
NC_USB3_EXTB_D2RP
MAKE_BASE=TRUE
NC_PCIE_TBT_T_D2RP1
PCH_BSSB_DATA
MAKE_BASE=TRUE
NC_MLB_DEV_L
USB3_EXTB_D2R_P
PCIE_TBT_T_R2D_C_P<1>
MAKE_BASE=TRUE
NC_PCH_BSSB_DATA
NC_PCH_BSSB_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_I2C_UPC_SDA
MAKE_BASE=TRUE
NC_VCCPRIM_CORE_VID0
NC_USB2_03P
MAKE_BASE=TRUE
NC_USB2_03N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_TBT_T_R2D_CP1
NC_USB3_EXTB_D2RN
MAKE_BASE=TRUE
NC_USB2_01N
MAKE_BASE=TRUE
NC_USB2_01P
MAKE_BASE=TRUE
USB_EXTA_N
MAKE_BASE=TRUE
NC_PCIE_CLK100M_TBT_TN
MAKE_BASE=TRUE
NC_TBT_T_CLKREQ_L
GND
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
NC_ AND NO_TEST SIGNALS
BOM_COST_GROUP=NO COST ITEMS
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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
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合肥怡飞苹果维修qq:82669515 qq群: 241000
DESIGN: X502/MLB_CATZ LAST CHANGE: Thu Aug 4 21:00:42 2016
DRAMDRAMCPU CPU
Memory Bit/Byte Swizzle
MAKE_BASE MAKE_BASE
71 OF 73
103 OF 500
1.0.0
051-02265
=MEM_B_DQ<6>
=MEM_B_DQ<1> =MEM_B_DQ<3>
=MEM_B_DQ<5> =MEM_B_DQ<2> =MEM_B_DQ<0> =MEM_B_DQ<16> =MEM_B_DQ<20> =MEM_B_DQ<19>
=MEM_B_DQ<21> =MEM_B_DQ<17>
=MEM_B_DQ<18>
=MEM_B_DQ<22>
=MEM_B_DQ<40>
MEM_B_DQ<4>
TRUE
MEM_B_DQ<5>
TRUE
MEM_B_DQ<6>
TRUE
MEM_B_DQ<7>
TRUE
MEM_B_DQ<8>
TRUE
MEM_B_DQ<9>
TRUE
TRUE
MEM_B_DQ<10> MEM_B_DQ<11>
TRUE
MEM_B_DQ<12>
TRUE
MEM_B_DQ<13>
TRUE
MEM_B_DQ<14>
TRUE
MEM_B_DQ<15>
TRUE
=MEM_B_DQ<41> =MEM_B_DQ<45> =MEM_B_DQ<46> =MEM_B_DQ<42> =MEM_B_DQ<43> =MEM_B_DQ<44> =MEM_B_DQ<47>
=MEM_B_DQ<59> =MEM_B_DQ<57> =MEM_B_DQ<61>
=MEM_B_DQ<62>
=MEM_B_DQ<58>
=MEM_B_DQ<60> =MEM_B_DQ<56> =MEM_B_DQ<10> =MEM_B_DQ<9> =MEM_B_DQ<12> =MEM_B_DQ<13> =MEM_B_DQ<11> =MEM_B_DQ<15> =MEM_B_DQ<14> =MEM_B_DQ<8> =MEM_B_DQ<24> =MEM_B_DQ<31>
=MEM_B_DQ<27> =MEM_B_DQ<25> =MEM_B_DQ<28> =MEM_B_DQ<30> =MEM_B_DQ<29> =MEM_B_DQ<32> =MEM_B_DQ<33> =MEM_B_DQ<34> =MEM_B_DQ<38> =MEM_B_DQ<36> =MEM_B_DQ<37>
=MEM_B_DQ<39> =MEM_B_DQ<55> =MEM_B_DQ<54>
MEM_B_DQ<48>
TRUE
MEM_B_DQ<49>
TRUE
TRUE
MEM_B_DQ<50> MEM_B_DQ<51>
TRUE
MEM_B_DQ<53>
TRUE
MEM_B_DQ<57>
TRUE
=MEM_B_DQ<50> =MEM_B_DQ<51> =MEM_B_DQ<52> =MEM_B_DQ<53> =MEM_B_DQ<49> =MEM_B_DQ<48>
=MEM_B_DQS_P<0> =MEM_B_DQS_N<0>
=MEM_B_DQS_N<2> =MEM_B_DQS_P<5> =MEM_B_DQS_N<5> =MEM_B_DQS_P<7>
=MEM_B_DQS_N<1> =MEM_B_DQS_P<3> =MEM_B_DQS_N<3>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DQS_P<6> =MEM_B_DQS_N<6>
TRUE
MEM_B_DQ<60> MEM_B_DQ<61>
TRUE
MEM_B_DQ<62>
TRUE
MEM_B_DQ<63>
TRUE
MEM_B_DQS_P<0>
TRUE
MEM_B_DQS_N<0>
TRUE
MEM_B_DQS_P<1>
TRUE
MEM_B_DQS_N<1>
TRUE
MEM_B_DQS_P<6>
TRUE
MEM_B_DQS_N<6>
TRUE
MEM_B_DQS_P<7>
TRUE
MEM_B_DQS_N<7>
TRUE
=MEM_A_DQ<16> =MEM_A_DQ<17>
=MEM_A_DQ<19>
=MEM_A_DQ<21>
=MEM_A_DQ<4>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<3>
=MEM_A_DQ<0>
=MEM_A_DQ<1> =MEM_A_DQ<5> =MEM_A_DQ<46>
TRUE
MEM_A_DQ<0>
MEM_A_DQ<6>
TRUE
MEM_A_DQ<8>
TRUE
MEM_A_DQ<11>
TRUE
MEM_A_DQ<12>
TRUE
MEM_A_DQ<14>
TRUE
=MEM_A_DQ<42>
=MEM_A_DQ<47>
=MEM_A_DQ<43>
=MEM_A_DQ<45>
=MEM_A_DQ<56> =MEM_A_DQ<62> =MEM_A_DQ<58>
=MEM_A_DQ<57>
=MEM_A_DQ<60>
=MEM_A_DQ<13>
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<27> =MEM_A_DQ<30> =MEM_A_DQ<28>
=MEM_A_DQ<31>
=MEM_A_DQ<29>
=MEM_A_DQ<26> =MEM_A_DQ<39> =MEM_A_DQ<33>
=MEM_A_DQ<36>
=MEM_A_DQ<34> =MEM_A_DQ<35>
TRUE
MEM_A_DQ<50> MEM_A_DQ<51>
TRUE
MEM_A_DQ<52>
TRUE
MEM_A_DQ<54>
TRUE
MEM_A_DQ<55>
TRUE
=MEM_A_DQ<54>
=MEM_A_DQS_P<2>
=MEM_A_DQ<50>
=MEM_A_DQS_N<2> =MEM_A_DQS_P<0> =MEM_A_DQS_N<0>
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<1>
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<3>
=MEM_A_DQS_N<1>
=MEM_A_DQS_N<3> =MEM_A_DQS_P<4> =MEM_A_DQS_N<4> =MEM_A_DQS_P<6> =MEM_A_DQS_N<6>
MEM_A_DQ<58>
TRUE
MEM_A_DQ<61>
TRUE
MEM_A_DQ<62>
TRUE
MEM_A_DQ<63>
TRUE
MEM_A_DQS_N<0>
TRUE
MEM_A_DQS_N<1>
TRUE
MEM_A_DQS_N<6>
TRUE
MEM_A_DQS_P<7>
TRUE
MEM_A_DQS_N<7>
TRUE
MEM_A_DQ<32>
TRUE
MEM_A_DQ<33>
TRUE
MEM_A_DQ<35>
TRUE
MEM_A_DQ<36>
TRUE
MEM_A_DQ<37>
TRUE
MEM_A_DQ<38>
TRUE
MEM_A_DQ<39>
TRUE
MEM_A_DQ<41>
TRUE
MEM_A_DQ<42>
TRUE
MEM_A_DQ<44>
TRUE
MEM_A_DQ<45>
TRUE
MEM_A_DQ<16>
TRUE
MEM_A_DQ<17>
TRUE
MEM_A_DQ<19>
TRUE
MEM_A_DQ<21>
TRUE
MEM_A_DQ<25>
TRUE
MEM_A_DQ<26>
TRUE
MEM_A_DQ<27>
TRUE
MEM_A_DQ<28>
TRUE
MEM_A_DQ<29>
TRUE
TRUE
MEM_A_DQ<30> MEM_A_DQ<31>
TRUE
MEM_A_DQS_N<5>
TRUE
MEM_A_DQS_N<2>
TRUE
MEM_A_DQS_P<3>
TRUE
MEM_B_DQ<32>
TRUE
MEM_B_DQ<33>
TRUE
MEM_B_DQ<34>
TRUE
MEM_B_DQ<35>
TRUE
MEM_B_DQ<36>
TRUE
MEM_B_DQ<37>
TRUE
MEM_B_DQ<38>
TRUE
MEM_B_DQ<39>
TRUE
TRUE
MEM_B_DQ<40> MEM_B_DQ<41>
TRUE
MEM_B_DQ<42>
TRUE
MEM_B_DQ<43>
TRUE
MEM_B_DQ<44>
TRUE
MEM_B_DQ<45>
TRUE
MEM_B_DQ<46>
TRUE
MEM_B_DQ<47>
TRUE
MEM_B_DQ<16>
TRUE
MEM_B_DQ<17>
TRUE
MEM_B_DQ<18>
TRUE
MEM_B_DQ<19>
TRUE
TRUE
MEM_B_DQ<20> MEM_B_DQ<21>
TRUE
MEM_B_DQ<22>
TRUE
MEM_B_DQ<23>
TRUE
MEM_B_DQ<24>
TRUE
MEM_B_DQ<25>
TRUE
MEM_B_DQ<26>
TRUE
MEM_B_DQ<27>
TRUE
MEM_B_DQ<28>
TRUE
MEM_B_DQ<29>
TRUE
MEM_B_DQ<31>
TRUE
MEM_B_DQS_N<3>
TRUE
MEM_B_DQS_P<4>
TRUE
MEM_B_DQS_P<5>
TRUE
MEM_B_DQS_P<2>
TRUE
MEM_B_DQS_N<2>
TRUE
MEM_B_DQS_P<3>
TRUE
MEM_A_DQS_P<6>
TRUE
MEM_A_DQS_P<5>
TRUE
MEM_A_DQS_N<4>
TRUE
MEM_A_DQS_P<4>
TRUE
MEM_A_DQS_N<3>
TRUE
MEM_A_DQS_P<1>
TRUE
MEM_A_DQ<56>
TRUE
MEM_A_DQ<47>
TRUE
=MEM_B_DQ<7>
TRUE
MEM_B_DQ<0> MEM_B_DQ<1>
TRUE
MEM_B_DQ<2>
TRUE
MEM_B_DQ<3>
TRUE
=MEM_B_DQ<4>
=MEM_A_DQ<44>
MEM_A_DQ<13>
TRUE
TRUE
MEM_A_DQ<10>
=MEM_A_DQ<23>
=MEM_A_DQ<20>
=MEM_A_DQ<2>
=MEM_A_DQ<18>
=MEM_A_DQ<22>
MEM_A_DQ<5>
TRUE
MEM_A_DQ<3>
TRUE
MEM_A_DQ<4>
TRUE
=MEM_A_DQS_P<7>
=MEM_A_DQS_P<5>
MEM_A_DQS_P<0>
TRUE
TRUE
MEM_A_DQ<60>
MEM_A_DQ<57>
TRUE
MEM_A_DQ<49>
TRUE
MEM_A_DQ<46>
TRUE
MEM_A_DQ<43>
TRUE
MEM_A_DQS_P<2>
TRUE
=MEM_A_DQ<53>
=MEM_A_DQ<48>
=MEM_A_DQ<52>MEM_A_DQ<59>
TRUE
MEM_A_DQ<53>
TRUE
=MEM_A_DQ<9>
=MEM_A_DQ<12>
=MEM_A_DQ<11>
MEM_A_DQ<34>
TRUE
=MEM_A_DQ<10>
MEM_A_DQ<48>
TRUE
MEM_B_DQ<58>
TRUE
MEM_B_DQ<54>
TRUE
MEM_B_DQ<52>
TRUE
MEM_B_DQS_N<5>
TRUE
MEM_B_DQS_N<4>
TRUE
=MEM_B_DQS_P<1>
=MEM_B_DQS_N<7>
=MEM_A_DQ<49>
=MEM_A_DQ<37> =MEM_A_DQ<38>
=MEM_A_DQ<51>
=MEM_A_DQ<55>
=MEM_A_DQ<32>
MEM_B_DQ<56>
TRUE
MEM_B_DQ<55>
TRUE
=MEM_B_DQ<35>
=MEM_A_DQ<24> =MEM_A_DQ<25>
TRUE
MEM_A_DQ<40>
=MEM_A_DQ<40>MEM_A_DQ<22>
TRUE
MEM_A_DQ<9>
TRUE
MEM_A_DQ<7>
TRUE
=MEM_A_DQ<8>
=MEM_A_DQ<61>
=MEM_A_DQ<59>
=MEM_A_DQ<63>
=MEM_A_DQ<41>MEM_A_DQ<23>
TRUE
MEM_A_DQ<24>
TRUE
TRUE
MEM_A_DQ<20>
MEM_A_DQ<18>
TRUE
MEM_A_DQ<15>
TRUE
MEM_A_DQ<1>
TRUE
MEM_A_DQ<2>
TRUE
MEM_B_DQ<59>
TRUE
=MEM_B_DQS_P<2>
=MEM_B_DQ<26>
TRUE
MEM_B_DQ<30>
=MEM_B_DQ<63>
=MEM_B_DQ<23>
SYNC_DATE=12/03/2015SYNC_MASTER=X502-EXP
BOM_COST_GROUP=NO COST ITEMS
Memory Signal Swaps
72 7
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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
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合肥怡飞苹果维修qq:82669515 qq群: 241000
CAMERA
MISC
DISPLAY
FOR DEBUG
FOR DC/DC
XDP
BATTERY
SMC
RIGHT SPEAKERS
MOJO PORT
SYSTEM STATE
LEFT SPEAKERS
BOOTROM
POWER
WIRELESS
USBC/TBT
AUDIO FLEX
TRACKPAD AND KEYBOARD
CAP POWER DISCHARGE
USB2 FIXTURE PORT
72 OF 73
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
NO_TEST=1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
NO_TEST=1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE FUNC_TEST=TRUE
104 OF 500
1.0.0
051-02265
USB_UPC_XB_F_N USB_UPC_XB_F_P
PCIE_SSD_R2D_C_P<0..3>
NO_TEST=1
PCIE_SSD_R2D_N<0..3>
NO_TEST=1
PCIE_SSD_R2D_P<0..3>
NO_TEST=1
PCIE_SSD_R2D_C_N<0..3>
NO_TEST=1
PCIE_SSD_D2R_N<0..3>
NO_TEST=1
PCIE_SSD_D2R_P<0..3>
NO_TEST=1
PCIE_AP_D2R_N PCIE_AP_D2R_P PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P PCIE_AP_R2D_N PCIE_AP_R2D_P
EDP_ML_C_P<0..3>
NO_TEST=1
EDP_ML_C_N<0..3>
NO_TEST=1
EDP_INT_ML_N<0..3>
NO_TEST=1
EDP_INT_ML_P<0..3>
NO_TEST=1
PCIE_AP_D2R_C_N PCIE_AP_D2R_C_P
TP_USB_TESTERN
AUD_CONN_HP_SENSE_R
TP_USB_TESTERP
BANJO_FBVR2_RC
CPUVR_SW1
CPU_VCCGTSENSE_N
GTVR_ISNS2_P
KBD_BLC_GSLAT
KBD_BLC_XBLANK KBD_I2C_SCL
KBD_INT_L
TPAD_SPI_MOSI TPAD_SPI_INT_L
TPAD_SPI_MISO TPAD_SPI_IF_EN TPAD_SPI_CLK
TPAD_SPI_CS_CONN_L
KBD_BLC_GSSOUT
KBD_I2C_SDA
KBD_BLC_GSSIN
TPAD_VIBE_L SMC_LSOC_RST SMC_ONOFF_L SMC_PME_S4_WAKE_L
TP_CAM_TEST_MODE2
ACT_THERM_TRIP_L FAN_LT_PWM
KBD_BLC_GSSCK
PP3V3_G3H
PPVIN_S4_TPAD_FUSE
MEM_A_CS_L<0..1>
NO_TEST=1
MEM_A_DQ<0..63>
NO_TEST=1
MEM_A_ODT<0>
PPVCCOPC_S0G
PPVCCSA_S0G PPVTT_S0
SPI_MLBROM_CS_L
PPVCCIO_S0G
PP3V3_S5G
PP1V_OPC_S0
MEM_B_CLK_P<0..1>
NO_TEST=1
MEM_B_DQ<0..63>
NO_TEST=1
MEM_B_DQS_P<0..7>
NO_TEST=1
AUD_CONN_RING2
XDP_CPU_TMS
ITP_PMODE
SMBUS_SMC_5_G3H_SCL
SMBUS_SMC_5_G3H_SCL
SYS_DETECT_L
PPDCIN_G3H
XDP_PRESENT_CPU
PP1V_S5G
TP_CAM_LV_JTAG_TDI
PP5V_S4
MIPI_CLK_CONN_P
PPDCIN_G3H_CHGR PPVOUT_S0_LCDBKLT
PPBUS_G3H
SSD_BOOT_CONN_L TP_PCH_SLP_A_L
SMC_DEV_SUPPLY_L
SMC_TMS
SMC_TDO
SMC_TCK
XDP_CPU_PWRBTN_L
XDP_DBRESET_L
SPI_MLB_IO<3>
SPI_MLB_IO<2>
SPI_MLB_CS_L
SPIROM_USE_MLB
SPKRCONN_RR_OUT_P
SPKRCONN_FR_OUT_P
SPKRCONN_FR_OUT_N
8409_SPKR_ID1
SPKRCONN_RL_OUT_N SPKRCONN_RL_OUT_P
SPKRCONN_FL_OUT_P
SPKRCONN_FL_OUT_N
8409_SPKR_ID0
PP3V3_G3H
HALL_SENSOR_RIGHT
DMIC1_CLK
AUD_CONN_TIP_SENSE
AUD_CONN_SLEEVE_XW
AUD_CONN_SLEEVE
XDP_CPU_TDO
PM_SLP_S3_L
PM_SLP_S0S3_L
XDP_CPU_TDI
CAM_TEST_MODE TP_CAM_LV_JTAG_TCK
TP_CAM_LV_JTAG_TDO
XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TCK
PM_PWRBTN_L
PM_SLP_SUS_L
PM_SLP_S0_L
SMC_DEBUGPRT_RX_L
PP5V_S0_ALSCAM_F
TCON_BKLT_PWM
MIPI_DATA_CONN_N
I2C_BKLT_SDA
I2C_BKLT_SCL
I2C_ALS_SDA_CONN
I2C_ALS_SCL_CONN
XDP_CPU_TRST_L
ALL_SYS_PWRGD
PP1V8_S0
EDP_PANEL_PWR_EN
SPI_MLB_MISO
MIPI_DATA_CONN_P
XDP_CPU_PREQ_L
TP_UPC_XB_DBG_UART_RX
SMC_DEBUGPRT_TX_L
PP3V3_S0SW_LCD
I2C_CAM_SDA_CONN
PPVOUT_S0_LCDBKLT
PP5V_S0SW_LCD
TP_CAM_TEST_MODE0
XDP_PCH_TDO XDP_PCH_TMS
XDP_PM_RSMRST_L
PM_SLP_S4_L PM_SLP_S5_L
SPKRCONN_RR_OUT_N
SMC_TDI
SPI_MLB_CLK
SPI_MLB_MOSI
JTAG_TBT_TCK JTAG_TBT_TDI JTAG_TBT_X_TMS TBT_X_TEST_EN PP20V_USBC_XA_VBUS PP20V_USBC_XB_VBUS
PP1V8_S5G
PP3V3_S4_WLS PP3V3_S5
PPVCCCPU_S0G PPVCCGT_S0G
PPVCCPCH_S5G
JTAG_WLAN_SEL TP_JTAG_WLAN_TCK JTAG_WLAN_TDI TP_JTAG_WLAN_TDO
FAN_LT_TACH
PP3V3_S4 PP5V_S0 PP5V_S4_TPAD_CONN
PP1V8_S0_PCH_VCCHDA_F
PP1V_SUS_PCH_VCCAPLL_F
VR0V9_IND_TBT_X
PPVCCCPU_S0G_PH2
PD_VSNS_CPU_VCCOPC_TN
CPUVR_SNB2
BANJO_VBSTVR1 BANJO_VBSTVR3 BANJO_VBSTVR4 BANJO_VBSTVR5 CPUVR_BP2 CPUVR_PHASE2 CPUVR_SNB1
AGND_U7320
PMIC_ENH
TBA_PHASE1
VCINP_P5V_U7320
VCINP_P5V_U7310
AGND_U7470
VCINP_P5V_U7310
SAVR_SW
SAVR_BP
P5VS4_DRVH_R
P3V3S5_DRVH_R
P1VOPC_SNS_R
P1VOPC_REFIN_R
P1VOPC_DRVH_R
P1VOPC_BOOT_RC
GTVR_SW2
GTVR_SW1
GTVR_SNB3
GTVR_SNB2
GTVR_SNB1
GTVR_BP1
CPU_VCCST_PWRGD_R
USBC_XB_D2R_N<1..2>
NO_TEST=1
USBC_XB_D2R_P<1..2>
NO_TEST=1
USBC_XB_R2D_C_N<1..2>
NO_TEST=1
USBC_XB_R2D_C_P<1..2>
NO_TEST=1
USBC_XB_R2D_N<1..2>
NO_TEST=1
USBC_XB_R2D_P<1..2>
NO_TEST=1
USBC_XB_USB_BOT_N USBC_XB_USB_BOT_P USBC_XB_USB_TOP_N USBC_XB_USB_TOP_P
USBC_XA_D2R_N<1..2>
NO_TEST=1
USBC_XA_D2R_P<1..2>
NO_TEST=1
USBC_XA_R2D_C_N<1..2>
NO_TEST=1
USBC_XA_R2D_C_P<1..2>
NO_TEST=1
USBC_XA_R2D_N<1..2>
NO_TEST=1
USBC_XA_R2D_P<1..2>
NO_TEST=1
USBC_XA_USB_BOT_N USBC_XA_USB_BOT_P USBC_XA_USB_TOP_N USBC_XA_USB_TOP_P
CPU_PROCHOT_R_L
CPUVR_PHASE1
CPUVR_ISNS2_P
CPUVR_ISNS2_N
CPUVR_BP1
CPUVR_BOOT1
BANJO_VBSTVR5_R
BANJO_VBSTVR4_R
BANJO_VBSTVR3_R
BANJO_VBSTVR1_R
BANJO_SWVR3_SNUB
BANJO_SWVR3R
BANJO_SWVR2_SNUB
BANJO_SWVR2
BANJO_FBVR2_N
AGND_U7310
RF_G_1_MATCH
RF_G_1_DIPLEXER
RF_G_0_MATCH
RF_G_0_DIPLEXER
RF_A_1_MATCH
RF_A_1_DIPLEXER
RF_A_0_MATCH
RF_A_0_DIPLEXER
RF_1_ANT_MATCH_T
RF_1_ANT
RF_0_ANT_MATCH_T
RF_0_ANT
MEM_CAM_DQS_P<0..1>
NO_TEST=1
MEM_CAM_DQS_N<0..1>
NO_TEST=1
MEM_CAM_DQ<0..15>
NO_TEST=1
MEM_CAM_DM<0..1>
NO_TEST=1
MEM_CAM_BA<0..2>
NO_TEST=1
MEM_CAM_A<0..14>
NO_TEST=1
MEM_B_ODT<0>
MEM_B_DQS_N<0..7>
NO_TEST=1
MEM_B_CS_L<0..1>
NO_TEST=1
MEM_B_CLK_N<0..1>
NO_TEST=1
MEM_B_CKE<0..3>
NO_TEST=1
MEM_B_CAB<0..9>
NO_TEST=1
MEM_B_CAA<0..9>
NO_TEST=1
MEM_A_DQS_P<0..7>
NO_TEST=1
MEM_A_DQS_N<0..7>
NO_TEST=1
MEM_A_CLK_P<0..1>
NO_TEST=1
MEM_A_CLK_N<0..1>
NO_TEST=1
MEM_A_CKE<0..3>
NO_TEST=1
MEM_A_CAB<0..9>
NO_TEST=1
MEM_A_CAA<0..9>
NO_TEST=1
MIPI_CLK_CONN_N
LCD_IRQ_L
MAKE_BASE=TRUE
USB_TESTER_N
MAKE_BASE=TRUE
USB_TESTER_P
CPU_CFG<3>
PD_VSNS_CPU_VCCEOPIO_TN
PPVCCCPU_S0G_PH1
PPVCCSA_S0G_R PU_VSNS_CPU_VCCEOPIO_TP PU_VSNS_CPU_VCCOPC_TP
TP_UPC_XA_DBG_UART_TX
TP_UPC_XB_DBG_UART_TX
SAVR_SNB1
TBA_HPWR_EN_L
I2C_TCON_SDA_CONN
I2C_TCON_SCL_CONN
I2C_CAM_SCL_CONN
TP_CAM_TEST_MODE1
EDP_INT_AUX_P
EDP_INT_AUX_N
EDP_BKLT_PWM
DP_INT_HPD
TP_CAM_LV_JTAG_TRSTN
TP_UPC_XA_DBG_UART_RX
PD_TBA_MPM_DET
TP_JTAG_WLAN_TRST
TP_JTAG_WLAN_TMS
XDP_CPU_PRDY_L
TP_CAM_LV_JTAG_TMS
DMIC1_DATA
AUD_CONN_RING2_XW
AUD_CONN_HP_SENSE_L
AUD_CONN_HP_RIGHT
AUD_CONN_HP_LEFT
XDP_PRESENT_L
XDP_CPU_TCK
GND
GND
GND
GND
GND
GND GND
FCT, ICT PROPERTIES
SYNC_DATE=06/15/2015SYNC_MASTER=PAULM
BOM_COST_GROUP=NO COST ITEMS
37 36
37 36
37 36
37 36
37 36
34
34
34
34
34
17 6
34
34
34
34
34
34
34
25 21 7
TP-P6
1
TPA411
TP-P6
1
TPA410
17 6
40 39 28
40 39 28
60 39 14
68 60 39 14
66 60 59 39 26 14
68 60 19
72 66 65
53 52
69 68 63 53
69 68 63 60 58 53 50 43
51 50
51 50
17
51 50
51 50
51 48
51 50
51 50
51 50
51 50
51 48
51
17 6
51
51
51
51
51
51
51
51 48
51 48
38 16
38 16
38 16
38
38 16
38 16
66 5
66 5
38
51 41
17 6
53
53
0201-THICKSTNCL
ESD112-B1-02ELS
CRITICAL
2
1
DA410
0201-THICKSTNCL
ESD112-B1-02ELS
CRITICAL
2
1
DA411
56
55
72 55
55
69 67 64 63 60 51 50 48
53
60
61
12
12
27
30
30
29
29
72 69 68 60
53 52 51 47 42 41 28 19
32 28
55
56
59
59
62
61
55
55
55
55
59
59
55
55
26
28 26
28 26
51
28 26
31 28
41
69 62
69 56
69 63 61
59
69 63 61
69 63 57 45
69 63 55 45
69 64 60
69 68 64 63 61 60 58 44
69 63 44
59
69 67 64 61 59
72 42
72 42
52
69 64 63 60 58 54
47 40 39 28
40 39
40 39
47 40 39 28
47
47
47
47
47
47
47
47 16
14
34
34
34
34
34
34
36
36
36
36
36
36
36
36
36
60 17
17
17
17 6
17 6
60 39
41 39 17
60 14
60 39 14
66
66 5
17 6
66 5
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