Apple Macbook Pro 13 2020 A2251 Schematics
8
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1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
Table of Contents
7
6 5 4 3
HeFei YIFEI MAC FIX
LAST_MODIFICATION=Fri Dec 20 23:04:51 2019
2 1
CK
ECNREV DESCRIPTION OF REVISION
DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE
APPD
DATE
2019-12-2000214438996 ENGINEERING RELEASED
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
12
13
14
15
Table of Contents
BOM Configuration
BOM Configuration
PD Parts
CPU GFX and USB Type-C
CPU MISC/JTAG/CFG/RSVD
CPU LPDDR4x Interface
CPU & PCH Power
CPU & PCH Grounds
CPU Core Decoupling
PCH Decoupling
PCH SPI/SMB/UART/GPIO
PCH Power Management
PCH PCIE/USB/CLKS
myEE 03/01/2019 PMIC LDOs
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
62
63
64
65
66
67
68
69
70
71
72
73
74
7961
80
81
82
84
85
86
87
88
89
90
96
98
120
PMIC GPIOs & Control
TBT 5V REGULATOR
Power FETs
LCD Backlight Driver
eDP Display Connector
S4E<0>
S4E<1>
S4E<2>
S4E<3> X1795_MIHIR
OCARINA PMIC & NAND VCC VR X1795_MIHIR 06/04/2019
SSD Support
Display Mux
Power Aliases - 1
myEE
myEE
myEE
myEE
myEE
myEE
X1795_MIHIR
X1795_MIHIR
X1795_MIHIR
myEE
myEE
myEE
03/01/2019
03/01/2019
03/01/2019
D
03/01/2019
03/01/2019
03/01/2019
05/15/2019
05/15/2019
05/15/2019
05/15/2019
03/01/2019
03/01/2019
03/01/2019
C
15
16
17
18
19
20
21
22
25
26
27
28
18
19
20
23
28
36
37
38
3923
4024
41
42
43
44
CPU/PCH Merged XDP
Chipset Shared Support
LPDDR4x Channels / Aliasing
USB-C
WIFI/BT: Support
WIFI/BT: MODULE 1
WIFI/BT: MODULE 2
SoC GPIO/SEP/USB/DDR/Test
SoC AOP/AON/SMC
SoC ISP/I2C/UART/SPI/I2S
SoC PCIe
SoC Power 1
SoC Power 2
myEE
J214_DAVID
J214_DAVID
myEE
X1795_AMIR
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
03/01/2019
03/20/2019
03/05/2019
03/01/2019
05/15/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
75
76
77
78
121
122
124
125
79 127 03/01/2019
12880
81
82
83
84
85
86
87
88
140
141
142
143
145
149
150
1
Power Aliases - 1
Signal Aliases
ICT FCT 1
ICT FCT 2
Desense Capacitors 1
Desense Capacitors 2
Dev Support 1
Dev Support 2
BOM Variants 1
BOM Variants 2
Alternates BOM Table
NAND BOM Config/Groups
References
LPDDR4x Sub-Channel
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
myEE
J79A_MLB
03/01/2019
03/01/2019
03/01/2019Chipset Support 2
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
01/31/2017
C
B
29
30
31
32
33
34
35
36
37
38
39
40
41
42
45
46
47
48
49
50
51
52
53
54
55
56
57
58
SoC Power 3
SoC Ground
SoC Shared Support
SoC Project Support
T151
Secure Element
T139 Support
I2C Connections 1
I2C Connections 2
Power Sensors: High Side
Power Sensors: Load Side
Power Sensors: Extended
Power Sensors: Extended 2
Thermal Sensors
myEE
myEE
myEE
myEE
X1795_MIHIR
X1795_TAEWAN
myEE
myEE
myEE
Jack
Jack
Jack
Jack
X1412_JACK
03/01/2019
03/01/2019
03/01/2019
03/01/2019
05/30/2019
03/01/2019
03/01/2019
12/15/2019
12/15/2019
12/15/2019
12/15/2019
04/25/2019
89
90
91
92
93
94
95
96
9703/01/2019
100
101
102
1
1
1
1
2
3
1
2
198
1
2
1
LPDDR4x Sub-Channel
LPDDR4x Sub-Channel
LPDDR4x Sub-Channel
USB-C COMM + DEBUG X-T
USB-C COMM + DEBUG W-R05/17/2019
USB-C CONNECTOR
USB-C VRs AND POWER
BURNSIDE BRIDGE
ACE2 CONTROLLER
BURNSIDE BRIDGE
ACE2 CONTROLLER
BURNSIDE BRIDGE
ACE2 CONTROLLER
BURNSIDE BRIDGE
J79A_MLB
J79A_MLB
t290 icl yn
t290 icl yn
J132_RUENJOU
t290 icl yn
t290 icl yn
t290 icl yn
t290 icl yn
t290 icl yn
t290 icl yn
t290 icl yn
t290 icl yn
01/31/2017J79A_MLB
01/31/2017
01/31/2017
02/01/2018
02/01/2018
03/22/2017
02/01/20184
02/01/2018
02/01/2018
02/01/2018
02/01/2018299
02/01/2018
02/01/2018
02/01/2018
B
A
Schematic / PCB #'s
051-05198 SCH1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SCHEM,MLB-WELL,X1795
59
60
62
63
64
65
66
67
68
69
70
71
72
74
75
76
77
78
Power Sensors:Extended 3
Fans/SMC/AMUX Support
Audio Placeholder
Audio Jack Codec
Audio Left Amplifiers
Audio Right Amplifiers
Audio Flex Connectors
Keyboard & Trackpad 1
Keyboard & Trackpad 2
DC-In & Battery Connectors
PBUS Supply & Battery Charger
IMVP9 IC
IMVP9 POWER BLOCK
VR: VCCIN_AUX ISL
EMPTY
Power - 5V 3.3V Supply
VR: VCCPRIM_1P8
PMIC BUCKS AND SWs
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL
CRITICALPCBF,MLB-WELL,X1795820-01949 PCB1
SCH
PCB
Jack
myEE
myEE
J214_MIHIR
myEE
myEE
myEE
X1412_SHAN
myEE
myEE
myEE
J214_JACK
myEE
J214_JACK
myEE
myEE
myEE
myEE
12/15/2019
03/01/2019
03/01/2019
03/05/2019
03/01/2019
03/01/2019
03/01/2019
05/17/2019
03/01/2019
03/01/2019
03/01/2019
03/26/2019
03/01/2019
03/26/2019
03/01/2019
03/01/2019
03/01/2019
03/01/2019
103
104
105
106
107
108
109
2
1
1
1
1
1
1
ACE2 CONTROLLER
USB-C CONNECTOR A
USB-C CONNECTOR A
Power FETs TBT S0
Power FETs TBT S0
TBT 5V REGULATOR
TBT 5V REGULATOR
t290 icl yn
J132_RUENJOU
J132_RUENJOU
CPU_CARD_ICL_Y
CPU_CARD_ICL_Y
J132_JIN
J132_JIN
02/01/2018
03/22/2017
03/22/2017
06/08/2018
06/08/2018
08/24/2017
08/24/2017
Table of Contents
DRAWING TITLE
SCHEM,MLB-WELL,X1795
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
1 OF 150
SHEET
1 OF 109
A
SIZEDRAWING NUMBER
D
8
3
124567
Module Parts
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3 245
1
D
CPU
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
998-17651 CRITICAL CPU:SOCKET1 U0500
337S00709 U0500 CRITICAL1
337S00710
1
1337S00711
337S00778 1 U0500 CRITICAL CPU:BTR
337S00804 PRQ:BTRCRITICALU05001
337S00803
1 U0500 CRITICAL
CPU,ICLUN,QS3R,ES2,B4,1.4,0.7,BGA1344
CPU,ICLUN,QS3P,ES2,B4,1.4,0.7,BGA1344
CPU,ICLUN,QS3N,ES2,B4,1.8,0.9,BGA1344
CPU,ICLUN,QS3Q,ES2,B4,1.8,0.9,BGA1344
CPU,ICLUN,QS3M,ES2,B4,1.8,0.9,BGA1344
CPU,ICLUN,QSHZ,QS,D2,2.0,1.05,BGA1344
CPU,ICLUN,QSHY,QS,D2,2.3,1.1,BGA1344
CPU,ICLUN,QSHZ,QS,D2,2.0,1.05,BGA1344
CPU,ICLUN,QSHZ,QS,D2,2.3,1.1,BGA1344
SOCKET,CPU,CFL-U
CPU:QS3R
CPU:QS3PCRITICALU0500
U0500
CRITICAL
CPU:QS3N
U05001337S00712 CRITICAL CPU:QS3Q
CRITICAL337S00713 1 CPU:QS3MU0500
U0500337S00777 CRITICAL1 CPU:BST
PRQ:BST
P0a and P1a, the same D2
MM#:999D89
MM#:999D87
MM#:999D86
MM#:999D88
MM#:999D85
P1a D2
P1a D2
MM#:999H22
MM#:999H21
SOC
POP,SOC,GIBRALTAR+1GB 20NM,M,B0,CSP1406
339S00372 U3900
1 CRITICAL SOC:B0_2G
POP,SOC,GIBRALTAR+2GB 20NM,M,B0,CSP1406
U3900 SOC:B0_1GCRITICAL1339S00370
SOC Alternate Parts
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
TABLE_ALT_ITEM
Hynix 1GB SCK
TABLE_ALT_ITEM
Micron 1GB ATK
TABLE_ALT_ITEM
Hynix 1GB ATK
TABLE_ALT_ITEM
Hynix 2GB SCK
TABLE_ALT_ITEM
Micron 2GB ATK
TABLE_ALT_ITEM
Hynix 2GB ATK
339S00375
339S00378
PART NUMBER
339S00370339S00371 ALL
339S00370 ALL
339S00370 ALL339S00376
339S00372
SOC:B0_1G
SOC:B0_1G
SOC:B0_1G
SOC:B0_2G
SOC:B0_2G
SOC:B0_2G
ALL339S00373 339S00372
ALL339S00372339S00377
ALL
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
D
C
B
A
BURNSIDE BRIDGE
338S00561 BBR_TR:QSA1
4
ACE2
353S02158
353S01960 in P0a
4
PMU
1
CHARGER IC
353S01525
AMR
677-19902
OCARINA
338S00410
WIRELESS(Harpoon)
339S00609
1 CRITICAL
HARPOON Alternate Parts
PART NUMBER
339S00609339S00610
IC,TBT,BURNSIDE BRIDGE,PRQ,A1,BGA105
IC,CD3217,ACE2,B2,USB PWR SW W/HV,BGA123
IC,PMU-A,D2449A0C,CALPE,CSP324,&X28X7.32
IC,ISL9240HIB0Z,PMU,SUONA,WCSP40,2.1X3.3
677-10581 in P0a
SUBASSY (T&R) PCBA,AMR INTERPOSER,X1795
IC,PMU,OCARINA,D2499A0,OPT-AG,WLCSP56
IC,MODULE,HARPOON,ES7.9,LGA385,Murata
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
U3730
USI
U2800_X,U2800_R,U2800_W,U2800_T
U3100_X,U3100_R,U3100_W,U3100_T
U7800338S00267 CRITICAL
U7000
J4800, J4801
U9000
U3730
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL1
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL2
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL1
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
P1B:PRQ:BTR/BST
EVT:PRQ:BTR/BST
ACE2:B2
Programmables
BBR ROMs
IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8
335S00133 CRITICAL1
341S01381
341S01382
341S01633
341S01634
1
1
BBR ROM Alternate Parts
PART NUMBER
335S00133335S00232
BT ROM
335S00256
341S01342
341S01644
1
BT ROM Alternate Parts
PART NUMBER
335S00248
335S00255
335S00256
WIFI ROM
335S00214 1 CRITICAL
341S01645
WIFI ROM Alternate Parts
PART NUMBER
335S00214335S00216
1 U3710
IC,SPI SERIAL FLASH,8MBITS,3.0V,USON8
IC,TBT-XT,(V18.3) NEW-PROTO-0,X1412
IC,TBT-WR (V18.3) NEW-PROTO-0,X1412
ROM,TBT-XT (Vxxxx) DFR-B,X1795
ROM,TBT-WR (Vxxxx) DFR-B,X1795
BT_ROM:BLANK
IC,SPI SERIAL FLASH,2MBIT,1.8V,DFN8
BT_ROM:BLANK
BT_ROM:BLANK
IC,EEPROM,SER,UWIRE,16K,1.8V,DFN8
WIFI_ROM:BLANK
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
U3060,UB260
IC,BT SFLASH ROM (V22_shared)
IC,BT SFLASH ROM (V39) X1795
U3750
U3750335S00256
IC,WIFI ROM (V01) WW1,X1795
U3710
Macronix
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
Macronix
Adesto
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
Rohm
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
U3060
UB260
U3060
UB260
U3060
UB260
CRITICAL BBR_XT_ROM:BLANK1335S00133
CRITICAL BBR_XT_ROM:P01
CRITICAL1
CRITICAL
CRITICAL
BBR_WR_ROM:BLANK
BBR_WR_ROM:P0
BBR_XT_ROM:PVT
BBR_WR_ROM:PVT
UB260U3060
TABLE_ALT_HEAD
P1 341S01411 341S01412
P0a 341S01466 341S01467
TABLE_ALT_ITEM
P1a 341S01511 341S01512
P1b 341S01511 341S01512
EVT 341S01511 341S01512
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
U37501
U3750
CRITICAL
CRITICAL
U3750 CRITICAL
BT_ROM:BLANK
BT_ROM:PVT
P1 BT ROM:341S01417
TABLE_ALT_HEAD
P0a BT ROM:341S01434, same as in J152
P1a BT ROM:341S01501, same as in J152
TABLE_ALT_ITEM
P1b BT ROM:341S01501, same as in P1a
EVT BT ROM:341S01501, same as in P1a
TABLE_ALT_ITEM
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
U3710
CRITICAL
WIFI_ROM:BLANK
WIFI_ROM:PVT
P1a WIFI ROM 341S00725
P1b WIFI ROM 341S00725
TABLE_ALT_HEAD
TABLE_ALT_ITEM
EVT WIFI ROM 341S00725
C
Strategic Silicon
TABLE_STRATEGIC_HEAD
PART# COMMENT
337S00456 08
333S00125
333S00126
333S00167 08
left
right
335S00322 10
335S00324 09
335S00325 09
335S00329
335S00330
335S00332
338S00285 08
353S01442
338S00408
353S01188
353S01525
BT_ROM:P01
353S00928 06
338S00253
353S4415
353S01320
338S1163
SYNC_MASTER=myEE SYNC_DATE=03/01/2019
PAGE TITLE
STRATEGIC VALUE
01333S00069
01333S00070
01
01
08333S00166
09339S00370
09339S00372
08338S00267
10335S00321
09335S00327
09
09
09
05
08
09
06
07353S00526
02353S01077
08353S01629
09
01
08
01
CPU
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
pSOC
pSOC
CALPE
NAND
NAND
NAND
NAND
NAND
NAND
NAND
NAND
OCARINA
ACE
TITAN RIDGE
DEBUG MUX2
SUONA
IMVP8
TPS62180
ISL95870HRUZ
TAS5770L
SECURE ELEMENT
BACKLIGHT CONTROLLER
MIPI SWITCH
ACCELEROMETER
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
B
A
BOM Configuration
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
2 OF 150
SHEET
2 OF 109
8
67
35 4
2
1
678
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BOM VariantsBOM Groups
D
BOM GROUP BOM OPTIONS
X1795_COMMON
X1795_COMMON1
X1795_COMMON2
X1795_COMMON3
X1795_PROGPARTS
X1795_DEVEL:ENG
X1795_DEVEL:DVT
X1795_DEVEL:PVT
USBC_MLB_TBT_OPTS
USBC_MLB_TBT
X1795_USBC
SCH,PCB,ALTERNATE,COMMON,X1795_COMMON1,X1795_COMMON2,X1795_COMMON3,X1795_PROGPARTS
X1795_USBC,SYSDET:FET,BOARD_ID,BOARD_REV:110
EDP_ENABLE,XDP:YES,SKIP_5V3V3:AUDIBLE,RF_TUNING
LOADRC:YES,SE:PROD_2019
BBR_XT_ROM:PVT,BBR_WR_ROM:PVT,WIFI_ROM:PVT,BT_ROM:PVT
ALTERNATE,ESPI_DBG,DBGLED,USBC_DBG,XDP_CONN:YES,WIFI_DBG,SSD_DBG,FAN_DBG,DEBUG_BUTTON,LOADISNS,SENSOR:DEV,BOOTCFG0
ALTERNATE,USBC_DBG,XDP_CONN:YES,WIFI_DBG
ALTERNATE
BBR_FORCE_PWR:ACE,BBR_GP6:BBR_S0
BBR_X_PWR:SWSW_VOUTLV,BBR_T_PWR:SWSW_VOUTLV,BBR_PERST:PLTRST,BBR_RST:SPLIT
BBR_TR:QSA1,ACE2:B2,USBC_MLB_TBT,USBC_MLB_TBT_OPTS
CMPT:THRSSD
CMPT:512GSSD
POLY:27UF
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM NUMBER BOM NAME BOM OPTIONS
685-00325 COMMON BOM,MLB-WELL,X1795 X1795_COMMON
985-01186 X1795_DEVEL:ENG
939-08546
939-08545
DEV BOM,MLB-WELL,X1795
PCBA,MLB-WELL,NO CPU,X1795
PCBA,MLB-WELL,CPU SOCKET,X1795
BASE_BOM,DEVEL_BOM,ALTERNATE
BASE_BOM,DEVEL_BOM,ALTERNATE,CPU:SOCKET
P0: DC1 CPU SOCKET, DC2 NO CPU
Variable BOM Groups
Development/Base BOMs
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
685-00325 BASE1 CRITICAL BASE_BOM
985-01186
1 DEVEL CRITICAL DEVEL_BOMPOLY:33UF
COMMON BOM,MLB-WELL,X1795
DEV BOM,MLB-WELL,X1795
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
C
board_rev TABLE
P0a NO DFR: 000
P0a with DFR: 001
P1a NO DFR: 010
P1a with DFR: 011
P1b with DFR: 100
evt-01: 101
evt-02: 101
DFR: 110
APN POLY CAPS
128S00093
128S00093
128S00106
128S00106
41
15
41
15
TANT,PLOY,NEC 33uF, 16V
TANT,PLOY,NEC 33uF, 16V
TANT,PLOY,NEC 27uF, 18V
TANT,PLOY,NEC 27uF, 18V
C6480,C6481,C6482,C6483,C6484,C6485,C6580,C6581,C6582,C6583,C6584,C6585,C6907,C6908,C7210,C7211,C7212,C7213,C7220,C7221,C7222,C7223,C7230,C7231,C7232,C7233,C7240,C7241,C7242,C7402,C7403,C7404,C7405,C7406,C7407,C7600,C7660,C7661,C7662,C7675,C7702
C8100,C8109,C8111,C9079,C3502_VWR,C3503_VWR,C3504_VWR,C3502_VXT,C3503_VXT,C3504_VXT,C8172,C8173,C8174,C8175,C8176
C6480,C6481,C6482,C6483,C6484,C6485,C6580,C6581,C6582,C6583,C6584,C6585,C6907,C6908,C7210,C7211,C7212,C7213,C7220,C7221,C7222,C7223,C7230,C7231,C7232,C7233,C7240,C7241,C7242,C7402,C7403,C7404,C7405,C7406,C7407,C7600,C7660,C7661,C7662,C7675,C7702
C8100,C8109,C8111,C9079,C3502_VWR,C3503_VWR,C3504_VWR,C3502_VXT,C3503_VXT,C3504_VXT,C8172,C8173,C8174,C8175,C8176
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL
CRITICAL
CRITICAL
CRITICAL
POLY:33UF
C
POLY:33UF
POLY:27UF
POLY:27UF
B
DRAM
333S00180
333S00205 4
333S00218
333S00181
333S00206 4
333S00219
333S00204
333S00207
333S00220
4
4
4
4
4
4
4
IC,SDRAM,LPDDR4x-4266,16GBIT,19NM,HYN,BGA200
IC,SDRAM,LPDDR4x-4266,16GBIT,18NM,MIC,BGA200
IC,SDRAM,LPDDR4x-4266,16GBIT,19NM,SS,BGA200
IC,SDRAM,LPDDR4x-4266,32GBIT,21NM,HYN,BGA200
IC,SDRAM,LPDDR4x-4266,32GBIT,18NM,MIC,BGA200
IC,SDRAM,LPDDR4x-4266,32GBIT,19NM,SS,BGA200
IC,SDRAM,LPDDR4x-3733,64GBIT,19NM,HYN,H,BGA200
IC,SDRAM,LPDDR4x-4266,64GBIT,19NM,MIC,BGA200
IC,SDRAM,LPDDR4x-4266,64GBIT,16NM,MIC,BGA200
U2300_1,U2300_2,U2300_3,U2300_4
U2300_1,U2300_2,U2300_3,U2300_4
U2300_1,U2300_2,U2300_3,U2300_4
U2300_1,U2300_2,U2300_3,U2300_4
U2300_1,U2300_2,U2300_3,U2300_4
U2300_1,U2300_2,U2300_3,U2300_4
U2300_1,U2300_2,U2300_3,U2300_4
U2300_1,U2300_2,U2300_3,U2300_4
U2300_1,U2300_2,U2300_3,U2300_4
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
DRAM:HY_8G
DRAM:MI_8G
DRAM:SS_8G
DRAM:HY_16G
DRAM:MI_16G
DRAM:SS_16G
DRAM:HY_32G
DRAM:MI_32G
DRAM:SS_32G
Main DRAM SPD Straps
BOM GROUP BOM OPTIONS
DRAMCFG:HY_8G
DRAMCFG:MI_8G
DRAMCFG:SS_8G
DRAMCFG:HY_16G
DRAMCFG:MI_16G
DRAMCFG:SS_16G
DRAMCFG:HY_32G
DRAMCFG:MI_32G
DRAMCFG:SS_32G
DRAM:HY_8G,RAMCFG3_L,RAMCFG2_L,RAMCFG1_L,RAMCFG0_L
DRAM:MI_8G,RAMCFG3_L,RAMCFG2_L,RAMCFG1_L
DRAM:SS_8G,RAMCFG3_L,RAMCFG2_L,RAMCFG0_L
DRAM:HY_16G,RAMCFG3_L,RAMCFG1_L,RAMCFG0_L
DRAM:MI_16G,RAMCFG3_L,RAMCFG1_L
DRAM:SS_16G,RAMCFG3_L,RAMCFG0_L
DRAM:HY_32G,RAMCFG2_L,RAMCFG1_L,RAMCFG0_L
DRAM:MI_32G,RAMCFG2_L,RAMCFG1_L
DRAM:SS_32G,RAMCFG2_L,RAMCFG0_L
B
TABLE_BOMGROUP_HEAD
NOTE
TABLE_BOMGROUP_ITEM
0x10
TABLE_BOMGROUP_ITEM
0x11
TABLE_BOMGROUP_ITEM
0x12
TABLE_BOMGROUP_ITEM
0x14
TABLE_BOMGROUP_ITEM
0x15
TABLE_BOMGROUP_ITEM
0x16
TABLE_BOMGROUP_ITEM
0x18
TABLE_BOMGROUP_ITEM
0x19
TABLE_BOMGROUP_ITEM
0x1A
A
8
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
PAGE TITLE
A
BOM Configuration
CPU DRAM CFG Chart
CAPACITY
8
16
32 SAMSUNG
RSVD
0
0
1
1
67
CFG 2CFG 3
0
1
0
1
35 4
VENDOR
HYNIX
MICRON
CFG 1
0
0
1
1RSVD
CFG 0
0
1
0
1
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
3 OF 150
SHEET
3 OF 109
1
SIZE
D
678
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QQ微信：181806465
3 245
1
BOARD MECHANICALS
D
Shield Cans - BOTTOM SIDE
BURNSIDE BRIDGE - LEFT (U2800_T) - 806-12859
1
SH0418
SM
OMIT
FENCE-TITAN-RIDGE-X940
BURNSIDE BRIDGE - RIGHT (U2800_W) - 806-12859
1
SH0420
SM
OMIT
FENCE-TITAN-RIDGE-X940
LPDDR4 (U2300_1 ~ U2300_4) - 806-20740
Shield Cans - TOP SIDE
SOC (U3900) - 806-12855
1
SH0412
SM
FENCE-MLB-BTM-H9M-X940
DIPLEXERS - 806-12854
1
SH0411
SM
SHLD-MLB-DIPLEXERS-X940
CPU SLED (U0500) - 806-14839
POGO PINS
LIO and RIO -2X (870-09666)
SH0471
POGO-2.0OD-2.95H-SM
1
AROUND THE FAN AND CENTER - 8X (870-09667)
POGO-2.0OD-2.95H-SM
SH0463
POGO-2.3OD-4.0H-SM
SM-1
1
POGO-2.3OD-4.0H-SM POGO-2.3OD-4.0H-SM POGO-2.3OD-4.0H-SM
SH0472
SM-1SM-1
1
SH0464
SM-1 SM-1 SM-1
1
SH0465
1
SH0466
1
Cowling Bosses - BOTTOM SIDE
remove DFR TOUCH CONN (J4402) - 860-00414
USB-C CONN - LIO (J3300) - 860-00392
SH0445
3.4OD1.75ID-1.12H-SM3.4OD1.75ID-1.12H-SM
1
DFR DISPLAY CONN (J4401) - 860-00412
SH0446
1
D
C
1
SH0415
SM
OMIT
SHLD-FENCE-X379
removed NAND - TOP SOUTH (U8600)
removed NAND - BOTTOM SOUTH (U8700)
removed NAND - TOP NORTH (U8800)
removed NAND - BOTTOM NORTH (U8900)
806-24474
806-24476
1 SH0415 CRITICAL
J214 LPDDR shielding can
SHIELD FENCE,BURNSIDE BRIDGE,X1413
1
SH0423
SM
SLED-METAL-MATT-NICKEL-X940
CPU SLED (U0500) - 806-14839
1
SH0424
SM
SLED-METAL-MATT-NICKEL-X940
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
SH0418,SH04202 CRITICAL
SH0467
POGO-2.3OD-4.0H-SM POGO-2.3OD-4.0H-SM
SM-1
1
SH0468
1
SH0469
POGO-2.3OD-4.0H-SM
SM-1
1
SH0470
POGO-2.3OD-4.0H-SM
1
PLATED HOLES
Detail D Detail JDetail E
2X (998-19890) 1X (998-19892)
1
3.0R2.25-NSP
1
3.0R2.25-NSP
SH0480
OMIT_TABLE
SH0481
2X (998-19891)
OMIT_TABLEOMIT_TABLE
1
SL-1.86X3.27-2.61X4.02-NSP
TH-NSP
OMIT_TABLE
1
SL-1.86X3.27-2.61X4.02-NSP
TH-NSP
SH0482
SH0483
OMIT_TABLE
1
2.61R1.86-NSP
SH0484
REMOVE SH0426/SH0427
IPD CONN (J4501) - 860-00412
SM-1SM-1
SH0428
3.4OD1.75ID-1.7H-SM
1
3.4OD1.75ID-1.7H-SM
SH0429
1
DFR (J5110) - 860-01484
C
SH0430
3.4OD1.75ID-1.5H-SM
1
USB-C CONN - RIO (JB500) - 860-00392
SH0447
3.4OD1.75ID-1.12H-SM
1
3.4OD1.75ID-1.12H-SM
SH0448
1
B
Shield CAN Alignment Slots 14X - 998-04440 (1.2mm X 0.4mm)
SH0449
TH-NSP
1
SL-1.2X0.4-1.5X0.7
SH0455
TH-NSP
1
SL-1.2X0.4-1.5X0.7
SH0450
TH-NSP
1
SL-1.2X0.4-1.5X0.7
SH0461
TH-NSP
1
SL-1.2X0.4-1.5X0.7
SH0451
TH-NSP
1
SL-1.2X0.4-1.5X0.7
SH0457
TH-NSP
1
SL-1.2X0.4-1.5X0.7
SH0452
TH-NSP
1
SL-1.2X0.4-1.5X0.7
SH0458
TH-NSP
1
SL-1.2X0.4-1.5X0.7
TOP Rubber Mount Standoffs - 13X - (860-00430)
REMOVE SH0414
Thermal Stage Mounting Holes
Plated Through Hole - 3.15mm - APN 998-0845
SH0490
3P9R3P15
1
Plated Through Hole - 3.6mm - APN 998-03850
SH0491
1
SH0492
1
SH0493
4.0R3.6-NSP4.0R3.6-NSP4.0R3.6-NSP
1
AUDIO JACK CONN (J6600) - 860-00829
SH0432
2.7X1.8R-1.4ID-1.64H-SM
1
MESA CONN (J4900) - 860-00829
SH0433
2.7X1.8R-1.4ID-1.64H-SM
1
Bottom Thermal Stage Boss - 860-01604
NOSTUFF
SH0434
4.0OD1.6ID-0.92H-TH
1
B
A
SH0400
1
2
SH0404
2.8OD1.2ID-1.435H-SM
1
2
SH0408
1
2
SH0401
1
2
SH0405
1
2
SH0409
1
2
Bottom Rubber Mount Standoffs
SH0402
1
2
SH0406
1
2
SH0403
- 1X - (860-00476)
2.8OD1.2ID-1.435H-SM2.8OD1.2ID-1.435H-SM2.8OD1.2ID-1.435H-SM2.8OD1.2ID-1.435H-SM
1
SH0437
2.8OD1.2ID-3.25H-SM
2
1
2
SH0407
2.8OD1.2ID-1.435H-SM2.8OD1.2ID-1.435H-SM2.8OD1.2ID-1.435H-SM
1
2
Cowling Bosses - TOP SIDE
eDP CONN (J8500) - 860-00415
SH0421
3.4OD1.75ID-0.844H-SM3.4OD1.75ID-0.844H-SM
1
PAGE TITLE
SH0422
1
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
A
PD Parts
DRAWING NUMBER
051-05198
SH0410
2.8OD1.2ID-1.435H-SM2.8OD1.2ID-1.435H-SM2.8OD1.2ID-1.435H-SM
1
2
2.8OD1.2ID-1.435H-SM
SH0436
1
2
BOM_COST_GROUP=MECHANICALS
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Apple Inc.
REVISION
6.0.0
BRANCH
evt-3
PAGE
4 OF 150
SHEET
4 OF 109
SIZE
D
8
67
35 4
2
1
D
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QQ微信：181806465
678
66B8
66B8
66B8
66B8
66B8
66B8
66B8
66B8
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
EDP_INT_ML_P<0>
EDP_INT_ML_N<0>
EDP_INT_ML_P<1>
EDP_INT_ML_N<1>
EDP_INT_ML_P<2>
EDP_INT_ML_N<2>
EDP_INT_ML_P<3>
EDP_INT_ML_N<3>
NC
NC
NC
NC
NC
NC
NC
NC
AH5
AH4
AJ5
AJ4
AE4
AE5
AC4
AC5
AV4
AV5
AT4
AT5
AN5
AN4
AL5
AL4
DDIA_TXP[0]
DDIA_TXN[0]
DDIA_TXP[1]
DDIA_TXN[1]
DDIA_TXP[2]
DDIA_TXN[2]
DDIA_TXP[3]
DDIA_TXN[3]
DDIB_TXP[0]
DDIB_TXN[0]
DDIB_TXP[1]
DDIB_TXN[1]
DDIB_TXP[2]
DDIB_TXN[2]
DDIB_TXP[3]
DDIB_TXN[3]
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 1 OF 19
GPP_A16/DDSP_HPDB/TIME_SYNC1
GPP_A15/DDSP_HPDC/TIME_SYNC0
DDI
DISPLAY SIDEBANDS
DDIA_AUX_P
DDIA_AUX_N
DDIB_AUX_P
DDIB_AUX_N
GPP_A17/DDSP_HPDA
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
DISP_UTILS
DISP_RCOMP
AF4
AF5
AP4
AP5
DJ39
DC40
DH39
DC38
DC39
DC37
H6
AB2
EDP_INT_AUX_P
EDP_INT_AUX_N
NC
NC
CPU_DP_INT_HPD
PCH_WLAN_AUDIO_SYNC
PCH_BT_AUDIO_SYNC
EDP_BKLT_EN
BKLT_PWM_MLB2TCON
EDP_PANEL_PWR_EN
NC
DISP_RCOMP
1
R0531
150
1%
1/20W
MF
201
2
3 245
66B8
BI
66B8
BI
5A6 32C3
IN
5A6 17B1
IN
5A6 17B1
IN
5A6 65C7
OUT
17D3
OUT
66C8
OUT
1
D
C
B
PP3V3_S5
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
19D5
OUT
19D5
OUT
19D5
BI
19D5
BI
19D5
OUT
19D5
OUT
19D5
BI
19D5
BI
19D5
OUT
19C5
OUT
19C5
BI
19C5
BI
19C5
OUT
19C5
OUT
19C5
BI
19C5
BI
19C5
OUT
19C5
OUT
19C5
BI
19C5
BI
19C5
OUT
19C5
OUT
19C5
BI
19C5
BI
19B5
OUT
19B5
OUT
19B5
BI
19B5
BI
19B5
74B2 14A7 13A7 12B7
19B5
19B5
19B5
OUT
OUT
BI
BI
USBC_HSX_R2D_C_P<1>
USBC_HSX_R2D_C_N<1>
USBC_HSX_D2R_C_P<1>
USBC_HSX_D2R_C_N<1>
USBC_HSX_R2D_C_P<2>
USBC_HSX_R2D_C_N<2>
USBC_HSX_D2R_C_P<2>
USBC_HSX_D2R_C_N<2>
USBC_HST_R2D_C_P<1>
USBC_HST_R2D_C_N<1>
USBC_HST_D2R_C_P<1>
USBC_HST_D2R_C_N<1>
USBC_HST_R2D_C_P<2>
USBC_HST_R2D_C_N<2>
USBC_HST_D2R_C_P<2>
USBC_HST_D2R_C_N<2>
USBC_HSW_R2D_C_P<1>
USBC_HSW_R2D_C_N<1>
USBC_HSW_D2R_C_P<1>
USBC_HSW_R2D_C_P<2>
USBC_HSW_R2D_C_N<2>
USBC_HSW_D2R_C_P<2>
USBC_HSW_D2R_C_N<2>
USBC_HSR_R2D_C_P<1>
USBC_HSR_R2D_C_N<1>
USBC_HSR_D2R_C_P<1>
USBC_HSR_D2R_C_N<1>
USBC_HSR_R2D_C_P<2>
USBC_HSR_R2D_C_N<2>
USBC_HSR_D2R_C_P<2>
USBC_HSR_D2R_C_N<2>
BL5
BL6
BH1
BH2
BG5
BG6
BF2
BF1
BD6
BD5
BC1
BC2
BA5
BA6
BB2
BB1
BP5
BP6
BR2
BR1
BU6
BU5
BT1
BT2
BY5
BY6
BW2
BW1
CD6
CD5
CA1
CA2
TCP0_TX_P0
TCP0_TX_N0
TCP0_TXRX_P0
TCP0_TXRX_N0
TCP0_TX_P1
TCP0_TX_N1
TCP0_TXRX_P1
TCP0_TXRX_N1
TCP1_TX_P0
TCP1_TX_N0
TCP1_TXRX_P0
TCP1_TXRX_N0
TCP1_TX_P1
TCP1_TX_N1
TCP1_TXRX_P1
TCP1_TXRX_N1
TCP2_TX_P0
TCP2_TX_N0
TCP2_TXRX_P0
TCP2_TXRX_N0
TCP2_TX_P1
TCP2_TX_N1
TCP2_TXRX_P1
TCP2_TXRX_N1
TCP3_TX_P0
TCP3_TX_N0
TCP3_TXRX_P0
TCP3_TXRX_N0
TCP3_TX_P1
TCP3_TX_N1
TCP3_TXRX_P1
TCP3_TXRX_N1
SYM 8 OF 19
GPP_E13/DDPA_CTRLCLK/TBT_LSX0_TXD
GPP_E14/DDPA_CTRLDATA/TBT_LSX0_RXD
GPP_E15/DPPB_CTRLCLK/TBT_LSX1_TXD
GPP_E16/DPPB_CTRLDATA/TBT_LSX1_RXD
GPP_E17/DPPC_CTRLCLK/TBT_LSX2_TXD
GPP_E18/DPPC_CTRLDATA/TBT_LSX2_RXD
GPP_E11/TBT_LSX3_TXD
GPP_E12/TBT_LSX3_RXD
TCP0_AUX_P
TCP0_AUX_N
TCP1_AUX_P
TCP1_AUX_N
TCP2_AUX_P
TCP2_AUX_N
TCP3_AUX_P
TCP3_AUX_N
TC_RCOMP_P
TC_RCOMP_N
BJ6
BJ5
BB6
BB5
BR5
BR6
CB5
CB6
DE35
DC35
DH34
DJ34
DG35
DH35
DE25
DF25
BL1
BM1
USBC_HSX_AUXCH_C_P
USBC_HSX_AUXCH_C_N
USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N
USBC_HSW_AUXCH_C_P
USBC_HSW_AUXCH_C_N
USBC_HSR_AUXCH_C_P
USBC_HSR_AUXCH_C_N
LSX_HSX_R2P
LSX_HSX_P2R
LSX_HST_R2P
LSX_HST_P2R
LSX_HSW_R2P
LSX_HSW_P2R
LSX_HSR_R2P
LSX_HSR_P2R
TC_RCOMP_P
TC_RCOMP_NUSBC_HSW_D2R_C_N<1>
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
R0530
150
1/20W
1%
MF
201
21
19D5 78C4
19D5 78C4
19C5 78C4
19C5 78C4
19C5 78C4
19C5 78C4
19B5 78C4
19B5 78C4
5B6 15B6 19D5
15B6 19D5
5B6 15B6 19C5
15B6 19C5
5A6 15A6 19C5
19C5
5A6 15B6 19B5
15B6 19B5
PLACE_NEAR=U0500.BL1:12.7MM
C
B
A
R0561
R0562
R0563
R0564
10K
10K
10K
10K
21
MF1/20W
21
MF1/20W
21
MF1/20W
21
MF1/20W
LSX_HS_P2R PD in USBC block
R0557
R0558
R0559
R0560
100K
100K
100K
100K
21
MF1/20W
21
MF1/20W
21
MF1/20W
21
MF1/20W
2015%
LSX_HSX_R2P
LSX_HST_R2P
2015%
LSX_HSW_R2P
2015%
LSX_HSR_R2P
2015%
CPU_DP_INT_HPD
2015%
PCH_WLAN_AUDIO_SYNC
2015%
EDP_BKLT_EN
2015%
PCH_BT_AUDIO_SYNC
2015%
5C3 15B6 19D5
5C3 15B6 19C5
5B3 15A6 19C5
5B3 15B6 19B5
5D3 32C3
5D3 17B1
5D3 65C7
5D3 17B1
15A8
FIVR_VLOAD_GTM
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AH10
AJ10
AP10
AW10
BA10
BF34
BH34
BH38
BH9
BN34
BP10
BR10
C3
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 19 OF 19
SPARE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CJ40
CL38
CW35
DB33
DB36
DF1
DF3
DH3
DJ3
F1
H1
M36
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NCNC
DESIGN: X502/DEV_MLB_U
LAST CHANGE: Tue Apr 28 20:32:21 2015
SYNC_MASTER=myEE SYNC_DATE=03/01/2019
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
IV ALL RIGHTS RESERVED
CPU GFX and USB Type-C
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
BRANCH
evt-3
PAGE
5 OF 150
SHEET
5 OF 109
A
SIZE
D
8
67
35 4
2
1
678
www.haojiyoubbs.com
QQ微信：181806465
3 245
1
D
77D2 75B4 64A2 54B3 31B6 16C7 13D8 10B3 8C7 8A5
PP1V05_VCCSTG_OUT_LGC
8B7 15D2
31A3
BI
CPU_PROCHOT_L
PP1V05_S0_CPU_VCCST
R0610
1K
5%
1/20W
MF
201
PLACE_NEAR=U0500.E2:254MM
1
R0612
1K
5%
1/20W
MF
201
2
J2
CK6
J1
E2
C4
N2
N1
P1
P2
H2
E4
CF41
CN1
OMIT_TABLE
CATERR*
PECI
PROCHOT*
THRMTRIP*
SKTOCC*
BPM[0]*
BPM[1]*
BPM[2]*
BPM[3]*
PROC_PRDY*
PROC_PREQ*
PROC_POPIRCOMP
PCH_OPIRCOMP
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 4 OF 19
JTAG
CPU MISC
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST*
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
PCH_TRST*
PCH_JTAGX
AC8
Y6
V6
T6
AA2
AA8
Y5
V5
T5
AA1
W1
XDP_CPU_TCK
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TRST_L
XDP_PCH_TCK
XDP_PCH_TDI
XDP_PCH_TDO
XDP_PCH_TMS
XDP_PCH_TRST_L
PCH_JTAGX
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
D
15C8 15D2
15C1
15C1 15D2
15C1
15C1
15C6 15D2
15B1 15D2
15B1 15D2
15B1 15D2
15B1
15C8
49.9
1%
1/20W
MF
201
1
2
R0613
1
62B6 77C2
2
R0611
510
2 1
5%
1/20W
MF
201
31C2
31B6 62D6 77C2 80A6
6A7 15D6 77D3
6A7 15D6
6A7
6A7
15D6
15D6
OUT
BI
OUT
BI
BI
BI
BI
OUT
IN
CPU_CATERR_L
CPU_PECI
CPU_PROCHOT_R_L
PM_THRMTRIP_L
NC_SKTOCC_L
CPU_BPM_L<0>
CPU_BPM_L<1>
TP_CPU_BPM_L<2>
TP_CPU_BPM_L<3>
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
PROC_POPIRCOMP
PCH_OPIRCOMP
C
B
PPVCCIO_OUT
R0660
R0661
R0662
R0663
R0664
R0665
R0666
R0640
R0641
R0642
R0643
NOSTUFF
1K
21
1K
21
21
21
1K
21
1K
21
1K
21
10K
21
10K
21
10K
21
10K
21
75A2 15C7
PLACE_NEAR=J1800.10:20MM
NO_XNET_CONNECTION=1
5% 1/20W MF 201
PLACE_NEAR=J1800.12:20MM
NO_XNET_CONNECTION=1
MF1/20W5%
MF1/20W5%
MF1/20W5%
MF
201MF1/20W5%
201
201
201
2015%
PLACE_NEAR=J1800.9:20MM
NO_XNET_CONNECTION=1
5% MF1K201
1/20W
PLACE_NEAR=J1800.11:20MM
NO_XNET_CONNECTION=1
5% 1/20W MF1K201
PLACE_NEAR=J1800.15:20MM
NO_XNET_CONNECTION=1
PLACE_NEAR=J1800.27:20MM
NO_XNET_CONNECTION=1
PLACE_NEAR=J1800.29:20MM
NO_XNET_CONNECTION=1
NO_XNET_CONNECTION=1
1/20W
NO_XNET_CONNECTION=1
5% 201
1/20W MF
NO_XNET_CONNECTION=1
5% 201
1/20W MF
NO_XNET_CONNECTION=1
5% 201
1/20W MF
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<12>
CPU_CFG<13>
CPU_BPM_L<0>
CPU_BPM_L<1>
TP_CPU_BPM_L<2>
TP_CPU_BPM_L<3>
6C5 15C8 15D6
6C5 15D6
6B5 15D3
6B5 15D3
6B5 15D3
6B5 15D3
6B5 15D3
6D5 15D6 77D3
6D5 15D6
6D5
6D5
49.9
1%
1/20W
MF
201
1
2
R0681
PLACE_NEAR=U0500.CF41:12.7MM
R0682
49.9
1%
1/20W
MF
201
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
R0680
49.9
1%
1/20W
MF
201
SD3_RCOMP
1
2
PLACE_NEAR=U0500.CN1:12.7MM
15D6
R0622
6B7 15C8
BI
6B7 15D6
BI
15D6
BI
15D6
BI
6A8 15D6
BI
15D6
BI
15C6
BI
15C6
BI
6B7 15D3
BI
6B7 15D3
BI
6B7 15D3
BI
15D3
BI
6B7 15D3
BI
6B7 15D3
BI
15C3
BI
15C3
BI
15D3
BI
15D3
BI
15D3
BI
15D3
BI
1
200
1%
1/20W
MF
201
2
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>
CPU_CFG<18>
CPU_CFG<19>
PLACE_NEAR=U0500.CU47:12.7MM
CPU_CFG_RCOMP
15C2
1
2
OUT
ITP_PMODE
FIVR_PROBE_ANA_0
15A6
FIVR_PROBE_ANA_1
15A6
FIVR_PROBE_DIG_0
15A6
FIVR_PROBE_DIG_1
15A6
FIVR_ANAPB0
15A6
FIVR_ANAPB1
15A6
CU47
BF10
BD10
BG10
CU33
CV32
SD3_RCOMP
G9
H8
G8
K5
K6
N4
N5
K4
R5
R6
R8
T8
N6
Y8
V8
T4
M5
M6
U2
U1
R1
K1
BE9
OMIT_TABLE
ICL-UN-4+2
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
DBG_PMODE
IST_TP[0]
IST_TP[1]
IST_TRIG[0]
IST_TRIG[1]
PCH_IST_TP[0]
PCH_IST_TP[1]
SYM 18 OF 19
U0500
ICL-UN
BGA
RESERVED
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
TP
TP
TP
TP
A43
AB1
AL10
AT10
AV1
AV2
AV10
AW1
AW2
B44
BG9
BK34
BL2
BM2
CE10
CG10
CN32
CP33
CT33
CU32
CY10
DC1
DD1
DH9
DH20
DJ9
K2
R33
T33
CR32
CV10
DJ45
DJ46
DDR_VIEW_0
TP_CPU_RSVD_AB1
FIVR_VLOAD_SA
FIVR_VLOAD_CORE1
NC_TP_CPU_RSVD_AV1
TP_CPU_RSVD_AV2
FIVR_VLOAD_CORE3
NC_TP_CPU_RSVD_AW1
TP_CPU_RSVD_AW2
DDR_VIEW_1
FIVR_VLOAD_TCSS
FIVR_VLOAD_CORE2
NC_TP_CPU_RSVD_BL2
NC_TP_CPU_RSVD_BM2
PEG_VIEW_2
PEG_VIEW_3
NC_TP_CPU_RSVD_CN32
NC_TP_CPU_RSVD_CP33
FIVR_VLOAD_VCCIO
FIVR_VLOAD_VNN
FIVR_VLOAD_1P05
NC_TP_CPU_RSVD_DC1
NC_TP_CPU_RSVD_DD1
NC_TP_CPU_RSVD_DH9
NC_TP_CPU_RSVD_DH20
NC_TP_CPU_RSVD_DJ9
TP_CPU_RSVD_K2
FIVR_VLOAD_CCF
FIVR_VLOAD_CORE0
NC_TP_CPU_RSVD_CR32
NC_TP_CPU_RSVD_CV10
NC_TP_CPU_RSVD_DJ45
NC_TP_CPU_RSVD_DJ46
15A8
15A8
15A8
76B3
15A8
76C3
15A8
15A8
15A8
76B3
76C3
15A8
15A8
76C3
76C3
15A6
15A6
15A6
76C3
76C3
76C3
76C3
76C3
15A8
15A8
76B3
76C3
76C3
76C3
C
B
A
1
2
1
R0650
100K
5%
1/16W
MF-LF
402
2
CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CPU_CFG<4>
6B5 15D6
EDP_ENABLE
R0634
1K
5%
1/20W
MF
201
8
NOSTUFF
IFDIM TRIGGER
DESIGN: X502/DEV_MLB_U
LAST CHANGE: Mon Apr 27 22:56:39 2015
A
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
PAGE TITLE
CPU MISC/JTAG/CFG/RSVD
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
6 OF 150
SHEET
6 OF 109
1
SIZE
D
678
www.haojiyoubbs.com
QQ微信：181806465
3 245
1
D
C
B
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18D5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18C5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
18B5
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MEM_A_DQ_0<0>
MEM_A_DQ_0<1>
MEM_A_DQ_0<2>
MEM_A_DQ_0<3>
MEM_A_DQ_0<4>
MEM_A_DQ_0<5>
MEM_A_DQ_0<6>
MEM_A_DQ_0<7>
MEM_A_DQ_1<0>
MEM_A_DQ_1<1>
MEM_A_DQ_1<2>
MEM_A_DQ_1<3>
MEM_A_DQ_1<4>
MEM_A_DQ_1<5>
MEM_A_DQ_1<6>
MEM_A_DQ_1<7>
MEM_A_DQ_2<0>
MEM_A_DQ_2<1>
MEM_A_DQ_2<2>
MEM_A_DQ_2<3>
MEM_A_DQ_2<4>
MEM_A_DQ_2<5>
MEM_A_DQ_2<6>
MEM_A_DQ_2<7>
MEM_A_DQ_3<0>
MEM_A_DQ_3<1>
MEM_A_DQ_3<2>
MEM_A_DQ_3<3>
MEM_A_DQ_3<4>
MEM_A_DQ_3<5>
MEM_A_DQ_3<6>
MEM_A_DQ_3<7>
MEM_B_DQ_0<0>
MEM_B_DQ_0<1>
MEM_B_DQ_0<2>
MEM_B_DQ_0<3>
MEM_B_DQ_0<4>
MEM_B_DQ_0<5>
MEM_B_DQ_0<6>
MEM_B_DQ_0<7>
MEM_B_DQ_1<0>
MEM_B_DQ_1<1>
MEM_B_DQ_1<2>
MEM_B_DQ_1<3>
MEM_B_DQ_1<4>
MEM_B_DQ_1<5>
MEM_B_DQ_1<6>
MEM_B_DQ_1<7>
MEM_B_DQ_2<0>
MEM_B_DQ_2<1>
MEM_B_DQ_2<2>
MEM_B_DQ_2<3>
MEM_B_DQ_2<4>
MEM_B_DQ_2<5>
MEM_B_DQ_2<6>
MEM_B_DQ_2<7>
MEM_B_DQ_3<0>
MEM_B_DQ_3<1>
MEM_B_DQ_3<2>
MEM_B_DQ_3<3>
MEM_B_DQ_3<4>
MEM_B_DQ_3<5>
MEM_B_DQ_3<6>
MEM_B_DQ_3<7>
BW46
BW44
BW47
BU47
BW43
BU44
BU43
BU46
BT40
BT37
BT41
BV36
BT36
BV37
BV40
BV41
BP46
BP44
BP47
BM47
BP43
BM44
BM43
BM46
BL40
BL37
BL41
BN36
BL36
BN37
BN40
BN41
AW46
AW44
AW47
AU43
AW43
AU44
AU46
AU47
AU37
AV37
AU36
AV40
AV36
AU40
AV41
AU41
AP46
AP44
AP47
AM46
AP43
AM44
AM43
AM47
AM37
AN36
AM36
AN40
AN37
AM40
AN41
AM41
OMIT_TABLE
DDRA_DQ0[0]
DDRA_DQ0[1]
DDRA_DQ0[2]
DDRA_DQ0[3]
DDRA_DQ0[4]
DDRA_DQ0[5]
DDRA_DQ0[6]
DDRA_DQ0[7]
DDRA_DQ1[0]
DDRA_DQ1[1]
DDRA_DQ1[2]
DDRA_DQ1[3]
DDRA_DQ1[4]
DDRA_DQ1[5]
DDRA_DQ1[6]
DDRA_DQ1[7]
DDRA_DQ2[0]
DDRA_DQ2[1]
DDRA_DQ2[2]
DDRA_DQ2[3]
DDRA_DQ2[4]
DDRA_DQ2[5]
DDRA_DQ2[6]
DDRA_DQ2[7]
DDRA_DQ3[0]
DDRA_DQ3[1]
DDRA_DQ3[2]
DDRA_DQ3[3]
DDRA_DQ3[4]
DDRA_DQ3[5]
DDRA_DQ3[6]
DDRA_DQ3[7]
DDRB_DQ0[0]
DDRB_DQ0[1]
DDRB_DQ0[2]
DDRB_DQ0[3]
DDRB_DQ0[4]
DDRB_DQ0[5]
DDRB_DQ0[6]
DDRB_DQ0[7]
DDRB_DQ1[0]
DDRB_DQ1[1]
DDRB_DQ1[2]
DDRB_DQ1[3]
DDRB_DQ1[4]
DDRB_DQ1[5]
DDRB_DQ1[6]
DDRB_DQ1[7]
DDRB_DQ2[0]
DDRB_DQ2[1]
DDRB_DQ2[2]
DDRB_DQ2[3]
DDRB_DQ2[4]
DDRB_DQ2[5]
DDRB_DQ2[6]
DDRB_DQ2[7]
DDRB_DQ3[0]
DDRB_DQ3[1]
DDRB_DQ3[2]
DDRB_DQ3[3]
DDRB_DQ3[4]
DDRB_DQ3[5]
DDRB_DQ3[6]
DDRB_DQ3[7]
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 2 OF 19
LPDDR4 NON-INTERLEAVED0
DDRA_CLK_P
DDRA_CLK_N
DDRB_CLK_P
DDRB_CLK_N
DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1
DDRA_CS[0]
DDRA_CS[1]
DDRB_CS[0]
DDRB_CS[1]
DDRA_CA0
DDRA_CA1
DDRA_CA2
DDRA_CA3
DDRA_CA4
DDRA_CA5
DDRB_CA0
DDRB_CA1
DDRB_CA2
DDRB_CA3
DDRB_CA4
DDRB_CA5
DDRA_DQSN[0]
DDRA_DQSN[1]
DDRA_DQSN[2]
DDRA_DQSN[3]
DDRA_DQSP[0]
DDRA_DQSP[1]
DDRA_DQSP[2]
DDRA_DQSP[3]
DDRB_DQSN[0]
DDRB_DQSN[1]
DDRB_DQSN[2]
DDRB_DQSN[3]
DDRB_DQSP[0]
DDRB_DQSP[1]
DDRB_DQSP[2]
DDRB_DQSP[3]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DDR0_VREF_CA
DDR1_VREF_CA
DDR_VTT_CTL
BJ44
BJ46
BB41
BB40
BG47
BH45
BB36
BB38
BF36
BF40
BH40
BC40
BG46
BD44
BD43
BG44
BG43
BB47
BF37
BE40
BC41
BF38
BF41
BC36
BV45
BT38
BN45
BL38
BV44
BV38
BN44
BN38
AV44
AU38
AN44
AM38
AV45
AV38
AN45
AN38
BD47
BC44
BC37
BC45
BB46
BJ47
BE36
BB44
BD46
BJ43
BH44
BE37
BB43
BB37
C42
E42
M37
MEM_A_CLK_P
MEM_A_CLK_N
MEM_B_CLK_P
MEM_B_CLK_N
MEM_A_CKE<0>
MEM_A_CKE<1>
MEM_B_CKE<0>
MEM_B_CKE<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_B_CS_L<0>
MEM_B_CS_L<1>
MEM_A_CA<0>
MEM_A_CA<1>
MEM_A_CA<2>
MEM_A_CA<3>
MEM_A_CA<4>
MEM_A_CA<5>
MEM_B_CA<0>
MEM_B_CA<1>
MEM_B_CA<2>
MEM_B_CA<3>
MEM_B_CA<4>
MEM_B_CA<5>
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
NC
CPU_DDR0_ALERT_L
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
18D8
18D8
18C8
18C8
18D8
18D8
18C8
18C8
18D8
18D8
18C8
18C8
18D8
18D8
18D8
18D8
18D8
18D8
18C8
18C8
18C8
18C8
18C8
18C8
18A5
18A5
18A5
18A5
18A5
18A5
18A5
18A5
18A5
18A5
18A5
18A5
18A5
18A5
18A5
18A5
R0730
0
5%
1/20W
MF
0201
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18D3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18C3
BI
18B3
BI
18B3
BI
21
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
18B3
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MEM_C_DQ_0<0>
MEM_C_DQ_0<1>
MEM_C_DQ_0<2>
MEM_C_DQ_0<3>
MEM_C_DQ_0<4>
MEM_C_DQ_0<5>
MEM_C_DQ_0<6>
MEM_C_DQ_0<7>
MEM_C_DQ_1<0>
MEM_C_DQ_1<1>
MEM_C_DQ_1<2>
MEM_C_DQ_1<3>
MEM_C_DQ_1<4>
MEM_C_DQ_1<5>
MEM_C_DQ_1<6>
MEM_C_DQ_1<7>
MEM_C_DQ_2<0>
MEM_C_DQ_2<1>
MEM_C_DQ_2<2>
MEM_C_DQ_2<3>
MEM_C_DQ_2<4>
MEM_C_DQ_2<5>
MEM_C_DQ_2<6>
MEM_C_DQ_2<7>
MEM_C_DQ_3<0>
MEM_C_DQ_3<1>
MEM_C_DQ_3<2>
MEM_C_DQ_3<3>
MEM_C_DQ_3<4>
MEM_C_DQ_3<5>
MEM_C_DQ_3<6>
MEM_C_DQ_3<7>
MEM_D_DQ_0<0>
MEM_D_DQ_0<1>
MEM_D_DQ_0<2>
MEM_D_DQ_0<3>
MEM_D_DQ_0<4>
MEM_D_DQ_0<5>
MEM_D_DQ_0<6>
MEM_D_DQ_0<7>
MEM_D_DQ_1<0>
MEM_D_DQ_1<1>
MEM_D_DQ_1<2>
MEM_D_DQ_1<3>
MEM_D_DQ_1<4>
MEM_D_DQ_1<5>
MEM_D_DQ_1<6>
MEM_D_DQ_1<7>
MEM_D_DQ_2<0>
MEM_D_DQ_2<1>
MEM_D_DQ_2<2>
MEM_D_DQ_2<3>
MEM_D_DQ_2<4>
MEM_D_DQ_2<5>
MEM_D_DQ_2<6>
MEM_D_DQ_2<7>
MEM_D_DQ_3<0>
MEM_D_DQ_3<1>
MEM_D_DQ_3<2>
MEM_D_DQ_3<3>
MEM_D_DQ_3<4>
MEM_D_DQ_3<5>
MEM_D_DQ_3<6>
MEM_D_DQ_3<7>
AJ46
AJ44
AJ47
AG43
AJ43
AG44
AG46
AG47
AG37
AG36
AJ37
AJ41
AJ36
AJ40
AG41
AG40
AD46
AD44
AD47
AB47
AD43
AB46
AB44
AB43
AD37
AD36
AB36
AD40
AB37
AD41
AB41
AB40
J46
J43
J47
G44
J44
G43
G46
E45
J36
G37
G36
G40
J37
J40
G41
J41
B40
E40
A40
D38
D40
E38
B38
A38
B33
E33
A33
E35
D33
D35
B35
A35
DDRC_DQ0[0]
DDRC_DQ0[1]
DDRC_DQ0[2]
DDRC_DQ0[3]
DDRC_DQ0[4]
DDRC_DQ0[5]
DDRC_DQ0[6]
DDRC_DQ0[7]
DDRC_DQ1[0]
DDRC_DQ1[1]
DDRC_DQ1[2]
DDRC_DQ1[3]
DDRC_DQ1[4]
DDRC_DQ1[5]
DDRC_DQ1[6]
DDRC_DQ1[7]
DDRC_DQ2[0]
DDRC_DQ2[1]
DDRC_DQ2[2]
DDRC_DQ2[3]
DDRC_DQ2[4]
DDRC_DQ2[5]
DDRC_DQ2[6]
DDRC_DQ2[7]
DDRC_DQ3[0]
DDRC_DQ3[1]
DDRC_DQ3[2]
DDRC_DQ3[3]
DDRC_DQ3[4]
DDRC_DQ3[5]
DDRC_DQ3[6]
DDRC_DQ3[7]
DDRD_DQ0[0]
DDRD_DQ0[1]
DDRD_DQ0[2]
DDRD_DQ0[3]
DDRD_DQ0[4]
DDRD_DQ0[5]
DDRD_DQ0[6]
DDRD_DQ0[7]
DDRD_DQ1[0]
DDRD_DQ1[1]
DDRD_DQ1[2]
DDRD_DQ1[3]
DDRD_DQ1[4]
DDRD_DQ1[5]
DDRD_DQ1[6]
DDRD_DQ1[7]
DDRD_DQ2[0]
DDRD_DQ2[1]
DDRD_DQ2[2]
DDRD_DQ2[3]
DDRD_DQ2[4]
DDRD_DQ2[5]
DDRD_DQ2[6]
DDRD_DQ2[7]
DDRD_DQ3[0]
DDRD_DQ3[1]
DDRD_DQ3[2]
DDRD_DQ3[3]
DDRD_DQ3[4]
DDRD_DQ3[5]
DDRD_DQ3[6]
DDRD_DQ3[7]
SYM 3 OF 19
LPDDR4 NON-INTERLEAVED
DDRC_CLK_P
DDRC_CLK_N
DDRD_CLK_P
DDRD_CLK_N
DDRC_CKE0
DDRC_CKE1
DDRD_CKE0
DDRD_CKE1
DDRC_CS[0]
DDRC_CS[1]
DDRD_CS[0]
DDRD_CS[1]
DDRC_CA0
DDRC_CA1
DDRC_CA2
DDRC_CA3
DDRC_CA4
DDRC_CA5
DDRD_CA0
DDRD_CA1
DDRD_CA2
DDRD_CA3
DDRD_CA4
DDRD_CA5
DDRC_DQSN[0]
DDRC_DQSN[1]
DDRC_DQSN[2]
DDRC_DQSN[3]
DDRC_DQSP[0]
DDRC_DQSP[1]
DDRC_DQSP[2]
DDRC_DQSP[3]
DDRD_DQSN[0]
DDRD_DQSN[1]
DDRD_DQSN[2]
DDRD_DQSN[3]
DDRD_DQSP[0]
DDRD_DQSP[1]
DDRD_DQSP[2]
DDRD_DQSP[3]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DRAM_RESET*
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
W44
W46
M40
M41
U43
V44
M38
P41
U40
U37
W37
T37
P47
P44
U47
M43
M44
P43
W38
W40
U38
V45
T36
U46
AH44
AG38
AC45
AD38
AH45
AJ38
AC44
AB38
H45
G38
C39
D34
H44
J38
D39
C34
M46
M47
T40
N45
P40
W47
P37
N44
P46
W43
U44
U41
U36
P36
CB43
D44
E44
C43
MEM_C_CLK_P
MEM_C_CLK_N
MEM_D_CLK_P
MEM_D_CLK_N
MEM_C_CKE<0>
MEM_C_CKE<1>
MEM_D_CKE<0>
MEM_D_CKE<1>
MEM_C_CS_L<0>
MEM_C_CS_L<1>
MEM_D_CS_L<0>
MEM_D_CS_L<1>
MEM_C_CA<0>
MEM_C_CA<1>
MEM_C_CA<2>
MEM_C_CA<3>
MEM_C_CA<4>
MEM_C_CA<5>
MEM_D_CA<0>
MEM_D_CA<1>
MEM_D_CA<2>
MEM_D_CA<3>
MEM_D_CA<4>
MEM_D_CA<5>
MEM_C_DQS_N<0>
MEM_C_DQS_N<1>
MEM_C_DQS_N<2>
MEM_C_DQS_N<3>
MEM_C_DQS_P<0>
MEM_C_DQS_P<1>
MEM_C_DQS_P<2>
MEM_C_DQS_P<3>
MEM_D_DQS_N<0>
MEM_D_DQS_N<1>
MEM_D_DQS_N<2>
MEM_D_DQS_N<3>
MEM_D_DQS_P<0>
MEM_D_DQS_P<1>
MEM_D_DQS_P<2>
MEM_D_DQS_P<3>
NC
CPU_DDR1_ALERT_L
NC
PP1V1_S3_CPU
NC
NC
1
NC
NC
NC
NC
R0740
470
1%
1/20W
MF
201
2
NC
MEM_RESET_R_L
NC
NC
NC
NC
CPU_DDR_RCOMP<0>
CPU_DDR_RCOMP<1>
CPU_DDR_RCOMP<2>
R0741
1/20W
0201
R0750
100
1%
1/20W
MF
201
0
5%
MF
1
2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
18C8
18C8
18B8
18B8
18C8
18C8
18B8
18B8
18C8
18C8
18B8
18B8
18C8
18C8
18C8
18C8
18C8
18C8
18B8
18B8
18B8
18B8
18B8
18B8
18A3
18A3
18A3
18A3
18A3
18A3
18A3
18A3
18A3
18A3
18A3
18A3
18A3
18A3
18A3
18A3
79C4
21
77B4 75A1 8D7
MEM_RESET_L
NOSTUFF
1
C0741
0.1UF
10%
16V
2
X5R-CERM
0201
R0751
100
1%
1/20W
MF
201
R0731
0
5%
1/20W
MF
0201
1
2
R0752
21
100
1%
1/20W
MF
201
OUT
1
2
18B8 18C8
18D8
D
C
B
A
BOM_COST_GROUP=CPU & CHIPSET
PLACE_NEAR=U0500.C43:12.7mm
PLACE_NEAR=U0500.E44:12.7mm
PLACE_NEAR=U0500.D44:12.7mm
PAGE TITLE
CPU LPDDR4x Interface
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-05198
REVISION
BRANCH
PAGE
7 OF 150
SHEET
7 OF 109
6.0.0
evt-3
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
SIZE
A
D
8
67
35 4
2
1
678
www.haojiyoubbs.com
QQ微信：181806465
3 245
1
D
C
B
A
A13
A15
A18
A20
A23
A25
A28
A30
AA10
AB11
AC10
AD1
AD11
AE10
AF1
AF10
AG1
AH1
B10
B12
B13
B15
B17
B18
B20
B22
B23
B25
B26
B28
B30
BN9
BR34
BR9
BT34
BT9
BU10
BU35
BV34
BV9
BW10
BW34
BW35
BW8
BY10
BY35
BY9
C10
CA34
CA36
CA9
CB10
CB35
CC34
CC36
CC9
CD10
CD33
CD35
CD36
CD9
CE32
CE8
CF33
CF35
CF36
CF9
CG32
CH32
CH33
CH35
CJ33
CJ35
CJ36
CK32
CL33
CL35
CL36
CM32
CM33
CM35
CP35
CP36
CT35
CU35
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
PPVCCIN_S0_CPU
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 11 OF 19
POWER 1
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN
VCCIN_SENSE
VSSIN_SENSE
VIDALERT*
VIDSCK
VIDSOUT
80D8 79D6 77D2 75C3 40B4
79C4 77B4 75A1 7B1
VCCIN
0 - 1.89V
80A IccMax
from IBL# 575925
D13
D15
D18
D20
D23
D25
D28
D30
E10
E12
E13
E15
E17
E18
E20
E22
E23
E25
E26
E28
E30
F13
F15
F18
F20
F23
F25
F28
G12
G13
G15
G17
G18
G20
G22
G23
G25
G26
G28
J11
J13
J14
J16
J17
J19
J21
J22
J24
J26
J27
J29
K10
K15
K18
K20
K23
K25
K28
K30
K9
L1
L11
M10
M11
M9
N10
P11
R10
T10
T11
U11
V1
V10
W11
Y10
Y11
Y9
B9
D9
H5
G6
G5
13D8 10B3 8A5 6D6
64A2 54B3 31B6 16C7
77D2 75A3 10B3
77D2 16C2 11B8 11A5
PLACE_NEAR=U0500.B9:12.7mm
NO_XNET_CONNECTION=1
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R
77D2 75B4
6D7 15D2
PP1V1_S3_CPU
VDDQ
1.1V +/- 5%
3.5A IccMax
from IBL# 572795
PP1V05_S0_CPU_VCCST
1.05V, 750mA
PP1V05_S0SW_VCCSTG
1.05V, 150mA
PP1V05_VCCSTG_OUT
Bypass only
VOLTAGE=1.05V
PP1V05_VCCSTG_OUT_LGC
Reference Power rail for all Legacy
Signals Pull-up on Platform
1
R0805
100
5%
1/20W
MF
201
2
R0800.2:
PLACE_NEAR=U0500.H5:12.7mm
PLACE_NEAR=U0500.D9:12.7mm
1
R0804
100
5%
1/20W
MF
201
2
NO_XNET_CONNECTION=1
R0811
0
2 1
R0812
0
2 1
5% 0201
1/20WMF
5% 0201
R0801.2:
54D8
OUT
54D8
OUT
1/20WMF
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
AA33
AA35
AA46
AB34
AC33
AC35
AD33
AD34
AE34
AF35
AF46
AG34
AH35
AJ34
AK34
AL35
AL46
AM34
AN34
AN35
AR34
AT35
AT46
AU34
AU35
AV34
AY34
BA35
BA46
BB34
BB35
CF1
CE1
G31
G33
G34
J31
J33
J34
K33
PLACE_NEAR=U0500.G6:12.7mm
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCCST
VCCSTG
VCCSTG_OUT
VCCSTG_OUT
VCCSTG_OUT
VCCSTG_OUT
VCCSTG_OUT
VCCSTG_OUT
VCCSTG_OUT
F2
VCCSTG_OUT_LGC
SYM 13 OF 19
POWER 3
NOSTUFF
R0800
56
1%
1/20W
MF
201
1
2
R0801
43
1%
1/20W
MF
201
1
2
R0810
0
2 1
5% 0201
MF 1/20W
BGA
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCCPLL
VCCPLL
VCCPLL_OC
VCCPLL_OC
VCCPLL_OC
VCCPLL_OC
VCC1P8A
VCC1P8A
VCC1P8A
VCC1P8A
VCC1P8A
VCC1P8A
VCC1P8A
VCC1P8A
VCC1P8A
BC34
BD35
BE34
BF35
BF46
BG35
BH36
BK35
BL34
BL46
BM35
BP35
BT46
CA46
K34
K46
M34
N33
N35
P34
R35
T34
T35
T46
V35
W34
Y33
Y34
CJ1
CK1
CC44
CC45
CD40
CD41
BJ10
BK9
BL10
BL9
BM10
BM8
CD1
CD2
CE2
PP1V05_S0_CPU_VCCST
R0802.2:
PLACE_NEAR=U0500.G5:12.7mm
1
R0802
100
1%
1/20W
MF
201
2
CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT
IN
OUT
BI
PP1V05_S0_CPU_VCCPLL
1.05V, 90mA, bypass only
PP1V1_S0SW
1.1V, 160mA
PP1V8_S0SW
1.8V, 700mA
54B2
54B2
54B2
80D8 79C6 77D2 75B3 40A5 16D2
56D8
OUT
56D8
OUT
75A3 10C3
77D2 75A4 11D8
79A6 75C1 11C8
74B2 15B4 11B8
77D2 75B4 64A2 54B3 31B6 16C7 13D8 10B3 8C7 6D6
77D2 11C8 11A5
74B2 11C8
74B4 8B1
77D2 74A4 8B1
PPVCCIN_AUX_PCH_PRIM
PLACE_NEAR=U0500.AW8:50.8MM
1
R0820
100
5%
1/20W
MF
201
2
PCH_VCCINSENSE_P
PCH_VCCINSENSE_N
PLACE_NEAR=U0500.AV8:50.8MM
1
R0821
100
5%
1/20W
MF
201
2
77D2 75B4 10C3
77D2 75A4 64D1 10C3
PP1V05_PRIM_OUT_PCH
Bypass only
PP1V8_S5
1.8V, 1.3A
PP3V3_S5
3.3V, 202mA
PP1V05_S5_PCH_VCCDSW
Bypass only
PP3V3_S5
3.3V, 4mA
PLACE_NEAR=U0500.DA15:30MM
PPVNN_PCH_EXT
PLACE_NEAR=U0500.DA17:30MM
PP1P05_PCH_EXT
VCCIN_AUX
1.8V typ
19A IccMax
from IBL# 575925
XW0850
SHORT-14L-0.1MM-SM
XW0853
SHORT-14L-0.1MM-SM
AG9
AH8
AJ8
AJ9
AK9
AL1
AL8
AM1
AM9
AN10
AN9
AP1
AP8
AR1
AR9
AT8
AU9
AV9
AY9
BB10
BB9
BC9
AW8
AV8
CP37
CT37
CU37
DA18
DA20
DA21
DA23
DA33
DB18
DB20
DB21
DB23
DD18
DD20
DD21
DD23
DA37
DA25
DA26
DA28
DB25
DB26
DB28
DD25
DD26
DD28
DG32
DH32
CW33
21
21
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX_VCCSENSE
VCCIN_AUX_VSSSENSE
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P05
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_1P8
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCDSW_1P05
VCCDSW_1P05
VCCDSW_3P3
PVCC_FB_P
P1VPRIM_FB_R
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 12 OF 19
POWER 2
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
OMIT_TABLE
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
VCCIN_AUX
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 14 OF 19
VCC_V1P05EXT_1P05
VCC_V1P05EXT_1P05
VCC_V1P05EXT_1P05
VCC_VNNEXT_1P05
VCC_VNNEXT_1P05
VCC_VNNEXT_1P05
VCCA_CLKLDO_1P8
VCCA_CLKLDO_1P8
VCCIO_OUT
VCCLDOSTD_0P85
VCCLDOSTD_0P85
VCCPGPPR
VCCRTC
POWER 4
VCCDPHY_1P24
VCCDPHY_1P24
CKPLUS_WAIVE=MISS_N_DIFFPAIR
VCCRTC
VCCSPI
VCCSPI
VCC1P05
VCC1P05
VCC1P05
R0850
R0853
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
IV ALL RIGHTS RESERVED
CH10
CH9
CJ11
CK10
CK9
CL11
CM10
CM9
CN10
CN11
CN8
CN9
CP1
CP11
CR1
CR10
CR8
CR9
CT11
CU1
CU10
CU11
CW11
CG44
CG43
DA17
DB17
DD17
DA15
DB15
DD15
DG13
DH13
AN8
DG27
DH27
DD30
DG38
DH38
DA30
DB30
DG16
DH16
CH1
CH2
CJ2
NOSTUFF
NOSTUFF
D
PCH_CORE_VID0
PCH_CORE_VID1
BI
BI
17D3
17D3
C
PP1P05_PCH_EXT
1.05V, 200mA
PPVNN_PCH_EXT
1.05V, 200mA
PP1V8_PCH_CLKLDO
1.8V, 165mA
PPVCCIO_OUT
Pull ups only
PP0V85_LDOSTD
Bypass only
PP1V8_S5
1.8V, 5mA
PP3V_G3H_RTC
3.3V, 2mA
PP1V8_S5
3.3V, 3mA
PP1V24_S5_PCH_VCCDPHY
Bypass only
PP1V05_PCH_OUT_FET
Output to VCCST and VCCSTG
PLACE_NEAR=R7819.2:5MM
21
0
5%
PLACE_NEAR=R7820.2:5MM
21
PVCCPCOREPRIM_FB_P
1/20W 0201MF
P1VPRIM_FB
02015%01/20W MF
75C1
75B1
OUT
OUT
CPU & PCH Power
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
BRANCH
evt-3
PAGE
8 OF 150
SHEET
8 OF 109
74B4 8A4
77D2 75A4
74C2 11B8
77C2 75B4
60B6
60B6
77D2 74A4 8A4
77D2 11C3 11B5
77D2 11D8 11A5
B
77D2 11D8 11A5
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
SIZE
A
D
8
67
35 4
2
1
678
www.haojiyoubbs.com
QQ微信：181806465
3 245
1
D
C
B
A3
A5
A6
A9
A12
A17
A22
A26
A45
A46
AA4
AA5
AA6
AA9
AA42
AA45
AC1
AC2
AC6
AC9
AC42
AC46
AD2
AD35
AE6
AE8
AE9
AE36
AE37
AE38
AE40
AE41
AF2
AF6
AF8
AF42
AF45
AG2
AH2
AH6
AH42
AH46
AJ6
AJ35
AK1
AK2
AK36
AK37
AK38
AK40
AK41
AL2
AL6
AL42
AL45
AM2
AN6
AN42
AN46
AP2
AP6
AP35
AR2
AR36
AR37
AR38
AR40
AR41
AT1
AT2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 15 OF 19
GND1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AT6
AT42
AT45
AV6
AV42
AV46
AW4
AW5
AW6
AW35
AY1
AY2
AY36
AY37
AY38
AY40
AY41
B2
B4
B6
B7
B31
B34
B36
B39
B42
B46
B47
BA4
BA8
BA42
BA45
BB4
BB8
BC38
BC42
BC46
BD4
BD8
BE1
BE2
BE38
BE41
BF4
BF5
BF6
BF8
BF42
BF45
BG4
BG8
BH37
BH41
BH42
BH46
BJ1
BJ2
BJ4
BJ8
BJ35
BK36
BK37
BK38
BK40
BK41
BL4
BL8
BL42
BL45
BM4
BM5
BM6
BN1
BN2
BN42
BN46
BP4
BP8
BR4
BR8
BR35
BR36
BR37
BR38
BR40
BR41
BT42
BT45
BU4
BU8
BV1
BV2
BV42
BV46
BW4
BW5
BW6
BW36
BW37
BW38
BW40
BW41
BY4
BY8
C1
C7
C31
C36
C47
CA37
CA42
CA45
CB1
CB2
CB4
CB8
CC42
CC46
CD4
CD8
CD38
CE4
CE5
CE6
CF2
CF37
CF42
CF46
CG8
CH4
CH8
CH36
CH42
CH46
CJ37
CJ38
CJ41
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 16 OF 19
GND2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK2
CK8
CL37
CL42
CL45
CL46
CM4
CM8
CM36
CM37
CM38
CM40
CM41
CN6
CN42
CN46
CP2
CP38
CR2
CR6
CT36
CT38
CT42
CT45
CT46
CU2
CU6
CU8
CU9
CU36
CV6
CV42
CV46
CW36
CW37
CW38
CW40
CY6
CY12
CY14
CY16
CY17
CY19
CY21
CY22
CY24
CY25
CY27
CY29
CY30
CY32
D6
D7
D12
D17
D22
D26
D46
D47
DA6
DA10
DA13
DA31
DA35
DA42
DA45
DA46
DB13
DB31
DB37
DB43
DB47
DC6
DC10
DC44
DC45
DC46
DD12
DD13
DD31
DD33
DE7
DE9
DE10
DE13
DE16
DE18
DE21
DE24
DE27
DE30
DE32
DE38
DE41
DE46
DE47
DF4
DF45
DG7
DG47
DH1
DH4
DH7
DH42
DH45
DH47
DJ4
DJ6
DJ42
DJ44
E1
E5
E9
E36
F12
F17
F22
F26
F30
F31
F33
F34
F39
G4
G10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 17 OF 19
GND 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G30
G47
H4
H9
H10
H42
H46
K8
K13
K17
K22
K26
K31
K42
K45
L2
L33
L35
L36
L37
L38
L40
L41
M4
M8
N8
N9
N42
N46
P38
R2
R4
R9
T9
T38
T41
T42
T45
U34
V2
V4
V9
V33
V42
V46
W2
W36
W41
Y4
Y35
Y36
Y37
Y38
Y40
Y41
D
C
B
A
8
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
PAGE TITLE
A
CPU & PCH Grounds
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
9 OF 150
SHEET
9 OF 109
1
SIZE
D
678
www.haojiyoubbs.com
QQ微信：181806465
3 245
1
D
75C3
PPVCCIN_S0_CPU
PLACE_SIDE=TOP
1
C1000
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C100F
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C100U
1UF
20%
6.3V
2
X6S-CERM
0201
1
2
1
2
1
2
PLACE_SIDE=TOP
PLACE_SIDE=TOP
C1001
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C100G
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C100V
1UF
20%
6.3V
X6S-CERM
0201
1
2
PLACE_SIDE=TOP
1
2
PLACE_SIDE=TOP
1
2
C1002
1UF
20%
6.3V
X6S-CERM
0201
C100H
1UF
20%
6.3V
X6S-CERM
0201
C100W
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
1
C1003
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C100I
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C100X
1UF
20%
6.3V
2
X6S-CERM
0201
1
2
1
2
1
2
PLACE_SIDE=TOP
PLACE_SIDE=TOP
C1004
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C100J
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C100Y
1UF
20%
6.3V
X6S-CERM
0201
1
2
PLACE_SIDE=TOP
1
2
PLACE_SIDE=TOP
1
2
C1005
1UF
20%
6.3V
X6S-CERM
0201
C100K
1UF
20%
6.3V
X6S-CERM
0201
C100Z
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
1
C1006
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C100L
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C1080
1UF
20%
6.3V
2
X6S-CERM
0201
1
2
1
2
1
2
PLACE_SIDE=TOP
PLACE_SIDE=TOP
C1007
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C100M
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C1081
1UF
20%
6.3V
X6S-CERM
0201
1
2
PLACE_SIDE=TOP
1
2
PLACE_SIDE=TOP
1
2
C1008
1UF
20%
6.3V
X6S-CERM
0201
C100N
1UF
20%
6.3V
X6S-CERM
0201
C1082
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
1
C1009
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C100O
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C1083
1UF
20%
6.3V
2
X6S-CERM
0201
1
2
1
2
1
2
PLACE_SIDE=TOP
PLACE_SIDE=TOP
C100A
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C100P
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C1084
1UF
20%
6.3V
X6S-CERM
0201
1
2
PLACE_SIDE=TOP
1
2
PLACE_SIDE=TOP
1
2
C100B
1UF
20%
6.3V
X6S-CERM
0201
C100Q
1UF
20%
6.3V
X6S-CERM
0201
C1085
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
1
C100C
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C100R
1UF
20%
6.3V
2
X6S-CERM
0201
PLACE_SIDE=TOP
1
C1086
1UF
20%
6.3V
2
X6S-CERM
0201
1
2
1
2
1
2
PLACE_SIDE=TOP
PLACE_SIDE=TOP
C100D
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C100S
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
C1087
1UF
20%
6.3V
X6S-CERM
0201
1
2
PLACE_SIDE=TOP
1
2
PLACE_SIDE=TOP
1
2
C100E
1UF
20%
6.3V
X6S-CERM
0201
C100T
1UF
20%
6.3V
X6S-CERM
0201
C1088
1UF
20%
6.3V
X6S-CERM
0201
PP1V1_S3_CPU
75A1
1
C10A0
1UF
20%
6.3V
2
X6S-CERM
0201
1
C10A8
10UF
20%
6.3V
2
CER-X6S
0402
1
C10A1
1UF
20%
6.3V
2
X6S-CERM
0201
1
C10A9
10UF
20%
6.3V
2
CER-X6S
0402
1
C10A2
1UF
20%
6.3V
2
X6S-CERM
0201
1
C10B0
10UF
20%
6.3V
2
CER-X6S
0402
1
C10A3
1UF
20%
6.3V
2
X6S-CERM
0201
1
C10B1
10UF
20%
6.3V
2
CER-X6S
0402
1
C10A4
1UF
20%
6.3V
2
X6S-CERM
0201
NOSTUFF
1
C10B2
10UF
20%
6.3V
2
CER-X6S
0402
1
C10A5
1UF
20%
6.3V
2
X6S-CERM
0201
NOSTUFF
1
C10B3
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
1
C10A6
1UF
20%
6.3V
2
X6S-CERM
0201
NOSTUFF
1
C10A7
1UF
20%
6.3V
2
X6S-CERM
0201
D
C
PLACE_SIDE=TOP
PLACE_SIDE=TOP
1
C1089
1UF
20%
6.3V
2
X6S-CERM
0201
MIRROR_WITH=C1011
1
C1010
10UF
20%
6.3V
2
CER-X6S
0402
1
C1025
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1041
1
C1040
10UF
20%
6.3V
2
CER-X6S
0402
1
C108A
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1011
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1027
1
C1026
10UF
20%
6.3V
2
CER-X6S
0402
1
C1041
10UF
20%
6.3V
2
CER-X6S
0402
PLACE_SIDE=TOP
PLACE_SIDE=TOP
1
C108B
1UF
20%
6.3V
2
X6S-CERM
0201
MIRROR_WITH=C1013
1
C1012
10UF
20%
6.3V
2
CER-X6S
0402
1
C1027
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1043
1
C1042
10UF
20%
6.3V
2
CER-X6S
0402
1
C108C
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1013
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1029
1
C1028
10UF
20%
6.3V
2
CER-X6S
0402
1
C1043
10UF
20%
6.3V
2
CER-X6S
0402
PLACE_SIDE=TOP
PLACE_SIDE=TOP
1
C108D
1UF
20%
6.3V
2
X6S-CERM
0201
MIRROR_WITH=C1015
1
C1014
10UF
20%
6.3V
2
CER-X6S
0402
1
C1029
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1045
1
C1044
10UF
20%
6.3V
2
CER-X6S
0402
1
C108E
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1015
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1031
1
C1030
10UF
20%
6.3V
2
CER-X6S
0402
1
C1045
10UF
20%
6.3V
2
CER-X6S
0402
PLACE_SIDE=TOP
PLACE_SIDE=TOP
1
C108F
1UF
20%
6.3V
2
X6S-CERM
0201
MIRROR_WITH=C1017
1
C1016
10UF
20%
6.3V
2
CER-X6S
0402
1
C1031
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1047
1
C1046
10UF
20%
6.3V
2
CER-X6S
0402
1
C108G
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1017
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1033
1
C1032
10UF
20%
6.3V
2
CER-X6S
0402
1
C1047
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1019
1
C1018
10UF
20%
6.3V
2
CER-X6S
0402
1
C1033
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1049
1
C1048
10UF
20%
6.3V
2
CER-X6S
0402
1
C1019
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1035
1
C1034
10UF
20%
6.3V
2
CER-X6S
0402
1
C1049
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1021
1
C1020
10UF
20%
6.3V
2
CER-X6S
0402
1
C1035
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1051
1
C1050
10UF
20%
6.3V
2
CER-X6S
0402
1
C1021
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1037
1
C1036
10UF
20%
6.3V
2
CER-X6S
0402
1
C1051
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1023
1
C1022
10UF
20%
6.3V
2
CER-X6S
0402
1
C1037
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1053
1
C1052
10UF
20%
6.3V
2
CER-X6S
0402
1
C1023
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1039
1
C1038
10UF
20%
6.3V
2
CER-X6S
0402
1
C1053
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1025
1
C1024
10UF
20%
6.3V
2
CER-X6S
0402
1
C1039
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1055
1
C1054
10UF
20%
6.3V
2
CER-X6S
0402
77D2 75B4 8C4
77D2 75A4 64D1 8C4
PP1V05_S0_CPU_VCCPLL
C10C2
X6S-CERM
75A3 8C4
PP1V1_S0SW
C10C4
X6S-CERM
1UF
20%
6.3V
0201
1UF
20%
6.3V
0201
PP1V8_S0SW
CRITICAL
1
C10C0
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
CRITICAL
1
C10C1
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
CRITICAL
1
C10CA
22UF
20%
10V
2
X5R
0402
NOSTUFF
1
2
1
C10C3
1UF
20%
6.3V
2
X6S-CERM
0201
C
NOSTUFF
1
2
1
C10C5
1UF
20%
6.3V
2
X6S-CERM
0201
B
1
2
1
3 2
C1055
10UF
20%
6.3V
CER-X6S
0402
CRITICAL
C1060
180UF
20%
2.5V
POLY-AL
SM
MIRROR_WITH=C1057
1
2
1
3 2
NOSTUFF
C1057
10UF
20%
6.3V
CER-X6S
0402
C1061
180UF
20%
2.5V
POLY-AL
SM
NOSTUFF
1
C1056
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1059
1
2
CRITICAL
NOSTUFF
C1058
10UF
20%
6.3V
CER-X6S
0402
3 2
NOSTUFF
1
C1059
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C1062
180UF
20%
2.5V
POLY-AL
SM
1
3 2
CRITICAL
C1063
180UF
20%
2.5V
POLY-AL
SM
77D2 75A3 8C7
77D2 75B4 64A2 54B3 31B6 16C7 13D8 8C7 8A5 6D6
PP1V05_S0SW_VCCSTG
1UF
20%
6.3V
0201
1
2
C10C6
X6S-CERM
PP1V05_S0_CPU_VCCST
1UF
20%
6.3V
0201
1
2
C10C8
X6S-CERM
NOSTUFF
1
C10C7
1UF
20%
6.3V
2
X6S-CERM
0201
NOSTUFF
1
C10C9
1UF
20%
6.3V
2
X6S-CERM
0201
B
A
8
SYNC_MASTER=myEE SYNC_DATE=03/01/2019
PAGE TITLE
A
CPU Core Decoupling
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
10 OF 150
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1
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D
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3 245
1
D
77D2 11A5 8B1
77D2 11A5 8B1
77D2 75A4 8B4
PP1V24_S5_PCH_VCCDPHY
BYPASS=U0500.DG16:DE16:3MM
PP0V85_LDOSTD
BYPASS=U0500.DG27:DE27:2.54MM
PP1V05_PRIM_OUT_PCH
BYPASS=U0500.CP37:CM37:3MM
C1305
2.2UF
20%
4V
X6S-CERM
0201
1
C1224
4.7UF
20%
6.3V
2
X6S
0402
1
2
1
C1201
1UF
20%
6.3V
2
X6S-CERM
0201
PPVCCIN_AUX_PCH_PRIM
75B3
MIRROR_WITH=C1261
1
C1260
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1267
1
C1266
10UF
20%
6.3V
2
CER-X6S
0402
PLACE_SIDE=TOP
1
C1290
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1261
10UF
20%
6.3V
2
CER-X6S
0402
1
C1267
10UF
20%
6.3V
2
CER-X6S
0402
PLACE_SIDE=TOP
1
C1291
1UF
20%
6.3V
2
X6S-CERM
0201
MIRROR_WITH=C1263
1
C1262
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1269
1
C1268
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
PLACE_SIDE=TOP
1
C1292
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1263
10UF
20%
6.3V
2
CER-X6S
0402
1
C1269
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
PLACE_SIDE=TOP
1
2
C1293
1UF
20%
6.3V
X6S-CERM
0201
MIRROR_WITH=C1265
1
C1264
10UF
20%
6.3V
2
CER-X6S
0402
MIRROR_WITH=C1271
1
C1270
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
PLACE_SIDE=TOP
1
C1294
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1265
10UF
20%
6.3V
2
CER-X6S
0402
1
C1271
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
PLACE_SIDE=TOP
1
C1295
1UF
20%
6.3V
2
X6S-CERM
0201
MIRROR_WITH=C1273
1
C1272
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
PLACE_SIDE=TOP
1
C1296
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1273
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
PLACE_SIDE=TOP
1
C1297
1UF
20%
6.3V
2
X6S-CERM
0201
MIRROR_WITH=C1275
1
C1274
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
PLACE_SIDE=TOP
1
C1298
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1275
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
PLACE_SIDE=TOP
1
C1299
1UF
20%
6.3V
2
X6S-CERM
0201
MIRROR_WITH=C1277
1
C1276
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
1
C1277
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
D
C
79A6 75C1 8B4
77D2 11A5 8A4
74B2 8A4
PP1V8_S5
PP1V05_S5_PCH_VCCDSW
BYPASS=U0500.DG32:DE32:3MM
PP3V3_S5
BYPASS=U0500.DB28:DE30:3MM
1
C1206
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1232
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1221
1UF
20%
6.3V
2
X6S-CERM
0201
BYPASS=U0500.DD18:DE18:3MM
75B1
PLACE_SIDE=TOP
1
C1280
1UF
20%
6.3V
2
X6S-CERM
0201
1
2
PLACE_SIDE=TOP
PLACE_SIDE=TOP
C1281
1UF
20%
6.3V
X6S-CERM
0201
1
2
PP1V8_S5
PLACE_NEAR=U0500.CJ11:12.7mm
C1282
1UF
20%
6.3V
X6S-CERM
0201
PLACE_SIDE=TOP
1
C1283
1UF
20%
6.3V
2
X6S-CERM
0201
1
2
0.6UH-20%-2.8A-0.02OHM
PLACE_SIDE=TOP
PLACE_SIDE=TOP
C1284
1UF
20%
6.3V
X6S-CERM
0201
1
2
NOSTUFF
L1250
21
XFL4012-SM
R1250
0.01
1%
1/3
MF
0402
21
PP1V8_PCH_CLKLDO_R
C1285
1UF
20%
6.3V
X6S-CERM
0201
R1251
VOLTAGE=1.8V
0.0025
1%
1/3W
MF
0402
C
PP1V8_PCH_CLKLDO
1
2
77D2 11B5 8B1
B
74C2 8B1
74B2 15B4 8B4
77D2 16C2 11A5 8C7
PP3V_G3H_RTC
BYPASS=U0500.DH38:DE38:3MM BYPASS=U0500.DG38:DE38:3MM
PP3V3_S5
BYPASS=U0500.DA28:CY29:3MM BYPASS=U0500.DB25:DE24:3MM
PP1V05_VCCSTG_OUT
BYPASS=U0500.J31:K31:3MM
1
C1227
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1207
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1233
1UF
20%
6.3V
2
X6S-CERM
0201
1
C1228
0.1UF
10%
10V
2
X6S-CERM
0201
1
C1208
0.1UF
10%
10V
2
X6S-CERM
0201
NOSTUFF
1
C1234
1UF
20%
6.3V
2
X6S-CERM
0201
BYPASS=U0500.G31:F31:3MM
77D2 11C3 8B1
77D2 11D8 8B1
77D2 16C2 11B8 8C7
Aliases for Bypass Pins
PP1V8_PCH_CLKLDO
PP1V24_S5_PCH_VCCDPHY
PP1V05_VCCSTG_OUT
4V
X6S
1
2
C1250
22UF
0603-3
BYPASS=U0500.CJ11::12.7mm
BYPASS=U0500.CJ11::12.7mm
1
20% 20%
4V
2
X6S
C1251
22UF
0603-3
PP1V8_PCH_CLKLDO
MIN_LINE_WIDTH=0.4500
MIN_NECK_WIDTH=0.0750
VOLTAGE=1.8V
MAKE_BASE=TRUE
PP1V24_S5_PCH_VCCDPHY
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0900
VOLTAGE=1.24V
MAKE_BASE=TRUE
PP1V05_VCCSTG_OUT
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0900
VOLTAGE=1.05V
MAKE_BASE=TRUE
1
C1252
1UF
20%
6.3V
2
X6S-CERM
0201
B
A
8
77D2 11C8 8A4
77D2 11D8 8B1
PP1V05_S5_PCH_VCCDSW
PP0V85_LDOSTD
PP1V05_S5_PCH_VCCDSW
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0900
VOLTAGE=1.05V
MAKE_BASE=TRUE
PP0V85_LDOSTD
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0900
VOLTAGE=0.85V
MAKE_BASE=TRUE
PAGE TITLE
A
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
PCH Decoupling
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
12 OF 150
SHEET
11 OF 109
1
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D
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OMIT_TABLE
3 245
1
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 5 OF 20
D
12A6 20C3
IN OUT
12A6 20D5
OUT
12A6 20D5
OUT
12A6 20C3
IN
12A6 19C3 77D4
IN
12A6 19C3 77D4
OUT
PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L
PCH_UART_DEBUG_D2R_1
PCH_UART_DEBUG_R2D_1
DJ37
DH37
DF39
DE39
DF37
DE37
GPP_D8/UART0A_RXD
GPP_D9/UART0A_TXD
GPP_D10/UART0A_RTS*
GPP_D11/UART0A_CTS*
GPP_B17/UART2A_RXD
GPP_B18/UART2A_TXD
OMIT_TABLE
SMBUS,SMLINK
UART
ESPI
GPP_A7/SMBCLK
GPP_A8/SMBDATA
GPP_A9/SMBALERT*
GPP_E9/SML0CLK
GPP_E10/SML0DATA
GPP_A0/ESPI_IO0
GPP_A1/ESPI_IO1
GPP_A2/ESPI_IO2
GPP_A3/ESPI_IO3
GPP_A4/ESPI_CS*
GPP_A5/ESPI_CLK
GPP_A6/ESPI_RESET*
CM43
CM47
CN45
DE28
DF28
CU40
CU38
CP40
CU41
CP41
CT40
CT41
SMBUS_PCH_CLK
SMBUS_PCH_DATA
NC_PCH_GPP_A9
PCH_I2C_UPC_SCL
PCH_I2C_UPC_SDA
ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L
ESPI_CLK60M_R
ESPI_RESET_L
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
15C6 36D8
15C6 36D8
15B6 36B6
15B6 36B6
24A7 24B6
24A7 24B6
24A7 24B6
24A7 24B6
24A7 24B6
24B6
D
22
21
R1327
2015% 1/20W MF
ESPI_CLK60M
OUT
24B6
C
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 6 OF 19
21B3 21C1
OUT
17D2 17D6 21C3
OUT
17D6 24D6 80A7
OUT
19D3 36B3 36B6
BI
12A6 23D6
IN
12A6 19C3
PCH_BT_ROM_BOOT_L
NC_TP_PCH_GPP_A11
76C3
NC_TP_PCH_GPP_A19
76C3
PCH_WLAN_PERST_L
SOC_PERST_L
PCH_UPC_I2C_INT_L
JTAG_ISP_TCK
12A6 19C3
JTAG_ISP_TDI
12A6 19C3
PCH_SOC_SYNC
NC_TP_PCH_GPP_C8
76C3
NC_TP_PCH_GPP_C9
76D3
NC_TP_PCH_GPP_C10
76C3
PCH_BBR_FORCE_PWR
OUT
JTAG_TBT_W_TMS
12B6 19C3
JTAG_TBT_R_TMS
12B6 19C3
NC_TP_PCH_GPP_D19
76D3
NC_TP_PCH_GPP_D20
76D3
XDP_PCH_STRP_GPP_E0
12A6 15B8
XDP_PCH_STRP_CNV_DISABLE
12B6 15B8
XDP_MEM_OK
12A6 15B8
XDP_PCH_STRP_SPIROM_SAF
12A6 15B8
XDP_PCH_OBSDATA_B0
15B8
XDP_PCH_OBSDATA_B1
15B8
XDP_PCH_OBSDATA_B2
12A6 15B8
CU43
CU44
CR46
CH44
CH45
CA41
DC42
DB41
DG41
DH41
DE42
DF44
DG44
DA40
DA41
DA38
DB38
DF34
DE31
DE34
DG30
DH31
DH28
DJ31
GPP_A10/CPU_GP0
GPP_A11/CPU_GP1
GPP_A19/PCHHOT*
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_B11/PMCALERT*
GPP_C1
GPP_C2
GPP_C7
GPP_C8
GPP_C9
GPP_C10
GPP_C13
GPP_D17
GPP_D18
GPP_D19
GPP_D20
GPP_E0
GPP_E1
GPP_E2
GPP_E3
GPP_E4
GPP_E5
GPP_E6
GPP_G0
GPP_G7
GPP_G6
GPP_G2
GPP_G3
GPP_G4
GPP_G5
GPP_H3
GPP_H4
GPP_H5
GPP_H8
GPP_H18
GPP_H19
GPP_H21
GPP_H22
GPP_R5
GPP_R6
GPD2/LAN_WAKE*
GPD7
CB46
CF45
CE47
CB47
CE43
CE44
CE46
CV44
CV45
CY46
CY47
CY43
CY44
DA36
DB35
DB40
CW41
CF38
CL40
MLB_RAMCFG0
JTAG_TBT_T_TMS
JTAG_TBT_X_TMS
MLB_RAMCFG1
MLB_RAMCFG2
MLB_RAMCFG3
MLB_RAMCFG4
TBT_POC_RESET
JTAG_ISP_TDO
NC_TP_PCH_GPP_H5
DP_INT_HPD_MASK
NC_TP_PCH_GPP_H18
NC_TP_PCH_GPP_H19
NC_TP_PCH_GPP_H21
NC_TP_PCH_GPP_H22
NC_TP_PCH_GPP_R5
NC_TP_PCH_GPP_R6
PCH_LAN_WAKE_L
PCH_STRP_GPD7
12A5
12B6 19C3
12B6 19C3
12A5
12A5
12A5
12A5
12A6 19C3
OUT
12B6 19C3
76D3
32A6 32C3
IN
76D3
76D3
76D3
76D3
76D3
76D3
12A6
12A6 19C3
C
B
PP3V3_S5
R1355
R1356
R1357
R1358
R1359
R1376
R1351
10K
10K
10K
10K
10K
100K
100K
74B2 14A7 13A7 5B7
21
5% 201
21
21
21
21
21
21
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
JTAG_TBT_X_TMS
JTAG_TBT_T_TMS
JTAG_TBT_W_TMS
JTAG_TBT_R_TMS
JTAG_ISP_TDO
XDP_PCH_STRP_CNV_DISABLE
PCH_LAN_WAKE_L
12C2 19C3
12C2 19C3
12C5 19C3
12C5 19C3
12C2 19C3
12C5 15B8
12C2
XDP_PCH_OBSDATA_B3
15B8
XDP_PCH_OBSFN_C0
15A8
FIVR_DIGPB_1
15A6
NC_TP_PCH_GPP_E20
76D3
NC_TP_PCH_GPP_E21
76D3
NC_TP_PCH_GPP_E22
76D3
NC_TP_PCH_GPP_E23
76D3
DJ28
DH30
DF31
DJ25
DH24
DH25
DG24
GPP_E7
GPP_E8
GPP_E19/PCIE_LNK_DOWN
GPP_E20
GPP_E21
GPP_E22
GPP_E23
MEMORY CONFIGURATION STRAPS.
B
A
NOSTUFF
NOSTUFF
PP1V8_S5
R1352
R1353
R1362
R1363
R1364
R1365
R1367
R1377
R1371
R1370
R1368
R1369
R1360
R1361
R1374
R1375
47K
47K
47K
47K
47K
47K
1K
100K
100K
100K
100K
100K
100K
100K
100K
100K
21
5% 201
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
1/20W MF
5% 2011/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
75B1 24A8 17B7 14A7
PCH_UART_DEBUG_D2R_1
PCH_UART_DEBUG_R2D_1
PCH_UART_BT_D2R
PCH_UART_BT_R2D
PCH_UART_BT_RTS_L
PCH_UART_BT_CTS_L
XDP_PCH_STRP_SPIROM_SAF
XDP_PCH_OBSDATA_B2
PCH_STRP_GPD7
XDP_MEM_OK
XDP_PCH_STRP_GPP_E0
PCH_BBR_FORCE_PWR
JTAG_ISP_TCK
JTAG_ISP_TDI
PCH_SOC_SYNC
TBT_POC_RESET
12D5 20C3
12D5 20D5
12D5 20D5
12D5 20C3
12B5 15B8
12B5 15B8
12C2 19C3
12B5 15B8
12C5 15B8
12C5 19C3
12C5 19C3
12C5 19C3
12C5 23D6
12C2 19C3
77D4 19C3 12D5
77D4 19C3 12D5
MLB_RAMCFG0
12C2
MLB_RAMCFG1
12C2
MLB_RAMCFG2
12C2
MLB_RAMCFG3
12C2
MLB_RAMCFG4
12C2
BOM GROUP BOM OPTIONS
PCH INTERNAL PULL-UPS ARE TO 1.8V.
RAMCFG4_L
1
R1334
1K
5%
1/20W
MF
201
2
RAMCFG3_L
1
R1333
1K
5%
1/20W
MF
201
2
RAMCFG2_L
1
R1332
1K
5%
1/20W
MF
201
2
RAMCFG4_L,RAMCFG3_L,RAMCFG2_L,RAMCFG1_L,RAMCFG0_LRAMCFG_SLOT
RAMCFG1_L
1
R1331
1K
5%
1/20W
MF
201
2
RAMCFG0_L
1
R1330
1K
5%
1/20W
MF
201
2
PAGE TITLE
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
IV ALL RIGHTS RESERVED
DESIGN: X502/MLB
LAST CHANGE: Tue Feb 2 13:18:21 2016
PCH SPI/SMB/UART/GPIO
DRAWING NUMBER
051-05198
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
REVISION
BRANCH
PAGE
13 OF 150
SHEET
12 OF 109
6.0.0
evt-3
SIZE
D
A
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
8
67
35 4
2
1
D
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QQ微信：181806465
77D2 75B4 64A2 54B3 31B6 16C7 10B3 8C7 8A5 6D6
16B5
IN
PP1V05_S0_CPU_VCCST
NOSTUFF
R1410
VCCST_PWRGD
VCCST_PWRGD 1V TOLERANT
1K
5%
1/20W
MF
201
678
3 245
1
U0500
ICL-UN
15C1 31C1 77C2
IN
PLACE_NEAR=U0500.CN10:5mm
NOSTUFF
1
C1400
100PF
2
PLACE_NEAR=U0500.BJ2:38mm
5%
25V
C0G
0201
1
2
31B6 77C2
13A6 17A4 17B4
OUT
17D8 20C5 20D5
15C8 16B7 17B8 17C6
IN
19C3 77C2
R1406
1%
60.4
201
64A5
OUT
R1409
100K
21
MF 1/20W
1
5%
1/20W
MF
201
2
R1408
0201
PLACE_NEAR=U0500.CN2:15mm
0
MF
21
5%
1/20W
31C1 77C2
16A5 17B8
77C2
16A2
TP_DSWLDO_MON
PLT_RST_L
PM_SYSRST_L
PM_RSMRST_L
TP_CPU_PWRGD
VCCST_PWRGD_R
VCCST_OVERRIDE
VCCSTPWRGOOD_TCSS
PM_PCH_SYS_PWROK
IN
PM_PCH_PWROK
IN
PM_PCH_DPWROK
IN
PCIE_WAKE_L
13A6
CA40
CG46
DF42
CA38
CG6
CL1
CN2
CL2
DE44
CF40
CC37
CB44
DSWLDO_MON
GPP_B13/PLTRST*
SYS_RESET*
RSMRST*
PROCPWRGD
VCCST_PWRGD
VCCST_OVERRIDE
VCCSTPWRGOOD_TCSS
SYS_PWROK
PCH_PWROK
DSW_PWROK
WAKE*
ICL-UN-4+2
BGA
SYM 10 OF 19
SYSTEM POWER MANAGEMENT
GPP_H10/CPU_C10_GATE*
GPP_B12/SLP_S0*
GPD4/SLP_S3*
GPD5/SLP_S4*
GPD10/SLP_S5*
SLP_SUS*
GPD3/PWRBTN*
GPD0/BATLOW*
GPP_B2/VRALERT*
CG47
CL41
CH38
CD37
CH37
CU46
CH41
CH40
CC41
PM_SLP_S0_3V3_L
PM_SLP_S3_L_1
PM_SLP_S4_L
PM_SLP_S5_L
PM_SLP_SUS_L
CPU_C10_GATE_L
PCH_PWRBTN_L
PCH_BATLOW_L
PCH_WLAN_DEV_WAKE
13A6 16B4
OUT
13A6 16A7 16B7 19B5 62D6 64A6 64B5 64C3 77C2 81C3
OUT
13A6 81C3
OUT
13A6 81C3
OUT
13A6 16B7 17C8 59C7
OUT
13A6 16C4 64B4
OUT
13A6 15C8 62C6 77C2
IN
13A6
21B6
OUT
D
C
C
B
R1451
R1452
100K
10K
PP3V3_S5
21
21
1/20W MF
5% 1/20W 201MF
74B2 14A7 12B7 5B7
PCH_BATLOW_L
2015%
PCIE_WAKE_L
B
13C3
13C6
NOSTUFF
A
R1463
R1447
R1448
R1460
R1454
R1455
R1456
R1457
R1458
8
1K
100K
100K
100K
100K
100K
100K
100K
100K
21
5% 1/20W
21
5%
21
5% 1/20W MF
21
21
21
21
21
21
PCH_PWRBTN_L
201MF
CPU_C10_GATE_L
201MF1/20W
201
13D3 15C8 62C6 77C2
13D3 16C4 64B4
DESIGN: X502/MLB
MF1/20W 2015%
PM_SLP_S5_L
PLT_RST_L
MF1/20W
MF1/20W
MF1/20W
MF1/20W
MF1/20W
2015%
PM_SLP_S4_L
2015%
PM_SLP_S3_L_1
2015%
PM_SLP_S0_3V3_L
2015%
PM_SLP_SUS_L
2015%
13D6 17A4 17B4 17D8 20C5 20D5 31B6 77C2
13D3 81C3
13D3 81C3
16B4 13D3
13D3 16B7 17C8 59C7
LAST CHANGE: Tue Apr 5 13:08:54 2016
SYNC_MASTER=myEE SYNC_DATE=03/01/2019
PAGE TITLE
81C3 77C2 64C3 64B5 64A6 62D6 19B5 16B7 16A7 13D3
PCH Power Management
DRAWING NUMBER
SIZE
051-05198
Apple Inc.
REVISION
A
D
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=CPU & CHIPSET
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
14 OF 150
SHEET
13 OF 109
1
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C
PCIe Port Assignments:
SOC lane 0
SOC lane 1
SOC lane 2
SOC lane 3
AirPort
EXT A (SS,DCI)
Fixture USB-A
EXT USB-A
PLACE_NEAR=U0500.CE6:12.7mm
100
1%
1/20W
MF
201
1
2
R1504
26D7
26D7
32D8
32D8
26D7
26D7
32D8
32D8
26D7
26D7
32C8
32D8
26D7
26D7
32C8
32C8
21D1
21D1
21C1
21C1
19D3
19D3
19D3
19D3
76B3 78A6
76B3 78A8
76B3 78A6
76B3 78A8
78A6
78A8
78A6
78A8
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
678
PCIE_SOC_D2R_N<0>
PCIE_SOC_D2R_P<0>
PCIE_SOC_R2D_C_N<0>
PCIE_SOC_R2D_C_P<0>
PCIE_SOC_D2R_N<1>
1
PCIE_SOC_D2R_P<1>
PCIE_SOC_R2D_C_N<1>
PCIE_SOC_R2D_C_P<1>
PCIE_SOC_D2R_N<2>
PCIE_SOC_D2R_P<2>
PCIE_SOC_R2D_C_N<2>
PCIE_SOC_R2D_C_P<2>
PCIE_SOC_D2R_N<3>
PCIE_SOC_D2R_P<3>
PCIE_SOC_R2D_C_N<3>
PCIE_SOC_R2D_C_P<3>
PCH_PCIE_WLAN_D2R_N
PCH_PCIE_WLAN_D2R_P
PCH_PCIE_WLAN_R2D_C_N
PCH_PCIE_WLAN_R2D_C_P
USB3_BSSB_D2R_N
USB3_BSSB_D2R_P
USB3_BSSB_R2D_C_N
USB3_BSSB_R2D_C_P
USB3_EXTC_D2R_N
USB3_EXTC_D2R_P
USB3_EXTC_R2D_C_N
USB3_EXTC_R2D_C_P
USB3_EXTD_D2R_N
USB3_EXTD_D2R_P
USB3_EXTD_R2D_C_N
USB3_EXTD_R2D_C_P
PCH_PCIE_RCOMP_N
PCH_PCIE_RCOMP_P
NC
NC
NC
NC
NC
NC
NC
NC
DA1
DA2
CV8
CV9
DB1
DB2
CY8
CY9
CU5
CU4
DA12
DB12
CV4
CV5
DF11
DE11
CY4
CY5
DH10
DG10
DA5
DA4
DJ11
DH11
CV1
CV2
DA9
DA8
CW2
CW1
DC8
DC9
DC5
DC4
DH14
DJ14
DE5
DE4
DF14
DE14
DD2
DC2
OMIT_TABLE
PCIE1_RXN
PCIE1_RXP
PCIE1_TXN
PCIE1_TXP
PCIE2_RXN
PCIE2_RXP
PCIE2_TXN
PCIE2_TXP
PCIE3_RXN
PCIE3_RXP
PCIE3_TXN
PCIE3_TXP
PCIE4_RXN/USB30_3_RXN
PCIE4_RXP/USB30_3_RXP
PCIE4_TXN/USB30_3_TXN
PCIE4_TXP/USB30_3_TXP
PCIE5_RXN/USB30_2_RXN
PCIE5_RXP/USB30_2_RXP
PCIE5_TXN/USB30_2_TXN
PCIE5_TXP/USB30_2_TXP
PCIE6_RXN/USB30_1_RXN
PCIE6_RXP/USB30_1_RXP
PCIE6_TXN/USB30_1_TXN
PCIE6_TXP/USB30_1_TXP
PCIE7_RXN
PCIE7_RXP
PCIE7_TXN
PCIE7_TXP
USB30_4_RXN/PCIE8_RXN
USB30_4_RXP/PCIE8_RXP
USB30_4_TXN/PCIE8_TXN
USB30_4_TXP/PCIE8_TXP
USB31_1_RXN
USB31_1_RXP
USB31_1_TXN
USB31_1_TXP
USB31_2_RXN
USB31_2_RXP
USB31_2_TXN
USB31_2_TXP
PCIE_RCOMPN
PCIE_RCOMPP
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 7 OF 19
USB2
PCIE/USB3/SATA
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
GPP_A12/USB_OC1*
GPP_A13/USB_OC2*
GPP_A14/USB_OC3*
GPP_A18/USB_OC0*
USB2_COMP
USB_ID
USB_VBUSSENSE
DF20
DE20
DH18
DG18
DE23
DF23
DJ17
DH17
DJ23
DH23
DF17
DE17
CR44
CN44
CR47
CR43
DJ20
DH21
DG21
USB2_TBT_X_N
USB2_TBT_X_P
USB2_TBT_T_N
USB2_TBT_T_P
USB2_TBT_W_N
USB2_TBT_W_P
USB2_TBT_R_N
USB2_TBT_R_P
USB_FIXT1_N
USB_FIXT1_P
USB_FIXT2_N
USB_FIXT2_P
XDP_USB_EXTD_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTA_OC_L
PCH_USB2_COMP
PCH_USB2_VBUSSENSE
3 245
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
14A6
14A6 15B1
14A6
14A6
19D5
19D5
19C5
19C5
19B5
19B5
19B5
19B5
76B3 78A6
76B3 78A8
76B3 78A6
76B3 78A8
X RP
T RP
W RP
R RP
TP for Fixture
TP for Fixture
GROUNDED PER CFL EDS.
1
R1581
10K
5%
1/20W
MF
201
2
1
R1501
113
1%
1/20W
MF
201
2
PLACE_NEAR=U0500.DJ20:12.7MM
1
D
C
B
A
NOSTUFF
NOSTUFF
NOSTUFF
R1550
R1551
R1552
R1553
R1533
R1534
R1535
R1520
100K
100K
100K
100K
47K
47K
60.4
PP3V3_S5
21
5% 201
21
21
21
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
PP1V8_S5
21
5% 201
1/20W MF
21
21
21
PLACE_NEAR=U0500.DF9:25.4mm
1/20W MF
1% 201
1/20W MF
ANY CLKREQ CAN MAP TO ANY CLK.
ANY CLKREQ OR CLK CAN MAP TO ANY PCIE PORT.
UNUSED CLKREQS AND CLKS SHOULD BE DISABLED.
PER SKYLAKE PDG, SKYLAKE PCH EDS.
74B2 13A7 12B7 5B7
XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L
75B1 24A8 17B7 12A7
SOC_CLKREQ_BUF_L
PCH_WLAN_CLKREQ_L
2015%
PCH_STRP_NO_REBOOT
2015%1K1/20W MF
PCH_DIFFCLK_BIASREF
14C3
14C3
14C3 15B1
14D3
14A6 15A2 17B5
14A6 17C8
14A6
14A3
B
OMIT_TABLE
U0500
ICL-UN
ICL-UN-4+2
BGA
SYM 9 OF 19
CLOCK SIGNALS
NC_PCIE_CLK100M0P
NC_PCIE_CLK100M0N
NC_DEBUG_CLKREQ_L
21D3 78D8
OUT
21D3 78D8
OUT
14A6 17C8
IN
PCH_PCIE_CLK100M_WLAN_P
PCH_PCIE_CLK100M_WLAN_N
PCH_WLAN_CLKREQ_L
NC_PCIE_CLK100M2P
NC_PCIE_CLK100M2N
PCH_STRP_NO_REBOOT
14A6
NC_PCIE_CLK100M3P
NC_PCIE_CLK100M3N
NC_ENETSD_CLKREQ_L
NC_PCIE_CLK100M4P
NC_PCIE_CLK100M4N
NC_GPU_CLKREQ_L
26C6 78D8
OUT
26C6 78D8
OUT
14A6 15A2 17B5
IN
PCIE_CLK100M_SOC_P
PCIE_CLK100M_SOC_N
SOC_CLKREQ_BUF_L
GPP_B10 PU is on XDP page
CR4
CR5
CM46
CH5
CH6
CK46
CM6
CM5
CK47
CK5
CK4
CK43
CG5
CG4
CK44
CN5
CN4
CM44
CLKOUT_PCIE_P0
CLKOUT_PCIE_N0
GPP_B5/SRCCLKREQ0*
CLKOUT_PCIE_P1
CLKOUT_PCIE_N1
GPP_B6/SRCCLKREQ1*
CLKOUT_PCIE_P2
CLKOUT_PCIE_N2
GPP_B7/SRCCLKREQ2*
CLKOUT_PCIE_P3
CLKOUT_PCIE_N3
GPP_B8/SRCCLKREQ3*
CLKOUT_PCIE_P4
CLKOUT_PCIE_N4
GPP_B9/SRCCLKREQ4*
CLKOUT_PCIE_P5
CLKOUT_PCIE_N5
GPP_B10/SRCCLKREQ5*
XTAL_IN
XTAL_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST*
RTCRST*
DH6
DF6
DF9
DB46
DB44
CC38
CC40
NC
PCH_CLK38M4_XTALIN
PCH_CLK38M4_XTALOUT
PCH_DIFFCLK_BIASREF
PMU_CLK32K_PCH_1V0
PCH_RTC_RESET_L
PCH_RTC_RESET_L
14A6
OUT
IN
IN
IN
16C8
16D8
17D3
77C2
17D2
62C3
R1573
100K
1%
1/20W
MF
201
1
R1572
127K
1%
1/20W
MF
201
2
21
BOM_COST_GROUP=CPU & CHIPSET
PMU_CLK32K_PCH
PLACE_NEAR=U0500.DB46:5MM
PLACE_NEAR=U0500.DB46:5MM
IN
62D7
SYNC_MASTER=myEE SYNC_DATE=03/01/2019
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DESIGN: X502/MLB
LAST CHANGE: Thu Jun 18 20:05:18 2015
PCH PCIE/USB/CLKS
DRAWING NUMBER
051-05198
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
REVISION
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Primary / Merged (CPU/PCH) Micro2-XDP
D
C
XDP:YES
13D6 16B7 17B8 17C6 19C3
77C2
IN
PM_RSMRST_L
PLACE_NEAR=U0500.CA38:18MM
R1800
1K
XDP:YES
13A6 13D3 62C6 77C2
PCH_PWRBTN_L
OUT
PLACE_NEAR=U0500.CH41:8MM MF1/20W 2015%
R1802
DEBUG:STUFF R1840 TO DELIBERATELY STALL AFTER RESET
CPU_CFG<0>
6B7 6C5 15D6
R1841
10
75A2 6B7
1K
PPVCCIO_OUT
R1840
1K
5%
1/20W
MF
201
Hook3 Components do not have XDP BOMOPTION
because they serve as CLKREQ_L PU
15A4
6D2 15D2
6D2
OUT
OUT
OUT
SOC_CLKREQ_BUF_L
XDP_CPU_TCK
PCH_JTAGX
NOSTUFF
21
75B1 15B4 15B3
R1870
R1835
1K
0
PP1V8_S5
NO_XNET_CONNECTION
XDP:YES
21
21
21
MF1/20W 2015%
XDP:YES
150
5%
1/20W
MF
201
MF1/20W 2015%
MF1/20W
1
NO_XNET_CONNECTION
2
MF1/20W 2015%
0201
R1872
21
1K
5%
1/20W
MF
201
1
2
R1871
21
5%
PLACE_NEAR=J1800.58:28MM
6D5
6D5
6B7 6C5 15C8
6B7 6C5
6C5
6C5
6A7 6D5 77D3
6A7 6D5
6A8 6B5
6B5
6B5
6B5
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PLACE_NEAR=U0500.K5:2.54MM
XDP_PRESENT_CPU_L
15B4
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_BPM_L<0>
CPU_BPM_L<1>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
XDP_PM_RSMRST_L
XDP_CPU_PWRBTN_L
XDP_HOOK2
XDP_HOOK3
SMBUS_PCH_DATA
12D2 36D8
SMBUS_PCH_CLK
12D2 36D8
6D2 15D2
XDP_PCH_TCK
OUT
NOSTUFF
R1801
1K
5%
1/20W
MF
NO_XNET_CONNECTION
201
XDP:YES
C1804
0.1UF
X5R-CERM
0201
PLACE_NEAR=J1800.42:28MM PLACE_NEAR=J1800.47:28MM
1
2
10%
10V
PP1V05_PCH_OUT_FET
75B3
SKL/KBL/CFL
PULL CFG<3> LOW
WHEN XDP PRESENT
1
2
XDP_PIN_1
OBSFN_A0
OBSFN_A1
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_A3
OBSFN_B0
OBSFN_B1
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
SDA
SCL
TCK1
TCK0
XDP:YES
C1800
0.1UF
10%
10V
X5R-CERM
0201
PLACE_NEAR=J1800.44:28MM
NOTE: This is not the standard XDP pinout.
PP1V05_VCCSTG_OUT_LGC
6D7 8B7
XDP_CONN:YES
Use with 921-0133 Adapter Flex to
support chipset debug.
J1800
0
0
NOSTUFF
21
XDP:YES
21
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
5%
6B5
6B5
6B5 6B7
6B5 6B7
6B5 6B7
6B5
6B5
6B5
6B5 6B7
6B5 6B7
6B5
6B5
MF1/20W 0201
0201MF1/20W5%
ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.
R1821
PLACE_NEAR=J1800.51:2.54MM
R1822
PLACE_NEAR=J1800.53:2.54MM
R1823
PLACE_NEAR=J1800.55:2.54MM
R1824
PLACE_NEAR=J1800.57:2.54MM
1
R1830
1K
5%
1/20W
MF
201
2
IN
0
0
0
0
XDP_PCH_TDO
6D2 15B1
XDP_PCH_TDI
6D2 15B1
XDP_PCH_TMS
6D2 15B1
XDP_CPU_TDO
6D2 15C1
XDP_CPU_TCK
6D2 15C8
XDP_PCH_TCK
6D2 15C6
PLACE_NEAR=J1800.45:28MM
6B5
21
XDP:YES
XDP:YES
5%
21
21
5% 1/20W
21
5%
XDP:YES
XDP:YES
PLACE_NEAR=U0500.V5:28MM MF1/20W 2015%
R1890
100
XDP:YES
PLACE_NEAR=U0500.Y5:28MM MF1/20W 2015%
R1891
51
XDP:YES
PLACE_NEAR=U0500.T5:28MM MF1/20W 2015%
R1892
51
XDP:YES
PLACE_NEAR=U0500.V6:28MM MF1/20W 2015%
R1810
100
XDP:YES
PLACE_NEAR=U0500.AC8:28MM MF1/20W 2015%
R1813
51
NOSTUFF
PLACE_NEAR=U0500.AA8:28MM MF1/20W 2015%
R1897
51
XDP:YES
R1806
0
21
PM_SYSRST_L
5%
1/20W
MF
0201
XDP_CPU_TDO
0201MF1/20W
XDP_CPU_TRST_L
0201MF5% 1/20W
XDP_CPU_TDI
MF
0201
XDP_CPU_TMS
MF1/20W
0201
OUT
OUT
OUT
IN
6D2 15D2
6D2
6D2
6D2
21
12
D
12
21
12
12
13D6 31C1 77C2
BI
C
DF40RC-60DP-0.4V
1
2
M-ST-SM1
62
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
42 41
44 43
46 45
48 47
50 49
52 51
54 53
56 55
58 57
60 59
64 63
61
518S0847
PPVCCIO_OUT
75A2
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP:YES
1
C1801
0.1UF
10%
10V
2
X5R-CERM
0201
PLACE_NEAR=J1800.43:28MM
NC
NC
CPU_CFG<17>
CPU_CFG<16>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<19>
CPU_CFG<18>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
VOLTAGE=1.05V
PPVCC_OBS_CD
ITP_PMODE
XDP_DBRESET_L
XDP:YES
1
C1806
0.1UF
10%
10V
2
X5R-CERM
0201
R1860
R1861
B
12A6 12C5
12B6 12C5
12A6 12B5
12A6 12B5
12B5
12B5
12A6 12B5
12B5
12B5
BI
BI
BI
BI
BI
BI
BI
BI
BI
PCH XDP Signals
These signals do not connect to the Primary (Merged) XDP connector in this architecture.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation.
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.
PCH/XDP Signals
XDP_PCH_STRP_GPP_E0
XDP_PCH_STRP_CNV_DISABLE
XDP_MEM_OK
XDP_PCH_STRP_SPIROM_SAF
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_B1
XDP_PCH_OBSDATA_B2
XDP_PCH_OBSDATA_B3
XDP_PCH_OBSFN_C0
OBSDATA_A0
OBSDATA_A1
OBSDATA_A2
OBSDATA_B0
OBSDATA_B1
OBSDATA_B2
OBSDATA_B3
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
TP1840
TP1841
TP1842
TP1843
TP1868
TP1869
TP1870
TP1871
TP1867
12D2 36B6
BI
12D2 36B6
BI
5A6 5B3 19B5
BI
5B3 19B5
BI
5B6 5C3 19D5
BI
5C3 19D5
BI
5B6 5C3 19C5
BI
5B3 19C5
BI
5A6 5B3 19C5
BI
PCH_I2C_UPC_SCL
PCH_I2C_UPC_SDA
LSX_HSR_R2P
LSX_HSR_P2R
LSX_HSX_R2P
LSX_HSX_P2R
LSX_HST_R2P
LSX_HST_P2R
LSX_HSW_R2P
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3OBSDATA_A3
OBSDATA_C4
OBSDATA_C5
OBSDATA_C6
OBSDATA_C7
OBSFN_C1OBSFN_C0
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
TP1844
TP1845
TP1846
TP1847
TP1848
TP1849
TP1850
TP1851
TP1852
75B1 15C7 15B3
PP1V8_S5
74B2 11B8 8B4
15D6
XDP_PRESENT_CPU_L
NOSTUFF
R1850
100K
1/20W
201
PP3V3_S5
1
5%
MF
2
NO_XNET_CONNECTION
XDP:YES
R1876
10K
5%
1/20W
MF
201
XDP_PRESENT1_L
1
XDP:YES
2
R1874
MF
0201
0
21
1/20W
5%
Per Intel comments
POD_PRESENT2_N going to logic control
R1873
NEED TO CONNECT TO VCCST, *STG POWER LOGIC
75B1 15C7 15B4
XDP_PRESENT2_L
PP1V8_S5
XDP:YES
21
1K
2
1
XDP:YES
6
VCC
U1870
74AUP1G07GF
SOT891
GND
3
MF1/20W 2015%
XDP:YES
C1870
X5R-CERM
4
YA
5
NCNC
XDP_PCH_TDO
XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS
XDP_USB_EXTC_OC_L
1
0.1UF
10%
10V
2
0201
XDP_PRESENT_L
NCNC
R1875
100K
5%
1/20W
MF
201
6D2 15D2
IN
6D2
OUT
6D2 15D2
OUT
6D2 15D2
OUT
14A6 14C3
OUT
B
1
2
24C6 64A5
OUT
A
Other Debug Signals
6B3
BI
6B3
BI
6C3 6B5
BI
6B3
BI
6B3
BI
6B3
BI
6B3
BI
6B3
BI
6B3
BI
6C3
BI
6B3
BI
5A6
BI
PEG_VIEW_2
PEG_VIEW_3
DDR_VIEW_0 FIVR_PROBE_DIG_0
DDR_VIEW_1
FIVR_VLOAD_CORE0
FIVR_VLOAD_CORE1
FIVR_VLOAD_CORE2
FIVR_VLOAD_CORE3
FIVR_VLOAD_CCF
FIVR_VLOAD_SA
FIVR_VLOAD_TCSS
FIVR_VLOAD_GTM
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
TP1872
TP1878
TP1879
TP1880
TP1881
TP1882
TP1883
TP1884
TP1885
TP1886
TP1887
TP1888
6B5
6B5
6B5
6B3
6B3
6B3
6A5
6A5
12B5
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
FIVR_PROBE_ANA_0
FIVR_PROBE_ANA_1
FIVR_PROBE_DIG_1
FIVR_VLOAD_1P05
FIVR_VLOAD_VCCIO
FIVR_VLOAD_VNN
FIVR_ANAPB0
FIVR_ANAPB1
FIVR_DIGPB_1
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
1
TP
TP-P6
TP1889
TP1890
TP1891
TP1892
TP1893
TP1894
TP1895
TP1896
TP1897
TP1898
SOC_CLKREQ_BUF_L
15C8
Per Intel comments HOOK3
HOOK3 connected to GPP_B10
SOC_CLKREQ_BUF_L
MAKE_BASE=TRUE
14A6 17B5
BOM_COST_GROUP=DEBUG
SYNC_MASTER=myEE SYNC_DATE=03/01/2019
PAGE TITLE
CPU/PCH Merged XDP
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
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18 OF 150
SHEET
15 OF 109
A
8
67
35 4
2
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1
VCCIN_AUX DISCHARGE
Ensure VCCIN_AUX decays below 200mV within 100ms (PDG requirement tPCH35)
D
14A3
14A3
PCH_CLK38M4_XTALOUT
IN
PCH_CLK38M4_XTALIN
OUT
PLACE_NEAR=U0500.DF6:2MM
200K
1%
1/20W
MF
201
1
2
R1901
38.4MHZ CRYSTAL
R1900
0
21
5%
1/20W
MF
0201
R1902
0
21
5%
1/20W
MF
0201
PCH_CLK38M4_XTALOUT_R
38.4MHZ-10PPM-8PF-30OHM
PCH_CLK38M4_XTALIN_R
CRITICAL
Y1900
2.5X2.0-SM
CRITICAL
C1900
5.6PF
+/-0.05PF
C0G-CERM
1
2
4
3
CRITICAL
C1901
5.6PF
+/-0.05PF
C0G-CERM
25V
0201
25V
0201
80D8 79C6 77D2 75B3 40A5 8D4
PP3V3_G3H_RTC
75C4
1
21
R1961
100K
5%
1/20W
MF
201
2
PVCCINAUX_DSCHG_EN
6
D
R1960
0
21
56A6 56C6
IN
21
PVCCINAUX_DSCHG_EN_LVCCINAUX1_EN_R
MF1/20W
02015%
2
G
Q1960
DMN5L06VK-7
S
SOT563
VER-4
1
NOSTUFF
C1960
47PF
5%
25V
C0G
0201
1
2
5
G
PPVCCIN_AUX_PCH_PRIM
PVCCINAUX_DSCHG
3
D
Q1960
DMN5L06VK-7
S
SOT563
VER-4
4
1
R1962
47
5%
1/16W
MF-LF
402
2
D
VCCSTG_OUT DISCHARGE
C
B
Ensure VCCSTG_OUT <= VCCST during power-down (required at all times)
77D2 11B8 11A5 8C7
75B4 64D5
VCCIN VR EN and VCCST_PWRGD Generation
77D2 75B4 64A2 54B3 31B6 13D8 10B3 8C7 8A5 6D6
62A6 62C6 77C2
IN
13A6 13D3 16A7 19B5 62D6 64A6 64B5 64C3 77C2 81C3
IN
ALL_SYS_PWRGD
PM_SLP_S3_L_1
R1910
13D6 15C8 17B8 17C6 19C3 77C2
IN
13A6 13D3 17C8 59C7
IN
PM_RSMRST_L
PM_SLP_SUS_L
0
5%
1/20W
MF
0201
PP1V05_S0_CPU_VCCST
10%
16V
0201
1
2
NC
21
C1910
0.1UF
X5R-CERM
CPUVRENA
NOSTUFF
R1911
0
MF 1/20W
5%
0201
21
6
VCC
1
A Y
2
5
B
NC
AND
GND
3
BYPASS=U1912.6:3:5MMBYPASS=U1910::5mm
U1910
74AUP1G08
X1-DFN1010-6
4
C1912
0.1UF
X5R-CERM
0201
CPUVRENB
10%
16V
NC
13A6 13D3 64B4
IN
1
2
U1912
74AUP1G08
6
X1-DFN1010-6
VCC
1
A Y
2
AND
B
4
CPU_VR_EN
OUT
54B3
64A3
P1V05_VCCST_EN
IN
1/20W
R1912
5
NC
GND
3
0
5%
1/20W
MF
0201
21
VCCST_PWRGD
OUT
13D8
13A6 13D3 24B6 77C2 81A8 81C3
PM_SLP_S0_3V3_L
IN
R1950
0
1/20W5% 0201MF
NOSTUFF
21
R1953
0
2 1
MF5%0201
75B1
PVCCSTG_DSCHG_EN_LCPU_C10_GATE_L
SLP_S0# 1.8V Level Shifter
PP1V8_S5
BYPASS=U1930::5mm
PM_SLP_S0_3V3_L
MAKE_BASE=TRUE
C1930
0.1UF
10%
6.3V
CERM-X5R
0201
2
G
1
2
2
6
D
Q1950
DMN5L06VK-7
S
5
NC
1
NC
SOT563
VER-4
1
U1930
74AUP1G34GX
SOT1226
4
3
PM_SLP_S0_L
1
R1930
100K
5%
1/20W
MF
201
2
PP3V3_G3H
C1950
NOSTUFF
47PF
5%
25V
C0G
0201
1
2
OUT
PP1V05_VCCSTG_OUT
1
R1951
100K
5%
1/20W
MF
201
2
PVCCSTG_DSCHGPVCCSTG_DSCHG_EN
3
D
Q1950
5
G
DMN5L06VK-7
S
SOT563
VER-4
4
NOSTUFF
1
R1952
300
1%
1/20W
MF
201
2
C
B
A
PCH_PWROK Generation
74B2 31C1 17C7
BYPASS=U1915::5mm
13A6 13D3 16B7 19B5 62D6 64A6 64B5 64C3 77C2 81C3 13C6
31C1
PM_SLP_S3_L_1
PM_PCH_PWROK_R
IN
PP3V3_S5
10%
16V
0201
1
2
NC
C1915
0.1UF
X5R-CERM
VCC
1
A Y
2
AND
B
5
NC
GND
U1915
74AUP1G08
6
X1-DFN1010-6
3
R1915
0
5%
MF
0201
21
13C6 17B8 77C2
OUT
32A6
SMC_DPWROK1V8 SMC_DPWROK1V8_RPM_PCH_PWROK
4
PCHPWROK_R PM_PCH_DPWROK
1
R1917
100K
5%
1/20W
MF
201
2
1/20W
R1921
NOSTUFF
PP3V3_S5
74B2
0
5%
1/20W
MF
0201
21
DSW_PWROK 3.3V Level Shifter
BYPASS=U1920::2MM
10%
6.3V
0201
1
2
U1920
74AUP1T97
5
SOT891
1
2
4
6
3
1
R1920
100K
5%
1/20W
MF
201
2
OUTIN
C1920
0.1UF
CERM-X5R
1
R1922
100K
5%
1/20W
MF
201
2
R1916
0
5%
MF
0201
21
BOM_COST_GROUP=CPU & CHIPSET
PM_PCH_PWROK_R
MAKE_BASE=TRUE
1/20W
PAGE TITLE
Chipset Shared Support
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=03/20/2019SYNC_MASTER=J214_DAVID
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
19 OF 150
SHEET
16 OF 109
A
SIZE
D
8
67
35 4
2
1
Platform Reset Connections
www.haojiyoubbs.com
QQ微信：181806465
678
3 245
1
D
PP1V8_S5
75B1
PP3V3_S5
74B2
REMOVED J2001 ESPI ANALYZER CONNECTOR etc
1
C2005
0.1UF
10%
16V
2
X5R-CERM
0201
1
VCCA VCCB
6
U2002
20C5 20D5
13A6 13D6
IN
17A4 17B4
31B6 77C2
PLT_RST_L
R2002
R2001
SLSV1T34AMU-COMBO
NC
2
5
UDFN
NC
GND
3
100K
100K
BA
21
1/20W5%
21
1
2
4
R2003
C2006
0.1UF
10%
16V
X5R-CERM
0201
PLT_RST_3V3_L
1
100K
5%
1/20W
MF
201
2
PCH_WLAN_PERST_L
201MF
SOC_PERST_L
201MF1/20W5%
OUT
19C3
12C5 17D2 21C3
OUT
12C5 24D6 80A7
OUT
PCH_RTC_RESET_L
14A3
PCH_WLAN_PERST_L
21A3
BKLT_PWM_MLB2TCON
5D3
8C1
8C1
PCH_CORE_VID0
PCH_CORE_VID1
SIGNAL ALIASES
MAKE_BASE=TRUE
PCH_RTC_RESET_L
MAKE_BASE=TRUE
PCH_WLAN_PERST_L
MAKE_BASE=TRUE
BKLT_PWM_MLB2TCON
MAKE_BASE=TRUE
PCH_CORE_VID0
MAKE_BASE=TRUE
PCH_CORE_VID1
D
14A3 62C3 77C2
12C5 17D6 21C3
66C1 77D5
56A5 64A5
56A5 64A5
C
14A6
BI BI
PCH_WLAN_CLKREQ_L
R2010
1K
21
PCH_WLAN_CLKREQ_R_L
1/20W5% 201MF
RSMRST override
Force PCH-side RSMRST low if SLP_SUS is low, in case of uncontrolled shutdown
PP3V3_S5
10%
16V
0201
1
2
NC
C2070
0.1UF
X5R-CERM
6
VCC
1
A Y
2
AND
B
5
NC
GND
3
U2070
74AUP1G08
X1-DFN1010-6
4
RSMRSTL_R
1
R2072
100K
5%
1/20W
MF
201
2
13A6 13D3 16B7 59C7
31B1
74B2 31C1 16A7
IN
PM_SLP_SUS_L
PM_RSMRST_R_L
IN
BYPASS=U2070::5mm
SOC_CLKREQ_L ISOLATION SWITCH & DELAY
21A2 21C3
R2071
0
5%
1/20W
MF
0201
NOSTUFF
R2070
0
21
5%
1/20W
MF
0201
C
BT_AUDIO_SYNC ISOLATION BUFFER
21
PM_RSMRST_L
13D6 15C8 16B7 17B8 19C3 77C2
OUT
75C1 17B4
21B3 21C2 21C7
PP1V8_G3S
IN
BT_AUDIO_SYNC
1
C2030
0.1UF
10%
16V
2
X5R-CERM
0201
U2030
74AUP1G126GX
5
X2SON5
2
A
OE
3
4
Y
1
PCH_BT_AUDIO_SYNC
OUT
5A6 5D3
B
13A6 13D6 17A4 17D8 20C5 20D5 31B6 77C2
IN
0
5%
MF
0201
5%
MF
201
PP1V8_S5
21
SOC_CLKREQ_SW_EN
BYPASS=U2050::2MM
C2050
D2050
LGA
K A
RB522ES-30
NO_XNET_CONNECTION=1
0.1UF
10%
16V
X5R-CERM
0201
1
2
C2
1
C2051
0.022UF
10%
6.3V
2
X5R-CERM
0201
A2
V+
U2050
TS5A3166YZPR
XBGA
IN
GND
C1
COM
NO
B1
A1
SOC_CLKREQ_BUF_L
SOC_CLKREQ_L
PCH latches SOC_CLKREQ_L boot strap
65us after RSMRST# de-assertion
BI
BI
14A6 15A2
26D7
75C1 17C4
21A2 21C5 21D7 23D2
13A6 13D6 17B4 17D8 20C5 20D5 31B6 77C2
IN
75B1 24A8 14A7 12A7
NOSTUFF
R2050
13C6 16A5 77C2
IN
13D6 15C8 16B7 17C6 19C3 77C2
IN
PM_PCH_PWROK
170us-nom delay
PM_RSMRST_L
1/20W
R2051
20K
2 1
1/20W
R2052
33
21
SOC_CLKREQ_SW_EN_D
5%
1/20W
MF
201
NO_XNET_CONNECTION=1
PLT_RST_L
WLAN_AUDIO_SYNC ISOLATION BUFFER
PP1V8_G3S
WLAN_AUDIO_SYNC
PLT_RST_L
1
C2020
0.1UF
10%
16V
2
X5R-CERM
0201
R2030
2
A
3
117S0201
0
21
5%
1/20W
MF
0201
NOSTUFF
U2020
74AUP1G126GX
5
X2SON5
4
Y
OE
1
117S0201
PCH_WLAN_AUDIO_SYNC
B
5A6 5D3
OUTIN
A
SOC SWD <=> DEBUG MUX PATH
SOC
24C3 77D4
OUT
24C3 77C4 19D3
BI
SWD_SOC_SWCLK
SWD_SOC_SWDIO SWD_SOC_SWDIO_R
R2008
33
21
5%
1/20W
MF
201
R2009
33
21
5%
1/20W
MF
201
DEBUG MUX
SWD_SOC_SWCLK_R
IN
19D3
BI
R2021
0
21
5%
1/20W
MF
0201
BOM_COST_GROUP=CPU & CHIPSET
NOSTUFF
SYNC_MASTER=J214_DAVID SYNC_DATE=03/05/2019
PAGE TITLE
Chipset Support 2
SIZE
D
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
20 OF 150
SHEET
17 OF 109
A
8
67
35 4
2
1
678
www.haojiyoubbs.com
QQ微信：181806465
3 245
1
D
C
B
CHANNEL A
88C6 7D5
88C6 7D5 7C5
88C6 7D5
CHANNEL B
89C6 7D5
89C6 7C5
89C6 7D5
CHANNEL C
90C6 7D1
90C6 7D1 7C1
90C6 7D1
CHANNEL D
91C6 7D1
91C6 7C1
91C6 7D1
LPDDR4x SUB CHANNELS
LPDDR4X
PP1V8_S3_MEM
PP1V1_S3
PP0V6_S3
MEM_A_DQ_2<7..0>
MEM_A_DQ_0<7..0>
MEM_A_DQ_3<7..0>
MEM_A_DQ_1<7..0>
MEM_A_DQS_P<3..0>
MEM_A_DQS_N<3..0>
PP1V8_S3_MEM
PP1V1_S3
PP0V6_S3
MEM_B_DQ_2<7..0>
MEM_B_DQ_0<7..0>
MEM_B_DQ_3<7..0>
MEM_B_DQ_1<7..0>
MEM_B_DQS_P<3..0>
MEM_B_DQS_N<3..0>
PP1V8_S3_MEM
PP1V1_S3
PP0V6_S3
MEM_C_DQ_1<7..0>
MEM_C_DQ_3<7..0>
MEM_C_DQ_0<7..0>
MEM_C_DQ_2<7..0>
MEM_C_DQS_P<3..0>
MEM_C_DQS_N<3..0>
PP1V8_S3_MEM
PP1V1_S3
PP0V6_S3
MEM_D_DQ_1<7..0>
MEM_D_DQ_3<7..0>
MEM_D_DQ_0<7..0>
MEM_D_DQ_2<7..0>
MEM_D_DQS_P<3..0>
MEM_D_DQS_N<3..0>
88D3
88B3
88D3
88B3
7B1 18B8 18C8 91B5 90B5 89B5 88B5
7D5 88C6
7D5 88C6
MEM_RESET_L
MEM_A_CLK_P
MEM_A_CLK_N
MEM_A_CS_L<1..0>
MEM_A_CA<5..0>
MEM_A_CKE<1..0>
7B1 18B8 18C8 18D8 91B5 90B5 89B5 88B5
7D5 89C6
7D5 89C6
MEM_RESET_L
MEM_B_CLK_P
MEM_B_CLK_N
MEM_B_CS_L<1..0>
MEM_B_CA<5..0>
MEM_B_CKE<1..0>
7B1 18B8 18C8 18D8 91B5 90B5 89B5 88B5
7D1 90C6
7D1 90C6
MEM_RESET_L
MEM_C_CLK_P
MEM_C_CLK_N
MEM_C_CS_L<1..0>
MEM_C_CA<5..0>
MEM_C_CKE<1..0>
MEM_RESET_L
7B1 18C8 18D8 91B5 90B5 89B5 88B5
MEM_D_CLK_P
7D1 91C6
MEM_D_CLK_N
7D1 91C6
MEM_D_CS_L<1..0>
MEM_D_CA<5..0>
MEM_D_CKE<1..0>
RESET_L
CLK_P
CLK_N
CS_L<1..0>
CA<5..0>
RESET_L
CLK_P
CLK_N
CS_L<1..0>
CA<5..0>
RESET_L
CLK_P
CLK_N
CS_L<1..0>
CA<5..0>
RESET_L
CLK_P
CLK_N
CS_L<1..0>
CA<5..0>
PP1V8
PP1V1
PP0V6
DQ_0<7..0>
DQ_1<7..0>
DQ_2<7..0>
DQ_3<7..0>
DQS_P<3..0>
DQS_N<3..0>CKE<1..0>
LPDDR4X
PP1V8
PP1V1
PP0V6
DQ_0<7..0>
DQ_1<7..0>
DQ_2<7..0>
DQ_3<7..0>
DQS_P<3..0>
DQS_N<3..0>CKE<1..0>
LPDDR4X
PP1V8
PP1V1
PP0V6
DQ_0<7..0>
DQ_1<7..0>
DQ_2<7..0>
DQ_3<7..0>
DQS_P<3..0>
DQS_N<3..0>CKE<1..0>
LPDDR4X
PP1V8
PP1V1
PP0V6
DQ_0<7..0>
DQ_1<7..0>
DQ_2<7..0>
DQ_3<7..0>
DQS_P<3..0>
DQS_N<3..0>CKE<1..0>
Memory Bit & Byte Swizzle
MAKE_BASE=TRUE
MEM_A_DQ_0<0>
7D8
MEM_A_DQ_0<1>
7D8
MEM_A_DQ_0<2>
7D8
MEM_A_DQ_0<3>
88D3 89D3 90D3 91D3 77B4 74D4 63B6 63A6 18C6 18B6
88A3 89A3 90A3
88D5 18C4
88D5 18D4
88C5 18C4
88C5 18D4
88C5 88B5 18A4
88C5 18A4
88A3 89A3 90A3 91A3
89D5 18B4
89D5 18C4
89C5 18B4
89C5 18C4 18B4
89C5 89B5 18A4
89C5 18A4
88A3 89A3 90A3 91A3
90D5 18D2
90D5 18C2
90C5 18D2
90C5 18C2
90C5 90B5 18A2
90C5 18A2
88A3 89A3 90A3
91D5 18C2 18B2
91D5 18B2
91C5 18C2
91C5 18B2
91C5 91B5 18A2
91C5 18A2
91A3 80C8 80B8 79B6 75A1 63C2 63A8 63A5 18C6 18B6
88B3 89B3 90B3 91B3 79C6 77B4 75A1 63A6 18C6 18B6
89D3 90D3 91D3 77B4 74D4 63B6 63A6 18D6 18C6 18B6
80C8 80B8 79B6 75A1 63C2 63A8 63A5 18D6 18C6 18B6
89B3 90B3 91B3 79C6 77B4 75A1 63A6 18D6 18C6 18B6
89D3 90D3 91D3 77B4 74D4 63B6 63A6 18D6 18C6 18B6
80C8 80B8 79B6 75A1 63C2 63A8 63A5 18D6 18C6 18B6
89B3 90B3 91B3 79C6 77B4 75A1 63A6 18D6 18C6 18B6
88D3 89D3 90D3 91D3 77B4 74D4 63B6 63A6 18D6 18C6
91A3 80C8 80B8 79B6 75A1 63C2 63A8 63A5 18D6 18C6
88B3 89B3 90B3 91B3 79C6 77B4 75A1 63A6 18D6 18C6
7D8
MEM_A_DQ_0<4>
7D8
MEM_A_DQ_0<5>
7D8
MEM_A_DQ_0<6>
7D8
MEM_A_DQ_0<7>
7D8
MEM_A_DQ_1<0>
7D8
MEM_A_DQ_1<1>
7D8
MEM_A_DQ_1<2>
7D8
MEM_A_DQ_1<3>
7D8
MEM_A_DQ_1<4>
7D8
MEM_A_DQ_1<5>
7D8
MEM_A_DQ_1<6>
7D8
MEM_A_DQ_1<7>
7D8
MEM_A_DQ_2<0>
7D8
MEM_A_DQ_2<1>
7D8
MEM_A_DQ_2<2>
7C8
MEM_A_DQ_2<3>
7C8
MEM_A_DQ_2<4>
7C8
MEM_A_DQ_2<5>
7C8
MEM_A_DQ_2<6>
7C8
MEM_A_DQ_2<7>
7C8
MEM_A_DQ_3<0>
7C8
MEM_A_DQ_3<1>
7C8
MEM_A_DQ_3<2>
7C8
MEM_A_DQ_3<3>
7C8
MEM_A_DQ_3<4>
7C8
MEM_A_DQ_3<5>
7C8
MEM_A_DQ_3<6>
7C8
MEM_A_DQ_3<7>
7C8
MEM_B_DQ_0<0>
7C8
MEM_B_DQ_0<1>
7C8
MEM_B_DQ_0<2>
7C8
MEM_B_DQ_0<3>
7C8
MEM_B_DQ_0<4>
7C8
MEM_B_DQ_0<5>
7C8
MEM_B_DQ_0<6>
7C8
MEM_B_DQ_0<7>
7C8
MEM_B_DQ_1<0>
7C8
MEM_B_DQ_1<1>
7C8
MEM_B_DQ_1<2>
7C8
MEM_B_DQ_1<3>
7B8
MEM_B_DQ_1<4>
7B8
MEM_B_DQ_1<5>
7B8
MEM_B_DQ_1<6>
7B8
MEM_B_DQ_1<7>
7B8
MEM_B_DQ_2<0>
7B8
MEM_B_DQ_2<1>
7B8
MEM_B_DQ_2<2>
7B8
MEM_B_DQ_2<3>
7B8
MEM_B_DQ_2<4>
7B8
MEM_B_DQ_2<5>
7B8
MEM_B_DQ_2<6>
7B8
MEM_B_DQ_2<7>
7B8
MEM_A_DQ_0<0>
MEM_A_DQ_0<1>
MEM_A_DQ_0<2>
MEM_A_DQ_0<3>
MEM_A_DQ_0<4>
MEM_A_DQ_0<5>
MEM_A_DQ_0<6>
MEM_A_DQ_0<7>
MEM_A_DQ_1<0>
MEM_A_DQ_1<1>
MEM_A_DQ_1<2>
MEM_A_DQ_1<3>
MEM_A_DQ_1<4>
MEM_A_DQ_1<5>
MEM_A_DQ_1<6>
MEM_A_DQ_1<7>
MEM_A_DQ_2<0>
MEM_A_DQ_2<1>
MEM_A_DQ_2<2>
MEM_A_DQ_2<3>
MEM_A_DQ_2<4>
MEM_A_DQ_2<5>
MEM_A_DQ_2<6>
MEM_A_DQ_2<7>
MEM_A_DQ_3<0>
MEM_A_DQ_3<1>
MEM_A_DQ_3<2>
MEM_A_DQ_3<3>
MEM_A_DQ_3<4>
MEM_A_DQ_3<5>
MEM_A_DQ_3<6>
MEM_A_DQ_3<7>
MEM_B_DQ_0<0>
MEM_B_DQ_0<1>
MEM_B_DQ_0<2>
MEM_B_DQ_0<3>
MEM_B_DQ_0<4>
MEM_B_DQ_0<5>
MEM_B_DQ_0<6>
MEM_B_DQ_0<7>
MEM_B_DQ_1<0>
MEM_B_DQ_1<1>
MEM_B_DQ_1<2>
MEM_B_DQ_1<3>
MEM_B_DQ_1<4>
MEM_B_DQ_1<5>
MEM_B_DQ_1<6>
MEM_B_DQ_1<7>
MEM_B_DQ_2<0>
MEM_B_DQ_2<1>
MEM_B_DQ_2<2>
MEM_B_DQ_2<3>
MEM_B_DQ_2<4>
MEM_B_DQ_2<5>
MEM_B_DQ_2<6>
MEM_B_DQ_2<7>
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88D5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
89D5 18C6
MAKE_BASE=TRUE
MEM_C_DQ_0<0>
7D4
MEM_C_DQ_0<1>
7D4
MEM_C_DQ_0<2>
7D4
MEM_C_DQ_0<3>
7D4
MEM_C_DQ_0<4>
7D4
MEM_C_DQ_0<5>
7D4
MEM_C_DQ_0<6>
7D4
MEM_C_DQ_0<7>
7D4
MEM_C_DQ_1<0>
7D4
MEM_C_DQ_1<1>
7D4
MEM_C_DQ_1<2>
7D4
MEM_C_DQ_1<3>
7D4
MEM_C_DQ_1<4>
7D4
MEM_C_DQ_1<5>
7D4
MEM_C_DQ_1<6>
7D4
MEM_C_DQ_1<7>
7D4
MEM_C_DQ_2<0>
7D4
MEM_C_DQ_2<1>
7D4
MEM_C_DQ_2<2>
7C4
MEM_C_DQ_2<3>
7C4
MEM_C_DQ_2<4>
7C4
MEM_C_DQ_2<5>
7C4
MEM_C_DQ_2<6>
7C4
MEM_C_DQ_2<7>
7C4
MEM_C_DQ_3<0>
7C4
MEM_C_DQ_3<1>
7C4
MEM_C_DQ_3<2>
7C4
MEM_C_DQ_3<3>
7C4
MEM_C_DQ_3<4>
7C4
MEM_C_DQ_3<5>
7C4
MEM_C_DQ_3<6>
7C4
MEM_C_DQ_3<7>
7C4
MEM_D_DQ_0<0>
7C4
MEM_D_DQ_0<1>
7C4
MEM_D_DQ_0<2>
7C4
MEM_D_DQ_0<3>
7C4
MEM_D_DQ_0<4>
7C4
MEM_D_DQ_0<5>
7C4
MEM_D_DQ_0<6>
7C4
MEM_D_DQ_0<7>
7C4
MEM_D_DQ_1<0>
7C4
MEM_D_DQ_1<1>
7C4
MEM_D_DQ_1<2>
7C4
MEM_D_DQ_1<3>
7B4
MEM_D_DQ_1<4>
7B4
MEM_D_DQ_1<5>
7B4
MEM_D_DQ_1<6>
7B4
MEM_D_DQ_1<7>
7B4
MEM_D_DQ_2<0>
7B4
MEM_D_DQ_2<1>
7B4
MEM_D_DQ_2<2>
7B4
MEM_D_DQ_2<3>
7B4
MEM_D_DQ_2<4>
7B4
MEM_D_DQ_2<5>
7B4
MEM_D_DQ_2<6>
7B4
MEM_D_DQ_2<7>
7B4
MEM_C_DQ_0<0>
MEM_C_DQ_0<1>
MEM_C_DQ_0<2>
MEM_C_DQ_0<3>
MEM_C_DQ_0<4>
MEM_C_DQ_0<5>
MEM_C_DQ_0<6>
MEM_C_DQ_0<7>
MEM_C_DQ_1<0>
MEM_C_DQ_1<1>
MEM_C_DQ_1<2>
MEM_C_DQ_1<3>
MEM_C_DQ_1<4>
MEM_C_DQ_1<5>
MEM_C_DQ_1<6>
MEM_C_DQ_1<7>
MEM_C_DQ_2<0>
MEM_C_DQ_2<1>
MEM_C_DQ_2<2>
MEM_C_DQ_2<3>
MEM_C_DQ_2<4>
MEM_C_DQ_2<5>
MEM_C_DQ_2<6>
MEM_C_DQ_2<7>
MEM_C_DQ_3<0>
MEM_C_DQ_3<1>
MEM_C_DQ_3<2>
MEM_C_DQ_3<3>
MEM_C_DQ_3<4>
MEM_C_DQ_3<5>
MEM_C_DQ_3<6>
MEM_C_DQ_3<7>
MEM_D_DQ_0<0>
MEM_D_DQ_0<1>
MEM_D_DQ_0<2>
MEM_D_DQ_0<3>
MEM_D_DQ_0<4>
MEM_D_DQ_0<5>
MEM_D_DQ_0<6>
MEM_D_DQ_0<7>
MEM_D_DQ_1<0>
MEM_D_DQ_1<1>
MEM_D_DQ_1<2>
MEM_D_DQ_1<3>
MEM_D_DQ_1<4>
MEM_D_DQ_1<5>
MEM_D_DQ_1<6>
MEM_D_DQ_1<7>
MEM_D_DQ_2<0>
MEM_D_DQ_2<1>
MEM_D_DQ_2<2>
MEM_D_DQ_2<3>
MEM_D_DQ_2<4>
MEM_D_DQ_2<5>
MEM_D_DQ_2<6>
MEM_D_DQ_2<7>
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
90D5 18C6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
Current LPDDR4x APNs for BOM:
Hynix (MPN -- APN):
H9HCNNNBKMALHR-NEE, 333S00180
H9HCNNNCPMALHR-NEE, 333S00181
H9HCNNNFAMALTR-NME, PENDING
Micron (MPN -- APN):
MT53E512M32D2NP-046 WT:E, PENDING
MT53E1G32D4NQ-046 WT:E, PENDING
MT53E2G32D8QD-046 WT:E, PENDING
Samsung (MPN -- APN):
K4UBE3D4AM-MGCJT00, 333S00194
K4UCE3Q4AM-AGCJT00, 333S00195
D
C
B
MEM_B_DQ_3<0>
7B8
MEM_B_DQ_3<1>
7B8
MEM_B_DQ_3<2>
7B8
MEM_B_DQ_3<3>
7B8
MEM_B_DQ_3<4>
7B8
MEM_B_DQ_3<5>
7B8
MEM_B_DQ_3<6>
7B8
MEM_B_DQ_3<7>
7B8
MAKE_BASE=TRUE
MEM_A_DQS_P<0>
7C5
MEM_A_DQS_N<0>
7C5
MEM_A_DQS_P<1>
7C5
MEM_A_DQS_N<1>
7C5
MEM_A_DQS_P<2>
7C5
MEM_A_DQS_N<2>
7C5
MEM_A_DQS_P<3>
7C5
MEM_A_DQS_N<3>
7C5
MEM_B_DQ_3<0>
MEM_B_DQ_3<1>
MEM_B_DQ_3<2>
MEM_B_DQ_3<3>
MEM_B_DQ_3<4>
MEM_B_DQ_3<5>
MEM_B_DQ_3<6>
MEM_B_DQ_3<7>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
MEM_D_DQ_3<0>
7B4
MEM_D_DQ_3<1>
7B4
MEM_D_DQ_3<2>
7B4
MEM_D_DQ_3<3>
7B4
MEM_D_DQ_3<4>
7B4
MEM_D_DQ_3<5>
7B4
MEM_D_DQ_3<6>
7B4
MEM_D_DQ_3<7>
7B4
MEM_D_DQ_3<0>
MEM_D_DQ_3<1>
MEM_D_DQ_3<2>
MEM_D_DQ_3<3>
MEM_D_DQ_3<4>
MEM_D_DQ_3<5>
MEM_D_DQ_3<6>
MEM_D_DQ_3<7>
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
91D5 18B6
MAKE_BASE=TRUE
88C5 18D6
88C5 18D6
88B5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
88C5 18D6
MEM_C_DQS_P<0>
7C1
MEM_C_DQS_N<0>
7C1
MEM_C_DQS_P<1>
7C1
MEM_C_DQS_N<1>
7C1
MEM_C_DQS_P<2>
7C1
MEM_C_DQS_N<2>
7C1
MEM_C_DQS_P<3>
7C1
MEM_C_DQS_N<3>
7C1
MEM_C_DQS_P<0>
MEM_C_DQS_N<0>
MEM_C_DQS_P<1>
MEM_C_DQS_N<1>
MEM_C_DQS_P<2>
MEM_C_DQS_N<2>
MEM_C_DQS_P<3>
MEM_C_DQS_N<3>
90C5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
90B5 18C6
90C5 18C6
90C5 18C6
90C5 18C6
A
8
MEM_B_DQS_P<0>
7C5
MEM_B_DQS_N<0>
7C5
MEM_B_DQS_P<1>
7C5
MEM_B_DQS_N<1>
7C5
MEM_B_DQS_P<2>
7C5
MEM_B_DQS_N<2>
7C5
MEM_B_DQS_P<3>
7C5
MEM_B_DQS_N<3>
7C5
67
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
89C5 18C6
89C5 18C6
89B5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
89C5 18C6
MEM_D_DQS_P<0>
7C1
MEM_D_DQS_N<0>
7C1
MEM_D_DQS_P<1>
7C1
MEM_D_DQS_N<1>
7C1
MEM_D_DQS_P<2>
7C1
MEM_D_DQS_N<2>
7C1
MEM_D_DQS_P<3>
7C1
MEM_D_DQS_N<3>
7C1
35 4
MEM_D_DQS_P<0>
MEM_D_DQS_N<0>
MEM_D_DQS_P<1>
MEM_D_DQS_N<1>
MEM_D_DQS_P<2>
MEM_D_DQS_N<2>
MEM_D_DQS_P<3>
MEM_D_DQS_N<3>
BOM_COST_GROUP=DRAM
91C5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
91B5 18B6
91C5 18B6
91C5 18B6
91C5 18B6
PAGE TITLE
LPDDR4x Channels / Aliasing
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
DRAWING NUMBER
051-05198
REVISION
BRANCH
PAGE
SHEET
1
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
SIZE
6.0.0
evt-3
23 OF 150
18 OF 109
A
D
678
www.haojiyoubbs.com
QQ微信：181806465
3 245
1
D
5C6 94D6
5C6 94D6
5C6 94D6
5C6 94D6
5C6 94D6
5C6 94D6
5C6 94D6
5C6 94D6
5C3 78C4 94D6
BI
5C3 78C4 94D6
BI
5B6 5C3 15B6 94D6
BI
5C3 15B6 94D6
BI
14D3 94D6
BI
14D3 94D6
BI
5C6 94D2
5C6 94D2
5B6 94D2
5B6 94D2
5C6 94D2
5C6 94D2
5B6 94D2
5B6 94D2
5C3 78C4 94D2
BI
5C3 78C4 94D2
BI
5B6 5C3 15B6 94D2
BI
5B3 15B6 94D2
BI
14D3 94D2
BI
14D3 94D2
BI
USBC_HSX_R2D_C_P<1>
IN
USBC_HSX_R2D_C_N<1>
IN
USBC_HSX_R2D_C_P<2>
IN
USBC_HSX_R2D_C_N<2>
IN
USBC_HSX_D2R_C_P<1>
OUT
USBC_HSX_D2R_C_N<1>
OUT
USBC_HSX_D2R_C_P<2>
OUT
USBC_HSX_D2R_C_N<2>
OUT
USBC_HSX_AUXCH_C_P
USBC_HSX_AUXCH_C_N
LSX_HSX_R2P
LSX_HSX_P2R
USB2_TBT_X_P
USB2_TBT_X_N
USBC_HST_R2D_C_P<1>
IN
USBC_HST_R2D_C_N<1>
IN
USBC_HST_R2D_C_P<2>
IN
USBC_HST_R2D_C_N<2>
IN
USBC_HST_D2R_C_P<1>
OUT
USBC_HST_D2R_C_N<1>
OUT
USBC_HST_D2R_C_P<2>
OUT
USBC_HST_D2R_C_N<2>
OUT
USBC_HST_AUXCH_C_P
USBC_HST_AUXCH_C_N
LSX_HST_R2P
LSX_HST_P2R
USB2_TBT_T_P
USB2_TBT_T_N
USBC_X_HS_R2D_C_P<1>
USBC_X_HS_R2D_C_N<1>
USBC_X_HS_R2D_C_P<2>
USBC_X_HS_R2D_C_N<2>
USBC_X_HS_D2R_C_P<1>
USBC_X_HS_D2R_C_N<1>
USBC_X_HS_D2R_C_P<2>
USBC_X_HS_D2R_C_N<2>
USBC_X_HS_AUXCH_C_P
USBC_X_HS_AUXCH_C_N
USBC_X_HS_LSX_R2P
USBC_X_HS_LSX_P2R
USB2_TBT_X_P
USB2_TBT_X_N
USBC_T_HS_R2D_C_P<1>
USBC_T_HS_R2D_C_N<1>
USBC_T_HS_R2D_C_P<2>
USBC_T_HS_R2D_C_N<2>
USBC_T_HS_D2R_C_P<1>
USBC_T_HS_D2R_C_N<1>
USBC_T_HS_D2R_C_P<2>
USBC_T_HS_D2R_C_N<2>
USBC_T_HS_AUXCH_C_P
USBC_T_HS_AUXCH_C_N
USBC_T_HS_LSX_R2P
USBC_T_HS_LSX_P2R
USB2_TBT_T_P
USB2_TBT_T_N
USBC
USB3_BSSB_R2D_C_P
USB3_BSSB_R2D_C_N
USB3_BSSB_D2R_P
USB3_BSSB_D2R_N
UPC_XT_GPIO7
SWD_SOC_SWDIO
SWD_SOC_SWCLK
SOC_FORCE_DFU
SOC_DFU_STATUS
SMC_DEBUGPRT_TX
SMC_DEBUGPRT_RX
PCH_I2C_UPC_SDA
PCH_I2C_UPC_SCL
PCH_UPC_I2C_INT_L
I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L
USB_SOC_P
USB_SOC_N
TBT_POC_RESET
UPC_PMU_RESET
PCH_BBR_FORCE_PWR
PCH_STRP_GPD7
PMU_ACTIVE_READY
TBT_PWR_EN
PM_RSMRST_L
PLT_RST_3V3_L
USB3_BSSB_R2D_C_P
USB3_BSSB_R2D_C_N
USB3_BSSB_D2R_P
USB3_BSSB_D2R_N
SOC_DOCK_CONNECT
SWD_SOC_SWDIO_R
SWD_SOC_SWCLK_R
SOC_FORCE_DFU
SOC_DFU_STATUS
SMC_DEBUGPRT_TX
SMC_DEBUGPRT_RX
PCH_I2C_UPC_SDA
PCH_I2C_UPC_SCL
PCH_UPC_I2C_INT_L
I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L
USB_SOC_P
USB_SOC_N
TBT_POC_RESET
UPC_PMU_RESET
PCH_BBR_FORCE_PWR
PCH_STRP_GPD7
PMU_ACTIVE_READY
TBT_PWR_EN
PM_RSMRST_L
PLT_RST_3V3_L
14C6 92C1
IN
14C6 92C1
IN
14C6 92C1
OUT
14C6 92C1
OUT
24A7 24C3 77D4 92C3
OUT
17A5 92C5
BI
17A5 92C5
BI
23D3 62C7 77D4 81B7 92C7
BI
23C3 77D4 81A4 92C7
BI
24A3 77C4 92C1
BI
24A3 77C4 92C1
BI
36B3 92D2
BI
36B3 92D2
BI
12C5 36B3 36B6 92D2
OUT
24B6 36B3 92D5
BI
24B6 36B3 92C5
BI
24B3 92D2
OUT
77D4 81C3 94D7
BI
77D4 81C3 94C7
BI
12A6 12C2 92C3
IN
52C2 62D6 77B2 80A7 92C3
OUT
12A6 12C5 92C3
IN
12A6 12C2 92A7
IN
23D3 62A6 62D6 77B2 81A8 92C7
IN
62B3 95C6
IN
13D6 15C8 16B7 17B8 17C6 77C2 95C6
IN
17D6 92B7
IN
D
C
B
SWD_SOC_SW* Placement Topology
SWD_SOC_SWCLK
H9M
U3900
Front
ACE
1
2
R
SWD_SOC_SWCLK_T
Rear
ACE
5B6 94C6
5B6 94C6
5B6 94C6
5B6 94C6
5B6 94C6
5B6 94C6
5B6 94C6
5B6 94C6
5C3 78C4 94B6
BI
5C3 78C4 94B6
BI
5A6 5B3 15A6 94B6
BI
5B3 94B6
BI
14D3 94B6
BI
14D3 94B6
BI
5B6 94C2
5B6 94C2
5B6 94C2
5B6 94C2
5B6 94C2
5B6 94C2
5B6 94C2
5B6 94C2
5C3 78C4 94B2
BI
5C3 78C4 94B2
BI
5A6 5B3 15B6 94B2
BI
5B3 15B6 94B2
BI
14D3 94B2
BI
14D3 94B2
BI
USBC_HSW_R2D_C_P<1>
IN
USBC_HSW_R2D_C_N<1>
IN
USBC_HSW_R2D_C_P<2>
IN
USBC_HSW_R2D_C_N<2>
IN
USBC_HSW_D2R_C_P<1>
OUT
USBC_HSW_D2R_C_N<1>
OUT
USBC_HSW_D2R_C_P<2>
OUT
USBC_HSW_D2R_C_N<2>
OUT
USBC_HSW_AUXCH_C_P
USBC_HSW_AUXCH_C_N
LSX_HSW_R2P
LSX_HSW_P2R
USB2_TBT_W_P
USB2_TBT_W_N
USBC_HSR_R2D_C_P<1>
IN
USBC_HSR_R2D_C_N<1>
IN
USBC_HSR_R2D_C_P<2>
IN
USBC_HSR_R2D_C_N<2>
IN
USBC_HSR_D2R_C_P<1>
OUT
USBC_HSR_D2R_C_N<1>
OUT
USBC_HSR_D2R_C_P<2>
OUT
USBC_HSR_D2R_C_N<2>
OUT
USBC_HSR_AUXCH_C_P
USBC_HSR_AUXCH_C_N
LSX_HSR_R2P
LSX_HSR_P2R
USB2_TBT_R_P
USB2_TBT_R_N
USBC_W_HS_R2D_C_P<1>
USBC_W_HS_R2D_C_N<1>
USBC_W_HS_R2D_C_P<2>
USBC_W_HS_R2D_C_N<2>
USBC_W_HS_D2R_C_P<1>
USBC_W_HS_D2R_C_N<1>
USBC_W_HS_D2R_C_P<2>
USBC_W_HS_D2R_C_N<2>
USBC_W_HS_AUXCH_C_P
USBC_W_HS_AUXCH_C_N
USBC_W_HS_LSX_R2P
USBC_W_HS_LSX_P2R
USB2_TBT_W_P
USB2_TBT_W_N
USBC_R_HS_R2D_C_P<1>
USBC_R_HS_R2D_C_N<1>
USBC_R_HS_R2D_C_P<2>
USBC_R_HS_R2D_C_N<2>
USBC_R_HS_D2R_C_P<1>
USBC_R_HS_D2R_C_N<1>
USBC_R_HS_D2R_C_P<2>
USBC_R_HS_D2R_C_N<2>
USBC_R_HS_AUXCH_C_P
USBC_R_HS_AUXCH_C_N
USBC_R_HS_LSX_R2P
USBC_R_HS_LSX_P2R
USB2_TBT_R_P
USB2_TBT_R_N
PCH_UART_DEBUG_R2D
PCH_UART_DEBUG_D2R
JTAG_ISP_TDI
JTAG_ISP_TDO
JTAG_ISP_TCK
JTAG_TBT_X_TMS
JTAG_TBT_T_TMS
JTAG_TBT_W_TMS
JTAG_TBT_R_TMS
PPDCIN_G3H
PPVIN_5VUSBC
PP5V_G3S_USBC
PP3V3_VIN_X
PP3V3_VIN_T
PP3V3_VIN_W
PP3V3_VIN_R
PP3V3_S0_TBT_XT
PP3V3_S0_TBT_WR
PP3V3_G3H_UPC5VEN
PP1V8_VDDIO
TBT_X_THERM_D_P
TBT_X_THERM_D_N
TBT_T_THERM_D_P
TBT_T_THERM_D_N
TBT_W_THERM_D_P
TBT_W_THERM_D_N
TBT_R_THERM_D_P
TBT_R_THERM_D_N
PCH_UART_DEBUG_R2D_1
PCH_UART_DEBUG_D2R_1
JTAG_ISP_TDI
JTAG_ISP_TDO
JTAG_ISP_TCK
JTAG_TBT_X_TMS
JTAG_TBT_T_TMS
JTAG_TBT_W_TMS
JTAG_TBT_R_TMS
PPDCIN_G3H
PPBUS_G3H
PP5V_G3S
PP3V3_G3H_RTC
PP3V3_S0_TBT_XT_ISNS_R
PP3V3_S0_TBT_WR_ISNS_R
PP3V3_G3H_RTC
PP1V8_SLPS2R
TBT_X_THERM_D_P
TBT_X_THERM_D_N
TBT_T_THERM_D_P
TBT_T_THERM_D_N
TBT_W_THERM_D_P
TBT_W_THERM_D_N
TBT_R_THERM_D_P
TBT_R_THERM_D_N
12A6 12D5 77D4 92C6
IN
12A6 12D5 77D4 92B6
OUT
12A6 12C5 92D2
IN
12B6 12C2 92D2
OUT
12A6 12C5 92D2
IN
12B6 12C2 92D6
IN
12B6 12C2 92D2
IN
12B6 12C5 93D6
IN
12B6 12C5 93D2
IN
53B1 53D7 75B7 77C4 77D2 77D4 95A3
IN
75D7 95C6
IN
75B7 79A8 95C6
IN
19B3 75D4 92C4 92C8 95B6 95C6
IN
75D3 95D6
IN
75D3 95C6
IN
19B3 75D4 92C4 92C8 95B6 95C6
IN
71A7 74C6 95A3
IN
42B5 42D6 92D7
OUT
42D6 92D7
OUT
42D4 42D5 92D3
OUT
42C6 92D3
OUT
42B5 42C5 93D7
OUT
42C6 93D7
OUT
42B5 42C5 93D3
OUT
42C6 93D3
OUT
C
B
T
X
SoC SWD
FAN TACH
SMC UART
DCI
SoC SWD
SoC USB2
x86 UART
NORMAL SITTING MACBOOK PRO.
VIEW FROM TOP
W
R
13A6 13D3 16A7 16B7 62D6 64A6 64B5 64C3 77C2 81C3
92D4
IN
PM_SLP_S3_L_1
PM_SLP_S3_L
UPC_DBG0_W
UPC_DBG1_W
P5VUSBC_POS_XT
P5VUSBC_NEG_XT
P5VUSBC_POS_WR
P5VUSBC_NEG_WR
SMC_FAN_0_TACH
SMC_FAN_1_TACH
P5VUSBC_POS_XT
P5VUSBC_NEG_XT
P5VUSBC_POS_WR
P5VUSBC_NEG_WR
24A3 44C6 93C6
IN
24A3 44C8 93C6
IN
41B4 95C5
OUT
41B4 95C5
OUT
41A5 95A5
OUT
41A5 95A5
OUT
A
Port I2C_ADDR
X GND (0)
T
W
R
FLOAT (7)
OVERRIDE OTP (3)
OVERRIDE OTP (4)
ALL 4 BURNSIDE BRIDGE I2C ADDRESS = 0x18
8
I2CM_CNFG
PU (3)
PU (3)
OVERRIDE OTP (3)
OVERRIDE OTP (3)
I2C1_OA
0x38
0x3F
0x3B
0x3C
I2C1_AA
0x6B
0x6B
0x6B
0x6B
I2C2_OA
0x38
0x3F
0x3B
0x3C
67
I2C2_AA
0x6B
0x6B
0x6B
0x6B
SYNC_MASTER=X1795_AMIR SYNC_DATE=05/15/2019
PAGE TITLE
A
USB-C
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=TBT
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
28 OF 150
SHEET
19 OF 109
1
SIZE
D
678
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3 245
1
D
75C1 20C6
12A6 12D5
13A6 13D6 17A4 17B4 17D8 20C5 31B6 77C2
PP1V8_G3S_WLANBT
BYPASS=U3640::5mm
IN
IN
IN
PCH_UART_BT_R2D
PLT_RST_L
C3640
0.1UF
X5R-CERM
10%
10V
0201
1
2
8
VCC
U3640
74LVC2G126
X2-DFN2010-COMBO
2
1
5
7
1OE
A2
2OE
CRITICAL
GND
4
Y1A1
Y2
6
3
BT UART BUFFERS
UART_BT_BUF_CTS_LPCH_UART_BT_RTS_L
UART_BT_BUF_R2D
NOSTUFF
1
R3641
100K
5%
1/20W
MF
201
2
NOSTUFF
1
R3642
100K
5%
1/20W
MF
201
2
OUT
OUT
D
21B2 21C3 12A6 12D5
21B3 21C3
C
21B2 21C3
21B2 21C3
75C1 20D5
IN
IN
PP1V8_G3S_WLANBT
NOSTUFF
1
R3651
100K
5%
1/20W
MF
201
2
NOSTUFF
1
R3652
100K
5%
1/20W
MF
201
2
UART_BT_BUF_RTS_L
UART_BT_BUF_D2R
13A6 13D6 17A4 17B4 17D8 20D5 31B6 77C2
PLT_RST_L
BYPASS=U3650::5mm
C3650
0.1UF
X5R-CERM
10%
10V
0201
1
2
VCC
8
C
U3650
74LVC2G126
X2-DFN2010-COMBO
2
1
1OE
5
7
CRITICAL
A2
2OE
GND
Y1A1
Y2
4
PCH_UART_BT_CTS_L
6
PCH_UART_BT_D2R
3
OUT
OUT
12A6 12D5
12A6 12D5
B
radar 47644489
311S00437 in P0 BOM
311S00112 in P1 BOM
B
A
8
SYNC_MASTER=myEE SYNC_DATE=03/01/2019
PAGE TITLE
A
WIFI/BT: Support
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=WIRELESS
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
36 OF 150
SHEET
20 OF 109
1
SIZE
D
TP3700
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QQ微信：181806465
TP3701
TP3702
TP3703
TP3704
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
1
WLAN_JTAG_SEL
1
WLAN_JTAG_TCK
1
WLAN_JTAG_TDI
1
AP_PCIE_WAKE_L
WLAN_JTAG_TRST_L
21A7 21C6
21C6
21A4 21C6
21C3
21C6
79C7 77B4 75D1 21D3 21A7
PLACE_NEAR=U3730.63:2MM
1
C3724
10UF
20%
6.3V
2
CERM-X5R
0402-4
678
PLACE_NEAR=U3730.89:2MM
1
C3725
10UF
20%
6.3V
2
CERM-X5R
0402-4
PP3V3_G3S_WLANBT
PLACE_NEAR=U3730.74:2MM
1
C3721
10UF
20%
6.3V
2
CERM-X5R
0402-4
PLACE_NEAR=U3730.35:2MM
1
C3722
10UF
20%
6.3V
2
CERM-X5R
0402-4
79C7 77B4 75D1 21D6 21A7
3 245
PP3V3_G3S_WLANBT
PLACE_NEAR=U3730.89:1MM
DESENSE
1
C3713
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=U3730.89:1MM
DESENSE
1
C3714
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PLACE_NEAR=U3730.74:1MM
PLACE_NEAR=U3730.74:1MM
DESENSE
1
C3715
12PF
5%
25V
2
NP0-C0G
0201
DESENSE
1
C3716
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PLACE_NEAR=U3730.63:1MM
PLACE_NEAR=U3730.63:1MM
DESENSE
1
C3717
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=U3730.35:1MM
DESENSE
1
C3718
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
1
PLACE_NEAR=U3730.35:1MM
DESENSE
1
C3719
12PF
5%
25V
2
NP0-C0G
0201
DESENSE
1
C3720
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
D
TP3715
TP3716
TP3718
TP3719
TP3721
TP3722
TP3724
TP3725
C
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
TP-P5
A
1
WLAN_AUDIO_SYNC
1
WLAN_HOST_WAKE
1
BT_AUDIO_SYNC
1
BT_GPIO_4
1
BT_DEV_WAKE
1
BT_HOST_WAKE
1
WLAN_JTAG_TMS
1
WLAN_JTAG_TDO
17B4 21A2 21C5 23D2
21A3 21B6 24B3
17B4 21B3 21C2
21C3
21B3 24C6
21B3 24B3
21C6
21C6
75C1 21D3 21C2 21B8
21B2 25A6
21A2 25A6
PP1V8_G3S_WLANBT
1
R3715
100K
5%
1/20W
MF
201
2
1
R3717
100K
5%
1/20W
MF
201
2
1
R3714
100K
5%
1/20W
MF
201
2
22D1
22D1
22C1
22C1
22B1
22B1
BI
BI
BI
BI
BI
BI
50_G_0_MATCH
50_A_0_MATCH
50_G_1_MATCH
50_A_1_MATCH
50_G_2_MATCH
50_A_2_MATCH
WLAN_JTAG_SEL
21A7 21D7
WLAN_JTAG_TCK
21D7
WLAN_JTAG_TDI
21A4 21D7
WLAN_JTAG_TMS
21C7
WLAN_JTAG_TRST_L
21D7
WLAN_JTAG_TDO
21C7
UART_WLAN_R2D
21B3 25A6
UART_WLAN_D2R
UART_WLAN_D2R_CTS_L
UART_WLAN_R2D_RTS_L
21A2 25A6
SPROM_DOUT
21A7
SPROM_DIN
21A6
SPROM_CLK
21A7
SPROM_CS
21A7
NC_WLAN_GPIO_13
WLAN_CONTEXT_B
78B4
WLAN_AUDIO_SYNC
17B4 21A2 21D7 23D2
WLAN_SROM_STRAP
21A8
TP_WLAN_PMU_TEST
NC_WLAN_GPIO_14
WLAN_CONTEXT_A
78B4
WLAN_HOST_WAKE
21A3 21D7 24B3
PCH_WLAN_DEV_WAKE
13C3
NC
91
2G_ANT_CORE0
87
5G_ANT_CORE0
76
2G_ANT_CORE1
72
5G_ANT_CORE1
49
2G_ANT_CORE2
65
5G_ANT_CORE2
44
BT_ONLY_ANT
1
WL_JTAG_SEL
81
WL_JTAG_TCK
82
WL_JTAG_TDI
83
WL_JTAG_TMS
84
WL_JTAG_TRST
85
WL_JTAG_TDO
93
WL_UART_RX
94
WL_UART_TX
95
WL_UART_RTS
96
WL_UART_CTS
67
WL_SPROM_MO
68
WL_SPROM_MI
69
WL_SPROM_CLK
70
WL_SPROM_CS
97
WL_GPIO_13
100
WL_GPIO_21
99
WL_GPIO_20
98
WL_GPIO_17
159
WL_PMU_TEST_O
161
WL_GPIO_14
163
WL_GPIO_12
78
WL_HOST_WAKE
79
WL_DEV_WAKE
30
29
VDDBAT_HP
28
VDDBAT_LP
42
VDD3P3_BT
35
89
74
VDD3P3_PAD
63
18
17
VDDIO_PMU
VDDIO_RFSW
3
VDDIO_DIG
2
VDD3P3_SD&OTP
VDD3P3_FEM_CORE0
VDD3P3_FEM_CORE1
VDD3P3_FEM_CORE2
OMIT_TABLE
U3730
LBEE5ZZ1HP-049
LGA
SYM 1 OF 3
CRITICAL
339S00404
(GPIO2, 100K IPU VDDIO)
(GPIO4, IPD)
(GPIO6, ACTIVE LOW)
(GPIO5)
(100K IPU VDDIO)
(EXT PU NEEDED)
(ACTIVE LOW, EXT PU NEEDED)
(ACTIVE LOW, 100K IPU VDDIO)
(ACTIVE HIGH)
(NC)
(MOTION CONTEXT B)
(WIFI TIME SYNC, EXT PD NEEDED)
(ACTIVE LOW SROM PRESENCE)
(NOTE DEFINED)
(NC) (BT TIME STAMP)
(MOTION CONTEXT A)
(EXT PULL NEEDED)
(IPD) (IPD)
(ACTIVE LOW, IPU VDDIO)
(ACTIVE LOW, EXT PU NEEDED)
(40K IPD)
(I2S:EXT PD NEEDED, UART:NONE?)
(EXT PU NEEDED)
(EXT PU NEEDED)
(IPU VDDIO)
(EXT PU NEEDED)(GPIO3, 100K IPU VDDIO)
BT_GPIO_2/BT_SF_STRAP
(NOT DEFINED)
(ACTIVE LOW)
(I2S:IPD, UART:IPU)
(I2S:IPD, UART:NONE)
(I2S:IPD, UART:NONE)
(BT TIME SYNC)
(RSVD)
(EXT PULL NEEDED)
PLACE_NEAR=U3730.3:1MM
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_TX_P
PCIE_TX_N
PCIE_RX_P
PCIE_RX_N
PCIE_CLKREQ*
PCIE_WAKE*
PERST*
BT_UART_RX
BT_UART_TX
BT_UART_CTS
BT_UART_RTS
BT_JTAG_STRAP
BT_SF_CS
BT_SF_CLK
BT_SF_MISO
BT_SF_MOSI
BT_I2S_WS
BT_I2S_DO
BT_I2S_CLK
BT_I2S_DI
BT_GPIO_3
BT_GPIO_4
BT_DEV_WAKE
BT_HOST_WAKE
PP1V8_G3S_WLANBT
1
C3723
0.1UF
10%
6.3V
2
CERM-X5R
0201
6
PCH_PCIE_CLK100M_WLAN_P
5
PCH_PCIE_CLK100M_WLAN_N
9
PCH_PCIE_WLAN_D2R_C_P
8
PCH_PCIE_WLAN_D2R_C_N
12
PCH_PCIE_WLAN_R2D_P
11
PCH_PCIE_WLAN_R2D_N
14
PCH_WLAN_CLKREQ_R_L
15
AP_PCIE_WAKE_L
16
PCH_WLAN_PERST_L
54
UART_BT_BUF_R2D
55
UART_BT_BUF_D2R
56
UART_BT_BUF_CTS_L
57
UART_BT_BUF_RTS_L
53
BT_ROM_BOOT_HPN_L
60
NC
36
BT_SPI2_CSN
BT_SPI2_CLK
37
BT_SPI2_MISO
38
39
BT_SPI2_MOSI
40
UART_BT_LH_R2D
41
TP_I2S_BT_D2R
123
UART_BT_LH_D2R
124
TP_I2S_BT_R2D
59
BT_AUDIO_SYNC
58
BT_GPIO_4
61
BT_DEV_WAKE
62
BT_HOST_WAKE
DESENSE
1
CC800
12PF
5%
25V
2
NP0-C0G
0201
DESENSE
1
CC801
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
14A6
IN
78D8
14A6
IN
78D8
17C6 21A2
21D7
12C5 17D2 17D6
20D3 21B3
20C6 21B2
20D3 21B2
20C6 21B2
21B8
21B7
21B6
21B6
21B2 25A6
BT_AUDIO_SYNC
MAKE_BASE=TRUE
21C7
21B3 21C7 24C6
21B3 21C7 24B3
75C1 21C6 21C2 21B8
C3707
GND_VOID=TRUE
U3730.9:2mm
C3706
GND_VOID=TRUE
U3730.8:2mm
C3709
GND_VOID=TRUE
C3708
GND_VOID=TRUE
PP1V8_G3S_WLANBT
1
R3716
100K
5%
1/20W
MF
201
2
17B4 21B3 21C7
132S0395
2 1
2 1
2 1
2 1
R3785
5%01/20W MF 0201
0.1UF
6.3V X6S 0201
10%
0.1UF
10%
U0500.DG10:2mm
0.1UF
6.3V X6S 0201
10%
U0500.DH10:2mm
0.1UF
6.3V X6S 0201
10%
75B1 62B7
X6S6.3V 0201
PP1V8_S5
PCH_BT_ROM_BOOT_L
21
PCH_PCIE_WLAN_D2R_P
PCH_PCIE_WLAN_D2R_N
PCH_PCIE_WLAN_R2D_C_P
PCH_PCIE_WLAN_R2D_C_N
10K
5%
1/20W
MF
201
1
2
R3780
(PCH)
75C1 21D3 21C6 21B8
OUT
OUT
IN
IN
IN
D
14C6
14C6
14C6
14C6
12C5 21B3
C
B
A
21D3 21C6 21C2
PP1V8_G3S_WLANBT
75C1
R3751
100K
5%
1/20W
MF
201
21C3
BOOT_STRAPS
WLAN_SROM_STRAP WLAN_JTAG_SEL
21C6 21C6 21D7
R3705
WLAN_SROM_STRAP:
LOW: SROM Enabled
HIGH: SROM Disabled
1
2
10K
1/20W
R3752
100K
1
5%
MF
201
2
5%
1/20W
MF
201
1
R3753
2
10K
5%
1/20W
MF
201
1
2
R3754
1K
21
5%
1/20W
MF
201
BT_SFLASH_WP_L
BT_SFLASH_HOLD_L
SPROM_CS
21C6
10K
5%
MF
201
1
2
R3700
1/20W
WLAN_JTAG_SEL:
LOW: Some JTAG are GPIOs
HIGH: JTAG Enabled
BLUETOOTH SERIAL FLASH
8
VCC
U3750
PLACE_NEAR=U3750.8:2MM
1
C3710
0.1UF
10%
6.3V
2
CERM-X5R
0201
2MBIT
21C3 21C3
BT_SPI2_CLK BT_SPI2_MOSI
6
CLK
USON
DI(IO0)
5
W25Q20EWUXIE
BT_SFLASH_CS_LBT_SPI2_CSN
79C7 77B4 75D1 21D6 21D3
1
CS*
3
WP*(IO2)
7
HOLD*(IO3)
PP3V3_G3S_WLANBT
OMIT_TABLE
GND
4
DO(IO1)
EPAD
9
2
BT_SPI2_MISO
R3701
R3702
10K
5%
1/20W
MF
201
1K
21
1
2
5%
1/20W
MF
201
SPROM_DOUT
21C6
SPROM_CS_R
SPROM_CLK
21C6
NC
1
CS
2
SK
7
PE
8
VCC
U3710
CAS93C86B
UDFN8
ORG
OMIT_TABLE
EPADGND
9
5
DODI
WLAN SERIAL EEPROM
PLACE_NEAR=U3750.8:4MM
1
C3712
10UF
20%
6.3V
2
CERM-X5R
0402-4
21C3
1
C3711
0.1UF
10%
6.3V
2
CERM-X5R
0201
43
6
WIFI_SROM_ORG
PLACE_NEAR=U3710.8:2MM
SPROM_DIN
21C6
R3712
10K
2 1
5%
1/20W
MF
201
P1V5_WLANBT_VLX
21B4
DIDT=TRUE
SWITCH_NODE=TRUE
P1V2_WLANBT_VLX
21B4
DIDT=TRUE
SWITCH_NODE=TRUE
PVIN_RFLDO_WLANBT_VLX
21B4
DIDT=TRUE
SWITCH_NODE=TRUE
BT_REG_ON
WL_REG_ON
19
WLAN_PWR_EN
21A3 62B3
21
20
PP1V5_WLANBT
BT_PWR_EN
21B3 62B3
L3701
2.2UH-1.2A
0806
PLACE_NEAR=U3730.23:4MM
L3702
1UH-20%-4.1A-0.048OHM
2520-1
PLACE_NEAR=U3730.25:4MM
L3703
2.2UH-1.2A
2 1
0806
PLACE_NEAR=U3730.24:4MM
62D6
PMU_CLK32K_WLANBT
IN
WLAN_JTAG_TDI
25B3
VDD1P5_1X1
SR1P4_VLX
SR1P8_VLX
VIN_RFLDO
22
23
P1V5_WLANBT_VLX
21B3
21B5
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0540
VOLTAGE=1.5V
21
PP1V5_WLANBT_C
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0540
VOLTAGE=1.2V
PP1V2_WLANBT_C
21
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0540
VOLTAGE=1.8V
34
24
PPVIN_RFLDO_WLANBT
PVIN_RFLDO_WLANBT_VLX
21A3
21A5
PLACE_NEAR=L3701.2:1MM
PLACE_NEAR=L3702.2:1MM
PPVIN_RFLDO_WLANBT_C
PLACE_NEAR=L3703.1:1MM
SR1P2_VLX
26
25
P1V2_WLANBT_VLX
21A5
0402-THICKSTNCL
0402-THICKSTNCL
0402-THICKSTNCL
VDD1P2_3X3
33
32
PP1V2_WLANBT
21A3
PMU_CLK32K_WLANBT
MAKE_BASE=TRUE
WLAN_JTAG_TDI
CLK32K
52
PMU_CLK32K_WLANBT
21A2 21A4
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0540
C3701
1
4
2
VOLTAGE=1.5V
3
PP1V5_WLANBT
7.5UF
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0540
VOLTAGE=1.2V
C3702
PP1V2_WLANBT
1
3
7.5UF
4
2
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0540
VOLTAGE=1.8V
C3703
1
3
7.5UF
4
2
MAKE_BASE=TRUE
PPVIN_RFLDO_WLANBT
21A2 21B4
20%
4V
20%
4V
20%
4V
21C6 21D7
21B4
21B4
21B4
WIFI_DBG
J3740
505070-1222
M-ST-SM
UART_BT_BUF_R2D
20D3 21C3
PCH_BT_ROM_BOOT_L UART_BT_BUF_CTS_L
12C5 21C1 20D3 21C3
BT_DEV_WAKE
21B3 21C7 24C6
BT_HOST_WAKE
21B3 21C7 24B3
BT_PWR_EN
21B5 62B3
BT_AUDIO_SYNC
17B4 21C2 21C7
15
DEBUG CONNECTORS
J3750
505070-1222
M-ST-SM
UART_WLAN_R2D
21C6 25A6
NC
WLAN_HOST_WAKE
21B6 21D7 24B3
WLAN_PWR_EN
21B5 62B3
PCH_WLAN_PERST_L
17D3
BOM_COST_GROUP=WIRELESS
NC
15
WIFI_DBG
1413
21
UART_BT_BUF_D2R
43
65
UART_BT_BUF_RTS_L
87
UART_BT_LH_R2D
109
UART_BT_LH_D2R
1211
NC
16
1413
21
43
65
87
109
1211
16
UART_WLAN_D2R
UART_WLAN_R2D_RTS_L
UART_WLAN_D2R_CTS_L
PCH_WLAN_CLKREQ_R_L
WLAN_AUDIO_SYNC
PMU_CLK32K_WLANBT
SYNC_MASTER=myEE SYNC_DATE=03/01/2019
PAGE TITLE
20C6 21C3
20C6 21C3
21C3 25A6
21C3 25B6
21C6 25A6
21C6 25A6
21C6 25A6
17C6 21C3
17B4 21C5 21D7 23D2
21A4 21B4
WIFI/BT: MODULE 1
DRAWING NUMBER
051-05198
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
REVISION
6.0.0
BRANCH
evt-3
PAGE
37 OF 150
SHEET
21 OF 109
B
A
SIZE
D
8
67
35 4
2
1
D
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C
B
A
10
13
27
31
43
45
46
47
48
50
51
64
66
71
73
75
77
80
86
88
90
92
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
4
7
OMIT_TABLE
U3730
LBEE5ZZ1HP-049
LGA
SYM 2 OF 3
CRITICAL
GND
THRM_PAD
THRM_PAD
154
155
156
157
158
160
162
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
OMIT_TABLE
U3730
LBEE5ZZ1HP-049
LGA
SYM 3 OF 3
CRITICAL
THRM_PAD THRM_PAD
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
678
3 245
RF_TUNING
CRITICAL
1
L3811
1.4NH+/-0.1NH-1.1A
21
0201
RF_TUNING
CRITICAL
L3814
2.5NH+/-0.1NH-0.6A
21
0201
RF_TUNING
CRITICAL
NO STUFF
1
C3810
0.2PF
+/-0.05PF
25V
2
COG-CERM
0201
NO_TEST=1NO_TEST=1
50_G_0_MATCH50_G_0_DIPLEXER
1
NOSTUFF
L3813
5.1NH-3%-0.4A
0201
2
21D6
D
21D6
RF_TUNING
CRITICAL
J3810
20449-001E-03
F-ST-SM
4
3
2
1
NO_TEST=1
50_0_ANT
NO STUFF
C3817
0.2PF
+/-0.05PF
COG-CERM
25V
0201
CORE0 DIPLEXER AND MATCHING
2
RF_TUNING
COM
RF_TUNING
CRITICAL
L3810
1.2NH-+/-0.05NH-1.1A-0.04OHM
21
0201
1
2
NOSTUFF
1
C3816
0.2PF
+/-0.05PF
25V
2
COG-CERM
0201
DPX205950DT-9063B3SJ
NO_TEST=1
50_0_COM
U3810
0805
CRITICAL
GND
5
3
1
HI
LO
NO_TEST=1 NO_TEST=1
50_A_0_DIPLEXER 50_A_0_MATCH
NO STUFF
C3812
0.2PF
+/-0.05PF
COG-CERM
4
6
NO STUFF
C3815
+/-0.05PF
COG-CERM
1
25V
2
0201
0.2PF
25V
0201
1
2
L3821
RF_TUNING
CRITICAL
J3820
20449-001E-03
F-ST-SM
4
3
2
1
NO_TEST=1
50_1_ANT
NO STUFF
C3827
0.2PF
+/-0.05PF
COG-CERM
25V
0201
CORE1 DIPLEXER AND MATCHING
2
RF_TUNING
U3820
CRITICAL
COM
5
RF_TUNING
CRITICAL
L3820
1.2NH-+/-0.05NH-1.1A-0.04OHM
21
0201
1
2
NOSTUFF
1
C3826
0.2PF
+/-0.05PF
25V
2
COG-CERM
0201
DPX205950DT-9063B3SJ
NO_TEST=1
50_1_COM
0805
GND
3
1.2NH-+/-0.05NH-1.1A-0.04OHM
21
NO STUFF
25V
0201
25V
0201
1
2
2.5NH+/-0.1NH-0.6A
1
2
C3822
0.2PF
+/-0.05PF
COG-CERM
4
HI
6
LO
1
NO_TEST=1
50_G_1_DIPLEXER
NO STUFF
C3825
0.2PF
+/-0.05PF
COG-CERM
0201
RF_TUNING
CRITICAL
L3824
21
0201
RF_TUNING
CRITICAL
50_A_1_MATCH50_A_1_DIPLEXER
1
2
1
2
NO_TEST=1NO_TEST=1
NO STUFF
C3820
0.2PF
+/-0.05PF
25V
COG-CERM
0201
NO_TEST=1
50_G_1_MATCH
NOSTUFF
L3823
5.1NH-3%-0.4A
0201
21D6
C
21D6
L3831
2.2NH+/-0.1NH-0.6A
21
0201-1
RF_TUNING
CRITICAL
L3834
21
0201
NO_TEST=1
50_G_2_MATCH
NO STUFF
1
C3830
0.2PF
+/-0.05PF
25V
2
COG-CERM
0201
1
NOSTUFF
L3833
5.1NH-3%-0.4A
0201
2
21C6
21C6
B
A
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
RF_TUNING
CRITICAL
J3830
20449-001E-03
F-ST-SM
4
3
2
1
NO_TEST=1
50_G_2_DIPLEXER
25V
0201
25V
0201
1
2
1.2NH-+/-0.05NH-1.1A-0.04OHM
1
2
PAGE TITLE
CORE2/Aux DIPLEXER AND MATCHING
RF_TUNING
CRITICAL
L3830
NO_TEST=1 NO_TEST=1
50_2_ANT 50_A_2_MATCH
NO STUFF
C3837
0.2PF
+/-0.05PF
25V
COG-CERM
0201
1.2NH-+/-0.05NH-1.1A-0.04OHM
21
0201
1
2
NOSTUFF
1
C3836
0.2PF
+/-0.05PF
25V
2
COG-CERM
0201
NO_TEST=1
50_2_COM
2
DPX205950DT-9163C2SJ
5
3
COM
CRITICAL
0805
U3830
RF_TUNING
GND
1
4
LO
6
HI
50_A_2_DIPLEXER
C3832
0.2PF
+/-0.05PF
COG-CERM
NO STUFF
NO_TEST=1
NO STUFF
C3835
0.2PF
+/-0.05PF
COG-CERM
WIFI/BT: MODULE 2
SIZE
D
BOM_COST_GROUP=WIRELESS
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
38 OF 150
SHEET
22 OF 109
8
67
35 4
2
1
Note 1) IPU represents SW configured state, not HW default
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3 245
1
D
C
76B8
76D8
76D8
46B1
34A7 34C6
12A6 12C5
32B8
33A1 33A7
76A8
31C8
47B7 47C8 48B7 48C8
47B7 47D8 48B7 48D7
31C8
51A7
67C7 68C7 69C7 70C7 72D3
34A7 34C5
31D8
31D8
31D8
32A6 71B7 77A2
35D4 77D8
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
IN
IN
IN
OUT
IN
NC_PLCAM_TX_THROTTLE
NC_GNSS_HOST_TIME
CODEC_INT_L
SE_CTLR_FW_DWLD
PCH_SOC_SYNC
MESA_INT
MESA_PWR_EN
NC_WLAN_DEV_WAKE
BOARD_REV0
SPKRAMP_INT_L
SPKRAMP_RESET_L
BOARD_REV1
TPAD_SPI_EN
SSD_BFH
SE_DEV_WAKE
BOOT_CONFIG0
BOOT_CONFIG1
BOOT_CONFIG2
SSD_PMU_RESET_L
DFR_DISP_INT
A13
A12
B12
AJ36
R36
AB36
AC36
V34
V36
AA36
U36
U35
V32
R32
L36
M33
J33
P33
K32
J32
AA34
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 3 OF 18
GPIO/TEST/MISC
(IPD)
(MESA:IPD, GFX:IPU)
(IPU)
(IPD)
(IPD)
(IPD)
TMR32_PWM0
TMR32_PWM1
TMR32_PWM2
CFSB
FORCE_DFU
DFU_STATUS
HOLD_RESET
ANALOGMUX_OUT
TST_CLKOUT
TESTMODE
DROOP
SOCHOT
XO0
XI0
L33
L35
K36
K34
W32
V33
J34
AN36
P32
C12
L32
L34
AV23
AV24
WLAN_AUDIO_SYNC_R
DFR_PWR_EN
SOC_KBD_BKLT_PWMNC_GNSS_DEV_WAKE
PMU_ACTIVE_READY
SOC_FORCE_DFU
SOC_DFU_STATUS
SOC_HOLD_RESET
TEST_SOC_AMUXOUT
TEST_SOC_TST_CLKOUT
SOC_TESTMODE
PMU_DROOP_L
SOC_SOCHOT_L
SOC_XTAL24M_OUT
SOC_XTAL24M_IN
35C8
OUT
32A8
OUT
19C3 62A6 62D6 77B2 81A8
IN
19D3 62C7 77D4 81B7
IN
19D3 77D4 81A4
OUT
23A7
23A7
62A6 62D3
IN
23A7 62D6
OUT
77B2 80A8
1
R3940
511K
1%
1/20W
MF
201
2
1/20W MF 02015%
76D6
76D6
NOSTUFF
R3900
0
R3941
0
24MHZ-30PPM-9.5PF-60OHM
21
WLAN_AUDIO_SYNC
21
SOC_XTAL24M_OUT_R
0201MF1/20W 5%
Y3940
1.60X1.20MM-SM
17B4 21A2 21C5 21D7
IN
D
C
B
31B6
31B8
49D7
49D7
49D7
77A4 81C2
77A4 81C2
BI
OUT
OUT
OUT
OUT
BI
BI
I2C_SEP_SDA
I2C_SEP_SCL
SEP_CAM_DISABLE_L
SEP_DMIC_DISABLE_L
SEP_DISABLE_STROBE
USB_SOC_P
USB_SOC_N
NC_SOC_USB_ID
76A8
SOC_USB_VBUS
23A7 77D4
SOC_USB_REXT
1
R3960
200
1%
1/20W
MF
201
2
AV8
SEP_I2C0_SDA
AT7
SEP_I2C0_SCL
AU9
SEP_SPI0_MISO
AV9
SEP_SPI0_MOSI
AT8
SEP_SPI0_SCLK
B23
USB_DP
A23
USB_DM
D23
USB_ID
E23
USB_VBUS
F22
USB_REXT
(IPD)
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 7 OF 18
SEP/USB/DDR
DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF
DDR0_ZQ
DDR3_ZQ
DDR0_RET*
DDR1_RET*
DDR2_RET*
DDR3_RET*
DDR0_SYS_ALIVE
DDR1_SYS_ALIVE
DDR2_SYS_ALIVE
DDR3_SYS_ALIVE
H3
H35
AL3
AL35
N2
AF36
H4
H34
AL4
AL34
G3
G35
AM3
AM35
240
1%
1/20W
MF
201
1
2
R3970
SOC_DDR0_RREF
SOC_DDR1_RREF
SOC_DDR2_RREF
SOC_DDR3_RREF
SOC_DDR0_ZQ
SOC_DDR3_ZQ
AON_SLEEP1_RESET_L
PMU_SYS_ALIVE
R3971
240
1%
1/20W
MF
201
IN
IN
C3940
12PF
5%
25V
CERM
0201
240
1%
1/20W
MF
201
1
2
1
2
R3972
24C3
24B6 62A6 62C6 71B7 77B2 80A8
1
2
R3973
240
1%
1/20W
MF
201
NC GND
4312
1
2
1
C3941
12PF
5%
25V
2
CERM
0201
R3974
240
1%
1/20W
MF
201
PP1V1_SLPDDR
240
1%
1/20W
MF
201
1
2
1
2
R3975
74C4
B
A
PP1V8_AWAKE
R3932
PP1V8_SLPS2R
R3934
R3937
R3939
8
117S0201
0
10K
10K
47K
SYNC_MASTER=myEE SYNC_DATE=03/01/2019
PAGE TITLE
74B6 32A7 31D6 31D5 31C6 26A7
21
5%
21
21
21
MF1/20W 0201
81B8 74C6 32A7
MF1/20W 2015%
MF1/20W 2015%
MF1/20W 2015%
SOC_USB_VBUS
SOC_HOLD_RESET
SOC_TESTMODE
SOC_SOCHOT_L
23B6 77D4
23C3
23C3
23C3 62D6 77B2 80A8
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
67
35 4
IV ALL RIGHTS RESERVED
2
SoC GPIO/SEP/USB/DDR/Test
SIZE
Apple Inc.
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
39 OF 150
SHEET
23 OF 109
1
A
D
D
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3 245
1
OMIT_TABLE
CRITICAL
U3900
H9M
76B6
12C5 17D6 80A7
76D8
76B8
37C6
37C6
OUT
IN
IN
OUT
OUT
BI
NC_WLAN_CONTEXT_A
NC_WLAN_CONTEXT_B
NC_GYRO_INT1
NC_GYRO_INT2
SE_HOST_WAKE_R
SOC_PERST_L
NC_ALTIMETER_INT
NC_SPI_GYRO_CS_L
NC_SPI_ALTIMETER_CS_L
NC_I2C_AOP_SCL
NC_I2C_AOP_SDA
D3
AOP_FUNC[0]
F4
AOP_FUNC[1]
M6
AOP_FUNC[2]
D4
AOP_FUNC[3]
F3
AOP_FUNC[4]
K6
AOP_FUNC[5]
E4
AOP_FUNC[6]
J3
AOP_FUNC[7]
H6
AOP_FUNC[8]
N6
AOP_I2C0_SCL
G5
AOP_I2C0_SDA
(IPD)
(IPD)
(IPD)
BGA
SYM 6 OF 18
AOP
(IPU)
(IPU)
(IPU)
(IPD)
(IPD)
AOP_PDM_CLK0
AOP_PDM_CLK1
AOP_PDM_CLK2
AOP_PDM_CLK3
AOP_PDM_CLK4
AOP_PDM_DATA0
AOP_PDM_DATA1
AOP_SPI_MOSI
AOP_SPI_SCLK
AOP_SPI_MISO
P6
K2
J6
L6
L5
J5
K4
D2
F2
E2
PDM_DMIC_CLK0_R
PDM_DMIC_CLK1_R
TP_SMC_FIXTURE_MODE_L
NC_PLCAM_PROX_INT_L
NC_PLCAM_ROMEO_B2B_DETECT
PDM_DMIC_DATA0
PDM_DMIC_DATA1
NC_SPI_AOP_SENSOR_MOSI_R
NC_SPI_AOP_SENSOR_CLK_R
NC_SPI_AOP_SENSOR_MISO
OUT
OUT
IN
IN
IN
IN
IN
32B8
32B8
76D6 77B2
76C8
76C8
49D1
49C1
D
C
62C6
62C6
OUT
BI
SPMI_CLK
R4036
R4037
PLACE_NEAR=U3900.AD6:5MM
PLACE_NEAR=U7800.M7:5MM
20
21
21
MF1/20W5% 201
2015%201/20W MF
32B8
31B4
76B8
76B8
15B1 64A5
46B1
21B3 21C7
76C8
76D8
32B8
76B8
76D8
62C6
62D7 77A4
49D6 62A6 62D6 77B2 80A7
IN
IN
IN
OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
DFR_TOUCH_INT_L
CPU_SMC_THRMTRIP_L
NC_SMC_GFX_SELF_THROTTLE
NC_SMC_TOPBLK_SWP_L
XDP_PRESENT_L
CODEC_RESET_L
BT_DEV_WAKE
NC_PCIEDN_WAKE_L
NC_ENET_LOW_PWR
TPAD_SPI_INT_L
NC_SDCONN_STATE_CHANGE_L
NC_ENET_MEDIA_SENSE
PMU_INT_L
SPMI_CLK_R
SPMI_DATA_RSPMI_DATA
PMU_CLK32K_SOC
SOC_COLD_RESET_L
4.7K
R4039
5% 201
1/20W MF
21
PMU_COLD_RESET_L
AL6
AON_GPIO0
AE6
AON_GPIO1
AT5
AON_GPIO2
AN4
AON_GPIO3
AK4
AON_GPIO4
AV5
AON_GPIO5
AR3
AON_GPIO6
AG6
AON_GPIO7
AU5
AON_GPIO8
AP2
AON_GPIO9
AR4
AON_GPIO10
AN3
AON_GPIO11
AT6
AON_GPIO12
AD6
AON_SPMI_SCLK
AR2
AON_SPMI_SDATA
AR5
RT_CLK32768
AK2
COLD_RESET*
AK3
CFSB_AON
(IPU)
(IPD)
(IPU)
(IPU)
(IPD)
(IPU)
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 5 OF 18
AON
(IPU)
(IPU)
(IPU)
(IPD)
(IPU)
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
JTAG_SEL
DOCK_CONNECT
AON_SWD0_TMS
AON_SWD1_TMS
AON_SWD01_TCK
WDOG
AON_SLEEP1_RESET*
AK6
AN5
AH6
AP4
AJ6
AC6
AN2
AJ4
AH4
AJ2
AJ5
AF6
SWD_SOC_SWCLK
SWD_SOC_SWDIO
TP_JTAG_SOC_TDI
TP_JTAG_SOC_TDO
TP_JTAG_SOC_TRST_L
SOC_JTAG_SEL
(DAP=0, TAP=1)
SOC_DOCK_CONNECT
NC_SWD_WLAN_SWDIO
NC_MESA_MENUKEY_L
NC_SWD_WLAN_SWDCLK
SOC_WDOG
AON_SLEEP1_RESET_L
IN
77C4
77C4
77C4
24A7
IN
IN
OUT
OUT
OUT
17A6 77D4
17A6 77C4
BI
19D3 24A7 77D4
76A8
BI
76D8
76A8
62D6 77B2 80A7
23B3
C
B
A
PP1V8_S5
R4046
R4047
R4054
R4055
R4056
R4057
R4059
10K
100K
100K
100K
100K
100K
100K
75B1 17B7 14A7 12A7
21
5% 201
21
21
21
21
21
21
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
5% 201
1/20W MF
SOC_JTAG_SEL
SOC_DOCK_CONNECT
ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CS_L
24C3
19D3 24C3 77D4
12D2 24B6
12D2 24B6
12D2 24B6
12D2 24B6
12D2 24B6
12D2 24A7
12D2 24A7
12D2 24A7
12D2 24A7
12D1
12D2 24A7
12D2
31C4
31D4
31C5
31C5
31B5
31C5
16B2 77C2 81A8 81C3
31A6 32B1 54C2
23A3 62A6 62C6 71B7 77B2 80A8
19C3 36B3
19D3 36B3
36C3
36C3
36B8
36B8
36D6
36D6
36D3 77C4
36D3 77C4
36C6
36C6
36B8
36B8
BI
BI
BI
BI
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
BI
IN
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
ESPI_IO<0>
ESPI_IO<1>
ESPI_IO<2>
ESPI_IO<3>
ESPI_CLK60M
ESPI_CS_L
ESPI_RESET_L
SMC_PECI_RX
SMC_PECI_TX
SMC_PCH_PWROK
SMC_PCH_SYS_PWROK
SMC_RSMRST_L
SMC_SYSRST_L
PM_SLP_S0_L
SMC_PROCHOT_L
PMU_SYS_ALIVE
I2C_UPC_SCL
I2C_UPC_SDA
I2C_SNS0_S0_SCL
I2C_SNS0_S0_SDA
I2C_SNS1_S0_SCL
I2C_SNS1_S0_SDA
I2C_DISP_SCL
I2C_DISP_SDA
I2C_PWR_SCL
I2C_PWR_SDA
I2C_SNS_G3S_SCL
I2C_SNS_G3S_SDA
I2C_SSD_SCL
I2C_SSD_SDA
V2
SMC_ESPI_IO0
U3
SMC_ESPI_IO1
U4
SMC_ESPI_IO2
V8
SMC_ESPI_IO3
U2
SMC_ESPI_CLK
V7
SMC_ESPI_CS*
V6
SMC_ESPI_RESET*
M5
SMC_PECI_IN
T6
SMC_PECI_OUT
W7
PCH_PWROK
W8
SYS_PWROK
W6
RSMRST*
W4
SYS_RESET*
AA4
SLP_S0B
R5
PROCHOT*
AA6
SYS_ALIVE
M3
SMC_I2C0_SCL
J4
SMC_I2C0_SDA
N4
SMC_I2C1_SCL
P4
SMC_I2C1_SDA
U5
SMC_I2C2_SCL
M2
SMC_I2C2_SDA
U6
SMC_I2C3_SCL
R4
SMC_I2C3_SDA
P3
SMC_I2C4_SCL
T4
SMC_I2C4_SDA
R2
SMC_I2C5_SCL
P2
SMC_I2C5_SDA
R3
SMC_I2C6_SCL
T2
SMC_I2C6_SDA
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 9 OF 18
SMC
(IPD)
(IPD)
(IPD)
(IPU)
(IPU)
(IPU)
(IPD)
(IPU)
(IPD)
(IPD)
(IPD)
SMC_GPIO0
SMC_GPIO1
SMC_GPIO2
SMC_GPIO3
SMC_GPIO4
SMC_GPIO5
SMC_GPIO6
SMC_GPIO7
SMC_GPIO8
SMC_GPIO9
SMC_GPIO10
SMC_GPIO11
SMC_GPIO12
SMC_GPIO13
SMC_GPIO14
SMC_GPIO15
SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7
REFP_ADC
REFM_ADC
SMC_PWM0
SMC_TACH0
SMC_PWM1
SMC_TACH1
SMC_PWM2
SMC_UART0_RXD
SMC_UART0_TXD
SWD_OUT0_TCK
SWD_OUT0_TMS
SWD_OUT1_TCK
SWD_OUT1_TMS
Y4
Y8
Y5
AA2
Y7
Y6
AB2
AD5
AD2
AB4
AC2
AC3
AA8
AB3
AE2
L4
AG2
AC4
AH3
AD4
AB6
AH2
AG4
AC5
AF4
AG3
J2
L3
R6
L2
M4
V4
V5
AE3
AA5
AF2
AA7
CODEC_WAKE_L
BT_HOST_WAKE
WLAN_HOST_WAKE
DP_INT_HPD_MASK
SMC_LID_RIGHT
NC_PCC_EVENT
NC_TPAD_VIBE_L
TPAD_KBD_WAKE_L
SMC_LID_LEFT
SMC_DPWROK1V8
NC_DISP_GCON_INT_L
NC_SOC_PCH_GCON_INT_L
TPAD_ACTUATOR_DISABLE_L
NC_TBT_WAKE_L
UPC_I2C_INT_L
DP_INT_HPD_L
SMC_CPU_HS_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_DCIN_ISENSE
SMC_DCIN_VSENSE
SMC_PP3V3_WLANBT_ISENSE
SMC_CPUVCCIN_ISENSE
SMC_CPUVCCIN_VSENSE
PP1V25_SLPS2R_SMC_AVREF
GND_SMC_AVSS
SMC_FAN_0_PWM
SMC_FAN_0_TACH
SMC_FAN_1_PWM
SMC_FAN_1_TACH
NC_SMC_LED_ONEWIRE
SMC_DEBUGPRT_RX
SMC_DEBUGPRT_TX
SSD0_SWCLK
SSD0_SWDIO
NC_SSD1_SWCLK_UART_R2D
NC_SSD1_SWDIO_UART_D2R
46B1
IN
21B3 21C7
IN
21A3 21B6 21D7
IN
32A8
OUT
32C3
IN
76D8
IN
76A8
OUT
32B8
IN
BI
32A8
OUT
76D8
IN
76D8
OUT
BI
76A6
IN
19C3
IN
32A8
IN
44D2
IN
44D2
IN
44D2
IN
44D2
IN
44D2
IN
44D2
IN
44D2
IN
44D2
IN
31A6
PLACE_NEAR=U3900.AF3:4MM
44C6
OUT
19B3 44C6
IN
44C8
OUT
19B3 44C8
IN
BI
19D3 77C4
IN
19D3 77C4
OUT
32B8 67C7 68C7 69C7 70C7 72D5
OUT
BI
76B8
OUT
BI
32D2
32A8
XW4089
SM
21
76B8
32B8 67C7 68C7 69C7 70C7 72D5
76B8
BOM_COST_GROUP=SOC
PAGE TITLE
SoC AOP/AON/SMC
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
40 OF 150
SHEET
24 OF 109
B
A
SIZE
D
8
67
35 4
2
1
D
www.haojiyoubbs.com
QQ微信：181806465
678
3 245
1
OMIT_TABLE
CRITICAL
U3900
H9M
66A6 78D6
IN
66A6 78D6
IN
76D6
IN
76D6
IN
66B6 78D6
IN
66B6 78D6
IN
76D6
IN
76D6
IN
76D6
IN
76D6
IN
76D6 76C8
IN
76D6
IN
35D1
OUT
35C1
OUT
35D1
OUT
35D1
OUT
MIPI_FTCAM_DATA_P<0>
MIPI_FTCAM_DATA_N<0>
GND
GND
MIPI_FTCAM_CLK_P
MIPI_FTCAM_CLK_N
GND
GND
GND
GND
GND NC_PLCAM_TX_CLK12M_R
GND
MIPI_DFR_DATA_P
MIPI_DFR_DATA_N
MIPI_DFR_CLK_P
MIPI_DFR_CLK_N
SOC_MIPI0C_REXT
SOC_MIPI1C_REXT
SOC_MIPID_REXT
B27
MIPI0C_DATA0_P
A27
MIPI0C_DATA0_N
B25
MIPI0C_DATA1_P
A25
MIPI0C_DATA1_N
B26
MIPI0C_CLK_P
A26
MIPI0C_CLK_N
B28
MIPI1C_DATA0_P
A28
MIPI1C_DATA0_N
B30
MIPI1C_DATA1_P
A30
MIPI1C_DATA1_N
B29
MIPI1C_CLK_P
A29
MIPI1C_CLK_N
B33
MIPID_DATA0_P
A33
MIPID_DATA0_N
B32
MIPID_CLK_P
A32
MIPID_CLK_N
F23
MIPI0C_REXT
F26
MIPI1C_REXT
F27
MIPID_REXT
BGA
SYM 4 OF 18
ISP
(IPD)
(IPD)
ISP_I2C0_SDA
ISP_I2C0_SCL
ISP_I2C1_SDA
ISP_I2C1_SCL
SENSOR0_CLK
SENSOR0_RST
SENSOR0_ISTRB
SENSOR1_CLK
SENSOR1_RST
SENSOR1_ISTRB
SENSOR2_CLK
SENSOR2_RST
SENSOR_INT
DISP_TE
DISP_VSYNC
CLK32K_OUT
AF32
AH36
AB32
AG32
AK35
AK34
AJ33
AD33
AC32
AC34
AD32
AJ32
AA33
H32
T36
AK33
I2C_FTCAM_SDA
I2C_FTCAM_SCL
NC_I2C_PLCAM_SDA
NC_I2C_PLCAM_SCL
NC_FTCAM_CLK12M_R
NC_FTCAM_RESET_L
DFR_TOUCH_RESET_L
NC_PLCAM_RX_CLK12M_R
NC_PLCAM_RX_RESET_L
DFR_DISP_RESET_L
NC_PLCAM_TX_RESET_L
NC_PLCAM_TX_INT
DFR_DISP_TE
BOARD_REV2
DFR_TOUCH_CLK32K_RESET_L
BI
37B4
OUT
BI
37D6
OUT
76D8
OUT
76D8
OUT
35B7 35C7 77C8
OUT
76C8
OUT
76C8
OUT
35B7 35C4 77D8
OUT
OUT
76B8
OUT
76C8
IN
35D4 77D8
IN
31C8
IN
35C5 77C8
OUT
37B6
37D6
D
C
B
1
R4100
4.02K
1%
1/20W
MF
201
2
1
R4101
4.02K
1%
1/20W
MF
201
2
37D8
37D8
37C8
37C8
37C8
37C8
37B8
37B8
37A8
37A8
37D6
37D6
48C3 77B7
47C3 77C7
76D6 77C4
76D6 77C4
34A7 34C6
34A7 34C6
34A7 34C6
34A7 34C6
76A8
76A8
76A8
76A8
21B2 21C3
21B2 21C3
76A8
76A8
21B2 21C6
21B3 21C6
21A2 21C6
21A2 21C6
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
IN
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
1
R4102
4.02K
1%
1/20W
MF
201
2
I2C_SPKRAMP_L_SDA
I2C_SPKRAMP_L_SCL
I2C_SPKRAMP_R_SDA
I2C_SPKRAMP_R_SCL
I2C_CODEC_SDA
I2C_CODEC_SCL
I2C_ALS_SDA
I2C_ALS_SCL
I2C_DFR_SDA
I2C_DFR_SCL
NC_I2C_SOC_5_SDA
NC_I2C_SOC_5_SCL
SPKR_ID1
SPKR_ID0
TP_SOC_DEBUGPRT_RX
TP_SOC_DEBUGPRT_TX
UART_SE_D2R
UART_SE_R2D
UART_SE_D2R_CTS_L
UART_SE_R2D_RTS_L
NC_UART_BT_D2R
NC_UART_BT_R2D
NC_UART_BT_D2R_CTS_L
NC_UART_BT_R2D_RTS_L
UART_BT_LH_D2R
UART_BT_LH_R2D
NC_UART_GNSS_D2R_CTS_L
NC_UART_GNSS_R2D_RTS_L
UART_WLAN_D2R
UART_WLAN_R2D
UART_WLAN_D2R_CTS_L
UART_WLAN_R2D_RTS_L
AE35
AD35
AF34
AG35
M34
R33
Y32
AE34
T34
U32
R35
U33
P34
R34
Y33
Y34
B15
A15
C15
D15
J36
J35
N32
M32
M36
N36
M35
U34
B14
A14
C14
C13
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
I2C2_SDA
I2C2_SCL
I2C3_SDA
I2C3_SCL
I2C4_SDA
I2C4_SCL
I2C5_SDA
I2C5_SCL
I2C6_SDA
I2C6_SCL
UART0_RXD
UART0_TXD
UART1_RXD
UART1_TXD
UART1_CTS*
UART1_RTS*
UART2_RXD
UART2_TXD
UART2_CTS*
UART2_RTS*
UART3_RXD
UART3_TXD
UART3_CTS*
UART3_RTS*
UART4_RXD
UART4_TXD
UART4_CTS*
UART4_RTS*
(IPU)
(IPU)
(IPU)
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 2 OF 18
I2C/UART/SPI/I2S
(IPU)
(IPD)
(IPD)
(IPD)
(IPD)
SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN
SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN
SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN
I2S0_DIN
I2S0_DOUT
I2S0_BCLK
I2S0_LRCK
I2S0_MCK
I2S1_DIN
I2S1_DOUT
I2S1_BCLK
I2S1_LRCK
I2S1_MCK
I2S2_DIN
I2S2_DOUT
I2S2_BCLK
I2S2_LRCK
I2S2_MCK
I2S3_DIN
I2S3_DOUT
I2S3_BCLK
I2S3_LRCK
I2S3_MCK
AR9
AR7
AU7
AT9
P36
N34
P35
T32
A19
A20
C19
A18
C17
C18
B18
A17
AC33
AG34
AA32
AG33
AR35
B20
C20
C21
A21
D21
AH34
AB34
AF33
AH35
AR33
AD36
AB35
AE36
W34
AG36
SPI_SOCROM_MISO
SPI_SOCROM_MOSI_R
SPI_SOCROM_CLK_R SPI_SOCROM_CLK
SPI_SOCROM_CS_L
SPI_TPAD_MISO
SPI_TPAD_MOSI_R
SPI_TPAD_CLK_R
SPI_TPAD_CS_L
SPI_MESA_MISO
SPI_MESA_MOSI_R
SPI_MESA_CLK_R
WLAN_JTAG_TDI
SPI_DFR_MISO
SPI_DFR_MOSI_R
SPI_DFR_CLK_R
SPI_DFR_CS_L
I2S_SPKRAMP_L_D2R
I2S_SPKRAMP_L_R2D_R
I2S_SPKRAMP_L_BCLK_R
I2S_SPKRAMP_L_LRCLK
NC_DFR_TOUCH_RSVD
I2S_SPKRAMP_R_D2R
I2S_SPKRAMP_R_R2D_R
I2S_SPKRAMP_R_BCLK_R
I2S_SPKRAMP_R_LRCLK
NC_PCHROM_SW_EN
76B8
I2S_CODEC_D2R
I2S_CODEC_R2D_R
I2S_CODEC_BCLK_R
I2S_CODEC_LRCLK
NC_I2S_CODEC_MCLK
NC_I2S_HAWKING_D2R
NC_I2S_CODEC1_R2D_R
NC_I2S_HAWKING_BCLK_R
NC_I2S_HAWKING_LRCLK
NC_I2S_CODEC1_MCLK
31B1 31C8
IN
31B4
OUT
31C8 32B6
IN
32C8
OUT
32C8
OUT
51D8
OUT
33A1 33D8
IN
32B8
OUT
32B8
OUT
21A5
OUT
32B6
IN
32B8
OUT
32B8
OUT
35D7 77D8
OUT
47B8 47C8 48B8 48C8
IN
32C8
OUT
32C8
OUT
32C6
OUT
76D8
BI
32A6
IN
32C8
OUT
32C8
OUT
32C6
OUT
46B1
IN
32C8
OUT
32C8
OUT
32C6
OUT
76D8
OUT
76D8
IN
76D8
OUT
76D8
OUT
76D8
OUT
76D8
OUT
R4171
R4172
PLACE_NEAR=U3900.AR7:5MM
PLACE_NEAR=U3900.AU7:5MM
20
20
21
21
MF1/20W
SPI_SOCROM_MOSI
2015%
MF1/20W
2015%
OUT
OUT
C
31B1 31C8
31B4 31C8
B
A
8
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
PAGE TITLE
A
SoC ISP/I2C/UART/SPI/I2S
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
41 OF 150
SHEET
25 OF 109
1
SIZE
D
678
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QQ微信：181806465
3 245
1
OMIT_TABLE
CRITICAL
D
14D6
14D6
14D6
14D6
14D6
14D6
14D6
14D6
17B5
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PCIE_SOC_D2R_P<0>
PCIE_SOC_D2R_N<0>
PCIE_SOC_D2R_P<1>
PCIE_SOC_D2R_N<1>
PCIE_SOC_D2R_P<2>
PCIE_SOC_D2R_N<2>
PCIE_SOC_D2R_P<3>
PCIE_SOC_D2R_N<3>
SOC_CLKREQ_L
(All Caps)
GND_VOID=TRUE
C4210
0.22UF
C4211
0.22UF
C4212
0.22UF
C4213
0.22UF
C4214
0.22UF
C4215
0.22UF
C4216
0.22UF
C4217
0.22UF
R4218
100
21
21
21
21
21
21
21
21
6.3V X5R 020120%
6.3V X5R
6.3V X5R 020120%
6.3V X5R
6.3V X5R
6.3V X5R
6.3V X5R
6.3V X5R
21
5% 2011/20W MF
U3900
H9M
PCIE_SOC_D2R_C_P<0>
PCIE_SOC_D2R_C_N<0>
020120%
32D6
32D6
IN
IN
PCIE_SOC_R2D_P<0>
PCIE_SOC_R2D_N<0>
PCIE_SOC_D2R_C_P<1>
PCIE_SOC_D2R_C_N<1>
020120%
020120%
32D6
32D6
IN
IN
PCIE_SOC_R2D_P<1>
PCIE_SOC_R2D_N<1>
PCIE_SOC_D2R_C_P<2>
PCIE_SOC_D2R_C_N<2>
020120%
020120%
32D6
32C6
IN
IN
PCIE_SOC_R2D_P<2>
PCIE_SOC_R2D_N<2>
PCIE_SOC_D2R_C_P<3>
PCIE_SOC_D2R_C_N<3>
020120%
32C6
32C6
IN
IN
PCIE_SOC_R2D_P<3>
PCIE_SOC_R2D_N<3>
SOC_CLKREQ_R_L
14A6 78D8
IN
14A6 78D8
IN
PCIE_CLK100M_SOC_P
PCIE_CLK100M_SOC_N
SOC_PCIE_UP_REXT
1
R4200
3.01K
1%
1/20W
MF
201
2
B10
PCIE_UP_TX0_P
C10
PCIE_UP_TX0_N
E10
PCIE_UP_RX0_P
F10
PCIE_UP_RX0_N
A9
PCIE_UP_TX1_P
B9
PCIE_UP_TX1_N
D9
PCIE_UP_RX1_P
E9
PCIE_UP_RX1_N
B8
PCIE_UP_TX2_P
C8
PCIE_UP_TX2_N
E8
PCIE_UP_RX2_P
F8
PCIE_UP_RX2_N
A7
PCIE_UP_TX3_P
B7
PCIE_UP_TX3_N
D7
PCIE_UP_RX3_P
E7
PCIE_UP_RX3_N
B21
PCIE_UP_CLKREQ*
G13
PCIE_UP_EXT_REFCLK_P
G12
PCIE_UP_EXT_REFCLK_N
G11
PCIE_UP_REXT
BGA
SYM 1 OF 18
PCIE UP/DN
PCIE_DN_TX0_P
PCIE_DN_TX0_N
PCIE_DN_RX0_P
PCIE_DN_RX0_N
PCIE_DN_TX1_P
PCIE_DN_TX1_N
PCIE_DN_RX1_P
PCIE_DN_RX1_N
PCIE_DN_TX2_P
PCIE_DN_TX2_N
PCIE_DN_RX2_P
PCIE_DN_RX2_N
PCIE_DN_TX3_P
PCIE_DN_TX3_N
PCIE_DN_RX3_P
PCIE_DN_RX3_N
PCIE_DN_REFCLK0_P
PCIE_DN_REFCLK0_N
PCIE_DN_CLKREQ0*
PCIE_DN_PERST0*
PCIE_DN_REFCLK1_P
PCIE_DN_REFCLK1_N
PCIE_DN_CLKREQ1*
PCIE_DN_PERST1*
PCIE_DN_REFCLK2_P
PCIE_DN_REFCLK2_N
PCIE_DN_CLKREQ2*
PCIE_DN_PERST2*
AV31
AU31
AR31
AP31
AU30
AT30
AP30
AN30
AV29
AU29
AR29
AP29
AU28
AT28
AP28
AN28
AP26
AR26
AM33
AN34
AN25
AP25
AN35
AK32
AU26
AV26
AH32
AE32
NC_PCIE_WLAN_R2D_C_P
NC_PCIE_WLAN_R2D_C_N
NC_PCIE_WLAN_D2R_P
NC_PCIE_WLAN_D2R_N
NC_PCIE_ENET_R2D_C_P
NC_PCIE_ENET_R2D_C_N
NC_PCIE_ENET_D2R_P
NC_PCIE_ENET_D2R_N
NC_PCIE_DN2_R2D_CP
NC_PCIE_DN2_R2D_CN
NC_PCIE_DN2_D2RP
NC_PCIE_DN2_D2RN
NC_PCIE_DN3_R2D_CP
NC_PCIE_DN3_R2D_CN
NC_PCIE_DN3_D2RP
NC_PCIE_DN3_D2RN
NC_PCIE_CLK100M_WLAN_P
NC_PCIE_CLK100M_WLAN_N
NC_WLAN_CLKREQ_L
NC_WLAN_PERST_L
NC_PCIE_CLK100M_ENET_P
NC_PCIE_CLK100M_ENET_N
ENET_CLKREQ_L
NC_ENET_RESET_L
NC_PCIE_CLK100M_DN2P
NC_PCIE_CLK100M_DN2N
NC_PCIEDN2_CLKREQ_L
NC_PCIEDN2_RESET_L
OUT
OUT
IN
IN
OUT
OUT
IN
IN
76B8
76B8
76B8
76B8
76B8
76B8
76B8
76B8
OUT
OUT
IN
OUT
OUT
OUT
26A7
OUT
76B8
76B8
76A8
76A8
76C8
76C8
76C8
76C8
76C8
76C8
76C8
76C8
76C8
76C8
76A8
76A8
76C8
76C8
76D8
D
(UID_MODE strap on A00)
C
B
67C2
67C2
67C2 78D8
67C2 78D8
68C2
68C2
68C2
68C2
69C2
69C2
69C2
69C2
70C2
70C2
70C2
70C2
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
PCIE_SSD0_R2D_C_P<0>
PCIE_SSD0_R2D_C_N<0>
PCIE_SSD0_D2R_P<0>
PCIE_SSD0_D2R_N<0>
PCIE_SSD0_R2D_C_P<1>
PCIE_SSD0_R2D_C_N<1>
PCIE_SSD0_D2R_P<1>
PCIE_SSD0_D2R_N<1>
PCIE_SSD0_R2D_C_P<2>
PCIE_SSD0_R2D_C_N<2>
PCIE_SSD0_D2R_P<2>
PCIE_SSD0_D2R_N<2>
PCIE_SSD0_R2D_C_P<3>
PCIE_SSD0_R2D_C_N<3>
PCIE_SSD0_D2R_P<3>
PCIE_SSD0_D2R_N<3>
AU11
AT11
AP11
AN11
AV12
AU12
AR12
AP12
AU13
AT13
AP13
AN13
AV14
AU14
AR14
AP14
PCIE_STG0_TX0_P
PCIE_STG0_TX0_N
PCIE_STG0_RX0_P
PCIE_STG0_RX0_N
PCIE_STG0_TX1_P
PCIE_STG0_TX1_N
PCIE_STG0_RX1_P
PCIE_STG0_RX1_N
PCIE_STG0_TX2_P
PCIE_STG0_TX2_N
PCIE_STG0_RX2_P
PCIE_STG0_RX2_N
PCIE_STG0_TX3_P
PCIE_STG0_TX3_N
PCIE_STG0_RX3_P
PCIE_STG0_RX3_N
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 8 OF 18
PCIE STG 0/1
PCIE_DN_REFCLK3_P
PCIE_DN_REFCLK3_N
PCIE_DN_CLKREQ3*
PCIE_DN_PERST3*
PCIE_DN_EXT_REFCLK_P
PCIE_DN_EXT_REFCLK_N
PCIE_DN_REXT
PCIE_STG1_TX0_P
PCIE_STG1_TX0_N
PCIE_STG1_RX0_P
PCIE_STG1_RX0_N
PCIE_STG1_TX1_P
PCIE_STG1_TX1_N
PCIE_STG1_RX1_P
PCIE_STG1_RX1_N
PCIE_STG1_TX2_P
PCIE_STG1_TX2_N
PCIE_STG1_RX2_P
PCIE_STG1_RX2_N
PCIE_STG1_TX3_P
PCIE_STG1_TX3_N
PCIE_STG1_RX3_P
PCIE_STG1_RX3_N
AT25
AU25
AJ34
AK36
AM27
AM26
AM25
AU16
AT16
AP16
AN16
AV17
AU17
AR17
AP17
AU18
AT18
AP18
AN18
AV19
AU19
AR19
AP19
NC_PCIE_CLK100M_DN3P
NC_PCIE_CLK100M_DN3N
NC_PCIEDN3_CLKREQ_L
NC_PCIEDN3_RESET_L
SOC_PCIE_DN_REXT
R4201
3.01K
1%
1/20W
MF
201
NC_PCIE_SSD1_R2D_C_P<0>
NC_PCIE_SSD1_R2D_C_N<0>
NC_PCIE_SSD1_D2R_P<0>
NC_PCIE_SSD1_D2R_N<0>
NC_PCIE_SSD1_R2D_C_P<1>
NC_PCIE_SSD1_R2D_C_N<1>
NC_PCIE_SSD1_D2R_P<1>
NC_PCIE_SSD1_D2R_N<1>
NC_PCIE_SSD1_R2D_C_P<2>
NC_PCIE_SSD1_R2D_C_N<2>
NC_PCIE_SSD1_D2R_P<2>
NC_PCIE_SSD1_D2R_N<2>
NC_PCIE_SSD1_R2D_C_P<3>
NC_PCIE_SSD1_R2D_C_N<3>
NC_PCIE_SSD1_D2R_P<3>
NC_PCIE_SSD1_D2R_N<3>
76A8
76A8
76A8
76A8
1
2
76C8
OUT
76C8
OUT
76C8
IN
76C8
IN
76C8
OUT
76C8
OUT
76C8
IN
76C8
IN
76C8
OUT
76C8
OUT
76C8
IN
76C8
IN
76C8
OUT
76C8
OUT
76C8
IN
76C8
IN
C
B
A
PP1V8_AWAKE
R4232
47K
67C3 68C3 78C8 78D8
67C3 68C3 78C8 78D8
32A6 67C3
32A6 68C3
69C3 70C3 78C8 78D8
69C3 70C3 78C8 78D8
32A6 69C3
32A6 70C3
32A6 67C7 68C7 69C7 70C7
32B8
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
PCIE_CLK100M_SSD0_01_P
PCIE_CLK100M_SSD0_01_N
SSD0_CLKREQ0_L
SSD0_CLKREQ1_L
PCIE_CLK100M_SSD0_23_P
PCIE_CLK100M_SSD0_23_N
SSD0_CLKREQ2_L
SSD0_CLKREQ3_L
SSD0_PCIE_RESET_L
SSD0_CLK24M_R
AP21
AR21
AT33
AR34
AN22
AP22
AP34
AN33
AR36
AP7
AM14
AM15
PCIE_STG0_REFCLK01_P
PCIE_STG0_REFCLK01_N
PCIE_STG0_CLKREQ0*
PCIE_STG0_CLKREQ1*
PCIE_STG0_REFCLK23_P
PCIE_STG0_REFCLK23_N
PCIE_STG0_CLKREQ2*
PCIE_STG0_CLKREQ3*
PCIE_STG0_PERST*
PCIE_STG0_NANDCLK
PCIE_STG0_EXT_REFCLK_P
PCIE_STG0_EXT_REFCLK_N
PCIE_STG1_REFCLK01_P
PCIE_STG1_REFCLK01_N
PCIE_STG1_CLKREQ0*
PCIE_STG1_CLKREQ1*
PCIE_STG1_REFCLK23_P
PCIE_STG1_REFCLK23_N
PCIE_STG1_CLKREQ2*
PCIE_STG1_CLKREQ3*
PCIE_STG1_PERST*
PCIE_STG1_NANDCLK
PCIE_STG1_EXT_REFCLK_P
PCIE_STG1_EXT_REFCLK_N
AU21
AV21
B17
D18
AT22
AU22
C16
A16
AP36
AV7
AM19
AM20
NC_PCIE_CLK100M_SSD1_01_P
NC_PCIE_CLK100M_SSD1_01_N
NC_SSD1_CLKREQ0_L
NC_SSD1_CLKREQ1_L
NC_PCIE_CLK100M_SSD1_23_P
NC_PCIE_CLK100M_SSD1_23_N
NC_SSD1_CLKREQ2_L
NC_SSD1_CLKREQ3_L
NC_SSD1_PCIE_RESET_L
NC_SSD1_CLK24M_R
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
76C8
76C8
76B8
76B8
76C8
76C8
76B8
76B8
76B8
76B8
PAGE TITLE
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
A
SoC PCIe
SOC_PCIE_STG0_REXT
1
R4250
3.01K
1%
74B6 32A7 31D6 31D5 31C6 23A7
21
MF1/20W
ENET_CLKREQ_L
2015%
26C3
1/20W
MF
201
2
AM16
PCIE_STG0_REXT
PCIE_STG1_REXT
AM21
SOC_PCIE_STG1_REXT
R4251
3.01K
1%
1/20W
MF
201
DRAWING NUMBER
051-05198
1
Apple Inc.
REVISION
SIZE
D
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
2
BOM_COST_GROUP=SOC
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
BRANCH
evt-3
PAGE
42 OF 150
SHEET
26 OF 109
8
67
35 4
2
1
678
www.haojiyoubbs.com
QQ微信：181806465
3 245
1
D
C
Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3
74D6 32D8
PPVDDCPU_AWAKE
0.625V - 1.06V
11.6A Max
C4300
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4305
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4320
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4330
4.3UF
20%
4V
CERM
0402
1
3
C4301
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4306
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4321
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4331
4.3UF
20%
4V
CERM
0402
1
3
C4302
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4307
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4322
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4332
4.3UF
20%
4V
CERM
0402
1
3
C4303
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4308
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4323
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4333
4.3UF
20%
4V
CERM
0402
1
3
C4304
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4309
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4324
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4334
4.3UF
20%
4V
CERM
0402
1
3
AA12
AA14
AA16
AB11
AB13
AB15
AC12
AC14
AC16
AD11
AD13
AD15
AD17
AE10
AE12
AE14
AE16
AE18
P11
P13
P15
P17
R12
R14
R16
T11
T13
T15
U12
U14
U16
V17
W12
W14
W16
Y17
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
OMIT_TABLE
CRITICAL
U3900
H9M
BGA
SYM 10 OF 18
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SENSE
VSS_CPU_SENSE
AA10
AB17
AC10
R10
T17
U10
V11
V13
V15
W10
Y11
Y13
Y15
N18
N17
C4350
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4355
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4351
1
C4356
1
C4360
4.3UF
20%
4V
CERM
0402
1
SOC_VDDCPU_SENSE
NC_SOC_VSSCPU_SENSE
3
4
2
9.1UF
20%
4V
CERM
0402
4
2
4.3UF
20%
4V
CERM
0402
4
2
3
3
OUT
76A8
C4352
9.1UF
20%
4V
CERM
0402
1
4
2
62C3 78D4
PPVDDCPUSRAM_AWAKE
74D6
0.8V - 1.06V
0.9A Max
C4353
9.1UF
20%
4V
CERM
0402
3
1
3
C4354
9.1UF
20%
4V
CERM
0402
1
3
C4357
9.1UF
20%
4V
CERM
0402
1
3
D
4
4
4
2
2
2
C
B
A
74D6 32D8
PP0V82_SLPDDR
5.6A Max
4
4
4
4
4
2
2
2
2
2
OMIT_TABLE
CRITICAL
U3900
H9M
C4370
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4380
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4385
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4371
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4381
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4386
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4372
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4373
9.1UF
20%
4V
CERM
0402
1
3
4
2
AA20
AA22
AA24
AA26
AA28
AC18
AC20
AC22
AC24
AC26
AC28
AE20
AE22
AE24
AE26
AE28
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG28
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AJ26
AJ28
J10
J12
J14
J16
J18
J20
BGA
VDD_SOC VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
SYM 11 OF 18
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC
VDD_SOC_SENSE
VSS_SENSE
J22
J24
J26
J28
L10
L12
L14
L16
L18
L20
L22
L24
L26
L28
N10
N12
N14
N16
N20
N22
N24
N26
N28
R18
R20
R22
R24
R26
R28
U18
U20
U22
U24
U26
U28
W20
W22
W24
W26
W28
AD27
AD28
NC_SOC_VDDSOC_SENSE
NC_SOC_VSSSOC_SENSE
76A8
76A8
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
IV ALL RIGHTS RESERVED
SoC Power 1
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
43 OF 150
SHEET
27 OF 109
B
A
SIZE
D
8
67
35 4
2
1
D
www.haojiyoubbs.com
QQ微信：181806465
C
B
A
678
Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3
PP1V1_SLPDDR
74C4
0.86A Max
PP0V9_SLPDDR
74B4
1.9A Max
74B4 28B3 28A3
PP0V9_SLPDDR
74B4
25mA Max
PP0V9_SLPDDR
330mA Max
C4400
9.1UF
20%
4V
CERM
0402
1
2
C4405
4.3UF
20%
4V
CERM
0402
1
2
C4410
4.3UF
20%
4V
CERM
0402
1
2
9mA Max
PP0V9_SLPDDR
74B4
PP0V9_SLPDDR
74B4
5mA Max
PP0V8_SLPS2R
74D2
102mA Max
20%
4V
0201
20%
4V
0201
K19
K21
K23
K25
K27
M11
M13
M15
M17
M19
M21
M23
M25
M27
P19
P21
P23
P25
P27
T19
T21
T23
T25
T27
V19
V21
V23
V25
V27
Y19
Y21
Y23
Y25
Y27
AL14
AL16
AL12
AK13
AK15
AK17
AL18
AL20
AL22
AK19
AK21
AL17
AL26
AL28
AL30
AK25
AK27
AK29
AK23
AJ15
AL24
AJ21
AJ27
1
2
1
2
C4450
2.2UF
X6S-CERM
C4454
2.2UF
X6S-CERM
3
C4402
9.1UF
20%
4V
CERM
0402
1
3
4
2
C4420
4.3UF
20%
4V
CERM
0402
1
2
C4423
2.2UF
X6S-CERM
0201
C4426
4.3UF
20%
4V
CERM
0402
1
2
4
20%
4
4V
U3900
H9M
AB19
AB21
AB23
AB25
AB27
AD19
AD21
AD23
AD25
AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF25
AF27
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AH27
AK11
3
1
2
3
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
K11
VDD_FIXED
K13
VDD_FIXED
K15
VDD_FIXED
K17
VDD_FIXED
W18
VDD_FIXED_CPU
G22
VDD_FIXED_USB
H23
VDD_FIXED_MIPI
H25
VDD_FIXED_MIPI
H27
VDD_FIXED_MIPI
AB9
VDD_LOW
AD9
VDD_LOW
P9
VDD_LOW
T9
VDD_LOW
V9
VDD_LOW
Y9
VDD_LOW
H11
VDD_FIXED_UP_PCIE_ANA
H13
VDD_FIXED_UP_PCIE_ANA
H15
VDD_FIXED_UP_PCIE_ANA
J15
VDD_FIXED_UP_PCIE_CLK
J11
VDD_FIXED_UP_PCIE_CLK
J13
VDD_FIXED_UP_PCIE_CLK
BGA
SYM 12 OF 18
OMIT_TABLE
CRITICAL
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED
VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_ANA
VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG0_PCIE_CLK
VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_ANA
VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_STG1_PCIE_CLK
VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_ANA
VDD_FIXED_DN_PCIE_CLK
VDD_FIXED_DN_PCIE_CLK
VDD_FIXED_DN_PCIE_CLK
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_REFBUF
C4401
9.1UF
20%
4V
CERM
0402
3
4
1
3
4
2
C4406
4.3UF
20%
4V
CERM
0402
3
4
1
3
4
2
C4411
4.3UF
20%
4V
CERM
0402
3
4
1
3
4
2
C4425
4.3UF
20%
4V
CERM
0402
1
4
2
C4451
2.2UF
20%
4V
X6S-CERM
0201
C4455
2.2UF
20%
4V
X6S-CERM
0201
1
2
1
2
C4430
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4435
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4440
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4445
4.3UF
20%
4V
CERM
0402
1
3
4
2
C4452
2.2UF
20%
4V
X6S-CERM
0201
C4456
2.2UF
20%
4V
X6S-CERM
0201
C4431
4.3UF
1
C4436
4.3UF
1
C4441
4.3UF
1
PP0V9_SLPDDR_SOC_PCIEREFBUF
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0.9V
1
2
1
2
20%
4V
CERM
0402
2
20%
4V
CERM
0402
2
20%
4V
CERM
0402
2
3
4
3
4
3
4
20%
4V
0201
20%
4V
0201
1
2
1
2
C4453
2.2UF
X6S-CERM
C4457
2.2UF
X6S-CERM
PP0V9_SLPDDR
PP0V9_SLPDDR
PP0V9_SLPDDR
C2
E1
G1
H8
J9
K8
L9
M8
N9
P1
R1
U1
C36
E37
G37
H30
J29
K30
L29
M30
N29
P37
R37
U37
AB1
AD1
AE1
AF9
AG8
AH9
AJ8
AK9
AL8
AM1
AP1
AT2
AB37
AD30
AD37
AE29
AE37
AF30
AG29
AH30
AJ29
AM37
AP37
AT36
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR0
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR1
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR2
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
VDDIO11_DDR3
R4445
2 1
1/20W
0201
OMIT_TABLE
CRITICAL
U3900
SYM 13 OF 18
330mA Max
330mA Max
330mA Max
0
5%
MF
PP0V9_SLPDDR
H9M
BGA
3 245
VDDIO11_PLL_DDR
VDDIO11_PLL_DDR
VDDIO11_PLL_DDR
VDDIO11_PLL_DDR
VDDIO11_RET_DDR
VDDIO11_RET_DDR
VDDIO11_RET_DDR
VDDIO11_RET_DDR
74B4 28B3 28A8 28A3
74B4 28B3 28A8 28A3
74B4 28B3 28A8 28A3
G9
G29
AM9
AK30
G4
G34
AM4
AM34
45mA Max
1
C4460
0.22UF
20%
6.3V
2
X6S-CERM
0201
1
C4470
2.2UF
20%
4V
2
X6S-CERM
0201
PP1V1_SLPDDR
74C4
8mA Max
1
C4461
0.22UF
20%
6.3V
2
X6S-CERM
0201
1
C4471
2.2UF
20%
4V
2
X6S-CERM
0201
74B4 28B3 28A8 28A3
BOM_COST_GROUP=SOC
1
C4462
0.22UF
20%
6.3V
2
X6S-CERM
0201
1
C4472
2.2UF
20%
4V
2
X6S-CERM
0201
PAGE TITLE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
PP1V1_SLPDDR_SOC_VDDIOPLLDDR_F
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1
C4463
0.22UF
20%
6.3V
2
X6S-CERM
0201
VOLTAGE=1.1V
PP1V1_SLPS2R
Current included in VDD2
1
C4473
2.2UF
20%
4V
2
X6S-CERM
0201
SoC Power 2
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
1
R4460
5.1
L4460
120-OHM-25%-0.48A-0.21DCR
0201
21
MF1/20W
02011%
21
74C4
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
DRAWING NUMBER
051-05198
REVISION
6.0.0
BRANCH
evt-3
PAGE
44 OF 150
SHEET
28 OF 109
D
C
B
A
SIZE
D
8
67
35 4
2
1
678
www.haojiyoubbs.com
QQ微信：181806465
Current estimates @ 105C & 2GB from Gibraltar Power Specification Rev 0.5.3
3 245
1
D
C
B
A
PP1V8_AWAKE
74B6
40mA Max
74C6
74C6
PP1V8_AWAKE
74B6
2mA Max
74C6
PP1V8_SLPS2R
1mA Max
PP1V8_SLPS2R
1mA Max
C4521
2.2UF
X6S-CERM
74B6
74B6
PP1V8_SLPS2R
74C6
134mA Max
PP1V8_SLPS2R
20mA Max
20%
4V
0201
1
2
C4522
X6S-CERM
PP1V8_AWAKE
20mA Max
PP1V8_AWAKE
1mA Max
2.2UF
20%
4V
0201
R4530
0
5%
1/20W
MF
0201
R4515
49.9
1/20W
R4519
49.9
1/20W
1
2
21
C4530
C4540
21
1%
MF
201
21
1%
MF
201
C4523
2.2UF
X6S-CERM
0201
1UF
20%
6.3V
X6S-CERM
0201
0.1UF
10%
6.3V
X6S
0201
C4500
2.2UF
X6S-CERM
C4510
2.2UF
20%
4V
X6S-CERM
0201
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP1V8_SLPS2R_SOC_LPADC_RC
PP1V8_SLPS2R_SOC_LPOSC_RC
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1
20%
4V
2
PP1V8_AWAKE_SOC_TSADC_RC
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1
2
1
2
R4545
1
20%
4V
2
0201
1
2
C4511
1
C4524
4.3UF
20%
4V
CERM
0402
1
4
2
PP1V8_AWAKE
74B6
7mA Max
49.9
1/20W
1%
MF
201
21
C4501
2.2UF
X6S-CERM
4.3UF
20%
4V
CERM
0402
3
4
2
3
C4545
1UF
20%
6.3V
X6S-CERM
0201
1
20%
4V
2
0201
C4512
4.3UF
1
C4525
4.3UF
20%
4V
CERM
0402
1
4
2
PP1V8_AWAKE_SOC_FMON_RC
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1
2
C4502
20%
4V
CERM
0402
4
2
C4519
X6S-CERM
3
C4535
X6S-CERM
2.2UF
20%
X6S-CERM
0201
3
2.2UF
20%
4V
0201
C4526
4.3UF
20%
4V
CERM
0402
1
2
2.2UF
20%
4V
0201
1
4V
2
C4513
0.1UF
1
2
3
4
1
2
C4503
X6S-CERM
10%
6.3V
X6S
0201
C4515
X6S-CERM
C4527
4.3UF
1
C4536
2.2UF
20%
4V
0201
1
2
20UF
20%
2.5V
0402
20%
4V
CERM
0402
3
4
2
0.1UF
10%
6.3V
X6S
0201
D
OMIT_TABLE
CRITICAL
U3900
H9M
A4
VDD1 VDD12_CPU_UVD
AV34
1
2
AB8
AB10
1
2
1
2
AA29
AB30
AC29
V30
W29
Y30
H17
H19
H21
AK31
AM31
AL11
AM10
AA18
P16
AD16
AF18
H28
G23
G25
G27
H22
AF12
AM30
AK12
VDD1
AV4
VDD1
B35
VDD1
W1
VDD1
W37
VDD1
Y1
VDD1
Y37
VDD1
AA9
VDDIO18_AOP1
P8
VDDIO18_AOP1
R9
VDDIO18_AOP1
T8
VDDIO18_AOP1
U9
VDDIO18_AOP1
W9
VDDIO18_AOP1
AC9
VDDIO18_AOP2
AD8
VDDIO18_AOP2
AE9
VDDIO18_AOP2
VDD18_LPADC
VDD18_LPOSC
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
P30
VDDIO18_GRP1
R29
VDDIO18_GRP1
T30
VDDIO18_GRP1
U29
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
G16
VDDIO18_GRP2
G18
VDDIO18_GRP2
G20
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP3
VDDIO18_GRP3
VDDIO18_GRP4
VDDIO18_GRP4
VDD18_TSADC
VDD18_TSADC
VDD18_TSADC
VDD18_TSADC
VDD18_TSADC
VDD18_MIPI
VDD18_MIPI
VDD18_MIPI
VDD18_USB
VDD18_FMON
VDD18_EFUSE1
VDD18_EFUSE2
SYM 14 OF 18
BGA
VDD12_PLL_CPU
VDD12_PCIE_REFBUF
VDD12_PCIE_REFBUF
VDD12_DN_PCIE
VDD12_UP_PCIE
VDD12_STG0_PCIE
VDD12_STG1_PCIE
VDD12_PLL_SOC
VDD12_PLL_SOC
VDD12_PLL_SOC
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD11_XTAL
VDD33_USB
Y18
V18
AK24
AM23
AM29
G14
AM13
AM18
AC23
AD24
AE23
AG1
AG37
AJ1
AJ37
AK1
AK37
AU3
AU34
AU35
AU4
B3
B4
C34
D34
J1
J37
K1
K37
M1
M37
W3
W35
Y3
Y35
AN23
F21
PP1V2_AWAKE
10mA Max
1
C4550
2.2UF
20%
4V
2
X6S-CERM
0201
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP1V2_AWAKE_SOC_PLLCPU_F
PP1V2_AWAKE_SOC_PCIEREFBUF_F
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP1V2_AWAKE_SOC_PCIEPLL_F
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP1V2_AWAKE_SOC_PLLSOC_F
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1
C4580
2.2UF
20%
4V
2
X6S-CERM
0201
1
C4581
2.2UF
20%
4V
2
X6S-CERM
0201
1
2
PP1V1_SLPDDR_SOC_XTAL_F
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP3V3_AWAKE
74B2
12mA Max
1
C4595
0.1UF
10%
6.3V
2
X6S
0201
74C2
C4560
0.1UF
10%
6.3V
X6S
0201
C4565
2.2UF
20%
4V
X6S-CERM
0201
C4570
0.1UF
10%
6.3V
X6S
0201
C4582
2.2UF
20%
4V
X6S-CERM
0201
C4590
C4555
0.1UF
R4560
0
5%
1
2
1
2
1
2
0.1UF
6.3V
0201
1/20W
MF
0201
C4566
2.2UF
X6S-CERM
C4571
0.1UF
PP1V1_SLPS2R
1
C4583
2.2UF
20%
4V
2
X6S-CERM
0201
FERR-240OHM-25%-350MA
1
10%
2
X6S
10%
6.3V
X6S
0201
21
20%
4V
0201
10%
6.3V
X6S
0201
R4590
L4590
1
2
1
2
1
2
1
2
5.1
0201
R4555
0
5%
1/20W
MF
0201
C4561
0.1UF
10%
6.3V
X6S
0201
C4567
2.2UF
X6S-CERM
0201
R4570
0
5%
1/20W
MF
0201
21
MF1/20W
02011%
21
PP1V2_AWAKE
21
PP1V2_AWAKE
1
2
1
20%
4V
2
21
1
2
1.74A Max
1
C4591
2.2UF
20%
4V
2
X6S-CERM
0201
C4562
2.2UF
20%
4V
X6S-CERM
0201
20%
4V
0201
1
2
C4568
2.2UF
X6S-CERM
PP1V2_AWAKE
C4572
2.2UF
20%
4V
X6S-CERM
0201
74C4
PP1V1_SLPDDR
R4565
PAGE TITLE
13mA Max
80mA Max
0
21
5%
1/20W
MF
0201
31mA Max
4mA Max
74C2
74C2 29C1
PP1V2_AWAKE
74C2
74C4
60mA Max
C
74C2 29C2
B
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
A
8
SoC Power 3
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
45 OF 150
SHEET
29 OF 109
1
SIZE
D
678
www.haojiyoubbs.com
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3 245
1
D
C
B
A1
A10
A11
A2
A22
A24
A3
A31
A34
A35
A36
A37
A5
A6
A8
AA1
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA27
AA3
AA30
AA31
AA35
AA37
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AB26
AB28
AB29
AB31
AB33
AB5
AB7
AC1
AC11
AC13
AC15
AC17
AC19
AC21
AC25
AC27
AC30
AC31
AC35
AC37
AC7
AC8
AD10
AD12
AD14
AD18
AD20
AD22
AD26
AD29
AD3
AD31
AD34
AD7
AE11
AE13
AE15
AE17
AE19
AE21
AE25
AE27
AE30
AE31
AE33
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U3900
H9M
BGA
SYM 15 OF 18
OMIT_TABLE
CRITICAL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE4
AE5
AE7
AE8
AF1
AF10
AF14
AF16
AF20
AF22
AF24
AF26
AF28
AF29
AF3
AF31
AF35
AF37
AF5
AF7
AF8
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG30
AG31
AG5
AG7
AG9
AH1
AH10
AH12
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH29
AH31
AH33
AH37
AH5
AH7
AH8
AJ11
AJ13
AJ17
AJ19
AJ23
AJ25
AJ3
AJ30
AJ31
AJ35
AJ7
AJ9
AK10
AK14
AK16
AK18
AK20
AK22
AK26
AK28
AK5
AK7
AK8
AL1
AL10
AL13
AL15
AL19
AL2
AL21
AL23
AL25
AL27
AL29
AL31
AL32
AL33
AL36
AL37
AL5
AL7
AL9
AM11
AM12
AM17
AM2
AM22
AM24
AM28
AM32
AM36
AM5
AM6
AM7
AM8
AN1
AN10
AN12
AN14
AN15
AN17
AN19
AN20
AN21
AN24
AN26
AN27
AN29
AN31
AN32
AN37
AN6
AN7
AN8
AN9
AP10
AP15
AP20
AP23
AP24
AP27
AP3
AP32
AP33
AP35
AP5
AP6
AP8
AP9
AR1
AR10
AR11
AR13
AR15
AR16
AR18
AR20
AR22
AR23
AR24
AR25
AR27
AR28
AR30
AR32
AR37
AR6
AR8
AT1
AT10
AT12
AT14
AT15
AT17
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U3900
H9M
BGA
SYM 16 OF 18
OMIT_TABLE
CRITICAL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AT19
AT20
AT21
AT23
AT24
AT26
AT27
AT29
AT3
AT31
AT32
AT34
AT35
AT37
AT4
AU1
AU10
AU15
AU2
AU20
AU23
AU24
AU27
AU32
AU33
AU36
AU37
AU6
AU8
AV1
AV10
AV11
AV13
AV15
AV16
AV18
AV2
AV20
AV22
AV25
AV27
AV28
AV3
AV30
AV32
AV33
AV35
AV36
AV37
AV6
B1
B11
B13
B16
B19
B2
B22
B24
B31
B34
B36
B37
B5
B6
C1
C11
C22
C23
C24
C25
C26
C27
C28
C29
C3
C30
C31
C32
C33
C35
C37
C4
C5
C6
C7
C9
D1
D10
D11
D12
D13
D14
D16
D17
D19
D20
D22
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D35
D36
D37
D5
D6
D8
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E24
E25
E26
E27
E28
E29
E3
E30
E31
E32
E33
E34
E35
E36
E5
E6
F1
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F24
F25
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F5
F6
F7
F9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U3900
H9M
BGA
SYM 17 OF 18
OMIT_TABLE
CRITICAL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G10
G15
G17
G19
G2
G21
G24
G26
G28
G30
G31
G32
G33
G36
G6
G7
G8
H1
H10
H12
H14
H16
H18
H2
H20
H24
H26
H29
H31
H33
H36
H37
H5
H7
H9
J17
J19
J21
J23
J25
J27
J30
J31
J7
J8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K28
K29
K3
K31
K33
K35
K5
K7
K9
L1
L11
L13
L15
L17
L19
L21
L23
L25
L27
L30
L31
L37
L7
L8
M10
M12
M14
M16
M18
M20
M22
M24
M26
M28
M29
M31
M7
M9
N1
N11
N13
N15
N19
N21
N23
N25
N27
N3
N30
N31
N33
N35
N37
N5
N7
N8
P10
P12
P14
P18
P20
P22
P24
P26
P28
P29
P31
P5
P7
R11
R13
R15
R17
R19
R21
R23
R25
R27
R30
R31
R7
R8
T1
T10
T12
T14
T16
T18
T20
T22
T24
T26
T28
T29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U3900
H9M
BGA
SYM 18 OF 18
OMIT_TABLE
CRITICAL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T3
T31
T33
T35
T37
T5
T7
U11
U13
U15
U17
U19
U21
U23
U25
U27
U30
U31
U7
U8
V1
V10
V12
V14
V16
V20
V22
V24
V26
V28
V29
V3
V31
V35
V37
W11
W13
W15
W17
W19
W2
W21
W23
W25
W27
W30
W31
W33
W36
W5
Y10
Y12
Y14
Y16
Y2
Y20
Y22
Y24
Y26
Y28
Y29
Y31
Y36
D
C
B
A
8
SYNC_DATE=03/01/2019SYNC_MASTER=myEE
PAGE TITLE
A
SoC Ground
DRAWING NUMBER
051-05198
Apple Inc.
REVISION
6.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BOM_COST_GROUP=SOC
67
35 4
IV ALL RIGHTS RESERVED
2
BRANCH
evt-3
PAGE
46 OF 150
SHEET
30 OF 109
1
SIZE
D
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