Apple iPhone XS Schematic

VIETMOBILE.VN

IPHONE XS MAX SCHEMATIC

VIETMOBILE.VN

VIETMOBILE.VN

VIETMOBILE.VN

VIETMOBILE.VN

8

VIETMOBILE.VN

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6543

D32/D33 Top MLB: EVT (D32 Build)

LAST_MODIFICATION=Wed Jan 31 16:37:18 2018

2 1

ECNREV DESCRIPTION OF REVISION

CK
APPD

DATE

2018-02-0500111753087 ENGINEERING RELEASED

D

1
2
3
4
5
6
7
8

10
11
12

1
2
3
4
5
6
10
11
129
13
14
15

TABLE OF CONTENTS
SYSTEM:BOM Tables
SYSTEM:BOM Tables FF Specific
SYSTEM: Mechanical Components
SYSTEM: Testpoints (Top)
BOOTSTRAPPING
SOC: JTAG,USB,XTAL
SOC: PCIE
SOC: MIPI
SOC: LPDP
SOC: SERIAL
SOC: GPIO & UART

test_mlb

test_mlb
test_mlb
test_mlb

test_mlb
test_mlb
test_mlb

10/13/2016
08/09/2017

10/13/2016
10/13/2016
10/17/2016
04/07/2017

10/13/2016
04/05/2017
04/05/2017

46
47
48
49
50
51
52
53
54
55
56
57

60
61
62
63
64
65
66
67
68
70
71
81

I/O: LDCM
I/O: Gecko
I/O: USB PD
I/O: Hydra
I/O: B2B Dock
B2B: Interposer Bot
SYSTEM: AP I2C
SYSTEM: ISP I2C
SYSTEM: AOP/SMC I2C
SYSTEM: SOC/PMU GPIOs
SYSTEM: AOP GPIOs
Interposer: Pins 1-144

test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

D

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

06/06/2017
10/17/2016
10/13/2016
10/13/2016
10/13/2016
08/30/2017

05/09/2017
05/09/2017
08/29/2017

C

13
14
15
16
17
18
19
20
21
22
23
24
25
26

16
17
18
19

21
26
27

29
30
31
32
33 SYSTEM POWER: Charger

SOC: AOP
SOC: POWER (1/3)
SOC: POWER (2/3)
SOC: POWER (3/3)
SOC: DEV BOARD ALIASES20
SOC: LPDP ALIASES
NAND
SYSTEM POWER: PMU Bucks (1/4)
SYSTEM POWER: PMU Bucks (2/4)28
SYSTEM POWER: PMU LDOs (3/4)
SYSTEM POWER: PMU (4/4)
SYSTEM POWER: Boost
SYSTEM POWER: B2B Battery

test_mlb

test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

10/17/2016
04/17/2017
08/17/2017
03/22/2017
03/10/2017
06/01/2017
03/10/2017
03/10/2017
10/13/2016
10/13/2016
10/13/2016

58
59
60

82
83
85

Interposer: Pins 145-285
Interposer: Top Aliases
Interposer: Pins 286-359

08/30/2017
08/17/2017
08/30/2017

C

B

27 35
28
29
30
31
32
33 41
34
35
36
37
38
39
40

36
37
38
39 10/13/2016
40

42
43
44

46
47
48 AUDIO: CODEC (2/2)

SYSTEM POWER: B2B Cyclone + Button
SENSORS
CAMERA: PMU (1/2)
CAMERA: PMU (2/2)
CAMERA: B2B Wide (TX)
CAMERA: B2B Tele [MT]
CAMERA: Strobe Drivers
CAMERA: B2B Fcam
CAMERA: B2B Strobe + Hold Button
PEARL: Power
PEARL: B2B Romeo + Juliet

AUDIO: CODEC (1/2)

test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

test_mlb45
test_mlb
test_mlb
test_mlb

10/13/2016
10/13/2016
10/13/2016
03/22/2017

10/13/2016
03/22/2017
10/13/2016

B

03/22/2017

10/13/2016
10/13/2016PEARL: B2B Rosaline + Sensor
10/13/2016
10/13/2016

A

41
42
43
44
45

49
50
51
57
59

AUDIO: SOUTH SPKAMP
AUDIO: NORTH SPKAMP
ARC: AMP
CG: B2B Display
I/O: Overvoltage Cut-Off Circuit

BOM:639-03991 (Ultimate)
BOM:639-03992 (Extreme)
BOM:639-03990 (Max)
MCO:056-05750

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

051-02545 SCHSCH,MLB_TOP,D32 CRITICAL ?1

PCBPCB,MLB_TOP,D32 ?CRITICAL820-00997 1

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

test_mlb

04/05/2017
04/05/2017
04/05/2017
10/13/2016

TABLE OF CONTENTS

DRAWING TITLE

SCH,MLB,TOP,D32

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-02545

REVISION

7.0.0

BRANCH

PAGE

1 OF 85

SHEET

1 OF 60

A

SIZEDRAWING NUMBER

D

8

3

124567

Display CMC's

VIETMOBILE.VN

PART NUMBER

155S00391155S00415 ALT_PARTS ALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CMC,35OSM,7HGz,MUR

TABLE_ALT_HEAD

TABLE_ALT_ITEM

678

3 245

1

D

NAND

Ultimate

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

HYNIX, 3DV4. ULTIMATE CRITICAL ULTIMATEU26001335S00340

PART NUMBER

335S00359 335S00340 U2600ALT_PARTS TOSHIBA, BICS3, ULT

335S00286 U2600335S00340 ALT_PARTS SANDISK, BICS3, ULT

335S00340335S00288 SAMSUNG, 3DV4, ULTALT_PARTS U2600

Extreme

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

D

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

Global R/C Alternates

TABLE_ALT_HEAD

PART NUMBER

138S0648 ALT_PARTS

138S0652 ALL

138S0706138S0739

ALT_PARTS

ALT_PARTS

ALL

ALL138S00049 138S0831

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO

CAP,CER,X5R,0.22UF,20%,6.3V,20%

CAP,CER,X5R,2.2UF,20%,6.3V,0201

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Yangtze Inductors

TABLE_ALT_HEAD

PART NUMBER

152S00918

152S00918

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

ALL152S00872 ALT_PARTS

ALT_PARTS ALL152S00847

IND,MLD,0.47UH,TDK

TABLE_ALT_ITEM

IND,MLD,0.47UH,CYN

CRITICAL PART# COMMENT

152S00918

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

IND,MLD,0.22UH,20%,5.8A,40MOHM,H=.65,1608

C

335S00342 EXTREMECRITICAL1 U2600HYNIX, 3DV4, Extreme

PART NUMBER

335S00276 ALT_PARTS335S00342

335S00358 U2600ALT_PARTS335S00342

Max

1 HYNIX, 3DV4, MAX CRITICAL MAX335S00343 U2600

PART NUMBER

335S00343

U2600335S00247 ALT_PARTS335S00342

U2600

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

U2600ALT_PARTS335S00339

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SANDISK, BISC3, SUPREME

TABLE_ALT_ITEM

SAMSUNG, 3DV4, SUPREME

TABLE_ALT_ITEM

TOSHIBA, 3DV4, SUPREME

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SAMSUNG, 3DV4, MAX

BOM OPTIONCRITICAL

TABLE_5_ITEM

Denali Inductors

TABLE_ALT_HEAD

PART NUMBER

ALT_PARTS152S00831 ALL152S00878

ALT_PARTS152S00818

152S00822152S00835

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

ALT_PARTS ALL

ALT_PARTS152S00822

ALT_PARTS152S00877 152S00817 ALL

ALL152S00831

ALL152S00827

ALT_PARTS152S00829 152S00817 ALL

ALT_PARTS ALL152S00825 152S00823

ALT_PARTS152S00819 ALL152S00833

ALT_PARTS152S00819 ALL152S00824

152S00834

ALT_PARTS152S00820 ALL

ALT_PARTS152S00828 152S00820 ALL

ALT_PARTS152S00821 ALL152S00826

ALT_PARTS ALL152S00866 152S00821

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

IND,MLD,0.22UH,20%,5.9A,36MOHM,H=.65,1608

TABLE_ALT_ITEM

IND,MLD,0.22UH,20%,5.9A,36MOHM,H=.65,1608,CYN

TABLE_ALT_ITEM

IND,MLD,0.47UH,20%,4.5A,40MOHM,H=.80,2012

TABLE_ALT_ITEM

IND,MLD,0.47UH,20%,4.5A,50MOHM,H=.80,2012

TABLE_ALT_ITEM

IND,MLD,0.1UH,20%,9A,20MOHM,H=0.8,2012

TABLE_ALT_ITEM

IND,MLD,0.1UH,20%,9.0A,22MOHM,H=0.8,2012

TABLE_ALT_ITEM

IND,MLD,1UH,20%,3A,60MO,H=.65,2016

TABLE_ALT_ITEM

IND,MLD,1UH,20%,2.1A,62MO,H=.65,2012

TABLE_ALT_ITEM

IND,MLD,1UH,20%,2A,69MO,H=.65,2012

TABLE_ALT_ITEM

IND,MLD,0.47UH,20%,3.8A,270MO,H=.80,2012

TABLE_ALT_ITEM

IND,MLD,0.47UH,20%,3.2A,400MO,H=.80,2012

TABLE_ALT_ITEM

IND,MLD,1UH,20%,2.1A,52MO,H=.80,2012

TABLE_ALT_ITEM

IND,MLD,1UH,20%,2.1A,52MO,H=.80,2012

CRITICAL PART# COMMENT

152S00831

152S00822

152S00817

152S00823

152S00819

152S00820

152S00821

IND,MLD,0.22UH,20%,5.8A,40MOHM,H=.65,1608

IND,MLD,0.47UH,20%,4.5A,47MOHM,H=.8,2012

IND,MLD,0.1UH,20%,9.4A,22MOHM,H=0.65,1608

IND,MLD,1UH,20%,3.0A,60MO,H=.65,2016

IND,MLD,1UH,20%,1.7A,69MO,H=.65,2012

IND,MLD,0.47UH,20%,3.2A,42MO,H=.80,2012

IND,MLD,1UH,20%,2.2A,60MO,H=.80,2012

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

C

B

A

PART NUMBER

ALT_PARTS

ALT_PARTS

ALL138S00148 138S00149

ALL138S00150 138S00149

ALT_PARTS138S00151 ALL138S00149

PART NUMBER

138S00143 138S00144 ALT_PARTS

138S00163 ALT_PARTS138S00144

PART NUMBER

ALL

ALL

138S00139 ALL138S00138 ALT_PARTS

138S00139138S00164 ALLALT_PARTS

PART NUMBER

138S00221 ALT_PARTS138S00146 ALL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

0402-3T,10.5uF@1V, Kyocera

0402-3T,10.5uF@1V, SEMCO

0402-3T,10.5uF@1V, TY

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

0402,16uF@1V, Kyocera

0402,16uF@1V, TY

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

0201,3uF@1V, Kyocera

0201,3uF@1V, TY

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

0402,5.1uF@3V, Kyocera

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL PART# COMMENT

138S00149

CRITICAL PART# COMMENT

138S00144

CRITICAL PART# COMMENT

138S00139

CRITICAL PART# COMMENT

138S00146

0402-3T,10.5uF@1V

0402,16uF@1V

0201,3uF@1V

0402,5.1uF@3V

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

XTAL Alternate

PART NUMBER

197S00118 ALT_PARTS197S0612 Y1000

197S00120 ALT_PARTS Y1000

197S00118

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

XTAL, 24M, 1612

XTAL, 24M, 1612

NEON Alternate

PART NUMBER

152S00721 ALT_PARTS

152S00876

L4100, L4120 TY, IND

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

B

A

TABLE_ALT_HEAD

PART NUMBER

138S00141 ALT_PARTS ALL138S00140

138S00142

138S00166 ALT_PARTS

138S00141 ALLALT_PARTS

138S00141 ALL

8

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0201,1.1uF@3V, Kyocera

TABLE_ALT_ITEM

0201,1.1uF@3V, SEMCO

TABLE_ALT_ITEM TABLE_ALT_ITEM

0201,1.1uF@3V, Taiyo

CRITICAL PART# COMMENT

138S00141

0201,1.1uF@3V

67

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

ANSEL Alternate

PART NUMBER

152S00875152S00716

ALT_PARTS

L3700

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TY, IND

TABLE_ALT_HEAD

SYSTEM:BOM Tables

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

2 OF 85

SHEET

2 OF 60

1

SIZE

D

D

VIETMOBILE.VN

EEEE Codes

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

EEEE FOR (MLB_TOP,639-03991,ULTIMATE)

EEEE FOR (MLB_TOP,639-03992,EXTREME)

EEEE FOR (MLB_TOP,639-03990,MAX)

678

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

CRITICAL

EEEE_HWV01825-7691

ULTIMATEEEEE_HWV1825-7691 1

TABLE_5_ITEM

EXTREMEEEEE_HWV21825-7691 CRITICAL

TABLE_5_ITEM

MAXCRITICAL

3 245

1

D

C

Cyprus OMIT

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

339S00510 1 SOCU1000 CRITICALCYPRUS 4GB Micron

Cyprus ALTs

PART NUMBER

ALT_PARTS

ALT_PARTS U1000339S00510339S00512

U1000339S00510339S00511

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

CYPRUS 4GB Hynix

CYPRUS 4GB Samsung

Combo Stiffener

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

C

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

ST04011604-19651 Combo Stiffener CRITICAL ALL

BOM OPTIONCRITICAL

TABLE_5_ITEM

B

B

A

8

67

SYNC_MASTER=

PAGE TITLE

SYNC_DATE=08/09/2017

A

SYSTEM:BOM Tables FF Specific

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02545

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

3 OF 85

SHEET

3 OF 60

1

678

VIETMOBILE.VN

3 245

1

FIDUCIALS

FD0401

0P5SQ-CROSS-NSP

FID

1

ROOM=ASSEMBLY

D

CL0400

2.10R1.60-NSP

1

Crosses

FD0402

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0403

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0404

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0407

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0406

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

D

C

1

SH0403

SM

SHIELD-N-MLB-D32

CL0401

2.10R1.60-NSP

1

R0402

0.00

1/32W
01005

21

0%
MF

R0401

0.00

1/32W
01005

21

0%
MF

CKPLUS_WAIVE=TERMSHORTED

CKPLUS_WAIVE=TERMSHORTED

Squares

FD0405

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0408

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0410

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0411

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0412

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

C

B

CL0402

STDOFF-3.0OD1.6ID-H0.62-TH-D32

1
2

CKPLUS_WAIVE=TERMSHORTED

ST0401

WELD-AP-D3X

SM

1

OMIT_TABLE

1

SH0401

SM

SHIELD-W-MLB-D32

R0403

0.00

1/32W
01005

21

0%
MF

CKPLUS_WAIVE=TERMSHORTED

B

A

SB0401

STDOFF-2.9OD1.4ID-0.77H-SM1

1

1

SH0402

SM

SHIELD-S-MLB-D32

CL0403

2.10R1.60-NSP

1

PAGE TITLE

SYSTEM: Mechanical Components

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

4 OF 85

SHEET

4 OF 60

A

SIZE

D

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

D

C

37 36

37 36

15

23 15

15

23 15

15

15

15

15

15

PEARL

PP_ROMEO_DENSE_ANODE

PP_ROMEO_CATHODE

BUMP SENSE

GPU_SENSE_NEG

IN

GPU_SENSE_POS

IN

CPU_PCORE_SENSE_NEG

IN

CPU_PCORE_SENSE_POS

IN

SOC_SENSE_NEG

IN

SOC_SENSE_POS

IN

DCS_SENSE_POS

IN

VDDQL_DCS_SENSE_NEG

IN

VDDQL_SENSE_POS

IN

PP0510

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0511

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0553

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0513

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0551

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0512

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0516

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0514

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0517

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0552

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0518

P2MM-NSM

SM

1

PP

ROOM=TEST

20 17

20 17

PP_GPU

PP_CPU_PCORE

LVCC

XW0510

SHORT-10L-0.05MM-SM

XW0511

SHORT-10L-0.05MM-SM

12

IN

12

IN

13

IN

23 13

IN

49 23 7

58 19 13

19 11 6

19 13

IN

IN

IN

IN

58

21

58

21

PAD_MTR_ANALOG_TEST_P

PAD_MTR_ANALOG_TEST_N

AOP_TO_DDR_SLEEP1_READY_PROBE

SPMI_PMU_BI_PMGR_SDATA

PMU_TO_AP_HYDRA_ACTIVE_READY

SWD_AP_BI_NAND_SWDIO

SWD_AOP_TO_MANY_SWCLK

SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

PP_GPU_LVCC

PP_CPU_PCORE_LVCC

METROLOGY

PMU

NAND

PP0506

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0507

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0592

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0593

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0520

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0521

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0522

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0560

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0561

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0562

P2MM-NSM

SM

1

PP

ROOM=TEST

28 13

28 13

28 13

56 28

56 27

56 28

49 26

36 30

36 23 9

48 11

48 11

Sensors

SPI_AOP_TO_IMU_SCLK

IN

SPI_AOP_TO_IMU_MOSI

IN

SPI_IMU_TO_AOP_MISO

IN

IMU_TO_AOP_DATARDY

IN

COMPASS_TO_AOP_INT

IN

PHOSPHORUS_TO_AOP_INT

IN

Hydra VBUS

HYDRA_TO_YANGTZE_VBUS1_VALID_L

IN

Rigel

CAMPMU_TO_RIGEL_ENABLE

IN

RIGEL_TO_ISP_INT

IN

CCG SWD

AP_BI_CCG2_SWDIO

IN

AP_TO_CCG2_SWCLK

IN

PP0540

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0541

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0542

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0544

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0546

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0547

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0550

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0570

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0571

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0586

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0587

P2MM-NSM

SM

1

PP

ROOM=TEST

56 47

56 43 41

43 42 41

48 11

23 13

30 17

49 12

40 11

40 11

VALIDATION PP's

IN

IN

IN

IN

IN

IN

IN

IN

IN

GECKO_TO_AOP_IRQ_L

SPKAMP_BOT_ARC_TO_AOP_INT_L

SPKAMP_TO_OTHERS_SYNC

CCG2_TO_SMC_INT_L

PMU_TO_AOP_CLK32K

CAMPMU_TO_JULIET_DVDD_LDO_EN

UART_AP_DEBUG_RXD

SPI_CODEC_TO_AP_MISO

SPI_AP_TO_CODEC_MOSI

PP0590

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0591

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0566

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0567

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0594

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0595

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0596

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0597

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0598

P2MM-NSM

SM

1

PP

ROOM=TEST

D

C

B

A

23 7

12 6

23 12 7

9

9

12

SOC Debug

AP_TO_PMU_TEST_CLKOUT

IN

BOARD_ID0

IN

SOC_DEBUG2

IN

SOC_DEBUG3

IN

DFU_STATUS

IN

PMU_TO_AP_PRE_UVLO_L

IN

PP0500

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0501

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0502

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0503

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0504

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0505

P2MM-NSM

SM

1

PP

ROOM=TEST

19 7

19 8

19 8

17 8

17 8

19

19

NAND_ANI1_VREF

IN

NAND_ANI0_VREF

IN

AP_TO_NAND_RESET_L

IN

PCIE Refclk

90_PCIE_AP_TO_NAND_REFCLK_P

IN

90_PCIE_AP_TO_NAND_REFCLK_N

IN

90_PCIE_BB_TO_AP_RXD_C_P

IN

90_PCIE_BB_TO_AP_RXD_C_N

IN

PP0563

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0564

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0565

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0530

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0531

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0532

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0533

P2MM-NSM

SM

1

PP

ROOM=TEST

23

PP0599

PMU XTAL

42 41 40 13

50 43

PP0588

P2MM-NSM

SM

IN

XTAL_TO_PMU_CLK32K_2

1

PP

ROOM=TEST

57 43

57 43

IN

IN

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK

WALLET MODE

NFC_TO_ARC_RESET_L

NFC_TO_ARC_TRIG

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0524

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0525

P2MM-NSM

SM

1

PP

ROOM=TEST

B

A

SYSTEM: Testpoints (Top)

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

5 OF 85

SHEET

5 OF 60

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

TOP BOARD ONLY CONFIGURATION IS D33 MLB MAV

BOTTOM BOARD SELECTS ICE/MAV and D32/D33

1

D

55

55

BOARD_REV3

OUT

BOARD_REV2

OUT

BOOTSTRAPPING:BOARD REV

BOARD ID
BOOT CONFIG

R0623

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

R0622

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

NOSTUFF

PP1V8_IO

53 52 44

D

37 36 34 32 31 30 29 20 19 17

SELECTED -->

C

55

55

12

BOARD_REV1

OUT

BOARD_REV0

OUT

BOARD_ID4

OUT

CKPLUS_WAIVE=SINGLE_NODENET

R0621

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

R0620

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

C

B

11

57 12

12

12 5

PP1V8_IO

OUT

BOARD_ID2

OUT

PP1V8_IO

OUT

BOARD_ID0

OUT

CKPLUS_WAIVE=SINGLE_NODENET

MAKE_BASE=TRUE

On mlb_bot

MAKE_BASE=TRUE

No connect

B

DEFAULT -->

No connect

R0601

4.7K

1/32W
01005

ROOM=SOC

21

1%
MF

A

19 11 5

19 11

SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

OUT

SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1

OUT

R0602

19 11

8

SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0

OUT

4.7K

1%

1/32W

MF

01005

ROOM=SOC

NOSTUFF

21

<-------Removed at EVT

67

POR -->

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

BOOTSTRAPPING

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

6 OF 85

SHEET

6 OF 60

1

SIZE

D

SOC - USB, JTAG, XTAL

VIETMOBILE.VN

678

3 245

1

D

C

VDD18_XTAL:1.06-1.17V @ 2mA MAX
VDD18_USB: 1.62V - 1.98V @ 20mA MAX

PP1V8_IO

15 17

1

C1097

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

FL1092

240OHM-25%-0.2A-0.9OHM

21

01005

1

C1093

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

R1093

0.00

1/32W
01005

ROOM=SOC

0%
MF

21

1

C1090

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

PP1V8_USB_DEBUG

PP1V8_XTAL

1

C1092

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

AP27

AP13

AP15

VDD18_USB

VDD18_XTAL

7

PP3V3_USB_DEBUG

C1096

0.1UF

20%

6.3V

X5R-CERM

01005

ROOM=SOC

1

C1095

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

AP14

AR14

VDD33_USB

R1090

1

2

AM14

0.00

0%

1/32W

MF

01005

ROOM=SOC

AM15

D

VDD33_USB*: 3.14-3.46V @ 12mA MAX

21

R1091

PP0V8_USB_DEBUG

C1098

0.1UF

20%

6.3V

X5R-CERM

01005

ROOM=SOC

0.00

1

2

1/32W
01005

ROOM=SOC

21

0%
MF

PP3V3_USB

17

(Analog)

VDD_FIXED_USB*: 0.765V - 0.84V @ 5mA MAX

PP0V8_SOC_FIXED_S1

8 9 10 14 17

C

USB Reference

B

CONNECTED TO GND OFFPAGE ON MLB

CONNECTED TO GND OFFPAGE ON MLB

CONNECTED TO GND OFFPAGE ON MLB

49

49

49

49

57 23 15 7

49 23 5

57 23 15 7

23 5

19 5

19

BI
BI

90_USB_DBG_DATA_P
90_USB_DBG_DATA_N

PP3V3_USB_DEBUG

7

NC_DBG_USB_ID

DBG_USB_VBUS_REXT

7

GND

17

NC_JTAG_TRST_L
NC_JTAG_TDO
NC_JTAG_TDI

SWD_DOCK_BI_AP_SWDIO

BI

SWD_DOCK_TO_AP_SWCLK

IN

PMU_TO_SYSTEM_COLD_RESET_L

IN

PMU_TO_AP_HYDRA_ACTIVE_READY

IN

PMU_TO_SYSTEM_COLD_RESET_L

IN

AP_TO_PMU_TEST_CLKOUT

OUT

AP_TO_NAND_RESET_L

OUT

AP_TO_NAND_FW_STRAP

OUT

GND

17

GND

17

AY16

AW16

AU13

AT13

AT14

AP33

AP32
AR34
AP30
AP29
AR35

AP28

H2

AR33

G37

J4

J5
AE2
AE3

VDD18_USB_DEBUG

DBG_USB_DP
DBG_USB_DM

DBG_USB_VBUS

DBG_USB_ID

DBG_USB_REXT

JTAG_SEL

JTAG_TRST*
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK

COLD_RESET*
CFSB

CFSB_AON
TST_CLKOUT
SSD_RESET*
SSD_BFH
HOLD_RESET
TESTMODE

ALT_FUNC
CTM_TRIGGER

VDD33_USB_DEBUG

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 1 OF 16

ROOM=SOC

CRITICAL

OMIT_TABLE

VDD_FIXED_USB

VDD_FIXED_USB_DEBUG

XI0

AJ35

AW17
AY17

AT15

AU15

AU14

N3
N2

N5
N4

P4
P2
AP23
AY25

AW25

ANALOGMUX_OUT

USB_DP

USB_DM

USB_VBUS

USB_ID

USB_REXT

CPU_TRIGGER0
CPU_TRIGGER1

GPU_TRIGGER0
GPU_TRIGGER1

SOCHOT1

DROOP

WDOG

XO0

AP_TO_PMU_AMUX_OUT

90_USB_AP_DATA_P
90_USB_AP_DATA_N

USB_VBUS_DETECT

NC_AP_USB_ID

AP_USB_REXT

PMU_TO_AP_THROTTLE_PCORE_L
PMU_TO_AP_THROTTLE_ECORE_L

PMU_TO_AP_THROTTLE_GPU0_L
PMU_TO_AP_THROTTLE_GPU1_L

AP_TO_PMU_SOCHOT_L
PMU_TO_AP_PRE_UVLO_L
AP_TO_PMU_WDOG_RESET

XTAL_AP_24M_IN

XTAL_AP_24M_OUT

7

OUT

BI
BI

IN

IN
IN

IN

OUT

IN

OUT

AP_USB_REXT

7

1

R1000

200

1%
1/32W
MF
01005

2

23

26

49

49

DBG_USB_VBUS_REXT

7

ROOM=SOC

1

R1001

200

1%
1/32W
MF
01005

2

ROOM=SOC

B

23

23

23

IN

55

23

23 12 5

23

NOSTUFF

1

R1010

511K

1%
1/32W
MF
01005

2

ROOM=SOC

R1011

1.00K

5%

1/32W

MF

01005

ROOM=SOC

24MHZ-30PPM-9.5PF-60OHM

21

SOC_24M_O

1

C1010

12PF

5%
16V

2

CERM
01005

ROOM=SOC

CRITICAL

ROOM=SOC

Y1000

1.60X1.20MM-SM

NC GND

4312

XTAL_GND

1

C1011

12PF

5%
16V

2

CERM
01005

ROOM=SOC

A

8

67

OMIT

SHORT-20L-0.05MM-SM

XW1001

ROOM=SOC

2

SYNC_MASTER=test_mlb

PAGE TITLE

1

SOC: JTAG,USB,XTAL

DRAWING NUMBER

SYNC_DATE=10/17/2016

SIZE

051-02545

Apple Inc.

REVISION

A

D

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

10 OF 85

SHEET

7 OF 60

1

D

VIETMOBILE.VN

SOC - PCIE

PP1V2_SOC

10 17

C1199

2.2UF

20%

6.3V

X5R-CERM

0201

ROOM=SOC

678

VDD12_PCIE:1.14V - 1.26V @ 130mA MAX

VDD12_PCIE_REFBUF:1.14V - 1.26V @ 30mA MAX

OMIT

XW1101

SHORT-20L-0.05MM-SM

2 1

1

2

ROOM=SOC

PP1V2_SOC_PCIE_REFBUF_XW

R1195

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

PP1V2_SOC_PCIE_REFBUF

1

C1198

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

AM31

AM29

AK27

AL26

AL30

AL28

PP0V8_SOC_FIXED_PCIE_REFBUF

AL27

1

C1194

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

VDD_FIXED_PCIE_REFBUF:0.769V - 0.85V @ 65mA MAX

R1194

0.00

1/32W
01005

21

0%
MF

ROOM=SOC

VDD_FIXED_PCIE:0.769V - 0.85V @ 105mA MAX

PP0V8_SOC_FIXED_PCIE_REFBUF_XW

3 245

OMIT

XW1100

SHORT-20L-0.05MM-SM

2 1

ROOM=SOC

1

C1193

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

PP0V8_SOC_FIXED_S1

1

C1191

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

7 9 10 14 17

D

VDD12_PCIE

VDD_FIXED_PCIE0

VDD_FIXED_PCIE1

VDD12_PCIE_REFBUF

VDD12_PCIE_REFBUF

VDD_FIXED_PCIE_REFBUF

U1000

19 8

19 5

19 5

17 17

17

PCIE_NAND_BI_AP_CLKREQ_L

BI

90_PCIE_AP_TO_NAND_REFCLK_P

OUT

90_PCIE_AP_TO_NAND_REFCLK_N

OUT

90_PCIE_NAND_TO_AP_RXD_C_P

IN IN

90_PCIE_NAND_TO_AP_RXD_C_N

IN

U37

AW19

AY19

AY27

AW27

PCIE_CLKREQ0*
PCIE_REF_CLK0_P

PCIE_REF_CLK0_N

PCIE_RX0_P
PCIE_RX0_N

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 2 OF 16

PCIE_CLKREQ3*

PCIE_REF_CLK3_P
PCIE_REF_CLK3_N

PCIE_RX3_P
PCIE_RX3_N

U34
AY22

AW22

AY33
AW33

PCIE_WLAN_BI_AP_CLKREQ_L

90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_REFCLK_N

90_PCIE_WLAN_TO_AP_RXD_C_P
90_PCIE_WLAN_TO_AP_RXD_C_N

BI

OUT
OUT

58 8

58

58

17

IN

PCIE LINK 3

C

B

PCIE LINK 0

PCIe BB CLKREQ PU on BB domain

PCIe Clock Request Pull-Ups

PP1V8_IO

17

1

2

R1130

100K

1/32W
01005

ROOM=SOC

PCIE_NAND_BI_AP_CLKREQ_L

19 8

PCIE_WLAN_BI_AP_CLKREQ_L

58 8

R1100

100K

5%

1/32W

MF

01005

ROOM=SOC

PCIe Reset Pull-Downs

5%
MF

17

17

19 8

1

2

90_PCIE_AP_TO_NAND_TXD_C_P

OUT

90_PCIE_AP_TO_NAND_TXD_C_N

OUT

PCIE_AP_TO_NAND_PERST_L

OUT

NC_PCIE1_CLKREQ1_L

NC_PCIE1_REF_CLK_P
NC_PCIE1_REF_CLK_N

NC_PCIE1_RX1_P
NC_PCIE1_RX1_N

NC_PCIE1_TX1_P
NC_PCIE1_TX1_N

NC_PCIE1_PERST_L

AU26
AV26

T36

AW20

AY20

AY29

AW29

AU28
AV28

PCIE_TX0_P
PCIE_TX0_N

PCIE_CLKREQ1*
PCIE_REF_CLK1_P

PCIE_REF_CLK1_N

PCIE_RX1_P
PCIE_RX1_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_PERST1*

Hardwired as Input

NAND LINK

PCIE_TX3_P
PCIE_TX3_N

PCIE_PERST3*PCIE_PERST0*

LINK3

PCIE_CLKREQ2*

PCIE_REF_CLK2_P
PCIE_REF_CLK2_N

PCIE_RX2_P
PCIE_RX2_N

PCIE_TX2_P
PCIE_TX2_N

PCIE_PERST2*

LINK1 LINK2

AU32
AV32

R37

U35U36
AW21

AY21

AY31
AW31

AU30
AV30

T34T35

90_PCIE_AP_TO_WLAN_TXD_C_P
90_PCIE_AP_TO_WLAN_TXD_C_N

PCIE_AP_TO_WLAN_PERST_L

NC_PCIE2_CLKREQ1_L

NC_PCIE2_REF_CLK_P
NC_PCIE2_REF_CLK_N

NC_PCIE2_RX1_P
NC_PCIE2_RX1_N

NC_PCIE2_TX1_P
NC_PCIE2_TX1_N

NC_PCIE2_PERST_L

OUT
OUT

OUT

17

17

57 8

C

B

PCIE_AP_TO_WLAN_PERST_L

57 8

PCIE_AP_TO_BB_PERST_L

57 8

PCIE_AP_TO_NAND_PERST_L

19 8

R1101

100K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1121

100K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1131

100K

5%

1/32W

MF

01005

ROOM=SOC

PCIE_RCAL_POS

1

R1140

1

2

200

1%
1/32W
MF
01005

2

ROOM=SOC

1

C1140

10PF

5%
16V

2

CERM
01005

ROOM=SOC

PCIE_RCAL_NEG

AT31

AR31

PCIE_RCAL_P
PCIE_RCAL_N

PCIE_CLKREQ4*

PCIE_REF_CLK4_P
PCIE_REF_CLK4_N

PCIE_RX4_P
PCIE_RX4_N

T37
AY23

AW23

AY35
AW35

PCIE_BB_BI_AP_CLKREQ_L

90_PCIE_AP_TO_BB_REFCLK_P
90_PCIE_AP_TO_BB_REFCLK_N

90_PCIE_BB_TO_AP_RXD_C_P
90_PCIE_BB_TO_AP_RXD_C_N

BI

OUT
OUT

IN
IN

57

57

57

17 5

17 5

PCIE LINK 4

LINK4

PCIE_TX4_P
PCIE_TX4_N

PCIE_PERST4*

AU34
AV34

R35

90_PCIE_AP_TO_BB_TXD_C_P
90_PCIE_AP_TO_BB_TXD_C_N

PCIE_AP_TO_BB_PERST_L

OUT
OUT

OUT

17

17

57 8

A

8

67

SYNC_DATE=04/07/2017

PAGE TITLE

A

SOC: PCIE

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

11 OF 85

SHEET

8 OF 60

1

SIZE

D

SOC - MIPI

VIETMOBILE.VN

678

NEED MIPI LANE AND POLAIRTY SWAPPING MAP

3 245

1

D

(Analog)
VDD_FIXED_MIPID 0.769V - 0.85V @ TBDmA MAX
VDD_FIXED_MIPIC 0.769V - 0.85V @ TBDmA MAX
VDD_FIXED_MIPID_PLL 0.769V - 0.85V @ TBDmA MAX

PP0V8_SOC_FIXED_S1

7 8 10 14 17

20%

6.3V

1

2

F17

C1291

2.2UF

20%

6.3V

X5R-CERM

0201

ROOM=SOC

1

C1290

0.1UF

2

X5R-CERM

01005

ROOM=SOC

AM9

AP9

AL10

G18

VDD18_MIPIC

VDD18_MIPID

1

C1296

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1295

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

VDD18_MIPI*:1.62V - 1.98V @ TBDmA MAX

PP1V8_IO

D

17

C

MIPI lanes can all flip polarity for routing purposes

GNDed offpage on MLB

37

BI

37

BI

37

IN

37

IN

37

IN

37

IN

Juliet MIPI

17

IN

17

BI

17

BI

17

IN

17

IN

17

IN

17

IN

44

BI

44

BI

90_MIPI_JULIET_TO_AP_DATA0_P
90_MIPI_JULIET_TO_AP_DATA0_N

90_MIPI_JULIET_TO_AP_DATA1_P
90_MIPI_JULIET_TO_AP_DATA1_N

90_MIPI_JULIET_TO_AP_CLK_P
90_MIPI_JULIET_TO_AP_CLK_N

MIPI0C_REXT

9

GND

GND
GND

GND
GND

GND
GND

90_MIPI_AP_TO_DISPLAY_DATA0_P
90_MIPI_AP_TO_DISPLAY_DATA0_N

B9
A9

A11
B11

B10
A10

D11
D10

A8
B8

B6
A6

A7
B7

AY8

AW8

MIPI0C_DPDATA0
MIPI0C_DNDATA0

MIPI0C_DPDATA1
MIPI0C_DNDATA1

MIPI0C_DPCLK
MIPI0C_DNCLK

MIPI0C_REXT
MIPI1C_REXT

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1C_DPCLK
MIPI1C_DNCLK

MIPID_DPDATA0
MIPID_DNDATA0

< CANT SWAP DUE TO BiDi

< CANT SWAP DUE TO BiDi

VDD_FIXED_MIPIC

VDD_FIXED_MIPID

VDD_FIXED_MIPID_PLL

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 3 OF 16

ALT FUNC's

SIO_LEAP_MADI_IN and AOP_LEAP_MADI_IN

SIO_LEAP_MADI_OUT and AOP_LEAP_MADI_OUT

MTR_ADC_DOUT and

MTR_ADC_CLKOUT and SOC_DEBUG3

PLL_DIGOBS_IN_0 and

PLL_DIGOBS_IN_1 and

ISP_FCAM_SPMI_SDATA

ISP_FCAM_SPMI_SCLK

SOC_DEBUG2

SENSOR3_CLK

ISP_SPMI_SDATA

ISP_SPMI_SCLK

ISP_I2C0_SCL

ISP_I2C0_SDA

ISP_I2C1_SCL

ISP_I2C1_SDA

ISP_I2C2_SCL

ISP_I2C2_SDA

ISP_I2C3_SCL

ISP_I2C3_SDA

ISP_GPIO_0
ISP_GPIO_1
ISP_GPIO_2
ISP_GPIO_3
ISP_GPIO_4
ISP_GPIO_5
ISP_GPIO_6
ISP_GPIO_7
ISP_GPIO_8
ISP_GPIO_9

A16
C21

A17
B20

A18
C22

A19
A20

A23
A22
A21
B22
A15
B19
C20
A13
B13
D20

ISP_TO_WIDE_SHUTDOWN_L
ISP_TO_TELE_SHUTDOWN_L

NC_ISP_GPIO_3

ISP_TO_FCAM_SHUTDOWN_L

ISP_TO_JULIET_SHUTDOWN_L

NC_ISP_GPIO_7

ISP_TO_DISPLAY_FLASH_INT

I2C0_ISP_SCL
I2C0_ISP_SDA

I2C1_ISP_SCL
I2C1_ISP_SDA

I2C2_ISP_SCL
I2C2_ISP_SDA

I2C3_ISP_SCL
I2C3_ISP_SDA

SOC_DEBUG2

SOC_DEBUG3

RIGEL_TO_ISP_INT

OUT

BI

OUT

BI

OUT

BI

OUT

BI

OUT
OUT
OUT

OUT
OUT
OUT

OUT

53

53

53

53

53

53

53

53

31

32

5

5

34

37

44

IN

36 23 5

C

B

Display MIPI

44

44

44

44

44

44

44

44

57

44

90_MIPI_AP_TO_DISPLAY_DATA1_P

OUT

90_MIPI_AP_TO_DISPLAY_DATA1_N

OUT

90_MIPI_AP_TO_DISPLAY_DATA2_P

OUT

90_MIPI_AP_TO_DISPLAY_DATA2_N

OUT

90_MIPI_AP_TO_DISPLAY_DATA3_P

OUT

90_MIPI_AP_TO_DISPLAY_DATA3_N

OUT

90_MIPI_AP_TO_DISPLAY_CLK_P

BI

90_MIPI_AP_TO_DISPLAY_CLK_N

OUT

OUT

NC_DISP_BSYNC1

DISPLAY_TO_AP_BSYNC_WATCHDOG

IN

MIPID_REXT

9

NC_DISP_I2C_SCL
NC_DISP_I2C_SDA

AW7

AY7

AW5

AY5

AW4

AY4

AY6

AW6

AG4
AH3

AH4

AU9

AG3
AG2

MIPID_DPDATA1
MIPID_DNDATA1

MIPID_DPDATA2
MIPID_DNDATA2

MIPID_DPDATA3
MIPID_DNDATA3

MIPID_DPCLK
MIPID_DNCLK

DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1

DISP_TOUCH_EB

MIPID_REXT

ALT FUNC's

DISP_I2C_SCL
DISP_I2C_SDA

DISP_SPMI_SCLK
DISP_SPMI_SDATA

SENSOR0_CLK
SENSOR1_CLK
SENSOR2_CLK

A14
B14
B17

R1240

AP_TO_WIDE_CLK_R

AP_TO_TELE_CLK_R

AP_TO_FCAM_JULIET_RIGEL_CLK_RAP_TO_TOUCH_SCAN_CLK

33.2

1/32W
01005

ROOM=SOC

17

17

21

1%
MF

Series Terminations Offpage

AP_TO_WIDE_CLK

OUT

31

B

A

MIPI Reference

200

1%

1/32W

MF

01005

ROOM=SOC

1

2

R1250

200

1%

1/32W

MF

01005

ROOM=SOC

1

2

R1251

GNDed offpage on MLB

MIPI0C_REXT

MIPID_REXT

9

9

NC_DISP_POL

GND

17

AE5

AA2

DISP_POL

DISP_TE

PAGE TITLE

SOC: MIPI

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

12 OF 85

SHEET

9 OF 60

A

SIZE

D

8

67

35 4

2

1

SOC - LPDP

VIETMOBILE.VN

678

3 245

1

D

VDD12_PLL_LPDP 1.14V - 1.26V @ 8mA MAX
VDD12_LPDP_RX 1.14V - 1.26V @ 60mA MAX

PP1V2_SOC

8 17

Dan LPDP Lane Assignment

1

C1390

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1391

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1392

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC ROOM=SOC

1

2

GND'd offpage
GND'd offpage

C1393

0.01UF

10%

6.3V
X5R
01005

1

C1394

15PF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

Desense for Wifi frequencies

GND

17

GND

17

AM10

VDD12_LPDP_TX

F29

F27

VDD12_LPDP_RX

AM11

AM12

AM13

VDD12_PLL_LPDP

VDD_FIXED_LPDP_TX

VDD_FIXED_PLL_LPDP

VDD_FIXED_PLL_LPDP 0.769V - 0.85V @ 4mA MAX
VDD_FIXED_LPDP_RX 0.769V - 0.85V @ 50mA MAX

G28

F31

VDD_FIXED_LPDP_RX

1

C1395

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

(Analog)

PP0V8_SOC_FIXED_S1

1

C1396

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

7 8 9 14 17

D

C

Wide: 0-2
Tele: 3-5
Fcam: 6-7

Justin LPDP Lane Assignment

Wide: 2-4
Tele: 5-7
Fcam: 0-1

LPD Assigned off page

18

18

18

18

18

18

18

18

18

18

90_LPDP_WIDE_TO_AP_D0_P

IN

90_LPDP_WIDE_TO_AP_D0_N

IN

90_LPDP_WIDE_TO_AP_D1_P

IN

90_LPDP_WIDE_TO_AP_D1_N

IN

90_LPDP_WIDE_TO_AP_D2_P

IN

90_LPDP_WIDE_TO_AP_D2_N

IN

90_LPDP_TELE_TO_AP_D0_P

IN

90_LPDP_TELE_TO_AP_D0_N

IN

90_LPDP_TELE_TO_AP_D1_P

IN

90_LPDP_TELE_TO_AP_D1_N

IN

A25
B25

B26
C26

A27
B27

B28
C28

B30
C30

LPDPRX_RX_D0_P
LPDPRX_RX_D0_N

CYP-4GB-M-TMJA47A0-C7

LPDPRX_RX_D1_P
LPDPRX_RX_D1_N

LPDPRX_RX_D2_P
LPDPRX_RX_D2_N

LPDPRX_RX_D3_P
LPDPRX_RX_D3_N

LPDPRX_RX_D4_P
LPDPRX_RX_D4_N

U1000

WLCSP

SYM 4 OF 16

LPDP_TX0P

LPDP_TX0N

LPDP_TX1P

LPDP_TX1N

LPDP_TX2P

LPDP_TX2N

LPDP_TX3P

LPDP_TX3N

AY14
AW14

AY13
AW13

AY12
AW12

AY11
AW11

NC_LPDP_TX0_P
NC_LPDP_TX0_N

NC_LPDP_TX1_P
NC_LPDP_TX1_N

NC_LPDP_TX2_P
NC_LPDP_TX2_N

NC_LPDP_TX3_P
NC_LPDP_TX3_N

C

B

31

32

34

18

18

18

18

18

18

90_LPDP_TELE_TO_AP_D2_P

IN

90_LPDP_TELE_TO_AP_D2_N

IN

90_LPDP_FCAM_TO_AP_D0_P

IN

90_LPDP_FCAM_TO_AP_D0_N

IN

90_LPDP_FCAM_TO_AP_D1_P

IN

90_LPDP_FCAM_TO_AP_D1_N

IN

LPDP_WIDE_BI_AP_AUX

BI

LPDP_TELE_BI_AP_AUX

BI

LPDP_FCAM_BI_AP_AUX

BI

NC_LPDP_D2_AUX
NC_LPDP_D3_AUX
NC_LPDP_D4_AUX
NC_LPDP_D5_AUX
NC_LPDP_D6_AUX

A31
B31

B32
C32

A33
B33

D23
D24
C24
D25
D27
D29
D31
D33

LPDPRX_RX_D5_P
LPDPRX_RX_D5_N

LPDPRX_RX_D6_P
LPDPRX_RX_D6_N

LPDPRX_RX_D7_P
LPDPRX_RX_D7_N

LPDPRX_AUX_D0_P
LPDPRX_AUX_D1_P
LPDPRX_AUX_D2_P
LPDPRX_AUX_D3_P
LPDPRX_AUX_D4_P
LPDPRX_AUX_D5_P
LPDPRX_AUX_D6_P
LPDPRX_AUX_D7_P

LPDP_AUX_P
LPDP_AUX_N

EDP_HPD

DP_WAKEUP

AY10
AW10

AF2
AF4

NC_LPDP_AUX_P
NC_LPDP_AUX_N

NC_EPD_HPD

NC_DP_WAKEUP

B

A

1

R1300

200

1%
1/32W
MF
01005

2

ROOM=SOC

1

C1301

10PF

5%
16V

2

CERM
01005

ROOM=SOC

LPDPRX_RCAL_POS

LPDPRX_RCAL_NEG

A29
B29

LPDPRX_RCAL_P
LPDPRX_RCAL_N

LPDP_RCAL_P
LPDP_RCAL_N

AU10
AT10

NC_LPDP_RCAL_P
NC_LPDP_RCAL_N

PAGE TITLE

SOC: LPDP

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

13 OF 85

SHEET

10 OF 60

SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb

SIZE

D

A

8

67

35 4

2

1

SOC - SERIAL INTERFACES

VIETMOBILE.VN

678

3 245

1

D

40

42

I2S_AP_TO_CODEC_MCLK1

OUT

I2S_AP_TO_SPKAMP_TOP_MCLK

OUT

R1460

33.2

1%

1/32W

MF

01005

ROOM=SOC

R1464

33.2

1%

1/32W

MF

01005

ROOM=SOC

U1000

D

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 6 OF 16

21

40

40

40

40

I2S_AP_TO_CODEC_MCLK1_R
I2S_AP_TO_CODEC_ASP3_BCLK

OUT

I2S_AP_TO_CODEC_ASP3_LRCLK

OUT

I2S_CODEC_ASP3_TO_AP_DIN

IN

I2S_AP_TO_CODEC_ASP3_DOUT

OUT

NC_I2S1_MCLK
NC_I2S1_BCLK

48 5

48 5

40

21

57

57

57

57

AP_BI_CCG2_SWDIO

BI

AP_TO_CCG2_SWCLK

OUT

CODEC_TO_AP_INT_L

IN

I2S_AP_TO_SPKAMP_TOP_MCLK_R

I2S_BB_TO_AP_BCLK

OUT

I2S_BB_TO_AP_LRCLK

OUT

I2S_BB_TO_AP_DIN

IN

I2S_AP_TO_BB_DOUT

OUT

NC_AP_PDM_OUT0_DAT

AD35
AD37
AC34
AC35
AC36

AA35

Y37
Y34
Y35
Y36

AC37
AB34
AB35
AB36
AA37

AF36

I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT

I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT

I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT

AP_PDM_OUT0_DAT

GPIO SMC INT 8
GPIO SMC INT 9

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

I2C3_SCL

I2C3_SDA

SMC_I2CM0_SCL

SMC_I2CM0_SDA

SMC_I2CM1_SCL

SMC_I2CM1_SDA

ALT FUNC'S

SMC_UART0_RXD

SMC_UART0_TXD

C15
D17

L2
K5

K37
L34

M4
M5

AU24
AT24

AU20
AR24

AR23
AT20

CCG2_TO_SMC_INT_L
IKTARA_TO_SMC_INT

I2C0_AP_SCL
I2C0_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

I2C2_AP_SCL
I2C2_AP_SDA

I2C3_AP_SCL
I2C3_AP_SDA

I2C0_SMC_SCL
I2C0_SMC_SDA

I2C1_SMC_SCL
I2C1_SMC_SDA

OUT

BI

OUT

BI

OUT

BI

OUT

BI

OUT

BI

OUT

BI

IN
IN

52

52

52

54

60

52

52

52

54

58 52

58 52

60 54

60 54

48 5

I2C bus descriptions on 66-68

C

19 6

58

SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0

OUT

Hardwired as Board_ID3 -->

SPI_AP_TO_RACER_SCLK

OUT

R1465

0.00

0%

1/32W

MF

01005

ROOM=SOC

R1461

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

21

19 6 5

19 6

58

58

58

NC_I2S3_MCK
NC_I2S3_BCLK
NC_I2S3_LRCLK
NC_I2S3_DIN
NC_I2S3_DOUT

SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

IN

SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1

OUT

SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0_R

6

PP1V8_IO

IN

SPI_RACER_TO_AP_MISO

IN

SPI_AP_TO_RACER_MOSI

OUT

SPI_AP_TO_RACER_SCLK_R
SPI_AP_TO_RACER_CS_L

OUT

NC_SPI2_MISO
NC_SPI2_MOSI
NC_SPI2_SCLK
NC_SPI2_CS_L

AF37
AE34
AE35
AE37
AE36

AF34

AG37
AG35

AF35

AH36
AH35
AH34
AH37

V37
W35
W34

V35

I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

AP_PDM_OUT0_CLK
AP_PDM_IN2_CLK
AP_PDM_IN2_DAT
AP_PDM_IN1_DAT
AP_PDM_IN1_CLK

ALT FUNC'S
SPMI SCLK

SPMI SDATA

I2C4_SCL

I2C4_SDA

DWI_CLK

DWI_DO

G35
G34

J2
J3

I2C4_AP_SCL
I2C4_AP_SDA

NC_DWI_PMGR_TO_BACKLIGHT_CLK

NC_DWI_PMGR_TO_BACKLIGHT_DATA

17

17

OUT

BI

C

52

52

B

40

SPI_AP_TO_CODEC_SCLK

OUT

SPI: Route as Daisy-Chain. No T's Allowed

Place series terminations close to SoC Pins

R1462

0.00

0%

1/32W

MF

01005

ROOM=SOC

40 5

40 5

21

40

SPI_CODEC_TO_AP_MISO

IN

SPI_AP_TO_CODEC_MOSI

OUT

SPI_AP_TO_CODEC_SCLK_R
SPI_AP_TO_CODEC_CS_L

OUT

AD5
AD3
AD2
AD4

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

CLK24M_OUT

NAND_SYS_CLK

AP21

W36

AP_TO_RACER_REF_CLK_R

AP_TO_NAND_SYS_CLK_R

OUT

17

Series Terminations Offpage

B

R1480

23

NC_SPI4_MISO

PMU_TO_AP_DOUBLE_CLICK_DET_L

IN

NC_SPI4_SCLK

E37

F35
F37

SPI4_MISO
SPI4_MOSI
SPI4_SCLK

0.00

1/32W
01005

ROOM=SOC

21

0%
MF

AP_TO_NAND_SYS_CLK

OUT

19

Lynx

A1

VCC

C1490

2.2UF

6.3V

X5R-CERM

0201

ROOM=SOC

PP1V8_IO

1

20%

2

17

A

8

67

I2C4_AP_SDA

52

I2C4_AP_SCL

52

At EVT, check if we can remove

U1401

STLNXA1L9YZ2

WLCSP

B1

SDA NC

A2 C1

SCL

CRITICAL

VSS

B3

B2

C2

C3

A3

NC

NC
NC

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=04/05/2017

A

SOC: SERIAL

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

.

BRANCH

PAGE

14 OF 85

SHEET

11 OF 60

1

SIZE

D

SOC - GPIO INTERFACES

VIETMOBILE.VN

678

3 245

1

D

C

GPIOs are wired on page 70

AP_TO_BT_DEVICE_WAKE

55

BOARD_REV0

55

BOARD_REV1

55

BOARD_REV2

55

AP_TO_PMU_AMUX_SYNC

55

BOARD_REV3

55

AP_CANARY1

55

PMU_TO_AP_BUTTON_VOL_UP_L

55

NC_AP_GPIO8

55

AP_TO_BBPMU_RADIO_ON_L

55

AP_TO_SPKRAMP_TOP_RESET_L

55

AP_TO_NFC_FW_DWLD_REQ

55

AP_TO_BB_PEAK_POWER_INDICATOR

55

AP_TO_NFC_DEV_WAKE

55

CAMPMU_TO_AP_IRQ_L

55

AP_TO_GNSS_TIME_MARK

55

SPKRAMP_TOP_TO_AP_INT_L

55

BB_TO_AP_COEX

55

BT_TO_AP_TIME_SYNC

55

AP_TO_BB_RESET_L

55

BB_TO_AP_PEAK_POWER_INDICATOR

55

BB_TO_AP_RESET_DETECT_L

55

AP_TO_BB_COREDUMP_TRIG

55

AP_TO_CAMPMU_RESET_L

55

AP_TO_BB_COEX

55

DISPLAY_TO_AP_PANEL_ID

55

AP_CANARY2

55

NC_AP_GPIO27

55

NC_AP_GPIO28

55

AP_TO_RACER_RESET_L

55

GNSS_TO_AP_LOW_PWR_IND

55

K3

T4
T3

T2
U4
U2
Y2

AA3
AA4

K2

H35
H34

L4

K36
K35

G36

K34

J37
AB3
D16
D13
C14
D14

J35
H37
AB4
AC2
AB5
AC4

K4

AA5

GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 5 OF 16

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

UART0_RXD
UART0_TXD

UART1_CTS*
UART1_RTS*

UART1_RXD
UART1_TXD

UART2_CTS*
UART2_RTS*

UART2_RXD
UART2_TXD

UART3_CTS*
UART3_RTS*

UART3_RXD
UART3_TXD

UART4_CTS*
UART4_RTS*

UART4_RXD
UART4_TXD

UART6_RXD
UART6_TXD

UART7_RXD
UART7_TXD

R5
R4
R3

P36
P37

V2
V3
V4
V5

N35
N36
P34
P35

L37
M35
M37
N34

Y4
W3
W4
W5

D19
C18

L35
L36

PMU_TO_AP_PRE_UVLO_L

NC_TMR32_PWM1

AP_TO_WLAN_TIME_SYNC

UART_AP_DEBUG_RXD
UART_AP_DEBUG_TXD

UART_BT_TO_AP_CTS_L
UART_AP_TO_BT_RTS_L

UART_BT_TO_AP_RXD
UART_AP_TO_BT_TXD

NC_UART_WLAN_TO_AP_CTS_L
NC_UART_AP_TO_WLAN_RTS_L

NC_UART_WLAN_TO_AP_RXD
NC_UART_AP_TO_WLAN_TXD

UART_NFC_TO_AP_CTS_L
UART_AP_TO_NFC_RTS_L

UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_TXD

UART_GNSS_TO_AP_CTS_L
UART_AP_TO_GNSS_RTS_L

UART_GNSS_TO_AP_RXD
UART_AP_TO_GNSS_TXD

NC_UART6_RXD_L
NC_UART6_TXD_L

UART_ACCESSORY_TO_AP_RXD
UART_AP_TO_ACCESSORY_TXD

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

57

49

58

58

58

58

17

17

17

17

57

57

57

57

57

57

57

57

49

49

D

23 7 5

49 5

C

B

1

R1501

39.2K

1%
1/32W
MF
01005

2

ROOM=SOC

57 49

23

23

6 5

57 6

HYDRA_TO_AP_FORCE_DFU

IN

5

5

5

DFU_STATUS

OUT

PMU_TO_AP_BUTTON_POWER_KEY_L

IN

PMU_TO_AP_BUTTON_VOL_DOWN_L

IN

PAD_MTR_ANALOG_TEST_P

OUT

PAD_MTR_ANALOG_TEST_N

OUT

MTR_RREF_P
MTR_RREF_N

NC_PAD_MTR_VREF_P
NC_PAD_MTR_VREF_N

BOARD_ID0

IN

6

6

PP1V8_IO

IN

BOARD_ID2

IN

BOARD_ID4

IN

C17

C16

M3
M2

AM37
AM36

AK37
AK36

AL35
AL34

C13
H36

R2

T5

FORCE_DFU

DFU_STATUS

REQUEST_DFU1
REQUEST_DFU2

PAD_MTR_ANALOG_TEST_P
PAD_MTR_ANALOG_TEST_N

PAD_MTR_RREF_P
PAD_MTR_RREF_N

PAD_MTR_VREF_P
PAD_MTR_VREF_N

ALT FUNC

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID4

SOC_DEBUG1

B

A

8

67

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=04/05/2017

A

SOC: GPIO & UART

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

15 OF 85

SHEET

12 OF 60

1

SIZE

D

SOC - AOP

VIETMOBILE.VN

678

3 245

1

D

1.62V - 1.98V @ 10mA MAX

PP1V8_S2

15 17

1

C1690

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1691

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

AM19

AM17

AM25

AM23

D

C

ALT FUNC's

|
|
|

V

AOP_LPPLL

AOP_PDM_CLK4
AOP_PDM_CLK3

VDDIO18_AOP

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 7 OF 16

5

AOP_TO_DDR_SLEEP1_READY_PROBE

OUT

IMU_TO_AOP_DATARDY

56

SPI_AOP_TO_IMU_CS_L

56

AOP_TO_SPKAMP_BOT_RESET_L

56

SPI_AOP_TO_PHOSPHORUS_CS_L

56

PHOSPHORUS_TO_AOP_INT

56

ROMEO_TO_AOP_B2B_DETECT

56

RACER_TO_AOP_INT_L

56

AOP_TO_CODEC_RESET_L

56

NC_AOP_FUNC8

56

IMU_TO_AOP_INT

56

NC_AOP_FUNC10

56

NC_AOP_FUNC11

56

NC_AOP_FUNC12

56

AOP_TO_CODEC_CLP_EN

56

AOP_TO_BBPMU_COEX

56

PROX_BI_AOP_INT_L

56

POTASSIUM_TO_AOP_INT

56

HALL_CASE_TO_AOP_SOUTH_L

56

ALS_TO_AOP_INT_L

56

NFC_TO_AOP_HOST_WAKE

56

COMPASS_TO_AOP_INT

56

HALL_FLAP_TO_AOP_IRQ_L

56

SPKAMP_BOT_ARC_TO_AOP_INT_L

56

AU21

AP8

AP10

AT6

AR8
AT17
AP11
AP18

AR9
AP12
AR11
AU17
AR15
AR12

AT7

AR18

AT9
AP19
AT18

AT8
AU18
AT11

AU4

AT12

AON_SLEEP1_RESET*
AOP_FUNC[0]

AOP_FUNC[1]
AOP_FUNC[2]
AOP_FUNC[3]
AOP_FUNC[4]
AOP_FUNC[5]
AOP_FUNC[6]
AOP_FUNC[7]
AOP_FUNC[8]
AOP_FUNC[9]
AOP_FUNC[10]
AOP_FUNC[11]
AOP_FUNC[12]
AOP_FUNC[13]
AOP_FUNC[14]
AOP_FUNC[15]
AOP_FUNC[16]
AOP_FUNC[17]
AOP_FUNC[18]
AOP_FUNC[19]
AOP_FUNC[20]
AOP_FUNC[21]
AOP_FUNC[22]

<--

SCM_SPI CS & Trig

<

SCM_I2CM0 TRIGGER

SCM_I2CM1 TRIGGER

<

AOP_PDM_CLK0
AOP_PDM_DATA0
AOP_PDM_DATA1

RT_CLK32768

SWD_TMS2
SWD_TMS3

AOP_I2CM0_SCL

AOP_I2CM0_SDA

AOP_I2CM1_SCL

AOP_I2CM1_SDA

AOP_PDM_OUT0_CLK

AOP_PDM_DATAOUT

AT21
AT22
AU23

AP26

C19
B16

AP17
AP5

AR17
AT5

AT23
AU22

NC_SWD_TMS3

HALL_CASE_TO_AOP_NORTH_L

AOP_TO_CODEC_GPIO1
CODEC_TO_AOP_GPIO2

AOP_TO_GECKO_RESET_L

PMU_TO_AOP_CLK32K

SWD_AP_BI_NAND_SWDIO

I2C0_AOP_SCL
I2C0_AOP_SDA

I2C1_AOP_SCL_SOC

I2C1_AOP_SDA

GECKO_TO_AOP_IRQ_L

OUT

IN

OUT

IN

BI

OUT

BI

OUT

BI

56

56

40

40

56

54

54

54

54

C

23 5

19 5

ALT FUNC's

SMC_UART1_TXD
SMC_UART1_RXD

I2C bus descriptions on 66-68

B

A

50 43 42 41 40 5

50 43 42 41 40

28 5

ALT FUNC

AOP_PDM_CLK2

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK

IN

40

SPI_AOP_TO_IMU_SCLK

OUT

I2S_AOP_TO_CODEC_MCLK2

OUT

R1604

49.9

1%

1/32W

MF

01005

ROOM=SOC

R1605

49.9

1/32W
01005

ROOM=SOC

21

1%
MF

R1601

R1602

21

33.2

1%

1/32W

MF

01005

ROOM=SOC

33.2

1%

1/32W

MF

01005

ROOM=SOC

28 5

28 5

21

57

57

58

58

58

58

40

40

21

40

40

SPI_IMU_TO_AOP_MISO

IN

SPI_AOP_TO_IMU_MOSI

OUT

SPI_AOP_TO_IMU_SCLK_R

UART_BB_TO_AOP_RXD

IN

UART_AOP_TO_BB_TXD

OUT

AOP_TO_WLAN_CONTEXT_A

OUT

AOP_TO_WLAN_CONTEXT_B

OUT

UART_RACER_TO_AOP_RXD

IN

UART_AOP_TO_RACER_TXD

OUT

I2S_AOP_TO_CODEC_ASP2_BCLK

OUT

I2S_CODEC_ASP2_TO_AOP_DIN

IN

I2S_AOP_TO_CODEC_MCLK2_R
I2S_AOP_TO_CODEC_ASP2_LRCLK

OUT

I2S_AOP_TO_CODEC_ASP2_DOUT

OUT

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R

43 42 41 40

I2S_CODEC_ASP1_TO_AOP_AMPS_DIN

IN

AOP_TO_HALOGEN_AFE_EN

56

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R

50 43 40

I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT

OUT

AP6
AP7

AP16

AR5
AR6

AU16
AT16

AP4
AT4

AU11
AU19
AR20

AU7
AU8

AU5
AT19
AU12

AU6
AP20

AOP_SPI_MISO
AOP_SPI_MOSI
AOP_SPI_SCLK

AOP_UART0_RXD
AOP_UART0_TXD

AOP_UART1_RXD
AOP_UART1_TXD

AOP_UART2_RXD
AOP_UART2_TXD

AOP_I2S0_BCLK
AOP_I2S0_DIN
AOP_I2S0_MCK
AOP_I2S0_LRCK

AOP_I2S0_DOUT

AOP_I2S1_BCLK
AOP_I2S1_DIN
AOP_I2S1_MCK
AOP_I2S1_LRCK
AOP_I2S1_DOUT

AOP_PDM_CLK2

ALT FUNC's

AOP_PDM_IN1_CLK

AOP_PDM_IN2_CLK
AOP_PDM_IN2_DAT

B

NUB_DOCK_CONNECT

NUB_DOCK_ATTENTION

NUB_SWD_TCK_OUT

NUB_SPMI_SCLK

NUB_SPMI_SDATA

NUB_SWD_TMS0
NUB_SWD_TMS1

|
V

AR27
AP25
AP24
AR21

AR29
AR26

AP22

HYDRA_TO_NUB_DOCK_CONNECT

HYDRA_TO_NUB_INT

SWD_AOP_TO_MANY_SWCLK

SPMI_PMGR_TO_PMU_SCLK_R

SPMI_PMU_BI_PMGR_SDATA
SWD_AOP_BI_RACER_SWDIO

SWD_AOP_BI_BB_SWDIO

IN

IN

OUT

BI

BI
BI

ALT FUNC's

49

49

NUB_PDM_CLK1

58 19 5

23 5

58

57

|
V

R1603

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

SPMI_PMGR_TO_PMU_SCLK

OUT

23

A

PAGE TITLE

8

67

SOC: AOP

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

16 OF 85

SHEET

13 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

C

B

A

SOC - CPU, GPU & SOC RAILS

1.06V @ 13.8A MAX

0.905V @ 12.9A MAX

0.527V @ 2.4A MAX

PP_CPU_PCORE

17

Remote sense XW's for Buck0 Buck1 and Buck11 live off page

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

AD9
AD17
AE10
AE12
AE16
AF13
AF15

AG10

AJ10
AK13
AK15

V11

V13
W10
W14
W16

Y9

Y17

AL16
AL18
AL22
AL24

AM21

AL20

AB9
AB17
AE14
AF11
AH15
AK11

N12
U10

W12

F13
H11
H15
H19

J24
K13
K21

G22
M15
M19
M23

VDD_PCPU

VDD_LOW

VDD_LOW_ULPPLL
VDD_LOW_FLPPLL

VDD_CPU_SRAM

VDD_GPU_SRAM

SYM 8 OF 16

VDD_FIXED_PLL_SOC
VDD_FIXED_PLL_GPU

VDD_FIXED_PLL_ANE

VDD_FIXED_PLL_DDR0
VDD_FIXED_PLL_DDR1
VDD_FIXED_PLL_DDR2
VDD_FIXED_PLL_DDR3

ROOM=SOC

C1705

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1711

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1708

14UF

20%

4V

X5R

0402-D2X-1

1

3

4

2

ROOM=SOC

C1709

14UF

20%

4V

X5R

0402-D2X-1

1

3

4

2

ROOM=SOC

C1704

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1710

14UF

20%

4V

X5R

0402-D2X-1

1

432

VDD_LOW: 0.691V - 0.756V @ 75mA MAX
VDD_LOW_ULPPLL: 0.691V - 0.756V @ 0.3mA MAX

PP0V7_VDD_LOW_S2

17

R1702

C1751

4UF

20%

4V

X5R

0201

ROOM=SOC

1

2

C1750

4UF

20%

4V

X5R

0201

ROOM=SOC

1

2

100

5%

1/32W

MF

01005

ROOM=SOC

21

R1701

10

21

5%

1/32W

MF

01005

ROOM=SOC

1.02V @ 2.1A MAX

0.975V @ 1.4A MAX

0.765V @ 0.33A MAX

PP_CPU_SRAM

17

ROOM=SOC

C1773

14UF

20%

4V

X5R

0402-D2X-1

1

432

1.06V @ 0.6A MAX

0.725V @ 0.41A MAX

0.685V @ 0.39A MAX

PP_GPU_SRAM

17

ROOM=SOC

C1772

14UF

20%

4V

X5R

0402-D2X-1

1

4

2

3

1

C1702

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

ROOM=SOC

C1706

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1712

14UF

20%

4V

X5R

0402-D2X-1

1

432

PP0V7_VDD_LOW_ULPPLL_R

1

C1742

4UF

20%
4V

2

X5R
0201

ROOM=SOC

PP0V7_VDD_LOW_FLPPLL_R

1

C1743

0.47UF

20%

6.3V

2

X5R
01005

ROOM=SOC

ROOM=SOC

C1781

14UF

20%

4V

X5R

0402-D2X-1

1

432

C1703

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1707

14UF

20%

4V

X5R

0402-D2X-1

1

ROOM=SOC

C1713

14UF

20%

4V

X5R

0402-D2X-1

1

ROOM=SOC

C1782

14UF

20%

4V

X5R

0402-D2X-1

1

432

432

432

for dev board compapability

VDD_GPU

VDD_ECPU

VDD_FIXED_ECPU

VDD_FIXED_MTR

VDD_FIXED_PCPU

VDD12_PLL_SOC

VDD12_PLL_ANE
VDD12_PLL_PCPU
VDD12_PLL_ECPU

VDD12_PLL_GPU

F11
F15
G10
G12
G14
G16
G20
K25
G24
G26
H13
H17
H21
H25
J12
J14
J20
J22
H23
J26
K11
K15
K23
L10
L12
L14
L20
L22
L24
L26
M13
M17
M21
M25
N20
N22
N24
N26

N10
P9
P13
T9
T13
V9
U11

M11
AD31
U12

AE24
AE22
AD23

AH5
AJ29
D7
N29

AE23
AD24
U13
M12
AD22

1

C1730

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

ROOM=SOC

C1732

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1737

14UF

20%

4V

X5R

0402-D2X-1

1

432

1

C1731

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

ROOM=SOC

C1733

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1738

14UF

20%

4V

X5R

0402-D2X-1

1

432

C1734

0402-D2X-1

1

ROOM=SOC

C1739

0402-D2X-1

1

ROOM=SOC

C1791

14UF

20%

4V

X5R

0402-D2X-1

1

432

14UF

20%

4V

X5R

432

14UF

20%

4V

X5R

432

ROOM=SOC

C1792

14UF

0402-D2X-1

1

0402-D2X-1

20%

4V

X5R

432

1.06V @ 14.5A MAX

0.725V @ 6.3A MAX

0.570V @ 3.1A MAX

ROOM=SOCROOM=SOC

C1735

14UF

4V

X5R

1

432

ROOM=SOC

C1736

14UF

20%20%

4V

X5R

0402-D2X-1

1

432

0.945V @ 2.9A MAX

0.626V @ 1.2A MAX

0.517V @ 0.62A MAX

PP_CPU_ECORE

ROOM=SOC

C1793

14UF

20%

4V

X5R

0402-D2X-1

1

3

4

2

1

C1794

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

VDD_FIXED_PCPU: 0.81V @ 5mA

VDD_FIXED_MTR 0.769V - 0.85V @ TBDmA
VDD_FIXED_ECPU: 0.769V - 0.85V @ 5mA

PP0V8_SOC_FIXED_S1
PP0V8_SOC_FIXED_S1
PP0V8_SOC_FIXED_S1

VDD_FIXED_PLL_DDR3: 0.81V @ 8mA
VDD_FIXED_PLL_DDR2: 0.81V @ 8mA

PP0V8_SOC_FIXED_S1

VDD_FIXED_PLL_SOC: 0.81V @ 9mA
VDD_FIXED_PLL_GPU: 0.81V @ 5mA

VDD_FIXED_PLL_ANE: 0.81V @ 5mA
VDD_FIXED_PLL_DDR0: 0.81V @ 8mA
VDD_FIXED_PLL_DDR1: 0.81V @ 8mA
VDD_FIXED_PLL_LPDP: 0.81V @ 2mA

VDD12_PLL_SOC: 1.14 - 1.26V @ 8mA MAX

VDD12_PLL_ANE: 1.14 - 1.26V @ 7mA MAX
VDD12_PLL_PCPU: 1.14 - 1.26V @ 7mA MAX
VDD12_PLL_ECPU: 1.14 - 1.26V @ 7mA MAX

VDD12_PLL_GPU: 1.14 - 1.26V @ 7mA MAX

PP1V2_SOC

PP_GPU

17

14 17

7 8 9 10 17

14 17

14 17

17

17

AA8
AA18
AA22
AA24
AA28
AA30
AB19
AB21
AB25
AB27

AC18
AC22
AC24
AC28
AD19
AD21
AD25
AD27

AE18
AE28
AF19
AF21
AF25
AF27

AG18
AG22
AG24
AG28

AH10
AH19
AH25
AH27

AJ16
AJ18
AJ22
AJ24

AJ28
AK19
AK21
AK25

F22
G19
H27

J10

1

C1760

4UF

20%
4V

2

X5R
0201

ROOM=SOC

VDD_SOC

1

C1761

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1762

14UF

20%

4V

X5R

0402-D2X-1

1

432

1

C1765

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1763

14UF

20%

4V

X5R

0402-D2X-1

1

432

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 9 OF 16

PAGE TITLE

ROOM=SOC

C1764

14UF

20%

4V

X5R

0402-D2X-1

1

432

J28
K27
L28
M27
N16
N18
N28
P15
P19
P25
P27
R16
R18
R22
R24
R28
R30
T15
T19
T21
T25
T27
U8
U16
U18
U22
U24
U28
U30
V15
V19
V21
V25
V27
W18
W22
W24
W28
W30
Y19
Y21
Y25
Y27

0.783V @ 4.2A MAX

0.661V @ 2.6A MAX

0.595V @ 2.1A MAX

PP_SOC_S1

D

17

C

B

A

8

67

1

C1720

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1721

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1722

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1723

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

SOC: POWER (1/3)

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

17 OF 85

SHEET

14 OF 60

1

SIZE

D

678

VIETMOBILE.VN

SOC - CPU, GPU & SOC RAILS

3 245

1

D

C

B

0.8V @ 900mA MAX

PP0V8_SOC_FIXED_S1

17

1

C1802

4UF

20%
4V

2

X5R
0201

ROOM=SOC

GPU_SENSE_POS

23 5

CPU_PCORE_SENSE_POS

23 5

SOC_SENSE_POS

1

C1803

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1804

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1801

14UF

20%

4V

X5R

0402-D2X-1

1

1

2

3

4

2

C1805

4UF

20%
4V
X5R
0201

ROOM=SOC

AA20
AA26
AB23
AB29

AC8
AC20
AC26
AD29
AE20
AE26

AF17
AF23

AF29
AG20
AG26

AH17
AH23
AH29

AJ20

AJ26

AK17
AK23

AL12

F19

P21

AG16

AH21

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 10 OF 16

VDD_FIXED VDD_FIXED

VDD_GPU_SENSE
VDD_PCPU_SENSE
VDD_SOC_SENSE

VSS_GPU_SENSE

VSS_PCPU_SENSE

VSS_SENSE

VSS_DDR_SENSE

H29
K29
M29
N8
N14
P17
P23
P29
R14
R20
R26
T17
T23
T29
U20
U26
V17
V23
V29
W8
W20
W26
Y23
Y29

P22
AH16
AH20
B4

VDDQL* TOTAL: 0.573V - 0.63V @ 620mA MAX

PP0V6_VDDQL_S1

15 17

GPU_SENSE_NEG

CPU_PCORE_SENSE_NEG

SOC_SENSE_NEG

VDDQL_DCS_SENSE_NEG

5

5

5 5

5

1

C1830

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1831

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1832

4UF

20%
4V

2

X5R
0201

ROOM=SOC

Place caps on SoC Corners

VDDQL_SENSE_POS

5

1

C1833

4UF

20%
4V

2

X5R
0201

ROOM=SOC

AC1
AE1
AG1
AG8

AL8
AN1
AR1
AU1

AC38
AE38

AF31

AG38

AK31
AN38
AR38
AU38

D1

F1
F8

H1

L8

P1

T1

V1

D38

F38
H31
H38

M31

P38

T38
V38

C4

CYP-4GB-M-TMJA47A0-C7

VDDQL_DDR0

VDDQL_DDR1

VDDQL_DDR2

VDDQL_DDR3

VDDQL_SENSE

U1000

WLCSP

SYM 11 OF 16

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

VDD1_DDR0

VDD1_DDR1

VDD1_DDR2

VDD1_DDR3

VDD2_DDR0

VDD2_DDR1

PP0V6_VDDQL_S1

15 17

AL4
AN35
G4
D35

AH2
N37

AA1
AV2

AA38
AV37

C2
Y1

C37
Y38

AB2
AH1
AK1
AM1
AU3

AB37
AH38
AK38
AM38
AU36

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

1

C1850

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1840

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

DDR IMPEDANCE CONTROL

1

R1860

240

1%
1/32W
MF
01005

2

ROOM=SOC

1

R1861

240

1%
1/32W
MF
01005

2

ROOM=SOC

VDD1_DDR*: 1.70V - 1.95V @ 220mA MAX

1

C1851

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1852

4UF

20%
4V

2

X5R
0201

ROOM=SOC

VDD2_DDR*: 1.06V - 1.17V @ 2.2A MAX

1

C1841

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1842

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

R1862

240

1%
1/32W
MF
01005

2

ROOM=SOC

1

C1843

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

2

ROOM=SOC

1

C1853

4UF

20%
4V

2

X5R
0201

ROOM=SOC

R1863

240

1%
1/32W
MF
01005

1

R1870

240

1%
1/32W
MF
01005

2

ROOM=SOC

PP1V8_S2

PP1V1_S2

1

R1871

240

1%
1/32W
MF
01005

2

ROOM=SOC

17

15 17

D

C

B

A

1.8V @ 75mA MAX (GRP)

1.8V @ 0.03mA MAX (MTR)

PP1V8_IO

17

20%

4V

X5R

1

2

C1810

26UF

0402-0.1MM

ROOM=SOC

C1811

4UF

20%

4V

X5R

0201

ROOM=SOC

1

2

C1812

ROOM=SOC

1

4UF

20%

4V

2

X5R X5R

0201

GRP2 IS AOP

C1813

4UF

20%

4V

0201

ROOM=SOC

PP1V1_S2

15 17

Current included in VDD2

PMU_TO_SYSTEM_COLD_RESET_L

rdar#: 29793211, This pin replaces the 4 DDR* sys alive pins

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 12 OF 16

1.8V @ 5.3mA MAX (CPU)

1.8V @ 1.1mA MAX (GPU)

1.8V @ 3.3mA MAX (SOC)

1.8V @ 0.3mA MAX (AMUX)

1.8V @ 1.5mA MAX (TSADC_SOC)

1.8V @ 1mA MAX (FMON)

57 23 7

1.8V @ 0.03mA MAX (ULPPLL)

AD8

M8

1

2

V8

AB31

P31

T31
V31
Y31

F21

F23

F25

AD30

VDDIO18_GRP1

VDDIO18_GRP3

VDDIO18_GRP4

VDDIO18_MTR

VDD18_TSADC_CPU0
VDD18_TSADC_CPU1
VDD18_TSADC_CPU2
VDD18_TSADC_CPU3
VDD18_TSADC_CPU4
VDD18_TSADC_CPU5

VDD18_TSADC_GPU0

VDD18_TSADC_ANE

VDD18_AMUX

VDD18_EFUSE1
VDD18_EFUSE2

VDD18_TSADC_SOC0
VDD18_TSADC_SOC1
VDD18_TSADC_SOC2

VDD18_FMON

VDD18_ULPPLL

P14
AF16
AA17
AE8
U14
N13

G15
AL14
AJ34
R8

AC30
AE29

D34
M9

AC29
AL21

C1871

2.2UF

20%

6.3V

X5R-CERM

0201

ROOM=SOC

PP1V8_FMON_R

PP1V8_ULPPLL_R

1

2

1

C1741

4UF

20%
4V

2

X5R
0201

ROOM=SOC

PP1V8_IO

ROOM=SOC

R1801

49.9

1%

MF

R1802

100

5%

1/32W

MF

01005

ROOM=SOC

7 15 17

21

1/32W

01005

21

0.912V @ 950mA MAX

0.761V @ 600mA MAX

0.631V @ 350mA MAX

PP_DCS_S1

17

1

2

PP1V8_IO

PP1V8_S2

C1860

4UF

20%
4V
X5R
0201

ROOM=SOC

1

C1861

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1862

4UF

20%
4V

2

X5R
0201

ROOM=SOC

Place caps on SoC Corners

DCS_SENSE_POS

5

7 15 17

13 17

1

C1863

4UF

20%
4V

2

X5R
0201

ROOM=SOC

AL5

AN34

G5

C35
AL3
AF9

AL9

AE30
AK30

F9

K9

G30
M30

A4

VDDIO11_RET_DDR0
VDDIO11_RET_DDR1
VDDIO11_RET_DDR2
VDDIO11_RET_DDR3

LP4_IN_RESET*

VDD_DCS_DDR0

VDD_DCS_DDR1

VDD_DCS_DDR2

VDD_DCS_DDR3

VDD_DCS_SENSE

VDD2_DDR2

VDD2_DDR3

VDDIO12_PLL_DDR0
VDDIO12_PLL_DDR1
VDDIO12_PLL_DDR2
VDDIO12_PLL_DDR3

D3
J1
L1
N1
W2

D36
J38
L38
N38
W37

AG5
AK29
D6
N30

VDD12_PLL_DDR* Total: 1.14V - 1.26V @ 10mA MAX

PP1V2_SOC

PAGE TITLE

SOC: POWER (2/3)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

17

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

18 OF 85

SHEET

15 OF 60

A

SIZE

D

8

67

35 4

2

1

SOC - POWER SUPPLIES

VIETMOBILE.VN

678

3 245

1

D

C

B

A1
A2
A3

A5
A12
A24
A26
A28
A30
A32
A34
A35
A36
A37
A38

AA9
AA19
AA21
AA23
AA25
AA27
AA29
AA31
AA34
AA36

AB1

AB8
AB18
AB20
AB22
AB24
AB26
AB28
AB30
AB38

AC3

AC5

AC9
AC17
AC19
AC21
AC23
AC25
AC27
AC31

AD1
AD18
AD20
AD26
AD28
AD34
AD36
AD38

AE9

AE11
AE13
AE15
AE17
AE19
AE21
AE25
AE27
AE31

AF1
AF3
AF5

AF8
AF10
AF12
AF14
AF18
AF20
AF22
AF24
AF26
AF28
AF30

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 13 OF 16

VSSVSS

AF38
AG9
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG29
AG34
AG36
AJ4
AH18
AH22
AH24
AH26
AH28
AJ1
AJ3
AJ5
AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ36
AJ37
AJ38
AK2
AK3
AK4
AK5
AK10
AK12
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK34
AK35
AL1
AL2
AL11
AL13
AL15
AL17
AL19
AL23
AL25
AL29
AL31
AL36
AL37
AL38
AM2
AM3
AM4
AM5
AM8
AM16
AM18
AM20
AM22
AM24
AM28
AM30
AM34
AM35
AN2
AN3
AN4

AN5
AN36
AN37

AP1

AP2

AP3
AP31
AP34
AP35
AP36
AP37
AP38

AR2

AR3

AR4

AR7
AR10
AR13
AR16
AR19
AR22
AR25
AR28
AR30
AR32
AR36
AR37

AT1

AT2

AT3

AT25
AT26
AT27
AT28
AT29
AT30
AT32
AT33
AT34
AT35
AT36
AT37
AT38

AU2
AU25
AU27
AU29
AU31
AU33
AU35
AU37

AV1

AV3

AV4

AV5

AV6

AV7

AV8

AV9
AV10
AV11
AV12
AV13
AV14
AV15
AV16
AV17
AV18
AV19
AV20
AV21
AV22
AV23
AV24
AV25
AV27
AV29
AV31

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 14 OF 16

VSSVSS

AV33
AV35
AV36
AV38
AW1
AW2
AW3
AW9
AW15
AW18
AW24
AW26
AW28
AW30
AW32
AW34
AW36
AW37
AW38
AY1
AY2
AY3
AY9
AY15
AY18
AY24
AY26
AY28
AY30
AY32
AY34
AY36
AY37
AY38
B1
B2
B3
B5
B12
B15
B18
B21
B23
B24
B34
B35
B36
B37
B38
C1
C3
C5
C6
C7
C8
C9
C10
C11
C12
C23
C25
C27
C29
C31
C33
C34
C36
C38
D2
D4
D5
D8
D9
D12
D15
D18
D21
D22
D26

D28
D30
D32
D37

E1
E2
E3
E4

E5
E34
E35
E36
E38

F2
F3
F4

F5
F10
F12
F14
F16
F18
F20
F24
F26
F28
F30
F34
F36

G1
G2

G3
G11
G13
G17
G21
G23
G25
G27
G29
G31
G38

H3

H4

H5
H10
H12
H14
H16
H18
H20
H22
H24
H26
H28
H30

J11
J13
J15
J21
J23
J25
J27
J29
J34
J36

K1

K8

K10
K12
K14
K20
K22
K24
K26

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 15 OF 16

VSSVSS

K28
K38
L3
L5
L9
L11
L13
L15
L21
L23
L25
L27
L29
M1
M10
M14
M16
M18
M20
M22
M24
M26
M28
M34
M36
M38
N9
N11
N15
N17
N19
N21
N23
N25
N27
N31
P3
P5
P8
P16
P18
P20
P24
P26
P28
P30
R1
R9
R13
R15
R17
R19
R21
R23
R25
R27
R29
R31
R34
R36
R38
T8
T14
T16
T18
T20
T22
T24
T26
T28
T30
U1
U3
U5
U9
AJ2

U15
U17
U19
U21
U23
U25
U27
U29
U31
U38
V10
V12
V14
V16
V18
V20
V22
V24
V26
V28
V30
V34
V36

W1

U1000

CYP-4GB-M-TMJA47A0-C7

WLCSP

SYM 16 OF 16

VSSVSS

W9
W11
W13
W15
W17
W19
W21
W23
W25
W27
W29
W31
W38
Y3
Y5
Y8
Y18
Y20
Y22
Y24
Y26
Y28
Y30

AE4

D

C

B

A

8

67

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: POWER (3/3)

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

19 OF 85

SHEET

16 OF 60

1

SIZE

D

Medusa Compatibility

VIETMOBILE.VN

678

3 245

1

PCIE Series Caps

D

43 42 41 36 33 29 26 24 22 17

59 47 46 40 36 29 24 22

59 47 45 44

PP_VDD_MAIN

MAKE_BASE=TRUE

PP_VDD_BOOST

MAKE_BASE=TRUE

PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN

PP_VDD_MAIN

PP_VDD_BOOST
PP_VDD_BOOST
PP_VDD_BOOST
PP_VDD_BOOST

PP_VDD_BOOST

21

21

21

21

21

21

21

21

21

21

21

21

22

21
22

22

22

22

22

22

6.3V

6.3V20%

6.3V

6.3V

21

01005

21

01005

21

01005

21

01005

0.22UF

0.22UF

0.22UF

0.22UF

0.1UF

0.1UF

0.1UF

0.1UF

90_PCIE_AP_TO_NAND_TXD_P
90_PCIE_AP_TO_NAND_TXD_N

90_PCIE_WLAN_TO_AP_RXD_P
90_PCIE_WLAN_TO_AP_RXD_N

90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_AP_TO_WLAN_TXD_N

IN
IN

OUT
OUT

C1100

90_PCIE_NAND_TO_AP_RXD_C_P 90_PCIE_NAND_TO_AP_RXD_P

8

90_PCIE_NAND_TO_AP_RXD_C_N 90_PCIE_NAND_TO_AP_RXD_N

8

GND_VOID

20%

X5R

C1101

GND_VOID

X5R 01005-1

C1102

90_PCIE_AP_TO_NAND_TXD_C_P

8

90_PCIE_AP_TO_NAND_TXD_C_N

8

GND_VOID

20%

X5R 01005-1

C1103

GND_VOID

20%

X5R 01005-1

21

01005-1

ROOM=SOC

21

ROOM=SOC

21

ROOM=SOC

21

ROOM=SOC

C1130

90_PCIE_WLAN_TO_AP_RXD_C_P

8

90_PCIE_WLAN_TO_AP_RXD_C_N

8

GND_VOID

20% 6.3V

X5R-CERM

ROOM=SOC

C1131

GND_VOID

20% 6.3V

X5R-CERM

ROOM=SOC

C1132

90_PCIE_AP_TO_WLAN_TXD_C_P

8

90_PCIE_AP_TO_WLAN_TXD_C_N

8

GND_VOID

20% 6.3V

X5R-CERM

ROOM=SOC

C1133

GND_VOID

20% 6.3V

X5R-CERM

ROOM=SOC

OUT
OUT

58

58

58

58

19

IN

19

IN

44

PP1V26_S2

19

19

20 17
29 22

CAMPMU_TO_JULIET_DVDD_LDO_EN

30 5

C4080

0.47UF

20%

6.3V
X5R

01005

ROOM=B2B_PEARL

20%

6.3V
X5R

1

2

1

C4081

0.47UF

2

01005

ROOM=B2B_PEARL

IN OUT

B1

EN

U4002

SCY99224-1.20V

WLCSP

CRITICAL

ROOM=B2B_PEARL

GND

B2

A2A1

1

2

PP1V1_CAM_JULIET_DVDD

C4082

2.2UF

20%

6.3V
X5R-CERM
0201

ROOM=B2B_PEARL

37

D

FF Touch Compatibility Compatibility

23

PMU_TO_TOUCH_CLK32K

1

C3072

1000PF

10%
10V

2

X5R
01005

ROOM=PMU

PMU_TO_TOUCH_CLK32K

MAKE_BASE=TRUE

ACORN_GECKO_ANSEL_TO_PMU_ADC

MAKE_BASE=TRUE

Place Near PMU

58

60 47 30 23

C

22

20

44 29 22 20 17

20 5

20 5

20

22

57 26 23 22

54 50 49 48 42 41 40 38 25 20

59

PP2V5_LDO0_S2

MAKE_BASE=TRUE

PP1V1_S2

MAKE_BASE=TRUE

PP1V26_S2

MAKE_BASE=TRUE

PP_CPU_PCORE

MAKE_BASE=TRUE

PP_GPU

MAKE_BASE=TRUE

PP_SOC_S1

MAKE_BASE=TRUE

PP1V2_SOC

MAKE_BASE=TRUE

PP1V8_ALWAYS

MAKE_BASE=TRUE

PP1V8_S2

MAKE_BASE=TRUE

PP2V5_LDO0_S2

PP1V1_S2
PP1V1_S2
PP1V1_S2

PP1V26_S2

PP_CPU_PCORE

PP_GPU

PP_SOC_S1

PP1V2_SOC
PP1V2_SOC
PP1V2_SOC

PP1V8_ALWAYS

PP1V8_S2
PP1V8_S2
PP1V8_S2

22

15

22

22

22

14 17

14 17

14

14

15

8 10

15

23

13 15

90_PCIE_BB_TO_AP_RXD_C_P

8 5

90_PCIE_BB_TO_AP_RXD_C_N

8 5

90_PCIE_AP_TO_BB_TXD_C_P

8

90_PCIE_AP_TO_BB_TXD_C_N

8

AP_TO_TELE_CLK_R

9

AP_TO_FCAM_JULIET_RIGEL_CLK_R

9

21

01005

21

01005

21

01005

21

0.1UF
90_PCIE_BB_TO_AP_RXD_P

90_PCIE_BB_TO_AP_RXD_N

0.1UF

0.1UF
90_PCIE_AP_TO_BB_TXD_P

90_PCIE_AP_TO_BB_TXD_N

0.1UF

C1120

GND_VOID

X5R-CERM

C1121

GND_VOID

X5R-CERM

C1122

GND_VOID

X5R-CERM

C1123

GND_VOID

X5R-CERM

20% 6.3V

ROOM=SOC

20% 6.3V

ROOM=SOC

20% 6.3V

ROOM=SOC

20% 6.3V

PACK_TYPE=01005

ROOM=SOC

FF Specific CLK Series Terminations

R1241

33.2

1/32W
01005

ROOM=SOC

21

1%
MF

R1242

33.2

1/32W

01005

ROOM=SOC

21

1%
MF

R1243

33.2

1/32W
01005

ROOM=SOC

21

1%
MF

AP_TO_TELE_CLK

AP_TO_JULIET_CLK

AP_TO_RIGEL_CLK

OUT

OUT

OUT

32

37

36

IN
IN

OUT
OUT

57

57

57

57

NC_DISPLAY_TO_CHESTNUT_PWR_EN

23

Dev Board Power Compability

43 42 41 36 33 29 26 24 22 17

VDD_MAIN_SNS

OUT

22

BUCK11_FB

23

21

NC_UART_WLAN_TO_AP_CTS_L
NC_UART_AP_TO_WLAN_RTS_L

MAKE_BASE=TRUE

NC_UART_WLAN_TO_AP_RXD

MAKE_BASE=TRUE

NC_UART_AP_TO_WLAN_TXD

MAKE_BASE=TRUE

MAKE_BASE=TRUE

Dev Board Compatiblity GNDs

GND

10

GND

10

FF Display Compatibility

NC_DISPLAY_TO_CHESTNUT_PWR_EN

Should live on PMU LDO page by caps

59 47 45 44

GND

PP_VDD_MAIN

XW2990

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

NC_UART_WLAN_TO_AP_CTS_L
NC_UART_AP_TO_WLAN_RTS_L

OMIT

MAKE_BASE=TRUE

NC_UART_WLAN_TO_AP_RXD
NC_UART_AP_TO_WLAN_TXD

BUCK11_FB

MAKE_BASE=TRUE

IN

OUT

IN

OUT

MAKE_BASE=TRUE

C

21 17

12

12

12

12

B

37 36 34 32 31 30 29 20 19 6

53 52 44

20

20

20

PP1V8_IO

MAKE_BASE=TRUE

PP_CPU_SRAM

MAKE_BASE=TRUE

PP_GPU_SRAM

MAKE_BASE=TRUE

PP_DCS_S1

MAKE_BASE=TRUE

PP1V8_IO
PP1V8_IO
PP1V8_IO
PP1V8_IO
PP1V8_IO

PP_CPU_SRAM

PP_GPU_SRAM

PP_DCS_S1

7 15

11

8

15

9

14

14

15

AP_TO_RACER_REF_CLK_R

11

R1244

33.2

1/32W
01005

ROOM=SOC

21

1%
MF

R1481

0.00

0%

1/32W

MF

01005

ROOM=SOC

GND

7

GND

AP_TO_FCAM_CLK

21

AP_TO_RACER_REF_CLK

OUT

OUT

34

58

7

7

9

9

9

9

9

9

9

9

GND
GND

GND
GND

GND

GND

GND
GND

GND

B

MAKE_BASE=TRUE

UF Dam Caps

PP0V6_VDDQL_S1

21 17

A

PP0V6_VDDQL_S1

21 17

MAKE_BASE=TRUE

PP_CPU_ECORE

21

MAKE_BASE=TRUE

PP3V3_USB

22

MAKE_BASE=TRUE

PP0V7_VDD_LOW_S2

22

MAKE_BASE=TRUE

PP0V8_SOC_FIXED_S1

20

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP0V6_VDDQL_S1

PP_CPU_ECORE

PP3V3_USB

PP0V7_VDD_LOW_S2

PP0V8_SOC_FIXED_S1
PP0V8_SOC_FIXED_S1
PP0V8_SOC_FIXED_S1

GND

15

14 17

7

14

15

7 8 9 10 14

14

22

PP_GPU

14 17

Dev Board Compatibility FB XW's

OMIT

XW1731

SHORT-20L-0.05MM-SM

21

ROOM=SOC

NO_XNET_CONNECTION

BUCK1_FB

20

PP_CPU_ECORE

14 17

NC_DWI_PMGR_TO_BACKLIGHT_CLK

MAKE_BASE=TRUE

NC_DWI_PMGR_TO_BACKLIGHT_DATA

MAKE_BASE=TRUE

Place near SOC Balls

OMIT

XW1790

SHORT-20L-0.05MM-SM

2 1

ROOM=SOC

BUCK11_FB

GND

OUT OUTOUT

GND
GND
GND

GND

NC_DWI_PMGR_TO_BACKLIGHT_CLK

NC_DWI_PMGR_TO_BACKLIGHT_DATA

21 17

PP_CPU_PCORE

14 17

23

23

23

23

11

11

OMIT

XW1701

SHORT-20L-0.05MM-SM

2 1

ROOM=SOC

BUCK0_FB

20

1

C2000

220PF

5%
25V

2

COG
01005

ROOM=SOC

PAGE TITLE

SOC: DEV BOARD ALIASES

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

20 OF 85

SHEET

17 OF 60

SYNC_DATE=04/17/2017

SYNC_MASTER=

SIZE

D

A

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

D

D

C

31

31

31

31

31

31

32

32

32

32

90_LPDP_WIDE_TO_AP_D0_P

IN

90_LPDP_WIDE_TO_AP_D0_N

IN

90_LPDP_WIDE_TO_AP_D1_P

IN

90_LPDP_WIDE_TO_AP_D1_N

IN

90_LPDP_WIDE_TO_AP_D2_P

IN

90_LPDP_WIDE_TO_AP_D2_N

IN

90_LPDP_TELE_TO_AP_D0_P

IN

90_LPDP_TELE_TO_AP_D0_N

IN

90_LPDP_TELE_TO_AP_D1_P

IN

90_LPDP_TELE_TO_AP_D1_N

IN

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

90_LPDP_WIDE_TO_AP_D0_P
90_LPDP_WIDE_TO_AP_D0_N

90_LPDP_WIDE_TO_AP_D1_P
90_LPDP_WIDE_TO_AP_D1_N

90_LPDP_WIDE_TO_AP_D2_P
90_LPDP_WIDE_TO_AP_D2_N

90_LPDP_TELE_TO_AP_D0_P
90_LPDP_TELE_TO_AP_D0_N

90_LPDP_TELE_TO_AP_D1_P
90_LPDP_TELE_TO_AP_D1_N

10

10

10

10

10

10

10

10

10

10

C

B

32

32

34

34

34

34

90_LPDP_TELE_TO_AP_D2_P

IN

90_LPDP_TELE_TO_AP_D2_N

IN

90_LPDP_FCAM_TO_AP_D0_P

IN

90_LPDP_FCAM_TO_AP_D0_N

IN

90_LPDP_FCAM_TO_AP_D1_P

IN

90_LPDP_FCAM_TO_AP_D1_N

IN

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

90_LPDP_TELE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D2_N

90_LPDP_FCAM_TO_AP_D0_P
90_LPDP_FCAM_TO_AP_D0_N

90_LPDP_FCAM_TO_AP_D1_P
90_LPDP_FCAM_TO_AP_D1_N

10

10

10

10

10

10

B

A

8

67

SYNC_DATE=08/17/2017

PAGE TITLE

A

SOC: LPDP ALIASES

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02545

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

21 OF 85

SHEET

18 OF 60

1

391mA MAX

VIETMOBILE.VN

678

3 245

1

D

34 32 31 30 29 20 19 17 6

53 52 44 37 36

1

2

PP1V8_IO

C2624

2.2UF

20%

6.3V
X5R-CERM
0201

ROOM=NAND

1

C2641

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2643

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2626

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2629

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=NAND

1

C2645

2.2UF

20%

6.3V

2

X5R-CERM
0201

1

C2610

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=NAND

1

C2630

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=NAND

1

C2647

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NANDROOM=NAND

S4E NAND

D

C

1

C2611

220PF

5%
25V

2

COG
01005

ROOM=NAND

932mA MAX

PP0V9_NAND

22

1

C2622

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2612

220PF

5%
25V

2

COG
01005

ROOM=NAND

1

C2627

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2618

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C2602

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=NAND

1

C2640

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2614

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C2605

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=NAND

1

C2642

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2615

47PF

5%
16V

2

CERM
01005

ROOM=NAND

1

C2600

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2644

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2617

22PF

5%
16V

2

CERM
01005

ROOM=NAND

1

C2601

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2646

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2613

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=NAND

1

C2616

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=NAND

1

C2619

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=NAND

1100mA MAX (1us peak power)

PP2V63_NAND

1

C2621

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=NAND

C

22

B

1

C2603

220PF

5%
25V

2

COG
01005

ROOM=NAND

1

C2606

220PF

5%
25V

2

COG
01005

ROOM=NAND

1

R2604

3.01K

1%
1/32W
MF
01005

2

ROOM=NAND

1

C2609

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

8 5

8 5

11

17

17

17

17

1

C2607

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND ROOM=NAND

1

C2608

47PF

5%
16V

2

CERM
01005

5

5

1

C2604

22PF

5%
16V

2

CERM
01005

ROOM=NAND

NAND_ANI1_VREF

OUT

NAND_ANI0_VREF

OUT

XW2600

SHORT-20L-0.05MM-SM

2 1

ROOM=NAND

Place near C2629

PP1V8_IO_PCI_AVDD

OMIT

J8

N8

J6

M9

N6

PCI_VDD_1

PCI_AVDD_H

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

L2J4G12

PCI_VDD_2

ANI0_VREF

AVDD18_PLL

G8

G6

ANI1_VREF

L6

L8

VDD

R6

R8

E10

E2

U2600

J2

N2

K9

VDDIO

T5

P9

D3

E12

G4

L12

VCC

R2

NC

F3

R4

VPP

VDD_PLL

1

C2649

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2650

2

1

C2638

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

2.2UF

20%

6.3V
X5R-CERM
0201

ROOM=NAND

1

C2651

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2639

68PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C2652

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=NAND

1

C2634

47PF

5%
16V

2

CERM
01005

ROOM=NAND

1

C2635

22PF

5%
16V

2

CERM
01005

ROOM=NAND

1

C2636

220PF

5%
25V

2

COG
01005

ROOM=NAND

1

C2637

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

B

H23Q2T8QK6MES-BC

AP_TO_NAND_SYS_CLK

IN

90_PCIE_AP_TO_NAND_REFCLK_P

IN

90_PCIE_AP_TO_NAND_REFCLK_N

IN

8

PCIE_NAND_BI_AP_CLKREQ_L

BI

PCIE_NAND_RESREF
90_PCIE_AP_TO_NAND_TXD_P

IN

90_PCIE_AP_TO_NAND_TXD_N

IN

90_PCIE_NAND_TO_AP_RXD_P

OUT

90_PCIE_NAND_TO_AP_RXD_N

OUT

M3

CLK_IN

K11

PCIE_REFCLK_P

J12

PCIE_REFCLK_M

P5

PCIE_CLKREQ_N

H7

PCI_RESREF

M11

PCIE_RX0_P

N12

PCIE_RX0_M

R12

PCIE_TX0_P

T11

PCIE_TX0_M

LGA

ROOM=NAND

BOMOPTION=OMIT_TABLE

CRITICAL

EXT_D0/BOOT0
EXT_D1/BOOT1

EXT_D2/BOOT2/SPINAND_SCLK

EXT_D3/SWD_UID0/SPINAND_MISO

EXT_D4/UART_RX

EXT_D5/SWD_UID1/SPINAND_MOSI

EXT_D6/UART_TX

EXT_D7/SPF

EXT_NCE/PERST*

EXT_NRE/JTAG_TMS

EXT_NWE/JTAG_TCK

EXT_RNB/JTAG_TDO

EXT_CLE/JTAG_TDI

EXT_ALE/JTAG_SEL

B3
C4
B5
C6
B7
C8
B9
B11

E8
D7
E6
E4
D5
D9

NC

NC

NC

PMU_TO_NAND_LOW_BATT_BOOT_L

AP_TO_NAND_FW_STRAP
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1

SYSTEM_ALIVE

PCIE_AP_TO_NAND_PERST_L

SWD_AP_BI_NAND_SWDIO

SWD_AOP_TO_MANY_SWCLK

IN
IN
IN

OUT

IN

IN

IN

BI

IN

55

7

11 6

11 6 5

11 6

26 23

8

13 5

58 13 5

7 5

A

AP_TO_NAND_RESET_L

IN

Board trace <= 0.2Ohm

NAND_ZQ_ANI
NAND_ZQ_NAND

1

R2600

100

0.1%
1/32W
MF
01005

2

ROOM=NAND

8

1

R2601

300

0.1%
1/32
MF
01005

2

ROOM=NAND

L4

G10

K3

C10

RESET*
TRST*
ZQ_C

ZQ_N

A4

A2

67

A6

A8

A10

A12

B1

B13

C2

C12

D1

D11

D13

F1

F5

F7

F9

F11

F13

H1

H3

H5

H9

H11

H13

VSS

J10

K1

K5

K7

K13

L10

M1

M5

M7

M13

N4

N10

P1

P3

P7

P11

P13

R10

T1

T7

T9

T13

U2

U4

U6

DROOP_N

WP_N

U8

U12

U10

T3
G2

PP1V8_IO

53 52 44

37 36 34 32 31 30 29 20 19 17 6

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=03/22/2017

A

NAND

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

26 OF 85

SHEET

19 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

C

17

BUCK4

4.9A MAX2.1A MAX

17

BUCK5

1.7A Capable

Trimmed to 1.4A Max

44 29 22 17

BUCK6

2.1A MAX

PP1V1_S2

1

C2744

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

PP0V8_SOC_FIXED_S1

PP1V26_S2

1

C2764

4UF

20%
4V

2

X5R
0201

ROOM=PMU

(Place C2763 Close to Ansel)

1

C2743

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2763

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2742

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2752

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2762

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2741

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2751

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2761

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2740

220PF

5%
25V

2

COG
01005

ROOM=PMU

1

C2750

220PF

5%
25V

2

COG
01005

ROOM=PMU

1

C2760

220PF

5%
25V

2

COG
01005

ROOM=PMU

L2740

0.47UH-20%-4.5A-0.047OHM

BUCK4_LX0

21

PIJR20120H-SM

ROOM=PMU

L2741

0.22UH-20%-5.3A-0.04OHM

21

BUCK4_LX1

1608

ROOM=PMU

OMIT

XW2740

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

BUCK4_FB

L2750

1UH-20%-2.2A-0.06OHM

21

BUCK5_LX0

PIJR20120H-SM

ROOM=PMU

OMIT

XW2750

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

BUCK5_FB

L2760

1UH-20%-3.0A-0.06OHM

2 1

PIJR2016-SM

ROOM=PMU

OMIT

XW2760

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

BUCK6_LX0

BUCK6_FB

V7

W7

Y7

V5

W5

Y5

T5

BUCK4_FB

A6
B6
C6

E5

BUCK5_FB

V3

W3

Y3

T4

BUCK6_FB

BUCK4_LX0

BUCK4_LX1

BUCK5_LX0

BUCK6_LX0

U2700

D2542A0P0VQAVAC

WLCSP

SYM 2 OF 5

CRITICAL

ROOM=PMU

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK0_FB

BUCK1_LX0

BUCK1_LX1

L16
L17
L18

N16
N17
N18

R16
R17
R18

U16
U17
U18

N13

BUCK0_FB

A15
B15
C15

A13
B13
C13

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK1_LX0

BUCK1_LX1

L2700

0.47UH-20%-4.5A-0.047OHM

21

PIJR20120H-SM

ROOM=PMU

L2701

0.22UH-20%-5.3A-0.04OHM

21

1608

ROOM=PMU

L2702

0.1UH-20%-9.4A-0.022OHM

21

1608

ROOM=PMU

L2703

0.1UH-20%-9.4A-0.022OHM

21

1608

ROOM=PMU

17

IN

1

C2700

220PF

5%
25V

2

COG
01005

ROOM=PMU

1

C2701

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2706

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

L2710

0.47UH-20%-4.5A-0.047OHM

21

PIJR20120H-SM

ROOM=PMU

L2711

0.22UH-20%-5.3A-0.04OHM

21

1608

ROOM=PMU

1

C2702

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2703

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2710

220PF

5%
25V

2

COG
01005

ROOM=PMU

1

C2704

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2711

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

0.4V - 1.15V

PP_CPU_PCORE

1

C2705

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

0.4V - 1.06V

1.03V for overdrive only

1

C2712

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2713

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

PP_GPU

17 5

13.8A MAX

BUCK0

D

14.3A Capable Trimmed to 10A Max

17 5

BUCK1

C

B

BUCK7

BUCK8

2.1A MAX1.25A MAX

BUCK9

0.735V - 1.01V

PP_CPU_SRAM

17

0.675V - 1.06V

PP_GPU_SRAM

17

0.600V - 0.875V

PP_DCS_S1

17

1

C2793

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

NOSTUFF

1

C2772

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2782

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2792

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2771

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2781

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2791

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2770

220PF

5%
25V

2

COG
01005

ROOM=PMU

1

C2780

220PF

5%
25V

2

COG
01005

ROOM=PMU

1

C2790

220PF

5%
25V

2

COG
01005

ROOM=PMU

L2770

1UH-20%-3.0A-0.06OHM

2 1

PIJR2016-SM

ROOM=PMU

OMIT

XW2770

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

BUCK7_LX0

BUCK7_FB

L2780

1UH-20%-2A-0.069OHM

2 1

2012

ROOM=PMU

OMIT

XW2780

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

BUCK8_LX0

BUCK8_FB

L2790

1UH-20%-2A-0.069OHM

2 1

2012

ROOM=PMU

OMIT

XW2790

SHORT-20L-0.05MM-SM

21

ROOM=PMU

BUCK9_LX0

BUCK9_FB

W16
W17
W18

T13

A17
B17

C17

E14

G1
G2

F4

BUCK7_LX0

BUCK7_FB

BUCK8_LX0

BUCK8_FB

BUCK9_LX0

BUCK9_FB

BUCK1_LX2

BUCK1_LX3

BUCK1_FB

BUCK2_LX0

BUCK2_LX1

BUCK2_FB

A11
B11
C11

A9
B9
C9

E9

BUCK1_FB

V9
W9
Y9

V11
W11
Y11

T12

BUCK2_FB

BUCK1_LX2

NC_BUCK1_LX3_1
NC_BUCK1_LX3_2
NC_BUCK1_LX3_3

BUCK2_LX0

BUCK2_LX1

17

IN

L2720

0.47UH-20%-4.5A-0.047OHM

21

PIJR20120H-SM

ROOM=PMU

L2721

0.22UH-20%-5.3A-0.04OHM

21

1608

ROOM=PMU

OMIT

XW2720

SHORT-20L-0.05MM-SM

21

ROOM=SOC

NO_XNET_CONNECTION

L2712

0.1UH-20%-9.4A-0.022OHM

21

1608

ROOM=PMU

1

C2720

220PF

5%
25V

2

COG
01005

ROOM=PMU

1

C2721

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2722

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2716

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

2

C2723

26UF

20%
4V
X5R
0402-0.1MM

ROOM=PMU

(Place in TTS)

1

C2714

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2724

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2715

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

0.67V/0.80V

PP_SOC_S1

17

4.9A MAX

BUCK2

B

A

BUCK3_LX0

BUCK3_FB

VBUCK3_SW

BUCK3_SW1

BUCK3_SW2
BUCK3_SW3
BUCK3_SW4

A4
B4
C4

E4

C1
C2

A2
B1
B2

D2
E1
D1

BUCK3_LX0

BUCK3_FB

L2730

1UH-20%-3.0A-0.06OHM

21

PIJR2016-SM

ROOM=PMU

OMIT

XW2730

SHORT-20L-0.05MM-SM

21

ROOM=PMU

PP1V8_TOUCH_RACER_S2

PP1V8_IO

PP1V8_IMU_S2

PP1V8_NFC_S2

1

C2730

220PF

5%
25V

2

COG
01005

ROOM=PMU

53 52

59

58

1

C2731

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

PP1V8_S2

59 54 50

1

C2732

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

44 37 36 34 32 31 30 29 19 17 6

SYNC_MASTER=test_mlb

PAGE TITLE

49 48 42 41 40 38 25 17

BUCK3

2.5A MAX

A

SYNC_DATE=03/10/2017

SYSTEM POWER: PMU Bucks (1/4)

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

54 50 28 27

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

27 OF 85

SHEET

20 OF 60

SIZE

D

8

67

35 4

2

1

PMU - BUCKS

VIETMOBILE.VN

678

3 245

1

D

C

PP_VDD_MAIN

17

PP_VDD_MAIN

17 21

PP_VDD_MAIN

17

C2854

4UF

20%

6.3V

CERM-X5R

0201

ROOM=PMU

1

C2850

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=PMU

1

2

1

C2581

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=PMU

PP_VDD_MAIN

17 21

1

C2852

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=PMU

C2855

4UF

20%

6.3V

CERM-X5R

0201

ROOM=PMU

D

U2700

D2542A0P0VQAVAC

WLCSP

17

1

2

PP_VDD_MAIN

17 21

4UF

20%

6.3V
0201

1

2

PP_VDD_MAIN

17 21

C2856

CERM-X5R

ROOM=PMU

VDD_MAIN_SNS

IN

C2857

4UF

20%

6.3V

CERM-X5R

0201

ROOM=PMU

1

2

R12

VDD_MAIN_SNS

M2

VDD_MAIN_0

F6

VDD_MAIN_1

F12

VDD_MAIN_2

T7

VDD_MAIN_3

V13

VDD_MAIN_4

P13

VDD_MAIN_5

M15
M16
M17
M18

T15
T16
T17
T18

A14
B14
C14
D14

A10
B10
C10
D10

V10

W10

Y10

VDD_BUCK0_01

VDD_BUCK0_23

VDD_BUCK1_01

VDD_BUCK1_23

VDD_BUCK2

SYM 3 OF 5

BUCK10_LX0

BUCK10_FB

BUCK11_LX0

BUCK11_LX1

BUCK11_FB

J1
J2

K4

J16
J17
J18

G16
G17
G18

F14

BUCK10_LX0

BUCK10_FB

BUCK11_LX0

BUCK11_LX1

BUCK11_FB

1UH-20%-2A-0.069OHM

0.47UH-20%-3.2A-0.042OHM

0.22UH-20%-5.3A-0.04OHM

L2800

21

2012

ROOM=PMU

OMIT

XW2800

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

L2810

21

PIJR20120H-SM

ROOM=PMU

L2811

21

1608

ROOM=PMU

17

IN

1

C2800

220PF

5%
25V

2

COG
01005

ROOM=PMU

1

C2810

220PF

5%
25V

2

COG
01005

ROOM=PMU

1

C2801

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2811

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2812

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2813

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2814

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

PP0V6_VDDQL_S1

0.415V - 1.06V

PP_CPU_ECORE

17

17

1.25A MAX 2.9A MAX

BUCK11BUCK10

C

B

PP_VDD_MAIN

17

C2858

4UF

6.3V

CERM-X5R

0201

ROOM=PMU

C2863

4UF

20%

6.3V

CERM-X5R

0201

ROOM=PMU

20%

1

PP_VDD_MAIN

17

2

1

PP_VDD_MAIN

17

2

C2859

CERM-X5R

ROOM=PMU

C2867

4UF

20%

6.3V

CERM-X5R

0201

ROOM=PMU

4UF

20%

6.3V
0201

1

2

1

PP_VDD_MAIN

17

2

PP_VDD_MAIN

17

C2860

4UF

6.3V

CERM-X5R

0201

ROOM=PMU

C2864

4UF

20%

6.3V

CERM-X5R

0201

ROOM=PMU

20%

1

2

1

2

PP_VDD_MAIN

17

PP_VDD_MAIN

17

C2861

4UF

20%

6.3V

CERM-X5R

0201

ROOM=PMU

C2865

4UF

20%

6.3V

CERM-X5R

0201

ROOM=PMU

1

PP_VDD_MAIN

17

4UF

20%

6.3V
0201

4UF

20%

6.3V
0201

1

2

1

2

2

1

PP_VDD_MAIN

17

2

C2862

CERM-X5R

ROOM=PMU

C2866

CERM-X5R

ROOM=PMU

A3
B3
C3

V6

W6

Y6

A7
B7
C7

V2

W2

Y2

Y15
Y16
Y17

B18
C18
D18

F1
F2

K1
K2

H16
H17
H18

VDD_BUCK3

VDD_BUCK4

VDD_BUCK5

VDD_BUCK6

B

VDD_BUCK7

VDD_BUCK8

VDD_BUCK9

VDD_BUCK10

VDD_BUCK11

A

8

67

A

SYNC_DATE=06/01/2017SYNC_MASTER=test_mlb

PAGE TITLE

SYSTEM POWER: PMU Bucks (2/4)

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

28 OF 85

SHEET

21 OF 60

1

SIZE

D

XW to VDD_MAIN_SNS lives on alias page

VIETMOBILE.VN

678

3 245

1

D

23

44 43 42 41 36 33 29 26 24 17

59 47 46 40 36 29 24 17

PMU_LDO5_UVLO_DET

OUT

59 47 45

PP_VDD_BOOST

XW2995

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

PP_VDD_MAIN

OMIT

1

C2970

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C2971

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C2991

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=PMU

PMU - LDOs

D

C

B

PMU_VSS_RTC

23

A1

A18

D5
D7

D8
D11
D13
D15
D16
D17
E11
E16
E18

G3
G15

J3

J15

K3

K14

L15

M6
M8

N9
N10
N11
N14
N15

P8
P11
P14

R8

R9
R10
R11
R14
R15

T3

T6

T8

U4

U5

U6

U8

U9
U11
U12
U15

V15

Y1

Y18

P2

VSS

VSS_XTAL

U2700

D2542A0P0VQAVAC

WLCSP

SYM 5 OF 5

VSS_SW_BUCK_0

VSS_SW_BUCK_0_11

VSS_SW_BUCK0_7

VSS_SW_BUCK1

VSS_SW_BUCK1_5

VSS_SW_BUCK2

VSS_SW_BUCK2_4

VSS_SW_BUCK4_6

VSS_SW_BUCK5_3

VSS_SW_BUCK8_1

VSSA_BUCK0
VSSA_BUCK1
VSSA_BUCK2
VSSA_BUCK3
VSSA_BUCK4
VSSA_BUCK5
VSSA_BUCK6
VSSA_BUCK7
VSSA_BUCK8

VSSA_BUCK9
VSSA_BUCK10
VSSA_BUCK11

T14
D9
U10
D3
U7
D6
U3
W15
E17
D4
H3
H15

P15
P16
P17
P18

K15
K16
K17
K18

V16
V17
V18

A12
B12
C12
D12

A8
B8
C8

V12
W12
Y12

V8
W8
Y8

V4
W4
Y4

A5
B5
C5

A16
B16
C16

PP_VDD_MAIN

17

PP_VDD_BOOST

17

PP_VDD_MAIN

17

PP1V1_S2

17

PP_VDD_BOOST

17

PP_VDD_BOOST

17

PP_VDD_BOOST

17

This cap also services LDO 14

PP_VDD_BOOST

17

PP1V26_S2

17

SHORTED TO BOOST ON D3X

GND

17

PP1V1_S2

17

PP2V5_LDO0_S2

17

17

GND

1

C2980

4UF

20%
4V

2

X5R
0201

ROOM=CAM_PMU

NC

R6

VDD_LDO0

M4

VDD_LDO1_3

R5

VDD_LDO2

T1

VDD_LDO4

V1

VDD_LDO5

W1

VDD_LDO5

M1

VDD_LDO6

L1

VDD_BYPASS

L4

VDD_LDO7

R1

VDD_LDO8

L6

VDD_LDO9

R7

VDD_LDO10

N4

VDD_LDO11_13

R4

VDD_LDO12

R3

VDD_LDO14

N6

VCC_LDOG

E13

VPP_OTP

N12

TP_DET

U2700

D2542A0P0VQAVAC

WLCSP

SYM 1 OF 5

VLDO0
VLDO1
VLDO2
VLDO3
VLDO4
VLDO5
VLDO6

VLDO7
VLDO8
VLDO9

VLDO10
VLDO11
VLDO12
VLDO13
VLDO14

VPUMP

P6
M5
P5
M3
T2
U1
L2

L3
R2
L5

P7
N5
P4
N3
P3

E2

NC_DENALI_LDO6

Job Taken by Gecko

NC_DENALI_LDO12

PMU_VPUMP

1

C2920

47NF

20%

6.3V

2

X5R-CERM
01005

ROOM=PMU

VPUMP: 10nF min. @4.6V

1

2

1

C2900

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

C2901

2.2UF

20%

6.3V
X5R-CERM
0201

ROOM=PMU

1

C2903

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

1

C2909

2

1

C2907

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

1.0UF

20%
10V
X5R-CERM
0201-1

ROOM=PMU

1

C2911

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

1

C2913

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

PP2V5_LDO0_S2

PP3V3_USB

PP1V8_AUDIO_VA_S2

PP3V0_PENROSE

PP0V7_VDD_LOW_S2

PP2V63_NAND

17

17

40

35

17

19

LDO 2,4,8 and 5 all have
STability caps off page

PP3V0_S2

PP0V9_NAND

19

PP1V8_ALWAYS

D3X Cap Off page

PP3V0_DISPLAY

PP1V2_SOC

44

17

PP1V2_CODEC_S2

PP1V0_DISPLAY_DVDD

D3X Cap Off page

1

C2916

0.47UF

20%

6.3V

2

X5R
01005

ROOM=PMU

44

C

LDO0 250 mA MAX
LDO1 50 mA MAX

LDO2 50 mA MAX
LDO3 50 mA MAX
LDO4 250 mA MAX
LDO5 1.15 A MAX

LDO6 110 mA MAX

LDO7 250 mA MAX

58 49 48 38

LDO8 800 mA MAX
LDO9 10 mA MAX

57 26 23 17

LDO10 250 mA MAX
LDO11 250 mA MAX
LDO12 50 mA MAX

42 41 40

LDO13 250 mA MAX
LDO14 250 mA MAX

B

H1

VSS_SW_BUCK9_10

A

VSS_SW_BUCK11

8

H2

F16
F17
F18

44 29 20 17

PP1V26_S2

67

U2900

SCY99224-1.10V

IN OUT

B1

EN

WLCSP

ROOM=PMU

CRITICAL

GND

B2

A2A1

1

C2917

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

PP1V1_RACER_S2

59

SYNC_MASTER=test_mlb

PAGE TITLE

SYSTEM POWER: PMU LDOs (3/4)

SIZE

Apple Inc.

DRAWING NUMBER

051-02545

REVISION

SYNC_DATE=03/10/2017

D

A

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

29 OF 85

SHEET

22 OF 60

1

678

VIETMOBILE.VN

3 245

1

TODO: Update

CONTROL PIN NOTES:

D

PMU - GPIOs

COLD_RESET & SYSTEM_ALIVE

PP1V8_S2

17

49

57 23 15 7

NOTE (1):INPUT PULL-DOWN 100-300k
NOTE (2):INPUT PULL-DOWN 1M
NOTE (3):INPUT PULL-UP OR DOWN 100k-300k
NOTE (4):OUTPUT OPEN-DRAIN, REQUIRES PULL-UP

D

R3010

200K

U2700

D2542A0P0VQAVAC

WLCSP

7

7

AP_TO_PMU_WDOG_RESET

IN

HYDRA_TO_PMU_HOST_RESET

IN

AP_TO_PMU_SOCHOT_L

IN

PMU_TO_SYSTEM_COLD_RESET_L

OUT

NC_PMU_SHDN

H8

J8

M10

F13

G13

RESET_IN1
RESET_IN2
RESET_IN3

RESET*

SHDN

SYM 4 OF 5

IREF

VREF

P9

P10

PMU_IREF

PMU_VREF

1/32W
01005

ROOM=PMU

C3010

0.22UF

01005-1

ROOM=PMU

1%
MF

20%

6.3V
X5R

21

21

C

B

1

R3061

100K

5%
1/32W
MF
01005

2

ROOM=PMU

C3041

100PF

NP0-C0G

01005

ROOM=PMU

C3042

100PF

NP0-C0G

01005

ROOM=PMU

C3044

100PF

NP0-C0G

01005

ROOM=PMU

5%

16V

5%

16V

5%

16V

1

R3062

100K

5%
1/32W
MF
01005

2

ROOM=PMU

SYSTEM_ALIVE

PMU_TO_SYSTEM_COLD_RESET_L

NTCs

FOREHEAD NTC

1

1

2

REAR CAMERA NTC

1

2

RADIO PA NTC on MLB Bottom

AP NTC

1

2

R3041

10KOHM-1%

01005

ROOM=PMU

2

1

R3042

10KOHM-1%

01005

ROOM=PMU

2

1

R3044

10KOHM-1%

01005

ROOM=PMU

2

26 23 19

57 23 15 7

FOREHEAD_NTC

FOREHEAD_NTC_RETURN

RCAM_NTC

RCAM_NTC_RETURN

nmapedit @mlb_top_lib.mlb_top(sch_1):page39;

AP_NTC

AP_NTC_RETURN

OMIT

23

XW3041

SHORT-20L-0.05MM-SM

ROOM=PMU

OMIT

23

23

XW3042

SHORT-20L-0.05MM-SM

ROOM=PMU

SHORT-20L-0.05MM-SM

21

21

OMIT

XW3044

21

ROOM=PMU

1

C3020

100PF

5%
16V

2

NP0-C0G
01005

ROOM=PMU

57 26 22 17

Only has DS control when powered by VBUCK3
Only has DS control when powered by VBUCK3

60 47 30 23 17

57

OUT

1

R3011

200K

1%
1/32W
MF
01005

2

ROOM=PMU

1

R3020

3.92K

0.1%
1/32W
TK
01005

2

ROOM=PMU

PP1V8_ALWAYS

3

VDD

49 7 5

17

26 23 19

58 30 24

11

54

54

13

13 5

17

49 46 23

55

17

44

36 9 5

7 5

58 55

57

58

26

PMU_TO_AP_HYDRA_ACTIVE_READY

OUT

PMU_TO_AOP_CLK32K

OUT

PMU_TO_TOUCH_CLK32K

OUT

SYSTEM_ALIVE

OUT

TOUCH_TO_MANY_FORCE_PWM

IN

PMU_TO_AP_DOUBLE_CLICK_DET_L

OUT

NC_PMU_CRASH_L
I2C1_SMC_SCL

IN

I2C1_SMC_SDA

BI

SPMI_PMGR_TO_PMU_SCLK

IN

SPMI_PMU_BI_PMGR_SDATA

BI

7

AP_TO_PMU_AMUX_OUT

IN

NC_DISPLAY_TO_CHESTNUT_PWR_EN

OUT

GND

17

GND

17

GND

17

HYDRA_TO_PMU_USB_BRICK_ID_TIA

IN

ACORN_GECKO_ANSEL_TO_PMU_ADC

IN

NC_PMU_AMUX_A7

PMU_AMUX_AY
AP_TO_PMU_AMUX_SYNC

IN

GND

IN

DISPLAY_TO_PMU_AMUX

IN

NC_AMUX_B3
NC_AMUX_B4

RIGEL_TO_ISP_INT

IN

AP_TO_PMU_TEST_CLKOUT

IN

PMU_TO_WLAN_CLK32K

IN

PMU_AMUX_BY

OUT

FOREHEAD_NTC

23

RCAM_NTC

23

RADIO_PA_NTC

IN

AP_NTC

23

CHARGER_NTC

IN

PMU_TCAL

PMU_VSS_RTC

23 22

XTAL_TO_PMU_CLK32K_2

23 5

PMU_VDD_RTC
PMU_VDD_REF

1

C3030

0.22UF

20%

6.3V

2

X5R
01005-1

ROOM=PMU

1

C3031

1.0UF

20%

10V

2

X5R-CERM
0201-1

ROOM=PMU

E12

K6
K7

K13

L9

M9

G12

G7
G6

H7
H6

E6
E7
E3

F3

F5
G4
G5

H4
H5

J6
J4
J5
J7

K8

L8

K5

L7

M7

Y13
Y14

W14

V14

W13

U14

P1
N1

N8
N2
N7

ACTIVE_RDY
SLEEP_32K

OUT_32K
SYS_ALIVE

FORCE_SYNC
DBLCLICK_DET

CRASH*

SCL
SDA
SCLK
SDATA

AMUX_A0
AMUX_A1
AMUX_A2
AMUX_A3
AMUX_A4
AMUX_A5
AMUX_A6
AMUX_A7
AMUX_AY

AMUX_B0
AMUX_B1
AMUX_B2
AMUX_B3
AMUX_B4
AMUX_B5
AMUX_B6
AMUX_B7
AMUX_BY

TDEV1
TDEV2
TDEV3
TDEV4
TDEV5
TCAL

XTAL1
XTAL2

VDD_RTC
VDD_REF
VDD_RTC_DIG

PRE_UVLO

UV_WARN0
UV_WARN1

UV_WARN11

UV_WARN0_DET
UV_WARN1_DET

UV_WARN11_DET

LDO5_UVLO_DET

IBAT

VBAT
BRICK_ID1
BRICK_ID2

ADC_IN

BUTTON1
BUTTON2
BUTTON3
BUTTON4

BUTTONO1
BUTTONO2
BUTTONO3

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25

FAULT_OUT*

P12

M14
F8
F15

M13
E8
E15

U2

T9
T10
R13
U13
T11

H14
J14
J13
H13

M11
L13
M12

G10
F11
F10
K9
H10
E10
F7
G8
G9
G11
K10
J9
H9
F9
J10
L14
L12
L11
J11
H11
L10
J12
H12
K12
K11

G14

PMU_TO_AP_PRE_UVLO_L

PMU_TO_AP_THROTTLE_PCORE_L

PMU_TO_AP_THROTTLE_GPU0_L

PMU_TO_AP_THROTTLE_ECORE_L

CPU_PCORE_SENSE_POS

GPU_SENSE_POS

BUCK11_FB

PMU_LDO5_UVLO_DET

PMU_VDD_MAIN_ISENSE
PMU_VDD_MAIN_VSENSE

HYDRA_TO_PMU_USB_BRICK_ID_TIA

PMU_VBATT_VSENSE

ACORN_GECKO_ANSEL_TO_PMU_ADC

BUTTON_VOL_DOWN_L

BUTTON_POWER_KEY_L

BUTTON_VOL_UP_L
BUTTON_RINGER_A

PMU_TO_AP_BUTTON_VOL_DOWN_L

PMU_TO_AP_BUTTON_POWER_KEY_L

PMU_TO_AP_BUTTON_VOL_UP_L

PMU_TO_CCG2_RESET_L

PMU_TO_AP_THROTTLE_GPU1_L

NC_BT_TO_PMU_HOST_WAKE

WLAN_TO_PMU_HOST_WAKE

BB_TO_PMU_PCIE_HOST_WAKE_L

PMU_NFC_TO_ARC_RESET_L

PMU_TO_GNSS_EN

PMU_TO_WLAN_CLK32K

PMU_TO_BT_REG_ON

PMU_TO_PHALANX2

YANGTZE_TO_PMU_INT_L

CODEC_TO_PMU_WAKE_L

PMU_MASK_NFC_TO_ARC_TRIG

PMU_TO_WLAN_REG_ON

PMU_TO_NFC_VDD_MAIN_EN

PMU_TO_NAND_LOW_BATT_BOOT_L

PMU_TO_PHALANX1
PMU_TO_DISPLAY_RESET_L
PMU_TO_BBPMU_RESET_R_L

PMU_TO_NFC_EN
NC_PMU_GPIO21

PMU_TO_IKTARA_EN_EXT_1V8

PMU_TO_BOOST_EN

PMU_TO_DISPLAY_PANICB
PMU_TO_DISPLAY_LDO_EN

PMU_TO_IKTARA_RESET_L

OUT

OUT
OUT
OUT

IN
IN
IN

IN

IN
IN
IN
IN
IN

IN
IN
IN
IN

OUT
OUT
OUT

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

55

OUT

12 7 5

7

7

7

15 5

15 5

17

22

C

26

26

49 46 23

26

60 47 30 23 17

27

35

27

27

12

12

55

B

58 45

20%

6.3V

1

2

NC

A

CHARGER NTC on Chrager Page

PMU_VSS_RTC

23 22

C3051

0.1UF

X5R-CERM

01005

NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC

8

67

Y3000

32.768KHZ-10PPM

CSP

1

NC

CLKOUT

GND

4

1

ROOM=PMU

SHORT-20L-0.05MM-SM

XW3000

2

OMIT

2

XTAL_TO_PMU_CLK32K_2

23 5

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=03/10/2017

A

SYSTEM POWER: PMU (4/4)

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

30 OF 85

SHEET

23 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

Boost Enable Pull

PMU_TO_BOOST_EN

55 24

1

R3100

511K

1%
1/32W
MF
01005

2

ROOM=BOOST

PART NUMBER

152S00871 L3100152S00869 ALT_PARTS

D

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

BOOST IND ALT, CYN

TABLE_ALT_ITEM

L3100152S00869152S00873 ALT_PARTS

BOOST IND ALT, TDK

C

52

I2C0_AP_SDA

BI

44 43 42 41 36 33 29 26 22 17

59 47 45

PP_VDD_MAIN

C3190

15UF

6.3V
CERM

0402-0.1MM

ROOM=BOOST

R3110

39.2

1%

1/32W

MF

01005

ROOM=BOOST

20%

21

BOOST

C

353S01124

When VDD_MAIN < 3.4, boosts to 3.4

1

2

1

L3100

MCFE2016TR47MHNA

MCFE2016-SM

ROOM=BOOST

CRITICAL

2

SYS_BOOST_LX

55 24

52

PMU_TO_BOOST_EN

IN

I2C0_AP_SCL

IN

I2C0_AP_BI_BOOST_SDA_R

A3
A4

C3
C4

A1
B2
C2
B1
C1

VIN

VIN

SW
SW

EN
SCL
SDA
VSEL
BYP*

CRITICAL

VOUT

U3100

VOUT

SN61280E

CSP

ROOM=BOOST

B3
B4

1

C3110

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=BOOST

1

C3111

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=BOOST

1

C3112

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=BOOST

1

C3113

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=BOOST

1

C3114

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=BOOST

1

C3115

220PF

5%
25V

2

COG
01005

ROOM=BOOST

Otherwise tracks VDD_MAIN

PP_VDD_BOOST

59 47 46 40 36 29 22 17

B

58 30 23

TOUCH_TO_MANY_FORCE_PWM

IN

A2

GPIO

PGND

D3

D2

D4

AGND

D1

BOOST_AGND

2

Tie directly to GND plane on layer 5

1

OMIT

XW3100

SHORT-20L-0.05MM-SM

ROOM=BOOST

B

A

8

67

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

SYSTEM POWER: Boost

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

31 OF 85

SHEET

24 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

D

BATTERY CONNECTOR

Rcpt: 516S00232
Plug: 516S00233

C

B

26

XW3200

VBATT_SENSE

OUT

PP_BATT_VCC I2C0_SMC_TO_GG_SCL_CONN

59 26

1

C3292

56PF

5%
25V

2

01005

ROOM=B2B_BATTERY

1

C3293

330PF

10%
16V

2

CER-X7RNP0-C0G-CERM
01005

ROOM=B2B_BATTERY

1

C3294

220PF

5%
25V

2

COG
01005

ROOM=B2B_BATTERY

SHORT-20L-0.05MM-SM

2 1

ROOM=B2B_BATTERY

PLACE_NEAR=J3200:2mm

NO_XNET_CONNECTION=1

J3200

B2B-BATT-RCPT

F-ST-SM

9

65

1
2

10

ROOM=B2B_BATTERY

3
4

87

CKPLUS_WAIVE=I2C_PULLUP

2

1

I2C0_SMC_BI_GG_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

2

1

Gas gauge I2C level translator

DZ3200

ESD202-B1-CSP01005

SG-WLL-2-2

ROOM=B2B_BATTERY

DZ3201

ESD202-B1-CSP01005

SG-WLL-2-2

ROOM=B2B_BATTERY

3

D

SYM_VER_3

RV3C002UN

Q3200

ROOM=B2B_BATTERY

ROOM=B2B_BATTERY

Q3201

RV3C002UN

SYM_VER_3

D

3

DFN

DFN

C

R3201

33

2

G S

1

1

GS

I2C0_BMU_SCL_R

PP1V8_S2

59

1

C3201

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_BATTERY

1/32W
01005

54 50 49 48 42 41 40 38 20 17

21

5%
MF

I2C0_SMC_SCL

54

IN

R3202

33

2

I2C0_BMU_SDA_R

1

C3202

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_BATTERY

1/32W
01005

21

5%
MF

I2C0_SMC_SDA

54

BI

B

A

8

67

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

SYSTEM POWER: B2B Battery

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

32 OF 85

SHEET

25 OF 60

1

SIZE

D

YANGTZE CHARGER

VIETMOBILE.VN

678

3 245

1

C3392

0.47UF

23

21

PMU_VDD_MAIN_ISENSEPMU_VDD_MAIN_VSENSE

23

D

PP_BATT_VCC

59 25

PMU_VBATT_VSENSE

23

1

C3353

2.2UF 2.2UF

20%
10V

2

X5R
0201

ROOM=CHARGER

1

C3380

2

1

C3352

20%
10V

2

X5R
0201

ROOM=CHARGER

0.1UF

20%

6.3V
X5R-CERM
01005

ROOM=CHARGER

R3380

12K

1/32W
01005

1

2

21

1%
MF

ROOM=CHARGER

C3351

220PF

5%
25V
COG
01005

ROOM=CHARGER

25

IN

PMU_VBATT_VSENSE_R

2

XW3300

SHORT-20L-0.05MM-SM

ROOM=BOOST

1

NO_XNET_CONNECTION=1

1

C3350

330PF

10%
16V

2

CER-X7R
01005

ROOM=CHARGER

VBATT_SENSE

OMIT

1

C3390

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=CHARGER

1

C3391

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=CHARGER

PP_VDD_MAIN_YANGTZE

R3300

1.00K

5%

1/32W

MF

01005

ROOM=CHARGER

NO_XNET_CONNECTION=1

OMIT

XW3301

ROOM=BOOST

NO_XNET_CONNECTION=1

20%

1

PMU_VDD_MAIN_VSENSE_R

2

2

1

6.3V
X5R

01005

ROOM=CHARGER

R3303

0.0025

1/3W
0402

1%
MF

1

R3301

1.00K

5%
1/32W
MF
01005

2

ROOM=CHARGER

NO_XNET_CONNECTION=1

PMU_VDD_MAIN_ISENSE_R

2

1

NO_XNET_CONNECTION=1

21

1

2

OMIT

XW3302

SHORT-20L-0.05MM-SMSHORT-20L-0.05MM-SM

ROOM=BOOST

PP_VDD_MAIN

C3345

220PF

5%
25V
COG
01005

ROOM=CHARGER

59 47 45 44 43

D

42 41 36 33 29 24 22 17

C

B

PP_VBUS1_E75

58 50

PP_VBUS2_IKTARA

59

NON-ZRB ALTS

PART NUMBER

57 23 22 17

55

OUT

138S00187138S00070

ALT_PARTS

PP1V8_ALWAYS

YANGTZE_TO_PMU_INT_L

C3310,C3311,C3312

1

R3330

100K

5%
1/32W
MF
01005

2

ROOM=CHARGER

1

C3301

1UF

10%
25V

2

X5R
402

ROOM=CHARGER

1

C3305

1UF

10%
25V

2

X5R
402

ROOM=CHARGER

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

NON-ZRB

1

C3341

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3306

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3303

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3307

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

TABLE_ALT_HEAD

TABLE_ALT_ITEM

49 48

23 19

49 5

1

C3304

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3308

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

YANGTZE_PMID

1

C3310

4.7UF

20%
25V

2

CER-X5R
0402-0.1MM

ROOM=CHARGER

1

C3322

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

PP_VAR_USB_RVP

OUT

54

54

I2C0_SMC_SDA

BI

I2C0_SMC_SCL

IN

SYSTEM_ALIVE

IN

HYDRA_TO_YANGTZE_VBUS1_VALID_L

IN

YANGTZE_VBUS_DETECT

1

C3323

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3311

4.7UF

20%
25V

2

CER-X5R
0402-0.1MM

ROOM=CHARGER

1

C3324

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3312

4.7UF

20%
25V

2

CER-X5R
0402-0.1MM

ROOM=CHARGER

1

2

C3325

220PF

5%
25V
COG
01005

ROOM=CHARGER

A5

VBUS1

B5

VBUS1

C5

VBUS1

D5

VBUS1

E5

VBUS1

G5

VBUS2

H5

VBUS2

J5

VBUS2

A6

PMID

B6

PMID

C6

PMID

D6

PMID

E6

PMID

F5

PMID

F6

PMID

G6

PMID

H6

PMID

J6

PMID

A3

AUX1

H3

SDA

G3

SCL

G4

SYS_ALIVE

C3

VBUS1_VALID*

B3

VBUS2_VALID*

F3

INT*

J3

VBUS1_DET

A1

BAT

B1

BAT

C1

BAT

D1

BAT

GND

F1

E1

BAT

BAT

U3300

SN2600B0

DSBGA

CRITICAL

ROOM=CHARGER

GND

GND

GND

A2

G1

BAT_SNS

VDD_MAIN

GND

GND

GND

D2

C2

B2

VDD_MAIN

VDD_MAIN

VDD_MAIN

GND

GND

F2

E2

VDD_MAIN

VDD_MAIN

BOOT1
BOOT2

ACT_DIODE*

LDO_IN
LDO_IN
LDO_IN

LDO_OUT

SW1
SW1
SW1
SW1

SW2
SW2
SW2
SW2

TEST1
TEST2
TEST3

NC
NC
NC
NC

NTC

A4
J4

A7
B7
C7
D7

F7
G7
H7
J7

H1
J1
J2

E3
E7

H4
B4
F4

D4
C4
E4
G2

H2

NC

NO_XNET_CONNECTION

C3340

0.1UF

YANGTZE_BOOT1

01005

ROOM=CHARGER

NO_XNET_CONNECTION

C3344

0.1UF

YANGTZE_BOOT2

20%
10V
X5R

01005

ROOM=CHARGER

YANGTZE_LX1

YANGTZE_LX2

1

2

BATTERY_NTC

21

20%
10V
X5R

21

C3360

220PF

5%
25V
COG
01005

ROOM=CHARGER

L3301

0.47UH-20%-5.6A-0.03OHM

21

YANGTZE_MID1LX

ROOM=CHARGER

L3303

0.47UH-20%-5.6A-0.03OHM

21

YANGTZE_MID2LX

MEHK2016-SM

ROOM=CHARGER

YANGTZE_LDO

1

C3361

2.2UF

20%
10V

2

X5R
0201

ROOM=CHARGER

26

1

C3362

2.2UF

20%
10V

2

X5R
0201

ROOM=CHARGER

NO_XNET_CONNECTION=1

L3302

0.47UH-20%-5.6A-0.03OHM

21

MEHK2016-SMMEHK2016-SM

ROOM=CHARGER

L3304

0.47UH-20%-5.6A-0.03OHM

21

MEHK2016-SM

ROOM=CHARGER

NO_XNET_CONNECTION=1

1

C3342

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3343

330PF

10%
16V

2

CER-X7R
01005

ROOM=CHARGER

C

B

A

R3332

7

USB_VBUS_DETECT

OUT

39K

1%

1/32W

MF

01005

ROOM=CHARGER

21

A8

B8

C8

D8

E8

F8

G8

H8

J8

BATTERY NTC

CHARGER NTC

C3370

100PF

5%

16V

NP0-C0G

01005

ROOM=CHARGER

1

1

2

I2

R3370

10KOHM-1%

01005

ROOM=CHARGER

2

BATTERY_NTC

26

SHORT-20L-0.05MM-SM

BATTERY_NTC_RETURN CHARGER_NTC

ROOM=CHARGER

OMIT

XW3370

21

C3045

100PF

5%

16V

NP0-C0G

01005

ROOM=PMU

1

2

1

I68

R3045

10KOHM-1%

01005

ROOM=PMU

2

23

OUT

CHARGER_NTC_RETURN

OMIT

XW3045

SHORT-20L-0.05MM-SM

21

ROOM=PMU

SYNC_MASTER=test_mlb

PAGE TITLE

SYSTEM POWER: Charger

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

33 OF 85

SHEET

26 OF 60

SYNC_DATE=10/13/2016

SIZE

A

D

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

Cyclone + Button Connnector

D

Cyclone Filtering

59

IKTARA_COIL2

BI

1

C3500

220PF

2%
50V

2

C0G
0201

ROOM=B2B_BUTTON

XW3500

SHORT-0201

21

ROOM=B2B_BUTTON

XW3501

SHORT-0201

21

ROOM=B2B_BUTTON

1

C3501

220PF

2%
50V

2

C0G
0201

ROOM=B2B_BUTTON

IKTARA_COIL2_CONN

27

BUTTON_VOL_DOWN_CONN_L

27

IKTARA_COIL2_CONN

27

BUTTON_VOL_UP_CONN_L

27

BUTTON_RINGER_A_CONN

27

IKTARA_COIL1_CONN

27

PP1V8_IMU_COMPASS_CONN

27

Rcpt: 516S00289
Plug: 516S00290

<-- This one on MLB

J3500

AA36D-S04VA1

F-ST-SM

PWR

PWR

ROOM=B2B_BUTTON

109

65

21
43

87

1211

COMPASS_TO_AOP_INT

I2C1_AOP_SCL

I2C1_AOP_SDA

27 54

27 54

D

56 27 5

C

59

IKTARA_COIL1

BI

BUTTONS

23

BUTTON_RINGER_A

OUT

1

C3510

220PF

2%
50V

2

C0G
0201

ROOM=B2B_BUTTON

XW3510

SHORT-0201

21

ROOM=B2B_BUTTON

XW3511

SHORT-0201

21

ROOM=B2B_BUTTON

R3520

499

1/32W
01005

ROOM=B2B_BUTTON

21

1%
MF

1

DZ3520

0201

5.5V-6.2PF

ROOM=B2B_BUTTON

2

1

C3511

220PF

2%
50V

2

C0G
0201

ROOM=B2B_BUTTON

IKTARA_COIL1_CONN

BUTTON_RINGER_A_CONN

1

C3520

22PF

2%
50V

2

C0G-CERM
0201

ROOM=B2B_BUTTON

27

27

Compass

FL3550

FERR-150OHM-25%-200MA

2 1

01005

ROOM=B2B_BUTTON

1

2

C3550

220PF

5%
25V
COG
01005

ROOM=B2B_BUTTON

C

PP1V8_IMU_COMPASS_CONNPP1V8_IMU_S2

27 54 50 28 20

B

23

23

BUTTON_VOL_DOWN_L

OUT

BUTTON_VOL_UP_L

OUT

C3530

220PF

ROOM=B2B_BUTTON

C3540

220PF

ROOM=B2B_BUTTON

5%
25V
COG

01005

5%
25V
COG

01005

R3530

100

1

2

1/32W
01005

ROOM=B2B_BUTTON

5%
MF

21

1

DZ3530

12V-33PF

01005-1

ROOM=B2B_BUTTON

2

BUTTON_VOL_DOWN_CONN_L

27

54 27

54 27

R3540

100

1

2

1/32W
01005

ROOM=B2B_BUTTON

5%
MF

21

1

DZ3540

12V-33PF

01005-1

2

ROOM=B2B_BUTTON

BUTTON_VOL_UP_CONN_L

27

56 27 5

I2C1_AOP_SCL

IN

I2C1_AOP_SDA

BI

COMPASS_TO_AOP_INT

OUT

1

C3531

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_BUTTON

NOSTUFF

1

C3532

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_BUTTON

NOSTUFF

1

C3533

220PF

5%
25V

2

COG
01005

ROOM=B2B_BUTTON

CKPLUS_WAIVE=I2C_PULLUP

CKPLUS_WAIVE=I2C_PULLUP

B

A

8

67

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

A

SYSTEM POWER: B2B Cyclone + Button

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02545

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

35 OF 85

SHEET

27 OF 60

1

678

VIETMOBILE.VN

3 245

1

D

D

Kobol - Accel & Gyro

C

56 5

56

54 50 28 27 20

IMU_TO_AOP_DATARDY

OUT

IMU_TO_AOP_INT

OUT

APN: 338S00367

PP1V8_IMU_S2

R3601

100K

5%

1/32W

MF

01005

ROOM=KOBOL

PP1V8_IMU_S2

1

C3600

0.1UF

20%

1

2

16

CRITICAL

1

VDDIOVDD

6.3V

2

X5R-CERM
01005

ROOM=KOBOL

1

C3601

0.1UF

20%

6.3V

2

X5R-CERM
01005

1

C3602

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=KOBOLROOM=KOBOL

54 50 28 27 20

C

U3600

BMI282AA

LGA

5

CS*

15

SM
INT

7

MOTION_INT

ROOM=KOBOL

SCLK

MOSI
MISO

2
3

46

SPI_AOP_TO_IMU_SCLKSPI_AOP_TO_IMU_CS_L
SPI_AOP_TO_IMU_MOSI

SPI_IMU_TO_AOP_MISO

OUT

ININ

IN

28 13 5 56

28 13 5

28 13 5

B

GND

9

8

10

11

12

13

14

B

A

28 13 5

28 13 5

56

Phosphorus

54 50 28 27 20

PP1V8_IMU_S2

ROOM=PHOSPHORUS

R3620

100K

5%

1/32W

MF

01005

1

2

6

8

VDD VDDIO

BOSCH (APN:338S00334)

1

C3620

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=PHOSPHORUS

1

C3622

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PHOSPHORUS

PP1V8_IMU_S2

U3620

SPI_AOP_TO_IMU_MOSI SPI_IMU_TO_AOP_MISO

IN

SPI_AOP_TO_IMU_SCLK

IN

SPI_AOP_TO_PHOSPHORUS_CS_L

IN

BMP284BA

SDI SDO

4

SCK

2

CS*

LGA

ROOM=PHOSPHORUS

GND

1

IRQ

53

7

PHOSPHORUS_TO_AOP_INT

OUT

OUT

54 50 28 27 20

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

SENSORS

28 13 5

56 5

Apple Inc.

DRAWING NUMBER

051-02545

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

36 OF 85

SHEET

28 OF 60

SIZE

D

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

Camera PMU

D

44 43 42 41 36 33 26 24 22 17

59 47 45

PP_VDD_MAIN

1

C3790

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=CAM_PMU

1

C3791

220PF

5%
25V

2

COG
01005

ROOM=CAM_PMU

J7

VDD_BUCK9

J8

VDD_BUCK9

C5

VDD_MAIN

E2

VDD_MAIN

G4

VDD_MAIN

VCC MAIN

U3700

D2462A1

WLCSP

SYM 1 OF 4

ROOM=CAM_PMU

CRITICAL

BUCKS

BUCK9_LX0
BUCK9_LX0

BUCK9_FB

H7
H8
H5

CAMPMU_BUCK_LX0

CAMPMU_BUCK_FB

CRITICAL

L3700

1UH-20%-2.5A-0.078OHM

21

PIWE20120H-SM

ROOM=CAM_PMU

XW3700

SHORT-20L-0.05MM-SM

21

ROOM=CAM_PMU

OMIT

1

C3700

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=CAM_PMU

PP2V85_VAR_CAM_VCM_PVDD

1

C3701

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=CAM_PMU

1

C3702

330PF

10%
16V

2

CER-X7R
01005

ROOM=CAM_PMU

D

31

C

59 47 46 40 36 24 22 17

44 22 20 17

PP_VDD_BOOST

PP1V26_S2

1

C3795

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C3797

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C3796

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C3798

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

A1

VDD_LDO4_17

H2

VDD_LDO9

B6

VDD_LDO10

B5

VDD_LDO15

A2

VDD_LDO4_17

B4

VDD_LDO18

U3700

D2462A1

WLCSP

SYM 2 OF 4

ROOM=CAM_PMU

CRITICAL

LDO OUTPUTLDO INPUT

VLDO4
VLDO9

VLDO10
VLDO15

VLDO17
VLDO18

B2
J2

A6
A5

B1
A4

1

C3704

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C3710

10UF

20%

6.3V

2

CERM-X5R
0402-0.1MM

ROOM=CAM_PMU

1

C3709

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C3715

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

PP2V85_FCAM_AVDD

PP_CAM_WIDE_ADC

PP1V1_CAM_WIDE_DVDD

PP1V1_FCAM_DVDD

PP2V85_CAM_TELE_AVDD

PP1V1_CAM_TELE_DVDD

34

31

<---- D3X has discrete Juliet DVDD LDO

31

34

32

32

AVDD: Analog Supply (Pixels)
ADC: ADC Supply
DVDD: Digital Supply
SVDD: AF Sensor Supply
PVDD: AF Driver Supply

C

B

For GPIO pullups only

37 36 34 32 31 30 20 19 17 6

53 52 44

PP1V8_IO

B3

VDD_LDO19

A7

VDD_LDO20_21

A8

VDD_LDO20_21

H1

VDD_LDO22

H3

VBUCK3

VLDO19
VLDO20

VLDO21
VLDO22

BUCK3_SW1

A3
B8

B7
G1

J3

NC

1

C3719

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C3721

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C3718

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C3720

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

PP2V85_CAM_JULIET_AVDD

PP2V85_CAM_WIDE_AVDD

37

31

PP3V3_ROMEO_WIDE_TELE_SVDD

PP_CAM_TELE_ADC

32

B

37 32 31

<---- Stability Cap on FF specific page

A

CAMPMU_VPUMP

1

C3751

47NF

20%

6.3V

2

X5R-CERM
01005

ROOM=CAM_PMU

J4

VPUMP

SW OUTPUTSW INPUT

ON_BUF

F2

CAMPMU_ON_BUF

C3750

0.22UF

6.3V

CER-X5R

01005

ROOM=CAM_PMU

10%

1

2

SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb

PAGE TITLE

A

CAMERA: PMU (1/2)

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

37 OF 85

SHEET

29 OF 60

8

67

35 4

2

1

Pull Downs

VIETMOBILE.VN

678

3 245

1

D

C

1

R3801

100K

5%
1/32W
MF
01005

2

ROOM=CAM_PMU

AP_TO_CAMPMU_RESET_L

1

C3800

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=CAM_PMU

53

55

57 55 30

I2C3_ISP_SDA

BI

CAMPMU_TO_AP_IRQ_L

OUT

1

R3800

200K

1%
1/32W
MF
01005

2

ROOM=CAM_PMU

1

C3810

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CAM_PMU

R3802

33.2

1%

1/32W

MF

01005

ROOM=CAM_PMU

21

R3803

49.9

1%

1/32W

MF

01005

ROOM=CAM_PMU

U3700

D2462A1

WLCSP

I2C

RESET

SYM 3 OF 4

ROOM=CAM_PMU

CRITICAL

GPIO

Alt Funcs

LPM_IN
FORCE_SYNC
BUCK9_VSEL

PRE-UVLO

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

GPIO9
GPIO10
GPIO11
GPIO12
GPIO15

NC

NC
NC

NC

E8

F8

D8
D6

F5

C1
D1
E1

J5

G5
C6

SCL
SDA

IRQ*
CRASH*
RESET_IN

VREF

IREF

VRTC

TDEV1
TDEV2

TCAL

REFERENCE

TEMPERATURE

53 33

I2C3_ISP_SCL

IN OUT

I2C3_ISP_SDA_U3700

21

30

57 55

CAMPMU_TO_AP_IRQ_R_L

AP_TO_CAMPMU_RESET_L

IN

CAMPMU_VREF
CAMPMU_IREF
CAMPMU_VRTC

F6
E6
D7
E4
D4
D3
F7
F3
G3
G2
E3

NC

NC
NC

NC

CAMPMU_TO_STROBE_DRIVER_HWEN

CAMPMU_TO_JULIET_DVDD_LDO_EN

CAMPMU_TO_RIGEL_ENABLE

PP1V8_IO

TOUCH_TO_MANY_FORCE_PWM

YOGI_TO_RIGEL_STATUS_R

MAMA_BEAR_BI_RIGEL_STATUS_R

OUT

OUT

MAKE_BASE=TRUE

IN

D

17 5

36 5

58 24 23

PP1V8_IO

53 52

44 37 36 34 32 31 29 20 19 17 6

ROOM=CAM_PMU

ROOM=CAM_PMU

R3811

10K

21

5%

1/32W

MF

01005

R3810

10K

21

5%

1/32W

MF

01005

YOGI_TO_RIGEL_STATUS

IN

MAMA_BEAR_BI_RIGEL_STATUS

38 36

C

BI

37 36

B

C2
C3
C4
C7
D2
D5

E5
F1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U3700

D2462A1

WLCSP

SYM 4 OF 4

ROOM=CAM_PMU

CRITICAL

AMUX_AY

ATM

G6

VSS

G7

VSS

G8

VSS

H4

VSS

H6

VSS

J1

VSS

J6

VSS

F4

VSS

C8
E7

ACORN_GECKO_ANSEL_TO_PMU_ADC

Advanced Test Mode (OTP rewrite)

OUT

60 47 23 17

B

A

8

67

SYNC_DATE=03/22/2017SYNC_MASTER=test_mlb

PAGE TITLE

A

CAMERA: PMU (2/2)

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

38 OF 85

SHEET

30 OF 60

1

SIZE

D

D

VIETMOBILE.VN

31

31

31

31

31

37 32 31 29

31

33 32 31

31 53

31 53

90_LPDP_WIDE_TO_AP_D0_CONN_N
90_LPDP_WIDE_TO_AP_D0_CONN_P

90_LPDP_WIDE_TO_AP_D2_CONN_N
90_LPDP_WIDE_TO_AP_D2_CONN_P

AP_TO_WIDE_CLK_CONN
PP3V3_ROMEO_WIDE_TELE_SVDD
PP1V8_CAM_WIDE_VDDIO_CONN
WIDE_AND_TELE_TO_STROBE_DRIVER_EN

I2C0_ISP_SDA
I2C0_ISP_SCL

678

Wide Camera Connector

Rcpt: 516S00313
Plug: 516S00314

GND_VOID

GND_VOID

GND_VOID GND_VOID

GND_VOID

<-- This one on MLB

ROOM=B2B_WIDE_RCAM

J3900

AA26DK-S026VA1

31

32

F-ST-SM

2827

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625

3029

GND_VOID

PP1V1_CAM_WIDE_DVDD_CONN

LPDP_WIDE_BI_AP_AUX_CONN

90_LPDP_WIDE_TO_AP_D1_CONN_N
90_LPDP_WIDE_TO_AP_D1_CONN_P

ISP_TO_WIDE_SHUTDOWN_L

WIDE_TO_TELE_SYNC

31

31

31

31

31 9

32

PP_CAM_VCM_PVDD_CONN

PP2V85_CAM_WIDE_AVDD_CONN

31

PP_CAM_WIDE_ADC

3 245

1

Power Filtering

FL3901

FERR-33OHM-25%-1.5A

PP2V85_VAR_CAM_VCM_PVDD

0201

ROOM=B2B_WIDE_RCAM

FL3995

10-OHM-750MA

37 36 34 32 30 29 20 19 17 6

53 52 44

37 32 31 29

PP1V8_IO

01005-1

ROOM=B2B_WIDE_RCAM

PP3V3_ROMEO_WIDE_TELE_SVDD

R3906

PP2V85_CAM_WIDE_AVDD

29

32 31

31 29

0.00

1/32W
01005

ROOM=B2B_BUTTON

21

0%
MF

PP2V85_CAM_WIDE_AVDD_CONN
PP_CAM_WIDE_ADC

1

C3997

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=B2B_WIDE_RCAM

21

21

_mod_write

1

C3991

220PF

5%
25V

2

COG
01005

ROOM=B2B_WIDE_RCAM

1

C3909

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=B2B_WIDE_RCAM

1

C3995

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=B2B_WIDE_RCAM

1

2

1

C3990

2

PP1V8_CAM_WIDE_VDDIO_CONN

1

C3996

220PF

5%
25V

2

COG
01005

ROOM=B2B_WIDE_RCAM

C3992

220PF

5%
25V
COG
01005

ROOM=B2B_WIDE_RCAM

PP_CAM_VCM_PVDD_CONN

220PF

5%
25V
COG
01005

ROOM=B2B_WIDE_RCAM

1

C3398

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=B2B_WIDE_RCAM

32 31 29

31

31

31 29

1

C3994

220PF

5%
25V

2

COG
01005

ROOM=B2B_WIDE_RCAM

D

C

ISP I2C

53 31

53 31

I2C0_ISP_SCL

IN

I2C0_ISP_SDA

BI

1

C3900

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_WIDE_RCAM

1

C3901

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_WIDE_RCAM

PP1V1_CAM_WIDE_DVDD

29

LPDP Filters

18

18

18

90_LPDP_WIDE_TO_AP_D0_P

OUT

90_LPDP_WIDE_TO_AP_D0_N

OUT

OUT

FL3903

FERR-33OHM-25%-1.5A

21

0201

ROOM=B2B_TELE_CAM

C3930

0.1UF

ROOM=B2B_WIDE_RCAM

20%

6.3V

X5R-CERM

01005

C3931

0.1UF

ROOM=B2B_WIDE_RCAM

20%

6.3V

X5R-CERM

01005

C3940

0.1UF

ROOM=B2B_WIDE_RCAM

20%

6.3V

X5R-CERM

01005

1

C3925

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=B2B_TELE_RCAM

21

GND_VOID

21

GND_VOID

21

GND_VOID

1

C3993

220PF

5%
25V

2

COG
01005

ROOM=B2B_WIDE_RCAM

90_LPDP_WIDE_TO_AP_D0_CONN_P

90_LPDP_WIDE_TO_AP_D0_CONN_N

90_LPDP_WIDE_TO_AP_D1_CONN_P90_LPDP_WIDE_TO_AP_D1_P

PP1V1_CAM_WIDE_DVDD_CONN

31

C

31

31

31

B

A

IO Filters

9

31 9

AP_TO_WIDE_CLK

IN

ISP_TO_WIDE_SHUTDOWN_L

IN

R3905

49.9

1/32W
01005

ROOM=B2B_WIDE_RCAM

21

1%
MF

1

C3906

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_WIDE_RCAM

NOSTUFF

1

C3907

220PF

5%
25V

2

COG
01005

ROOM=B2B_WIDE_RCAM

AP_TO_WIDE_CLK_CONN

31

18

18

18

10

OUT

90_LPDP_WIDE_TO_AP_D2_P

OUT

OUT

LPDP_WIDE_BI_AP_AUX

BI

ROOM=B2B_WIDE_RCAM

ROOM=B2B_WIDE_RCAM

ROOM=B2B_WIDE_RCAM

C3941

0.1UF

21

GND_VOID

20%

6.3V

X5R-CERM

01005

C3950

0.1UF

21

GND_VOID

20%

6.3V

X5R-CERM

01005

C3951

0.1UF

21

GND_VOID

20%

6.3V

X5R-CERM

01005

C3960

0.1UF

21

20%

6.3V

X5R-CERM

01005

ROOM=B2B_WIDE_RCAM

SYNC_MASTER=test_mlb

PAGE TITLE

1

C3961

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_WIDE_RCAM

90_LPDP_WIDE_TO_AP_D1_CONN_N90_LPDP_WIDE_TO_AP_D1_N

90_LPDP_WIDE_TO_AP_D2_CONN_P

90_LPDP_WIDE_TO_AP_D2_CONN_N90_LPDP_WIDE_TO_AP_D2_N

LPDP_WIDE_BI_AP_AUX_CONN

31

31

31

31

SYNC_DATE=10/13/2016

B

A

33 32 31

WIDE_AND_TELE_TO_STROBE_DRIVER_EN

OUT

8

1

C3908

220PF

5%
25V

2

COG
01005

ROOM=B2B_WIDE_RCAM

67

CAMERA: B2B Wide (TX)

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

39 OF 85

SHEET

31 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

90_LPDP_TELE_TO_AP_D0_CONN_N

32

90_LPDP_TELE_TO_AP_D0_CONN_P

32

90_LPDP_TELE_TO_AP_D1_CONN_N

32

90_LPDP_TELE_TO_AP_D1_CONN_P

32

90_LPDP_TELE_TO_AP_D2_CONN_N

32

90_LPDP_TELE_TO_AP_D2_CONN_P

32

AP_TO_TELE_CLK_CONN

32

PP_CAM_TELE_ADC

32

PP2V85_CAM_TELE_AVDD_CONN

32

Tele Camera Connector

Rcpt: 516S00313 <-- This one on MLB
Plug: 516S00314

ROOM=B2B_TELE_RCAM

J4000

AA26DK-S026VA1

GND_VOID

GND_VOID

GND_VOID

GND_VOID

GND_VOID

GND_VOID

31

F-ST-SM

2827

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625

PP1V1_CAM_TELE_DVDD_CONN

LPDP_TELE_BI_AP_AUX_CONN

32

32

WIDE_AND_TELE_TO_STROBE_DRIVER_EN

I2C1_ISP_SCL
I2C1_ISP_SDA

ISP_TO_TELE_SHUTDOWN_L

WIDE_TO_TELE_SYNC

32 53

32 53

32 9

32 31

PP3V3_ROMEO_WIDE_TELE_SVDD

PP1V8_CAM_TELE_VDDIO_CONN

32

Power Filtering

32

FL4001

10-OHM-750MA

37 36 34 31 30 29 20 19 17 6

33 32 31

PP_CAM_TELE_ADC

29

1

C3722

37 32 31 29

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=CAM_PMU

53 52 44

37 32 31 29

PP1V8_IO

PP3V3_ROMEO_WIDE_TELE_SVDD

PP_CAM_TELE_ADC

MAKE_BASE=TRUE

PP_CAM_VCM_PVDD_CONN

1

C4090

220PF

5%
25V

2

COG
01005

ROOM=B2B_TELE_RCAM

01005-1

ROOM=B2B_TELE_RCAM

R4006

0.00

1/32W
01005

ROOM=B2B_TELE_RCAM

21

0%
MF

21

1

C4091

220PF

5%
25V

2

COG
01005

1

C4017

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=B2B_TELE_RCAM

ROOM=B2B_TELE_RCAM

1

C4092

220PF

5%
25V

2

COG
01005

ROOM=B2B_TELE_RCAM

1

C4096

220PF

5%
25V

2

COG
01005

1

C4026

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=B2B_TELE_RCAM

1

2

ROOM=B2B_TELE_RCAM

C4095

18UF

20%

6.3V
CER-X5R
0402-0.1MM

ROOM=CAM_PMU

1

C4094

220PF

5%
25V

2

COG
01005

ROOM=B2B_TELE_RCAM

PP2V85_CAM_TELE_AVDD_CONNPP2V85_CAM_TELE_AVDD

PP1V8_CAM_TELE_VDDIO_CONN

32

32

32

32 31

D

C

PP_CAM_VCM_PVDD_CONN

32 31

ISP I2C

53 32

53 32

I2C1_ISP_SCL

IN

I2C1_ISP_SDA

BI

32

3029

1

C4000

56PF

5%
25V

2

NP0-C0G-CERM
01005

1

C4001

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_TELE_RCAM

ROOM=B2B_TELE_RCAM

PP_CAM_VCM_PVDD_CONN

32 31

FL4003

FERR-33OHM-25%-1.5A

LPDP

0201

ROOM=B2B_TELE_CAM

21

1

C4025

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=B2B_TELE_RCAM

1

C4093

220PF

5%
25V

2

COG
01005

PP1V1_CAM_TELE_DVDD_CONNPP1V1_CAM_TELE_DVDD

ROOM=B2B_TELE_RCAM

32 32

C

C4030

0.1UF

18

OUT

90_LPDP_TELE_TO_AP_D0_P

ROOM=B2B_TELE_RCAM

21

20%

6.3V

X5R-CERM

01005

GND_VOID

90_LPDP_TELE_TO_AP_D0_CONN_P

32

C4031

0.1UF

18

OUT

90_LPDP_TELE_TO_AP_D0_N

ROOM=B2B_TELE_RCAM

21

20%

6.3V

X5R-CERM

01005

GND_VOID

90_LPDP_TELE_TO_AP_D0_CONN_N

32

B

IO Filters

17

AP_TO_TELE_CLK AP_TO_TELE_CLK_CONN

IN

R4005

49.9

1/32W
01005

ROOM=B2B_TELE_RCAM

21

1%
MF

1

C4006

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_TELE_RCAM

NOSTUFF

32

18

18

18

18

OUT

OUT

OUT

OUT

90_LPDP_TELE_TO_AP_D1_P

90_LPDP_TELE_TO_AP_D1_N

90_LPDP_TELE_TO_AP_D2_P

90_LPDP_TELE_TO_AP_D2_N

ROOM=B2B_TELE_RCAM

ROOM=B2B_TELE_RCAM

ROOM=B2B_TELE_RCAM

ROOM=B2B_TELE_RCAM

C4040

0.1UF

21

20%

6.3V

X5R-CERM

01005

C4041

0.1UF

21

20%

6.3V

X5R-CERM

01005

C4050

0.1UF

21

20%

6.3V

X5R-CERM

01005

C4051

0.1UF

21

20%

6.3V

X5R-CERM

01005

GND_VOID

GND_VOID

GND_VOID

GND_VOID

90_LPDP_TELE_TO_AP_D1_CONN_P

90_LPDP_TELE_TO_AP_D1_CONN_N

90_LPDP_TELE_TO_AP_D2_CONN_P

90_LPDP_TELE_TO_AP_D2_CONN_N

32

32

32

32

B

A

32 9

33 32 31

32 31

ISP_TO_TELE_SHUTDOWN_L

IN

WIDE_AND_TELE_TO_STROBE_DRIVER_EN

IN

WIDE_TO_TELE_SYNC

IN

1

C4007

220PF

5%
25V

2

COG
01005

ROOM=B2B_TELE_RCAM

1

C4008

220PF

5%
25V

2

COG
01005

ROOM=B2B_TELE_RCAM

1

C4010

220PF

5%
25V

2

COG
01005

ROOM=B2B_TELE_RCAM

Lives Here For synccing purposes

PP1V1_CAM_TELE_DVDD

29

PP2V85_CAM_TELE_AVDD

29

1

C3717

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=CAM_PMU

PP1V1_CAM_TELE_DVDD

MAKE_BASE=TRUE

PP2V85_CAM_TELE_AVDD

MAKE_BASE=TRUE

32

32

10

LPDP_TELE_BI_AP_AUX

OUT

ROOM=B2B_TELE_RCAM

C4060

0.1UF

21

20%

6.3V

X5R-CERM

01005

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

1

C4061

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_TELE_RCAM

LPDP_TELE_BI_AP_AUX_CONN

32

CAMERA: B2B Tele [MT]

SIZE

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

40 OF 85

SHEET

32 OF 60

A

D

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

D

44 43 42 41 36 29 26 24 22 17

59 47 45

PP_VDD_MAIN

C4191

15UF

20%

6.3V
CERM

0402-0.1MM

ROOM=STROBE

D

LED STROBE DRIVERS (NEON)

APN:353S00868
I2C Address (7-bit): 0x67

PP_LED2_BOOST_OUT

1

2

1

C4193

220PF

5%
25V

2

COG
01005

ROOM=B2B_FCAM

33 30

33 32 31

57 38 33

53

53

1

CRITICAL

L4100

1UH-20%-3.6A-0.062OHM

PIWE20160H-SM

ROOM=STROBE

2

LED_DRIVER2_LX
CAMPMU_TO_STROBE_DRIVER_HWEN

IN

WIDE_AND_TELE_TO_STROBE_DRIVER_EN

IN

BB_TO_MANY_GSM_BURST_IND

IN

I2C3_ISP_SDA

BI

I2C3_ISP_SCL

IN

A2

B1
C2
B2

D2
A3
B3

SW
HWEN

INT 300K PD

STROBE

INT 300K PD

TX

INT 300K PD

SDA
SCL

U4100

LM35662

DSBGA

ROOM=STROBE2

CRITICAL

TORCH/TEMP

GND

OUTIN

LED1

LED2

C1

D3

D1

C3

1

C4105

220PF

5%
25V

2

COG
01005

ROOM=STROBE

1

C4106

15UF

2

ROOM=STROBE

STROBE_MODULE_NTC

20%

6.3V
CERM
0402-0.1MM

IN

35 33

1

C4102

220PF

5%
25V

2

COG
01005

1

C4101

220PF

5%
25V

2

COG
01005

ROOM=STROBEROOM=STROBE

PP_STROBE_DRIVER2_COOL_LED

PP_STROBE_DRIVER2_WARM_LED

35

35

C

B

C4196

15UF

20%

6.3V
CERM

0402-0.1MM

ROOM=STROBE

A1

C

APN:353S00558
I2C Address (7-bit): 0x63

PP_LED1_BOOST_OUT

1

2

CRITICAL

2

L4120

1UH-20%-3.6A-0.062OHM

U4120

LM3566

DSBGA

ROOM=STROBE

CRITICAL

TORCH/TEMP

GND

OUTIN

LED1

LED2

C1

D3

D1

C3

STROBE_MODULE_NTC

33 30

33 32 31

57 38 33

53

53

PIWE20160H-SM

ROOM=STROBE2

1

LED_DRIVER1_LX

CAMPMU_TO_STROBE_DRIVER_HWEN

IN

WIDE_AND_TELE_TO_STROBE_DRIVER_EN

IN

BB_TO_MANY_GSM_BURST_IND

IN

I2C3_ISP_SDA

BI

I2C3_ISP_SCL

IN

A2

B1
C2
B2

D2
A3
B3

SW
HWEN

INT 300K PD

STROBE

INT 300K PD

TX

INT 300K PD

SDA
SCL

1

C4125

220PF

5%
25V

2

COG
01005

ROOM=STROBE2

1

C4126

15UF

20%

6.3V

2

CERM
0402-0.1MM

ROOM=STROBE

PP_STROBE_DRIVER1_COOL_LED

PP_STROBE_DRIVER1_WARM_LED

1

C4122

220PF

5%
25V

2

IN

35 33

COG
01005

ROOM=STROBE2

1

C4121

220PF

5%
25V

2

COG
01005

ROOM=STROBE2

35

35

B

A1

A

8

67

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=03/22/2017

A

CAMERA: Strobe Drivers

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

41 OF 85

SHEET

33 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

LONG ISLAND POWER

37 36 32 31 30 29 20 19 17 6

53 52 44

29

29

PP1V8_IO

PP1V1_FCAM_DVDD

PP2V85_FCAM_AVDD

FL4200

10-OHM-750MA

21

01005-1

ROOM=B2B_FCAM

FL4202

10-OHM-750MA

21

01005-1

ROOM=B2B_FCAM

FL4204

10-OHM-750MA

21

01005-1

ROOM=B2B_FCAM

1

C4200

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=B2B_FCAM

1

C4202

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=B2B_FCAM

1

C4204

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=B2B_FCAM

1

C4201

220PF

5%
25V

2

COG
01005

ROOM=B2B_FCAM

1

C4203

220PF

5%
25V

2

COG
01005

ROOM=B2B_FCAM

1

C4205

220PF

5%
25V

2

COG
01005

ROOM=B2B_FCAM

PP1V8_FCAM_VDDIO_CONN

PP1V1_FCAM_DVDD_CONN

PP2V85_FCAM_AVDD_CONN

1

C3705

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=CAM_PMU

34

34

34

PP1V1_FCAM_DVDD_CONN

34

I2C2_ISP_SDA

34 53

PP1V8_FCAM_VDDIO_CONN

34

FCAM_TO_JULIET_SYNC

37 34

PP2V85_FCAM_AVDD_CONN

34

ISP_TO_FCAM_SHUTDOWN_L

34 9

AP_TO_FCAM_CLK_CONN

34

LPDP_FCAM_BI_AP_AUX_CONN

34

FCAM Connector

Rcpt: 516S00244
Plug: 516S00245

BB35K-RA18-3A

23

24

J4200

F-ST-SM

ROOM=B2B_FCAM

<-- This one on MLB

2019

21
43
65
87
109
1211
1413
1615
1817

2221

I2C2_ISP_SCL

90_LPDP_FCAM_TO_AP_D0_CONN_N
90_LPDP_FCAM_TO_AP_D0_CONN_P

90_LPDP_FCAM_TO_AP_D1_CONN_N
90_LPDP_FCAM_TO_AP_D1_CONN_P

34 53

34

34

34

34

D

C

B

FCAM I/O

17

IN

34 9

ISP_TO_FCAM_SHUTDOWN_L

IN

R4210

49.9

1%

1/32W

MF

01005

ROOM=B2B_FCAM

C

LPDP FILTERS

C4230

0.1UF

18

90_LPDP_FCAM_TO_AP_D0_P

OUT

ROOM=B2B_FCAM

21

20%

6.3V

X5R-CERM

01005

GND_VOID=TRUE

C4231

0.1UF

18

21

1

C4210

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_FCAM

NOSTUFF

1

C4211

220PF

5%
25V

2

COG
01005

ROOM=B2B_FCAM

AP_TO_FCAM_CLK_CONNAP_TO_FCAM_CLK

34

18

18

90_LPDP_FCAM_TO_AP_D0_N

OUT

OUT

OUT

90_LPDP_FCAM_TO_AP_D1_N

ROOM=B2B_FCAM

C4232

ROOM=B2B_FCAM

C4233

ROOM=B2B_FCAM

21

20%

6.3V

X5R-CERM

01005

0.1UF

21

20%

6.3V

X5R-CERM

01005

0.1UF

21

20%

6.3V

X5R-CERM

01005

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

90_LPDP_FCAM_TO_AP_D0_CONN_P

90_LPDP_FCAM_TO_AP_D0_CONN_N

90_LPDP_FCAM_TO_AP_D1_CONN_P90_LPDP_FCAM_TO_AP_D1_P

90_LPDP_FCAM_TO_AP_D1_CONN_N

34

34

34

B

34

A

37 34

FCAM_TO_JULIET_SYNC

OUT

ISP I2C2

53 34

53 34

I2C2_ISP_SCL

IN

I2C2_ISP_SDA

BI

1

C4212

2

NOTE: SAME I2C as FCAM

1

C4220

2

1

C4221

2

100PF

5%
16V
NP0-C0G
01005

ROOM=B2B_FCAM

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=B2B_FCAM

NOSTUFF

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=B2B_FCAM

NOSTUFF

10

LPDP_FCAM_BI_AP_AUX

BI

ROOM=B2B_FCAM

C4234

0.1UF

21

20%

6.3V

X5R-CERM

01005

1

C4235

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_FCAM

LPDP_FCAM_BI_AP_AUX_CONN

SYNC_MASTER=test_mlb

PAGE TITLE

CAMERA: B2B Fcam

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

34

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

42 OF 85

SHEET

34 OF 60

SYNC_DATE=10/13/2016

SIZE

D

A

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

Strobe Connector

D

39

39

PENROSE

OUT

PENROSE_VIS_TO_CODEC_AIN7_P

OUT

FL4301

FERR-150OHM-25%-200MA

21

01005

ROOM=B2B_STROBE

1

2

FL4331

FERR-150OHM-25%-200MA

21

01005

ROOM=B2B_STROBE

1

2

C4302

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=B2B_STROBE

C4332

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=B2B_STROBE

PENROSE_IR_TO_CODEC_AIN5_CONN_P

PENROSE_VIS_TO_CODEC_AIN7_CONN_P

35

35

PP_STROBE_DRIVER2_COOL_LED

35 33

PP_STROBE_DRIVER2_WARM_LEDPENROSE_IR_TO_CODEC_AIN5_P

35 33

I2C1_AP_SDA

35 52

I2C1_AP_SCL

35 52

PP_CODEC_TO_REARMIC2_BIAS_CONN

35

REARMIC2_TO_CODEC_BIAS_FILT_RET

40

REARMIC2_TO_CODEC_AIN2_CONN_P

35

REARMIC2_TO_CODEC_AIN2_CONN_N

35

GND

MAKE_BASE=TRUE

Rcpt: 516S00381
Plug: 516S00382

AA36D-S012VA1

<-- This one on MLB

ROOM=B2B_STROBE

J4300

F-ST-SM

1817

D

1413
21

43
65
87
109
1211

1615

2019

XW4300

SHORT-10L-0.05MM-SM

21

PENROSE_IR_TO_CODEC_AIN5_CONN_P

PENROSE_VIS_TO_CODEC_AIN7_CONN_P

PP_STROBE_DRIVER1_COOL_LED

BUTTON_POWER_KEY_CONN_L

STROBE_MODULE_NTC_CONN

PP3V0_PENROSE_CONN

35

35

35

35

35

PP_STROBE_DRIVER1_WARM_LED

PENROSE_IR_TO_CODEC_AIN5_CONN_N

35 33

35 33

39

C

FL4303

FERR-150OHM-25%-200MA

21

01005

ROOM=B2B_STROBE

1

C4303

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=B2B_STROBE

1

C4304

220PF

5%
25V

2

COG
01005

ROOM=B2B_STROBE

XW4301

SHORT-10L-0.05MM-SM

21

PENROSE_VIS_TO_CODEC_AIN7_CONN_N

39

C

PP3V0_PENROSE_CONNPP3V0_PENROSE

35 22

B

A

MIC2 (ANC REF)

PP_CODEC_TO_REARMIC2_BIAS PP_CODEC_TO_REARMIC2_BIAS_CONN

40 35

39

39

REARMIC2_TO_CODEC_AIN2_P REARMIC2_TO_CODEC_AIN2_CONN_P

OUT

REARMIC2_TO_CODEC_AIN2_N REARMIC2_TO_CODEC_AIN2_CONN_N

OUT

Power Key Button

23

BUTTON_POWER_KEY_L BUTTON_POWER_KEY_CONN_L

OUT

FL4305

FERR-150OHM-25%-200MA

2 1

01005

ROOM=B2B_STROBE

FL4306

FERR-150OHM-25%-200MA

2 1

01005

ROOM=B2B_STROBE

FL4307

FERR-150OHM-25%-200MA

2 1

01005

ROOM=B2B_STROBE

R4310

100

21

C4310

27PF

5%

6.3V

NP0-C0G

0201

ROOM=B2B_STROBE

1

2

5%

1/32W

MF

01005

ROOM=B2B_STROBE

1

C4305

220PF

5%
25V

2

COG
01005

1

C4306

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_STROBE

1

C4307

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_STROBE

1

DZ4310

5.5V-6.2PF

0201

2

ROOM=B2B_STROBE

ROOM=B2B_STROBE

35

35

35

Strobe Filtering

PP_STROBE_DRIVER1_WARM_LED

C4320

220PF

5%
25V
COG

01005

ROOM=B2B_STROBE

PP_STROBE_DRIVER1_COOL_LED

C4322

220PF

5%
25V
COG

01005

ROOM=B2B_STROBE

PP_STROBE_DRIVER2_WARM_LED

C4324

220PF

5%
25V
COG

01005

ROOM=B2B_STROBE

PP_STROBE_DRIVER2_COOL_LED

C4326

220PF

5%
25V
COG

01005

ROOM=B2B_STROBE

33

OUT

R4330

27K

0.5%

1/32W

MF

01005

ROOM=B2B_STROBE

1

2

1

2

1

2

1

2

FL4330

FERR-150OHM-25%-200MA

21

1

2

01005

ROOM=B2B_STROBE

1

2

STROBE_MODULE_NTC_CONNSTROBE_MODULE_NTC

C4330

220PF

5%
25V
COG
01005

ROOM=B2B_STROBE

35 33

B

35 33

35 33

35 33

52 35

52 35

I2C1_AP_SCL

IN

I2C1_AP_SDA

BI

PAGE TITLE

1

C4308

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_STROBE

1

C4309

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_STROBE

SYNC_DATE=03/22/2017SYNC_MASTER=test_mlb

A

CAMERA: B2B Strobe + Hold Button

35

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

43 OF 85

SHEET

35 OF 60

SIZE

D

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

D

Rigel Driver

1

C4494

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=RIGEL

1

C4493

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=RIGEL

1

C4492

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=RIGEL

C4497

15UF

20%

6.3V
CERM

0402-0.1MM

ROOM=RIGEL

PP_VDD_MAIN

59 47 45

1

2

44 43 42 41 33 29 26 24 22 17

D

C

Test Mode Debugging

Rigel ALTs

PART NUMBER

152S00640152S00720

ALT_PARTS

L4400,L4401

R4491

10K

1/32W

ROOM=RIGEL

01005

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

RIGEL Inductors

5%
MF

1

C4491

4UF

20%

6.3V

2

CERM-X5R

RIGEL_TESTMODE

1

2

36

0201

ROOM=RIGEL

1

C4490

1.0UF

20%

10V

2

X5R-CERM
0201-1

ROOM=RIGEL

Terminate @ Cap via on VDD_MAIN plane.

OMIT

XW4400

PP_RIGEL_VINCORE

SHORT-20L-0.05MM-SM

21

ROOM=RIGEL

PP1V8_IO

53 52

44 37 34 32 31 30 29 20 19 17 6

C

PP_VANA

TABLE_ALT_HEAD

TABLE_ALT_ITEM

E9

F10

F9

A10

A8

A9

A1

A2

A3

E2

F1

F2

F5

H5

H4

C5

H8

G2

G9

C4498

2.2UF

20%

6.3V

X5R-CERM

0201

ROOM=RIGEL

PP_VDD_BOOST

1

C4496

1.0UF

2

X5R-CERM

0201-1

ROOM=RIGEL

20%

10V

1

C4495

1.0UF

2

X5R-CERM

0201-1

ROOM=RIGEL

20%

10V

1

2

59 47 46 40 29 24 22 17

B

C4401

220PF

5%

25V

COG

01005

ROOM=RIGEL

C4412

220PF

5%

25V

COG

01005

ROOM=RIGEL

VCC4

VANA

PP_RIGEL_BUCK_BOOST_A

H10

J10

K10
D10

D9

E10
B10

B9
E8

D8
D3

E3
B1

B2
D1

D2
E1

J1
J2
J3

H9
K9

J9

H1
H2
H3

K1
K2
K3

G1

G10

VBBOUTA
VBBOUTA
VBBOUTA

VLXA
VLXA
VLXA

VCXA
VCXA

BOOSTSDA
BULKSDA

BULKSDB
BOOSTSDB

VCXB
VCXB

VLXB
VLXB
VLXB

VBBOUTB
VBBOUTB
VBBOUTB

IOUT0
IOUT0
IOUT0

IOUT1
IOUT1
IOUT1

IOUT2
IOUT2
IOUT2

IOUT3
IOUT4

20%
25V
X5R

0402

1

2

0.47UH-20%-4A-0.048OHM

L4400

2 1

PIWA20120H-SM

C4420

0.01UF

10%

6.3V

X5R

01005

ROOM=RIGEL

RIGEL_VLXA

20%
25V
X5R

0402

1

2

RIGEL_VCXA

RIGEL_BOOSTSDA

C4405

4.7UF

1

ROOM=RIGEL

2

RIGEL_BULKSDA

1

C4400

4.7UF

2

ROOM=RIGEL

RIGEL_BULKSDB

RIGEL_BOOSTSDB

RIGEL_VCXB

RIGEL_VLXB

10%

6.3V

X5R

1

20%
25V
X5R

0402

1

2

2

C4410

4.7UF

ROOM=RIGEL

PP_RIGEL_BUCK_BOOST_B

PP_ROMEO_DENSE_ANODE

37 5

PP_ROMEO_SPARSE_ANODE

37

PP_ROSALINE_ANODE

38

PP_ROMEO_A_ANODE

37

PP_ROMEO_B_ANODE

37

C4421

0.01UF

01005

L4401

0.47UH-20%-4A-0.048OHM

2 1

PIWA20120H-SM

20%
25V
X5R

0402

1

2

1

C4411

4.7UF

2

ROOM=RIGEL

ROOM=RIGEL

VINSDA

VINSDA

VINSDA

VINSUA

VINSUA

VINSUA

VINSUB

VINSUB

VINSUB

VINSDB

VINSDB

VINSDB

U4400

STB601A0

WLCSP

ROOM=RIGEL

CRITICAL

VINCORE

VINVCORE2

VDDIO

VCC3

VIN_LVT

VK
VK
VK
VK
VK

NTC

OTPHV

TAMP

ENA
XEF1
XEF0

THROT

STROBE

TESTMODE

TESTMODE2

TEST

MCLK

INT

SCL

SDA

PD0
PD1

LSCP

K4
K5
K6
K7
K8

G4
C4
D4
B3

C8
C7
B8
A4

B7
B5
B6
A7
B4
A5

A6
G5

G6
H7

PP_ROMEO_CATHODE

37 5

ROMEO_TO_RIGEL_VCSEL_NTC

CAMPMU_TO_RIGEL_ENABLE

YOGI_TO_RIGEL_STATUS

MAMA_BEAR_BI_RIGEL_STATUS

JULIET_PMU_TO_RIGEL_STROBE

RIGEL_TESTMODE

36

AP_TO_RIGEL_CLK

RIGEL_TO_ISP_INT

OUT

I2C3_ISP_SCL

I2C3_RIGEL_SDA_R

RIGEL_LSCP

37

IN

30 5

IN

37

17

53

38 30

37 30

23 9 5

R4400

2 1

33.2

1%

1/32W

MF

01005

ROOM=RIGEL

1

C4422

0.01UF

10%

6.3V

2

X5R
01005

ROOM=RIGEL

I2C3_ISP_SDA

B

53

BI

BI
BI

IN

IN

IN

A

8

67

PGNDA

PGNDA

C9

C10

PGNDB

PGNDB

C2

C1

GNDS

D5

C3

GNDS

GNDS

D6

GNDS

F3

D7

GNDS

GNDS

E5

GNDS

F8

E6

GNDS

GNDS

G7

GNDD

C6

GNDCORE2

GNDCORE

F6

H6

G3

GNDCORE3

PGNDK

GNDCORE4

J5

J4

G8

PGNDK

PGNDK

J7

J6

PGNDK

PGNDK

J8

A

PAGE TITLE

PEARL: Power

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

44 OF 85

SHEET

36 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

Romeo Connector

D

Romeo I/O

56 37

ROMEO_TO_AOP_B2B_DETECT

OUT

Romeo Power Filtering

PP_ROMEO_B_ANODE

37 36

PP_ROMEO_A_ANODE

37 36

37 36 5

37 36 5

PP_ROMEO_DENSE_ANODE
PP_ROMEO_SPARSE_ANODE

37 36

PP_ROMEO_CATHODE
PP3V3_ROMEO_WIDE_TELE_SVDD

1

C4554

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

2

C4592

220PF

5%
25V
COG
01005

ROOM=B2B_PEARL

1

C4593

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4594

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4595

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4596

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4597

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

ISP I2C3

Rcpt: 516S00267

<-- This one on MLB

Plug: 516S00268

J4500

AA36D-S010VA1

37 36 5

PP_ROMEO_DENSE_ANODE

F-ST-SM

1615

PP_ROMEO_DENSE_ANODE

37 36 5

D

37 32 31 29

37 36 5

37 36 30

37 36 5

PP_ROMEO_CATHODE

PP_ROMEO_B_ANODE

37 36

PP_ROMEO_A_ANODE

37 36

I2C3_ISP_SDA

37 53

MAMA_BEAR_BI_RIGEL_STATUS

PP_ROMEO_CATHODE

PP_ROMEO_SPARSE_ANODE

37 36

PWR

SIGNAL

PWR

ROOM=B2B_PEARL

1211

21
43
65
87
109

1413

1817

ROMEO_TO_AOP_B2B_DETECT

ROMEO_TO_RIGEL_VCSEL_NTC

PP3V3_ROMEO_WIDE_TELE_SVDD

PP_ROMEO_SPARSE_ANODE

PP_ROMEO_CATHODE

I2C3_ISP_SCL

37 53

PP_ROMEO_CATHODE

37 36 5

56 37

37 36

37 32 31 29

37 36 5

37 36

C

37 36

36 30

37

ROMEO_TO_RIGEL_VCSEL_NTC

OUT

MAMA_BEAR_BI_RIGEL_STATUS

IN

1

C4555

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4556

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

53 37

53 37

I2C3_ISP_SCL

IN

I2C3_ISP_SDA

BI

1

C4552

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_PEARL

1

C4553

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_PEARL

37 17

PP1V1_CAM_JULIET_DVDD

90_MIPI_JULIET_TO_AP_DATA0_P

9

90_MIPI_JULIET_TO_AP_DATA0_N

9

90_MIPI_JULIET_TO_AP_CLK_P

9

90_MIPI_JULIET_TO_AP_CLK_N

9

90_MIPI_JULIET_TO_AP_DATA1_P

9

90_MIPI_JULIET_TO_AP_DATA1_N

9

Juliet Connector

Rcpt: 516S00244
Plug: 516S00245

BB35K-RA18-3A

23

J4530

F-ST-SM

<-- This one on MLB

2019

21
43
65
87
109
1211
1413
1615
1817

JULIET_PMU_TO_RIGEL_STROBE

FCAM_TO_JULIET_SYNC

PP2V85_JULIET_AVDD_CONN

PP1V8_JULIET_VDDIO_CONN

ISP_TO_JULIET_SHUTDOWN_L

I2C2_ISP_SDA
I2C2_ISP_SCL

37

37

37 9

37 53

37 53

AP_TO_JULIET_CLK

C

37 36

37 34

37 17

B

A

Juliet Power and I/O

PP1V1_CAM_JULIET_DVDD

37 17

1

C4570

0.1UF

20%

6.3V

2

X5R-CERM
01005

FL4572

ROOM=B2B_PEARL

10-OHM-750MA

PP2V85_CAM_JULIET_AVDD

29 37

01005-1

ROOM=B2B_PEARL

21

FL4574

PP2V85_JULIET_AVDD_CONN

1

C4572

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=B2B_PEARL

10-OHM-750MA

36 34 32 31 30 29 20 19 17 6 37

53 52 44

PP1V8_IO PP1V8_JULIET_VDDIO_CONN

01005-1

ROOM=B2B_PEARL

21

1

C4574

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=B2B_PEARL

1

C4571

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4573

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4575

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

37 9

37 17

37 36

37 34

ISP_TO_JULIET_SHUTDOWN_L

IN

AP_TO_JULIET_CLK

IN

JULIET_PMU_TO_RIGEL_STROBE

OUT

FCAM_TO_JULIET_SYNC

IN

1

C4560

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

C4562

56PF

5%

NP0-C0G-CERM

ROOM=B2B_PEARL

1

2

25V

01005

C4563

220PF

5%
25V
COG
01005

ROOM=B2B_PEARL

1

C4564

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

2221

24

ROOM=B2B_PEARL

B

NOTE: SAME I2C as FCAM

I2C2_ISP_SDA

37 53

5%

25V

5%

25V

1

2

1

2

A

C4580

56PF

NP0-C0G-CERM

ROOM=B2B_PEARL

1

I2C2_ISP_SCL

2

37 53

01005

C4581

56PF

NP0-C0G-CERM

ROOM=B2B_PEARL

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

01005

PEARL: B2B Romeo + Juliet

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

45 OF 85

SHEET

37 OF 60

8

67

35 4

2

1

D

VIETMOBILE.VN

AOP I2C

54 38

54 38

BI

I2C0_AOP_SCL

IN

I2C0_AOP_SDA

HALL I/Os

56 38

HALL_FLAP_TO_AOP_IRQ_L

OUT

1

C4600

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_PEARL

1

C4601

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_PEARL

1

C4680

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

678

3 245

1

Rosaline + Sensor Connector

<-- This one on MLBRcpt: 516S00325

Plug: 516S00326

J4600

AA26DK-S028VA1

F-ST-SM

33

3029

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827

3231

34

FRONTMIC3_TO_CODEC_AIN3_CONN_P
FRONTMIC3_TO_CODEC_AIN3_CONN_N

I2C0_AOP_SDA
PROX_BI_AOP_INT_L
PP_ROSALINE_ANODE

ALS_TO_AOP_INT_L

BB_TO_MANY_GSM_BURST_IND_CONN

HALL_FLAP_TO_AOP_IRQ_L

COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN

CODEC_AOUT_TO_HAC_POS_CONN
CODEC_AOUT_TO_HAC_NEG_CONN

38 38

38

38 54

56 38

38 36

56 38

38

56 38

38

38

38

D

Yogi Signals

FRONTMIC3_TO_CODEC_BIAS_FILT_RET

40

PP_CODEC_TO_FRONTMIC3_BIAS_CONN
PP3V0_YOGI_PROX_ALS_CONN

38

I2C0_AOP_SCL

38 54

38 36 30

YOGI_TO_RIGEL_STATUS

PP1V8_S2_HALL_CONN

38

COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN

38

SPKRAMP_TOP_TO_COIL_OUT_NEG

42 38

SPKRAMP_TOP_TO_COIL_OUT_POS

42 38

ROOM=B2B_PEARL

OMIT

XW4600

SHORT-20L-0.05MM-SM

21

PROX & HALL POWER

R4612

PP1V8_S2 PP1V8_S2_HALL_CONN

C

40 25 20 17 38

54 50 49 48 42 41

49 48 22

59

58

0.00

0%

1/32W

MF

01005

ROOM=B2B_PEARL

R4611

0.00

0%

1/32W

MF

01005

ROOM=B2B_PEARL

21

1

C4602

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

21

1

C4613

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=B2B_PEARL

PP3V0_YOGI_PROX_ALS_CONNPP3V0_S2

1

C4614

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

38

PP_ROSALINE_ANODE

1

C4660

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

38 36

ROOM=B2B_PEARL

C

SPEAKER2

B

A

56 38

56 38 56 38

57 33

38

36 30

30
36

PROX/ALS/YOGI I/O

PROX_BI_AOP_INT_L

BI

ALS_TO_AOP_INT_L

OUT

BB_TO_MANY_GSM_BURST_IND

IN

YOGI_TO_RIGEL_STATUS YOGI_TO_RIGEL_STATUS

BI

38

R4619

0.00

1/32W
01005

ROOM=B2B_PEARL

21

0%
MF

1

C4617

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4618

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4619

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4650

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

ALS_TO_AOP_INT_L

BB_TO_MANY_GSM_BURST_IND_CONN

38

MIC3

PP_CODEC_TO_FRONTMIC3_BIAS

40

39

OUT

39

OUT

CODEC_AOUT_TO_HAC_NEG

39

CODEC_AOUT_TO_HAC_POS

39

FRONTMIC3_TO_CODEC_AIN3_N

FRONTMIC3_TO_CODEC_AIN3_P

FL4640

FERR-150OHM-25%-200MA

21

01005

ROOM=B2B_PEARL

FL4641

FERR-150OHM-25%-200MA

21

01005

ROOM=B2B_PEARL

FL4642

FERR-150OHM-25%-200MA

2 1

01005

ROOM=B2B_PEARL

FL4690

FERR-150OHM-25%-200MA

2 1

01005

ROOM=B2B_PEARL

FL4691

FERR-150OHM-25%-200MA

2 1

01005

ROOM=B2B_PEARL

1

DZ4640

6.8V-100PF

01005

ROOM=B2B_PEARL

2

1

DZ4641

6.8V-100PF

01005

ROOM=B2B_PEARL

2

1

DZ4642

6.8V-100PF

01005

ROOM=B2B_PEARL

2

PP_CODEC_TO_FRONTMIC3_BIAS_CONN

FRONTMIC3_TO_CODEC_AIN3_CONN_N

FRONTMIC3_TO_CODEC_AIN3_CONN_P

CODEC_AOUT_TO_HAC_NEG_CONN

1

DZ4690

6.8V-100PF

01005

ROOM=B2B_PEARL

2

CODEC_AOUT_TO_HAC_POS_CONN

1

DZ4691

6.8V-100PF

01005

ROOM=B2B_PEARL

2

38

38

38

38

38

42 38

42 38

42

OUT

42

OUT

SPKRAMP_TOP_TO_COIL_OUT_POS

IN

SPKRAMP_TOP_TO_COIL_OUT_NEG

IN

C4635

220PF

5%
25V
COG

ROOM=B2B_PEARL

01005

C4634

220PF

5%
25V
COG

ROOM=B2B_PEARL

01005

1

2

1

2

R4633

100

5%

1/32W

MF

01005

ROOM=B2B_PEARL

R4634

100

5%

1/32W

MF

01005

ROOM=B2B_PEARL

21

21

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONNCOIL_TO_SPKRAMP_TOP_VSENSE_POS

COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONNCOIL_TO_SPKRAMP_TOP_VSENSE_NEG

1

C4630

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4632

220PF

5%
25V

2

COG
01005

ROOM=B2B_PEARL

1

C4631

1000PF

10%
25V

2

X5R
0201

ROOM=B2B_PEARL

1

C4633

1000PF

10%
25V

2

X5R
0201

ROOM=B2B_PEARL

38

38

PEARL: B2B Rosaline + Sensor

DRAWING NUMBER

051-02545

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

7.0.0

BRANCH

PAGE

46 OF 85

SHEET

38 OF 60

B

A

SIZE

D

8

67

35 4

2

1

678

VIETMOBILE.VN

CALLAN AUDIO CODEC (ANALOG INPUTS & OUTPUTS)

3 245

1

D

50

50

35

35

38

38

LOWERMIC1_TO_CODEC_AIN1_P

IN

LOWERMIC1_TO_CODEC_AIN1_N

IN

REARMIC2_TO_CODEC_AIN2_P

IN

REARMIC2_TO_CODEC_AIN2_N

IN

FRONTMIC3_TO_CODEC_AIN3_P

IN

FRONTMIC3_TO_CODEC_AIN3_N

IN

K3

L3

K4

L4

K6

L6

AIN1+
AIN1-

AIN2+
AIN2-

AIN3+
AIN3-

U4700

CS42L75

WLCSP

SYM 1 OF 3

CRITICAL

ROOM=CODEC

AOUT+

AOUT-

K8
L8

CODEC_AOUT_TO_HAC_POS
CODEC_AOUT_TO_HAC_NEG

38

38

D

C

B

35

35

PENROSE_IR_TO_CODEC_AIN5_CONN_N

IN

PENROSE_VIS_TO_CODEC_AIN7_CONN_N

IN

C4300

0.22UF

2 1

10%

6.3V

CER-X5R

01005

ROOM=B2B_STROBE

^
|

|

Place Near B2B

|
|
V

C4301

0.22UF

2 1

10%

6.3V

CER-X5R

01005

ROOM=B2B_STROBE

42

42

46

50

50

35

LOWERMIC4_TO_CODEC_AIN4_P

IN

LOWERMIC4_TO_CODEC_AIN4_N

IN

PENROSE_IR_TO_CODEC_AIN5_P

IN

PENROSE_IR_TO_CODEC_AIN5_N

46

IN

46

IN

35

IN

46

IN

46

IN

PDM_CODEC_TO_SPKAMP_TOP_CLK

OUT

PDM_CODEC_TO_SPKAMP_TOP_DATA

OUT

CODEC_TO_HALOGEN_AMP_PDM_OUT

OUT

HALOGEN_TIA_IOUT
TIA_NEG_C

PENROSE_VIS_TO_CODEC_AIN7_P
PENROSE_VIS_TO_CODEC_AIN7_N

HALOGEN_VSTIM
STIM_NEG_C

NC
NC

NC
NC

NC
NC

NC
NC

NC

NC
NC

K5

AIN4+

L5

AIN4-

G3

AIN5+

G2

AIN5-

F3

AIN6+

G4

AIN6-

F4

AIN7+

E3

AIN7-

C2

AIN8+

D3

AIN8-

B8

DMIC1_CLK

D8

DMIC1_DATA

E11

DMIC2_CLK

E10

DMIC2_DATA

D10

DMIC3_CLK

D9

DMIC3_DATA

E9

DMIC4_CLK

F8

DMIC4_DATA

B11

PDMOUT1_CLK

B10

PDMOUT1_DATA

A10

PDMOUT2_CLK

B9

PDMOUT2_DATA

F10

PDMOUT3_CLK

F9

PDMOUT3_DATA

DP
DN

MBUS_REF

E1
F1

G1

90_MIKEYBUS_CODEC_DATA_P
90_MIKEYBUS_CODEC_DATA_N

MIKEYBUS_REFERENCE

1

R4710

100

5%
1/32W
MF
01005

2

ROOM=CODEC

C

C4700

100PF

21

5%

16V

NP0-C0G

R4700

20.0

1/32W
01005

ROOM=CODEC

21

5%
MF

R4701

50

IN

20.0

5%

1/32W

MF

01005

ROOM=CODEC

21

01005

ROOM=CODEC

C4701

100PF

21

5%

16V

NP0-C0G

01005

ROOM=CODEC

90_MIKEYBUS_DATA_P

90_MIKEYBUS_DATA_N

49

BI

49

BI

B

A

8

67

A

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

AUDIO: CODEC (1/2)

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

47 OF 85

SHEET

39 OF 60

1

SIZE

D

678

VIETMOBILE.VN

CALLAN AUDIO CODEC (POWER & I/O)

3 245

1

D

C

22

40

59 47 46 36 29 24 22 17

50 49 48 42 41 40 38 25 20 17

59 54

PP1V8_AUDIO_VA_S2

1

2

CODEC_AGND

PP_VDD_BOOST

PP1V8_S2

1

2

C4809

2.2UF

20%

6.3V
X5R-CERM
0201

ROOM=CODEC

C4811

10UF

20%

6.3V
CERM-X5R
0402-0.1MM

ROOM=CODEC

1

C4812

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CODEC

1

C4813

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CODEC

1

C4814

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CODEC

1

C4815

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CODEC

1

C4805

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CODEC

PP1V2_CODEC_S2

50 49 48 42 41 40 38 25 20 17

56

55

11

11

11

AOP_TO_CODEC_RESET_L

IN

CODEC_TO_PMU_WAKE_L

OUT

CODEC_TO_AP_INT_L

OUT

SPI_AP_TO_CODEC_CS_L

IN

SPI_AP_TO_CODEC_SCLK

IN

59 54

PP1V8_S2

R4800

100K

5%

1/32W

MF

01005

ROOM=CODEC

D

1

2

U4700

J4

H3
D4

C7
A7

RESET*

WAKE*
INT*

CS*
CCLK

CS42L75

WLCSP

SYM 3 OF 3

ROOM=CODEC

CRITICAL

JTAG_TMS

JTAG_TCK

JTAG_TDI

JTAG_TDO

E7
D7
E8
F7

NC
NC
NC
NC

C

B

50

35

38

50

LOWERMIC1_TO_CODEC_BIAS_FILT_RET

IN

REARMIC2_TO_CODEC_BIAS_FILT_RET

IN

FRONTMIC3_TO_CODEC_BIAS_FILT_RET

IN

LOWERMIC4_TO_CODEC_BIAS_FILT_RET

IN

C4803

4.7UF

21

20%

6.3V
X5R-CERM1
402-1.0MM

ROOM=CODEC

C4804

4.7UF

21

20%

6.3V
X5R-CERM1
402-1.0MM

ROOM=CODEC

C4801

4.7UF

21

20%

6.3V
X5R-CERM1
402-1.0MM

ROOM=CODEC

C4802

4.7UF

21

20%

6.3V
X5R-CERM1
402-1.0MM

ROOM=CODEC

Additional input cap remvoed per rdar 35537162
Future designs should re-add

PP_CODEC_TO_LOWERMIC1_BIAS

50

LOWERMIC1_BIAS_FILT_IN

PP_CODEC_TO_REARMIC2_BIAS

35

REARMIC2_BIAS_FILT_IN

PP_CODEC_TO_FRONTMIC3_BIAS

38

FRONTMIC3_BIAS_FILT_IN

PP_CODEC_TO_LOWERMIC4_BIAS

50

LOWERMIC4_BIAS_FILT_IN

1

C4823

1.0UF

20%
10V

2

X5R-CERM
0201-1

ROOM=CODEC

1

C4821

1.0UF

20%
10V

2

X5R-CERM
0201-1

ROOM=CODEC

1

2

C4824

1.0UF

20%
10V
X5R-CERM
0201-1

ROOM=CODEC

NC
NC

K11

MIC1_BIAS

K10

MIC1_BIAS_FILT

J11

MIC2_BIAS

J10

MIC2_BIAS_FILT

K9

MIC3_BIAS

J9

MIC3_BIAS_FILT

H9

MIC4_BIAS

H8

MIC4_BIAS_FILT

H11

MIC5_BIAS

H10

MIC5_BIAS_FILT

A2A9C1

VD

VL_SW

G11

B1

VL

VD_FILT

VD_FILT

CRITICAL

ROOM=CODEC

U4700

CS42L75

WLCSP

SYM 2 OF 3

L9

VP

J1

VA

J2

VA

F2

K2

VA

LP_FILT+

LP_FILT-

VP_MBUS

D1
D2

FILT-

K1

L2

FILT+

43 41

50 43 13

CODEC_TO_SPKRAMP_BOT_ARC_MCLK

OUT

I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT

IN

CODEC_LP_FILTP
CODEC_LP_FILTN

CODEC_FILTP

1

C4820

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=CODEC

1

C4808

10UF

20%

6.3V

2

CERM-X5R
0402-0.1MM

ROOM=CODEC

R4830

33.2

1%

1/32W

MF

01005

ROOM=CODEC

R4832

49.9

1%

1/32W

MF

01005

ROOM=CODEC

11 5

11 5

21

50 43 42 41 13 5

50 43 42 41 13

43 42 41 13

21

11

13

13

13

13

13

11

11

11

11

13

13

56

SPI_AP_TO_CODEC_MOSI

IN

SPI_CODEC_TO_AP_MISO

OUT

I2S_AP_TO_CODEC_MCLK1

IN

I2S_AOP_TO_CODEC_MCLK2

IN

CODEC_TO_SPKRAMP_BOT_ARC_MCLK_R

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK

OUT

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK

OUT

I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_R
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN

OUT

I2S_AOP_TO_CODEC_ASP2_BCLK

IN

I2S_AOP_TO_CODEC_ASP2_LRCLK

IN

I2S_AOP_TO_CODEC_ASP2_DOUT

IN

I2S_CODEC_ASP2_TO_AOP_DIN

OUT

I2S_AP_TO_CODEC_ASP3_BCLK

IN

I2S_AP_TO_CODEC_ASP3_LRCLK

IN

I2S_AP_TO_CODEC_ASP3_DOUT

IN

I2S_CODEC_ASP3_TO_AP_DIN

OUT

AOP_TO_CODEC_GPIO1

IN

CODEC_TO_AOP_GPIO2

OUT

AOP_TO_CODEC_CLP_EN

IN

NC
NC

NC
NC

C8

MOSI

B7

MISO

A4

MCLK1_IN

B4

MCLK2_IN

A5

MCLK_OUT

A6

ASP1_SCLK

C6

ASP1_LRCK/FSYNC

B5

ASP1_SDIN

B6

ASP1_SDOUT

C4

ASP2_SCLK

D5

ASP2_LRCK/FSYNC

D6

ASP2_SDIN

C5

ASP2_SDOUT

C11

ASP3_SCLK

C9

ASP3_LRCK/FSYNC

C10

ASP3_SDIN

D11

ASP3_SDOUT
DIGLDO_PULLDN

H5

DIGLDO_EN

A3

SW1_CLK

C3

SW1_SD

B3

SW2_CLK

B2

SW2_SD

E6

GPIO1

E5

GPIO2

F6

CLP_EN

TSTI
TSTI
TSTI

GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA

G10
J3
J5

F5H4
G5
G6
G7
H1
H2
H6
H7
J6
J7
J8
E4

B

A

1

C4822

1.0UF

20%
10V

2

X5R-CERM
0201-1

ROOM=CODEC

1

C4825

1.0UF

20%
10V

2

X5R-CERM
0201-1

ROOM=CODEC

NC
NC

G8

MIC6_BIAS

G9

MIC6_BIAS_FILT

GNDD

E2

A8

A1

SHORT-10L-0.1MM-SM

F11

A11

XW4802

2 1

ROOM=CODEC

K7

GNDP

L7

L1

L11

L10

CODEC_AGND

40

SYNC_MASTER=test_mlb

PAGE TITLE

AUDIO: CODEC (2/2)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

48 OF 85

SHEET

40 OF 60

SIZE

D

SYNC_DATE=10/13/2016

A

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

AMP AD0 AD1 I2C_ADR

D

42 40 22

50 49 48 42 41 40 38 25 20 17

59 54

PP1V2_CODEC_S2

PP1V8_S2

1

C4908

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=BOT_SPK

1

C4907

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=BOT_SPK

PP_VDD_MAIN

----->

59 47 45

TOP

00

TBD1

AP I2C2

D

BOT

ARC

44 43 42 36 33 29 26 24 22 17

0 0

0

1

TBD1

AOP I2C1

TBD2

C

B

56

50 49 48 42 41 40 38 25 20 17

AOP_TO_SPKAMP_BOT_RESET_L

IN

50 43 42 40 13 5

R4900

100K

5%

1/32W

MF

01005

ROOM=BOT_SPK

PP1V8_S2

59 54

43 40

50 43 42 40 13

43 42 40 13

56 43 5

1

43 42 5

2

54

54

BOT_SPK_VA

1

C4906

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=BOT_SPK

BOT_SPK_AGND

BOT_SPK_FILT

1

C4909

1UF

20%

6.3V

2

X6S-CERM
0201

ROOM=BOT_SPK

BOT_SPK_AGND

I2C1_AOP_SCL

IN

I2C1_AOP_SDA

BI

CODEC_TO_SPKRAMP_BOT_ARC_MCLK

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_DIN

IN

SPKAMP_BOT_ARC_TO_AOP_INT_L

OUT

SPKAMP_TO_OTHERS_SYNC

OUT

BOT_SPK_AGND

41

41

41

OMIT

XW4900

SM

ROOM=BOT_SPK

NC

1

H2

VA

H6

H7

VPVD_FILTVL

H3

A1

A2

C5

VPB

C6

C7

C4903

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=BOT_SPK

1

C4900

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOT_SPK

1

C4901

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOT_SPK

1

C4902

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOT_SPK

C

U4902

CS35L27

WLCSP

E7

VASP

F7

VSWIRE

H1

FILT+

F5

PDM1_CLK/SWIRE_CLK

F6

PDM1_DATA/SWIRE_SD1

G7

PDM2_CLK

G6

PDM2_DATA

F4

SWIRE_SD2

D5

SCL

D4

SDA

E6

MCLK

E5

SCLK

D6

SDIN

D7

FSYNC

E4

SDOUT

C3

VD_FILT_SEL

H4

RESET*

G4

INT*

H5

SYNC

G3

AD0/GPI

G2

AD1

GNDA

A6

G1

21

CRITICAL

ROOM=BOT_SPK

GNDB

B3

B6

C4

GNDD

G5

GNDP

E3

D3

CF1+
CF1+

CF1­CF1-

CF2+
CF2+
CF2+

CF2­CF2-

VBST
VBST

VSPK
VSPK

OUT+

OUT-

VSNS+

VSNS-

F3

A5
B5

A7
B7

A3
B1
B2

A4
B4

C1
C2

D1
E1

E2
D2

F2
F1

BOT_SPK_FLY_CAP1_POS

BOT_SPK_FLY_CAP1_NEG

BOT_SPK_FLY_CAP2_POS

BOT_SPK_FLY_CAP2_NEG

1

C4910

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOT_SPK

1

C4911

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOT_SPK

SPKRAMP_BOT_TO_COIL_OUT_POS
SPKRAMP_BOT_TO_COIL_OUT_NEG

COIL_TO_SPKRAMP_BOT_VSENSE_POS
COIL_TO_SPKRAMP_BOT_VSENSE_NEG

50

50

50

50

1

C4920

4.2UF

10%
16V

2

X5R-CERM
0402-0.1MM

ROOM=BOT_SPK

1

C4921

4.2UF

10%
16V

2

X5R-CERM
0402-0.1MM

ROOM=BOT_SPK

1

C4922

4.2UF

10%
16V

2

X5R-CERM
0402-0.1MM

ROOM=BOT_SPK

1

C4925

1UF

20%
16V

2

CER-X5R
0201

ROOM=BOT_SPK

PP_SPKAMP_BOT_VBOOST

1

C4923

220PF

5%
25V

2

COG
01005

ROOM=BOT_SPK

1

C4924

2200PF

10%
16V

2

X5R-CERM
01005

ROOM=BOT_SPK

B

A

Place off of allston GND pin

PAGE TITLE

AUDIO: SOUTH SPKAMP

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=04/05/2017

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

49 OF 85

SHEET

41 OF 60

A

SIZE

D

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

D

41 40 22

50 49 48 42 41 40 38 25 20 17

59 54

PP1V2_CODEC_S2

PP1V8_S2

1

C5008

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=TOP_SPK

1

C5007

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=TOP_SPK

PP_VDD_MAIN

----->

AMP

TOP

AD0

0

AD1

0

I2C_ADR

TBD1

AP I2C2

D

BOT

ARC

59 47 45

44 43 41 36 33 29 26 24 22 17

0

0

0

1

TBD1

AOP I2C1

TBD2

C

B

TOP_SPK_FILT

1

C5009

1UF

20%

6.3V

2

X6S-CERM
0201

ROOM=TOP_SPK

TOP_SPK_AGND

55

IN

50 49 48 42 41 40 38 25 20 17

42

AP_TO_SPKRAMP_TOP_RESET_L

1

2

PP1V8_S2

59 54

50 43 41 40 13 5

50 43 41 40 13

43 41 40 13

R5000

100K

5%
1/32W
MF
01005

ROOM=TOP_SPK

39

39

52

52

11

55

41 5
43

TOP_SPK_VA

1

C5006

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=TOP_SPK

TOP_SPK_AGND

PDM_CODEC_TO_SPKAMP_TOP_CLK

IN

PDM_CODEC_TO_SPKAMP_TOP_DATA

IN

I2C2_AP_SCL

IN

I2C2_AP_SDA

BI

I2S_AP_TO_SPKAMP_TOP_MCLK

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_DIN

IN

SPKRAMP_TOP_TO_AP_INT_L

OUT

SPKAMP_TO_OTHERS_SYNC

OUT

42

NC

OMIT

H6

H2

VA

E7

VASP

F7

VSWIRE

H1

FILT+

F5

PDM1_CLK/SWIRE_CLK

F6

PDM1_DATA/SWIRE_SD1

G7

PDM2_CLK

G6

PDM2_DATA

F4

SWIRE_SD2

D5

SCL

D4

SDA

E6

MCLK

E5

SCLK

D6

SDIN

D7

FSYNC

E4

SDOUT

C3

VD_FILT_SEL

H4

RESET*

G4

INT*

H5

SYNC

G3

AD0/GPI

G2

AD1

GNDA

ROOM=TOP_SPK

GNDB

H7

U5002

CS35L27

WLCSP

CRITICAL

GNDD

VPVD_FILTVL

H3

A2

A1

GNDP

C5

VPB

C7

C6

CF1+
CF1+

CF1­CF1-

CF2+
CF2+
CF2+

CF2­CF2-

VBST
VBST

VSPK
VSPK

OUT+

OUT-

VSNS+

VSNS-

A5
B5

A7
B7

A3
B1
B2

A4
B4

C1
C2

D1
E1

E2
D2

F2
F1

1

C5003

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=TOP_SPK

TOP_SPK_FLY_CAP1_POS

TOP_SPK_FLY_CAP1_NEG

TOP_SPK_FLY_CAP2_POS

TOP_SPK_FLY_CAP2_NEG

1

C5000

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=TOP_SPK

SPKRAMP_TOP_TO_COIL_OUT_POS
SPKRAMP_TOP_TO_COIL_OUT_NEG

COIL_TO_SPKRAMP_TOP_VSENSE_POS
COIL_TO_SPKRAMP_TOP_VSENSE_NEG

1

C5001

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=TOP_SPK

1

2

1

2

C5010

18UF

20%

6.3V
CER-X5R
0402-0.1MM

ROOM=TOP_SPK

C5011

18UF

20%

6.3V
CER-X5R
0402-0.1MM

ROOM=TOP_SPK

1

C5002

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=TOP_SPK

38

38

38

38

1

C5020

4.2UF

10%
16V

2

X5R-CERM
0402-0.1MM

ROOM=TOP_SPK

1

C5021

4.2UF

10%
16V

2

X5R-CERM
0402-0.1MM

ROOM=TOP_SPK

1

C5022

4.2UF

10%
16V

2

X5R-CERM
0402-0.1MM

ROOM=TOP_SPK

1

C5025

1UF

20%
16V

2

CER-X5R
0201

ROOM=TOP_SPK

PP_SPKAMP_TOP_VBOOST

1

C5023

220PF

5%
25V

2

COG
01005

ROOM=TOP_SPK

1

C5024

2200PF

10%
16V

2

X5R-CERM
01005

ROOM=TOP_SPK

C

B

TOP_SPK_AGND

42

XW5000

SM

21

ROOM=TOP_SPK

G1

A6

B3

B6

C4

G5

D3

E3

F3

A

8

67

SYNC_DATE=04/05/2017

PAGE TITLE

A

AUDIO: NORTH SPKAMP

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

50 OF 85

SHEET

42 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

C

B

57 5

55

57 5

55

NFC_TO_ARC_RESET_L

IN

PMU_NFC_TO_ARC_RESET_L

IN

NFC_TO_ARC_TRIG

IN

PMU_MASK_NFC_TO_ARC_TRIG

IN

R5112

61.9K

1/32W
01005

21

1%
MF

R5111

61.9K

1/32W
01005

21

1%
MF

1

R5100

200K

1%
1/32W
MF
01005

2

50 42 41 40 13 5

1

R5101

200K

1%
1/32W
MF
01005

2

PP1V2_ARC_VD_FILT

PP1V8_ARC_VA_INTERNAL

43

54

54

41 40

42 41 40 13

50 42 41 40 13

50 40 13

56 41 5

42 41 5

1

C5108

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=ARC

1

C5107

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=ARC

1

C5106

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=ARC

ARC_AGND

ARC_FILT

1

C5109

1UF

20%

6.3V

2

X6S-CERM
0201

ROOM=ARC

I2C1_AOP_SCL

IN

I2C1_AOP_SDA

BI

CODEC_TO_SPKRAMP_BOT_ARC_MCLK

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_DIN

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK

IN

I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT

OUT

SPKAMP_BOT_ARC_TO_AOP_INT_L

OUT

SPKAMP_TO_OTHERS_SYNC

OUT

PP1V8_ARC_VA_INTERNAL

43

Place off of allston GND pin

ARC_AGND

ARC_AGND

43

43

43

NC

XW5100

ROOM=ARC

NC

OMIT

SM

H6

H2

VA

E7

VASP

F7

VSWIRE

H1

FILT+

F5

PDM1_CLK/SWIRE_CLK

F6

PDM1_DATA/SWIRE_SD1

G7

PDM2_CLK

G6

PDM2_DATA

F4

SWIRE_SD2

D5

SCL

D4

SDA

E6

MCLK

E5

SCLK

D6

SDIN

D7

FSYNC

E4

SDOUT

C3

VD_FILT_SEL

H4

RESET*

G4

INT*

H5

SYNC

G3

AD0/GPI

G2

AD1

A6

GNDB

B3

GNDA

G1

21

H7

VPVD_FILTVL

U5102

CS35L27

WLCSP

CRITICAL

ROOM=ARC

GNDD

B6

C4

G5

H3

A2

A1

GNDP

E3

D3

C5

VPB

F3

C7

C6

CF1+
CF1+

CF1­CF1-

CF2+
CF2+
CF2+

CF2­CF2-

VBST
VBST

VSPK
VSPK

OUT+

OUT-

VSNS+

VSNS-

A5
B5

A7
B7

A3
B1
B2

A4
B4

C1
C2

D1
E1

E2
D2

F2
F1

1

C5103

0.22UF

10%

6.3V

2

CER-X5R
01005

ROOM=ARC

ARC_FLY_CAP1_POS

ARC_FLY_CAP1_NEG

ARC_FLY_CAP2_POS

ARC_FLY_CAP2_NEG

1

2

ROOM=ARC

C5100

18UF

20%

6.3V
CER-X5R
0402-0.1MM

1

C5101

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=ARC

1

C5102

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=ARC

1

2

1

2

ARC_TO_SOLENOID_OUT_POS
ARC_TO_SOLENOID_OUT_NEG

SOLENOID_TO_ARC_VSENSE_POS
SOLENOID_TO_ARC_VSENSE_NEG

C5110

18UF

20%

6.3V
CER-X5R
0402-0.1MM

ROOM=ARC

C5111

18UF

20%

6.3V
CER-X5R
0402-0.1MM

ROOM=ARC

50

50

50

50

PP_VDD_MAIN

1

C5120

4.2UF

10%
16V

2

X5R-CERM
0402-0.1MM

AMP

AD0

TOP 0

BOT

0

AD1

0

0

I2C_ADR

TBD1

TBD1

AP I2C2

D

AOP I2C1

----->

59 47 45

44 42 41 36 33 29 26 24 22 17

ARC

0

1

TBD2

C

PP_ARC_VBOOST

1

C5121

4.2UF

10%
16V

2

X5R-CERM
0402-0.1MM

ROOM=ARCROOM=ARC

1

C5122

4.2UF

10%
16V

2

X5R-CERM
0402-0.1MM

ROOM=ARC

1

C5125

1UF

20%
16V

2

CER-X5R
0201

ROOM=ARC

1

C5123

220PF

5%
25V

2

COG
01005

ROOM=ARC

1

C5124

2200PF

10%
16V

2

X5R-CERM
01005

ROOM=ARC

B

A

8

67

SYNC_DATE=04/05/2017

PAGE TITLE

A

ARC: AMP

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

51 OF 85

SHEET

43 OF 60

1

SIZE

D

Display Control Signals

VIETMOBILE.VN

678

3 245

1

Display Flex Connector

Display 1V0 LDO for D33 second display vendor

<-- This one on MLBRcpt: 516S00210

rdar: #29872369

Plug: 516S00211

D

55

55

FL5700

BM28P0.6-34DS/2-0.35V

PMU_TO_DISPLAY_RESET_L

IN

PMU_TO_DISPLAY_PANICB

IN

R5700

100K

5%

1/32W

MF

01005

NOSTUFF

FERR-150OHM-25%-200MA

2 1

1

2

01005

ROOM=B2B_DISPLAY

R5701

10

21

5%

1/32W

MF

01005

ROOM=B2B_DISPLAY

1

C5700

220PF

5%
25V

2

COG
01005

ROOM=B2B_DISPLAY

1

C5701

220PF

5%
25V

2

COG
01005

PMU_TO_DISPLAY_RESET_CONN_L

PMU_TO_DISPLAY_PANICB_CONN

ROOM=B2B_DISPLAY

44

44

DISPLAY_TO_AP_PANEL_ID

55

R5705

1.00K

1/32W
01005

ROOM=B2B_DISPLAY

21

5%
MF

DISPLAY_TO_AP_PANEL_ID_R

44

PP_VDD_MAIN_DISPLAY_CONN

44

PP1V8_DISPLAY_DVDD_CONN

44

DISPLAY_TO_PMU_AMUX_CONN

44

PMU_TO_DISPLAY_RESET_CONN_L

44

DISPLAY_TO_AP_PANEL_ID_R

44

PMU_TO_DISPLAY_PANICB_CONN

44

NC_SPI_DISPLAY_FLASH_CS_L
NC_PP_VPP
NC_SPI_AP_TO_DISPLAY_FLASH_MOSI

90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P

44

90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N

44

R5702

9

DISPLAY_TO_AP_BSYNC_WATCHDOG 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P

OUT

0.00

1/32W
01005

ROOM=B2B_DISPLAY

21

0%
MF

DISPLAY_TO_AP_BSYNC_WATCHDOG_CONN

1

C5702

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DISPLAY

44 44

90_MIPI_AP_TO_DISPLAY_CLK_CONN_P

44

90_MIPI_AP_TO_DISPLAY_CLK_CONN_N

44

90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P

44

90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N

44

J5700

F-ST-SM

ROOM=B2B_DISPLAY

PWR

3635

SIG

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433

NC

PP_VDD_MAIN_DISPLAY_CONN

PP3V0_DISPLAY_VCI_CONN

44

44

NC_SPI_AP_TO_DISPLAY_FLASH_SCLK

PP1V0_DISPLAY_VDD_CONN

PP1V1_DISPLAY_VDD_CONN

ISP_TO_DISPLAY_FLASH_INT_CONN

44

44

44

NC_SPI_DISPLAY_FLASH_TO_AP_MISO

DISPLAY_TO_AP_BSYNC_WATCHDOG_CONN

90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N

90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N

44

44

44

44

D

C

B

23

PWR

3837

DISPLAY_TO_PMU_AMUX

IN

FL5703

FERR-150OHM-25%-200MA

2 1

01005

ROOM=B2B_DISPLAY

1

2

C5703

56PF

5%
25V
NP0-C0G-CERM
01005

ROOM=B2B_DISPLAY

DISPLAY_TO_PMU_AMUX_CONN

44

Display MIPI

C

R5704

9

IN

Here for syncccing purposes

PP3V0_DISPLAY

22

PP1V0_DISPLAY_DVDD

22

0.00

1/32W
01005

ROOM=B2B_DISPLAY

MAKE_BASE=TRUE

MAKE_BASE=TRUE

0%
MF

21

1

C5704

220PF

5%
25V

2

COG
01005

ISP_TO_DISPLAY_FLASH_INT_CONNISP_TO_DISPLAY_FLASH_INT

ROOM=B2B_DISPLAY

PP3V0_DISPLAY

1

C2910

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

PP1V0_DISPLAY_DVDD

1

C2914

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

44

44

44

Display MIPI

9

9

9

9

9

9

9

90_MIPI_AP_TO_DISPLAY_DATA0_N

IN

90_MIPI_AP_TO_DISPLAY_DATA0_P

IN

90_MIPI_AP_TO_DISPLAY_DATA1_N

IN

90_MIPI_AP_TO_DISPLAY_DATA1_P

IN

90_MIPI_AP_TO_DISPLAY_DATA2_P

IN

90_MIPI_AP_TO_DISPLAY_DATA2_N

IN

90_MIPI_AP_TO_DISPLAY_DATA3_P

IN

ROOM=B2B_DISPLAY

L5700

35OHM-7GHZ-0.05MA-3OHM

TAM0403S-SM

SYM_VER-1

1

ROOM=B2B_DISPLAY

L5710

35OHM-7GHZ-0.05MA-3OHM

TAM0403S-SM

SYM_VER-1

1

ROOM=B2B_DISPLAY

L5720

35OHM-7GHZ-0.05MA-3OHM

TAM0403S-SM

SYM_VER-1

1

ROOM=B2B_DISPLAY

35OHM-7GHZ-0.05MA-3OHM

L5730

TAM0403S-SM

SYM_VER-1

1

4

32

GND_VOID

4

32

GND_VOID

4

32

GND_VOID

4

90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N

90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P

90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N

90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P

90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P

90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N

90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P

44

44

44

44

44

44

44

Display Power

36 34 32 31 30 29 20 19 17 6

53 52 37

44

PP1V8_IO

PP3V0_DISPLAY

FL5780

FERR-33OHM-25%-1.5A

2 1

0201

ROOM=B2B_DISPLAY

1

2

FL5782

0

21

5%

1/20W

MF

0201

1

2

FL5783

FERR-70OHM-25%-0.300A

21

01005

ROOM=B2B_DISPLAY

1

2

C5781

220PF

5%
25V
COG
01005

ROOM=B2B_DISPLAY

C5782

220PF

5%
25V
COG
01005

ROOM=B2B_DISPLAY

C5783

220PF

5%
25V
COG
01005

ROOM=B2B_DISPLAY

PP1V8_DISPLAY_DVDD_CONN

PP1V0_DISPLAY_VDD_CONNPP1V0_DISPLAY_DVDD

PP3V0_DISPLAY_VCI_CONN

44

44 44

44

B

A

1.2V LDO is for LGC test chip

Once normal panel is available switch to 1.1V

U5701

SCY99224-1.15V

29 22 20 17

55

PP1V26_S2
PMU_TO_DISPLAY_LDO_EN

C5721

0.47UF

20%

6.3V
X5R

ROOM=B2B_DISPLAY

01005

1

2

R5720

100K

1/32W

ROOM=B2B_DISPLAY

01005

NOSTUFF

5%
MF

IN OUT

B1

EN

1

2

WLCSP

CRITICAL

ROOM=B2B_DISPLAY

GND

B2

A2A1

C5705

2.2UF

20%

6.3V

X5R-CERM

0201

ROOM=B2B_DISPLAY

1

2

9

9

9

90_MIPI_AP_TO_DISPLAY_DATA3_N

IN

90_MIPI_AP_TO_DISPLAY_CLK_P

IN

90_MIPI_AP_TO_DISPLAY_CLK_N

IN

FERR-33OHM-25%-1.5A

PP1V1_DISPLAY_VDD

FL5781

2 1

0201

ROOM=B2B_DISPLAY

1

C5706

220PF

5%
25V

2

COG
01005

ROOM=B2B_DISPLAY

32

ROOM=B2B_DISPLAY

35OHM-7GHZ-0.05MA-3OHM

L5740

TAM0403S-SM

SYM_VER-1

1

PP1V1_DISPLAY_VDD_CONN

GND_VOID

4

32

GND_VOID

VOLTAGE=1.1V

44

90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N

90_MIPI_AP_TO_DISPLAY_CLK_CONN_P

90_MIPI_AP_TO_DISPLAY_CLK_CONN_N

44

44

44

XW5784

SHORT-0201

43 42 41 36 33 29 26 24 22 17 44

59 47 45

PP_VDD_MAIN PP_VDD_MAIN_DISPLAY_CONN

ROOM=B2B_DISPLAY

XW5785

SHORT-0201

ROOM=B2B_DISPLAY

PAGE TITLE

21

1

C5784

220PF

5%
25V

2

COG

21

01005

ROOM=B2B_DISPLAY

1

C5785

220PF

5%
25V

2

COG
01005

ROOM=B2B_DISPLAY

1

C5786

220PF

5%
25V

2

COG
01005

ROOM=B2B_DISPLAY

CG: B2B Display

DRAWING NUMBER

051-02545

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

7.0.0

BRANCH

PAGE

57 OF 85

SHEET

44 OF 60

SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb

SIZE

D

A

8

67

35 4

2

1

678

VIETMOBILE.VN

VDD_MAIN OV CUT-OFF CIRCUIT

3 245

1

D

43 42 41 36 33 29 26 24 22 17

59 47 44

ROOM=OV_COMP

U5900

TPS3720-S

A1

BGA

VDD

CRITICAL

OUTA
OUTB

A2
B2

PP_HYDRA_ACC1_OV_COMP

PMU_TO_IKTARA_RESET_L

Place near Hydra

VOLTAGE=4.3V

58 23

XW5900

SHORT-20L-0.05MM-SM

NO_XNET_CONNECTION

OMIT

ROOM=SOC

D

21

PP_HYDRA_ACC1PP_VDD_MAIN

50 49

C

PART NUMBER

GND

B1

ALT_PARTS353S01398353S01375 ON SEMIU5900

C

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

B

B

A

8

67

A

PAGE TITLE

I/O: Overvoltage Cut-Off Circuit

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

CDS_LIB=apple

BRANCH

PAGE

59 OF 85

SHEET

45 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

ROOM=HALOGEN

HYDRA_TO_PMU_USB_BRICK_ID_TIA

23 49

LDCM

47 59

R6021

200K

1/32W
01005

C6021

CERM-X5R

0402-0.1MM

ROOM=HALOGEN

1%
MF

10UF

21

20%

6.3V

21

PP_VDD_BOOST

17 22 24 29 36 40 46

1

C6020

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=HALOGEN

HALOGEN_VSTIM_C

46

HALOGEN_TIA_IN

C3
B3

ROOM=HALOGEN

U6020

SCY9920175

WLCSP

+

­B2

C2 A2

A3

AOP_TO_HALOGEN_AFE_EN

HALOGEN_TIA_IOUT_C

46 56

C6010

0.01UF

21

10%

6.3V
X5R

01005

ROOM=CODEC

HALOGEN_TIA_IOUT

C6013

0.01UF

TIA_NEG_C

21

D

39

AIN6

39

C

PDM attenuation

DC Bias

ROOM=HALOGEN

ROOM=HALOGEN

R6020

4.99K

1/32W
01005

21

1%
MF

C6022

5PF

21

+/-0.1PF

16V

NP0-C0G

01005

1

R6060

3.01M

1%
1/32W
TK
01005

2

ROOM=CODEC

10%

6.3V
X5R

01005

ROOM=CODEC

Input filters live here

to support page synccing

C

Codec

B

39

R6130 Value Quartered due to: 33165127

R6030

CODEC_TO_HALOGEN_AMP_PDM_OUT HALOGEN_AMP_ATN

IN

2.0K

1/32W
01005

ROOM=HALOGEN

21

1%
MF

R6031

499

1%

1/32W

MF

01005

ROOM=HALOGEN

C6030

2.2UF

1

CER-X5R

ROOM=HALOGEN

2

AOP_TO_HALOGEN_AFE_EN

46 56

HALOGEN_VSTIM_DECOUPLED

21

20%

6.3V
0201

C6036

0.1UF

20%

6.3V

X5R-CERM

01005

ROOM=HALOGEN

C6032

330PF

21

10%

1

2

1

R6032

22.1K

1%
1/32W
MF
01005

2

ROOM=HALOGEN

1

R6033

22.1K

1%
1/32W
MF
01005

2

ROOM=HALOGEN

R6034

42.2K

1%

1/32W

MF

01005

ROOM=HALOGEN

ROOM=HALOGEN

40

PP_VDD_BOOST

17 22 24 29 36 46 47 59

R6035

21

HALOGEN_VSTIM_FB

187K

1%

1/32W

MF

01005

ROOM=HALOGEN

21

HALOGEN_VSTIM_IN

1

C6031

100PF

5%
16V

2

NP0-C0G
01005

ROOM=HALOGEN

C1

B1

16V

CER-X7R

01005

CRITICAL

ROOM=HALOGEN

U6020

SCY9920175

WLCSP

+

­B2

C2 A2

HALOGEN_VSTIM_C

46

A1

AOP_TO_HALOGEN_AFE_EN

46 56

C6011

0.01UF

21

10%

6.3V
X5R

01005

ROOM=CODEC

C6012

0.01UF

21

10%

6.3V
X5R

01005

ROOM=CODEC

HALOGEN_VSTIM

STIM_NEG_C

B

39

AIN8

39

A

8

67

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=06/06/2017

A

I/O: LDCM

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

60 OF 85

SHEET

46 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

GECKO Reset Pull Down

56 47

AOP_TO_GECKO_RESET_L

D

C

1

R6100

100K

5%
1/32W
MF
01005

2

ROOM=GECKO

43 42 41 36 33 29 26 24 22 17

59 45 44

C6161

4UF

20%

6.3V

CERM-X5R

0201

ROOM=GECKO

Gecko

I2C ADDRESS: 0X52

PP_VDD_BOOSTPP_VDD_MAIN

4UF

20%

6.3V
0201

ROOM=GECKO

1

2

1

2

D4

D3

A3

VDD_BUCK

VDD_LDO

VDD_BYPASS

C6162

CERM-X5R

59 46 40 36 29 24 22 17

C

B

60 30 23 17

52

52

56 5

56 47

ACORN_GECKO_ANSEL_TO_PMU_ADC

OUT

I2C0_AP_SCL

IN

I2C0_AP_SDA

BI

GECKO_TO_AOP_IRQ_L

OUT

AOP_TO_GECKO_RESET_L

IN

D2
B2

A2
B1
C1

U6150

FAN53740UCA1X

CSP

AMUX
SCL

SDA
IRQ*
RESET*

ROOM=GECKO

CRITICAL

AGND

C2

B3

IND Alternate

VOUT

PGND

B4

NC

LX

GECKO_LX

A4
C3

C4

A1
D1

L6150

0.47UH-20%-2.7A-0.071OHM

21

MCFE1210-SM

1

C6151

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=GECKO

1

C6152

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=GECKO

PP_ACC_VAR

1

C6150

220PF

5%
25V

2

COG
01005

ROOM=GECKO

49

B

A

PART NUMBER

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

L6150ALT_PARTS152S00854 152S00853

ALT_PARTS L6150152S00855 152S00853

IND,PWR,0.47UH,20%,2.8A,CY

IND,PWR,0.47UH,20%,2.7A,Murata

TABLE_ALT_ITEM

SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016

PAGE TITLE

A

I/O: Gecko

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

61 OF 85

SHEET

47 OF 60

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

1

D

D

USB-PD

C

PP_VAR_USB_RVP

49 26

1

R6210

499K

1%
1/20W
MF
201

2

ROOM=USB_PD

1

R6211

50K

1%
1/32W
MF
01005

2

ROOM=USB_PD

1

C6210

22NF

20%

6.3V

2

X5R-CERM
01005

ROOM=USB_PD

54 50 49 42 41 40 38 25 20 17

58 49 38 22

59

PP1V8_S2
PP3V0_S2

1

2

11 5

54

IN

54

BI

11 5

BI

11 5

IN

C6290

1.0UF

20%
10V
X5R-CERM
0201-1

ROOM=USB_PD

1

C6291

1.0UF

20%
10V

2

X5R-CERM
0201-1

ROOM=USB_PD

CCG2_TO_SMC_INT_L

PP5V0_USB_RVP_R

I2C0_SMC_SCL
I2C0_SMC_SDA

AP_BI_CCG2_SWDIO
AP_TO_CCG2_SWCLK

PP1V8_VCCD_CCG2

1

C6292

1.0UF

20%
10V

2

X5R-CERM
0201-1

ROOM=USB_PD

NC

NC
NC

C3
D3
C2
D2
B2

A3
A2

E2
D1

A1

VDDD

VCCD

GPIO_C3
GPIO_D3
GPIO_C2
GPIO_D2
GPIO_B2

ROOM=USB_PD

CG8740AAT

I2C_0_SCL
I2C_0_SDA

SWD_IO
SWD_CLK

NCNC

E1E3C4

VDDIO

CRITICAL

U6200

CSP

E4

VCONN2

VCONN1

CC1
CC2

RD1

XRES

B4
A4

B3

B1

NC

PMU_TO_CCG2_RESET_L

C

CCG2_BI_HYDRA_CC

1

C6200

220PF

5%
25V

2

COG
01005

ROOM=USB_PD

55

IN

49

BIOUT

B

VSS

D4

VSS

C1

B

A

8

67

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

A

I/O: USB PD

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

62 OF 85

SHEET

48 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

D

Hydra

I2C Address: 0011010X

C

B

46 23

7

7

HYDRA_TO_PMU_USB_BRICK_ID_TIA

OUT

90_USB_AP_DATA_P

BI

90_USB_AP_DATA_N

BI

PP3V0_S2

C6300

1

0.01UF

10%

2

6.3V
X5R
01005

ROOM=HYDRA

NOSTUFF
No stuffed and 0 ohmed for P1
R was previosuly a 6.34K

15NH-250MA

GND_VOID

15NH-250MA

GND_VOID

1

C6390

1.0UF

20%
10V

2

X5R-CERM
0201-1

ROOM=HYDRA

R6300

0.00

1/32W
01005

ROOM=HYDRA

L6300

0201

ROOM=HYDRA

L6301

0201

ROOM=HYDRA

0%
MF

PP_ACC_VAR

1

C6391

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=HYDRA

54 50 48 42 41 40 38 25 20 17

PP1V8_S2

59

C6395

1

0.01UF

10%

2

6.3V
X5R
01005

ROOM=HYDRA

H4

VDD1V8

H5

VDD3V0

C6

B6

A6

ACC_PWR

D6

E6

U6300

CBTL1612A1

WLCSP

ROOM=HYDRA

CRITICAL

P_IN
ACC1
ACC1
ACC1
ACC1
ACC1
ACC2
ACC2
ACC2
ACC2
ACC2

DP1

DN1

DP2

DN2

CON_DET_L

POW_GATE_EN*

SWITCH_EN

HOST_RESET

SDA

SCL

INT

BYPASS

G6
A5
B5
C5
D5
E5
A7
B7
C7
D7
E7

C3
C4

A3
A4

G3
H3
E4

F6
G5

G4
F7
F5

HYDRA_TO_YANGTZE_VBUS1_VALID_L

PMU_TO_AP_HYDRA_ACTIVE_READY

HYDRA_TO_PMU_HOST_RESET

NC

NC

C2

DIG_DP

D2

DIG_DN

D3

USB1_DP

D4

USB1_DN

F3

BRICK_ID

B3

USB0_DP

B4

USB0_DN

D1

UART0_TX

C1

UART0_RX

F2

UART1_TX

E2

UART1_RX

B1

UART2_TX

A1

UART2_RX

E1

JTAG_CLK

F1

JTAG_DIO

H2

FORCE_DFU

G2

EXT_SW_EN

G1

DOCK_CONNECT

B2

CC0

A2

CC1

39

39

7

7

21

90_MIKEYBUS_DATA_P

BI

90_MIKEYBUS_DATA_N

BI

90_USB_DBG_DATA_P

BI

90_USB_DBG_DATA_N

BI

HYDRA_TO_PMU_USB_BRICK_ID_TIA_R

90_USB_AP_DATA_L_P
90_USB_AP_DATA_L_N

12

12

12

12 5

UART_AP_TO_ACCESSORY_TXD

IN

UART_ACCESSORY_TO_AP_RXD

OUT

UART_AP_DEBUG_TXD

IN

UART_AP_DEBUG_RXD

OUT

GND

MAKE_BASE=TRUE

21

21

7

7

57 12

13

48

SWD_DOCK_TO_AP_SWCLK

OUT

SWD_DOCK_BI_AP_SWDIO

BI

HYDRA_TO_AP_FORCE_DFU

OUT

HYDRA_TO_NUB_DOCK_CONNECT

OUT

CCG2_BI_HYDRA_CC

BI

47 58 48 38 22

PP_HYDRA_ACC1

PP_HYDRA_ACC2

50

90_HYDRA_DP1_CONN_P
90_HYDRA_DP1_CONN_N

90_HYDRA_DP2_CONN_P
90_HYDRA_DP2_CONN_N

HYDRA_CON_DETECT_L

OUT

OUT

I2C1_SMC_SDA
I2C1_SMC_SCL

HYDRA_TO_NUB_INT

OUT

HYDRA_BYPASS

C

From Yangtze

PP_VAR_USB_RVP

50 45

1

C6311

0.47UF

20%
25V

2

CER-X5R
0201

ROOM=HYDRA

50

BI

50

BI

50

BI

50

BI

50

IN

26 5

IN

BI

IN

23 7 5

23

54

54

13

1

C6312

0.47UF

20%
25V

2

CER-X5R
0201

ROOM=HYDRA

48 26

B

A

E3

DVSS

G7

H1

H6

H7

DVSS1

F4

1

C6330

1.0UF

20%
10V

2

X5R-CERM
0201-1

ROOM=HYDRA

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

8

67

I/O: Hydra

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

PAGE

63 OF 85

SHEET

49 OF 60

1

SIZE

D

678

VIETMOBILE.VN

3 245

1

D

C

ARC

SOLENOID_TO_ARC_VSENSE_POS

43

SOLENOID_TO_ARC_VSENSE_NEG

43

54 50 28 27 20

56

POTASSIUM_TO_AOP_INT

OUT

PP1V8_IMU_S2

R6490

100

1

C6475

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

5%

1/32W

MF

01005

ROOM=B2B_DOCK

R6491

100

1

C6474

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

5%

1/32W

MF

01005

ROOM=B2B_DOCK

POTASSIUM

1

R6440

10K

5%
1/32W
MF
01005

2

R6433

0.00

1/32W
01005

ROOM=B2B_BUTTON

21

0%
MF

21

21

SOLENOID_TO_ARC_VSENSE_POS_CONN

SOLENOID_TO_ARC_VSENSE_NEG_CONN

POTASSIUM_TO_AOP_INT_CONN

1

C6433

220PF

5%
25V

2

COG
01005

ROOM=B2B_BUTTON

54 49 48 42 41 40 38 25 20 17

52 50

52 50

43 42 41 40 13 5

43 42 41 40 13

43 40 13

50

59

50

IN

50

BI

IN

IN

BI

PP1V8_S2

I2C0_AP_SCL

I2C0_AP_SDA

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK

I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT

1

C6421

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

FL6400

FERR-150OHM-25%-200MA

2 1

01005

ROOM=B2B_DOCK

R6419

49.9

1/32W
01005

ROOM=B2B_DOCK

21

1%
MF

R6420

49.9

1/32W
01005

ROOM=B2B_DOCK

21

1%
MF

R6421

49.9

1/32W
01005

ROOM=B2B_DOCK

21

1%
MF

PP1V8_S2_SAKONNET_CONN

1

C6400

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

1

C6416

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

1

C6418

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN

1

C6419

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN

1

C6420

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN

50

50

50

50

PP_VBUS1_E75

58 26

C6490

0.1UF

ROOM=B2B_DOCK

10%
25V
X5R

0201

DOCK FLEX CONNECTOR

<-- This one on MLBRcpt: 516S00423

Plug: 516S00424

J6400

BM28PS-44DS-2-0.35V

SPKRAMP_BOT_TO_COIL_OUT_NEG

50 41

SPKRAMP_BOT_TO_COIL_OUT_POS

50 41

COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN

50

LOWERMIC4_TO_CODEC_BIAS_FILT_RET

40

LOWERMIC4_TO_CODEC_AIN4_CONN_P

50

POTASSIUM_TO_AOP_INT_CONN

50

I2C1_AOP_SCL

50 54

PMU_TO_PHALANX1

55 50

PP_CODEC_TO_LOWERMIC1_BIAS_CONN

50

LOWERMIC1_TO_CODEC_AIN1_CONN_N

50

I2C0_AP_SDA

50 52

HYDRA_CON_DETECT_CONN_L

50

I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN

50

PP1V8_S2_SAKONNET_CONN

50

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN

50

I2C0_AP_SCL

50 52

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN

50

SOLENOID_TO_ARC_VSENSE_NEG_CONN

50

10%
25V
X5R

0201

1

C6492

0.1UF

2

ROOM=B2B_DOCK

1

C6491

0.1UF

2

ROOM=B2B_DOCK

10%
25V
X5R

0201

1

2

C6493

220PF

01005

ROOM=B2B_DOCK

5%
25V
COG

1

C6494

220PF

2

01005

ROOM=B2B_DOCK

5%
25V
COG

1

2

F-ST-SM

4645

21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
4241
4443

4847

ROOM=B2B_DOCK

COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN

PP_CODEC_TO_LOWERMIC4_BIAS_CONN

LOWERMIC4_TO_CODEC_AIN4_CONN_N

PP1V8_IMU_POTASSIUM_S2_CONN

I2C1_AOP_BI_POTASSIUM_SDA_CONN

PMU_TO_PHALANX2

LOWERMIC1_TO_CODEC_BIAS_FILT_RET

LOWERMIC1_TO_CODEC_AIN1_CONN_P

MIKEYBUS_REFERENCE

90_HYDRA_DP2_CONN_P
90_HYDRA_DP2_CONN_N
90_HYDRA_DP1_CONN_P
90_HYDRA_DP1_CONN_N

ARC_TO_SOLENOID_OUT_POS

SOLENOID_TO_ARC_VSENSE_POS_CONN

PP_HYDRA_ACC1_CONN
PP_HYDRA_ACC2_CONNARC_TO_SOLENOID_OUT_NEG

C6495

0.1UF

10%
25V
X5R

0201

ROOM=B2B_DOCK

1

C6496

0.1UF

2

ROOM=B2B_DOCK

10%
25V
X5R

0201

1

2

C6497

0.1UF

10%
25V
X5R

0201

ROOM=B2B_DOCK

50

50

50

50

50

55 50

40

50

39

49

49

49

49

50 43

50

50

50 50 43

1

2

D

C

B

A

54 50

I2C1_AOP_SCL

IN

1

C6431

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

CKPLUS_WAIVE=I2C_PULLUP

R6432

54

I2C1_AOP_SDA

BI

CKPLUS_WAIVE=I2C_PULLUP

0.00

1/32W
01005

ROOM=B2B_PEARL

0%
MF

21

I2C1_AOP_BI_POTASSIUM_SDA_CONN

1

C6432

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

FL6430

FERR-150OHM-25%-200MA

54 50 28 27 20 50

PP1V8_IMU_S2 PP1V8_IMU_POTASSIUM_S2_CONN

LOWER MIC1

2 1

01005

ROOM=B2B_DOCK

FL6450

1

C6430

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

FERR-150OHM-25%-200MA

39

LOWERMIC1_TO_CODEC_AIN1_P

OUT

2 1

01005

ROOM=B2B_DOCK

FL6452

1

C6450

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

LOWERMIC1_TO_CODEC_AIN1_CONN_P

FERR-150OHM-25%-200MA

39

LOWERMIC1_TO_CODEC_AIN1_N

OUT

2 1

01005

ROOM=B2B_DOCK

FL6454

1

C6452

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

LOWERMIC1_TO_CODEC_AIN1_CONN_N

FERR-150OHM-25%-200MA

PP_CODEC_TO_LOWERMIC1_BIAS

40

2 1

01005

ROOM=B2B_DOCK

1

C6454

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

PP_CODEC_TO_LOWERMIC1_BIAS_CONN

PHALANX

55 50

55 50

PMU_TO_PHALANX2

IN

PMU_TO_PHALANX1

BI

1

C6465

330PF

10%
16V

2

CER-X7R
01005

ROOM=B2B_DOCK

1

C6466

330PF

10%
16V

2

CER-X7R
01005

ROOM=B2B_DOCK

50

50

50

50

49

Hydra

HYDRA_CON_DETECT_L

OUT

PP_HYDRA_ACC1

49 45

PP_HYDRA_ACC2

49

MIC4

39

OUT

39

OUT

22-OHM-25%-1800MA

LOWERMIC4_TO_CODEC_AIN4_N

PP_CODEC_TO_LOWERMIC4_BIAS

40

LOWERMIC4_TO_CODEC_AIN4_P

R6410

100

2 1

5%

1/32W

MF

01005

ROOM=B2B_DOCK

FL6411

10-OHM-1.1A

21

01005

ROOM=B2B_DOCK

FL6413

21

0201

ROOM=B2B_DOCK

FERR-150OHM-25%-200MA

FERR-150OHM-25%-200MA

FERR-150OHM-25%-200MA

1

C6410

27PF

5%
16V

2

NP0-C0G
01005

ROOM=B2B_DOCK

1

C6411

100PF

5%
16V

2

NP0-C0G
01005

ROOM=B2B_DOCK

1

C6413

100PF

5%
16V

2

NP0-C0G
01005

ROOM=B2B_DOCK

FL6462

2 1

01005

ROOM=B2B_DOCK

FL6464

2 1

01005

ROOM=B2B_DOCK

FL6460

2 1

01005

ROOM=B2B_DOCK

HYDRA_CON_DETECT_CONN_L

PP_HYDRA_ACC1_CONN

PP_HYDRA_ACC2_CONN

LOWERMIC4_TO_CODEC_AIN4_CONN_N

1

C6462

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

PP_CODEC_TO_LOWERMIC4_BIAS_CONN

1

C6464

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

LOWERMIC4_TO_CODEC_AIN4_CONN_P

1

C6460

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

50

50

50

41

41

50 41

50 41

SOUTH SPEAKER

R6480

COIL_TO_SPKRAMP_BOT_VSENSE_NEG COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN

OUT

1

C6480

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

COIL_TO_SPKRAMP_BOT_VSENSE_POS COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN

OUT

1

C6482

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

SPKRAMP_BOT_TO_COIL_OUT_POS

IN

SPKRAMP_BOT_TO_COIL_OUT_NEG

IN

ARC_TO_SOLENOID_OUT_NEG

50

50

50

ARC_TO_SOLENOID_OUT_POS

100

21

5%

1/32W

MF

01005

ROOM=B2B_DOCK

R6482

100

1/32W
01005

ROOM=B2B_DOCK

ROOM=B2B_DOCK

SYNC_MASTER=test_mlb

PAGE TITLE

21

5%
MF

C6471

220PF

5%
25V
COG

01005

1

C6483

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

1

C6485

220PF

5%
25V

2

COG
01005

ROOM=B2B_DOCK

1

2

1

C6472

1000PF

10%
25V

2

X5R
0201

I/O: B2B Dock

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

C6470

220PF

ROOM=B2B_DOCK

01005

5%
25V
COG

1

C6486

1000PF

10%
25V

2

X5R
0201

ROOM=B2B_DOCK

1

C6487

1000PF

10%
25V

2

X5R
0201

ROOM=B2B_DOCK

1

2

1

C6473

1000PF

10%
25V

2

X5R
0201

DRAWING NUMBER

051-02545

REVISION

BRANCH

PAGE

64 OF 85

SHEET

50 OF 60

50 43

50 43

7.0.0

SYNC_DATE=10/13/2016

SIZE

D

50

50

B

A

8

67

35 4

2

1

678

VIETMOBILE.VN

3 245

Top Board Interposer APN:998-12513 <--- STUFFED

1

D

C

B

A

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

PMU_TO_SYSTEM_COLD_RESET_L

57

GND

57

AP_TO_CAMPMU_RESET_L

57

GND

57

BB_TO_MANY_GSM_BURST_IND

57

GND

57

HALL_CASE_TO_AOP_NORTH_L

57

GND

57

AP_TO_TOUCH_SCAN_CLK

57

GND

57

I2S_BB_TO_AP_BCLK

57

GND

57

I2S_BB_TO_AP_DIN

57

GND

57

I2S_AP_TO_BB_DOUT

57

GND

57

I2S_BB_TO_AP_LRCLK

57

GND

57

PP1V8_ALWAYS

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

NFC_TO_ARC_RESET_L

57

GND

57

NFC_TO_ARC_TRIG

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

GND

57

AP_TO_BB_RESET_L

57

GND

57

SWD_AOP_BI_BB_SWDIO

57

GND

57

UART_GNSS_TO_AP_CTS_L

57

GND

57

UART_AP_TO_GNSS_RTS_L

57

GND

57

PCIE_AP_TO_WLAN_PERST_L

57

GND

57

AP_TO_RACER_RESET_L

57

GND

57

AP_TO_WLAN_TIME_SYNC

57

GND

57

GNSS_TO_AP_LOW_PWR_IND

57

GND

57

HYDRA_TO_AP_FORCE_DFU

57

GND

57

PP1V8_S2

57

PP1V8_S2

57

GND

57

GND

57

GND

57

GND

57

GND

57

INTERPOSER_PIN_90

57

GND

57

AP_TO_BB_COEX

57

BB_TO_AP_COEX

57

GND

57

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94

J_INT_BOT

SYM 1 OF 2

1

IO1

2

IO2

3

IO3

4

IO4

5

IO5

6

IO6

7

IO7

8

IO8

9

IO9
IO10
IO11
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO22
IO23
IO24
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
IO33
IO34
IO35
IO36
IO37
IO38
IO39
IO40
IO41
IO42
IO43
IO44
IO45
IO46
IO47
IO48
IO49
IO50
IO51
IO52
IO53
IO54
IO55
IO56
IO57
IO58
IO59
IO60
IO61
IO62
IO63
IO64
IO65
IO66
IO67
IO68
IO69
IO70
IO71
IO72
IO73
IO74
IO75
IO76
IO77
IO78
IO79
IO80
IO81
IO82
IO83
IO84
IO85
IO86
IO87
IO88
IO89
IO90
IO91
IO92
IO93
IO94

Bot Board Interposer APN:998-12514

SMT-PAD

95

IO95

96

IO96

97

IO97

98

IO98

99

IO99
IO100
IO101
IO102
IO103
IO104
IO105
IO106

INTERPOSER-MLB-BOT-V3-D32

IO107
IO108
IO109
IO110
IO111
IO112
IO113
IO114
IO115
IO116
IO117
IO118
IO119
IO120
IO121
IO122
IO123
IO124
IO125
IO126
IO127
IO128
IO129
IO130
IO131
IO132
IO133
IO134
IO135
IO136
IO137
IO138
IO139
IO140
IO141
IO142
IO143
IO144
IO145
IO146
IO147
IO148
IO149
IO150
IO151
IO152
IO153
IO154
IO155
IO156
IO157
IO158
IO159
IO160
IO161
IO162
IO163
IO164
IO165
IO166
IO167
IO168
IO169
IO170
IO171
IO172
IO173
IO174
IO175
IO176
IO177
IO178
IO179
IO180
IO181
IO182
IO183
IO184
IO185
IO186
IO187
IO188

100
101
102
103
104
105
106
107
108
109
110

AP_TO_BB_PEAK_POWER_INDICATOR

111
112
113
114
115
116
117
118
119
120
121
122

90_PCIE_AP_TO_BB_REFCLK_P

123

90_PCIE_AP_TO_BB_REFCLK_N

124
125
126
127
128
129
130
131
132
133
134
135
136

BB_TO_AP_PEAK_POWER_INDICATOR

137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166

PCIE_WLAN_BI_AP_CLKREQ_L

167
168
169

BB_TO_PMU_PCIE_HOST_WAKE_L

170
171
172
173
174
175
176
177
178

TOUCH_TO_MANY_FORCE_PWM

179
180
181
182
183
184
185
186
187
188

AP_TO_NFC_DEV_WAKE

AP_TO_NFC_FW_DWLD_REQ

PMU_TO_NFC_VDD_MAIN_EN

UART_AOP_TO_BB_TXD

UART_AP_TO_GNSS_TXD

AP_TO_BB_COREDUMP_TRIG

UART_AP_TO_NFC_TXD
UART_NFC_TO_AP_RXD

BB_TO_AP_RESET_DETECT_L

AP_TO_GNSS_TIME_MARK

NC_INTERPOSER_109

AP_TO_BBPMU_RADIO_ON_L

90_PCIE_BB_TO_AP_RXD_N
90_PCIE_BB_TO_AP_RXD_P

90_PCIE_AP_TO_BB_TXD_N
90_PCIE_AP_TO_BB_TXD_P

UART_BB_TO_AOP_RXD

UART_GNSS_TO_AP_RXD

PCIE_AP_TO_BB_PERST_L

UART_NFC_TO_AP_CTS_L

UART_AP_TO_NFC_RTS_L

PCIE_BB_BI_AP_CLKREQ_L

PMU_TO_BBPMU_RESET_L

PMU_TO_TOUCH_CLK32K

WLAN_TO_PMU_HOST_WAKE

PMU_TO_WLAN_CLK32K

NFC_TO_AOP_HOST_WAKE

UART_AP_TO_BT_TXD

UART_AP_TO_BT_RTS_L

GND

GND

GND

BOARD_ID2

PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN

GND

GND

GND

GND

GND

PMU_AMUX_BY
PMU_AMUX_AY

GND

NC_INT_135

GND
PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

PP_VDD_MAIN
PP_VDD_MAIN

GND

PP_VDD_MAIN
PP_VDD_MAIN

GND

PMU_TO_NFC_EN

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

57

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

58

GND

58

GND

58

GND

58

GND

58

AP_CANARY2

58

GND

58

GND

58

PP1V8_NFC_S2

58

PMU_TO_GNSS_EN

58

PMU_TO_BT_REG_ON

58

GND

58

90_PCIE_AP_TO_WLAN_REFCLK_N

58

90_PCIE_AP_TO_WLAN_REFCLK_P

58

GND

58

90_PCIE_AP_TO_WLAN_TXD_P

58

90_PCIE_AP_TO_WLAN_TXD_N

58

GND

58

90_PCIE_WLAN_TO_AP_RXD_N

58

90_PCIE_WLAN_TO_AP_RXD_P

58

GND

58

PP3V0_S2

58

PP1V8_TOUCH_RACER_S2

58

PP1V8_TOUCH_RACER_S2

58

PMU_TO_WLAN_REG_ON

58

RADIO_PA_NTC

58

BT_TO_AP_TIME_SYNC

58

UART_BT_TO_AP_RXD

58

GND

58

GND

58

UART_BT_TO_AP_CTS_L

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

PP_VBUS1_E75

58

GND

58

PP_GPU_LVCC

58

GND

58

PP_CPU_PCORE_LVCC

58

GND

58

PP_BATT_VCC

58

PP_BATT_VCC

58

GND

58

AP_TO_BT_DEVICE_WAKE

58

AOP_TO_WLAN_CONTEXT_A

58

UART_AOP_TO_RACER_TXD

58

SWD_AOP_TO_MANY_SWCLK

58

SPI_AP_TO_RACER_MOSI

58

SPI_AP_TO_RACER_SCLK

58

PP1V1_RACER_S2

58

PP1V1_RACER_S2

58

PP1V1_RACER_S2

58

AP_TO_RACER_REF_CLK

58

GND

58

AOP_TO_BBPMU_COEX

58

PP_VBUS2_IKTARA

58

PP_VBUS2_IKTARA

58

PP_VBUS2_IKTARA

58

PP_VBUS2_IKTARA

58

GND

58

AOP_TO_WLAN_CONTEXT_B

58

GND

58

UART_RACER_TO_AOP_RXD

58

GND

58

SPI_RACER_TO_AP_MISO

58

GND

58

SPI_AP_TO_RACER_CS_L

58

GND

58

PMU_TO_IKTARA_RESET_L

58

GND

58

SWD_AOP_BI_RACER_SWDIO

58

GND

58

I2C3_AP_SDA

58

GND

58

I2C3_AP_SCL

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

GND

58

189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281

J_INT_BOT

SMT-PAD

SYM 2 OF 2

IO189
IO190
IO191
IO192
IO193
IO194
IO195
IO196
IO197
IO198
IO199
IO200
IO201
IO202
IO203
IO204
IO205
IO206
IO207
IO208
IO209
IO210
IO211
IO212
IO213
IO214
IO215
IO216
IO217
IO218
IO219
IO220
IO221
IO222
IO223
IO224
IO225
IO226
IO227
IO228
IO229
IO230
IO231
IO232
IO233
IO234
IO235
IO236
IO237
IO238
IO239
IO240
IO241
IO242
IO243
IO244
IO245
IO246
IO247
IO248
IO249
IO250
IO251
IO252
IO253
IO254
IO255
IO256
IO257
IO258
IO259
IO260
IO261
IO262
IO263
IO264
IO265
IO266
IO267
IO268
IO269
IO270
IO271
IO272
IO273
IO274
IO275
IO276
IO277
IO278
IO279
IO280
IO281

INTERPOSER-MLB-BOT-V3-D32

IO282
IO283
IO284
IO285
IO286
IO287
IO288
IO289
IO290
IO291
IO292
IO293
IO294
IO295
IO296
IO297
IO298
IO299
IO300
IO301
IO302
IO303
IO304
IO305
IO306
IO307
IO308
IO309
IO310
IO311
IO312
IO313
IO314
IO315
IO316
IO317
IO318
IO319
IO320
IO321
IO322
IO323
IO324
IO325
IO326
IO327
IO328
IO329
IO330
IO331
IO332
IO333
IO334
IO335
IO336
IO337
IO338
IO339
IO340
IO341
IO342
IO343
IO344
IO345
IO346
IO347
IO348
IO349
IO350
IO351
IO352
IO353
IO354
IO355
IO356
IO357
IO358

282
283
284
285
286
287

ACORN_GECKO_ANSEL_TO_PMU_ADC

288
289

RACER_TO_AOP_INT_L

290
291

HALL_CASE_TO_AOP_SOUTH_L

292
293

PMU_TO_IKTARA_EN_EXT_1V8

294
295

IKTARA_TO_SMC_INT

296
297
298

I2C0_SMC_SCL
I2C0_SMC_SDA

299
300
301
302
303
304
305
306
307

IKTARA_COIL2
IKTARA_COIL2
IKTARA_COIL2
IKTARA_COIL2
IKTARA_COIL1
IKTARA_COIL1
IKTARA_COIL1
IKTARA_COIL1

308
309

NC_INTERPOSER_309

310
311

NC_INTERPOSER_311

312
313

AP_CANARY1

314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358

GND
GND
GND
GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

58

58

58

58

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

60

PAGE TITLE

B2B: Interposer Bot

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

65 OF 85

SHEET

51 OF 60

SYNC_DATE=08/30/2017

SIZE

D

D

C

B

A

8

67

35 4

2

1

AP I2C0

VIETMOBILE.VN

678

3 245

1

D

36 34 32 31 30 29 20 19 17 6

53 52 44 37

11

11

PP1V8_IO

R6600

ROOM=SOC

I2C0_AP_SCL
I2C0_AP_SDA

2.2K

5%

1/32W

MF

01005

1

2

R6601

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

AP I2C

2

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2C0_AP_SCL
I2C0_AP_SDA

I2C0_AP_SCL
I2C0_AP_SDA

I2C0_AP_SCL
I2C0_AP_SDA

OUT

OUT

OUT

47

47

BI

50

50

BI

24

24

BI

Bus Name

Bus Voltage

AP I2C0 PP1V8_IO

Bus Speed Device

GECKO

SAKONNET

400 kHz

BOOST

ARC EEPROM

7-Bit Addr.

0x52
0x08
0x75
0x50

Binary
1010 010X
0001 000X
1110 101X
1010 000X

8-Bit Addr.
0xA4, 0xA5
0x10, 0x11
0xEA, 0xEB
0xA0, 0xA1

Min Speed Max Speed

-

-

-

-

1 MHz

1 MHz
400 KHz
400 KHz

Location

TOP MLB

Dock Flex

TOP MLB

Dock Flex

D

C

36 34 32 31 30 29 20 19 17 6

53 52 44 37

11

11

AP I2C1

PP1V8_IO

R6610

2.2K

1/32W
01005

ROOM=SOC

I2C1_AP_SCL
I2C1_AP_SDA

5%
MF

1

2

R6611

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

Bus Name

2

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2C1_AP_SCL
I2C1_AP_SDA

OUT

35

35

BI

AP I2C1

Bus Voltage

PP1V8_IO

Bus Speed

100 kHz

Device

MIC2

7-Bit Addr.

0x56

Binary

1010 100X

8-Bit Addr.
0xA8, 0xA9

Min Speed

-

Max Speed Location

1 MHz

Strobe Flex

C

B

36 34 32 31 30 29 20 19 17 6

53 52 44 37

11

11

AP I2C2

PP1V8_IO

R6620

ROOM=SOC

I2C2_AP_SCL
I2C2_AP_SDA

AP I2C3

5%

1/32W

MF

01005

1

2

R6621

4.7K4.7K

5%

1/32W

MF

01005

ROOM=SOC

1

Bus Voltage

7-Bit Addr.DeviceBus Name

Top Speaker Amp

2

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2C2_AP_SCL
I2C2_AP_SDA

OUT

42

42

BI

AP I2C2

PP1V8_IO

1 MHz

Binary

1000 000X0x40

8-Bit Addr.
0x80, 0x81

Min Speed

-

Max SpeedBus Speed

1 MHz

Location

Top MLB

B

36 34 32 31 30 29 20 19 17 6

53 52 44 37

58 11

58 11

PP1V8_IO

R6630

I2C3_AP_SCL
I2C3_AP_SDA

AP I2C4

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R6631

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

Bus Name

2

MAKE_BASE=TRUE
MAKE_BASE=TRUE

Acorn and Touch EEPROM Live on Bottom Board

AP I2C3 PP1V8_IO

Bus Voltage

Bus Speed Device

ACORN

TOUCH EEPROM

400 kHz

7-Bit Addr. Binary

0X2A

0x51

0101 010X
1010 001X 0xA2, 0xA3

8-Bit Addr.
0x54, 0x55

Min Speed

-

-

Max Speed

1 MHz
1 MHz

Location

Bot MLB

Touch Flex

36 34 32 31 30 29 20 19 17 6

53 52 44 37

A

8

PP1V8_IO

I2C4_AP_SCL

11

I2C4_AP_SDA

11

R6670

4.7K

5%

1/32W

MF

ROOM=SOC

1

2

R6671

4.7K

5%

1/32W

MF

0100501005

ROOM=SOC

1

2

MAKE_BASE=TRUE
MAKE_BASE=TRUE

67

I2C4_AP_SCL
I2C4_AP_SDA

OUT

Bus SpeedBus VoltageBus Name

Device

LYNX

7-Bit Addr.

0X71

Location

Top MLB

A

PAGE TITLE

SYSTEM: AP I2C

DRAWING NUMBER

11

11

BI

AP I2C4

PP1V8_IO

400 kHz

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

051-02545

REVISION

7.0.0

BRANCH

PAGE

66 OF 85

SHEET

52 OF 60

1

SIZE

D

ISP I2C0

VIETMOBILE.VN

678

3 245

1

D

36 34 32 31 30 29 20 19 17 6

53 52 44 37

PP1V8_IO

I2C0_ISP_SCL

9

I2C0_ISP_SDA

9

1

R6701

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R6702

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

MAKE_BASE=TRUE
MAKE_BASE=TRUE

ISP I2C

Bus Voltage

I2C0_ISP_SCL
I2C0_ISP_SDA

OUT

BI

Bus Name

31

31

ISP I2C0 PP1V8_IO

Bus Speed

1 MHz

Device 7-Bit Addr. 8-Bit Addr.

Austin

Raman

0X10
0X3C

Binary
0010 000X
0111 100X

0x20, 0x21
0x78, 0x79

Min Speed

-

-

Max Speed Location

1 MHz
1 MHz

Wide Cam
Wide Cam

D

C

36 34 32 31 30 29 20 19 17 6

53 52 44 37

ISP I2C1

PP1V8_IO

I2C1_ISP_SCL

9

I2C1_ISP_SDA

9

1

R6711

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R6712

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2C1_ISP_SCL
I2C1_ISP_SDA

OUT

BI

32

32

Bus Name Bus Voltage Bus Speed

ISP I2C1 PP1V8_IO 1 MHz

Device

Billings

Grunberg+

7-Bit Addr.

0x20 0100 000X
0x1C

0011 100X

Binary

8-Bit Addr. Min Speed
0x40, 0x41
0x38, 0x39

-

- 1 MHz

Max Speed Location

1 MHz Tele Cam

Tele Cam

C

B

36 34 32 31 30 29 20 19 17 6

36 34 32 31 30 29 20 19 17 6

53 52 44 37

53 52 44 37

ISP I2C2

PP1V8_IO

I2C2_ISP_SCL

9

I2C2_ISP_SDA

9

ISP I2C3

PP1V8_IO

1

R6721

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R6731

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R6722

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R6732

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2C2_ISP_SCL
I2C2_ISP_SDA

I2C2_ISP_SCL
I2C2_ISP_SDA

OUT

BI

OUT

BI

34

34

37

37

Bus Name

ISP I2C2

Bus Voltage

PP1V8_IO

Bus Speed

1 MHz

Device Binary 8-Bit Addr.

Yonkers

Flatiron

Savage

7-Bit Addr.

0x10
0x70
0x18

0010 000X
1110 000X
0011 000X

0x20, 0x21
0xE0, 0xE1
0x30, 0x31

Min Speed

-

-

-

Max Speed

1 MHz
1 MHz

Location

Fcam

Fcam

1 MHz Juliet Flex

B

A

I2C3_ISP_SCL

9

I2C3_ISP_SDA

9

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2C3_ISP_SCL
I2C3_ISP_SDA

I2C3_ISP_SCL
I2C3_ISP_SDA

I2C3_ISP_SCL
I2C3_ISP_SDA

I2C3_ISP_SCL
I2C3_ISP_SDA

I2C3_ISP_SCL
I2C3_ISP_SDA

OUT

BI

OUT

BI

OUT

BI

OUT

BI

OUT

BI

30

30

33

33

33

33

36

36

37

37

Bus Name

ISP I2C3

PP1V8_IO

Bus SpeedBus Voltage

1 MHz

Device

Ansel

Neon
Neon

Rigel

7-Bit Addr.

0x40
0x63
0x67
0x55

Binary

1000 000X
1100 011X
1100 111X

8-Bit Addr.
0x80, 0x81
0xC6, 0xC7
0xCE, 0xCF
0xAA, 0xAB1100 011X

Mama Bear 0x50 1010 000X 0xA0, 0xA1

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Max Speed

-

- Top Board

1 MHz Top Board
1 MHz
1 MHz-

- 1 MHz Top Board
1 MHz- Romeo Flex

SYSTEM: ISP I2C

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

LocationMin Speed

Top Board

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

PAGE

67 OF 85

SHEET

53 OF 60

A

SIZE

D

8

67

35 4

2

1

876543

VIETMOBILE.VN

2 1

D

40 38 25 20 17
50 49 48 42 41

59 54

13

13

PP1V8_S2

I2C0_AOP_SCL
I2C0_AOP_SDA

50 28 27 20

PP1V8_IMU_S2

AOP I2C0

1

R6820

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

AOP I2C1

1

R6821

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

MAKE_BASE=TRUE
MAKE_BASE=TRUE

AOP/SMC I2C

DeviceBus Speed
Doppler

Blackbird

I2C0_AOP_SCL
I2C0_AOP_SDA

OUT

BI

38

38

Bus Name

AOP I2C0

Bus Voltage

PP1V8_S2

750 kHz

Yogi

7-Bit Addr.

0x58
0x29
0x33

Binary
1011 000X
0101 001X
0110 011X

8-Bit Addr.
0xB0, 0xB1
0x52, 0x53
0x66, 0x67

-

-

-

Max SpeedMin Speed

1 MHz

1 MHz

1 MHz

D

Location
Sensor Flex
Sensor Flex
Sensor Flex

C

I2C1_AOP_SCL_SOC

13

I2C1_AOP_SDA

13

SMC I2C0

1

R6822

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R6823

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

R6824

0.00

1/32W

ROOM=B2B_PEARL

01005

0%
MF

21

I2C1_AOP_SCL

MAKE_BASE=TRUE

MAKE_BASE=TRUE

I2C1_AOP_SCL
I2C1_AOP_SDA

I2C1_AOP_SCL
I2C1_AOP_SDA

I2C1_AOP_SCL
I2C1_AOP_SDA

I2C1_AOP_SCL
I2C1_AOP_SDA

OUT

BI

OUT

BI

OUT

BI

OUT

BI

43

43

41

41

27

27

50

50

AOP I2C1

Bus Voltage

Bus Speed

Device

Arc

Bottom Speaker

PP1V8_IMU_S2 0x1C, 0x1D

400 kHz

Moly

Potassium

7-Bit Addr.

0x42
0x40
0x0E
0x76

Binary
1000 001X
1000 000X 1 MHz

8-Bit Addr.
0x82, 0x83

0x80, 0x81
0001 110X
1110 110X 0xEC, 0xED

Min Speed

-

-

-

-

Max Speed

1 MHz

1 MHz
1 MHz

LocationBus Name
Top Board
Top Board

Button Cyclone

Dock Flex

C

B

40 38 25 20 17
50 49 48 42 41

59 54

60 11

60 11

PP1V8_S2

I2C0_SMC_SCL
I2C0_SMC_SDA

R6840

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

R6841

2

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2C0_SMC_SCL
I2C0_SMC_SDA

I2C0_SMC_SCL
I2C0_SMC_SDA

I2C0_SMC_SCL
I2C0_SMC_SDA

I2C0_SMC_SCL
I2C0_SMC_SDA

OUT

BI

OUT

BI

OUT

BI

25

25

26

26

48

48

Bus Name

SMC I2C0

Bus Voltage

Bus Speed

400 kHz

Yangtze

Iktara

CCG2PP1V8_S2

Gas Guage

Roswell

7-Bit Addr.Device

0x71
0x39
0x12
0x55

Binary
1110 001X
0111 001X
0010 010X
0010 010X
0100 000X

8-Bit Addr.
0xE2, 0xE3
0x72, 0x73
0x24, 0x25
0xAA, 0xAB
0x20, 0x210x10

Min Speed

-

-

-

-

Max Speed

400 KHz

400 KHz

1 MHz
1 MHz -

400 KHz

Location
Top Board
Bot Board
Top Board

BMU Flex
BMU Flex

B

A

40 38 25 20 17
50 49 48 42 41

59 54

11

11

PP1V8_S2

I2C1_SMC_SCL
I2C1_SMC_SDA

SMC I2C1

1

R6850

2.2K

5%

1/32W

MF

01005

ROOM=SOC

R6851

2

2.2K

ROOM=SOC

5%

1/32W

MF

01005

Lives on bottom board

1

2

A

MAKE_BASE=TRUE
MAKE_BASE=TRUE

I2C1_SMC_SCL
I2C1_SMC_SDA

OUT

BI

Bus Name

49

49

Bus Voltage

Bus Speed Min Speed

Device Binary 8-Bit Addr.

Hydra

7-Bit Addr. Location

-

-

Max Speed

400 KHz

400 KHz0xE8, 0xE91110 100X0x74Denali

Top Board0x34, 0x350011 010X0x1A
Top Board

I2C1_SMC_SCL
I2C1_SMC_SDA

OUT

BI

23

23

SMC I2C1

PP1V8_S2

400 kHz

3

1245678

678

VIETMOBILE.VN

AP/PMU GPIOs

3 245

1

D

C

B

SOC

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

AP_TO_BB_PEAK_POWER_INDICATOR

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_17

GPIO_18

GPIO_19

BB_TO_AP_PEAK_POWER_INDICATOR

GPIO_20

GPIO_21

GPIO_22

GPIO_23

GPIO_24

GPIO_25

GPIO_26

GPIO_27

AP_TO_BT_DEVICE_WAKE

12

12

12

12

AP_TO_PMU_AMUX_SYNC

12

12

12

PMU_TO_AP_BUTTON_VOL_UP_L

12

12

AP_TO_BBPMU_RADIO_ON_L

12

AP_TO_SPKRAMP_TOP_RESET_L

12

AP_TO_NFC_FW_DWLD_REQ

12

12

AP_TO_NFC_DEV_WAKE

12

CAMPMU_TO_AP_IRQ_L

12

AP_TO_GNSS_TIME_MARK

12

SPKRAMP_TOP_TO_AP_INT_L

12

12

BT_TO_AP_TIME_SYNC

12

12

12

BB_TO_AP_RESET_DETECT_L

12

AP_TO_BB_COREDUMP_TRIG

12

12

12

DISPLAY_TO_AP_PANEL_ID

12

12

12

AP_TO_BB_RESET_L

AP_TO_CAMPMU_RESET_L

BOARD_REV0

BOARD_REV1

BOARD_REV2

BOARD_REV3

AP_CANARY1

NC_AP_GPIO8

BB_TO_AP_COEX

AP_TO_BB_COEX

AP_CANARY2

NC_AP_GPIO27

AP_TO_BT_DEVICE_WAKE

MAKE_BASE=TRUE

BOARD_REV0

MAKE_BASE=TRUE

BOARD_REV1

MAKE_BASE=TRUE

BOARD_REV2

MAKE_BASE=TRUE

AP_TO_PMU_AMUX_SYNC

MAKE_BASE=TRUE

BOARD_REV3

MAKE_BASE=TRUE

AP_CANARY1

MAKE_BASE=TRUE

PMU_TO_AP_BUTTON_VOL_UP_L

MAKE_BASE=TRUE

IN

IN

IN

IN

IN

IN

IN

OUT

NC_AP_GPIO8

MAKE_BASE=TRUE

AP_TO_BBPMU_RADIO_ON_L

MAKE_BASE=TRUE

AP_TO_SPKRAMP_TOP_RESET_L

MAKE_BASE=TRUE

AP_TO_NFC_FW_DWLD_REQ

MAKE_BASE=TRUE

AP_TO_BB_PEAK_POWER_INDICATOR

MAKE_BASE=TRUE

AP_TO_NFC_DEV_WAKE

MAKE_BASE=TRUE

CAMPMU_TO_AP_IRQ_L

MAKE_BASE=TRUE

AP_TO_GNSS_TIME_MARK

MAKE_BASE=TRUE

SPKRAMP_TOP_TO_AP_INT_L

MAKE_BASE=TRUE

BB_TO_AP_COEX

MAKE_BASE=TRUE

BT_TO_AP_TIME_SYNC

MAKE_BASE=TRUE

AP_TO_BB_RESET_L

MAKE_BASE=TRUE

BB_TO_AP_PEAK_POWER_INDICATOR

MAKE_BASE=TRUE

BB_TO_AP_RESET_DETECT_L

MAKE_BASE=TRUE

AP_TO_BB_COREDUMP_TRIG

MAKE_BASE=TRUE

AP_TO_CAMPMU_RESET_L

MAKE_BASE=TRUE

AP_TO_BB_COEX

MAKE_BASE=TRUE

DISPLAY_TO_AP_PANEL_ID

MAKE_BASE=TRUE

AP_CANARY2

MAKE_BASE=TRUE

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT

NC_AP_GPIO27

MAKE_BASE=TRUE

58

6

6

6

23

6

60

23

57

42

57

57

57

30

57

42

57

58

57

57

57

57

57

44

58

D

GPIO_1

PMU_TO_AP_THROTTLE_GPU1_L

GPIO_2

GPIO_3

GPIO_4

BB_TO_PMU_PCIE_HOST_WAKE_L

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_13

PMU

Held Through 1 Reset

Sequenced GPIOs

57 30

GPIO_14

GPIO_15

IRQ GPIO_16

PMU_TO_NAND_LOW_BATT_BOOT_L

GPIO_17

GPIO_18

GPIO_19

GPIO_20

GPIO_21

GPIO_22

GPIO_23

GPIO_24

GPIO_25

PMU_TO_IKTARA_EN_EXT_1V8

PMU_TO_CCG2_RESET_L

23

23

NC_BT_TO_PMU_HOST_WAKE

23

WLAN_TO_PMU_HOST_WAKE

23

23

PMU_NFC_TO_ARC_RESET_L

23

23

23

23

23

YANGTZE_TO_PMU_INT_L

23

23

PMU_MASK_NFC_TO_ARC_TRIG

23

23

PMU_TO_NFC_VDD_MAIN_EN

23

23

23

PMU_TO_DISPLAY_RESET_L

23

PMU_TO_BBPMU_RESET_R_L

23

23

23

23

23

PMU_TO_DISPLAY_PANICB

23

PMU_TO_DISPLAY_LDO_EN

23

PMU_TO_GNSS_EN

PMU_TO_WLAN_CLK32K

PMU_TO_BT_REG_ON

PMU_TO_PHALANX2

CODEC_TO_PMU_WAKE_L

PMU_TO_WLAN_REG_ON

PMU_TO_PHALANX1

PMU_TO_NFC_EN

NC_PMU_GPIO21

PMU_TO_BOOST_EN

PMU_TO_AP_THROTTLE_GPU1_L

BB_TO_PMU_PCIE_HOST_WAKE_L

PMU_MASK_NFC_TO_ARC_TRIG

PMU_TO_NAND_LOW_BATT_BOOT_L

PMU_TO_IKTARA_EN_EXT_1V8

PMU_TO_CCG2_RESET_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

OUT

OUT

NC_BT_TO_PMU_HOST_WAKE

MAKE_BASE=TRUE

WLAN_TO_PMU_HOST_WAKE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PMU_NFC_TO_ARC_RESET_L

MAKE_BASE=TRUE

PMU_TO_GNSS_EN

MAKE_BASE=TRUE

PMU_TO_WLAN_CLK32K

MAKE_BASE=TRUE

PMU_TO_BT_REG_ON

MAKE_BASE=TRUE

PMU_TO_PHALANX2

MAKE_BASE=TRUE

YANGTZE_TO_PMU_INT_L

MAKE_BASE=TRUE

CODEC_TO_PMU_WAKE_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PMU_TO_WLAN_REG_ON

MAKE_BASE=TRUE

PMU_TO_NFC_VDD_MAIN_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PMU_TO_PHALANX1

MAKE_BASE=TRUE

PMU_TO_DISPLAY_RESET_L

MAKE_BASE=TRUE

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

PMU_TO_BBPMU_RESET_R_L

MAKE_BASE=TRUE

PMU_TO_NFC_EN

MAKE_BASE=TRUE

NC_PMU_GPIO21

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PMU_TO_BOOST_EN

MAKE_BASE=TRUE

PMU_TO_DISPLAY_PANICB

MAKE_BASE=TRUE

PMU_TO_DISPLAY_LDO_EN

MAKE_BASE=TRUE

OUT

OUT

OUT

OUT

IN

48

7

58

58

43

58

58

50

26

40

43

58

57

19

50

44

58

60

24

44

44

58 23

C

GPIO16 is the only PIN capable of nIRQ

R3070

1.00K

5%

1/32W

MF

01005

ROOM=PMU

21

PMU_TO_BBPMU_RESET_L

58

B

GPIO_28

GPIO_29

GPIO_30

12

AP_TO_RACER_RESET_L

12

GNSS_TO_AP_LOW_PWR_IND

12

NC_AP_GPIO28

NC_AP_GPIO28

MAKE_BASE=TRUE

AP_TO_RACER_RESET_L

MAKE_BASE=TRUE

OUT

GNSS_TO_AP_LOW_PWR_IND

MAKE_BASE=TRUE

57

57

IN

A

8

67

SYNC_DATE=05/09/2017

PAGE TITLE

A

SYSTEM: SOC/PMU GPIOs

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

CDS_LIB=apple

BRANCH

PAGE

70 OF 85

SHEET

55 OF 60

1

SIZE

D

D

VIETMOBILE.VN

678

A0P GPIOs

3 245

1

D

C

SCM_SPI TRIGGER & CS >

AOP

SCM_I2CM0 TRIGGER --->

SCM_I2CM1 TRIGGER >

AOP_FUNC_0

AOP_FUNC_1

AOP_FUNC_2

AOP_FUNC_3

AOP_FUNC_4

AOP_FUNC_5

AOP_FUNC_6

AOP_FUNC_7

AOP_FUNC_8

AOP_FUNC_9

AOP_FUNC_10

AOP_FUNC_11

AOP_FUNC_12

AOP_FUNC_13

AOP_FUNC_14

AOP_FUNC_15

AOP_FUNC_16

AOP_FUNC_17

AOP_FUNC_18

AOP_FUNC_19

AOP_FUNC_20

AOP_FUNC_21

AOP_FUNC_22

SPKAMP_BOT_ARC_TO_AOP_INT_L

IMU_TO_AOP_DATARDY

13

SPI_AOP_TO_IMU_CS_L

13

AOP_TO_SPKAMP_BOT_RESET_L

13

SPI_AOP_TO_PHOSPHORUS_CS_L

13

PHOSPHORUS_TO_AOP_INT

13

ROMEO_TO_AOP_B2B_DETECT

13

RACER_TO_AOP_INT_L

13

AOP_TO_CODEC_RESET_L

13

13

13

13

13

13

AOP_TO_CODEC_CLP_EN

13

AOP_TO_BBPMU_COEX

13

PROX_BI_AOP_INT_L

13

POTASSIUM_TO_AOP_INT

13

HALL_CASE_TO_AOP_SOUTH_L

13

13

NFC_TO_AOP_HOST_WAKE

13

COMPASS_TO_AOP_INT

13

HALL_FLAP_TO_AOP_IRQ_L

13

13

NC_AOP_FUNC8

IMU_TO_AOP_INT

NC_AOP_FUNC10

NC_AOP_FUNC11

NC_AOP_FUNC12

ALS_TO_AOP_INT_L

IMU_TO_AOP_DATARDY

MAKE_BASE=TRUE

SPI_AOP_TO_IMU_CS_L

MAKE_BASE=TRUE

AOP_TO_SPKAMP_BOT_RESET_L

MAKE_BASE=TRUE

SPI_AOP_TO_PHOSPHORUS_CS_L

MAKE_BASE=TRUE

OUT

OUT

OUT

PHOSPHORUS_TO_AOP_INT

MAKE_BASE=TRUE

ROMEO_TO_AOP_B2B_DETECT

MAKE_BASE=TRUE

RACER_TO_AOP_INT_L

MAKE_BASE=TRUE

AOP_TO_CODEC_RESET_L

MAKE_BASE=TRUE

OUT

NC_AOP_FUNC8

MAKE_BASE=TRUE

IMU_TO_AOP_INT

MAKE_BASE=TRUE

NC_AOP_FUNC10

MAKE_BASE=TRUE

NC_AOP_FUNC11

MAKE_BASE=TRUE

NC_AOP_FUNC12

MAKE_BASE=TRUE

AOP_TO_CODEC_CLP_EN

MAKE_BASE=TRUE

OUT

AOP_TO_BBPMU_COEX

MAKE_BASE=TRUE

PROX_BI_AOP_INT_L

MAKE_BASE=TRUE

POTASSIUM_TO_AOP_INT

MAKE_BASE=TRUE

HALL_CASE_TO_AOP_SOUTH_L

MAKE_BASE=TRUE

ALS_TO_AOP_INT_L

MAKE_BASE=TRUE

NFC_TO_AOP_HOST_WAKE

MAKE_BASE=TRUE

COMPASS_TO_AOP_INT

MAKE_BASE=TRUE

HALL_FLAP_TO_AOP_IRQ_L

MAKE_BASE=TRUE

SPKAMP_BOT_ARC_TO_AOP_INT_L

MAKE_BASE=TRUE

28 5

IN

28

41

28

28 5

IN

37

IN

60

IN

40

28

IN

C

40

58

IN

38

IN

50

IN

60

IN

38

IN

58

IN

27 5

IN

38

IN

IN

43 41 5

B

HALL_CASE_TO_AOP_NORTH_L

13

13

13

GECKO_TO_AOP_IRQ_L

AOP_TO_GECKO_RESET_L

13

AOP_TO_HALOGEN_AFE_EN

HALL_CASE_TO_AOP_NORTH_L

MAKE_BASE=TRUE

GECKO_TO_AOP_IRQ_L

MAKE_BASE=TRUE

AOP_TO_GECKO_RESET_L

MAKE_BASE=TRUE

AOP_TO_HALOGEN_AFE_EN

MAKE_BASE=TRUE

OUT

57

IN

B

47 5

IN

47

IN

46

A

8

67

SYNC_DATE=05/09/2017

PAGE TITLE

A

SYSTEM: AOP GPIOs

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

CDS_LIB=apple

BRANCH

PAGE

71 OF 85

SHEET

56 OF 60

1

SIZE

D

678

VIETMOBILE.VN

Interposer Aliases: Pins 1-144

3 245

1

D

C

B

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

PMU_TO_SYSTEM_COLD_RESET_L

51

GND

51

AP_TO_CAMPMU_RESET_L

51

GND

51

BB_TO_MANY_GSM_BURST_IND

51

GND

51

HALL_CASE_TO_AOP_NORTH_L

51

GND

51

AP_TO_TOUCH_SCAN_CLK

51

GND

51

I2S_BB_TO_AP_BCLK

51

GND

51

I2S_BB_TO_AP_DIN

51

GND

51

I2S_AP_TO_BB_DOUT

51

GND

51

I2S_BB_TO_AP_LRCLK

51

GND

51

PP1V8_ALWAYS

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

NFC_TO_ARC_RESET_L

51

GND

51

NFC_TO_ARC_TRIG

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

GND

51

AP_TO_BB_RESET_L

51

GND

51

SWD_AOP_BI_BB_SWDIO

51

GND

51

UART_GNSS_TO_AP_CTS_L

51

GND

51

UART_AP_TO_GNSS_RTS_L

51

GND

51

THIS SIDE HAS ATTRIBUTE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

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GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

59

GND

59

GND

59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

GND

59

GND

57 59

GND

57 59

GND

57 59

GND

57 59

PMU_TO_SYSTEM_COLD_RESET_L

AP_TO_CAMPMU_RESET_L

BB_TO_MANY_GSM_BURST_IND

HALL_CASE_TO_AOP_NORTH_L

AP_TO_TOUCH_SCAN_CLK

I2S_BB_TO_AP_BCLK

I2S_BB_TO_AP_DIN

I2S_AP_TO_BB_DOUT

I2S_BB_TO_AP_LRCLK

NFC_TO_ARC_RESET_L

NFC_TO_ARC_TRIG

AP_TO_BB_RESET_L

SWD_AOP_BI_BB_SWDIO

UART_GNSS_TO_AP_CTS_L

UART_AP_TO_GNSS_RTS_L

PP1V8_ALWAYS

56

9

11

11

11

11

55

13

12

12

D

THIS SIDE HAS ATTRIBUTE

MAKE_BASE=TRUE

PCIE_AP_TO_WLAN_PERST_L

51

51

51

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51

23 15 7

55 30

38 33

26 23 22 17

43 5

43 5

51

51

51

51

51

51

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51

51

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51

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51

51

AP_TO_BB_PEAK_POWER_INDICATOR

51

51

51

51

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51

51

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51

51

90_PCIE_AP_TO_BB_REFCLK_P

51

90_PCIE_AP_TO_BB_REFCLK_N

51

51

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51

51

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51

51

51

51

51

51

BB_TO_AP_PEAK_POWER_INDICATOR

51

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51

51

51

51

51

AP_TO_RACER_RESET_L

AP_TO_WLAN_TIME_SYNC

GNSS_TO_AP_LOW_PWR_IND

HYDRA_TO_AP_FORCE_DFU

INTERPOSER_PIN_90

AP_TO_BB_COEX
BB_TO_AP_COEX

AP_TO_NFC_DEV_WAKE

AP_TO_NFC_FW_DWLD_REQ

PMU_TO_NFC_VDD_MAIN_EN

UART_AOP_TO_BB_TXD

UART_AP_TO_GNSS_TXD

AP_TO_BB_COREDUMP_TRIG

UART_AP_TO_NFC_TXD
UART_NFC_TO_AP_RXD

BB_TO_AP_RESET_DETECT_L

BOARD_ID2

AP_TO_GNSS_TIME_MARK

NC_INTERPOSER_109

AP_TO_BBPMU_RADIO_ON_L

PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN

90_PCIE_BB_TO_AP_RXD_N
90_PCIE_BB_TO_AP_RXD_P

90_PCIE_AP_TO_BB_TXD_N
90_PCIE_AP_TO_BB_TXD_P

UART_BB_TO_AOP_RXD

UART_GNSS_TO_AP_RXD

PCIE_AP_TO_BB_PERST_L

UART_NFC_TO_AP_CTS_L

UART_AP_TO_NFC_RTS_L

PMU_AMUX_BY
PMU_AMUX_AY

PCIE_BB_BI_AP_CLKREQ_L

NC_INT_135

PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN

GND

GND

GND

GND

GND
PP1V8_S2
PP1V8_S2

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

MAKE_BASE=TRUE

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GND

GND

GND

GND

GND

GND
GND
GND
GND
GND

INTERPOSER_PIN_90

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND
GND
GND

57 59

57 59

57 59

57 59

57 59

57 59

59

59

59

57 58 59

59

59

59

59

59

AP_TO_BB_PEAK_POWER_INDICATOR

57 58 59

57 59

57 59

57 59

57 59

57 59

BB_TO_AP_PEAK_POWER_INDICATOR

57 59

57 58 59

57 58 59

57 58 59

57 58 59

PCIE_AP_TO_WLAN_PERST_L

AP_TO_RACER_RESET_L

AP_TO_WLAN_TIME_SYNC

GNSS_TO_AP_LOW_PWR_IND

8

55

12

55

HYDRA_TO_AP_FORCE_DFU

PP1V8_S2
PP1V8_S2

AP_TO_BB_COEX
BB_TO_AP_COEX

AP_TO_NFC_DEV_WAKE

AP_TO_NFC_FW_DWLD_REQ

PMU_TO_NFC_VDD_MAIN_EN

UART_AOP_TO_BB_TXD

UART_AP_TO_GNSS_TXD

AP_TO_BB_COREDUMP_TRIG

UART_AP_TO_NFC_TXD
UART_NFC_TO_AP_RXD

BB_TO_AP_RESET_DETECT_L

59

59

55

55

55

55

55

13

12

55

12

12

55

BOARD_ID2

AP_TO_GNSS_TIME_MARK

55

NC_INTERPOSER_109

55

AP_TO_BBPMU_RADIO_ON_L

PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN

90_PCIE_BB_TO_AP_RXD_N
90_PCIE_BB_TO_AP_RXD_P

90_PCIE_AP_TO_BB_TXD_N
90_PCIE_AP_TO_BB_TXD_P

90_PCIE_AP_TO_BB_REFCLK_P
90_PCIE_AP_TO_BB_REFCLK_N

UART_BB_TO_AOP_RXD

UART_GNSS_TO_AP_RXD

PCIE_AP_TO_BB_PERST_L

UART_NFC_TO_AP_CTS_L

UART_AP_TO_NFC_RTS_L

PMU_AMUX_BY
PMU_AMUX_AY

PCIE_BB_BI_AP_CLKREQ_L

55

59

59

59

17

17

17

17

8

8

13

12

8

12

12

23

23

8

NC_INT_135

55

PP_VDD_MAIN
PP_VDD_MAIN
PP_VDD_MAIN

59

59

59

49 12

C

12 6

B

A

8

67

SYNC_DATE=08/29/2017

PAGE TITLE

A

Interposer: Pins 1-144

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02545

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

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BRANCH

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BB_TO_PMU_PCIE_HOST_WAKE_L

51

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51

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51

90_PCIE_AP_TO_WLAN_REFCLK_N

51

90_PCIE_AP_TO_WLAN_REFCLK_P

51

51

51

51

51

51

51

51

51

51

51

51

51

51

51

PMU_TO_BBPMU_RESET_L

PMU_TO_TOUCH_CLK32K

PCIE_WLAN_BI_AP_CLKREQ_L

WLAN_TO_PMU_HOST_WAKE

PMU_TO_WLAN_CLK32K

NFC_TO_AOP_HOST_WAKE

TOUCH_TO_MANY_FORCE_PWM

UART_AP_TO_BT_TXD

UART_AP_TO_BT_RTS_L

90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_AP_TO_WLAN_TXD_N

90_PCIE_WLAN_TO_AP_RXD_N
90_PCIE_WLAN_TO_AP_RXD_P

PP1V8_TOUCH_RACER_S2
PP1V8_TOUCH_RACER_S2

PMU_TO_WLAN_REG_ON

BT_TO_AP_TIME_SYNC

UART_BT_TO_AP_RXD

PP_VDD_MAIN
PP_VDD_MAIN

PP_VDD_MAIN
PP_VDD_MAIN

PMU_TO_NFC_EN

AP_CANARY2

PP1V8_NFC_S2

PMU_TO_GNSS_EN

PMU_TO_BT_REG_ON

RADIO_PA_NTC

GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND

GND

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND

GND

GND

GND

GND

PP3V0_S2

THIS SIDE HAS ATTRIBUTE

MAKE_BASE=TRUE

GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND

GND

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND

GND

GND

GND

GND

57 58 59

57 58 59

57 59 60

57 58 59

57 58 59

57 58 59

57 58 59

57 58 59

57 58 59

57 58 59

57 58 59

57 58 59

PMU_TO_BBPMU_RESET_L

57 58 59

PMU_TO_TOUCH_CLK32K

57 58 59

PCIE_WLAN_BI_AP_CLKREQ_L

57 58 59

57 58 59

BB_TO_PMU_PCIE_HOST_WAKE_L

57 58 59

57 58 59

WLAN_TO_PMU_HOST_WAKE

57 58 59

PMU_TO_WLAN_CLK32K

57 58 59

NFC_TO_AOP_HOST_WAKE

57 58 59

TOUCH_TO_MANY_FORCE_PWM

57 58 59

UART_AP_TO_BT_TXD

57 58 59

UART_AP_TO_BT_RTS_L

57 58 59

57 58 59

57 58 59

57 58 59

57 58 59

57 58 59

57 58 59

59

59

59

55

59

58 59

PMU_TO_BT_REG_ON

58 59

90_PCIE_AP_TO_WLAN_REFCLK_N

90_PCIE_AP_TO_WLAN_REFCLK_P

58 59

90_PCIE_AP_TO_WLAN_TXD_P

90_PCIE_AP_TO_WLAN_TXD_N

58 59

90_PCIE_WLAN_TO_AP_RXD_N

90_PCIE_WLAN_TO_AP_RXD_P

58 59

PP1V8_TOUCH_RACER_S2
PP1V8_TOUCH_RACER_S2

PMU_TO_WLAN_REG_ON

BT_TO_AP_TIME_SYNC

UART_BT_TO_AP_RXD

MAKE_BASE=TRUE

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AP_CANARY2

PP_VDD_MAIN
PP_VDD_MAIN

PP_VDD_MAIN
PP_VDD_MAIN

PMU_TO_NFC_EN

PP1V8_NFC_S2

PMU_TO_GNSS_EN

PP3V0_S2

RADIO_PA_NTC

59

59

59

59

55

55

17

8

55

55

56

12

12

20

55

55

8

8

17

17

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17

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23

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12

D

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MAKE_BASE=TRUE

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51

51

51

51

51

51

51

51

51

51

51

51

UART_BT_TO_AP_CTS_L

PP_VBUS1_E75

PP_GPU_LVCC

PP_CPU_PCORE_LVCC

PP_BATT_VCC
PP_BATT_VCC

AP_TO_BT_DEVICE_WAKE
AOP_TO_WLAN_CONTEXT_A
UART_AOP_TO_RACER_TXD
SWD_AOP_TO_MANY_SWCLK

SPI_AP_TO_RACER_MOSI

SPI_AP_TO_RACER_SCLK

PP1V1_RACER_S2
PP1V1_RACER_S2
PP1V1_RACER_S2

AP_TO_RACER_REF_CLK

AOP_TO_BBPMU_COEX

PP_VBUS2_IKTARA
PP_VBUS2_IKTARA
PP_VBUS2_IKTARA
PP_VBUS2_IKTARA

AOP_TO_WLAN_CONTEXT_B

UART_RACER_TO_AOP_RXD

SPI_RACER_TO_AP_MISO

SPI_AP_TO_RACER_CS_L

PMU_TO_IKTARA_RESET_L

SWD_AOP_BI_RACER_SWDIO

I2C3_AP_SDA

I2C3_AP_SCL

GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

MAKE_BASE=TRUE

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GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

58 59

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58 59

58 59

58 59

58 59

58 59

58 59

58 59

58 59

UART_BT_TO_AP_CTS_L

12

PP_VBUS1_E75

PP_GPU_LVCC

PP_CPU_PCORE_LVCC

PP_BATT_VCC
PP_BATT_VCC

AP_TO_BT_DEVICE_WAKE
AOP_TO_WLAN_CONTEXT_A
UART_AOP_TO_RACER_TXD

5

5

59

59

55

13

13

SWD_AOP_TO_MANY_SWCLK

SPI_AP_TO_RACER_MOSI

SPI_AP_TO_RACER_SCLK

PP1V1_RACER_S2
PP1V1_RACER_S2
PP1V1_RACER_S2

AP_TO_RACER_REF_CLK

AOP_TO_BBPMU_COEX

PP_VBUS2_IKTARA
PP_VBUS2_IKTARA
PP_VBUS2_IKTARA
PP_VBUS2_IKTARA

AOP_TO_WLAN_CONTEXT_B

UART_RACER_TO_AOP_RXD

SPI_RACER_TO_AP_MISO

SPI_AP_TO_RACER_CS_L

11

11

59

59

59

17

56

59

59

59

59

13

13

11

11

PMU_TO_IKTARA_RESET_L

SWD_AOP_BI_RACER_SWDIO

I2C3_AP_SDA

I2C3_AP_SCL

13

CKPLUS_WAIVE=I2C_PULLUP

CKPLUS_WAIVE=I2C_PULLUP

50 26

C

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B

A

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67

SYNC_DATE=08/30/2017

PAGE TITLE

A

Interposer: Pins 145-285

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02545

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

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Interposer Top Level Aliases

3 245

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PP_VDD_MAIN

57

PP_VDD_MAIN

57

PP_VDD_MAIN

57

PP_VDD_MAIN

57

PP_VDD_MAIN

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PP_VDD_MAIN

58

PP_VDD_MAIN

58

PP_VDD_MAIN

58

PP_VDD_MAIN

57

PP_VDD_MAIN
PP_VDD_MAIN

57

PP_BATT_VCC

58

PP_BATT_VCC

58

PP1V1_RACER_S2

58

PP1V1_RACER_S2

58

PP1V1_RACER_S2

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PP_VDD_MAIN

MAKE_BASE=TRUE

PP_BATT_VCC

MAKE_BASE=TRUE

PP1V1_RACER_S2

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22

47 45 44 43 42 41

26 25

IKTARA_COIL1

60

IKTARA_COIL1

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IKTARA_COIL1

60

IKTARA_COIL2

60

IKTARA_COIL2

60

IKTARA_COIL2

60

IKTARA_COIL2

60

58

58

58

58

PP_VBUS2_IKTARA
PP_VBUS2_IKTARA
PP_VBUS2_IKTARA
PP_VBUS2_IKTARA

IKTARA_COIL1

36 33 29 26 24 22 17

IKTARA_COIL1

IKTARA_COIL2

PP_VBUS2_IKTARA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

D

27

27

26

C

PP1V8_S2

57

PP1V8_S2

57

PP_VDD_BOOST

PP_VDD_BOOST

PP1V8_S2

MAKE_BASE=TRUE

PP_VDD_BOOST

MAKE_BASE=TRUE

PP1V8_TOUCH_RACER_S2

58

54 50 49 48

42 41 40 38 25 20 17

PP1V8_TOUCH_RACER_S2

58

47 46 40 36 29 24 22 17

PP1V8_TOUCH_RACER_S2

MAKE_BASE=TRUE

20

C

B

A

Ground Aliases

57

57

57

58

60

57 58

57

57 58 60

58

58

57

57

57

57

57

57

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57

57

57

58

58

58

58

58

58

58

60

60

57

60

60

60

60

60

60

60

58

GND
GND
GND
GND
GND

GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PAGE TITLE

Interposer: Top Aliases

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02545

REVISION

7.0.0

BRANCH

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SYNC_DATE=08/17/2017

SIZE

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VIETMOBILE.VN

3 245

1

D

C

B

51

ACORN_GECKO_ANSEL_TO_PMU_ADC

51

51

51

51

HALL_CASE_TO_AOP_SOUTH_L

51

51

PMU_TO_IKTARA_EN_EXT_1V8

51

51

51

51

51

51

51

51

51

51

51

51

51

51

51

51

51

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51

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51

51

51

51

51

51

51

51

51

51

51

51

51

51

51

51

51

51

51

RACER_TO_AOP_INT_L

IKTARA_TO_SMC_INT

I2C0_SMC_SCL
I2C0_SMC_SDA

IKTARA_COIL2
IKTARA_COIL2
IKTARA_COIL2
IKTARA_COIL2
IKTARA_COIL1
IKTARA_COIL1
IKTARA_COIL1
IKTARA_COIL1

NC_INTERPOSER_309

NC_INTERPOSER_311

AP_CANARY1

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

THIS SIDE HAS ATTRIBUTE

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GND

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MAKE_BASE=TRUE

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MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

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MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

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MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

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MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

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MAKE_BASE=TRUE

AP_CANARY1

59 60

ACORN_GECKO_ANSEL_TO_PMU_ADC

GND

59 60

RACER_TO_AOP_INT_L

GND

59 60

HALL_CASE_TO_AOP_SOUTH_L

GND

59 60

PMU_TO_IKTARA_EN_EXT_1V8

GND

59 60

IKTARA_TO_SMC_INT

GND

59

GND

59

GND

59 60

NC_INTERPOSER_309

GND

59 60

NC_INTERPOSER_311

GND

59 60

55

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59 60

GND

59

GND

59

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

59

GND

59

GND

59

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

57 58 59 60

GND

59

GND

59

GND

57 58 59 60

GND

57 58 59 60

I2C0_SMC_SCL
I2C0_SMC_SDA

IKTARA_COIL2
IKTARA_COIL2
IKTARA_COIL2
IKTARA_COIL2
IKTARA_COIL1
IKTARA_COIL1
IKTARA_COIL1
IKTARA_COIL1

47 30 23 17

56

56

55

11

CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP

59

59

59

59

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59

59

59

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51

GND
GND

THIS SIDE HAS ATTRIBUTE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

GND

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GND

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D

C

B

A

8

67

SYNC_DATE=08/30/2017

PAGE TITLE

A

Interposer: Pins 286-359

DRAWING NUMBER

051-02545

Apple Inc.

REVISION

7.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

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