ANPEC APA4838RI-TR Datasheet

APA4838

Stereo 2.8W Audio Power Amplifier with DC Volume Control

and Selectable Gain

Features General Description

• Operating Voltage : 4.5V to 5V

• Stereo switchable bridged/single-ended

power amplifiers

• DC Volume Control Interface , 0dB to –78dB

with precision scale

• Supply Current , I

• Low Shutdown Current , I

= 15mA at Stereo BTL

DD

= 0.7µA

DD

• Bridge-Tied Load (BTL) or Single-Ended-(SE)

Modes Operation

• Output Power at 1% THD+N , V

DD

=5V

–2.3W/Ch (typ) into a 3 Ω Load
–2.0W/Ch (typ) into a 4 Ω Load
–1.2W/Ch (typ) into a 8 Ω Load

• Output Power at 10% THD+N , V

DD

=5V

–2.8W/Ch (typ) into a 3 Ω Load
–2.3W/Ch (typ) into a 4 Ω Load
–1.5W/Ch (typ) into a 8Ω Load

• Single-ended mode at 1.0% THD+N

–95mW/Ch (typ) into 32Ω Load

The APA4838 is a monolithic integrated circuit , which
provides DC volume control , and a stereo bridged
audio power amplifiers capable of producing 2.8W
(2.3W) into 3Ω with less than 10% (1.0%) THD+N.
APA4838 includes a DC volume control , stereo
bridge-tied and single-ended audio power amplifiers
, stereo docking outputs , and a selectable gain con­trol , that makes it optimally fittable for notebook PC
, multimedia monitors , and other portable
applications. The attenuator range of the volume
control in APA4838 is from 0dB (DC_Vol=0.8VDD) to
–78dB (DC_Vol=0V) with 31 steps. Both of the depop
circuitry and the thermal shutdown protection circuitry
are integrated in APA4838 , that reduces pops and
clicks noise during power up or shutdown mode op­eration , and protects the chip from being destroyed
by over temperature failure. To simplify the audio
system design , APA4838 combines a stereo bridge­tied loads (BTL) mode for speaker drive and a stereo
single-end (SE) mode for headphone drive into a
single chip , where both modes are easily switched
by the HP Sense input control pin signal. Besides
the low supply current design to increase the effi­ciency of the amplifiers , APA4838 also features a
shutdown function which keeps the supply current
only 0.7µA (typ).

• Depop Circuitry Integrated

• Thermal shutdown protection and over current

protection circuitry

• High supply voltage ripple rejection

• PC99 Compliant

• 28-pin TSSOP-P (with enhanced thermal pad)

power package available

Applications

•

Notebook and Desktop Computers

• Multimedia Monitors

Pin Description

GND

Shutdown

Gain S e lec t

Mode

Mute

V

DC Vol

GND

Right Dock

Righ t In
Beep In

Left In

Left D o c k

GND

DD

1
2

3
4
5
6
7

8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Righ t O ut +
V

DD

Righ t O ut ­Righ t G ain 2

Righ t G ain 1
GND
BYPASS
HP Sense
GND
Left G a in 1

Left G a in 2
Left O u t -

V

DD

Left O u t +

• Portable Applications

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw1

APA4838

Ordering and Marking Information

APA4838

APA4838 R :

Block Diagram

Mode

Mute

HP Sense

DC_V ol

Left Dock

Ω

20K

Ω

20K
Left
Audio Input

Right
Audio Input

200K

200K

20K

Ω

Ω

Ω

0.33

0.33

µ

F

µ

F

Right Dock

APA4838
XXXXX

Left In

Beep In

Rig h t In

Handling Code
Temp. Range
Package Code

Ga in Selec t

Mode

Control

Beep

Detect

­+

Bias
+

-

Package Code
R : T S S O P-P
Temp. Range
I : -40 to 8 5 C
Handling Code
TU : T u be T R : T ap e & Ree l

XXXXX - Date Code

Left Gain1

10K

20K

Ω

°

Ω

Left Gain2

10K

­+

20K

Ω

20K

Volume
Control

­+

31 steps

Bias

+

-

20K

Ω

Ω

Ω

20K

0.068µF

- Left Out

Ω

+ Left Out

+ Right Out

Ω

20K

Shutdown

V

DD

GND

Bypass

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

Power

Managem ent

Click and Pop

Suppression

Circuitry

20K

+

- Right O u t

Ω

20K

Ω

-

Ω

10K

10K

Ω

Ω

20K

0.068µF

Right Gain1

20K

Right Gain2

Ω

20K

Ω

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APA4838

Absolute Maximum Ratings

(Over operating free-air temperature range unless otherwise noted.)

Symbol Parameter Rating Unit

V

DD

V

IN

T

A

T

J

T

STG

T

S

V

ESD

P

D

Note:

1.APA4838 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C

2.Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses

3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses

Supply Voltage -0.3 to 6 V
Input Voltage Range, HP sense, Shutdown,

Mute, Mode, Gain Select

-0.3 to V

+0.3 V

DD

Operating Ambient Temperature Range -40 to 85
Maximum Junction Temperature Internally Limited*
Storage Temperature Range -65 to +150
Soldering Temperature,10 seconds 260
Electrostatic Discharge -2000 to 2000*

2

Power Dissipation Internally Limited W

C

°

1

C

°

C

°

C

°

V

Recommended Operating Conditions

Min. Max. Unit

Supply Voltage, V

DD

High level threshold voltage, V

Low level threshold voltage, V
Common mode input voltage, V

IH

HP Sense 4
Shutdown, Mute, Mode, Gain Select 1.0

Shutdown, Mute, Mode, Gain Select 2

IL

ICM

HP Sense 3

4.5 5.5 V

VDD-1.0 V

Thermal Characteristics

Symbol Parameter Value Unit

R

THJA

* 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias.
The thermal pad on the TSSOP_P package with solder on the printed circuit board.

Thermal Resistance from Junction to Ambient in Free Air

TSSOP-P* 45 K/W

V

V

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw3

APA4838

Electrical Characteristics

Electrical Characteristics for Entire IC

The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25°C

Symbol Parameter Test Conditions

V

I
I

Supply Voltage 4.5 5.5 V

DD

Quiescent Power Supply

DD

Current
Shutdown Curre nt V

SD

V

=0V, IO=0A 15 25 mA

IN

= V

PIN 2

DD

Electrical Characteristics for Volume Attenuators

The following specifications apply for VDD= 5V. Limits apply for TA= 25°C

Symbol Parameter Test Conditions

C

RANGE

A

M

Attenuator Range

Mute Attenuation

Gain with V
Attenuation with V
V

=5V, Bridged Mode -70

PIN 5

V

=5V, Single-Ended Mode -70

PIN 5

=5V ±0.5

PIN 7

PIN 7

=0V -65 -78

Min. T yp. Max.

Min. Typ. Max.

APA4838

0.7 2.0

APA4838

Unit

A

µ

Unit

dB

dB

Electrical Characteristics for BTL Mode Operation

The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25°C

Symbol Parameter Test Conditions

V

OS

P

Output Offset Voltage VIN=0V 5 mV

O

Output Power

THD=1%, f=1kHz

=3

R

Ω

L

R

=4

Ω

L

R

=8

Ω

L

THD=10%, f=1kHz

=8

R

Ω

L

THD+N Total Harmonic Distortion + Noise AVD=2, f=1kHz

R

=4Ω , PO =1.5W

L

R

=8Ω , PO=1W

L

V

PSRR Power Supply Rejection Ratio

X

TALK

Channel Separation

SNR Signal-to-Noise Ratio

V

Output Noise Voltage

N

=100mV

RIPPLE

=8Ω, f=1kHz

R

L

=2.2µF, f=1kHz, RL=8

C

B

=5V, PO =1.1W, RL=8Ω,A-Wtd

V

DD

Filter

=8Ω,A-Wtd Filter

R

L

Rms CB

=2.2µF,

Ω

APA4838

Typ.

2.3

2.0

1.2

1.5

0.07

0.07
70 dB
90 dB
95 dB
30

Unit

W

%

V

µ

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw4

APA4838

Electrical Characteristics (Cont.)

Electrical Characteristics for SE Mode Operation (Cont.)

The following specifications apply for VDD= 5V unless otherwise noted. Limits apply for TA= 25°C

Symbol Parameter Test Conditions

V

THD+N

PSRR

X
SNR Signal-to-Noise Ratio

Output Offset Voltage VIN=0V 5 mV

OS

P

Output Power

O

Total Harmonic Distortio n
plus Noise

Power Supply Rej ec tio n
Ratio

Channel Separation

TALK

V

Output Noise Voltage

N

THD=1%, f=1kHz,
THD=10%, f=1kHz,

AV= 1 , V
P

=75mW, RL=32Ω, AV= 1, f=1kHz

O

V

RIPPLE

C

=2.2µF, RL=8Ω , f=1kHz

B

P

=75mW, RL=32Ω, A-Wtd Filter

O

=32Ω, A-Wtd Filter

R

L

=1V

OUT

=100mV

RMS

RMS

R

=32

L

R

=32

L

, RL=10kΩ, f=1kHz

, f=120Hz, CB=2.2µF

Ω
Ω

APA4838

Typ.

95

110

0.05 %

0.07 %
52 dB

90 dB

102 dB

20

Unit

mW

V

µ

Pin Description

Pin

Name No

GND 1, 8, 14,

20, 23

Shutdown 2 I Shutdown mode control signal input, place entire IC in shutdown mode when

Gain Select 3 I Gain select input pin, logic high will switch the amplifier to external gain

Mode 4 I Mode select input pin, fixed gain when logic L and gain adjustable mode

Mute 5 I Mute control input pin, active H.
V

DD

6, 16, 27 Supply voltage input pin
DC_Vol 7 I Volume control function input pin.
Right Dock 9 O Right docking output pin
Right In 10 I Right channel audio input pin
Beep In 11 I Beep signal input pin
Left In 12 I Left channel audio input pin
Left Dock 13 O Right docking output pin
Left Out + 15 O Left channel positive output pin
Left Out - 17 O Left channel negative output pin
Left Gain 2 18 Connect pin 2 of the external gain setting resistor for left channel
Left Gain 1 19 Connect pin 1 of the external gain setting resistor for left channel
HP Sense 21 I Headphone sense control pin

I/O Description

Ground connection for circuitry.

held high, Idd=0.7uA

mode, and logic low will switch to internal unity gain.

when logic H.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw5

APA4838

Pin Description (Cont.)

Pin

I/O Description

Name No

Bypass 22 Bypass pin
Right Gain 1 24 Connect pin 1 of the external gain setting resistor for right channel
Right Gain 2 25 Connect pin 2 of the external gain setting resistor for right channel
Right Out - 26 O Right channel negative output pin
Right Out + 28 O Right channel positive output pin

Truth Table for Logic Inputs

Mute

Gain

Select

0000Unity Gain SettingFixed LevelVol. Fixed -

0001Unity Gain SettingFixed Level Muted Vol. Fixed

0010Unity Gain SettingAdjustableVol. Adjustable -

0011Unity Gain SettingAdjustable MutedVol. Adjustable

Mode

HP

Sense

Gain Mode of

Power Amplifier

DC Vol. Control BTL Output SE Output

0100External Gain SettingFixed LevelVol. Fixed -

0101External Gain SettingFixed Level Muted Vol. Fixed

0110External Gain SettingAdjustableVol. Adjustable -

0111External Gain SettingAdjustable MutedVol. Adjustable

1 X X X - - Muted Muted

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw6

APA4838

Typical Application Circuit

To Control P in on

Headphone Ja c k

Left

Audio

Input

Beep In

Right

Audio

Input

20K

200K

200K

20K

100K

Ω

Ω

Ω

Ω

V

DD

Ω

Left Dock

Left In

0.33

Right In

0.33

Right Dock

V

DD

1,8,14,20,23

GND

µ

F0.1µF0.1µF

0.1

100K

Mute

Mode

20K

+

µ

F

+

µ

F

20K

6,16,27

Bypass

HP Sense

Ω

21

5
4

13

Ω

12

11

10

Ω

9

22

2.2µ

F

R_var

Internal g a in sel ec t

Mode

Control

Beep

Detect

Power

Management

Click and P op

Suppression

Circuitry

V

DD

V

DD

1 µ

F

DC Vol Control

Ω

Bias

20K

18

Ω

20K

Ω

10K

- Left Out

17

Ω

Ω

20K

-

15

+

+ Left Out

+
220µF

To HP sense

0.068µF

Ω

1K

Control

Pin

Pin

Ring

Circuit

+

-

+ Right Out

28

Tip

Sleeve

­+

Bias

+

-

73

Volume
Control

31 steps

Ω

20K

19

Ω

10K

­+

20K

Headphone Ja ck

- Right O u t

26

+

20K

220µF

Ω

Ω

1K

10K

Ω

Ω

+

20K

20K

-

Ω

10K

Ω

0.068µF

25242

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

Shutdown

20K

Ω

20K

Ω

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APA4838

Application Information

Volume Control Table

Gain (dB) Voltage Range (% of Vdd) Voltage Range (Vdd=5V)

Low High R ecomme nded Low High Recomme nded

0 77.5% 100.00% 100.000% 3.875 5.000 5.000

-1 75.0% 78.5% 76.875% 3.750 3.938 3.844

-2 72.5% 76.25% 74.375% 3.625 3.813 3.719

-3 70.0% 73.75% 71.875% 3.500 3.688 3.594

-4 67.5% 71.25% 69.375% 3.375 3.563 3.469

-5 65.0% 68.75% 66.875% 3.250 3.438 3.344

-6 62.5% 66.25% 64.375% 3.125 3.313 3.219

-8 60.0% 63.75% 61.875% 3.000 3.188 3.094

-10 57.5% 61.25% 59.375% 2.875 3.063 2.969

-12 55.0% 58.75% 56.875% 2.750 2.938 2.844

-14 52.5% 56.25% 54.375% 2.625 2.813 2.719

-16 50.0% 53.75% 51.875% 2.500 2.688 2.594

-18 47.5% 51.25% 49.375% 2.375 2.563 2.469

-20 45.0% 48.75% 46.875% 2.250 2.438 2.344

-22 42.5% 46.25% 44.375% 2.125 2.313 2.219

-24 40.0% 43.75% 41.875% 2.000 2.188 2.094

-26 37.5% 41.25% 39.375% 1.875 2.063 1.969

-28 35.0% 38.75% 36.875% 1.750 1.938 1.844

-30 32.5% 36.25% 34.375% 1.625 1.813 1.719

-32 30.0% 33.75% 31.875% 1.500 1.688 1.594

-34 27.5% 31.25% 29.375% 1.375 1.563 1.469

-36 25.0% 28.75% 26.875% 1.250 1.438 1.344

-38 22.5% 26.25% 24.675% 1.125 1.313 1.219

-40 20.0% 23.75% 21.875% 1.000 1.188 1.094

-42 17.5% 21.25% 19.375% 0.875 1.063 0.969

-44 15.0% 18.75% 16.875% 0.750 0.937 0.844

-46 12.5% 16.25% 14.375% 0.625 0.812 0.719

-48 10.0% 13.75% 11.875% 0.500 0.687 0.594

-50 7.5% 11.25% 9.375% 0.375 0.562 0.469

-52 5.0% 8.75% 6.875% 0.250 0.437 0.344

-78 0.0% 6.25% 0.000% 0.000 0.312 0.000

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Feb., 2003

www.anpec.com.tw8

APA4838

Typical Characteristics

THD+N vs. Frequency

10

VDD=5V
RL=3Ω
Po=1.8W
BTL

1

THD+N (%)

0.1

0.01
20 20k100 1k

Frequency (Hz)

Av=2

Av=4

Av=8

THD+N vs. Output Power

10

VDD=5V
RL=3Ω
Av=2
BTL

1

THD+N (%)

0.1

f=20Hz

0.01
10m 3100m 1

f=1KHz

Output Power (W)

f=20KHz

THD+N vs. Frequency

10

VDD=5V
RL=4Ω
Po=1.5W
BTL

1

Av=2

Av=4

THD+N (%)

0.1

0.01
20 20k100 1k

Av=8

Frequency (Hz)

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

THD+N vs. Output Power

10

VDD=5V
RL=4Ω
Av=2
BTL

1

0.1

THD+N (%)

0.01
100m 3500m

f=20KHz

f=1KHz

f=20Hz

Output Power (W)

1

www.anpec.com.tw9

APA4838

Typical Characteristics (Cont.)

THD+N vs. Frequency

10

VDD=5V
RL=8Ω
Po=1.0W
BTL

1

Av=2

THD+N (%)

0.1

0.01
20 20k100 1k

Frequency (Hz)

Av=4

Av=8

THD+N vs. Output Power

10

VDD=5V
RL=8Ω
Av=2
BTL

1

0.1

THD+N (%)

0.01
10m 2100m 1

f=20KHz

f=1KHz

f=20Hz

Output Power (W)

THD+N vs. Frequency

10

VDD=5V
RL=8Ω
Po=250mW
SE

1

Av=1

Av=2

THD+N (%)

0.1

0.01
20 20k100 1k

Av=4

Frequency (Hz)

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

THD+N vs. Output Power

10

VDD=5V
RL=8Ω
Av=1
SE

1

THD+N (%)

0.1

0.01
10m 500m100m

Output Power (W)

f=20KHz

f=1KHz

f=20Hz

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APA4838

Typical Characteristics (Cont.)

THD+N vs. Frequency

10

VDD=5V
RL=16Ω
Po=150mW
SE

1

Av=1

THD+N (%)

0.1

0.01
20 20k100 1k

Frequency (Hz)

Av=2

Av=4

THD+N vs. Output Power

10

VDD=5V
RL=16Ω
Av=1
SE

1

0.1

THD+N (%)

0.01
10m 300m100m

f=20Hz

f=1KHz

Output Power (W)

f=20KHz

THD+N vs. Frequency

10

VDD=5V
RL=32Ω
Po=75mW
SE

1

Av=1

Av=2

0.1

THD+N (%)

0.01
20 20k100 1k

Av=4

Frequency (Hz)

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

THD+N vs. Output Power

10

VDD=5V
RL=32Ω
Av=1
SE

1

f=20Hz

f=20KHz

0.1

THD+N (%)

f=1KHz

0.01
10m 200m50m 100m

Output Power (W)

www.anpec.com.tw11

APA4838

Typical Characteristics (Cont.)

THD+N vs. Frequency

10

VDD=5V
RL=10KΩ
Vo=1VRMS
SE

1

THD+N (%)

0.1

0.01
20 20k100 1k

Frequency (Hz)

Av=1

Av=2

Av=4

THD+N vs. Output Swing

10

VDD=5V
RL=10KΩ
Av=1
SE

1

THD+N (%)

0.1

0.01
100m 3500m 2

f=20Hz

f=20KHz

Output Swing (VRHS)

f=1KHz

Crosstalk vs. Frequency

+0

VDD=5V
RL=8Ω
Po=1.0W

-20

Av=2
BTL

-40

-60

-80

Crosstalk (dB)

-100

-120
20 20k100 1k

R-ch to L-ch

L-ch to R-ch

Frequency (Hz)

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

Crosstalk vs. Frequency

+0

VDD=5V
RL=32Ω
Po=75mW

-20

Av=2
SE

-40

-60

-80

Crosstalk (dB)

-100

-120
20 20k100 1k

R-ch to L-ch

Frequency (Hz)

L-ch to R-ch

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APA4838

Typical Characteristics (Cont.)

Noise Floor vs. Frequency

100

10

Noise Floor (µVRMS)

VDD=5V
RL=8Ω
Av=2
BTL

1

20 20k100 1k

Frequency (Hz)

No Filter

A-Weight

Noise Floor vs. Frequency

100

10

Noise Floor (µVRMS)

VDD=5V
RL=32Ω
Av=1
SE

1

20 20k100 1k

Frequency (Hz)

No Filter

A-Weight

Supply Current vs. Supply Voltage

25

20

15

BTL

10

SE

Supply Current (mA)

5

0

1 1 .5 2 2 .5 3 3.5 4 4.5 5 5 .5

Supply Voltage (V)

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

No Load

Power Dissipation vs. Output Power

2

1.8

1.6

1.4

1.2
1

0.8

0.6

Power Dissipation (W)

0.4

0.2
0

0 0.5 1 1.5 2 2.5

RL=8Ω

RL=3Ω

RL=4Ω

Output Power (W)

www.anpec.com.tw13

VDD=5V
Av=2
BTL

APA4838

Typical Characteristics (Cont.)

Power Dissipation vs. Output Power

0.25

0.2

RL=8Ω

0.15

0.1

0.05

Power Dissipation (W)

RL=16Ω

RL=32Ω

0

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

Output Power (W)

VDD=5V
Av=2
SE

Gain vs. Voltage, 5V, SE

4
0

-4

-8

-12

-16

-20

-24

-28

-32

-36

-40

-44

-48

-52

-56

Output Gain (dB)

-60

-64

-68

-72

-76

-80

0 0 .5 1 1 .5 2 2.5 3 3.5 4 4 .5 5

DC Vol Input Voltage (V)

VDD=5V
AV=1
SE

Output Power vs. Supply Voltage

2.25
2

1.5

THD+N=10%

1

THD+N=1%

Output Power (W)

0.5

0

2.5 3 3.5 4 4.5 5 5.5

Supply Voltage (V)

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

RL=8Ω
Av=2
BTL

Output Power vs. Supply Voltage

160
140
120
100

THD+N=10%

80
60
40

Output Power (mW)

THD+N=1%

20

0

2.5 3 3.5 4 4.5 5 5.5

Supply Voltage (V)

www.anpec.com.tw14

RL=32Ω
Av=1
SE

APA4838

Typical Characteristics (Cont.)

Output Power vs. Load Resistance

3

2.5

2

1.5

1

THD+N=10%

Output Power (W)

0.5

THD+N=1%

0

4 8 16 24 32 40 48 56 64

Load Resistance (Ω)

VDD=5V
Av=2
BTL

Output Power vs. Load Resistance

800
700

600
500
400
300
200

Output Power (mW)

100

THD+N=1%

0

4 8 16 24 32 40 48 56 64

THD+N=10%

Load Resistance (Ω)

VDD=5V
Av=1
SE

PSRR vs. Frequency

+0

6666

VDD=5V
Vin=100mVRMS
RL=8Ω

-20

Cbypass=2.2µF
Av=2
BTL

-40

Gain Adjustable

-60

-80

Fixed Gain Mode

Ripple Rejection Ratio (dB)

-100

20 20k100 1k

Frequency (Hz)

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

PSRR vs. Frequency

+0

VDD=5V
Vin=100mVRMS
RL=8Ω

-20

Cbypass=2.2µF
Av=1
SE

-40

-60

-80

Ripple Rejection Ratio (dB)

-100
20 20k100 1k

Gain Adjustable

Fixed Gain Mode

Frequency (Hz)

www.anpec.com.tw15

APA4838

Typical Characteristics (Cont.)

Gain vs. Frequency

+12

+10

+8

+6

Cf=0.068µF

Gain (dB)

+4

+2

-0
20 20k100 1k

Cf=0.22µF

Cf=0.1µF

VDD=5V
RL=8Ω
Av=2V/V
BTL

Frequency (Hz)

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw16

APA4838

Application Descriptions

BTL Operation

The APA4838 output stage (power amplifier) has two
pairs of operational amplifiers internally, allowed for
different amplifier configurations for each channel.

Gain 1 Gain 2

Volume Control

Amplifier output signal

Vbias

OP1

OP2

-Out

+Out

Figure 1: APA4838 power amplifier internal configu­ration (each channel)

The power amplifier OP1 gain is setting by internal
unity-gain or external gain setting which is selected
from Gain Select pin and the audio input signal come
from internal volume control block, while the second
amplifier OP2 is internally fixed in a unity-gain, in­verting configuration. Figure 1 shows that the output
of OP1 is connected to the input to OP2, which re­sults in the output signals of with both amplifiers with
identical in magnitude, but out of phase 180°.
Consequently, the differential gain for each channel
is 2X (Gain of SE mode).
By driving the load differentially through outputs -Out

BTL Operation (Cont.)

A BTL amplifier design has a few distinct advantages
over the SE configuration, as it provides differential
drive to the load, thus doubling the output swing for a
specified supply voltage.
Four times the output power is possible as compared
to a SE amplifier under the same conditions. A BTL
configuration, such as the one used in APA4838, also
creates a second advantage over SE amplifiers.

RL

Since the differential outputs, +Right Out, -Right Out,
+Left Out, and -Left Out, are biased at half-supply,
no need DC voltage exists across the load. This elimi­nates the need for an output coupling capacitor which
is required in a single supply, SE configuration.

Single-Ended Operation

Consider the single-supply SE configuration shown
Application Circuit. A coupling capacitor is required
to block the DC offset voltage from reaching the load.
These capacitors can be quite large (approximately
33µF to 1000µF) so they tend to be expensive, oc­cupy valuable PCB area, and have the additional
drawback of limiting low-frequency performance of
the system (refer to the Output Coupling Capacitor).
The rules described still hold with the addition of the
following relationship:

and +Out, an amplifier configuration commonly re­ferred to as bridged mode is established. BTL mode
operation is different from the classical single-ended
SE amplifier configuration where one side of its load
is connected to ground.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

1

Cbypass x 125kΩ

1

≤

RiCi

<<

1

RLCC

www.anpec.com.tw17

(1)

APA4838

Application Descriptions (Cont.)

Output SE/BTL Operation

The ability of the APA4838 to easily switch between
BTL and SE modes is one of its most important costs
saving features. This feature eliminates the require­ment for an additional headphone amplifier in appli­cations where internal stereo speakers are driven in
BTL mode but external headphone or speakers must
be accommodated.
Internal to the APA4838, two separate amplifiers drive
–Out and +Out for each channel (see Figure 1). The
HP Sense input controls the operation of the follower
amplifier that drives +Left Out and +Right Out.

• When HP Sense is held low, the OP2 is turn on and
the APA4838 is in the BTL mode.

•When HP Sense is held high, the OP2 is in a high
output impedance state, which configures the

Output SE/BTL Operation (Cont.)

In Figure 2, input HP Sense operates as follows:
When the phonejack plug is inserted, the 1kΩ resis­tor is disconnected and the HP Sense input is pulled
high and enables the SE mode.
When this input goes high level, the +Out amplifier is
shutdown causing the speaker to mute. The -Out
amplifier then drives through the output capacitor (CC)
into the headphone jack.
When there is no headphone plugged into the system,
the contact pin of the headphone jack is connected
from the signal pin, the voltage divider set up by re­sistors 100kΩ and 1kΩ. Resistor 1kΩ then pulls low
the HP Sense pin, enabling the BTL function.

Docking Output Signal

APA4838 as SE driver from -Out. IDD is reduced by
approximately one-half in SE mode.
Control of the HP Sense input can be a logic-level
TTL source or a resistor divider network or the ste­reo headphone jack with switch pin as shown in Ap­plication Circuit.

Ω

1k

HP sense

100k

VDD

Ω

Control

Pin

Headphone Jack

Tip

Ring

Sleeve

Figure 2: HP Sense input selection by phonejack
plug

APA4835 internal first amplifier is used as audio sig­nal pre-amplfier and feedback resistor is connected
between Dock output pin and audio input pin.
However, the internal first amplifier’s closed-loop gain
can be adjusted using external resistors. Use Equa­tion 2 to determine the input and feedback resistor
values for a desired gain.

AV

RF

-

=

Ri

(2)

The Dock output signal provides low distortion audio
quality for light driving output. ex. active speaker,
monitors or audio/visual equipment. These two out­puts can driving load of >1kΩ with rail-to-rail output
and output coupling capacitor is required when using
these outputs.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw18

APA4838

Application Descriptions (Cont.)

Docking Output Signal (Cont.)

Typical values for the output coupling capacitors are

0.33µF to 1.0µF. If polarized coupling capacitors are
used, connect their ’+’ terminals to the respective
output pin.
The Right Dock and Left Dock channel outputs sig­nal are also used to driving internal volume control
amplifier.

Input Capacitor, Ci

In the typical application an input capacitor, Ci, is re­quired to allow the amplifier to bias the input signal to
the proper DC level for optimum operation. In this
case, Ci and the minimum input impedance Ri form a
high-pass filter with the corner frequency determined
in the follow equation:

FC(highpass)=

1

2πRiCi

(3)

Input Capacitor, Ci (Cont.)

This leakage current creates a DC offset voltage at
the input to the amplifier that reduces useful
headroom, especially in high gain applications. For
this reason a low-leakage tantalum or ceramic ca­pacitor is the best choice. When polarized capaci­tors are used, the positive side of the capacitor should
face the amplifier input in most applications as the
DC level there is held at VDD/2, which is likely higher
that the source DC level. Please note that it is impor­tant to confirm the capacitor polarity in the application.

Effective Bypass Capacitor, Cbypass

As other power amplifiers, proper supply bypassing
is critical for low noise performance and high power
supply rejection.
The capacitors located on the bypass and power
supply pins should be as close to the device as

The value of Ci is important to consider as it directly
affects the low frequency performance of the circuit.
Consider the example where Ri is 100kΩ and the
specification calls for a flat bass response down to
40Hz. Equation is reconfigured as follow:

1

Ci=

2πRif

C

Consider to input resistance variation, the Ci is 0.04µF
so one would likely choose a value in the range of

0.1µF to 1.0µF.
A further consideration for this capacitor is the leak­age path from the input source through the input net­work (Ri+Rf, Ci) to the load.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

(4)

possible. The effect of a larger half supply bypass
capacitor will improve PSRR due to increased half­supply stability. Typical application employ a 5V regu­lator with 1.0µF and a 0.1µF bypass as supply filtering.
This does not eliminate the need for bypassing the
supply nodes of the APA4838. The selection of by­pass capacitors, especially Cbypass, is thus depen­dent upon desired PSRR requirements, click and pop
performance.
To avoid start-up pop noise occurred, the bypass
voltage should rise slower than the input bias voltage
and the relationship shown in equation (5) should be
maintained.

1

Cbypass x 125kΩ

<<

1

RiCi

(5)

www.anpec.com.tw19

APA4838

Application Descriptions (Cont.)

Effective Bypass Capacitor, Cbypass (Cont.)

The bypass capacitor is fed from a 125kΩ resistor
inside the amplifier. Bypass capacitor, Cbypass, val­ues of 3.3µF to 10µF ceramic or tantalum low-ESR
capacitors are recommended for the best THD and
noise performance.
The bypass capacitance also effects to the start up
time. It is determined in the following equation:

Tstart up = 5 x (Cbypass x 125kΩ)

Output Coupling Capacitor, Cc

In the typical single-supply (SE) configuration, an
output coupling capacitor (Cc) is required to block
the DC bias at the output of the amplifier thus pre­venting DC currents in the load. As with the input
coupling capacitor, the output coupling capacitor and

(6)

Power Supply Decoupling, Cs

The APA4838 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic dis­tortion (THD) is as low as possible. Power supply
decoupling also prevents the oscillations causing by
long lead length between the amplifier and the
speaker. The optimum decoupling is achieved by
using two different type capacitors that target on dif­ferent type of noise on the power supply leads. For
higher frequency transients, spikes, or digital hash
on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1µF placed as
close as possible to the device VDD lead works best.
For filtering lower-frequency noise signals, a large

aluminum electrolytic capacitor of 10µF or greater
impedance of the load form a high-pass filter gov­erned by equation.

FC(highpass)=

For example, a 330µF capacitor with an 8Ω speaker
would attenuate low frequencies below 60.6Hz. The
main disadvantage, from a performance standpoint,
is the load impedance is typically small, which drives
the low-frequency corner higher degrading the bass
response. Large values of CC are required to pass
low frequencies into the load.

1

2πRLCC

(7)

placed near the audio power amplifier is

recommended.

Optimizing Depop Circuitry

Circuitry has been included in the APA4838 to mini-

mize the amount of popping noise at power-up and

when coming out of shutdown mode. Popping oc-

curs whenever a voltage step is applied to the

speaker. In order to eliminate clicks and pops, all

capacitors must be fully discharged before turn-on.

Rapid on/off switching of the device or the shutdown

function will cause the click and pop circuitry. The

value of Ci will also affect turn-on pops. (Refer to

Effective Bypass Capacitance) The bypass voltage

rise up should be slower than input bias voltage.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw20

APA4838

Application Descriptions (Cont.)

Optimizing Depop Circuitry (Cont.)

Although the bypass pin current source cannot be
modified, the size of Cbypass can be changed to al­ter the device turn-on time and the amount of clicks
and pops. By increasing the value of Cbypass, turn­on pop can be reduced. However, the tradeoff for
using a larger bypass capacitor is to increase the turn­on time for this device. There is a linear relationship
between the size of Cbypass and the turn-on time.
In a SE configuration, the output coupling capacitor,
C

, is of particular concern. This capacitor discharges

C

through the internal 10kΩ resistors. Depending on
the size of CC, the time constant can be relatively
large. To reduce transients in SE mode, an external
1kΩ resistor can be placed in parallel with the inter­nal 10kΩ resistor. The tradeoff for using this resistor

Shutdown and Mute Function (Cont.)

The trigger point between a logic high and logic low

level is typically 2.0V. It is best to switch between

ground and the supply voltage V

to provide maxi-

DD

mum device performance.

By switching the Shutdown pin to high level, the am-

plifier enters a low-current state, IDD<1µA. APA4838

is in shutdown mode. On normal operating, Shut-

down pin pull to low level to keeping the IC out of the

shutdown mode. The Shutdown pin should be tied

to a definite voltage to avoid unwanted state changes.

The APA4838 mutes the amplifier and DOCK out-

puts when V

DD is applied to the Mute pin. Even while

muted, the APA4838 will amplify a system alert (beep)

signal whose magnitude satisfies the PCBEEP de-

tect circuitry. Applying 0V to the Mute pin returns the
is an increase in quiescent current.
In the most cases, choosing a small value of Ci in the
range of 0.33µF to 1µF, Cbypass being equal to 4.
7µF and an external 1kΩ resistor should be placed in
parallel with the internal 10kΩ resistor should pro­duce a virtually clickless and popless turn-on.
A high gain amplifier intensifies the problem as the
small delta in voltage is multiplied by the gain. So it
is advantageous to use low-gain configurations.

Shutdown and Mute Function

In order to reduce power consumption while not in
use, the APA4838 contains a Shutdown pin to exter­nally turn off the amplifier bias circuitry. This shut­down feature turns the amplifier off when a logic high
is placed on the Shutdown pin.

APA4838 to normal operation. Prevent unanticipated

mute behavior by connecting the Mute pin to VDD or

ground. Do not let the Mute pin float.

PCBEEP Detect Circuitry

APA4838 integrates a PCBEEP detect circuit for note-

book and computer used. When Beep In signal is

greater than 1/2VDD, the PCBEEP mode is active.

APA4838 will force to BTL mode and the internal fixed

gain mode. The Beep In signal becomes the ampli-

fier input signal and plays on the system speaker with-

out coupling capacitor. Use input resistor between

stereo input pin and Beep In to attenuate Beep In

signal. These resistors are shown as 200kΩ devices

in Application Circuit. Use higher value resistors to

reduce the gain applied to the beep signal.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw21

APA4838

Application Descriptions (Cont.)

PCBEEP Detect Circuitry (Cont.)

If the amplifier in the mute mode, it will out of mute
mode whenever PCBEEP mode enable. The
APA4838’s shutdown mode must be deactivated
before a system alert signal is applied to Beep In pin.
The APA4838 will return to previous setting when it
is out of PCBEEP mode. The Beep In pin should be
tied to a ground when not used to avoid unwanted
state changes.

Mode Function

The APA4838’s Mode function has 2 states controlled
by the voltage applied to the Mode pin. By applying
0V to the Mode pin, forces the APA4838 to fixed gain
amplifier and internal volume control block will be dis­able and internal first amplifier output signal (Dock)
to power amplifier directly. When Mode pin goes to
high level, which uses the internal DC controlled vol-

Internal and External Gain Selection (Cont.)

LF

C

R

Gain 1

Volume Control

Amplifier output signal

I2

F2

R

Gain 2

OP1

LF

R

-Out

Figure3: Bass Boost gain setting configuration

In some cases a designer may want to improve the

low frequency response of the bridged amplifier or

incorporate a bass boost feature. Refer to the Figure,

a resistor, RLF, and a capacitor, CLF, in parallel, can

be placed in series with the feedback resistor of the

bridged amplifier as seen in Figure.

Fc=

1

2πRLFCLF

(8)

ume control is selected. This mode sets the amplifier’s
gain according to the DC voltage applied to the DC
Vol control pin. Do not let the Mode pin float when it
does not used.

Internal and External Gain Selection

APA4838 provides external gain setting for base
boost function or internal feedback gain setting which
is decided by Gain Select control input. If Gain Se­lect pin goes high level, the gain setting will be de­fined by Gain1 and Gain2 pin. When Gain Select pin
tied to low level, APA4835 power amplifier gain set­ting as unit gain by internal resistor.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

The bridged-amplifier low frequency differential gain

is:

2x(RF2+RLF)

Fc=

R12

(9)

Using the component values shown in Figure (RF2 =

20kΩ,RLF = 20kΩ, and CLF = 0.068µF), a first-order, -

6dB pole is created at 120Hz. Assuming R12 = 20kΩ,

the low frequency differential gain is 4. The input (Ci)

and output (CO) capacitor values must be selected

for a low frequency response that covers the range

of frequencies affected by the desired bass-boost

operation.

www.anpec.com.tw22

APA4838

Application Descriptions (Cont.)

Internal and External Gain Selection (Cont.)

At low frequencies C

LF is a virtual open circuit and at

high frequencies, its nearly zero ohm impedance
shorts RLF. The result is increased bridge-amplifier
gain at low frequencies. The combination of RLF and
CLF form a -6dB corner frequency at

Volume Adjustable and Fixed Gain selection

The APA4838 has an internal stereo volume control
whose setting is a function of the DC voltage applied
to the DC Vol control pin. The APA4838 volume con­trol consists of 31 steps that are individually selected
by a variable DC voltage level on the DC Vol control
pin. The range of the steps, controlled by the DC
voltage, are from 0dB to -78dB. Each gain step cor­responds to a specific input voltage range, as shown

BTL Amplifier Efficiency

An easy-to-use equation to calculate efficiency starts

out as being equal to the ratio of power from the power

supply to the power delivered to the load. The fol-

lowing equations are the basis for calculating ampli-

fier efficiency.

Efficiency =

P

PSUP

(10)

O

Where :

PO = =

VORMS =

VORMS x VORMS

RL

VP

√2

PSUP = VDD x IDDRMS = VDD x

VPxVP

2RL

2VP
πRL

(11)

(12)

Efficiency of a BTL configuration :

PO

VPxVP

( ) / (VDD x ) =

=

PSUP

2RL

2VP

πRL

πVP

2VDD

(13)

in table. To minimize the effect of noise on the vol­ume control pin, which can affect the selected gain
level, hysteresis and internal clock delay are
implemented. The amount of hysteresis corresponds
to half of the step width, as shown in volume control
graph.
For highest accuracy, the voltage shown in the ’rec­ommended voltage’ column of the table is used to
select a desired gain. This recommended voltage is
exactly halfway between the two nearest transitions.
The gain levels are 1dB/step from 0dB to -6dB, 2dB/
step from -6dB to -52dB, and the last step at -78dB
as mute mode.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

Po (W) Efficiency (%) IDD(A) VPP(V) PD (W)

0.2 26.67 0.15 2.00 0.55

0.50 41.67 0.24 2.83 0.7

1.00 58.82 0.34 4.00 0.7

1.3 68.42 0.38 4.47 0.6

**High peak voltages cause the THD to increase.

Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL

Systems

Table 1 calculates efficiencies for four different out-

put power levels when load is 8Ω.

www.anpec.com.tw23

APA4838

Application Descriptions (Cont.)

BTL Amplifier Efficiency (Cont.)

The efficiency of the amplifier is quite low for lower
power levels and rises sharply as power to the load
is increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note
that the internal dissipation at full output power is less
than in the half power range. Calculating the efficiency
for a specific system is the key to proper power sup­ply design. For a stereo 1W audio system with 8Ω
loads and a 5V supply, the maximum draw on the
power supply is almost 3W.
A final point to remember about linear amplifiers
(either SE or BTL) is how to manipulate the terms in
the efficiency equation to utmost advantage when
possible. Note that in equation, VDD is in the
denominator. This indicates that as VDD goes down,
efficiency goes up. In other words, use the efficiency
analysis to choose the correct supply voltage and
speaker impedance for the application.

Power Dissipation

Power Dissipation (Cont.)

2

BTL mode : PD,MAX=

4VDD

2

2π RL

(15)

Since the APA4838 is a dual channel power amplifier,

the maximum internal power dissipation is 2 times

that both of equations depending on the mode of

operation. Even with this substantial increase in power

dissipation, the APA4838 does not require extra

heatsink. The power dissipation from equation15,

assuming a 5V-power supply and an 8Ω load, must

not be greater than the power dissipation that results

from the equation16:

PD,MAX=

TJ,MAX - TA

θJA

(15)

For TSSOP-28 package with and without thermal pad,

the thermal resistance (θJA) is equal to 45οC/W and

50οC/W, respectively.

Since the maximum junction temperature (T

J,MAX

) of
APA4838 is 150οC and the ambient temperature (TA)
is defined by the power system design, the maximum
power dissipation which the IC package is able to

Whether the power amplifier is operated in BTL or
SE modes, power dissipation is a major concern. In
equation14 states the maximum power dissipation
point for a SE mode operating at a given supply volt­age and driving a specified load.

2

SE mode : PD,MAX= (14)

VDD

2

2π RL

In BTL mode operation, the output voltage swing is
doubled as in SE mode. Thus the maximum power
dissipation point for a BTL mode operating at the
same given conditions is 4 times as in SE mode.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

handle can be obtained from equation16. Once the
power dissipation is greater than the maximum limit
(P

), either the supply voltage (VDD) must be

D,MAX

decreased, the load impedance (RL) must be in­creased or the ambient temperature should be
reduced.

www.anpec.com.tw24

APA4838

Application Descriptions (Cont.)

Thermal Pad Considerations

The thermal pad must be connected to ground. The
package with thermal pad of the APA4838 requires
special attention on thermal design. If the thermal
design issues are not properly addressed, the
APA4838 4Ω will go into thermal shutdown when driv­ing a 4Ω load.
The thermal pad on the bottom of the APA4838 should
be soldered down to a copper pad on the circuit board.
Heat can be conducted away from the thermal pad
through the copper plane to ambient. If the copper
plane is not on the top surface of the circuit board, 8
to 10 vias of 13 mil or smaller in diameter should be
used to thermally couple the thermal pad to the bot­tom plane. For good thermal conduction, the vias must
be plated through and solder filled. The copper plane
used to conduct heat away from the thermal pad
should be as large as practical.
If the ambient temperature is higher than 25°C, a
larger copper plane or forced-air cooling will be re­quired to keep the APA4838 junction temperature
below the thermal shutdown temperature (150°C).
In higher ambient temperature, higher airflow rate and/
or larger copper area will be required to keep the IC
out of thermal shutdown.

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw25

APA4838

φ

φ

Packaging Information

TS SO P/ T S SO P-P ( Refe re n c e JED EC Re g istratio n MO-1 53 )

e

N

2 x E / 2

E1 E

12

3

e/2

EXPOSED THERMAL

PAD ZONE

D

b

D1

A2

A

A1

E2

0.25

(3)

S

(2)

(L1)

L

GAUGE

PLANE

1

BOTTOM VIEW

Millime te rs Inc h e s

Dim

(THERMALLY ENHANCED VARIATIONDS ONLY)

Min. Max. Min. Max.

A1.20.047
A1 0.00 0.15 0.000 0.006
A2 0.80 1.05 0.031 0.041

b 0.1 9 0.3 0.0 07 0.0 1 2

D

D1

6.4 (N=20PIN)

7.7 (N=24PIN)

9.6 (N=28PIN)

4.2 BSC (N=20P IN)

4.7 BSC (N=24P IN)

3.8 BSC (N=28P IN)

6.6 (N=20PIN)

7.9 (N=24PIN)

9.8 (N=28PIN)

0.252 (N=20PIN)

0.303 (N=24PIN)

0.378 (N=28PIN)

0.165 BSC (N=20PIN)

0.188 BSC (N=24PIN)

0.150 BSC (N=28PIN)

0.260 (N=20PIN)

0.311 (N=24PIN)

0.386 (N=28PIN)

e 0.65 BS C 0.026 BS C

E 6.40 B S C 0.252 BS C
E1 4.30 4.50 0.169 0.177
E2 3.0 BSC (N=20PIN)

3.2 BSC (N=24P IN)

2.8 BSC (N=28P IN)

0.118 BSC (N=20P IN)

0.127 BSC (N=24PIN)

0.110 BSC (N=28P IN)

L 0.4 5 0.7 5 0.0 1 8 0.0 30

L1 1.0 REF 0.039REF

R 0.0 9 0.00 4

R1 0.09 0.004

S0.2 0.008

10°8
212

REF 12° REF

°

°

0

°

8

°

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw26

APA4838

Physical Specifications

Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Lead So ld e rability Meets EIA Specification RS I86-91, AN S I/J - S TD-002 Category 3.

Reflow Condition (IR/Convection or VPR Reflow)

Reference JEDEC Standard J-STD-020A APRIL 1999

Peak temperature

temperature

Pre-heat temperature

°

183 C

Classification R e flow Profiles

Convection or IR/

Convection

Average ramp-up rate(183°C to Peak) 3°C/second max. 10 °C /second max.
Preheat temperature 125 ± 25°C)
Temper atur e m ainta ined abov e 183°C
Time within 5°C of actual peak temperature
Peak temperature range
Ramp-down rate
Time 25°C to peak temperature

120 seconds max
60 – 150 seconds
10 –20 seconds 60 seconds
220 +5/-0°C or 235 +5/-0°C 215-219°C or 235 +5/-0°C
6 °C /second max. 10 °C /second max.
6 minutes max.

VPR

Time

Package Reflow Conditions

pkg. thickness ≥≥≥≥ 2.5mm
and all bgas

Convection 220 +5/-0 °C Convection 235 +5/-0 °C
VPR 215-219 °C VPR 235 +5/-0 °C
IR/Convection 220 +5/-0 °C IR/Convection 235 +5/-0 °C

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

pkg. thickness < 2.5mm and
pkg. volume ≥≥≥≥ 350 mm³

pkg. thickness < 2.5mm and pkg.
volume < 350mm³

www.anpec.com.tw27

APA4838

Reliability test pro gram

Test item Method Description

SOLDERABILITY MIL-STD-883D-2003
HOLT MIL-STD-883D-1005.7
PCT JESD-22-B, A102
TST MIL-STD-883D-1011.9
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-U p JE SD 78 10ms , Itr > 100mA

245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C

-65°C ~ 150°C, 200 C y c les

Carrier Tape & Reel Dimensions

E

Po

F

W

A

P

P1

Ao

J

t

D

Bo

Ko

D1

T2

C

B

Application

TSSOP- 28

A B C J T1 T2 W P E

330 ±1 100 ref 13 ±0.5 2 ±0.5 16.4 ±0.2 2 ±0.2 16 ±0.3 12 ±0.1 1.75±0.1

F D D1 Po P1 Ao Bo Ko t

7.5 ±0.1 1.5 +0.1 1.5 min 4.0 ±0.1 2.0 ±0.1 6.9 ±0.1 10.2 ±0.1 1.8 ±0.1 0.3±0.05

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

T1

(mm)

www.anpec.com.tw28

APA4838

Cover Tape Dimensions

Application Carrier Width Cover Tape Width Devices Per Reel

TSSOP- 28

Customer Service

Anpec Electronics Corp.

Head Office :

5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : [phone]
Fax : [phone]

Taipei Branch :

7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : [phone]
Fax : [phone]

16 21.3 2000

Copyright  ANPEC Electronics Corp.
Rev. A.1 - Apr., 2003

www.anpec.com.tw29