Analog Devices SSM2301CPZ, SSM2301RMZ Schematic [ru]

Filterless High Efficiency

Mono 1.4 W Class-D Audio Amplifier

FEATURES

Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers

from Analog Devices, Inc.

1.4 W into 8 Ω at 5.0 V supply with less than 1% THD + N
85% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Greater than 98 dB SNR (signal-to-noise ratio)
Single-supply operation from 2.5 V to 5.0 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 8-lead, 3 mm × 3 mm LFCSP and MSOP packages
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations

APPLICATIONS

Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys

GENERAL DESCRIPTION

The SSM2301 is a fully integrated, high efficiency, Class-D audio
amplifier designed to maximize performance for mobile phone
applications. The application circuit requires a minimum of
external components and operates from a single 2.5 V to 5.0 V
supply. It is capable of delivering 1.4 W of continuous output
power with less than 1% THD + N driving an 8 Ω load from
a 5.0 V supply.

The SSM2301 features a high efficiency, low noise modulation
scheme that does not require external LC output filters. The modu­lation provides high efficiency even at low output power.

SSM2301

The SSM2301 operates with 85% efficiency at 1.4 W into 8 Ω
from a 5.0 V supply and has a signal-to-noise ratio (SNR) that
is greater than 98 dB. Spread-spectrum modulation is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures.

The SSM2301 has a micropower shutdown mode with a maximum
shutdown current of 30 nA. Shutdown is enabled by applying
a logic low to the

The device also includes pop-and-click suppression circuitry.
This minimizes voltage glitches at the output during turn-on
and turn-off, thus reducing audible noise on activation and
deactivation.

The fully differential input of the SSM2301 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately V

The SSM2301 also has excellent rejection of power supply noise,
including noise caused by GSM transmission bursts and RF
rectification. PSRR is typically 63 dB at 217 Hz.

The gain can be set to 6 dB or 12 dB by utilizing the gain control
select pin connected respectively to ground or to VDD. Gain
can also be adjusted externally by inserting a resistor in series
with each input pin.

The SSM2301 is specified over the commercial temperature range
(−40°C to +85°C). It has built-in thermal shutdown and output
short-circuit protection. It is available in both an 8-lead, 3 mm ×
3 mm lead-frame chip scale package (LFCSP) and an 8-lead
MSOP package.

SD

DD

pin.

/2.

FUNCTIONAL BLOCK DIAGRAM

SSM2301

1

0.01µF

AUDIO IN+

AUDIO IN–

SHUTDOWN

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

IN+

IN–

1

0.01µF
GAIN

SD

NOTES

1

INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V

GAIN

CONTROL

DD

10µF

BIAS

/2.

Figure 1.

VBATT

VDD

GND

2.5V TO 5. 0V

FET

DRIVER

POP/CLICK

SUPPRESSION

OUT+

OUT–

06163-001

0.1µF

MODULATOR

OSCILLAT OR

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

SSM2301

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Applicat i o n C i rc uits ......................................................... 10

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution.................................................................................. 4

Pin Configurations and Function Descriptions ........................... 5

Typical Performance Characteristics ............................................. 6

REVISION HISTORY

10/07—Rev. 0 to Rev. A

Added MSOP Package.......................................................Universal

Changes to Features.......................................................................... 1

Changes to General Description .................................................... 1

Changes to Table 1............................................................................ 3

Deleted Evaluation Board Information Section ......................... 14

Updated Outline Dimensions....................................................... 14

Changes to Ordering Guide.......................................................... 14

Applications Information.............................................................. 12

Overview ..................................................................................... 12

Gain Selection............................................................................. 12

Pop-and-Click Suppression ...................................................... 12

Layout .......................................................................................... 12

Input Capacitor Selection.......................................................... 12

Proper Power Supply Decoupling ............................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

1/07—Revision 0: Initial Version

Rev. A | Page 2 of 16

SSM2301

SPECIFICATIONS

VDD = 5.0 V, TA = 25oC, RL = 8 Ω + 33 μH, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DEVICE CHARACTERISTICS

Output Power P

O

VDD = 5.0 V, RL = 8 Ω, THD = 1%
f = 1 kHz, 20 kHz BW

= 5.0 V, RL = 8 Ω, THD = 10%

V

DD

f = 1 kHz, 20 kHz BW

= 3.6 V, RL = 8 Ω, THD = 1%

V

DD

f = 1 kHz, 20 kHz BW

V

= 3.6 V, RL = 8 Ω, THD = 10%

DD

f = 1 kHz, 20 kHz BW

= 2.5 V, RL = 8 Ω, THD = 1%

V

DD

f = 1 kHz, 20 kHz BW

= 2.5 V, RL = 8 Ω, THD = 10%

V

DD

f = 1 kHz, 20 kHz BW

Efficiency η P

= 1.4 W, 8 Ω, VDD = 5.0 V 85 %

OUT

Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V 0.1 %
P
Input Common-Mode Voltage Range V
Common-Mode Rejection Ratio CMRR
Average Switching Frequency f
Differential Output Offset Voltage V

CM

GSMVCM

SW

OOS

= 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.04 %

O

1.0 VDD − 1.0 V
= 2.5 V ± 100 mV at 217 Hz 55 dB

1.8 MHz

G = 6 dB; G = 12 dB 2.0 mV

POWER SUPPLY

Supply Voltage Range V

DD

Guaranteed from PSRR test 2.5 5.0 V
Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, dc input floating/ground 70 85 dB
PSRR

Supply Current I

SY

V
V
Shutdown Current I

SD

V

GSM

= 100 mV at 217 Hz, inputs are ac grounded,

RIPPLE

C

= 0.01 μF, input referred

IN

VIN = 0 V, no load, VDD = 5.0 V 4.2 mA

= 0 V, no load, VDD = 3.6 V 3.5 mA

IN

= 0 V, no load, VDD = 2.5 V 2.9 mA

IN

SD = GND

GAIN CONTROL

Closed-Loop Gain AV0 GAIN pin = 0 V 6 dB
A
Differential Input Impedance Z

1 GAIN pin = V

V

IN

SD = VDD, SD = GND

DD

210 kΩ

SHUTDOWN CONTROL

Input Voltage High V
Input Voltage Low V
Turn-On Time t
Turn-Off Time t

Output Impedance Z

IH

IL

WU

SD

OUT

ISY ≥ 1 mA 1.2 V

ISY ≤ 300 nA 0.5 V

SD rising edge from GND to V

DD

SD falling edge from VDD to GND

SD = GND

NOISE PERFORMANCE

Output Voltage Noise e

n

Signal-to-Noise Ratio SNR P

VDD = 2.5 V to 5.0 V, f = 20 Hz to 20 kHz, inputs are

ac grounded, sine wave, A

= 1.4 W, RL = 8 Ω 98 dB

OUT

= 6 dB, A weighting

V

1.22 W

1.52 W

590 mW

775 mW

275 mW

345 mW

63 dB

20 nA

12 dB
150 kΩ

30 ms
5 μs
>100 kΩ

35 μV

Rev. A | Page 3 of 16

SSM2301

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C

DD

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

8-lead, 3 mm × 3 mm LFCSP 62 20.8 °C/W
8-lead MSOP 210 45 °C/W

θ

JA

Unit

JC

ESD CAUTION

Rev. A | Page 4 of 16

SSM2301

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

2GAIN

SSM2301

3IN+

(Not to Scale)

4IN–

PIN 1
INDICAT OR

TOP VIEW

8OUT–

7GND

6VDD

5OUT+

06163-002

SD 1

Figure 2. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

SD

Shutdown Input. Active low digital input.

2 GAIN Gain Selection. Digital input.
3 IN+ Noninverting Input.
4 IN− Inverting Input.
5 OUT+ Noninverting Output.
6 VDD Power Supply.
7 GND Ground.
8 OUT− Inverting Output.

SD 1

GAIN

IN+

IN– 4

SSM2301

2

TOP VIEW

3

(Not to Scale)

OUT–8

7

GND

6

VDD

OUT+5

Figure 3. MSOP Pin Configuration

6163-103

Rev. A | Page 5 of 16

SSM2301

TYPICAL PERFORMANCE CHARACTERISTICS

100

THD + N (%)

0.1

RL = 8Ω, 15µH
GAIN = 6dB

10

1

VDD = 2.5V

VDD = 3.6V

VDD = 5V

100

0.1

THD + N (%)

0.01

0.001

VDD = 5.0V
GAIN = 12dB
R

L

10

1

= 8Ω, 15µH

0.5W
1W

0.25W

0.01

0.0001 10

100

10

1

THD + N (%)

0.1

0.01

0.0001 10

100

10

0.001 0.01 0.1 1

OUTPUT POWER (W)

Figure 4. THD + N vs. Output Power into 8 Ω, A

RL = 8Ω, 15µH
GAIN = 12dB

VDD = 2.5V

VDD = 3.6V

0.001 0.01 0.1 1

OUTPUT POWER (W)

Figure 5. THD + N vs. Output Power into 8 Ω, A

VDD = 5.0V
GAIN = 6dB
R

= 8Ω, 15µH

L

= 6 dB

V

VDD = 5V

= 12 dB

V

0.0001
10 100k

06163-004

Figure 7. THD + N vs. Frequency, V

100

VDD = 3.6V
GAIN = 6dB
R

= 8Ω, 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001

0.0001
10 100k

06163-003

Figure 8. THD + N vs. Frequency, V

100

VDD = 3.6V
GAIN = 12dB
R

= 8Ω, 15µH

L

10

100 1k 10k

FREQUENCY (Hz)

= 5.0 V, AV = 12 dB, RL = 8 Ω

DD

0.5W

0.25W

0.125W

100 1k 10k

FREQUENCY (Hz)

= 3.6 V, AV = 6 dB, RL = 8 Ω

DD

06163-008

6163-009

1

0.1

THD + N (%)

0.01

0.001

0.0001
10 100k

0.5W

100 1k 10k

Figure 6. THD + N vs. Frequency, V

1W

0.25W

FREQUENCY (Hz)

= 5.0 V, AV = 6 dB, RL = 8 Ω

DD

06163-007

Rev. A | Page 6 of 16

1

0.1

THD + N (%)

0.01

0.001

0.0001
10 100k

Figure 9. THD + N vs. Frequency, V

0.5W

0.25W

0.125W

100 1k 10k

FREQUENCY (Hz)

= 3.6 V, AV = 12 dB, RL = 8 Ω

DD

6163-010