Analog Devices AD7305YR, AD7305BRU, AD7305BR, AD7305BN, AD7304YR Datasheet

+3 V/+5 V, Rail-to-Rail

a

FEATURES
Four 8-Bit DACs in One Package
+3 V, +5 V and 5 V Operation
Rail-to-Rail REF-Input to Voltage Output Swing

2.6 MHz Reference Multiplying Bandwidth
Compact 1.1 mm Height TSSOP 16-/20-Lead Package
Internal Power ON Reset
SPI Serial Interface Compatible—AD7304
Fast Parallel Interface—AD7305
40 A Power Shutdown

APPLICATIONS
Automotive Output Span Voltage
Instrumentation, Digitally Controlled Calibration
Pin-Compatible AD7226 Replacement when V

GENERAL DESCRIPTION

The AD7304/AD7305 are quad, 8-bit DACs that operate from a
single +3 V to +5 V supply or ±5 V supplies. The AD7304 has a
serial interface, while the AD7305 has a parallel interface. Inter­nal precision buffers swing rail-to-rail. The reference input range
includes both supply rails allowing for positive or negative full­scale output voltages. Operation is guaranteed over the supply
voltage range of +2.7 V to +5.5 V, consuming less than 9 mW
from a +3 V supply.

The full-scale voltage output is determined by the external refer­ence input voltage applied. The rail-to-rail V
V

allows for a full-scale voltage set equal the positive supply

OUT

V

, the negative supply VSS or any value in between.

DD

input to DAC

REF

The AD7304’s doubled-buffered serial-data interface offers high
speed, three-wire, SPI and microcontroller compatible inputs
using data in (SDI), clock (CLK) and chip select (CS) pins.
Additionally, an internal power-on reset sets the output to zero
scale.

The parallel input AD7305 uses a standard address decode
along with the WR control line to load data into the input regis­ters. The double buffered architecture allows all four input
registers to be preloaded with new values, followed by a LDAC
control strobe which copies all the new data into the DAC regis­ters thereby updating the analog output values. When operating
from less than +5.5 V, the AD7305 is pin-compatible with the
popular industry standard AD7226.

< 5.5 V

DD

Quad, 8-Bit DAC

AD7304/AD7305*

FUNCTIONAL BLOCK DIAGRAMS

V

B V

REF

REF

DAC A

DAC B

DAC C

DAC D

DAC A

DAC B

DAC C

DAC D

V

SS

A

AD7304

D

AD7305

GND

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

CS

SDI/SHDN

CLK

DB0
DB1
DB2
DB3
DB4
DB5
DB6

WR

A0/SHDN

A1

V

DD

PWR ON

RESET

SERIAL

REG

V

SS

PWR ON

RESET

DECODE

8 8

INPUT
REG A

8

GND

V

DD

8

INPUT
REG B

INPUT
REG C

INPUT
REG D

INPUT

REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

8 8

8 8

8 8

CLR

8

8

8

8 8

DAC A

REG

DAC B

REG

DAC C

REG

DAC D

REG

LDAC

DAC A

REG

DAC B

REG

DAC C

REG

DAC D

REG

LDAC

REF

V

REFCVREF

V

8

8

8

An internal power ON reset places both parts in the zero-scale
state at turn ON. A 40 µA power shutdown (SHDN) feature is
activated on both parts by tristating the SDI/SHDN pin on the
AD7304, and tristating the A0/SHDN address pin on the
AD7305.

The AD7304/AD7305 are specified over the extended industrial
(–40°C to +85°C), and the automotive (–40°C to +125°C)
temperature ranges. AD7304s are available in 16-lead plastic
DIP (N-16), and wide-body SOL-16 (R-16) packages. The
parallel input AD7305 is available in the 20-lead plastic DIP
(N-20), and the SOL-20 (R-20) surface mount package. For
ultracompact applications the thin 1.1 mm TSSOP-16 (RU-16)
package will be available for the AD7304, while the TSSOP-20
(RU-20) will house the AD7305.

*Protected under Patent Number 5684481.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

(@ V

= +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, V

DD

≤ V

AD7304/AD7305–SPECIFICATIONS

≤ VDD, –40C < TA < +85C/+125C, unless otherwise noted.)

REF

Parameter Symbol Condition 3 V  10% 5 V  10% 5 V  10% Units

STATIC PERFORMANCE

Resolution
Integral Nonlinearity
Differential Nonlinearity DNL Monotonic, All Codes 0 to FF
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Tempco

1

2

3

N 8 8 8 Bits
INL ±1 ±1 ±1 LSB max

±1 ±1 ±1 LSB max
15 15 ± 15 mV max
±4 ±4 ±4 LSB max
55 5 ppm/°C typ

ZSE

FSE

TCV

Data = 00
Data = FF

FS

H

H

H

REFERENCE INPUT

V

Range V

REFIN

Input Resistance (AD7304) R
Input Resistance (AD7305) R
Input Capacitance

3

C

REFIN

REFIN

REFIN

REFIN

Code = 55

H

All DACs at Code = 55

H

VSS/V

DDVSS/VDD

VSS/V

DD

V min/max

28 28 28 kΩ typ

7.5 7.5 7.5 kΩ typ
5 5 5 pF typ

ANALOG OUTPUTS

Output Voltage Range V
Output Current Drive I
Shutdown Resistance R
Capacitive Load

3

C

OUT

OUT

OUT

L

Code = 80H, ∆V

< 1 LSB ± 3 ±3 ±3 mA typ

OUT

DAC Outputs Placed in Shutdown State 120 120 120 kΩ typ
No Oscillation 200 200 200 pF typ

VSS/V

DDVSS/VDD

VSS/V

DD

V min/max

LOGIC INPUTS

Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current
Input Capacitance

AC CHARACTERISTICS

5

3

3

IL

IH

I

IL

C

IL

Output Slew Rate SR Code = 00H to FFH to 00
Reference Multiplying BW Small Signal, V
Total Harmonic Distortion THD V
Settling Time
Shutdown Recovery Time t
Time to Shutdown t

6

t

S

SDR

SDN

= 4 V p-p, VSS = –5 V, f = 1 kHz 0.025 %

REF

To ±0.1% of Full Scale 1.1/2 1.0/2 1.0/2 µs typ/max
To ±0.1% of Full Scale 2 2 2 µs max

= –5 V 2.6 MHz typ

SS

H

0.6 0.8 0.8 V min

2.1 2.4 2.4 V max
±10 ±10 ± 10 µA max
8 8 8 pF max

1/2.7 1/3.6 1/3.6 V/µs min/typ

15 15 15 µs typ

DAC Glitch Q 15 15 15 nVs typ
Digital Feedthrough Q 2 2 2 nVs typ
Feedthrough V

OUT/VREF

Code = 00H, V

=1 V p-p, f = 100 kHz –65 dB

REF

SUPPLY CHARACTERISTICS

Positive Supply Current I
Negative Supply Current I
Power Dissipation P
Power Down I

DD

SS

DISS

DD_SD

V

= 0 V or VDD, No Load 6 6 6 mA max

LOGIC

VSS = –5 V 6 mA max
V

= 0 V or VDD, No Load 15 30 60 mW max

LOGIC

SDI/SHDN = Floating 40 40 40 µA typ

Power Supply Sensitivity PSS ∆VDD = ±10% 0.004 0.004 0.004 %/%

NOTES

1

One LSB = V

2

The first three codes (00H, 01H, 10H) are excluded from the integral nonlinearity error measurement in single supply operation +3 V or +5 V.

3

These parameters are guaranteed by design and not subject to production testing.

4

Typicals represent average readings measured at +25°C.

5

SDI/SHDN and A0/SHDN pins have 30 µA maximum IIL input leakage current.

6

The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation.

Specifications subject to change without notice.

REF

/256.

SS

4

5V

V

= 10V p-p

REF

f = 20kHz

5V

0V

V

= 10V p-p

OUT

–5V

(OUT) (IN)

0V

–5V

Figure 1. AD7304/AD7305 Rail-to-Rail Reference Input to Output at 20 kHz

–2–

REV. A

AD7304/AD7305

WARNING!

ESD SENSITIVE DEVICE

TIMING SPECIFICATIONS

(@ VDD = +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, V
+85C/125C, unless otherwise noted.)

≤ V

≤ VDD, –40C < TA <

SS

REF

Parameter Symbol 3 V  10% 5 V  10% 5 V  10% Units

INTERFACE TIMING SPECIFICATIONS

1, 2

AD7304 Only

Clock Width High t
Clock Width Low t
Data Setup t
Data Hold t
Load Pulsewidth t
Load Setup t
Load Hold t
Clear Pulsewidth t
Select t
Deselect t

CH

CL

DS

DH

LDW

LD1

LD2

CLWR

CSS

CSH

70 55 55 ns min
70 55 55 ns min
50 40 40 ns min
30 20 20 ns min
70 60 60 ns min
40 30 30 ns min
40 30 30 ns min
60 60 60 ns min
30 20 20 ns min
60 40 40 ns min

AD7305 Only

Data Setup t
Data Hold t
Address Setup t
Address Hold t
Write Width t
Load Pulsewidth t
Load Setup t
Load Hold t

NOTES

1

These parameters are guaranteed by design and not subject to production testing.

2

All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

DS

DH

AS

AH

WR

LDW

LS

LH

ABSOLUTE MAXIMUM RATINGS*

60 40 40 ns min
30 20 20 ns min
60 40 40 ns min
30 20 20 ns min
60 50 50 ns min
60 50 50 ns min
60 40 40 ns min
30 20 20 ns min

ORDERING GUIDE

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –8 V

SS

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

REFX

Logic Inputs to GND . . . . . . . . . . . . . . . –0.3 V, V

V

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

OUTX

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA

I

OUT

Package Power Dissipation . . . . . . . . . . . . . . (T

Thermal Resistance θ

JA

+ 0.3 V

DD

J MAX–TA

16-Lead Plastic DIP Package (N-16) . . . . . . . . . . 103°C/W

16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . . 73°C/W

TSSOP-16 Package (RU-16) . . . . . . . . . . . . . . . . 180°C/W

20-Lead Plastic DIP Package (N-20) . . . . . . . . . . 120°C/W

20-Lead SOIC Package (R-20) . . . . . . . . . . . . . . . 74°C/W

TSSOP-20 Package (RU-20) . . . . . . . . . . . . . . . . 155°C/W

Maximum Junction Temperature (T

) . . . . . . . . .+150°C

J MAX

)/θ

DD

Model Range Description Options

AD7304BN –40°C/+85°C 16-Lead P-DIP N-16
AD7304BR –40°C/+85°C 16-Lead SOIC R-16
AD7304YR –40°C/+125°C 16-Lead SOIC R-16

JA

AD7304BRU –40°C/+85°C TSSOP-16 RU-16
AD7305BN –40°C/+85°C 20-Lead P-DIP N-20

AD7305BR –40°C/+85°C 20-Lead SOIC R-20
AD7305YR –40°C/+125°C 20-Lead SOIC R-20
AD7305BRU –40°C/+85°C TSSOP-20 RU-20

The AD7304/AD7305 contains 2759 transistors. Die size: 103 mil × 102 mil,
10,506 sq mil.

Temperature Package Package

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature

N-16 and N-20 (Soldering, 10 secs) . . . . . . . . . . . .+300°C

R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 secs) . . +215°C

R-16, R-20, RU-16, RU-20 (Infrared, 15 secs) . . . .+220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7304/AD7305 features proprietary ESD protection circuitry, permanent dam­age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

AD7304/AD7305

V

LDAC

LDAC

OUT

SDI

CLK

CS

SDI

CLK

CLR

SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

t

CSS

t

LD1

tDSt

t

CL

FS

ZS

DH

t

CH

t

LDW

t

S

t

CSH

1 LSB

ERROR BAND

t

LD2

t

CLRW

t

S

Figure 2. AD7304 Timing Diagram

t

SDN

SDI/SHDN

t

SDR

I

DD

Figure 3. AD7304 Timing Diagram

Table I. AD7304 Control Logic Truth Table

CS CLK LDAC CLR Serial Shift Register Function Input REG Function DAC Register Function

H X H H No Effect No Effect No Effect
L ↑+ H H Data Advanced 1 Bit No Effect No Effect
↑+ L H H No Effect Updated with SR Contents
H X L H No Effect Latched with SR Contents
HXH ↓– No Effect Loaded with 00
HXH ↑+ No Effect Latched with 00

NOTES

1

↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.

2

One Input Register receives the data bits D7–D0 decoded from the SR address bits (A1, A0); where REG A = (0, 0); B = (0, 1); C = (1, 0); D = (1, 1).

3

LDAC is a level-sensitive input.

H

H

2

No Effect

2

All Input Register Contents Transferred
Loaded with 00
Latched with 00

H

H

Table II. AD7304 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB LSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

AD7304 SAC SDC A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

If B11 (SAC), Shutdown All Channels, is set to logic LOW, all DACs are placed in a power shutdown mode, all output voltages become high resistance. If B10 (SDC),
Shutdown Decoded Channel, is set to logic LOW, only the DAC decoded by address bits A1 and A0 is placed in the shutdown mode.

3

–4–

REV. A

AD7304/AD7305

Table III. AD7305 Control Logic Truth Table

WR A1 A0 LDAC Input Register Function DAC Register Function

LLLH REG A Loaded with DB0–DB7 Latched with Previous Contents, No Change
↑+ L L H REG A Latched with DB0–DB7 Latched with Previous Contents, No Change
L L H H REG B Loaded with DB0–DB7 Latched with Previous Contents, No Change
↑+ L H H REG B Latched with DB0–DB7 Latched with Previous Contents, No Change
L H L H REG C Loaded with DB0–DB7 Latched with Previous Contents, No Change
↑+ H L H REG C Latched with DB0–DB7 Latched with Previous Contents, No Change
L H H H REG D Loaded with DB0–DB7 Latched with Previous Contents, No Change
↑+ H H H REG D Latched with DB0–DB7 Latched with Previous Contents, No Change
H X X L No Effect All Input Register Contents Loaded, Register Transparent
L X X L Input REG x Transparent to DB0–DB7 Register Transparent
HXX↑+ No Effect All Input Register Contents Latched
H X X H No Effect, Device Not Selected No Effect, Device Not Selected

NOTES

1

↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.

2

LDAC is a level sensitive input.

PIN CONFIGURATIONS

A0/SHDN

I

t

WR

WR

t

t

AS

AH

A0, A1

t

t

DS

DH

D0–D7

LDAC

V

OUT

t

LS

t

LH

t

S

Figure 4. AD7305 Timing Diagram

t

SDN

DD

Figure 5. AD7305 Timing Diagram

t

LDW

1 LSB

ERROR BAND

t

SDR

V

OUT

V

OUT

V

REF

V

REF

GND

LDAC

V

CLR

SS

1

B

2

A

3

4

A

5

B

6

7

8

AD7304

TOP VIEW

(Not to Scale)

16

V

V

15

14

V

13

V

12

V

11

SDI/SHDN

10

CLK

9

CS

OUT

OUT

DD

REF

REF

1

V

B

OUT

2

V

C

D

C

D

OUT

V

V

REF

GND

LDAC

DB7

DB6

DB5

DB4

A

SS

10

3

4

5

AD7305

TOP VIEW

6

(Not to Scale)

7

8

9

20

19

18

17

16

15

14

13

12

11

V

C

OUT

V

D

OUT

V

DD

A0/SHDN

A1

WR

DB0

DB1

DB2

DB3

REV. A

–5–