Analog Devices AD7305, AD7304 Datasheet

+3 V/+5 V, Rail-to-Rail

a

FEATURES
Four 8-Bit DACs in One Package
+3 V, +5 V and 5 V Operation
Rail-to-Rail REF-Input to Voltage Output Swing

2.6 MHz Reference Multiplying Bandwidth
Compact 1.1 mm Height TSSOP 16-/20-Lead Package
Internal Power ON Reset
SPI Serial Interface Compatible—AD7304
Fast Parallel Interface—AD7305
40 A Power Shutdown

APPLICATIONS
Automotive Output Span Voltage
Instrumentation, Digitally Controlled Calibration
Pin-Compatible AD7226 Replacement when V

GENERAL DESCRIPTION

The AD7304/AD7305 are quad, 8-bit DACs that operate from a
single +3 V to +5 V supply or ±5 V supplies. The AD7304 has a
serial interface, while the AD7305 has a parallel interface. Inter­nal precision buffers swing rail-to-rail. The reference input range
includes both supply rails allowing for positive or negative full­scale output voltages. Operation is guaranteed over the supply
voltage range of +2.7 V to +5.5 V, consuming less than 9 mW
from a +3 V supply.

The full-scale voltage output is determined by the external refer­ence input voltage applied. The rail-to-rail V
V

allows for a full-scale voltage set equal the positive supply

OUT

V

, the negative supply VSS or any value in between.

DD

input to DAC

REF

The AD7304’s doubled-buffered serial-data interface offers high
speed, three-wire, SPI and microcontroller compatible inputs
using data in (SDI), clock (CLK) and chip select (CS) pins.
Additionally, an internal power-on reset sets the output to zero
scale.

The parallel input AD7305 uses a standard address decode
along with the WR control line to load data into the input regis­ters. The double buffered architecture allows all four input
registers to be preloaded with new values, followed by a LDAC
control strobe which copies all the new data into the DAC regis­ters thereby updating the analog output values. When operating
from less than +5.5 V, the AD7305 is pin-compatible with the
popular industry standard AD7226.

< 5.5 V

DD

Quad, 8-Bit DAC

AD7304/AD7305*

FUNCTIONAL BLOCK DIAGRAMS

V

B V

REF

REF

DAC A

DAC B

DAC C

DAC D

DAC A

DAC B

DAC C

DAC D

V

SS

A

AD7304

D

AD7305

GND

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

CS

SDI/SHDN

CLK

DB0
DB1
DB2
DB3
DB4
DB5
DB6

WR

A0/SHDN

A1

V

DD

PWR ON

RESET

SERIAL

REG

V

SS

PWR ON

RESET

DECODE

8 8

INPUT
REG A

8

GND

V

DD

8

INPUT
REG B

INPUT
REG C

INPUT
REG D

INPUT

REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

8 8

8 8

8 8

CLR

8

8

8

8 8

DAC A

REG

DAC B

REG

DAC C

REG

DAC D

REG

LDAC

DAC A

REG

DAC B

REG

DAC C

REG

DAC D

REG

LDAC

REF

V

REFCVREF

V

8

8

8

An internal power ON reset places both parts in the zero-scale
state at turn ON. A 40 µA power shutdown (SHDN) feature is
activated on both parts by tristating the SDI/SHDN pin on the
AD7304, and tristating the A0/SHDN address pin on the
AD7305.

The AD7304/AD7305 are specified over the extended industrial
(–40°C to +85°C), and the automotive (–40°C to +125°C)
temperature ranges. AD7304s are available in 16-lead plastic
DIP (N-16), and wide-body SOL-16 (R-16) packages. The
parallel input AD7305 is available in the 20-lead plastic DIP
(N-20), and the SOL-20 (R-20) surface mount package. For
ultracompact applications the thin 1.1 mm TSSOP-16 (RU-16)
package will be available for the AD7304, while the TSSOP-20
(RU-20) will house the AD7305.

*Protected under Patent Number 5684481.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

(@ V

= +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, V

DD

≤ V

AD7304/AD7305–SPECIFICATIONS

≤ VDD, –40C < TA < +85C/+125C, unless otherwise noted.)

REF

Parameter Symbol Condition 3 V  10% 5 V  10% 5 V  10% Units

STATIC PERFORMANCE

Resolution
Integral Nonlinearity
Differential Nonlinearity DNL Monotonic, All Codes 0 to FF
Zero-Scale Error V
Full-Scale Voltage Error V
Full-Scale Tempco

1

2

3

N 8 8 8 Bits
INL ±1 ±1 ±1 LSB max

±1 ±1 ±1 LSB max
15 15 ± 15 mV max
±4 ±4 ±4 LSB max
55 5 ppm/°C typ

ZSE

FSE

TCV

Data = 00
Data = FF

FS

H

H

H

REFERENCE INPUT

V

Range V

REFIN

Input Resistance (AD7304) R
Input Resistance (AD7305) R
Input Capacitance

3

C

REFIN

REFIN

REFIN

REFIN

Code = 55

H

All DACs at Code = 55

H

VSS/V

DDVSS/VDD

VSS/V

DD

V min/max

28 28 28 kΩ typ

7.5 7.5 7.5 kΩ typ
5 5 5 pF typ

ANALOG OUTPUTS

Output Voltage Range V
Output Current Drive I
Shutdown Resistance R
Capacitive Load

3

C

OUT

OUT

OUT

L

Code = 80H, ∆V

< 1 LSB ± 3 ±3 ±3 mA typ

OUT

DAC Outputs Placed in Shutdown State 120 120 120 kΩ typ
No Oscillation 200 200 200 pF typ

VSS/V

DDVSS/VDD

VSS/V

DD

V min/max

LOGIC INPUTS

Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current
Input Capacitance

AC CHARACTERISTICS

5

3

3

IL

IH

I

IL

C

IL

Output Slew Rate SR Code = 00H to FFH to 00
Reference Multiplying BW Small Signal, V
Total Harmonic Distortion THD V
Settling Time
Shutdown Recovery Time t
Time to Shutdown t

6

t

S

SDR

SDN

= 4 V p-p, VSS = –5 V, f = 1 kHz 0.025 %

REF

To ±0.1% of Full Scale 1.1/2 1.0/2 1.0/2 µs typ/max
To ±0.1% of Full Scale 2 2 2 µs max

= –5 V 2.6 MHz typ

SS

H

0.6 0.8 0.8 V min

2.1 2.4 2.4 V max
±10 ±10 ± 10 µA max
8 8 8 pF max

1/2.7 1/3.6 1/3.6 V/µs min/typ

15 15 15 µs typ

DAC Glitch Q 15 15 15 nVs typ
Digital Feedthrough Q 2 2 2 nVs typ
Feedthrough V

OUT/VREF

Code = 00H, V

=1 V p-p, f = 100 kHz –65 dB

REF

SUPPLY CHARACTERISTICS

Positive Supply Current I
Negative Supply Current I
Power Dissipation P
Power Down I

DD

SS

DISS

DD_SD

V

= 0 V or VDD, No Load 6 6 6 mA max

LOGIC

VSS = –5 V 6 mA max
V

= 0 V or VDD, No Load 15 30 60 mW max

LOGIC

SDI/SHDN = Floating 40 40 40 µA typ

Power Supply Sensitivity PSS ∆VDD = ±10% 0.004 0.004 0.004 %/%

NOTES

1

One LSB = V

2

The first three codes (00H, 01H, 10H) are excluded from the integral nonlinearity error measurement in single supply operation +3 V or +5 V.

3

These parameters are guaranteed by design and not subject to production testing.

4

Typicals represent average readings measured at +25°C.

5

SDI/SHDN and A0/SHDN pins have 30 µA maximum IIL input leakage current.

6

The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation.

Specifications subject to change without notice.

REF

/256.

SS

4

5V

V

= 10V p-p

REF

f = 20kHz

5V

0V

V

= 10V p-p

OUT

–5V

(OUT) (IN)

0V

–5V

Figure 1. AD7304/AD7305 Rail-to-Rail Reference Input to Output at 20 kHz

–2–

REV. A

AD7304/AD7305

WARNING!

ESD SENSITIVE DEVICE

TIMING SPECIFICATIONS

(@ VDD = +3 V or +5 V, VSS = 0 V; or VDD = +5 V and VSS = –5 V, V
+85C/125C, unless otherwise noted.)

≤ V

≤ VDD, –40C < TA <

SS

REF

Parameter Symbol 3 V  10% 5 V  10% 5 V  10% Units

INTERFACE TIMING SPECIFICATIONS

1, 2

AD7304 Only

Clock Width High t
Clock Width Low t
Data Setup t
Data Hold t
Load Pulsewidth t
Load Setup t
Load Hold t
Clear Pulsewidth t
Select t
Deselect t

CH

CL

DS

DH

LDW

LD1

LD2

CLWR

CSS

CSH

70 55 55 ns min
70 55 55 ns min
50 40 40 ns min
30 20 20 ns min
70 60 60 ns min
40 30 30 ns min
40 30 30 ns min
60 60 60 ns min
30 20 20 ns min
60 40 40 ns min

AD7305 Only

Data Setup t
Data Hold t
Address Setup t
Address Hold t
Write Width t
Load Pulsewidth t
Load Setup t
Load Hold t

NOTES

1

These parameters are guaranteed by design and not subject to production testing.

2

All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

DS

DH

AS

AH

WR

LDW

LS

LH

ABSOLUTE MAXIMUM RATINGS*

60 40 40 ns min
30 20 20 ns min
60 40 40 ns min
30 20 20 ns min
60 50 50 ns min
60 50 50 ns min
60 40 40 ns min
30 20 20 ns min

ORDERING GUIDE

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –8 V

SS

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

REFX

Logic Inputs to GND . . . . . . . . . . . . . . . –0.3 V, V

V

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

OUTX

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA

I

OUT

Package Power Dissipation . . . . . . . . . . . . . . (T

Thermal Resistance θ

JA

+ 0.3 V

DD

J MAX–TA

16-Lead Plastic DIP Package (N-16) . . . . . . . . . . 103°C/W

16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . . 73°C/W

TSSOP-16 Package (RU-16) . . . . . . . . . . . . . . . . 180°C/W

20-Lead Plastic DIP Package (N-20) . . . . . . . . . . 120°C/W

20-Lead SOIC Package (R-20) . . . . . . . . . . . . . . . 74°C/W

TSSOP-20 Package (RU-20) . . . . . . . . . . . . . . . . 155°C/W

Maximum Junction Temperature (T

) . . . . . . . . .+150°C

J MAX

)/θ

DD

Model Range Description Options

AD7304BN –40°C/+85°C 16-Lead P-DIP N-16
AD7304BR –40°C/+85°C 16-Lead SOIC R-16
AD7304YR –40°C/+125°C 16-Lead SOIC R-16

JA

AD7304BRU –40°C/+85°C TSSOP-16 RU-16
AD7305BN –40°C/+85°C 20-Lead P-DIP N-20

AD7305BR –40°C/+85°C 20-Lead SOIC R-20
AD7305YR –40°C/+125°C 20-Lead SOIC R-20
AD7305BRU –40°C/+85°C TSSOP-20 RU-20

The AD7304/AD7305 contains 2759 transistors. Die size: 103 mil × 102 mil,
10,506 sq mil.

Temperature Package Package

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature

N-16 and N-20 (Soldering, 10 secs) . . . . . . . . . . . .+300°C

R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 secs) . . +215°C

R-16, R-20, RU-16, RU-20 (Infrared, 15 secs) . . . .+220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7304/AD7305 features proprietary ESD protection circuitry, permanent dam­age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

AD7304/AD7305

V

LDAC

LDAC

OUT

SDI

CLK

CS

SDI

CLK

CLR

SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

t

CSS

t

LD1

tDSt

t

CL

FS

ZS

DH

t

CH

t

LDW

t

S

t

CSH

1 LSB

ERROR BAND

t

LD2

t

CLRW

t

S

Figure 2. AD7304 Timing Diagram

t

SDN

SDI/SHDN

t

SDR

I

DD

Figure 3. AD7304 Timing Diagram

Table I. AD7304 Control Logic Truth Table

CS CLK LDAC CLR Serial Shift Register Function Input REG Function DAC Register Function

H X H H No Effect No Effect No Effect
L ↑+ H H Data Advanced 1 Bit No Effect No Effect
↑+ L H H No Effect Updated with SR Contents
H X L H No Effect Latched with SR Contents
HXH ↓– No Effect Loaded with 00
HXH ↑+ No Effect Latched with 00

NOTES

1

↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.

2

One Input Register receives the data bits D7–D0 decoded from the SR address bits (A1, A0); where REG A = (0, 0); B = (0, 1); C = (1, 0); D = (1, 1).

3

LDAC is a level-sensitive input.

H

H

2

No Effect

2

All Input Register Contents Transferred
Loaded with 00
Latched with 00

H

H

Table II. AD7304 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB LSB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

AD7304 SAC SDC A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

If B11 (SAC), Shutdown All Channels, is set to logic LOW, all DACs are placed in a power shutdown mode, all output voltages become high resistance. If B10 (SDC),
Shutdown Decoded Channel, is set to logic LOW, only the DAC decoded by address bits A1 and A0 is placed in the shutdown mode.

3

–4–

REV. A

AD7304/AD7305

Table III. AD7305 Control Logic Truth Table

WR A1 A0 LDAC Input Register Function DAC Register Function

LLLH REG A Loaded with DB0–DB7 Latched with Previous Contents, No Change
↑+ L L H REG A Latched with DB0–DB7 Latched with Previous Contents, No Change
L L H H REG B Loaded with DB0–DB7 Latched with Previous Contents, No Change
↑+ L H H REG B Latched with DB0–DB7 Latched with Previous Contents, No Change
L H L H REG C Loaded with DB0–DB7 Latched with Previous Contents, No Change
↑+ H L H REG C Latched with DB0–DB7 Latched with Previous Contents, No Change
L H H H REG D Loaded with DB0–DB7 Latched with Previous Contents, No Change
↑+ H H H REG D Latched with DB0–DB7 Latched with Previous Contents, No Change
H X X L No Effect All Input Register Contents Loaded, Register Transparent
L X X L Input REG x Transparent to DB0–DB7 Register Transparent
HXX↑+ No Effect All Input Register Contents Latched
H X X H No Effect, Device Not Selected No Effect, Device Not Selected

NOTES

1

↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.

2

LDAC is a level sensitive input.

PIN CONFIGURATIONS

A0/SHDN

I

t

WR

WR

t

t

AS

AH

A0, A1

t

t

DS

DH

D0–D7

LDAC

V

OUT

t

LS

t

LH

t

S

Figure 4. AD7305 Timing Diagram

t

SDN

DD

Figure 5. AD7305 Timing Diagram

t

LDW

1 LSB

ERROR BAND

t

SDR

V

OUT

V

OUT

V

REF

V

REF

GND

LDAC

V

CLR

SS

1

B

2

A

3

4

A

5

B

6

7

8

AD7304

TOP VIEW

(Not to Scale)

16

V

V

15

14

V

13

V

12

V

11

SDI/SHDN

10

CLK

9

CS

OUT

OUT

DD

REF

REF

1

V

B

OUT

2

V

C

D

C

D

OUT

V

V

REF

GND

LDAC

DB7

DB6

DB5

DB4

A

SS

10

3

4

5

AD7305

TOP VIEW

6

(Not to Scale)

7

8

9

20

19

18

17

16

15

14

13

12

11

V

C

OUT

V

D

OUT

V

DD

A0/SHDN

A1

WR

DB0

DB1

DB2

DB3

REV. A

–5–

AD7304/AD7305

AD7304 PIN FUNCTION DESCRIPTIONS

Pin # Name Function

1V

B Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V

OUT

is open circuit when SHDN is enabled.

2V

A Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V

OUT

is open circuit when SHDN is enabled.
3VSSNegative Power Supply Input. Specified range of operation 0 V to –5.5 V.
4V
5V

A Channel A Reference Input. Establishes V

REF

B Channel B Reference Input. Establishes V

REF

A full-scale voltage. Specified range of operation V

OUT

B full-scale voltage. Specified range of operation V

OUT

SS

SS

6 GND Common Analog and Digital Ground.
7 LDAC Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous

active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.
8 CLR Clears all Input and DAC registers to the zero condition. Asynchronous active low input. The serial register is not effected .
9 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Input Register Data to the

decoded Input Register when CS returns HIGH. Does not effect LDAC operation.
10 CLK Clock input, positive edge clocks data into shift register. Disabled by chip select CS.
11 SDI/SHDN Serial Data-Input loads directly into the shift register, MSB first. Hardware shutdown (SHDN) control input, active

when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is

DD

.

D full-scale voltage. Specified range of operation V

OUT

C full-scale voltage. Specified range of operation V

OUT

SS

SS

12 V
13 V
14 V
15 V

present on V

D Channel D Reference Input. Establishes V

REF

C Channel C Reference Input. Establishes V

REF

DD

D Channel D rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V

OUT

Positive power supply input. Specified range of operation +2.7 V to +5.5 V.

is open circuit when SHDN is enabled.
16 V

C Channel C rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V

OUT

is open circuit when SHDN is enabled.

< V
< V

< V

< V

REF

REF

REF

REF

REF

REF

B pin. Output

A pin. Output

A < VDD.
B < VDD.

D < VDD.

C < VDD.

D pin. Output

REF

C pin. Output

REF

AD7305 PIN FUNCTION DESCRIPTIONS

Pin # Name Function

1V

B Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V

OUT

B pin. Output

REF

is open circuit when SHDN is enabled.
2V

A Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V

OUT

A pin. Output

REF

is open circuit when SHDN is enabled.
3V
4V

SS

REF

Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.

Channel B Reference Input. Establishes V

full-scale voltage. Specified range of operation V

OUT

SS

< V

REF

< VDD.

5 GND Common Analog and Digital Ground.
6 LDAC Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous

active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.
7 DB7 MSB Digital Input Data Bit.
8 DB6 Data Bit 6.
9 DB5 Data Bit 5.
10 DB4 Data Bit 4.
11 DB3 Data Bit 3.
12 DB2 Data Bit 2.
13 DB1 Data Bit 1.
14 DB0 LSB Digital Input Data Bit.
15 WR Write data into Input Register control line, active low. See Control Logic Truth Table for operation.
16 A1 Address Bit 1.
17 A0/SHDN Address Bit 0/Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver.

DD

.

D pin. Output

REF

18 V
19 V

Does not effect DAC register contents as long as power is present on V

DD

D Channel D rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V

OUT

Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.

is open circuit when SHDN is enabled.
20 V

C Channel C rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V

OUT

C pin. Output

REF

is open circuit when SHDN is enabled.

–6–

REV. A

CODE – Decimal

0.500

–0.500

0 25632

DNL – LSB

64 96 128 160 192 224

0.375

0.000

–0.125

–0.250

–0.375

0.250

0.125

VDD = +5V
V

SS

= –5V

V

REF

= 2.5V

TEMPERATURE – C

4.0

3.6

2.0
–55 125–35

ZERO SCALE VOLTAGE – mV

–155 25456585105

3.2

2.8

2.4

VDD = +5.5V
V

SS

= 0V

V

REF

= +5.45V

Typical Performance Characteristics–

AD7304/AD7305

144

120

96

72

SINK CURRENT – mA

48

OUT

I

24

0

0153

Figure 6. I

–35

–28

–21

VDD = +5V
V

= –5V

SS

V

= V

REF

DATA = 00

SINK vs. V

OUT

1.0

DD

H

6912

V

– mV

OUT

Rail-to-Rail Performance

OUT

VDD = +5V
V

= –5V

SS

V

= V

REF

DD

DATA = FF

H

0.6

DAC D

0.2

INL – LSB

–0.2

–0.6

–1.0

–5.0 5.0–3.0

VDD = +5V
V

= –5V

SS

DATA = 80
T

H

= +25C

A

REFERENCE INPUT VOLTAGE – Volts

DAC B

–1.0 1.0 3.0

DAC C

DAC A

Figure 9. INL vs. Reference Input Voltage

–14

SOURCE CURRENT – mA

OUT

I

–7

0

4.0 5.04.2

Figure 7. I

1

0

–1

1

0

–1

1

INL – LSB

0

–1

1

0

–1

Figure 8. INL vs. Code, All DAC Channels

SOURCE vs. V

OUT

025632

4.4 4.6 4.8

V

OUTPUT VOLTAGE – Volts

OUT

Rail-to-Rail Performance

OUT

DAC A

DAC B

DAC C

DAC D

64 96 128 160 192 224

CODE – Decimal

VDD = +5V
V

= –5V

SS

V

= +2.5V

REF

T

= +25C

A

Figure 10. DNL vs. Code

Figure 11. Zero Scale Voltage vs. Temperature

REV. A

–7–

AD7304/AD7305

= +5V

V

DD

V

= +4V

V

OUT

CS

REF

DATA = 00

2s/DIV

H

FF

Figure 12. Large-Signal Settling Time

V

REFIN

(5V @

50kHz)

V

OUTA

H

DATA = FF

NO LOAD

RL = 70k

RL = 10k

0V

VDD = +5V
C

= 150pF

L

5V

0V

5s/DIV

CS

V

OUT

Figure 15. Time to Shutdown

5V

H

0V

–5V

5V

0V

–5V

V

= +5V

DD

CS

I

DD

1mA/V

V

OUT

2s/DIV

Figure 13. Multiplying Mode Step Response and Output
Slew Rate

6

4

0

GAIN – dB

–4

–6

–8

10k 10M

FREQUENCY – Hz

f

–3dB

VDD = +5V
V

= –5V

SS

DATA = FF
V

= 100mV rms

REF

= 2.6MHz

1M100k

H

Figure 14. Multiplying Mode Gain vs. Frequency

Figure 16. Shutdown Recovery Time (Wakeup)

10

VDD = +5V
V

= –5V

1

0.1

THD – %

0.010

0.001
10m 101

23456 789

V

AMPLITUDE – V p-p

REF

SS

Figure 17. THD vs. Reference Input Amplitude

A

–8–

REV. A

AD7304/AD7305

FREQUENCY – Hz

60

0

10 100

PSRR – dB

1k 100k

50

40

30

20

10

10k

DATA = 80

H

TA = +25C

+PSRR, VDD = +5V  10%

–PSRR, VSS = –5V  10%

+PSRR, VDD = +3V  10%

–PSRR, VSS = –3V  10%

1

0.1

THD – %

0.010

0.001
20 100k100

VDD = +5V
V

= –5V

SS

1k 10k

FREQUENCY – Hz

A

Figure 18. THD vs. Frequency

3.0

VDD = +5V
V

= –5V

SS

V

= 4V

2.4

1.8

1.2

NOISE DENSITY – V/ Hz

0.6

0

1 100k10

100 1k 10k

FREQUENCY – Hz

REF

DATA = FF

H

Figure 19. Output Noise Voltage Density vs. Frequency

VDD = +5V
V

SS

V

V

OUT

CS

REF

F = 1MHz
DATA = 80

Figure 21. Midscale Transition Glitch

40

VDD = +5V

20

= –5V

V

SS

V

= 50mV rms

REF

0

DAC A DATA = FF
DAC B, C, D DATA = 00

–20

–40

–60

–80

CROSS TALK – dB

–100

–120

–140

–160

100 10M1k

H

H

CT = 20 LOG

10k 1M

FREQUENCY – Hz

100k

Figure 22. Crosstalk vs. Frequency

= –5V

= 2.5V

H

7F

V

V

H

OUTB

REF

REV. A

V

OUTB

CLK

Figure 20. Digital Feedthrough

= +5V

V

DD

V

= –5V

SS

V

= 2.5V

REF

DAC A = FF
DAC B = OO
F = 2MHz

50ns/DIV

H

H

Figure 23. Power Supply Rejection vs. Frequency

–9–

AD7304/AD7305

12

VDD = +5V
V

= –5V

10

8

6

4

SUPPLY CURRENT – mA

2

0

051

DIGITAL INPUT VOLTAGE – Volts

234

SS

V

= 2.5V

REF

A0 = 5V
ALL OTHER DIGITAL
PINS VARYING

I

DD

I

SS

Figure 24. Supply Current vs. Digital Input Voltage

10.0000

1.0000

VDD = +5V
V

= –5V

SS

V

= 2.5V

REF

ALL DIGITAL PINS VARY,
EXCEPT A0 = 5V

SS

0.1000

0.0100

SUPPLY CURRENT – mA

0.0010

I

DD

I

80

VDD = +5.5V
V

= –5.5V

SS

70

V

= 2.5V

REF

PIN A0 FLOATING

60

50

40

SHUTDOWN SUPPLY – A

30

20

–55 125–35

–155 25456585105

TEMPERATURE – C

Figure 27. Shutdown Supply Current vs. Temperature

0.08

READING MADE AT TA = +25C
SAMPLE SIZE = 924 UNITS

0.04

VDD = 2.7V

0

ERROR DRIFT – LSB

–0.04

NORMALIZED TOTAL UNADJUSTED

VDD = 5.5V

0.0001
051

234

DIGITAL INPUT VOLTAGE – Volts

Figure 25. Shutdown Supply Current vs. Digital Input
Voltage (A0 Only)

5.0

VDD = +5V
V

= –5V

SS

V

= 2.5V

REF

4.4

3.8

3.2

SUPPLY CURRENT – mA

2.6

2.0
–55 125–35

IDD AND I

SS

–155 25456585105

TEMPERATURE – C

Figure 26. Supply Current vs. Temperature

–0.08

084

168 252 336 420 504

DEGREES CELCIUS

Figure 28. Normalized TUE Drift Accelerated by Burn-In

°

Hours of Operation @ 150

C

–10–

REV. A

AD7304/AD7305

V

DD

V

SS

V

OUT

X

120k

Q1

Q2

CIRCUIT OPERATION

The AD7304/AD7305 are a set of four-channel, 8-bit, voltage­output, digital-to-analog converters differing primarily in digital
logic interface and number of reference inputs. Both parts share
the same internal DAC design and true rail-to-rail output buff­ers. The AD7304 contains four independent multiplying refer­ence inputs, while the AD7305 has one common reference input.
The AD7304 uses a 3-wire SPI compatible serial data interface,
while the AD7305 offers a 8-bit parallel data interface.

D/A Converter Section

Each part contains four voltage-switched R-2R ladder DACs.
Figure A shows a typical equivalent DAC. These DACs are
designed to operate both single-supply or dual supply, depend­ing on whether the user supplies a negative voltage on the V

SS

pin. In a single-supply application the VSS is tied to ground. In
either mode the DAC output voltage is determined by the V

REF

input voltage and the digital data (D) loaded into the corre­sponding DAC register according to Equation 1.

V

= V

OUT

Note that the output full-scale polarity is the same as the V

× D/256 (1)

REF

REF

polarity for dc reference voltages.

V

DD

V

REF

DB7

DB6

DB0

V

2R

R

V

2R

2R

SS

2R

OUT

Figure 29. Typical Equivalent DAC Channel

These DACs are also designed to accommodate ac reference
input signals. As long as the ac signals are maintained between

< V

V

SS

<VDD, the user can expect 50 kHz of full-power

REF

multiplying bandwidth performance. In order to use negative
input reference voltages, the V

pin must be biased with a nega-

SS

tive voltage of equal or greater magnitude than the reference
voltage.

The reference inputs are code-dependent, exhibiting worst case
minimum resistance values specified in the parametric specifica­tion table. The DAC outputs V

A, B, C, D are each capable

OUT

of driving 2 kΩ loads in parallel with up to 500 pF loads. Output
source and sink current is shown in Figures 6 and 7. The output
slew rate is nominally 3.6 V/µs while operating from ± 5 V sup-
plies. The low output impedance of the buffers minimizes
crosstalk between analog input channels. At 100 kHz, 65 dB of
channel-to-channel isolation exists (Figure 22). Output voltage
noise is plotted in Figure 19. In order to maintain good analog
performance, power supply bypassing of 0.01 µF in parallel with
1 µF is recommended. The true rail-to-rail capability of the
AD7304/AD7305 allows the user to connect the reference inputs

directly to the same supply as the V

or VSS pin (Figure 30).

DD

Under these conditions clean power supply voltages (low ripple,
avoid switching supplies) appropriate for the application should
be used.

Figure 30. Equivalent DAC Amplifier Output Circuit

AD7304 SERIAL DATA INTERFACE

The AD7304 uses a 3-wire (CS, SDI, CLK) SPI compatible
serial data interface. New serial data is clocked into the serial
input register in a 12-bit data-word format. MSB bits are loaded
first. Table II defines the 12 data-word bits. Data is placed on
the SDI/SHDN pin and clocked into the register on the positive
clock edge of CLK subject to the data setup and data hold time
requirements specified in the TIMING SPECIFICATIONS.
Data can only be clocked in while the CS chip select pin is
active low. Only the last 12-bits clocked into the serial register
will be interrogated when the CS pin returns to the logic high
state, extra data bits are ignored. Since most microcontrollers
output serial data in 8-bit bytes, two right justified data bytes
can be written to the AD7304. Keeping the CS line low between
the first and second byte transfer will result in a successful serial
register update.

Once the data is properly aligned in the shift register the positive
edge of the CS initiates either the transfer of new data to the
target DAC register, determined by the decoding of address bits
A1 and A0, or the shutdown features will be activated based on
the SAC or SDC bits. When either SAC or SDC pins are set
(Logic = 0) the loading of new data determined by Bits B9 to
B0 are still loaded, but the results do not appear on the buffer
outputs until the device is brought out of the shutdown state.
The selected DAC output voltages become high impedance with
a nominal resistance of 120 kΩ to ground, Figure 30. If both
SAC and SDC pins are set, all channels are still placed in the
shutdown mode. When the AD7304 has been programmed into
the power shutdown state, the present DAC register data is
maintained as long as V

remains greater than 2.7 volts. The

DD

remaining characteristics of the software serial interface are
defined by Tables I, II and Figure 3 timing diagram.

Two additional pins CLR and LDAC on the AD7304 provide
hardware control over the clear function and the DAC Register
loading. If these functions are not needed the CLR pin can be
tied to logic high, and the LDAC pin can be tied to logic low.
The asynchronous input CLR pin forces all input and DAC
registers to the zero-code state. The asynchronous LDAC pin
can be strobed to active low when all DAC Registers need to be
updated simultaneously from their respective Input Registers.
The LDAC pin places the DAC Register in a transparent mode
while in the logic low state.

REV. A

–11–

AD7304/AD7305

CLK

SDI

V

REFAVREFBVREFCVREF

EN

CS

D0
D1
D2
D3

8

D4
D5

DACA

D6
D7

A0

A1

SDC

SAC

640k 680k

80k

2:4
DECODE

V

320k280k

GND

B

C

D

DD

INPUT

REGISTER

g

DQ

INPUT

REGISTER

g

DQ

INPUT

REGISTER

g

DQ

INPUT

REGISTER

g

DQ

POWER-

ON

RESET

AD7304

R

R

R

R

LDAC

D

DAC A

REGISTER

DAC B

REGISTER

DAC C

REGISTER

DAC D

REGISTER

V

DD

DAC A

OE

R

DAC B

OE

R

DAC C

OE

R

DAC D

OE

R

V

CLR

A

V

OUT

V

B

OUT

V

C

OUT

V

D

OUT

SS

Figure 31. AD7304 Equivalent Logic Interface

AD7304 Hardware Shutdown SHDN

If a three-state driver is used on the SDI/SHDN pin, the AD7304
can be placed into a power shutdown mode when the SDI/
SHDN pin is placed in a high impedance state. For proper
operation no other termination voltages should be present on
this pin. An internal window comparator will detect when the
logic voltage on the SHDN pin is between 28% and 36% of

. A high impedance internal bias generator provides this

V

DD

voltage on the SHDN pin. The four DAC output voltages be­come high impedance with a nominal resistance of 120 kΩ to
ground. See Figure 30 for an equivalent circuit.

AD7304/AD7305 POWER ON RESET

When the VDD power supply is turned on, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state. The V

power supply should have a monotonically in-

DD

creasing ramp in order to have consistent results, especially in
the region of V

= 1.5 V to 2.3 V. The VSS supply has no effect

DD

on the power ON reset performance. The DAC register data
will stay at zero until a valid serial register software load takes
place. In the case of the double buffered AD7305 the output
DAC register can only be changed once the LDAC strobe is
initiated.

AD7305 PARALLEL DATA INTERFACE

The AD7305 has an 8-bit parallel interface DB7 = MSB,
DB0 = LSB. Two address Bits A1 and A0 are decoded when an
active low write strobe is placed on the WR pin, see Table III.
The WR is a level-sensitive input pin, therefore the data setup
and data hold times defined in the TIMING SPECIFICATIONS
need to be adhered to.

The LDAC pin provides the capability of simultaneously updat­ing all DAC registers with new data from the Input Registers at

V

V

REF

DD

DATA

DB0–DB7

WR

A0/SHDN

8

640k

80k

280k

DAC A

2:4
DECODE

680k

320k

GND

B

C

D

V

DD

A1

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-

ON

RESET

AD7305

R

R

R

R

LDAC

DAC A

REGISTER

DAC B

REGISTER

DAC C

REGISTER

DAC D

REGISTER

DAC A

R

DAC B

R

DAC C

R

DAC D

R

V

A

OUT

OE

V

B

OUT

OE

V

C

OUT

OE

V

D

OUT

OE

V

SS

Figure 32. AD7305 Equivalent Logic Interface

the same time. This will result in the analog outputs all chang­ing to their new values at the same time. The LDAC pin is a
level-sensitive input. If the simultaneous update feature is not
required the LDAC pin can be tied to logic low. When the
LDAC is tied to logic low, the DAC Registers become transpar­ent and the Input Register data determines the DAC output
voltage. See Figure 32 for an equivalent interface logic diagram.

AD7226 Pin Compatibility

By tying the LDAC pin to ground, the AD7305 has the same
pin out and functionality as the AD7226, with the exception of
a lower power supply operating voltage.

AD7305 Hardware Shutdown SHDN

If a three state driver is used on the A0/SHDN pin, the AD7305
can be placed into a power shutdown mode when the A0/SHDN
pin is placed in a high impedance state. For proper operation no
other termination voltages should be present on this pin. An
internal window comparator will detect when the logic voltage
on the SHDN pin is between 28% and 36% of V

. A high

DD

impedance internal bias generator provides this voltage on the
SHDN pin. The four DAC output voltages become high imped­ance with a nominal resistance of 120 kΩ to ground.

ESD Protection Circuits

All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND). The V
back-biased ESD protection Zener connected to V

pins also contain a

REF

DD

(see

Figure 33).

DIGITAL
INPUTS

GND

V

DD

V

X

REF

Figure 33. Equivalent ESD Protection Circuits

–12–

REV. A

AD7304/AD7305

APPLICATIONS

The AD7304/AD7305 is inherently a 2-quadrant multiplying
D/A converter. That is, it can easily be set up for unipolar out­put operation. The full-scale output polarity is the same as the
reference input voltage polarity.

In some applications it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an external true rail-to-rail op
amp, such as the OP295. Connecting the external amplifier with
two equal value resistors as shown in Figure 34 results in a full
4-quadrant multiplying circuit. In this circuit the amplifier pro­vides a gain of two, which increases the output span magnitude
to 10 volts. The transfer equation of this circuit shows that both
negative and positive output voltages are created as the input
data (D) is incremented from code zero (V
scale (V

= 0 V) to full scale (V

OUT

V

= (D/128 –1) × V

OUT

REF

= +5 V).

OUT

= –5 V) to mid-

OUT

(2)

+5V

10k 10k

REF

AD7304

–5V < V

OUT

< +5V

Figure 34. Four-Quadrant Multiplying Application Circuit

REV. A

–13–

AD7304/AD7305

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.0118 (0.30)

0.0040 (0.10)

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

16-Lead Wide SOIC

(R-16)

0.4133 (10.50)

0.3977 (10.00)

16 9

0.2992 (7.60)

0.2914 (7.40)

81

PIN 1

0.0500
(1.27)

BSC

0.1043 (2.65)

0.0926 (2.35)

0.0192 (0.49)

0.0138 (0.35)

SEATING
PLANE

16-Lead Plastic DIP

(N-16)

0.840 (21.33)

0.745 (18.93)

16

18

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

9

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.130
(3.30)
MIN

SEATING
PLANE

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

8

0.0157 (0.40)

0

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

x 45

0.195 (4.95)

0.115 (2.93)

0.0118 (0.30)

0.0040 (0.10)

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

20-Lead SOIC

(R-20)

0.5118 (13.00)

0.4961 (12.60)

20 11

0.2992 (7.60)

0.2914 (7.40)

PIN 1

0.0500
(1.27)

BSC

101

0.1043 (2.65)

0.0926 (2.35)

0.0192 (0.49)

0.0138 (0.35)

SEATING
PLANE

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

20-Lead Plastic DIP

(N-20)

1.060 (26.90)

0.925 (23.50)

20

110

PIN 1

0.022 (0.558)

0.014 (0.356)

0.100
(2.54)

BSC

11

0.070 (1.77)

0.045 (1.15)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

SEATING
PLANE

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

8
0

0.0157 (0.40)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

C3252a-2–2/98

x 45

0.195 (4.95)

0.115 (2.93)

0.177 (4.50)

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.201 (5.10)

0.193 (4.90)

16

0.169 (4.30)

1

PIN 1

0.0256
(0.65)

BSC

16-Lead TSSOP

(RU-16)

9

8

0.0118 (0.30)

0.0075 (0.19)

0.256 (6.50)

0.246 (6.25)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

8
0

0.028 (0.70)

0.020 (0.50)

–14–

0.177 (4.50)

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

20-Lead Thin Surface Mount (TSSOP)

(RU-20)

0.260 (6.60)

0.252 (6.40)

20 11

0.169 (4.30)

1

PIN 1

0.0256 (0.65)
BSC

0.0118 (0.30)

0.0075 (0.19)

10

0.256 (6.50)

0.246 (6.25)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

8
0

0.028 (0.70)

0.020 (0.50)

PRINTED IN U.S.A.

REV. A