ANALOG DEVICES AD7276 Service Manual

3 MSPS, 12-/10-/8-Bit

V

FEATURES

Throughput rate: 3 MSPS Specified for V Power consumption

12.6 mW at 3 MSPS with 3 V supplies

Wide input bandwidth

70 dB SNR at 1 MHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Temperature range: −40°C to +125°C Power-down mode: 0.1 μA typical 6-lead TSOT package 8-lead MSOP package

AD7476 and AD7476A pin-compatible

GENERAL DESCRIPTION

The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed, low power, successive approximation analog-to-digital converters (ADCs), respectively. The parts operate from a single 2.35 V to 3.6 V power supply and feature throughput rates of up to 3 MSPS. The parts contain a low noise, wide bandwidth trackand-hold amplifier that can handle input frequencies in excess of 55 MHz.

The conversion process and data acquisition are controlled using

with microprocessors or DSPs. The input signal is sampled on the falling edge of

point. There are no pipeline delays associated with the part.

The AD7276/AD7277/AD7278 use advanced design techniques to achieve ver y low power dissipation at high throughput rates.

The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC; therefore, the analog input range for the part is 0 to VDD. The conversion rate is determined by the SCLK.

and the serial clock, allowing the devices to interface

CS

of 2.35 V to 3.6 V

DD

, and the conversion is also initiated at this

CS

ADCs in 6-Lead TSOT

AD7276/AD7277/AD7278

FUNCTIONAL BLOCK DIAGRAM

DD

12-/10-/8-BIT

IN

T/H

AD7276/ AD7277/ AD7278

Table 1.

Part Number Resolution Package

AD7276 12 8-Lead MSOP 6-Lead TSOT AD7277 10 8-Lead MSOP 6-Lead TSOT AD7278 8 8-Lead MSOP 6-Lead TSOT

AD72741 12 8-Lead MSOP 8-Lead TSOT AD72731 10 8-Lead MSOP 8-Lead TSOT

1

Part contains external reference pin.

PRODUCT HIGHLIGHTS

1. 3 MSPS ADCs in a 6-lead TSOT package.

2. AD7476/AD7477/AD7478 and AD7476A/AD7477A/

AD7478A pin-compatible.

3. High throughput with low power consumption.

4. Flexible power/serial clock speed management. This allows

maximum power efficiency at low throughput rates.

5. Reference derived from the power supply.

6. No pipeline delay. The parts feature a standard successive

approximation ADC with accurate control of the sampling instant via a

input and once-off conversion control.

CS

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

GND

Figure 1.

SCLK

SDATA

CS

04903-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7276/AD7277/AD7278

REVISION HISTORY

5/11—Rev. B to Rev. C

Changes to Figure 21...................................................................... 16

Changes to Ordering Guide.......................................................... 27

Changes to Endnote 5.................................................................... 27

11/09—Rev. A to Rev. B

Changes to Table 2............................................................................ 3

Changes to Table 3............................................................................ 5

Changes to Table 4............................................................................ 7

Changes to Ordering Guide.......................................................... 27

10/05—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Table 2............................................................................ 3

Changes to Table 5............................................................................ 8

Changes to the Partial Power-Down Mode Section .................. 18

Changes to the Power vs. Throughput Rate Section.................. 21

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 26

7/05—Revision 0: Initial Version

Rev. C | Page 2 of 28

AD7276/AD7277/AD7278

SPECIFICATIONS

AD7276 SPECIFICATIONS

VDD = 2.35 V to 3.6 V, B Grade and A Grade: f T

, unless otherwise noted.

MAX

= 48 MHz, f

SCLK

= 3 MSPS, Y Grade:1 f

SAMPLE

= 16 MHz, f

SCLK

= 1 MSPS, TA = T

SAMPLE

MIN

to

Table 2.

Parameter A Grade

2, 3

B, Y Grade

2,3

Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 1 MHz sine wave, B Grade f

= 100 kHz sine wave, Y Grade

IN

Signal-to-Noise + Distortion (SINAD)4 68 68 dB min

Signal-to-Noise Ratio (SNR) 69 69 dB min

70 70 dB typ

Total Harmonic Distortion (THD)4 −73 −73 dB max

−78 −78 dB typ

Peak Harmonic or Spurious Noise (SFDR)4 −80 −80 dB typ

Intermodulation Distortion (IMD)4

Second-Order Terms −82 −82 dB typ fa = 1 MHz, fb = 0.97 MHz

Third-Order Terms −82 −82 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 5 ns typ Aperture Jitter 18 18 ps typ Full Power Bandwidth 55 55 MHz typ @ 3 dB 8 8 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 12 12 Bits Integral Nonlinearity4 ±1.5 ±1 LSB max Differential Nonlinearity4 +1/−0.99 +1/−0.99 LSB max Guaranteed no missed codes to 12 bits Offset Error4 ±4 ±3 LSB max Gain Error4 ±3.5 ±3.5 LSB max Total Unadjusted Error4 (TUE) ±5 ±3.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD 0 to VDD V DC Leakage Current ±1 ±1 μA max −40°C to +85°C ±5.5 ±5.5 μA max 85°C to 125°C Input Capacitance 42 42 pF typ When in track 10 10 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V

1.7 1.7 V min 2.35 V ≤ VDD ≤ 2.7 V

INH

2 2 V min 2.7 V < VDD ≤ 3.6 V Input Low Voltage, V

0.7 0.7 V max 2.35 V ≤ VDD ≤ 2.7 V

INL

0.8 0.8 V max 2.7 V < VDD ≤ 3.6 V Input Current, IIN ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Capacitance, C

5

2 2 pF typ

IN

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.2 0.2 V max I

− 0.2 VDD − 0.2 V min I

DD

= 200 μA, VDD = 2.35 V to 3.6 V

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±2.5 ±2.5 μA max Floating-State Output Capacitance5 4.5 4.5 pF typ Output Coding Straight (natural) binary

Rev. C | Page 3 of 28

AD7276/AD7277/AD7278

Parameter A Grade

2, 3

B, Y Grade

2,3

Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 291 291 ns max 14 SCLK cycles with SCLK at 48 MHz, B Grade 875 875 ns max 14 SCLK cycles with SCLK at 16 MHz, Y Grade Track-and-Hold Acquisition Time4 60 60 ns min Throughput Rate 3 3 MSPS max See the Serial Interface section

POWER REQUIREMENTS

VDD 2.35/3.6 2.35/3.6 V min/max IDD Digital I/Ps 0 V or VDD

Normal Mode (Static) 1 1 mA typ VDD = 3.6 V, SCLK on or off Normal Mode (Operational) 5.5 5.5 mA max VDD = 2.35 V to 3.6 V, f

2.5 2.5 mA max VDD = 2.35 V to 3.6 V, f

4.2 4.2 mA typ VDD = 3 V, f

1.6 1.6 mA typ VDD = 3 V, f

= 3 MSPS, B Grade

SAMPLE

= 1 MSPS, Y Grade

SAMPLE

= 3 MSPS, B Grade

SAMPLE

= 1 MSPS, Y Grade

SAMPLE

Partial Power-Down Mode (Static) 34 34 μA typ Full Power-Down Mode (Static) 2 2 μA max −40°C to +85°C, typically 0.1 μA 10 10 μA max 85°C to 125°C

Power Dissipation6

Normal Mode (Operational) 19.8 19.8 mW max VDD = 3.6 V, f 9 9 mW max VDD = 3.6 V, f

12.6 12.6 mW typ VDD = 3 V, f

4.8 4.8 mW typ VDD = 3 V, f

= 3 MSPS, B Grade

SAMPLE

= 1 MSPS, Y Grade

SAMPLE

= 3 MSPS, B Grade

SAMPLE

= 1 MSPS, Y Grade

SAMPLE

Partial Power-Down 102 102 μW typ VDD = 3 V Full Power-Down 7.2 7.2 μW max VDD = 3.6 V, −40°C to +85°C

1

Y Grade specifications are guaranteed by characterization.

2

Temperature range from −40°C to +125°C.

3

Typical specifications are tested with VDD = 3 V and at 25°C.

4

See the Terminology section.

5

Guaranteed by characterization.

6

See the Power vs. Throughput Rate section.

Rev. C | Page 4 of 28

AD7276/AD7277/AD7278

AD7277 SPECIFICATIONS

VDD = 2.35 V to 3.6 V, f

= 48 MHz, f

SCLK

= 3 MSPS, TA = T

SAMPLE

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter A Grade

1, 2

B Grade

1, 2

Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 1 MHz sine wave

Signal-to-Noise + Distortion (SINAD)3 60.5 60.5 dB min Total Harmonic Distortion (THD)3 −70 −1 dB max

−76 −76 dB typ Peak Harmonic or Spurious Noise (SFDR)3 −80 −80 dB typ Intermodulation Distortion (IMD)3

Second-Order Terms −82 −82 dB typ fa = 1 MHz, fb = 0.97 MHz

Third-Order Terms −82 −82 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 5 ns typ Aperture Jitter 18 18 ps typ Full Power Bandwidth 74 74 MHz typ @ 3 dB 10 10 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 10 Bits Integral Nonlinearity3 ±0.5 ±0.5 LSB max Differential Nonlinearity3 ±0.5 ±0.5 LSB max Guaranteed no missed codes to 10 bits Offset Error3 ±1.5 ±1 LSB max Gain Error3 ±2 ±1.5 LSB max Total Unadjusted Error (TUE)3 ±2.5 ±2.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD 0 to VDD V DC Leakage Current ±1 ±1 μA max −40°C to +85°C ±5.5 ±5.5 μA max 85°C to 125°C Input Capacitance 42 42 pF typ When in track 10 10 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V

1.7 1.7 V min 2.35 V ≤ VDD ≤ 2.7 V

INH

2 2 V min 2.7 V < VDD ≤ 3.6 V Input Low Voltage, V

0.7 0.7 V max 2.35 V ≤ VDD ≤ 2.7 V

INL

0.8 0.8 V max 2.7 V < VDD ≤ 3.6 V Input Current, IIN ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Capacitance, C

4

2 2 pF typ

IN

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.2 0.2 V max I

− 0.2 VDD − 0.2 V min I

DD

= 200 μA, VDD = 2.35 V to 3.6 V

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±2.5 ±2.5 μA max Floating-State Output Capacitance4 4.5 4.5 pF typ Output Coding Straight (natural) binary

CONVERSION RATE

Conversion Time 250 250 ns max 12 SCLK cycles with SCLK at 48 MHz Track-and-Hold Acquisition Time3 60 60 ns min Throughput Rate 3.45 3.45 MSPS max SCLK at 48 MHz

Rev. C | Page 5 of 28

AD7276/AD7277/AD7278

Parameter A Grade

1, 2

B Grade

1, 2

Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 2.35/3.6 2.35/3.6 V min/max IDD Digital I/Ps 0 V or VDD

Normal Mode (Static) 0.6 0.6 mA typ VDD = 3.6 V, SCLK on or off Normal Mode (Operational) 5.5 5.5 mA max VDD = 2.35 V to 3.6 V, f

SAMPLE

= 3 MSPS

3.5 3.5 mA typ VDD = 3 V Partial Power-Down Mode (Static) 34 34 μA typ Full Power-Down Mode (Static) 2 2 μA max −40°C to +85°C, typically 0.1 μA 10 10 μA max 85°C to 125°C

Power Dissipation5

Normal Mode (Operational) 19.8 19.8 mW max VDD = 3.6 V, f

SAMPLE

= 3 MSPS

10.5 10.5 mW typ VDD = 3 V Partial Power-Down 102 102 μW typ VDD = 3 V Full Power-Down 7.2 7.2 μW max VDD = 3.6 V, −40°C to +85°C

1

Temperature range from −40°C to +125°C.

2

Typical specifications are tested with VDD = 3 V and at 25°C.

3

See the Terminology section.

4

Guaranteed by characterization.

5

See the Power vs. Throughput Rate section.

Rev. C | Page 6 of 28

AD7276/AD7277/AD7278

AD7278 SPECIFICATIONS

VDD = 2.35 V to 3.6 V, f

= 48 MHz, f

SCLK

= 3 MSPS, TA = T

SAMPLE

MIN

to T

, unless otherwise noted.

MAX

Table 4.

Parameter A Grade

1, 2

B Grade

1, 2

Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 1 MHz sine wave

Signal-to-Noise + Distortion (SINAD)3 49 49 dB min Total Harmonic Distortion (THD)3 −66 −67 dB max

−73 −73 dB typ Peak Harmonic or Spurious Noise (SFDR)3 −69 −69 dB typ Intermodulation Distortion (IMD)3

Second-Order Terms −76 −76 dB typ fa = 1 MHz, fb = 0.97 MHz

Third-Order Terms −76 −76 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 5 ns typ Aperture Jitter 18 18 ps typ Full Power Bandwidth 74 74 MHz typ @ 3 dB Full Power Bandwidth 10 10 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 8 8 Bits Integral Nonlinearity3 ±0.2 ±0.2 LSB max Differential Nonlinearity3 ±0.3 ±0.3 LSB max Guaranteed no missed codes to 8 bits Offset Error3 ±0.9 ±0.5 LSB max Gain Error3 ±1.2 ±1 LSB max Total Unadjusted Error (TUE)3 ±1.5 ±1.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to VDD 0 to VDD V DC Leakage Current ±1 ±1 μA max −40°C to +85°C ±5.5 ±5.5 μA max 85°C to 125°C Input Capacitance 42 42 pF typ When in track 10 10 pF typ When in hold

LOGIC INPUTS

Input High Voltage, V

1.7 1.7 V min 2.35 V ≤ VDD ≤ 2.7 V

INH

2 2 V min 2.7 V < VDD ≤ 3.6 V Input Low Voltage, V

0.7 0.7 V max 2.35 V ≤ VDD ≤ 2.7 V

INL

0.8 0.8 V max 2.7 V < VDD ≤ 3.6 V Input Current, IIN ±1 ±1 μA max Input Capacitance, C

4

2 2 pF typ

IN

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.2 0.2 V max I

− 0.2 VDD − 0.2 V min I

DD

= 200 μA, VDD = 2.35 V to 3.6 V

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±2.5 ±2.5 μA max Floating-State Output Capacitance4 4.5 4.5 pF typ Output Coding Straight (natural) binary

CONVERSION RATE

Conversion Time 208 208 ns max 10 SCLK cycles with SCLK at 48 MHz Track-and-Hold Acquisition Time3 60 60 ns min Throughput Rate 4 4 MSPS max SCLK at 48 MHz

Rev. C | Page 7 of 28

AD7276/AD7277/AD7278

Parameter A Grade

1, 2

B Grade

1, 2

Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 2.35/3.6 2.35/3.6 V min/max IDD Digital I/Ps = 0 V or VDD

Normal Mode (Static) 0.5 0.5 mA typ VDD = 3.6 V, SCLK on or off Normal Mode (Operational) 5.5 5.5 mA max VDD = 2.35 V to 3.6 V, f

SAMPLE

= 3 MSPS

3.5 3.5 mA typ VDD = 3 V Partial Power-Down Mode (Static) 34 34 μA typ Full Power-Down Mode (Static) 2 2 μA max −40°C to +85°C, typically 0.1 μA 10 10 μA max +85°C to +125°C Power Dissipation5

Normal Mode (Operational) 19.8 19.8 mW max VDD = 3.6 V, f

SAMPLE

= 3 MSPS

10.5 10.5 mW typ VDD = 3 V Partial Power-Down 102 102 μW typ VDD = 3 V Full Power-Down 7.2 7.2 μW max VDD = 3.6 V, −40°C to +85°C

1

Temperature range from −40°C to +125°C.

2

Typical specifications are tested with VDD = 3 V and at 25°C.

3

See the Terminology section.

4

Guaranteed by characterization.

5

See the Power vs. Throughput Rate section.

TIMING SPECIFICATIONS—AD7276/AD7277/AD7278

VDD = 2.35 V to 3.6 V, TA = T

MIN

to T

, unless otherwise noted.1

MAX

Table 5.

Parameter2 Limit at T

3

f

500 kHz min4

SCLK

MIN

, T

Unit Description

MAX

48 MHz max B grade 16 MHz max Y grade t

14 × t

CONVER T

12 × t 10 × t t

4 ns min

QUIET

AD7276

SCLK

AD7277

SCLK

AD7278

SCLK

Minimum quiet time required between the bus relinquish and the start of the next conversion

t1 3 ns min t2 6 ns min

5

t

4 ns max

3

5

t

15 ns max Data access time after SCLK falling edge

4

t5 0.4 t t6 0.4 t

5

t

5 ns min SCLK to data valid hold time

7

ns min SCLK low pulse width

SCLK

ns min SCLK high pulse width

SCLK

Minimum CS

to SCLK setup time

CS Delay from CS

pulse width

until SDATA three-state disabled

t8 14 ns max SCLK falling edge to SDATA three-state 5 ns min SCLK falling edge to SDATA three-state t

9

T

POWER-UP

1

Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this

value, a digital buffer or latch must be used.

2

Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

3

Mark/space ratio for the SCLK input is 40/60 to 60/40.

4

Minimum f

5

The time required for the output to cross the VIH or VIL voltage.

6

See the Power-Up Times section.

4.2 ns max

6

1 μs max Power-up time from full power-down

at which specifications are guaranteed.

SCLK

rising edge to SDATA three-state

CS

Rev. C | Page 8 of 28

AD7276/AD7277/AD7278

t

SCLK

SDATA

SCLK

SDATA

4

Figure 2. Access Time After SCLK Falling Edge

t

7

V

IH

V

IL

Figure 3. Hold Time After SCLK Falling Edge

SCLK

V

IH

V

IL

04903-002

SDATA

Figure 4. SCLK Falling Edge SDATA Three-State

04903-003

t

8

1.4V

04903-004

Rev. C | Page 9 of 28

ANALOG DEVICES AD7276 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AD7276 SPECIFICATIONS

AD7277 SPECIFICATIONS

AD7278 SPECIFICATIONS

TIMING SPECIFICATIONS—AD7276/AD7277/AD7278