Analog Devices AD7273 4 prb Datasheet

PRELIMINARY TECHNICAL DATA

3MSPS,10-/12-Bit

a

Preliminary Technical Data

FEATURES
Fast Throughput Rate: 3MSPS
Specified for V
Low Power:

13.5 mW max at 3MSPS with 3V Supplies

Wide Input Bandwidth:

70dB SNR at 1MHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface

TM

/QSPITM/MICROWIRETM/DSP Compatible

SPI
Power Down Mode: 1µA max
8-Lead TSOT Package
8-Lead MSOP Package

APPLICATIONS
Battery-Powered Systems

Personal Digital Assistants

Medical Instruments

Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High-Speed Modems
Optical Sensors

of 2.35 V to 3.6V

DD

V

V

IN

REF

ADCs in 8-Lead TSOT

AD7273/AD7274

FUNCTIONAL BLOCK DIAGRAM

T/H

AD7273/AD7274

V

DD

10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

CONTROL

LOGIC

GND

GND

SCLK
SDATA

&6

GENERAL DESCRIPTION

The AD7273/AD7274 are 10-bit and 12-bit, high speed,
low power, successive-approximation ADCs respectively.
The parts operate from a single 2.35V to 3.6 V power
supply and feature throughput rates up to 3 MSPS. The
parts contain a low-noise, wide bandwidth track/hold am­plifier which can handle input frequencies in excess of
TBD MHz.

The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. The conversion rate is deter­mined by the SCLK. There are no pipeline delays associ­ated with the part.

The AD7273/AD7274 use advanced design techniques to
achieve very low power dissipation at high throughput
rates.

The reference for the parts is applied externally and can
be in the range of 1.2V to V
dynamic input range to the ADC.

REV. PrB (6/04)

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.Trademarks
and registered tradermarks are the property of their respective companies.

This allows the widest

DD.

PRODUCT HIGHLIGHTS

1. 3MSPS ADCs in an 8-lead TSOT package.

2. High Throughput with Low Power Consumption.

3. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock

allowing the conversion time to be reduced through the
serial clock speed increase. This allows the average
power consumption to be reduced when a power-down
mode is used while not converting. The AD7273/
AD7274 features a power down mode to maximize
power efficiency at lower throughput rates. Current con­sumption is 1 µA max when in Power Down mode.

4. Reference can be driven up to the power supply.

5. No Pipeline Delay.
The parts feature a standard successive-approximation
ADC with accurate control of the sampling instant via a
CS input and once-off conversion control.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] Analog Devices, Inc., 2004

PRELIMINARY TECHNICAL DATA

(VDD=+2.35 V to +3.6 V, V

AD7273-SPECIFICATIONS

Parameter B Grade

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

2

2

-73 dB max

2

2

wise noted; TA=T

1

MIN

Units Test Conditions/Comments

61 dB min

-74 dB max

to T

= +2.5V , f

REF

, unless otherwise noted.)

MAX

= 1 MHz Sine Wave

IN

=52 MHz, f

SCLK

=3 MSPS unless other-

SAMPLE

Second Order Terms -82 dB typ fa= TBD kHz, fb= TBD kHz

Third Order Terms -82 dB typ fa= TBD kHz, fb= TBD kHz

Aperture Delay TBD ns typ
Aperture Jitter TBD ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB
Full Power Bandwidth TBD MHz typ @ 0.1dB
Power Supply Rejection Ratio (PSRR) TBD dB typ

DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error

Gain Error

2

2

Total Unadjusted Error (TUE)

2

2

±0.5 LSB max
±0.5 LSB max Guaranteed No Missed Codes to 10 Bits
±1 LSB max
±TBD LSB typ
±1 LSB max

2

±TBD LSB typ
±TBD LSB max

ANALOG INPUT

Input Voltage Range 0 to V

REF

Volts
DC Leakage Current ±0.5 µA max
Input Capacitance TBD pF typ

REFERENCE INPUT

V

Input Voltage Range 1.2 to V

REF

Vmin/Vmax

DD

DC leakage Current ±TBD µA max

Input Capacitance TBD pF max
Input Impedance TBD kΩ typ

LOGIC INPUTS

Input High Voltage, V

INH

0.7(VDD) V min 2.35V⭐ Vdd ⭐2.7V
2 V min 2.7V< Vdd ⭐ 3.6V

Input Low Voltage, V

INL

0.2(VDD) V max 2.35V⭐Vdd< 2.7V

0.8 V max 2.7V ⭐Vdd⭐ 3.6V
Input Current, I
Input Current, IIN, CS Pin ±TBD µA max
Input Capacitance, C

, SCLK Pin ±0.5 µA max Typically TBD nA, VIN= 0 V or V

IN

IN

3

10 pF max

DD

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance

OH VDD

0.2 V max I

OL

3

10 pF max

- 0.2 V min I

= 200 µA,VDD= 2.35 V to 3.6 V

SOURCE

= 200µA

SINK

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 230 ns max 12 SCLK cycles with SCLK at 52 MHz
Track/Hold Acquisition Time

2

50 ns max

Throughput Rate 3 MSPS max

NOTES

1

Temperature range from –40°C to +85°C.

2

See Terminology.

3

Guaranteed by Characterization.

Specifications subject to change without notice.

–2–

REV. PrB

PRELIMINARY TECHNICAL DATA

(VDD=+2.35 V to +3.6 V, V

AD7273-SPECIFICATIONS

Parameter B Grade

otherwise noted; TA=T

1

Units Test Conditions/Comments

POWER REQUIREMENTS

V

DD

I

DD

2.35/3.6 V min/Vmax

Normal Mode(Static) 2.5 mA typ VDD= 2.35V to 3.6V, SCLK On or Off
Normal Mode (Operational) 4.5 mA max V
Full Power-Down Mode (Static) 1 µA max SCLK On or Off, typically TBD nA

Full Power-Down Mode (Dynamic) TBD mA typ VDD= 3V, f

Power Dissipation

4

Normal Mode (Operational) 13.5 mW max VDD=3V, f
Full Power-Down 3 µW max VDD=3V

NOTES

1

Temperature range from –40°C to +85°C.

2

See Terminology.

3

Guaranteed by Characterization.

4

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

MIN

= +2 .5V, f

REF

to T

, unless otherwise noted.)

MAX

=52 MHz, f

SCLK

Digital I/Ps= 0V or V

= 2.35V to 3.6V, f

DD

SAMPLE

SAMPLE

=3MSPS unless

SAMPLE

DD

SAMPLE

= 1MSPS

= 3MSPS

= 3MSPS

REV. PrB

–3–

PRELIMINARY TECHNICAL DATA

AD7274-SPECIFICATIONS

(VDD=+2.35 V to +3.6 V, V
noted; TA=T

MIN

to T

MAX

= +2.5V, f

REF

=52 MHz, f

SCLK

, unless otherwise noted.)

=3MSPS unless otherwise

SAMPLE

Parameter B Grade1 Units Test Conditions/Comments

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD)
Signal-to-Noise Ratio (SNR) 71 dB min
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

2

2

2

70 dB min

-80 dB typ

2

-82 dB typ

= 1 MHz Sine Wave

IN

Second Order Terms -84 dB typ fa= TBD kHz, fb= TBD kHz

Third Order Term -84 dB typ fa= TBD kHz, fb= TBD kHz

Aperture Delay TBD ns typ
Aperture Jitter TBD ps typ
Full Power Bandwidth TBD MHz typ @ 3 dB
Full Power Bandwidth TBD MHz typ @ 0.1dB

Power Supply Rejection Ratio (PSRR) TBD dB typ
DC ACCURACY

Resolution 12 Bits
Integral Nonlinearity
Differential Nonlinearity

Offset Error

Gain Error

2

2

Total Unadjusted Error (TUE)

2

2

±1 LSB max
±1 LSB max Guaranteed No Missed Codes to 12 Bits
±TBD LSB max

2

±TBD LSB max
±TBD LSB max

ANALOG INPUT
Input Voltage Range

0 to V

REF

Volts
DC Leakage Current ±0.5 µA max
Input Capacitance TBD pF typ

REFERENCE INPUT

V

Input Voltage Range 1.2 to V

REF

Vmin/Vmax

DD

DC leakage Current ±TBD µA max

Input Capacitance TBD pF max
Input Impedance TBD kΩ typ

LOGIC INPUTS
Input High Voltage, V

INH

0.7(VDD) V min 2.35V⭐ Vdd ⭐2.7V
2 V min 2.7V < Vdd⭐ 3.6V

Input Low Voltage, V

0.2(VDD) V max 2.35V⭐Vdd< 2.7V

INL

0.8 V max 2.7V ⭐Vdd⭐ 3.6V

Input Current, I
Input Current, IIN, CS Pin ±TBD µA max
Input Capacitance, C

,SCLK Pin ±0.5 µA max Typically TBD nA, VIN= 0 V or V

IN

IN

3

10 pF max

DD

LOGIC OUTPUTS
Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance

OH

OL

3

V

- 0.2 V min I

DD

0.2 V max I

10 pF max

= 200 µA;VDD= 2.35 V to 3.6 V

SOURCE

=200 µA

SINK

Output Coding Straight (Natural) Binary
CONVERSION RATE

Conversion Time 270 ns max 14 SCLK Cycles with SCLK at 52 MHz
Track/Hold Acquisition Time
Throughput Rate 3

2

50 ns max

MSPS max

See Serial Interface Section

NOTES

1

Temperature range from –40°C to +85°C.

2

See Terminology.

3

Guranteed by Characterization.

Specifications subject to change without notice.

–4–

REV. PrB

PRELIMINARY TECHNICAL DATA

(VDD=+2.35 V to +3.6 V, V

AD7274 SPECIFICATIONS

otherwise noted; TA=T

Parameter B Grade1 Units Test Conditions/Comments

POWER REQUIREMENTS
V

DD

I

DD

2.35/3.6

V min/Vmax

Normal Mode (Static) 2.5 mA typ VDD= 2.35V to 3.6V,SCLK On or Off

Normal Mode (Operational) 4.5 mA max V

Full Power-Down Mode(Static) 1 µA max SCLK On or Off, typically TBD nA
Full Power-Down Mode(Dynamic) TBD mA typ V

Power Dissipation

4

Normal Mode (Operational) 13.5 mW max VDD= 3 V, f
Full Power-Down 3 µW max V

NOTES

1

Temperature range from –40°C to +85°C.

2

See Terminology.

3

Guranteed by Characterization.

4

See Power Versus Throughput Rate section.

Specifications subject to change without notice.

MIN

= + 2.5V, f

REF

to T

, unless otherwise noted.)

MAX

=52 MHz, f

SCLK

Digital I/Ps= 0V or V

= 2.35V to 3.6V, f

DD

= 3V, f

DD

DD

= 3 V

SAMPLE

SAMPLE

SAMPLE

DD

SAMPLE

=1MSPS

= 3MSPS

=3MSPS unless

=3MSPS

REV. PrB

–5–

PRELIMINARY TECHNICAL DATA

AD7273/AD7274

TIMING SPECIFICATIONS

Limit at T

MIN

, T

MAX

1

(VDD= +2.35 V to +3.6 V; V

= 2.5V, TA= T

REF

Preliminary Technical Data

to T

MIN

, unless otherwise noted.)

MAX

Parameter AD7273/AD7274 Units Description

f

SCLK

2

20 KHz min

3

52 MHz max

t

CONVERT

t

QUIET

14 x t

SCLK

12 x t

SCLK

TBD ns min Minimum Quiet Time required between Bus Relinquish

AD7274

AD7273

and start of Next Conversion

t

1

t

2

4

t

3

4

t

4

t

5

t

6

4

t

7

5

t

8

t

NOTES

1
2
3
4
5

6

Specifications subject to change without notice.

6

power-up

Guaranteed by Characterization. All input signals are specified with tr=tf=5ns (10% to 90% of V
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Minimum
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage.
t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
See Power-up Time section.

f

10 ns min Minimum CS Pulse Width
TBD ns min CS to SCLK Setup Time
TBD ns max Delay from CS Until SDATA Three-State Disabled
TBD ns max Data Access Time After SCLK Falling Edge

0.4t

0.4t

SCLK
SCLK

ns min SCLK Low Pulse Width

ns min SCLK High Pulse Width
TBD ns min SCLK to Data Valid Hold Time
TBD ns max SCLK Falling Edge to SDATA Three-State
TBD ns min SCLK Falling Edge to SDATA Three-State
TBD µs max Power Up Time from Full Power-down

) and timed from a voltage level of 1.6Volts.

DD

at which specifications are guaranteed.

sclk

8

, quoted in the

I

OL

I

OH

OUTPUT

PIN

200µA

TO

C

L

25pF

200µA

Figure 1. Load Circuit for Digital Output

Timing Specifications

t

4

SCLK

SDAT A

Figure 2. Access time after SCLK falling edge

+1.6V

t

7

SCLK

SDAT A

V

IH

V

IL

Figure 3. Hold time after SCLK falling edge

t

SCLK

V

IH

V

IL

SDATA

8

1.6 V

Figure 4. SCLK falling edge to SDATA Three-State

–6–

REV. PrB