Analog Devices AD7249AN, AD7249SQ, AD7249BR, AD7249BN, AD7249AR Datasheet

LC2MOS

a

FEATURES
Two 12-Bit CMOS DAC Channels with

On-Chip Voltage Reference
Output Amplifiers

Three Selectable Output Ranges per Channel

–5 V to +5 V, 0 V to +5 V, 0 V to +10 V
Serial Interface
125 kHz DAC Update Rate
Small Size: 16-Lead DIP or SOIC
Low Power Dissipation

APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports

GENERAL DESCRIPTION

The AD7249 DACPORT contains a pair of 12-bit, voltage­output, digital-to-analog converters with output amplifiers and
Zener voltage reference on a monolithic CMOS chip. No exter­nal trims are required to achieve full specified performance.

The output amplifiers are capable of developing +10 V across a
2 kΩ load. The output voltage ranges with single supply opera­tion are 0 V to +5 V or 0 V to +10 V, while an additional bipolar
± 5 V output range is available with dual supplies. The ranges
are selected using the internal gain resistor.

Interfacing to the AD7249 is serial, minimizing pin count and
allowing a small package size. Standard control signals allow
interfacing to most DSP processors and microcontrollers. The
data stream consists of 16 bits, DB15 to DB13 are don’t care
bits, the 13th bit (DB12) is used as the channel select bit and
the remaining 12 bits (DB11 to DB0) contain the data to update
the DAC. The 16-bit data word is clocked into the input register
on each falling SCLK edge.

The data format is natural binary in both unipolar ranges, while
either offset binary or twos complement format may be selected
in the bipolar range. A CLR function is provided which sets the
output to 0 V in both unipolar ranges and in the twos comple­ment bipolar range, while with offset binary data format, the
output is set to –REFIN. This function is useful as a power-on
reset as it allows the outputs to be set to a known voltage level.

Dual 12-Bit Serial DACPORT

®

AD7249

FUNCTIONAL BLOCK DIAGRAM

V

DD

AD7249

REFOUT

REFIN

AGND

DGND

SCLK SDIN BIN/COMP CLR LDACSYNC

INPUT SHIFT REGISTER

The AD7249 features a serial interface which allows easy con­nection to both microcomputers and 16-bit digital signal proces­sors with serial ports. The serial data may be applied at rates up
to 2 MHz allowing a DAC update rate of 125 kHz.

The AD7249 is fabricated on linear compatible CMOS

2

(LC

MOS), an advanced, mixed technology process. It is pack-

aged in 16-lead DIP and 16-lead SOIC packages.

PRODUCT HIGHLIGHTS

1. Two complete 12-bit DACPORTs
The AD7249 contains two complete voltage output, 12-bit
DACs in both 16-lead DIP and SOIC packages.

2. Single or dual supply operation

3. Minimum 3-wire interface to most DSP processors

4. DAC update rate—125 kHz

12-BIT
DAC A

12-BIT
DAC B

V

SS

2R

2R

A1

2R

2R

A2

R

V

R

V

OFSA

OUTA

OFSB

OUTB

DACPORT is a registered trademark of Analog Devices, Inc.

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD7249–SPECIFICATIONS

+5 V, RL = 2 k⍀, CL = 100 pF to AGND. All specifications T

(VDD = +12 V to +15 V,1 VSS = O V or –12 V to –15 V,1 AGND = DGND = O V, REFIN =

to T

MIN

unless otherwise noted.)

MAX

Parameter A Version2B Version2S Version2Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution 12 12 12 Bits
Relative Accuracy
Differential Nonlinearity
Unipolar Offset Error

Bipolar Zero Error

Full-Scale Error

3, 4

3

3

3

3

± 1 ± 1/2 ± 1 LSB max
± 0.9 ± 0.9 ± 0.9 LSB max Guaranteed Monotonic
± 5 ± 5 ± 6 LSB max VSS = 0 V or –12 V to –15 V1; DAC

Latch Contents All 0s

± 6 ± 5 ± 7 LSB max VSS = –12 V to –15 V

1

DAC Latch Contents All 0s

± 6 ± 6 ± 7 LSB max

Full-Scale Temperature Coefficient ± 5 ± 5 ± 5 ppm of FSR/°C typ

REFERENCE OUTPUT

REFOUT 4.95/5.05 4.95/5.05 4.95/5.05 V min/V max
Reference Temperature Coefficient ± 25 ± 25 ±30 ppm/°C typ
Reference Load Change
(∆V

vs. IL) –1 –1 –1 mV max Reference Load Current (IL)

REFOUT

Change (0 µA–100 µA)

REFERENCE INPUT

Reference Input Range, REFIN 4.95/5.05 4.95/5.05 4.95/5.05 V min/V max 5 V ± 1%
Input Current 5 5 5 µA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 2.4 2.4 V min

0.8 0.8 0.8 V max

Input Current

I

IN

Input Capacitance

5

± 1 ± 1 ± 1 µA max VIN = 0 V to V
8 8 8 pF max

DD

ANALOG OUTPUTS

Output Range Resistor,

& R

R

OFSA

OFSB

Output Voltage Ranges
Output Voltage Ranges

6

6

15/30 15/30 15/30 kΩ min/ max
+5, +10 +5, +10 +5, +10 V Single Supply; VSS = 0 V
+5, +10, ± 5 +5, +10, ± 5 +5, +10, ± 5 V Dual Supply; VSS = –12 V or –15 V

DC Output Impedance 0.5 0.5 0.5 Ω typ

AC CHARACTERISTICS

5

Voltage Output Settling-Time Settling Time to Within

± 1/2 LSB of Final Value
Positive Full-Scale Change 10 10 10 µs max Typically 3 µs
Negative Full-Scale Change 10 10 10 µs max Typically 5 µs

Digital-to-Analog Glitch Impulse

Digital Feedthrough
Digital Crosstalk

3

3

3

30 30 30 nV secs typ 1 LSB Change Around

Major Carry

10 10 10 nV secs typ
10 10 10 nV secs typ

POWER REQUIREMENTS

Range +10.8/+16.5 +11.4/+15.75 +11.4/+15.75 V min/V max For Specified Performance Unless

V

DD

Otherwise Stated

Range (Dual Supplies) –10.8/–16.5 –11.4/–15.75 –11.4/–15.75 V min/V max For Specified Performance Unless

V

SS

Otherwise Stated

I

DD

15 15 15 mA max Output Unloaded; Typically 11 mA

ISS (Dual Supplies) 5 5 5 mA max Output Unloaded; Typically 3 mA

NOTES

1

Power supply tolerance, A Version: ± 10%; B, S Versions: ±5%.

2

Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.

3

See Terminology.

4

Measured with respect to REFIN and includes unipolar/bipolar offset error.

5

Guaranteed by design not production tested.

6

0 V to 10 V output range available only with VDD ≥ 14.25 V.

Specifications subject to change without notice.

–2–

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TIMING CHARACTERISTICS

WARNING!

ESD SENSITIVE DEVICE

(VDD = +12 V to +15 V,3 VSS = 0 V or –12 V to –15 V,3 AGND = DGND = 0 V, RL = 2 k⍀,

1, 2

CL = 100 pF. All specifications T

MIN

to T

unless otherwise noted.)

MAX

AD7249

Limit at T

MIN

to T

MAX

Parameter (All Versions) Unit Conditions/Comments

4

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

NOTES

1

Timing specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage
level of 1.6 V.

2

See Figure 8.

3

Power supply tolerance, A Version: ± 10%; B, S Versions: ±5%.

4

SCLK Mark/Space Ratio range is 45/55 to 55/45.

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

VDD to AGND, DGND . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V

to AGND, DGND . . . . . . . . . . . . . . . . . . +0.3 V to –17 V

SS

AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V

V

OUTA, B

2

to AGND . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V

REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

REFIN to AGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to V

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Power Dissipation Plastic DIP . . . . . . . . . . . . . . . . . . . 600 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . +117°C/W

θ

JA

200 ns min SCLK Cycle Time
15 ns min SYNC to SCLK Falling Edge Setup Time
50 ns min SYNC to SCLK Hold Time
0 ns min Data Setup Time
150 ns min Data Hold Time
0 ns min SYNC High to LDAC Low
20 ns min LDAC Pulsewidth
0 ns min LDAC High to SYNC Low
50 ns min CLR Pulsewidth
20 ns min SYNC High Time

1

Power Dissipation, Cerdip . . . . . . . . . . . . . . . . . . . . . . 600 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76°C/W

θ

JA

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300°C

Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . 600 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

θ

+ 0.3 V

DD

+ 0.3 V

DD

DD

JA

Lead Temperature (Soldering)

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.

2

The outputs may be shorted to voltages in this range provided the power dissipation

of the package is not exceeded.

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . +300°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7249 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. C –3–

AD7249

PIN FUNCTION DESCRIPTION (DIP & SOIC PIN NUMBERS)

Pin Mnemonic Description

11 REFOUT Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the

part using its internal reference, REFOUT should be connected to REFIN.

12 REFIN Voltage Reference Input. It is internally buffered before being applied to both DACs. The nominal

reference voltage for specified operation of the AD7249 is 5 V.

13R

14V

OFSB

OUTB

15 AGND Analog Ground. Ground reference for all analog circuitry.
16 CLR Clear, Logic Input. Taking this input low clears both DACs. It sets V

17 BIN/COMP Logic Input. This input selects the data format to be either binary or twos complement. In both uni-

18 DGND Digital Ground. Ground reference for all digital circuitry.
19 SDIN Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.

10 LDAC Load DAC, Logic Input. Updates both DAC outputs. The DAC outputs are updated on the falling

11 SCLK Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
12 SYNC Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readi-

13 V
14 V

15 V

16 R

DD

OUTA

SS

OFSA

Output Offset Resistor for the amplifier of DAC B. It is connected to V

for the +5 V range, to

OUTB

AGND for the +10 V range and to REFIN for the –5 V to +5 V range.
Analog Output Voltage of DAC B. This is the buffer amplifier output voltage. Three different output

voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.

OUTA

and V

to 0 V in both

OUTB

unipolar ranges and the twos complement bipolar range and to –REFIN in the offset binary bipolar
range.

polar ranges natural binary format is selected by connecting this input to a Logic “0”. In the bipolar
configuration offset binary format is selected with a Logic “0” while a Logic “1” selects twos complement.

edge of this signal or alternatively if this line is permanently low, an automatic update mode is se­lected whereby both DACs are updated on the 16th falling SCLK pulse.

ness for a new data word.
Positive Power Supply.
Analog Output Voltage of DAC A. This is the buffer amplifier output voltage. Three different output

voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V.
Negative Power Supply (used for the output amplifier only) may be connected to 0 V for single sup-

ply operation or –12 V to –15 V for dual supplies.
Output Offset Resistor for the amplifier of DAC A. It is connected to V

for the +5 V range, to

OUTA

AGND for the +10 V range and to REFIN for the –5 V to +5 V range.

PIN CONFIGURATIONS

(DIP and SOIC)

1

REFOUT R

2

REFIN V

3

R

OFSB

V

4

OUTB

AGND

CLR

BIN/COMP LDAC

DGND SDIN

AD7249

TOP VIEW

5

(Not to Scale)

6

7

8

16

OFSA

15

SS

14

V

OUTA

V

13

DD

12

SYNC

11

SCLK

10

9

ORDERING GUIDE

Temperature Relative Package

Model Range Accuracy Option

AD7249AN –40°C to +85°C ± 1 LSB N-16
AD7249BN –40°C to +85°C ± 1/2 LSB N-16
AD7249AR –40°C to +85°C ± 1 LSB R-16
AD7249BR –40°C to +85°C ± 1/2 LSB R-16
AD7249SQ1–55°C to +125°C ± 1 LSB Q-16

NOTE

1

Available to /883B processing only. Contact your local sales office for military
data sheet.

–4–

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