ANALOG DEVICES AD7245A, AD7248A Service Manual

LC2MOS

DB0 DB11 DGND

V

SS

AGND

V

DD

REF OUT

R

OFS

R

FB

V

OUT

AD7245A

V

REF

2R 2R

CONTROL

LOGIC

DAC

DAC LATCH

INPUT LATCH

CS

WR

LDAC

CLR

a

FEATURES
12-Bit CMOS DAC with Output Amplifier and

Reference

Improved AD7245/AD7248:

12 V to 15 V Operation
ⴞ1/2 LSB Linearity Grade

Faster Interface—30 ns Typ Data Setup Time
Extended Plastic Temperature Range (–40ⴗC to +85ⴗC)
Single or Dual Supply Operation
Low Power—65 mW Typ in Single Supply
Parallel Loading Structure: AD7245A
(8+4) Loading Structure: AD7248A

GENERAL DESCRIPTION

The AD7245A/AD7248A is an enhanced version of the industry
standard AD7245/AD7248. Improvements include operation
from 12 V to 15 V supplies, a ±1/2 LSB linearity grade, faster
interface times and better full scale and reference variations with

. Additional features include extended temperature range

V

DD

operation for commercial and industrial grades.

The AD7245A/AD7248A is a complete, 12-bit, voltage output,
digital-to-analog converter with output amplifier and Zener voltage
reference on a monolithic CMOS chip. No external user trims
are required to achieve full specified performance.

Both parts are microprocessor compatible, with high speed data
latches and double-buffered interface logic. The AD7245A accepts
12-bit parallel data that is loaded into the input latch on the
rising edge of CS or WR. The AD7248A has an 8-bit-wide data
bus with data loaded to the input latch in two write operations.
For both parts, an asynchronous LDAC signal transfers data
from the input latch to the DAC latch and updates the ana
output. The AD7245A also has a CLR signal on the DAC latch
which allows features such as power-on reset to be implemented.

The on-chip 5 V buried Zener diode provides a low noise, tem­perature compensated reference for the DAC. For single supply
operation, two output ranges of 0 V to 5 V and 0 V to 10 V are
available, while these two ranges plus an additional ±5 V range
are available with dual supplies. The output amplifiers are capa­ble of developing 10 V across a 2 kΩ load to GND.

The AD7245A/AD7248A is fabricated in linear compatible CMOS

2

(LC

MOS), an advanced, mixed technology process that combines
precision bipolar circuits with low power CMOS logic. The
AD7245A is available in a small, 0.3" wide, 24-lead DIP
SOIC and in 28-terminal surface mount packages. The AD7248A
is packaged in a small, 0.3" wide, 20-lead DIP and SOIC and in
20-terminal surface mount packages.

DACPORT is a registered trademark of Analog Devices, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

and

log

12-Bit DACPORTs

AD7245A/AD7248A

AD7245A FUNCTIONAL BLOCK DIAGRAM

AD7248A FUNCTIONAL BLOCK DIAGRAM

V

DD

REF OUT

V

REF

AGND

LDAC

WR

CONTROL

CSLSB

CSMSB

LOGIC

4-BIT

INPUT

LATCH

PRODUCT HIGHLIGHTS

1. The AD7245A/AD7248A is a 12-bit DACPORT® on a single
chip. This single chip design and small package size offer
considerable space saving and increased reliability over
multichip designs.

2. The improved interface times on the part allows easy, direct
interfacing to most modern microprocessors.

3. The AD7245A/AD7248A features a wide power supply range
allowing operation from 12 V supplies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

R

OFS

2R 2R

DAC

DAC LATCH

AD7248A

8-BIT

INPUT

LATCH

DB7 DB0 DGND

R

FB

V

OUT

V

SS

AD7245A/AD7248A–SPECIFICATIONS

AGND = DGND = O V, RL = 2 k⍀, CL = 100 pF. All specifications T

2

A

2

B

to T

MIN

2

T

unless otherwise noted.)

MAX

(VDD = +12 V to +15 V,1 VSS = O V or –12 V to –15 V,

1

Parameter Version Version Version Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution 12 12 12 Bits
Relative Accuracy @ 25°C

to T

T

MIN

MIN

to T

MAX

MAX

T
Differential Nonlinearity
Unipolar Offset Error @ 25°C

T

to T

MIN

MAX

Bipolar Zero Error @ 25°C

T

to T

MIN

MAX

DAC Gain Error

3, 6

Full-Scale Output Voltage Error7 @ 25°C

∆Full Scale/∆V
∆Full Scale/∆V

DD

SS

Full-Scale Temperature Coefficient8±40 ±30 ±40

3

±3/4 ±1/2 ±1/2 LSB max
±1 ± 3/4 ± 3/4 LSB max

3

3

3

±1 ± 1 ±1 LSB max Guaranteed Monotonic
±3 ± 3 ±3 LSB max VSS = 0 V or –12 V to –15 V
±5 ± 5 ±5 LSB max Typical Tempco is ±3 ppm of FSR5/°C.
±3 ±2 ±2 LSB max R

±1/2 LSB max VDD = 15 V ± 10%

connected to REF OUT; VSS = –12 V to –15 V

OFS

4

±5 ± 4 ±4 LSB max Typical Tempco is ±3 ppm of FSR5/°C.
±2 ± 2 ±2 LSB max
±0.2 ±0.2 ±0.2 % of FSR max VDD = 15 V
±0.06 ± 0.06 ±0.06 % of FSR/V max VDD = +12 V to +15 V
±0.01 ± 0.01 ±0.01 % of FSR/V max VSS = –12 V to –15 V

ppm of FSR/°C max

VDD = 15 V

4

4

REFERENCE OUTPUT

REF OUT @ 25°C 4.99/5.01 4.99/5.01 4.99/5.01 V min/V max VDD = 15 V
∆REF OUT/∆V

DD

2 2 2 mV/V max VDD = 12 V to 15 V

4

Reference Temperature Coefficient ±25 ±25 ±35 ppm/°C typ
Reference Load Change

(∆REF OUT vs. ∆I) –1 –1 –1 mV max Reference Load Current Change (0–100 µA)

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance

IN

9

INH

INL

2.4 2.4 2.4 V min

0.8 0.8 0.8 V max
±10 ±10 ±10 µA max VIN = 0 V to V
8 8 8 pF max

DD

ANALOG OUTPUTS

Output Range Resistors 15/30 15/30 15/30 kΩ min/kΩ max
Output Voltage Ranges

10

5, 10 5, 10 5, 10 V VSS = 0 V; Pin Strappable
5, 10, 5, 10, 5, 10, VSS = –12 V to –15 V;4 Pin Strappable
±5 ± 5 ±5V

DC Output Impedance 0.5 0.5 0.5 Ω typ

AC CHARACTERISTICS

9

Voltage Output Settling Time Settling Time to Within ±1/2 LSB of Final Value

Positive Full-Scale Change 7 7 10 µs max DAC Latch All 0s to All 1s
Negative Full-Scale Change 7 7 10 µs max DAC Latch All 1s to All 0s; VSS = –12 V to –15 V

Output Voltage Slew Rate 2 2 1.5 V/µs min
Digital Feedthrough

3

10 10 10 nV-s typ

Digital-to-Analog Glitch Impulse 30 30 30 nV-s typ

POWER REQUIREMENTS

V

DD

+10.8/ +10.8/ +10.8/ V min/ For Specified Performance Unless Otherwise Stated
+16.5 +16.5 +16.5 V max

V

SS

–10.8/ –10.8/ –10.8/ V min/ For Specified Performance Unless Otherwise Stated

–16.5 –16.5 –16.5 V max
IDD @ 25°C 9 9 9 mA max Output Unloaded; Typically 5 mA
T

to T

MlN

ISS (Dual Supplies) 3 3 5 mA max Output Unloaded; Typically 2 mA

NOTES

1

Power supply tolerance is ± 10%.

2

Temperature ranges are as follows: A/B Versions; –40°C to +85°C; T Version; –55°C to +125°C.

3

See Terminology.

4

With appropriate power supply tolerances.

5

FSR means Full-Scale Range and is 5 V for the 0 V to 5 V output range and 10 V for both the 0 V to 10 V and ±5 V output ranges.

6

This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.

7

This error is calculated with respect to an ideal 4.9988 V on the 0 V to 5 V and ±5 V ranges; it is calculated with respect to an ideal 9.9976 V on the 0 V to 10 V
range. It includes the effects of internal voltage reference, gain and offset errors.

8

Full-Scale TC = ∆FS/∆T, where ∆FS is the full-scale change from TA = 25°C to T

9

Guaranteed by design and characterization, not production tested.

10

0 V to 10 V output range is available only when VDD ≥ +14.25 V.

MAX

10 10 12 mA max Output Unloaded

or T

MAX

.

MIN

Specifications subject to change without notice.

4

4

–2–

REV. B

AD7245A/AD7248A

WARNING!

ESD SENSITIVE DEVICE

SWITCHING CHARACTERISTICS

1

(VDD = +12 V to +15 V;2 VSS = 0 V to –12 V to –15 V;2 See Figures 5 and 7.)

Parameter A, B Versions T Version Unit Conditions

t

1

@ 25°C 55 55 ns typ Chip Select Pulsewidth
T

to T

MIN

t

2

MAX

80 100 ns min

@ 25°C 40 40 ns typ Write Pulsewidth

to T

T

MIN

t

3

MAX

80 100 ns min

@ 25°C 0 0 ns min Chip Select to Write Setup Time
T

to T

MIN

t

4

MAX

0 0 ns min

@ 25°C 0 0 ns min Chip Select to Write Hold Time
T

to T

MIN

t

5

MAX

0 0 ns min

@ 25°C 40 40 ns typ Data Valid to Write Setup Time

to T

T

MIN

t

6

MAX

80 80 ns min

@ 25°C 10 10 ns min Data Valid to Write Hold Time
T

to T

MIN

t

7

MAX

10 10 ns min

@ 25°C 40 40 ns typ Load DAC Pulsewidth
T

to T

MIN

t

(AD7245A Only)

8

MAX

80 100 ns min

@ 25°C 40 40 ns typ Clear Pulsewidth
T

to T

MIN

NOTES

1

Sample tested at 25°C to ensure compliance.

2

Power supply tolerance is ± 10%.

MAX

80 100 ns min

ABSOLUTE MAXIMUM RATINGS

1

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

DD

V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V

V

to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

OUT

V

OUT

V

OUT

REF OUT

2

to V
to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 24 V

SS

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –32 V, 0 V

DD

2

to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C

DD

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

DD

DD

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

The output may be shorted to voltages in this range provided the power dissipation

of the package is not exceeded. V
80 mA.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

short circuit current is typically

OUT

REV. B

–3–

AD7245A/AD7248A

AD7245A ORDERING GUIDE

Temperature Relative Package
Range Accuracy Option

2

Model

1

AD7245AAN –40°C to +85°C ± 3/4 LSB N-24
AD7245ABN –40°C to +85°C ±1/2 LSB N-24
AD7245AAQ –40°C to +85°C ±3/4 LSB Q-24
AD7245ATQ

3

–55°C to +125°C ± 3/4 LSB Q-24
AD7245AAP –40°C to +85°C ±3/4 LSB P-28A
AD7245AAR –40°C to +85°C ±3/4 LSB R-24
AD7245ABR –40°C to +85°C ± 1/2 LSB R-24
AD7245ATE3–55°C to +125°C ± 3/4 LSB E-28A

NOTES

1

To order MIL-STD-883, Class B processed parts, add /883B to part number.

Contact our local sales office for military data sheet and availability.

2

E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip

Carrier; Q = Cerdip; R = SOIC.

3

This grade will be available to /883B processing only.

AD7248A ORDERING GUIDE

Temperature Relative Package

Range Accuracy Option

2

Model

1

AD7248AAN –40°C to +85°C ± 3/4 LSB N-20
AD7248ABN –40°C to +85°C ±1/2 LSB N-20
AD7248AAQ –40°C to +85°C ±3/4 LSB Q-20
AD7248ATQ

3

–55°C to +125°C ± 3/4 LSB Q-20
AD7248AAP –40°C to +85°C ±3/4 LSB P-20A
AD7248AAR –40°C to +85°C ±3/4 LSB R-20
AD7248ABR –40°C to +85°C ± 1/2 LSB R-20

NOTES

1

To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact our local sales office for military data sheet and availability.

2

N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.

3

This grade will be available to /883B processing only.

TERMINOLOGY

RELATIVE ACCURACY

Relative Accuracy, or endpoint nonlinearity, is a measure of the
actual deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after allowing for
zero and full scale and is normally expressed in LSBs or as a
percentage of full-scale reading.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.

DIGITAL FEEDTHROUGH

Digital Feedthrough is the glitch impulse injected from the digital
inputs to the analog output when the inputs change state. It is
measured with LDAC high and is specified in nV-s.

DAC GAIN ERROR

DAC Gain Error is a measure of the output error between an
ideal DAC and the actual device output with all 1s loaded after
offset error has been allowed for. It is, therefore defined as:

Measured Value—Offset—Ideal Value

where the ideal value is calculated relative to the actual refer­ence value.

UNIPOLAR OFFSET ERROR

Unipolar Offset Error is a combination of the offset errors of the
voltage mode DAC and the output amplifier and is measured
when the part is configured for unipolar outputs. It is present
for all codes and is measured with all 0s in the DAC register.

BIPOLAR ZERO OFFSET ERROR

Bipolar Zero Offset Error is measured when the part is config­ured for bipolar output and is a combination of errors from the
DAC and output amplifier. It is present for all codes and is
measured with a code of 2048 (decimal) in the DAC register.

SINGLE SUPPLY LINEARITY AND GAIN ERROR

The output amplifier of the AD7245A/AD7248A can have a
true negative offset even when the part is operated from a single
positive power supply. However, because the lower supply rail
to the part is 0 V, the output voltage cannot actually go nega­tive. Instead the output voltage sits on the lower rail and this
results in the transfer function shown. This is an offset effect
and the transfer function would have followed the dotted line if
the output voltage could have gone negative. Normally, linearity
is measured after offset and full scale have been adjusted or
allowed for. On the AD7245A/AD7248A the negative offset is
allowed for by calculating the linearity from the code which the
amplifier comes off the lower rail. This code is given by the
negative offset specification. For example, the single supply
linearity specification applies between Code 3 and Code 4095
for the 25°C specification and between Code 5 and Code 4095
over the T

MIN

to T

temperature range. Since gain

MAX

error is
also measured after offset has been allowed for, it is calculated
between the same codes as the linearity error. Bipolar linearity and
gain error are measured between Code 0 and Code 4095.

OUTPUT

VO LTAG E

0V

NEGATIVE

OFFSET

DAC CODE

–4–

REV. B

AD7245A PIN FUNCTION DESCRIPTIONS

(DIP PIN NUMBERS)

AD7245A/AD7248A

Pin Mnemonic Description

lV

SS

Negative Supply Voltage (0 V for single
supply operation).

2R

OFS

Bipolar Offset Resistor. This provides
access to the on-chip application resistors
and allows different output voltage ranges.

3 REF OUT Reference Output. The on-chip reference

is provided at this pin and is used when
configuring the part for bipolar outputs.

4 AGND Analog Ground.

5 DB11 Data Bit 11. Most Significant Bit (MSB).

6–11 DB10–DB5 Data Bit 10 to Data Bit 5.

12 DGND Digital Ground.

13–16 DB4–DB1 Data Bit 4 to Data Bit 1.

17 DB0 Data Bit 0. Least Significant Bit (LSB).
18 CS Chip Select Input (Active LOW). The

device is selected when this input is active.

AD7245A PIN CONFIGURATIONS

DIP and SOIC

PLCC

Pin Mnemonic Description

19 WR Write Input (Active LOW). This is used in

conjunction with CS to write data into the
input latch of the AD7245A.

20 LDAC Load DAC Input (Active LOW). This is

an asynchronous input which when active
transfers data from the input latch to the
DAC latch.

21 CLR Clear Input (Active LOW). When this

input is active the contents of the DAC
latch are reset to all 0s.

22 V

23 R

DD

FB

Positive Supply Voltage.

Feedback Resistor. This allows access to
the amplifier’s feedback loop.

24 V

OUT

Output Voltage. Three different output
voltage ranges can be chosen: 0 V to 5 V,
0 V to 10 V or –5 V to +5 V.

LCCC

V

1

SS

2

R

OFS

REF OUT

(MSB) DB11

3

4

AGND

DB10

DB9

DB8

DB7

DB6

DB5

DGND DB4

AD7245A

5

TOP VIEW

(NOT TO SCALE)

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

V

OUT

R

FB

V

DD

CLR

LDAC

WR

CS

DB0 (LSB)

DB1

DB2

DB3

5

AGND

DB11

6

7

DB10

NC

8

DB9

9

DB8

10

DB7

11

NC = NO CONNECT

OFS

R

REF OUT

4

2

3

AD7245A

TOP VIEW

(NOT TO SCALE)

DB6

DB5

DGND

OUT

SS

V

NC

1

NC

DB4

DB3

VDDRFBV

262728

5

25

CLR

24

LDAC

23

WR

NC

22

21

CS

DB0

20

DB1

19

18171615141312

DB2

AGND

6

DB11

7

DB10

8

NC

9

DB9

10

DB8

11

DB7

NC = NO CONNECT

OFS

R

REF OUT

4 3 2 1 28 27 26

AD7245A

(NOT TO SCALE)

12 13 14 15 16 17 18

DB5

DB6

SS

V

NC

TOP VIEW

NC

DGND

OUT

V

DB4

RFBV

DB3

DD

DB2

25

CLR

24

LDAC

23

WR

NC

22

21

CS

DB0

20

DB1

19

REV. B

–5–

AD7245A/AD7248A

AD7248A PIN FUNCTION DESCRIPTIONS

(ANY PACKAGE)

Pin Mnemonic Description

l V

SS

Negative Supply Voltage (0 V for single

supply operation).

2 R

OFS

Bipolar Offset Resistor. This provides
access to the on-chip application resistors
and allows different output voltage ranges.

3 REF OUT Reference Output. The on-chip reference

is provided at this pin and is used when
configuring the part for bipolar outputs.

4 AGND Analog Ground.

5 DB7 Data Bit 7.

6 DB6 Data Bit 6.

7 DB5 Data Bit 5.

8 DB4 Data Bit 4.

9 DB3 Data Bit 3.

10 DGND Digital Ground.

11 DB2 Data Bit 2/Data Bit 10.

12 DB1 Data Bit 1/Data Bit 9.

13 DB0 Data Bit 0 (LSB)/Data Bit 8.

Pin Mnemonic Description

14 CSMSB Chip Select Input for MS Nibble. (Active

LOW). This selects the upper 4 bits of the
input latch. Input data is right justified.

15 CSLSB Chip Select Input for LS byte. (Active

LOW). This selects the lower 8 bits of the
input latch.

16 WR Write Input. This is used in conjunction

with CSMSB and CSLSB to load data
into the input latch of the AD7248A.

17 LDAC Load DAC Input (Active LOW). This is

an asynchronous input which when active
transfers data from the input latch to the
DAC latch.

18 V

19 R

DD

FB

Positive Supply Voltage.

Feedback Resistor. This allows access to
the amplifier’s feedback loop.

20 V

OUT

Output Voltage. Three different output
voltage ranges can be chosen: 0 V to 5 V,
0 V to 10 V or –5 V to +5 V.

V

R

OFS

REF OUT

AGND

(MSB) DB7

DB6

DB5

DB4

DB3

DGND

DIP and SOIC

1

SS

2

3

4

AD7248A

5

TOP VIEW

(NOT TO SCALE)

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

V

OUT

R

FB

V

DD

LDAC

WR

CSLSB

CSMSB

DB0 (LSB)

DB1

DB2

AD7248A PIN CONFIGURATIONS

PLCC

OFS

OUT

RFBV

VSSR

REF OUT

3

2 1 20 19

AGND

(MSB) DB7

DB6

DB5

DB4

4

5

6

(NOT TO SCALE)

7

8

9 10 11 12 13

DB3

PIN 1
IDENTIFIER

AD7248A

TOP VIEW

DB2

DGND

DB1

18

17

16

15

14

(LSB) DB0

V

DD

LDAC

WR

CSLSB

CSMSB

AGND

(MSB) DB7

DB6

DB5

DB4

LCCC

REF OUT

3

4

5

AD7248A

6

TOP VIEW

(NOT TO SCALE)

7

8

910111213

DB3

OFS

R

2

DGND

20 191

DB2

OUTVSS

DB1

RFBV

18

17

16

15

14

(LSB) DB0

V

DD

LDAC
WR

CSLSB
CSMSB

–6–

REV. B

Typical Performance Characteristics–

AD7245A/AD7248A

7

6

IDD (VSS = –15V, VIN = 0V OR VDD)

5

IDD (VSS = 0V, VIN = 0V OR VDD)

4

3

2

POWER SUPPLY CURRENT – mA

ISS (VSS = –15V)

1

0

–55 70

–25 0

TEMPERATURE – ⴗC

OR V

INL

25

INH

)

85 125

VDD = +15VIDD (VSS = –15V, VIN = V

TPC 1. Power Supply Current vs. Temperature

500

200

100

nV Hz

50

REFERENCE (NO DECOUPLING)

REFERENCE (DECOUPLED*)

VDD = 15V

= 0V

V

SS

= 25ⴗC

T

A

4.995

5.000

5.005

REFERENCE VOLTAGE – Vo lt s

5.010

–55

–25 0 25 70 85 125

TEMPERATURE – ⴗC

TPC 4. Reference Voltage vs. Temperature

PSRR – dB

80

60

40

OUTPUT WITH ALL

0s ON DAC

OUTPUT WITH ALL

1s ON DAC

DECOUPLING*

NO
DECOUPLING

DECOUPLING

20

10

50 2k100

*REFERENCE DECOUPLING COMPONENTS AS PER FIGURE 8

200 500 1k

OUTPUT WITH

ALL 0s ON DAC

FREQUENCY – Hz

20k5k 10k 50k

TPC 2. Noise Spectral Density vs. Frequency

1mV

100

90

10

0%

2V

1␮s

TPC 3. Positive-Going Settling Time
(V

= +15 V, VSS = –15 V)

DD

20

VDD = 15V WITH
100mV p-p SIGNAL

0

50 100

*POWER SUPPLY DECOUPLING CAPACITORS ARE 10␮F AND 0.1␮F

NO DECOUPLING

1k

2k200 10k

FREQUENCY – Hz

20k 100k

TPC 5. Power Supply Rejection Ration vs. Frequency

1mV

100

90

10

0%

2V

1␮s

TPC 6. Negative Going Settling Time
(V

= +15 V, VSS = –15 V)

DD

REV. B

–7–

AD7245A/AD7248A

CIRCUIT INFORMATION

D/A SECTION

The AD7245A/AD7248A contains a 12-bit voltage mode digi­tal-to-analog converter. The output voltage from the converter
has the same positive polarity as the reference voltage allowing
single supply operation. The reference voltage for the DAC is
provided by an on-chip buried Zener diode.

The DAC consists of a highly stable, thin-film, R–2R ladder and
twelve high-speed NMOS single-pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in Figure 1.

V

REF

AGND

2R 2R

DB0

R

OFS

R

R

2R

DB1

RR R

2R 2R2R

DB9

2R

DB10

SHOWN FOR ALL 1s ON DAC

DB11

2R

R

FB

V

OUT

Figure 1. D/A Simplified Circuit Diagram

The input impedance of the DAC is code dependent and can
vary from 8 kΩ to infinity. The input capacitance also varies
with code, typically from 50 pF to 200 pF.

The small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the ampli­fier is low with a figure of 25 nV/√Hz at a frequency of 1 kHz.
The broadband noise from the amplifier has a typical peak-to­peak figure of 150 µV for a 1 MHz output bandwidth. There is
no significant difference in the output noise between single and
dual supply operation.

VOLTAGE REFERENCE

The AD7245A/AD7248A contains an internal low noise buried
Zener diode reference which is trimmed for absolute accuracy
and temperature coefficient. The reference is internally connected
to the DAC. Since the DAC has a variable input impedance at
its reference input the Zener diode reference is buffered. This
buffered reference is available to the user to drive the circuitry
required for bipolar output ranges. It can be used as a reference
for other parts in the system provided it is externally buffered.
The reference will give long-term stability comparable with the
best discrete Zener reference diodes. The performance of the
AD7245A/AD7248A is specified with internal reference, and all
the testing and trimming is done with this reference. The reference
should be decoupled at the REF OUT pin and recommended
decoupling components are 10 µF and 0.1 µF capacitors in
series with a 10 Ω resistor. A simplified schematic of the refer­ence circuitry is shown in Figure 3.

V

DD

OP AMP SECTION

The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The user has access to two gain
setting resistors which can be connected to allow different out­put voltage ranges (discussed later). The buffer amplifier is
capable of developing up to 10 V across a 2 kΩ load to GND.

The output amplifier can be operated from a single positive
power supply by tying V

= AGND = 0 V. The amplifier can

SS

also be operated from dual supplies to allow a bipolar output
range of –5 V to +5 V. The advantages of having dual supplies
for the unipolar output ranges are faster settling time to voltages
near 0 V, full sink capability of 2.5 mA maintained over the entire
output range and elimination of the effects of negative offset on
the transfer characteristic (outlined previously). Figure 2 shows
the sink capability of the amplifier for single supply operation.

5

4

3

– mA

SINK

2

I

1

TA = T

TO T

MIN

MAX

0

061

23 4 5 78 910

OUTPUT VOLTAGE – Volts

Figure 2. Typical Single Supply Sink Current vs.
Output Voltage

I

C

V- TO -I

AGND

I

IS TEMPERATURE

C

COMPENSATION CURRENT

TO DAC

REF OUT

Figure 3. Internal Reference

DIGITAL SECTION

The AD7245A/AD7248A digital inputs are compatible with
either TTL or 5 V CMOS levels. All data inputs are static pro­tected MOS gates with typical input currents of less than 1 nA.
The control inputs sink higher currents (150 µA max) as a result
of the fast digital interfacing. Internal input protection of all
logic inputs is achieved by on-chip distributed diodes.

The AD7245A/AD7248A features a very low digital feedthrough
figure of 10 nV-s in a 5 V output range. This is due to the volt­age mode configuration of the DAC. Most of the impulse is
actually as a result of feedthrough across the package.

INTERFACE LOGIC INFORMATION—AD7245A

Table I shows the truth table for AD7245A operation. The part
contains two 12-bit latches, an input latch and a DAC latch. CS
and WR control the loading of the input latch while LDAC
controls the transfer of information from the input latch to the
DAC latch. All control signals are level triggered; and therefore,
either or both latches may be made transparent, the input latch
by keeping CS and WR “LOW”, the DAC latch by keeping
LDAC “LOW.” Input data is latched on the rising edge of WR.

–8–

REV. B

AD7245A/AD7248A

L

The data held in the DAC latch determines the analog output of
the converter. Data is latched into the DAC latch on the rising
edge of LDAC. This LDAC signal is an asynchronous signal
and is independent of WR. This is useful in many applications.
However, in systems where the asynchronous LDAC can occur
during a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. For
example, if LDAC goes LOW while WR is “LOW,” then the
LDAC signal must stay LOW for t

or longer after WR goes

7

high to ensure correct data is latched through to the output.

Table I. AD7245A Truth Table

CLR LDAC WR CS Function

H L L L Both Latches are Transparent
H H H X Both Latches are Latched
H H X H Both Latches are Latched
H H L L Input Latches Transparent
HH g L Input Latches Latched
H L H H DAC Latches Transparent
H g H H DAC Latches Latched
L X X X DAC Latches Loaded with all 0s
g H H H DAC Latches Latched with All

0s and Output Remains at
0 V or –5 V

g L L L Both Latches are Transparent

and Output Follows Input Data

H = High State, L = Low State, X = Don’t Care

The contents of the DAC latch are reset to all 0s by a low level
on the CLR line. With both latches transparent, the CLR line
functions like a zero override with the output brought to 0 V in
the unipolar mode and –5 V in the bipolar mode for the dura­tion of the CLR pulse. If both latches are latched, a “LOW”
pulse on the CLR input latches all 0s into the DAC latch and the
output remains at 0 V (or –5 V) after the CLR line has returned
“HIGH.” The CLR line can be used to ensure power-up to 0 V
on the AD7245A output in unipolar operation and is also use­ful, when used as a zero override, in system calibration cycles.

Figure 4 shows the input control logic for the AD7245A and the
write cycle timing for the part is shown in Figure 5.

t

1

CS

t

3

WR

DAC

DATA

NOTES

1. SEE TIMING SPECIFICATIONS.

2. ALL INPUT RISE AND FALL TIMES MEASURES FROM 10% TO

90% OF 5V, t

3. TIMING MEASUREMENT REFERENCE LEVEL IS

4. IF LDAC IS ACTIVATED WHILE WR IS LOW, LDAC MUST STAY

LOW FOR t7 OR LONGER AFTER WR GOES HIGH.

t

2

t

5

VA LI D

= tf = 5ns.

r

V

+ V

INH

INL

2

DATA

t

4

t

6

HIGH IMPEDANCE

BUS

t

7

5V

0V

5V

0V

5V

0V

5V

0V

Figure 5. AD7245A Write Cycle Timing Diagram

INTERFACE LOGIC INFORMATION—AD7248A

The input loading structure on the AD7248A is configured for
interfacing to microprocessors with an 8-bit wide data bus. The
part contains two 12-bit latches—an input latch and a DAC
latch. Only the data held in the DAC latch determines the ana­log output from the converter. The truth table for AD7248A
operation is shown in Table II, while the input control logic
diagram is shown in Figure 6.

4

UPPER

4 BITS

OF INPUT

LATCH

DAC LATCH

12

8

DB7 – DB0

8

LOWER

8 BITS

OF INPUT

LATCH

LDAC

CSMSB

CSLSB

WR

LDAC

CLR

WR

CS

DAC LATCH

INPUT LATCH

CSMSB, CSLSB and WR control the loading of data from the
external data bus to the input latch. The eight data inputs on
the AD7248A accept right justified data. This data is loaded to
the input latch in two separate write operations. CSLSB and

Figure 6. AD7248A Input Control Logic

WR control the loading of the lower 8-bits into the 12-bit wide

INPUT DATA

Figure 4. AD7245A Input Control Logic

latch. The loading of the upper 4-bit nibble is controlled by
CSMSB and WR. All control inputs are level triggered, and
input data for either the lower byte or upper 4-bit nibble is
latched into the input latches on the rising edge of WR (or
either CSMSB or CSLSB). The order in which the data is
loaded to the input latch (i.e., lower byte or upper 4-bit nibble

REV. B

first) is not important.

–9–

AD7245A/AD7248A

The LDAC input controls the transfer of 12-bit data from the
input latch to the DAC latch. This LDAC signal is also level
triggered, and data is latched into the DAC latch on the rising
edge of LDAC. The LDAC input is asynchronous and indepen­dent of WR. This is useful in many applications especially in
the simultaneous updating of multiple AD7248A outputs. How­ever, in systems where the asynchronous LDAC can occur during
a write cycle (or vice versa) care must be taken to ensure that
incorrect data is not latched through to the output. In other words,
if LDAC goes low while WR and either CS input are low (or
WR and either CS go low while LDAC is low), then the LDAC
signal must stay low for t

or longer after WR returns high to

7

ensure correct data is latched through to the output. The write
cycle timing diagram for the AD7248A is shown in Figure 7.

t

1

CSLSB

CSMSB

WR

LDAC

DATA

t

1

t

3

t

2

t

5

VA LI D

IN

DATA

t

4

t

3

t

6

t

2

t

5

VA LI D

DATA

t

4

t

7

t

6

5V

0V

5V

0V

5V

0V

5V

0V

5V

0V

Figure 7. AD7248A Write Cycle Timing Diagram

An alternate scheme for writing data to the AD7248A is to tie
the CSMSB and LDAC inputs together. In this case exercising
CSLSB and WR latches the lower 8 bits into the input latch.
The second write, which exercises CSMSB, WR and LDAC
loads the upper 4-bit nibble to the input latch and at the same
time transfers the 12-bit data to the DAC latch. This automatic
transfer mode updates the output of the AD7248A in two write
operations. This scheme works equally well for CSLSB and
LDAC tied together provided the upper 4-bit nibble is loaded
to the input latch followed by a write to the lower 8 bits of
the input latch.

Table II. AD7248A Truth Table

CSLSB CSMSB WR LDAC Function

L H L H Load LS Byte into Input Latch
LH g H Latches LS Byte into Input Latch
g H L H Latches LS Byte into Input Latch
H L L H Loads MS Nibble into Input Latch
HL g H Latches MS Nibble into Input Latch
H g L H Latches MS Nibble into Input Latch
H H H L Loads Input Latch into DAC Latch
HH Hg Latches Input Latch into DAC Latch
H L L L Loads MS Nibble into Input Latch and

H H H H No Data Transfer Operation

H = High State, L = Low State

Loads Input Latch into DAC Latch

APPLYING THE AD7245A/AD7248A

The internal scaling resistors provided on the AD7245A/
AD7248A allow several output voltage ranges. The part can
produce unipolar output ranges of 0 V to 5 V or 0 V to 10 V
and a bipolar output range of –5 V to +5 V. Connections for
the various ranges are outlined below.

UNIPOLAR (0 V TO 10 V) CONFIGURATION

The first of the configurations provides an output voltage range
of 0 V to 10 V. This is achieved by connecting the bipolar offset
resistor, R

, to AGND and connecting RFB to V

OFS

OUT.

In this
configuration the AD7245A/AD7248A can be operated single
supply (V
required, a V

= 0 V = AGND). If dual supply performance is

SS

of –12 V to –15 V should be applied. Figure 8

SS

shows the connection diagram for unipolar operation while the
table for output voltage versus the digital code in the DAC latch
is shown in Table III.

10⍀

0.1␮F

*DIGITAL CIRCUITRY

OMITTED FOR CLARITY

10␮F

REF OUT

REF

R

OFS

2R

V

REF

DAC

DGND

V

DD

2R

AD7245A/AD7248A*

AGND

V

SS

R

FB

V

OUT

Figure 8. Unipolar (0 to 10 V) Configuration

Table III. Unipolar Code Table (0 V to 10 V Range)

DAC Latch Contents
MSB LSB Analog Output, V

1 1 1 1 1 1 1 1 1 1 1 1 +2 V

1 0 0 0 0 0 0 0 0 0 0 1 +2 V

1 0 0 0 0 0 0 0 0 0 0 0 +2 V

0 1 1 1 1 1 1 1 1 1 1 1 +2 V

0 0 0 0 0 0 0 0 0 0 0 1 +2 V

REF

REF

REF

REF

REF

ⴛ

ⴛ

ⴛ

ⴛ

ⴛ



4095



4096





2049



4096





2048



4096





2047



4096






4096



OUT













=+V

REF











1




0 0 0 0 0 0 0 0 0 0 0 0 0 V





NOTE: 1 LSB = 2 ⴛ V

REF

(2

–12

) = V

REF



2048



1




–10–

REV. B

AD7245A/AD7248A

UNIPOLAR (0 V TO 5 V) CONFIGURATION

The 0 V to 5 V output voltage range is achieved by tying R

and V

R

FB

AD7248A can be operated single supply (V

together. For this output range the AD7245A/

OUT

= 0 V) or dual sup-

SS

OFS

,

ply. The table for output voltage versus digital code is as in Table
III, with 2 × V

1 LSB = V

replaced by V

REF

–12

(2

REF

) = V

. Note that for this range

REF





1

REF

ⴛ




4096

.




BIPOLAR CONFIGURATION

The bipolar configuration for the AD7245A/AD7248A, which
gives an output voltage range from –5 V to +5 V, is achieved by
connecting the R
and V

. The AD7245A/AD7248A must be operated from

OUT

input to REF OUT and connecting R

OFS

FB

dual supplies to achieve this output voltage range. The code
table for bipolar operation is shown in Table IV.

Table IV. Bipolar Code Table

DAC Latch Contents
MSB LSB Analog Output, V



1 1 1 1 1 1 1 1 1 1 1 1 +V

REF

×




2047

2048



1 0 0 0 0 0 0 0 0 0 0 1 +V

REF

×




2048

OUT








1




1 0 0 0 0 0 0 0 0 0 0 0 0 V





0 1 1 1 1 1 1 1 1 1 1 1 –V

0 0 0 0 0 0 0 0 0 0 0 1 –V

0 0 0 0 0 0 0 0 0 0 0 0 –V

NOTE: 1 LSB = 2 × V

REF

(2

–11

) = V

REF

REF

REF

REF

×

×

×








2048





2047



2048





2048



2048



2048

1











= –V

REF






1




AGND BIAS

The AD7245A/AD7248A AGND pin can be biased above sys­tem GND (AD7245A/AD7248A DGND) to provide an offset
“zero” analog output voltage level. With unity gain on the
amplifier (R

OFS

= V

= RFB) the output voltage, V

OUT

OUT

is

expressed as:

V

OUT

= V

+ D ⴛ V

BIAS

REF

where D is a fractional representation of the digital word in the
DAC latch and V

is the voltage applied to the AD7245A/

BIAS

AD7248A AGND pin.

Because the current flowing out of the AGND pin varies with
digital code, the AGND pin should be driven from a low imped­ance source. A circuit configuration is outlined for AGND bias
in Figure 9 using the AD589, a +1.23 V bandgap reference.

If a gain of 2 is used on the buffer amplifier the output voltage,
V

is expressed as

OUT

V

OUT

= 2(V

+ D ⴛ V

BIAS

REF

)

In this case care must be taken to ensure that the maximum
output voltage is not greater than V

–3 V. The VDD–V

DD

OUT

overhead must be greater than 3 V to ensure correct operation
of the part. Note that V

and VSS for the AD7245A/AD7248A

DD

must be referenced to DGND (system GND). The entire circuit
can be operated in single supply with the V

pin of the

SS

AD7245A/AD7248A connected to system GND.

10⍀

+

0.1␮F

15V

27k⍀

AGND

V

BIAS

+

AD589

–

*DIGITAL CIRCUITRY

OMITTED FOR CLARITY.

10␮F

REF OUT

REF

R

OFS

2R

REF

DAC

AD7245A/AD7248A*

DGND

V

V

DD

2R

R

FB

V

OUT

V

SS

SYSTEM

GND

Figure 9. AGND Bias Circuit

PROGRAMMABLE CURRENT SINK

Figure 10 shows how the AD7245A/AD7248A can be config­ured with a power MOSFET transistor, the VN0300M, to
provide a programmable current sink from V

DD

or V

SOURCE

.
The VN0300M is placed in the feedback of the AD7245A/
AD7248A amplifier. The entire circuit can be operated in single
supply by tying the V
The sink current, I

10⍀

+

0.1␮F

*DIGITAL CIRCUITRY

OMITTED FOR CLARITY.

10␮F

REF OUT

REF

of the AD7245A/AD7248A to AGND.

SS

, can be expressed as:

SINK

D ×V

=

I

SINK

R

OFS

REF

DAC

DGND

V

REF

R1

V

DD

2R

AD7245A/AD7248A*

AGND

2R

V

SS

R

FB

V

OUT

V

SOURCE

LOAD

I

SINK

VN0300M

R1

Figure 10. Programmable Current Sink

Using the VN0300M, the voltage drop across the load can typi­cally be as large as V

SOURCE

–6 V) with V

of the DAC at

OUT

5 V. Therefore, for a current of 50 mA flowing in the R1 (with
all 1s in the DAC register) the maximum load is 200 Ω with
V

= 15 V. The VN0300M can actually handle currents

SOURCE

up to 500 mA and still function correctly in the circuit, but in
practice the circuit must be used with larger values of V

SOURCE

otherwise it requires a very small load.

REV. B

–11–

AD7245A/AD7248A

Since the tolerance value on the reference voltage of the AD7245A/
AD7248A is ±0.2%, then the absolute value of I

can vary by

SINK

±0.2% from device to device for a fixed value of R1.

Because the input bias current of the AD7245A/AD7248A’s op
amp is only of the order of picoamps, its effect on the sink cur­rent is negligible. Tying the R

input to RFB input reduces this

OFS

effect even further and prevents noise pickup which could occur
if the R

pin was left unconnected.

OFS

The circuit of Figure 10 can be modified to provide a pro­grammable current source to AGND or –V

SINK

(for –V

SINK

,
dual supplies are required on the AD7245A/AD7248A). The
AD7245A/AD7248A is configured as before. The current through
R1 is mirrored with a current mirror circuit to provide the pro­grammable source current (see CMOS DAC Application Guide,
Publication No. G872-30-10/84, for suitable current mirror
circuit). As before the absolute value of the source current will
be affected by the ±0.2% tolerance on V

. In this case the perfor-

REF

mance of the current mirror will also affect the value of the
source current.

FUNCTION GENERATOR WITH PROGRAMMABLE
FREQUENCY

Figure 11 shows how the AD7245A/AD7248A with the AD537,
voltage-to-frequency converter and the AD639, trigonometric
function generator to provide a complete function generator
with programmable frequency. The circuit provides square wave,
triwave and sine wave outputs, each output of ±10 V amplitude.

The AD7245A/AD7248A provides a programmable voltage to
the AD537 input. Since both the AD7245A/AD7248A and
AD537 are guaranteed monotonic, the output frequency will
always increase with increasing digital code. The AD537 pro­vides a square wave output which is conditioned for ±10 V by
amplifier A1. The AD537 also provides a differential triwave
output. This is conditioned by amplifiers A2 and A3 to provide the
±1.8 V triwave required at the input of the AD639. The triwave is
further scaled by amplifier A4 to provide a ± 10 V output.

Adjusting the triwave applied to the AD639 adjust the distortion
performance of the sine wave output, (10 V in configuration
shown). Amplitude, offset and symmetry of the triwave can affect
the distortion. By adjusting these, via VR1 and VR2, an output
sine wave with harmonic distortion of better than –50 dB can be
achieved at low and intermediate frequencies.

Using the capacitor value shown in Figure 11 for C

(i.e., 680 pF)

F

the output frequency range is 0 to 100 kHz over the digital input
code range. The step size for frequency increments is 25 Hz.
The accuracy of the output frequency is limited to 8 or 9 bits by
the AD537, but is guaranteed monotonic to 12 bits.

MICROPROCESSOR INTERFACING—AD7245

AD7245A—8086 INTERFACE

Figure 12 shows the 8086 16-bit processor interfacing to the
AD7245A. In the setup shown in Figure 12, the double buffer­ing feature of the DAC is not used and the LDAC input is tied
LOW. AD0–AD11 of the 16-bit data bus are connected to the
AD7245A data bus (DB0–DB11). The 12-bit word is written
to the AD7245A in one MOV instruction and the analog output
responds immediately. In this example the DAC address is
D000. A software routine for Figure 12 is given in Table V.

8086

ALE

WR

AD15

AD0

*LINEAR CIRCUITRY OMITTED FOR CLARITY

ADDRESS BUS

16-BIT
LATCH

ADDRESS/DATA BUS

ADDRESS

DECODE

CS

LDAC

AD7245A*

WR

DB11
DB0

Figure 12. AD7245A to 8086 Interface

ⴞ10V

SQUARE

WAVE

+15V

V

DD

AD7245A/
AD7248A

R

V

OUT

R
REF
OUT

10⍀

0.1␮F10␮F

DGND

AGND

+

OFS

V

+15V

33k⍀

15k⍀

A1

20k⍀

+V

S

+

GND

O/P

+V

FB

SS

DEC

AD537

C

C

V

OS

–V

82k⍀

+15V

+15V

4.7k⍀

S

20k⍀

S

56k⍀

5k⍀
VR2

10k⍀
VR1

5.6k⍀

56k⍀

C

F

680pF

A1, A2, A3, A4 – 2 ⴛ AD712

Figure 11. Programmable Function Generator

–12–

A2

4.12k⍀

4.12k⍀

A3

3.9k⍀

3.9k⍀

X1

X2

U1

U2

COM

Y2

AD639

22k⍀

A4

22k⍀

+V

Z1

Z2

UP

–V

ⴞ10V
TRI WAVE

+15V

S

W

S

–15V

–15V

ⴞ1V
SINE WAVE

REV. B

Table V. Sample Program for Loading AD7245A from 8086

A8–A15

ALE

WR

AD0–AD7

AD7248A*

OCTAL
LATCH

ADDRESS

DECODE

ADDRESS BUS

CSMSB
LDAC

WR

DB0–DB7

CSLSB

*LINEAR CIRCUITRY OMITTED FOR CLARITY.

ADDRESS/DATA BUS

8085A/8088

ASSUME DS: DACLOAD, CS: DACLOAD

DACLOAD SEGMENT AT 000

00 8CC9 MOV CS, : DEFINE DATA SEGMENT

CS REGISTER

02 8ED9 MOV DS, : EQUAL TO CODE

CX SEGMENT REGISTER

04 BF00D0 0MOV DI, : LOAD DI WITH D000

#D000

07 C705 MOV MEM, : DAC LOADED WITH WXYZ

“YZWX” #YZWX

0B EA00 00 : CONTROL IS RETURNED TO
0E 00 FF THE MONITOR PROGRAM

In a multiple DAC system the double buffering of the AD7245A
allows the user to simultaneously update all DACs. In Figure
13, a 12-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri­ate address, CS4 (i.e., LDAC) is brought LOW, updating all the
DACs simultaneously.

ADDRESS BUS

8086

ALE

WR

AD15

AD0

16-BIT

LATCH

CS4

DATA BUS

ADDRESS

DECODE

CS1

CS

LDAC
WR

DB11
DB0

AD7245A*

AD7245A/AD7248A

MC68000

AS

DTACK

R/W

D0–D15

*LINEAR CIRCUITRY OMITTED FOR CLARITY

Figure 14. AD7245A to MC68000 Interface

Table VI. Sample Routine for Loading AD7245A from 68000

01000 MOVE.W #X,D0 The desired DAC data,

MOVE.W D0,$E000 The Data X is transferred

MOVE.B #228,D7 Control is returned to

TRAP #14 instructions.

ADDRESS BUS

ADDRESS

DECODE

DATA BUS

CS

LDAC

AD7245A*

WR

DB11

DB0

X, is loaded into Data
Register 0. X may be any
value between 0 and 4094
(decimal) or 0 and OFFF
(hexadecimal).

between D0 and the
DAC Latch.

the System Monitor
Program using these two

CS

AD7245A*

LDAC
WR

DB11

DB0

CS

AD7245A*

LDAC
WR

DB11

DB0

*LINEAR CIRCUITRY OMITTED FOR CLARITY

Figure 13. AD7245A to 8086 Multiple DAC Interface

AD7245A—MC68000 INTERFACE

Interfacing between the MC68000 and the AD7245A is accom­plished using the circuit of Figure 14. Once again the AD7245A
is used in the single buffered mode. A software routine for load­ing data to the AD7245A is given in Table VI. In this example
the AD7245A is located at address E000, and the 12-bit word is
written to the DAC in one MOVE instruction.

MICROPROCESSOR INTERFACE—AD7248A

Figure 15 shows the connection diagram for interfacing the
AD7248A to both the 8085A and 8088 microprocessors. This
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demultiplexed. Data to be
loaded to the AD7248A is right justified. The AD7248A is
memory mapped with a separate memory address for the input
latch high byte, the input latch low byte and the DAC latch.
Data is first written to the AD7248A input latch in two write
operations. Either the high byte or the low byte data can be
written first to the AD7248A input latch. A write to the AD7248A
DAC latch address transfers the input latch data to the DAC
latch and updates the output voltage. Alternatively, the LDAC
input can be asynchronous or can be common to a number
of AD7248As for simultaneous updating of a number of volt­age channels.

Figure 15. AD7248A to 8085A/8088 Interface

REV. B

–13–

AD7245A/AD7248A

A connection diagram for the interface between the AD7248A
and 68008 microprocessor is shown in Figure 16. Once again
the AD7248A acts as a memory mapped device and data is right
justified. In this case the AD7248A is configured in the auto­matic transfer mode which means that the high byte of the input
latch has the same address as the DAC latch. Data is written to
the AD7248A by first writing data to the AD7248A low byte.
Writing data to the high byte of the input latch also transfers the
input latch contents to the DAC latch and updates the output.

A0–A19

AS

68008

R/W

DTACK

D0–D7

*LINEAR CIRCUITRY OMITTED FOR CLARITY

ADDRESS BUS

ADDRESS

DECODE

DATA BUS

CSLSB
CSMSB

LDAC

WR

AD7248A*

DB0–DB7

Figure 16. AD7248A to 68008 Interface

An interface circuit for connections to the 6502 or 6809 micro­processors is shown in Figure 17. Once again, the AD7248A is
memory mapped and data is right justified. The procedure for
writing data to the AD7248A is as outlined for the 8085A/8088.
For the 6502 microprocessor the φ2 clock is used to generate
the WR, while for the 6809 the E signal is used.

Figure 18 shows a connection diagram between the AD7248A
and the 8051 microprocessor. The AD7248A is port mapped in
this interface and is configured in the automatic transfer mode.
Data to be loaded to the input latch low byte is output to Port 1.
Output Line P3.0, which is connected to CSLSB of the AD7248A,
is pulsed to load data into the low byte of the input latch. Puls­ing the P3.1 line, after the high byte data has been set up on
Port 1, updates the output of the AD7248A. The WR input of the
AD7248A can be hardwired low in this application because
spurious address strobes on CSLSB and CSMSB do not occur.

P3.0

P3.1

8051

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

*ADDITIONAL PINS OMITTED FOR CLARITY.

CSLSB

CSMSB

LDAC

WR

AD7248A*

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

Figure 18. AD7248A to MCS-51 Interface

A0–A15

R/W

6502/6809

␾2 OR E

D0–D7

*LINEAR CIRCUITRY OMITTED FOR CLARITY.

ADDRESS BUS

ADDRESS

EN

DECODE

DATA BUS

Figure 17. AD7248A to 6502/6809 Interface

CSLSB
CSMSB
LDAC

WR

AD7248A*

DB0–DB7

–14–

REV. B

MECHANICAL INFORMATION—AD7245A

24

112

13

PIN 1

1.228 (31.19)

1.126 (31.14)

0.260 ⴞ 0.001
(6.61 ⴞ 0.03)

0.11 (2.79)

0.09 (2.28)

0.130 (3.30)

0.128 (3.25)

0.015 (0.381)

0.008 (0.204)

0.32 (8.128)

0.30 (7.62)

SEATING
PLANE

0.060 (1.52)

0.015 (0.38)

0.02 (0.5)

0.09 (2.28)

0.07 (1.78)

0.05 (1.27)

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.

PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN LEAD PLATED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

2

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

24-Lead Plastic DIP

(N-24)

AD7245A/AD7248A

0.614 (15.6)

0.598 (15.2)

24 13

1

PIN 1

0.012 (0.30)

0.004 (0.10)

0.458 (11.63)

0.442 (11.23)

0.050

(1.27)

BSC

0.100 (2.54)

0.064 (1.63)

0.458

SQ

(11.63)

MAX

SQ

0.088 (2.24)

NOTES

1

THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS.

2

APPLIES TO ALL FOUR SIDES.

ALL TERMINALS ARE GOLD PLATED

0.054 (1.37)

24-Lead SOIC

(R-24)

0.299 (7.6)

0.291 (7.4)

0.419 (10.65)

0.394 (10.00)

0.013 (0.32)

0.009 (0.23)

8ⴗ
0ⴗ

0.019 (0.49)

0.014 (0.35)

12

0.104 (2.65)

0.093 (2.35)

SEATING
PLANE

28-Terminal

Leadless Ceramic Chip Carrier

(E-28A)

0.300 (7.62)

REF

26

25

19

18

BSC

0.150
(3.51)

28

1

BOTTOM

VIEW

BSC

0.200
(5.08)
BSC

4

5

11

12

1

0.095 (2.41)

0.075 (1.90)

0.011 (0.28)

0.007 (0.18)
R TYP

0.075

(1.91)

REF

0.075

(1.91)

0.055 (1.40)

0.045 (1.14)

0.005 (0.13)

0.016 (0.40)

0.028 (0.71)

0.022 (0.56)

0.050
(1.27)
BSC

45ⴗ TYP

24-Lead Cerdip

(Q-24)

24

112

PIN 1

0.225

(5.715)

SEATING

MAX

PLANE

0.125

(3.175)

MIN

0.021 (0.533)

0.015 (0.381)

CERDIP LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED

IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS

0.070 (1.78)

0.030 (0.76)

1.290 (32.77) MAX

0.110 (2.794)

TYP

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.

0.090 (2.286)

13

(7.493)

0.070 (1.778)

0.020 (0.508)

TYP

28-Terminal

Plastic Leaded Chip Carrier

(P-28A)

0.032 (0.812)

0.026 (0.661)

4

5

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

11

12

0.456 (11.58)

0.450 (11.43)

0.495 (12.57)

0.485 (12.32)

SQ

SQ

0.180 (4.51)

0.165 (4.20)

26

25

19

18

0.110 (2.79)

0.085 (2.16)

0.021 (0.533)

0.013 (0.331)

0.050 ⴞ 0.005
(1.27 ⴞ 0.13)

0.295

MAX

0.180
(4.572)
MAX

0.320 (8.128)

0.290 (7.366)

15ⴗ
0ⴗ

0.430 (10.5)

0.390 (9.9)

0.012 (0.305)

0.008 (0.203)

REV. B

–15–

AD7245A/AD7248A

MECHANICAL INFORMATION —AD7248A

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

PIN 1

0.125

(3.175)

MIN

LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42

20 11

1

PIN 1

0.0500

0.011 (0.275)

0.005 (0.125)

20-Lead Plastic DIP

(N-20)

1.07 (27.18) MAX

20

110

0.021 (0.533)

0.015 (0.381)

0.021 (0.533)

0.015 (0.381)

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.

11

0.070 (1.77)

0.045 (1.15)

0.255 (6.477)

0.245 (6.223)

0.145
(3.683)
MIN

20-Lead SOIC

(R-20)

0.5118 (13.00)

0.4961 (12.60)

0.299 (7.60)

0.291 (7.40)

SEATING
PLANE

0.419 (10.65)

0.404 (10.00)

0.015 (0.38)

0.007 (0.18)

(1.27)

BSC

10

0.107 (2.72)

0.089 (2.26)

0.022 (0.56)

0.014 (0.36)

0.32 (8.128)

0.29 (7.366)

15ⴗ

0

0.18 (4.57)

0.125 (3.18)

0.011 (0.28)

0.009 (0.23)

8ⴗ
0ⴗ

0.034 (0.86)

0.018 (0.46)

20-Lead Cerdip

(Q-20)

0.11 (2.79)

0.09 (2.28)

20

110

PIN 1

0.20 (5.0)

0.14 (3.18)

0.15 (3.8)

0.125 (3.18)

LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42

0.97 (24.64)

0.935 (23.75)

0.02 (0.5)

0.016 (0.41)

LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.

11

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

SEATING
PLANE

20-Terminal

Plastic Leaded Chip Carrier

(P-20A)

0.173 ⴞ 0.008

SQ

SQ

(4.385 ⴞ 0.185)

0.050
(1.27)
BSC

0.105 ⴞ 0.015

(2.665 ⴞ 0.375)

0.045 ⴞ 0.003

(1.143 ⴞ 0.076)

0.020
(0.51)

MAX

0.105 ⴞ 0.015

(2.665 ⴞ 0.375)

3

4

8

(9.905 ⴞ 0.125)

19

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

13

9

0.390 ⴞ 0.005

18

14

0.150
(3.81)
MIN

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

15°

0.008 (0.20)

0°

0.020
(0.51) MIN

0.017 ⴞ 0.004

(0.432 ⴞ 0.101)

0.029 ⴞ 0.003

(0.737 ⴞ 0.076)

0.025
(0.64) MIN

C00996–0–3/01 (B)

Revision History

Location Page

Data Sheet changed from REV. A to REV. B.

Changed V

Changed A Version of Full-Scale Temperature Coefficient from ±30 to ±40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changed B and T Versions of V

Changed B and T Versions of V

Change to Note 1 and Note 9 of Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Change to Note 2 in Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Changes to R-24 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

= 15 V ± 5% to VDD = 15 V ± 10% in Static Performance section in Test Conditions/Comments column . . . . . . . . 2

DD

Power Requirements from +11.4/+15.75 to +10.8/+16.5 for V min.

DD

Power Requirements from –11.4/–15.75 to –10.8/–16.5 for V max . . . . . . . . . . . . . . . . . . . . . 2

SS

–16–

REV. B

PRINTED IN U.S.A.