ANALOG DEVICES AD7191 Service Manual
Pin-Programmable, Ultralow Noise, 24-Bit,
A
V
FEATURES
Pin-programmable output rate
Output data rate: 10 Hz, 50 Hz, 60 Hz, 120 Hz
Pin-programmable PGA
Gain: 1, 8, 64, 128
Pin-programmable power-down and reset
RMS noise: 15 nV @ 10 Hz (gain = 128)
Up to 21.5 noise free bits (gain = 1)
Internal or external clock
Bridge power-down switch
Offset drift: 5 nV/°C
Gain drift: 1 ppm/°C
Specified drift over time
Simultaneous 50 Hz/60 Hz rejection
Internal temperature sensor
Power supply: 3 V to 5.25 V
Current: 4.35 mA
Temperature range: –40°C to +105°C
Package: 24-lead TSSOP
INTERFACE
2-wire serial
SPI, QSPI™, and MICROWIRE™ compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Strain gauge transducers
Pressure measurement
Medical and scientific instrumentation
DD
Sigma-Delta ADC for Bridge Sensors
GENERAL DESCRIPTION
The AD7191 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-) ADC. The on-chip low noise gain
stage means that signals of small amplitude can be interfaced
directly to the ADC. It contains two differential analog inputs.
The part also includes a temperature sensor that can be used for
temperature compensation.
For ease-of-use, all the features of the AD7191 are controlled by
dedicated pins. The on-chip PGA has a gain of 1, 8, 64, or 128,
supporting a full-scale differential input of ±5 V, ±625 mV,
±78 mV, or ±39 mV. The output data rate can be programmed
to 10 Hz, 50 Hz, 60 Hz, or 120 Hz. Simultaneous 50 Hz and 60 Hz
rejection is obtained when the output data rate is set to 10 Hz
or 50 Hz; 60 Hz only rejection is obtained when the output data
rate is set to 60 Hz. The AD7191 can be operated with the
internal clock, or an external clock can be used.
The part operates with a power supply of 3 V to 5.25 V. It
consumes a current of 4.35 mA. It is available in a 24-lead
TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
DV
AGND DGND REFIN(+) REFIN(–)
DD
AD7191
AD7191
AIN1
AIN2
AIN3
AIN4
BPDSW
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
MUX
TEMPERATURE
SENSOR
PGA
MCLK1 MCLK2 ODR2 ODR1 TEMP
CLOCK
CIRCUITRY
Figure 1.
Σ-Δ
ADC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
SERIAL
INTERFACE
AND CONTROL
LOGIC
DOUT/RDY
SCLK
PDOWN
CHAN
CLKSEL
PGA2
PGA1
08163-001
AD7191
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface ............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 6
Timing Diagram ........................................................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
RMS Noise and Resolution Specifications .................................. 13
ADC Circuit Information .............................................................. 14
Overview ...................................................................................... 14
Filter, Data Rate, and Settling Time ......................................... 14
Gain .............................................................................................. 15
Analog Input Channels .............................................................. 15
Temperature Sensor ................................................................... 16
Power-Down (PDOWN) ........................................................... 16
Clock ............................................................................................ 16
Bipolar Configuration ................................................................ 16
Data Output Coding .................................................................. 16
Bridge Power-Down Switch ...................................................... 16
Reference ..................................................................................... 16
Digital Interface .......................................................................... 17
Grounding and Layout .............................................................. 17
Applications Information .............................................................. 19
Weigh Scales ................................................................................ 19
EMI Recommendations ............................................................. 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
5/09—Rev. 0 to Rev A
Changes to Gain Error Specification, Normal Mode
Rejection Specification..................................................................... 3
Changes to Table 3 ............................................................................ 7
5/09—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD7191
SPECIFICATIONS
AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; AGND = DGND = 0 V; REFIN(+) = AVDD; REFIN(−) = AGND; MCLK = 4.92 MHz; all
specifications T
Table 1.
Parameter1 AD7191B Unit Test Conditions/Comments
Output Data Rate 10, 50, 60, 120 Hz nom
No Missing Codes2 24 Bits min
Resolution
RMS Noise and Update Rates
Integral Nonlinearity
Gain = 12 ±10 ppm of FSR max ±2 ppm typical, AVDD = 5 V
±15 ppm of FSR max ±2 ppm typical., AVDD = 3 V
Gain > 1 ±5 ppm of FSR typ AVDD = 5 V
±12 ppm of FSR typ AVDD = 3 V
Offset Error ±150/gain μV typ
Offset Error Drift vs. Temperature ±150/gain nV/°C typ Gain = 1 or 8
±5 nV/°C typ Gain = 64 or 128
Offset Error Drift vs. Time 25 nV/1000 hours typ Gain = 64 or 128
Gain Error ±0.4 % typ
Gain Drift vs. Temperature ±1 ppm/°C typ
Gain Drift vs. Time 10 ppm/1000 hours typ Gain = 1
Power Supply Rejection 90 dB typ Gain = 1, AIN = 1 V
95 dB min 110 dB typical, gain > 1, AIN = 1 V/gain
Normal Mode Rejection2
Internal Clock
@ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
74 dB min 50 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
@ 60 Hz 97 dB min 60 Hz output data rate, 60 ± 1 Hz.
External Clock
@ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.
82 dB min 50 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz.
@ 60 Hz 120 dB min 60 Hz output data rate, 60 ± 1 Hz
Common-Mode Rejection
@ DC2 100 dB min Gain = 1, AIN = 1 V
@ DC 110 dB min Gain > 1, AIN = 1 V/gain
@ 50 Hz, 60 Hz2 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz
@ 50 Hz, 60 Hz2 120 dB min
ANALOG INPUTS
Differential Input Voltage Ranges ±V
±(AVDD – 1.25 V)/gain V min/V max Gain > 1
Absolute AIN Voltage Limits2
AGND + 250 mV V min
MIN
to T
, unless otherwise noted.
MAX
AV
/gain V nom
REF
− 250 mV
DD
V max
See the RMS Noise and Resolution Specifications
section
See the RMS Noise and Resolution Specifications
section
50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz
(60 Hz output data rate)
V
= REFIN(+) − REFIN(−), gain = 1, 8, 64, or 128
REF
Rev. A | Page 3 of 20
AD7191
Parameter1 AD7191B Unit Test Conditions/Comments
Analog Input Current
Input Current2 ±2 nA max Gain = 1
±3 nA max Gain > 1
Input Current Drift ±5 pA/°C typ
REFERENCE INPUT
REFIN Voltage AVDD V nom
Reference Voltage Range2 1 V min
AVDD V max
Absolute REFIN Voltage Limits2 AGND – 50 mV V min
AVDD + 50 mV V max
Average Reference Input Current 4.5 μA/V typ
Average Reference Input Current
±0.03 nA/V/°C typ External clock.
Drift
±1.3 nA/V/°C typ Internal clock.
Normal-Mode Rejection2
Same as for analog
inputs
Common-Mode Rejection 100 dB typ
TEMPERATURE SENSOR
Accuracy +2 °C typ Applies after user calibration at one temperature.
Sensitivity 2815 Codes/°C typ
BRIDGE POWER-DOWN SWITCH
RON 10 Ω max
Allowable Current2 30 mA max Continuous current.
INTERNAL/EXTERNAL CLOCK
Internal Clock
Frequency 4.92 + 4% MHz min/MHz max
Duty Cycle 50:50 % typ
External Clock/Crystal
Frequency 4.9152 MHz nom
2.4576/5.12 MHz min/MHz max
Input Low Voltage, V
0.8 V max DVDD = 5 V.
INL
0.4 V max DVDD = 3 V.
Input High Voltage, V
2.5 V min DVDD = 3 V.
INH
3.5 V min DVDD = 5 V.
Input Current ±10 μA max MCLKIN = DVDD or DGND.
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
2
2 V min
INH
2
0.8 V max
INL
Hysteresis2 0.1/0.25 V min/V max
Input Currents ±10 μA max VIN = DVDD or DGND.
LOGIC OUTPUT (DOUT/RDY)
Output High Voltage, VOH 2
Output Low Voltage, V
Output High Voltage, V
Output Low Voltage, V
2
OL
OH
2
OL
0.4 V max DVDD = 3 V, I
2
4 V min DVDD = 5 V, I
0.4 V max DVDD = 5 V, I
DVDD − 0.6
V min DVDD = 3 V, I
REFIN = REFIN(+) − REFIN(−).
The differential input must be limited to
− 1.25 V)/gain when gain > 1.
±(AV
DD
= 100 μA.
SOURCE
= 100 μA.
SINK
= 200 μA.
SOURCE
= 1.6 mA.
SINK
Rev. A | Page 4 of 20
AD7191
Parameter1 AD7191B Unit Test Conditions/Comments
Floating-State Leakage Current ±10 μA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset binary
POWER REQUIREMENTS3
Power Supply Voltage
AVDD − AGND
DVDD − DGND
Power Supply Currents
AIDD Current 0.85 mA max 0.75 mA typical, gain = 1.
3.6 mA max 3 mA typical, gain = 8.
5 mA max 4 mA typical, gain = 64 or 128.
DIDD Current 0.4 mA max 0.35 mA typical, DVDD = 3 V.
0.6 mA max 0.5 mA typical, DVDD = 5 V.
1.5 mA typ External crystal used.
IDD (Power-Down Mode) 3 μA max
1
Temperature range: −40°C to +105°C.
2
Specification is not production tested but is supported by characterization data at initial product release.
3
Digital inputs equal to DV
or DGND.
DD
3/5.25 V min/V max
2.7/5.25 V min/V max
Rev. A | Page 5 of 20
AD7191
TIMING CHARACTERISTICS
AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2.
Parameter
t
3
1, 2
Limit at T
100 ns min SCLK high pulse width
MIN
, T
(B Version) Unit Conditions/Comments
MAX
t4 100 ns min SCLK low pulse width
Read Operation
t1 0 ns min
PDOWN falling edge to DOUT/RDY
active time
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
3
t
0 ns min SCLK active edge to data valid delay4
2
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
5, 6
t
10 ns min Bus relinquish time after PDOWN inactive edge
5
80 ns max
t6 0 ns min SCLK inactive edge to PDOWN inactive edge
t7 10 ns min
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4
The SCLK active edge is the falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
SCLK inactive edge to DOUT/RDY
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY
returns high after a read of the ADC. The digital word can be read only once.
high
I
(1.6mA WITH DVDD = 5V,
SINK
100µA WIT H DV
DD
= 3V)
TIMING DIAGRAM
OUTPUT
Figure 2. Load Circuit for Timing Characterization
PDOWN (I)
DOUT/RDY (O )
SCLK (I)
NOTES
1. I = INPUT, O = OUTPUT
TO
PIN
50pF
(200µA WIT H DVDD = 5V,
I
SOURCE
100µA WIT H DV
t
1
t
2
t
3
t
4
Figure 3. Read Cycle Timing Diagram
1.6V
DD
= 3V)
08163-002
t
5
t
6
t
7
08163-003
Rev. A | Page 6 of 20
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