ANALOG DEVICES AD7171 Service Manual

V

A

A

16-Bit Low Power Sigma-Delta ADC

FEATURES

Output data rate: 125 Hz
Pin-programmable power-down and reset
Status function
Internal clock oscillator
Current: 135 μA
Power supply: 2.7 V to 5.25 V
–40°C to +105°C temperature range
Package: 10-lead 3 mm x 3 mm LFCSP

INTERFACE

2-wire serial (read-only device)
SPI compatible
Schmitt trigger on SCLK

APPLICATIONS

Weigh scales
Pressure measurement
Industrial process control
Portable instrumentation

GENERAL DESCRIPTION

The AD7171 is a very low power 16-bit analog-to-digital converter
(ADC). It contains a precision 16-bit sigma-delta (Σ-) ADC
and an on-chip oscillator. Consuming only 135 µA, the AD7171
is particularly suitable for portable or battery operated products
where very low power is a requirement. The AD7171 also has a
power-down mode in which the device consumes 5 A, thus
increasing the battery life of the product.

For ease-of-use, all the features of the AD7171 are controlled by
dedicated pins. Each time a data read occurs, eight status bits
are appended to the 16-bit conversion. These status bits contain
a pattern sequence that can be used to confirm the validity of
the serial transfer.

AD7171

FUNCTIONAL BLOCK DIAGRAM

GND

IN(+)

IN(–)

AD7171

Table 1.

V

= VDD RMS Noise P-P Noise

REF

5 V 11.5 V 76 V 16 bits 16 bits
3 V 6.9 V 45 V 16 bits 16 bits

The output data rate of the AD7171 is 125 Hz, whereas the
settling time is 24 ms. The AD7171 has one differential input
and a gain of 1. This is useful in applications where the user
needs to use an external amplifier to implement system-specific
filtering or gain requirements.

The AD7171 operates with a power supply from 2.7 V to 5.25 V.
It is available in a 10-lead LFCSP package.

The AD7170 is a 12-bit version of the AD7171. It has the same
feature set as the AD7171 and is pin-for-pin compatible.

DD

REFIN(+)

16-BIT Σ-Δ

INTERNAL

Figure 1.

REFIN(–)

DOUT/RDY

ADC

CLOCK

SCLK

PDRST

P-P
Resolution ENOB

08417-001

Rev. 0

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AD7171

TABLE OF CONTENTS

Features .............................................................................................. 1

Interface ............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ..................................................................... 5

Timing Diagrams .......................................................................... 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Output Noise and Resolution Specifications ................................ 9

ADC Circuit Information .............................................................. 10

Overview ..................................................................................... 10

Filter, Data Rate, and Settling Time ......................................... 10

Gain .............................................................................................. 10

Power-Down/Reset(

Analog Input Channel ............................................................... 10

Bipolar Configuration ................................................................ 10

Data Output Coding .................................................................. 11

Reference ..................................................................................... 11

Digital Interface .......................................................................... 11

Grounding and Layout .............................................................. 12

Applications Information .............................................................. 13

Temperature System ................................................................... 13S

Signal Conditioning Circuit ........................................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

PDRST

) .................................................... 10

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

AD7171

SPECIFICATIONS

VDD = 2.7 V to 5.25 V, V

Table 1.

Parameter

ADC CHANNEL

Output Data Rate (f
No Missing Codes
Resolution Peak-to-Peak (p-p) 16 Bits V
Effective Resolution (ENOB) 16 Bits V
RMS Noise See Tab le 6 µV V
Integral Nonlinearity ±0.4 LSB
Offset Error ±200 V
Offset Error Drift vs. Temperature ±250 nV/°C
Full-Scale Error ±0.015 % of FS
Gain Drift vs. Temperature ±0.07 LSB/°C
Power Supply Rejection 85 dB V

ANALOG INPUTS

Differential Input Voltage Range ±V
Absolute AINx Voltage Limits
Average Input Current

Average Input Current Drift ±60 pA/V/°C
DC Common-Mode Rejection 90 dB V

REFERENCE

External REFIN Voltage VDD V REFIN = REFIN(+) − REFIN(−)
Reference Voltage Range
Absolute REFIN Voltage Limits
Average Reference Input Current 400 nA/V
Average Reference Input Current

Drift

DC Common-Mode Rejection 110 dB

INTERNAL CLOCK

Frequenc y

2

64 − 5% 64 + 5% kHz

LOGIC INPUTS

SCLK, PDRST

2

Input Low Voltage, V

0.8 V VDD = 5 V
Input High Voltage, V

2.4 V VDD = 5 V

SCLK (Schmitt-Triggered Input)

Hysteresis 100 mV VDD = 3 V
140 mV VDD = 5 V
Input Currents ±2 µA VIN = VDD or GND
Input Capacitance 5 pF All digital inputs

= VDD, GND = 0 V, all specifications T

REF

AD7171B

Min Typ Max

) 125 Hz Settling time = 3/f

ADC

2

2

GND − 0.03 V

2

±400 nA/V

16 Bits

MIN

to T

, unless otherwise noted.

MAX

1

Unit Test Conditions/Comments

V V

REF

+ 0.03 V

DD

= 0 V, V

INx

= 0 V, V

INx

= 0 V, V

INx

= 1 V

INx

= REFIN(+) − REFIN(−)

REF

Input current varies with input
voltage

= 1 V

INx

2

0.5 V

2

GND − 0.03 V

V

DD

+ 0.03 V

DD

±0.15 nA/V/°C

0.4 V VDD = 3 V

INL

1.8 V VDD = 3 V

INH

2

REF

REF

REF

= VDD
= VDD
= VDD

ADC

Rev. 0 | Page 3 of 16

AD7171

1

Unit Test Conditions/Comments

Parameter

LOGIC OUTPUT (DOUT/RDY)

Output High Voltage, V

OH

2

V

AD7171B

Min Typ Max

− 0.6 V VDD = 3 V, I

DD

4 V VDD = 5 V, I
Output Low Voltage, V

2

0.4 V V

OL

DD

0.4 V VDD = 5 V, I
Floating-State Leakage Current ±2 µA
Floating-State Output Capacitance 5 pF
Data Output Coding Offset binary

POWER REQUIREMENTS

3

Power Supply Voltage

VDD – GND 2.7 5.25 V

Power Supply Currents

IDD Current 110 130 µA VDD = 3 V
135 150 µA VDD = 5 V
IDD (Power-Down/Reset Mode) 5 µA

1

Temperature range is –40°C to +105°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Digital inputs equal to VDD or GND.

= 3 V, I

SOURCE

SOURCE

= 100 µA

SINK

= 1.6 mA

SINK

= 100 µA
= 200 µA

Rev. 0 | Page 4 of 16

AD7171

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.25 V,, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.

Table 2.

Parameter

1, 2

Limit at T

MIN

, T

Unit Conditions/Comments

MAX

READ

t1 100 ns min SCLK high pulse width
t2 100 ns min SCLK low pulse width

3

t

0 ns min SCLK active edge to data valid delay4

3

60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.7 V to 3.6 V
t4 10 ns min

SCLK inactive edge to DOUT/RDY

high

RESET

t5 100 ns min
t6 25 ms typ

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

See Figure 3.

3

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is the falling edge of SCLK.

low pulse width

PDRST

high to data valid delay

PDRST

I

(1.6mA WITH VDD = 5V,

SINK

100µA WIT H V

TO

OUTPUT

PIN

50pF

I

SOURCE

100µA WIT H V

Figure 2. Load Circuit for Timing Characterization

= 3V)

DD

1.6V

(200µA WITH VDD = 5V,

= 3V)

DD

08417-002

TIMING DIAGRAMS

DOUT/RDY (O)

SCLK (I)

DOUT/RDY (O)

MSB LSB

t

3

I = INPUT, O = OUTPUT

Figure 3. Read Cycle Timing Diagram

PDRST (I)

t

5

I = INPUT, O = OUTPUT

Figure 4. Resetting the AD7171

t

4

t

1

t

2

08417-003

t

6

08417-004

Rev. 0 | Page 5 of 16