ANALOG DEVICES AD7147 Service Manual

CapTouch Programmable Controller for

A

V

www.BDTIC.com/ADI

FEATURES

Programmable capacitance-to-digital converter (CDC)

Femtofarad resolution
13 capacitance sensor inputs
9 ms update rate, all 13 sensor inputs
No external RC components required
Automatic conversion sequencer

On-chip automatic calibration logic

Automatic compensation for environmental changes

Automatic adaptive threshold and sensitivity levels
Register map is compatible with the AD7142
On-chip RAM to store calibration data
SPI-compatible (serial-peripheral-interface-compatible)

serial interface (AD7147)

2

I

C-compatible serial interface (AD7147-1)
Separate V
Interrupt output and general-purpose input/output (GPIO)
24-lead, 4 mm × 4 mm LFCSP

2.6 V to 3.3 V supply voltage
Low operating current

Full power mode: 1 mA
Low power mode: 21.5 µA

APPLICATIONS

Cell phones
Personal music and multimedia players
Smart handheld devices
Television, A/V, and remote controls
Gaming consoles
Digital still cameras

GENERAL DESCRIPTION

The AD7147 CapTouch™ controller is designed for use with
capacitance sensors implementing functions such as buttons,
scroll bars, and wheels. The sensors need only one PCB layer,
enabling ultrathin applications.

The AD7147 is an integrated CDC with on-chip environmental
calibration. The CDC has 13 inputs channeled through a switch
matrix to a 16-bit, 250 kHz sigma-delta (∑-∆) converter. The CDC
is capable of sensing changes in the capacitance of the external
sensors and uses this information to register a sensor activation.
By programming the registers, the user has full control over the
CDC setup.

High resolution sensors require minor software to run on the
host processor.

level for serial interface

DRIVE

Single-Electrode Capacitance Sensors

AD7147

FUNCTIONAL BLOCK DIAGRAM

C

SHIELDVCC

8 11 10 9

19

CIN0

20

CIN1

21

CIN2

22

CIN3

23

CIN4

24

CIN5

1

CIN6

CIN7

CIN8

CIN9

CIN10

CIN11

CIN12

DRIVE

2

3

4

5

6

7

MATRIX

SWITCH

SERIAL INTERFACE

AND CONTROL LOGI C

13 14 15 16 17

SDO/

SDI/

ADD0

SCLK CS/

SDA

The AD7147 is designed for single electrode capacitance
sensors (grounded sensors). There is an active shield output to
minimize noise pickup in the sensor.

The AD7147 has on-chip calibration logic to compensate for
changes in the ambient environment. The calibration sequence
is performed automatically and at continuous intervals as long
as the sensors are not touched. This ensures that there are no
false or nonregistering touches on the external sensors due to
a changing environment.

The AD7147 has an SPI-compatible serial interface, and the
AD7147-1 has an I

2

C®-compatible serial interface. Both parts have
an interrupt output, as well as a GPIO. There is a V
the voltage level for the serial interface independent of V

The AD7147 is available in a 24-lead, 4 mm × 4 mm LFCSP and
operates from a 2.6 V to 3.6 V supply. The operating current con­sumption in low power mode is typically 26 A for 13 sensors.

EXCITATION

SOURCE

AD7147/

AD7147-1

16-BIT

-

CDC

ADD1

Figure 1.

GND BIAS

CALIBRATI ON

RAM

CALIBRATI ON

ENGINE

CONTROL

AND DATA

REGISTERS

INTERRUPT

AND GPIO

LOGIC

INT

POWER-ON

RESET LOGIC

DRIVE

1812

GPIO

pin to set

.

CC

06663-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

AD7147

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Average Current Specifications .................................................. 4

SPI Timing Specifications (AD7147) ......................................... 5

I2C Timing Specifications (AD7147-1) ..................................... 6

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 11

Capacitance Sensing Theory ..................................................... 11

BIAS Pin ....................................................................................... 12

Operating Modes ........................................................................ 12

Capacitiance-to-Digital Converter ............................................... 14

Oversampling the CDC Output ............................................... 14

Capacitance Sensor Offset Control .......................................... 14

Conversion Sequencer ............................................................... 14

CDC Conversion Sequence Time ............................................ 16

CDC Conversion Results ........................................................... 16

Capacitance Sensor Input Configuration .................................... 17

CINx Input Multiplexer Setup .................................................. 17

Single-Ended Connections to the CDC .................................. 17

Noncontact Proximity Detection ................................................. 18

Recalibration ............................................................................... 18

Proximity Sensitivity .................................................................. 18

FF_SKIP_CNT ............................................................................ 21

Environmental Calibration ........................................................... 23

Capacitance Sensor Behavior Without Calibration ............... 23

Threshold Equations .................................................................. 24

Capacitance Sensor Behavior with Calibration ...................... 24

Slow FIFO .................................................................................... 24

SLOW_FILTER_UPDATE_LVL .............................................. 25

Adaptive Threshold and Sensitivity ............................................. 26

Interrupt Output ............................................................................. 28

CDC Conversion-Complete Interrupt .................................... 28

Sensor-Touch Interrupt ............................................................. 28

INT

GPIO

Outputs ............................................................................................ 32

AC

General-Purpose Input/Output (GPIO) ................................. 32

Using the GPIO to Turn On/Off an LED ................................ 32

Serial Interface ................................................................................ 33

SPI Interface ................................................................................ 33

I2C-Compatible Interface .......................................................... 35

V

DRIVE

PCB Design Guidelines ................................................................. 38

Capacitive Sensor Board Mechanical Specifications ............. 38

Chip Scale Packages ................................................................... 38

Power-Up Sequence ....................................................................... 39

Typical Application Circuits ......................................................... 40

Register Map ................................................................................... 41

Detailed Register Descriptions ..................................................... 42

Bank 1 Registers ......................................................................... 42

Bank 2 Registers ......................................................................... 52

Bank 3 Registers ......................................................................... 57

Outline Dimensions ....................................................................... 69

Ordering Guide .......................................................................... 69

Output Control ....................................................... 30

Output .......................................................................... 32

SHIELD

Input ................................................................................. 37

REVISION HISTORY

8/08—Rev. 0 to Rev. A

Changes to Table 3 ............................................................................ 4

Added Figure 3, Renumbered Sequentially .................................. 6

Changes to Low Power Mode Section ......................................... 13

Added Latency from Touch to Response Section ...................... 13

Added Low Latency from Touch to Response Section .............. 13

Changes to Figure 60 and Figure 61 ............................................. 40

Changes to Figure 62 ...................................................................... 41

Added Exposed Pad Notation to Outline Dimensions ............. 69

Rev. A | Page 2 of 72

9/07—Revision 0: Initial Version

AD7147

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SPECIFICATIONS

VCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CAPACITANCE-TO-DIGITAL CONVERTER

Update Rate 8.73 9 9.27 ms 12 conversion stages, decimation = 64

17.46 18 18.54 ms 12 conversion stages, decimation = 128

34.9 36 37.1 ms 12 conversion stages, decimation = 256
Resolution 16 Bits
CINx Input Range ±8 pF
No Missing Codes 16 Bits

CINx Input Leakage 25 nA
Maximum Output Load 20 pF Capacitance load on CINx to ground
Total Unadjusted Error ±20 %
Output Noise (Peak-to-Peak) 12 Codes Decimation rate = 64
7 Codes Decimation rate = 128
3 Codes Decimation rate = 256
Output Noise (RMS) 1.1 Codes Decimation rate = 64

0.8 Codes Decimation rate = 128

0.5 Codes Decimation rate = 256
C

Offset Range 20 pF

STRAY

C

Offset Resolution 0.32 pF

STRAY

Low Power Mode Delay Accuracy 4 %

AC

SHIELD

Frequency 250 kHz
Output Voltage 0 VCC V Oscillating
Short-Circuit Source Current 10 mA
Short-Circuit Sink Current 10 mA
Maximum Output Load 150 pF Capacitance load on AC

LOGIC INPUTS (SDI, SCLK, CS, SDA, GPIO)

VIH Input High Voltage 0.7 × V

V

DRIVE

VIL Input Low Voltage 0.4 V
IIH Input High Current −1 μA VIN = V
IIL Input Low Current 1 μA VIN = GND
Hysteresis 150 mV

OPEN-DRAIN OUTPUTS (SCLK, SDA, INT)

VOL Output Low Voltage 0.4 V I
IOH Output High Leakage Current ±0.1 ±1 μA V

LOGIC OUTPUTS (SDO, GPIO)

VOL Output Low Voltage 0.4 V I
VOH Output High Voltage V
GPIO, SDO Floating State Leakage

− 0.6 V I

DRIVE

±1 μA

Current

POWER

VCC 2.6 3.3 3.6 V
V

1.65 3.6 V Serial interface operating voltage

DRIVE

ICC 0.9 1 mA In full power mode, VCC + V

15.5 21.5 μA

2.3 7.5 μA Full shutdown, VCC + V

Rev. A | Page 3 of 72

Guaranteed by design, but not production
tested

Percentage of 200 ms, 400 ms, 600 ms,
or 800 ms

to ground

SHIELD

DRIVE

= −1 mA

SINK

= V

OUT

= 1 mA, V

SINK

SOURCE

DRIVE

DRIVE

= 1 mA, V

= 1.65 V to 3.6 V

= 1.65 V to 3.6 V

DRIVE

Pin three-state, leakage measured to
GND and V

Low power mode, converter idle, V

CC

DRIVE

+ V

CC

DRIVE,

decimation = 256

DRIVE

AD7147

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AVERAGE CURRENT SPECIFICATIONS

Table 2. Typical Average Current in Low Power Mode1

Low Power Decimation Current Values of Conversion Stages (A)
Mode Delay Rate 1 2 3 4 5 6 7 8 9 10 11 12

200 ms 64 20.83 24.18 27.52 30.82 34.11 37.37 40.6 43.81 46.99 50.16 53.3 56.41
128 25.3 31.92 38.45 44.87 51.21 57.45 63.6 69.66 75.63 81.52 87.33 93.05
256 34.11 46.99 59.51 71.66 83.47 94.94 106.1 116.96 127.52 137.81 147.82 157.58
400 ms 64 18.17 19.86 21.55 23.23 24.9 26.57 28.23 29.88 31.53 33.17 34.81 36.44
128 20.43 23.79 27.12 30.43 33.72 36.98 40.22 43.43 46.62 49.78 52.93 56.05
256 24.9 31.53 38.06 44.5 50.83 57.08 63.23 69.3 75.28 81.17 86.98 92.71
600 ms 64 17.28 18.41 19.54 20.67 21.79 22.91 24.03 25.14 26.25 27.36 28.47 29.57
128 18.79 21.04 23.28 25.51 27.73 29.94 32.13 34.32 36.49 38.65 40.81 42.95
256 21.79 26.25 30.67 35.04 39.37 43.66 47.9 52.11 56.27 60.39 64.47 68.51
800 ms 64 16.84 17.69 18.53 19.38 20.23 21.07 21.91 22.75 23.59 24.43 25.26 26.09
128 17.97 19.66 21.35 23.03 24.7 26.37 28.03 29.69 31.34 32.98 34.62 36.25
256 20.23 23.59 26.93 30.24 33.53 36.79 40.03 43.24 46.43 49.6 52.74 55.86

1

VCC = 3.3 V, TA = 25°C, load = 50 pF.

1

Table 3. Maximum Average Current in Low Power Mode

Low Power Decimation Current Values of Conversion Stages (A)
Mode Delay Rate 1 2 3 4 5 6 7 8 9 10 11 12

200 ms 64 27.96 32.06 36.12 40.15 44.16 48.12 52.06 55.97 59.85 63.69 67.51 71.29
128 33.41 41.49 49.44 57.26 64.97 72.55 80.02 87.37 94.61 101.74 108.77 115.69
256 44.16 59.85 75.05 89.79 104.09 117.97 131.45 144.53 157.25 169.61 181.63 193.33
400 ms 64 24.74 26.8 28.86 30.91 32.95 34.99 37.01 39.03 41.04 43.04 45.03 47.02
128 27.49 31.59 35.66 39.7 43.71 47.68 51.62 55.53 59.41 63.26 67.08 70.87
256 32.95 41.04 49 56.83 64.54 72.12 79.6 86.96 94.2 101.34 108.37 115.3
600 ms 64 23.66 25.04 26.42 27.79 29.17 30.53 31.89 33.25 34.61 35.96 37.31 38.66
128 25.5 28.25 30.99 33.71 36.41 39.1 41.78 44.44 47.09 49.72 52.34 54.95
256 29.17 34.61 40 45.33 50.6 55.82 60.98 66.09 71.15 76.15 81.1 86.01
800 ms 64 23.12 24.16 25.19 26.23 27.26 28.29 29.32 30.34 31.36 32.38 33.4 34.42
128 24.5 26.57 28.63 30.68 32.72 34.76 36.79 38.8 40.81 42.81 44.81 46.79
256 27.26 31.36 35.44 39.47 43.48 47.46 51.4 55.31 59.19 63.04 66.86 70.66

1

VCC = 3.6 V, TA = −40°C to +85°C, load = 50 pF.

Rev. A | Page 4 of 72

AD7147

K

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SPI TIMING SPECIFICATIONS (AD7147)

TA = −40°C to +85°C, sample tested at 25°C to ensure compliance. V
noted. All input signals are specified with t

= tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.

R

Table 4. SPI Timing Specifications

Parameter Limit Unit Description

f

5 MHz max SCLK frequency

SCLK

t1 5 ns min
t2 20 ns min SCLK high pulse width
t3 20 ns min SCLK low pulse width
t4 15 ns min SDI setup time
t5 15 ns min SDI hold time
t6 20 ns max SDO access time after SCLK falling edge
t7 16 ns max
t8 15 ns min

SPI Timing Diagram

CS

t

1

t

SCL

SDI

2

116

t

4

t

5

MSB LSB

t

3

23

= 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise

DRIVE

falling edge to first SCLK falling edge

CS

rising edge to SDO high impedance

CS
SCLK rising edge to CS

15

high

12

t

8

15

16

t

SDO

6

MSB

Figure 2. SPI Detailed Timing Diagram

LSB

t

7

06663-002

Rev. A | Page 5 of 72

AD7147

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I2C TIMING SPECIFICATIONS (AD7147-1)

TA = −40°C to +85°C, sample tested at 25°C to ensure compliance. V
noted. All input signals timed from a voltage level of 1.6 V.

Table 5. I

2

C Timing Specifications1

Parameter Limit Unit Description

f

400 kHz max

SCLK

t1 0.6 μs min Start condition hold time, t
t2 1.3 μs min Clock low period, t
t3 0.6 μs min Clock high period, t
t4 100 ns min Data setup time, t
t5 300 ns min Data hold time, t
t6 0.6 μs min Stop condition setup time, t
t7 0.6 μs min Start condition setup time, t
t8 1.3 μs min Bus-free time between stop and start conditions, t
tR 300 ns max Clock/data rise time
tF 300 ns max Clock/data fall time

1

Guaranteed by design, not production tested.

I2C Timing Diagram

t

t

2

SCLK

t

1

SDA

t

8

STOP START STOPSTART

R

t

5

t

F

t

3

Figure 3. I

t

4

2

C Detailed Timing Diagram

= 1.65 V to 3.6 V, and VCC = 2.6 V to 3.6 V, unless otherwise

DRIVE

HD; STA

LOW

HIGH

SU; DAT

HD; DAT

SU; STO

SU; STA

BUF

t

1

t

7

t

6

06663-003

TO OUTPUT

PIN

C

50pF

200µA I

L

200µA I

OL

1.6V

OH

06663-004

Figure 4. Load Circuit for Digital Output Timing Specifications

Rev. A | Page 6 of 72

AD7147

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ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

VCC to GND −0.3 V to +3.6 V
Analog Input Voltage to GND −0.3 V to VCC + 0.3 V
Digital Input Voltage to GND −0.3 V to V
Digital Output Voltage to GND −0.3 V to V
Input Current to Any Pin Except Supplies1 10 mA
ESD Rating (Human Body Model) 2.5 kV
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
LFCSP

Power Dissipation 450 mW

θJA Thermal Impedance 135.7°C/W
IR Reflow Peak Temperature 260°C (±0.5°C)
Lead Temperature (Soldering 10 sec) 300°C

1

Transient currents of up to 100 mA do not cause SCR latch-up.

DRIVE

DRIVE

+ 0.3 V
+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 7 of 72

AD7147

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CIN2

CIN3

CIN4

CIN5

CIN1

1CIN6
2CIN7
3CIN8
4CIN9
5CIN10
6CIN11

21

22

23

24

PIN 1
INDICAT OR

AD7147

TOP VIEW

(Not to Scale)

CIN0

20

19

18 GPIO
17 INT
16 CS
15 SCLK
14 SDI
13 SDO

1CIN6
2CIN7
3CIN8
4CIN9
5CIN10
6CIN11

CIN2

CIN3

CIN4

CIN5

21

22

23

24

PIN 1
INDICATO R

AD7147-1

TOP VIEW

(Not to Scale)

CIN1

CIN0

20

19

18 GPIO
17 INT
16 ADD1
15 SCLK
14 ADD0
13 SDA

9

7

8

12

10

11

CC

V

GND

BIAS

CIN12

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED INT ERNALLY. FOR INCREASE D
RELIABILI TY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILIT Y
IT IS RECO MMENDED THAT T HE PAD BE SOLDERED TO THE G ROUND PLANE.

AC

DRIVE

SHIELD

V

06663-005

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED INT ERNALLY. FOR INCREASED
RELIABILI TY OF THE SOLDER JOINTS AND MAXI MUM THERMAL CAPABILITY
IT IS RECO MMENDED THAT T HE PAD BE SOLDERED TO THE G ROUND PLANE.

Figure 5. AD7147 Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

AD7147 AD7147-1 Mnemonic Description

1 1 CIN6 Capacitance Sensor Input.
2 2 CIN7 Capacitance Sensor Input.
3 3 CIN8
4 4 CIN9
5 5 CIN10
6 6 CIN11
7 7 CIN12
8 8 AC

CDC Active Shield Output. Connect to external shield or plane.

SHIELD

9 9 BIAS
10 10 GND
11 11 V
12 12 V

Supply Voltage.

CC

Serial Interface Operating Voltage Supply.

DRIVE

13 N/A SDO
N/A 13 SDA
14 N/A SDI
N/A 14 ADD0
15 15 SCLK
16 N/A

CS
N/A 16 ADD1
17 17

INT

Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.

Bias Node for Internal Circuitry. Requires 10 nF capacitor to ground.
Ground Reference Point for All Circuitry.

SPI Serial Data Output.
I2C Serial Data Input/Output. SDA requires pull-up resistor.
SPI Serial Data Input.
I2C Address Bit 0.
Clock Input for Serial Interface.
SPI Chip Select Signal.

I2C Address Bit 1.

General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor.
18 18 GPIO Programmable GPIO.
19 19 CIN0
20 20 CIN1
21 21 CIN2
22 22 CIN3
23 23 CIN4

Capacitance Sensor Input.

Capacitance Sensor Input.

Capacitance Sensor Input.

Capacitance Sensor Input.

Capacitance Sensor Input.
24 24 CIN5 Capacitance Sensor Input.

9

7

8

12

10

11

CC

V

GND

BIAS

CIN12

AC

DRIVE

SHIELD

V

Figure 6. AD7147-1 Pin Configuration

06663-006

Rev. A | Page 8 of 72

AD7147

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TYPICAL PERFORMANCE CHARACTERISTICS

935

70

915

895

875

(µA)

CC

I

855

835

815

795

DECIMATIO N = 128

2.6 3.7

2.7 2.8 2. 9 3.0 3. 1 3.2 3. 3 3.4 3. 5 3.6

DECIMATIO N = 64

DECIMATIO N = 256

VCC (V)

Figure 7. Supply Current vs. Supply Voltage

180

160

140

120

100

(A)

CC

80

I

60

40

20

0

2.5 3.7

2.7 2.9 3.1 3.3 3.5

200ms

400ms

600ms

800ms

VCC (V)

Figure 8. Low Power Supply Current vs. Supply Voltage,

Decimation Rate = 256

0.12

60

50

40

(A)

CC

I

30

20

10

06663-007

0

2.5 3.72.7 2.9 3.1 3. 3 3.5

200ms

400ms

600ms

800ms

06663-060

VCC (V)

Figure 10. Low Power Supply Current vs. Supply Voltage,

Decimation Rate = 64

2.5

2.0

1.5

(µA)

CC

I

1.0

0.5

06663-061

0

2.7

2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

VCC (V)

06663-010

Figure 11. Shutdown Supply Current vs. Supply Voltage

1150

0.10

0.08

0.06

(mA)

CC

I

0.04

0.02

0

2.5 3.7

2.72.93.13.33.5

Figure 9. Low Power Supply Current vs. Supply Voltage,

200ms

400ms

VCC (V)

Decimation Rate = 128

600ms

800ms

1100

1050

(µA)

CC

I

1000

950

06663-009

900

0

100 200 300 400 500

AC

Figure 12. Supply Current vs. Capacitive Load on AC

Rev. A | Page 9 of 72

CAPACITIVE LOAD (pF)

SHIELD

SHIELD

06663-062

AD7147

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58000

56000

54000

52000

50000

48000

CDC CODE (d)

46000

44000

42000

40000

0

100 200 300 400 500

AC

CAPACITIVE LOAD (pF)

SHIELD

Figure 13. Output Code vs. Capacitive Load on AC

SHIELD

06663-063

160

140

120

100

CDC NOISE p-p (LSB)

25mV 75mV 125mV 175mV
50mV 100mV 150 mV 200mV

80

60

40

20

0

25

50

100

200

400

800

1600

3200

SINE WAVE FREQUENCY (Hz)

6400

12800

25600

51200

102400

Figure 16. Power Supply Sine Wave Rejection, VCC = 3.6 V

204800

409600

819200

06663-064

1640000

960

940

920

900

880

(µA)

CC

860

I

840

820

800

780

–60 –40 –20 0 20 40 60 80 100 120

3.6V

3.3V

2.6V

TEMPERATURE (° C)

Figure 14. Supply Current vs. Temperature

12

10

8

6

(µA)

CC

I

4

2

3.6V

3.3V

2.6V

120

100

CDC NOISE p-p (LSB)

06663-013

25mV 75mV 125mV 175mV
50mV 100mV 150 mV 200mV

80

60

40

20

0

25

50

100

200

400

800

1600

3200

SQUARE WAVE F REQUENCY (Hz)

6400

12800

25600

51200

102400

204800

409600

819200

06663-065

1640000

Figure 17. Power Supply Square Wave Rejection, VCC = 3.6 V

35

30

25

20

15

10

INPUT CAPACIT ANCE (pF)

5

0

–45 135

–25–51535557595115

TEMPERATURE (° C)

Figure 15. Shutdown Supply Current vs. Temperature

06663-014

0

0 10000 20000 30000 40000 50000 60000

CDC OUTPUT CODE

Figure 18. CDC Linearity, VCC = 3.3 V

Rev. A | Page 10 of 72

06663-016

AD7147

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD7147 and AD7147-1 are CDCs with on-chip environ­mental compensation. They are intended for use in portable
systems requiring high resolution user input. The internal
circuitry consists of a 16-bit, ∑-∆ converter that can change a
capacitive input signal into a digital value. There are 13 input
pins, CIN0 to CIN12, on the AD7147 or AD7147-1. A switch
matrix routes the input signals to the CDC. The result of each
capacitance-to-digital conversion is stored in on-chip registers.
The host subsequently reads the results over the serial interface.
The AD7147 has an SPI interface, and the AD7147-1 has an I
interface, ensuring that the parts are compatible with a wide
range of host processors. AD7147 refers to both the AD7147
and AD7147-1, unless otherwise noted, from this point forward
in this data sheet.

The AD7147 interfaces with up to 13 external capacitance
sensors. These sensors can be arranged as buttons, scroll bars,
or wheels, or as a combination of sensor types. The external
sensors consist of an electrode on a single- or multiple-layer
PCB that interfaces directly to the AD7147.

The AD7147 can be set up to implement any set of input
sensors by programming the on-chip registers. The registers
can also be programmed to control features such as averaging,
offsets, and gains for each of the external sensors. There is an
on-chip sequencer that controls how each of the capacitance
inputs is polled.

The AD7147 has on-chip digital logic and 528 words of RAM
that are used for environmental compensation. The effects of
humidity, temperature, and other environmental factors can
affect the operation of capacitance sensors. Transparent to the
user, the AD7147 performs continuous calibration to compen­sate for these effects, allowing the AD7147 to consistently
provide error-free results.

The AD7147 requires a companion algorithm that runs on the
host or another microcontroller to implement high resolution
sensor functions, such as scroll bars or wheels. However, no
companion algorithm is required to implement buttons. Button
sensors are implemented on chip, entirely in digital logic.

The AD7147 can be programmed to operate in either full power
mode or low power automatic wake-up mode. The automatic
wake-up mode is particularly suited for portable devices that

2

C

require low power operation to provide the user with significant
power savings and full functionality.

The AD7147 has an interrupt output,
new data has been placed into the registers.
interrupt the host on sensor activation. The AD7147 operates

from a 2.6 V to 3.6 V supply and is available in a 24-lead, 4 mm ×
4 mm LFCSP.

INT

, to indicate when

INT

is used to

CAPACITANCE SENSING THEORY

The AD7147 measures capacitance changes from single electrode
sensors. The sensor electrode on the PCB comprises one plate
of a virtual capacitor. The other plate of the capacitor is the user’s
finger, which is grounded with respect to the sensor input.

The AD7147 first outputs an excitation signal to charge the
plate of the capacitor. When the user comes close to the sensor,
the virtual capacitor is formed, with the user acting as the second
capacitor plate.

PLASTIC CO VER

SENSOR PCB

-

ADC

MUX

AD7147

Figure 19. Capacitance-Sensing Method

A square wave excitation signal is applied to CINx during
the conversion, and the modulator continuously samples the
charge going through CINx. The output of the modulator is
processed via a digital filter, and the resulting digital data is
stored in the CDC_RESULT_Sx registers for each conversion
stage, at Address 0x00B to Address 0x016.

16-BIT
DATA

EXCITATION
SIGNAL
250kHz

06663-017

Rev. A | Page 11 of 72

AD7147

www.BDTIC.com/ADI

Registering a Sensor Activation

When a user approaches a sensor, the total capacitance associated
with that sensor changes and is measured by the AD7147. If
the change causes a set threshold to be exceeded, the AD7147
interprets this as a sensor activation.

On-chip threshold limits are used to determine when a sensor
activation occurs. Figure 20 shows the change in CDC_RESULT_Sx
when a user activates a sensor. The sensor is deemed to be active
only when the value of CDC_RESULT_Sx is either greater than the
value of STAGEx_HIGH_THRESHOLD or less than the value
of STAGEx_LOW_THRESHOLD.

SENSOR ACTIVE (A)

STAGEx_HIGH_THRESHOLD

CDC_RESULT_Sx

AMBIENT OR
NO-TOUCH VALUE

CDC OUTPUT CO DES

SENSOR ACTIVE (B)

Figure 20. Sensor Activation Thresholds

STAGEx_LOW _THRESHOLD

In Figure 20, two sensor activations are shown. Sensor Active A
occurs when a sensor is connected to the positive input of the
converter. In this case, when a user activates the sensor, there is an
increase in CDC code, and the value of CDC_RESULT_Sx exceeds
that of STAGEx_HIGH_THRESHOLD. Sensor Active B occurs
when the sensor is connected to the negative input of the converter.
In this case, when a user activates the sensor, there is a decrease
in CDC code, and the value of CDC_RESULT_Sx becomes less
than the value of STAGEx_LOW_THRESHOLD.

For each conversion stage, the STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD registers are in Register
Bank 3. The values in these registers are updated automatically
by the AD7147 due to its environmental calibration and
adaptive threshold logic.

At power-up, the values in the STAGEx_HIGH_THRESHOLD
and STAGEx_LOW_THRESHOLD registers are the same as those
in the STAGEx_OFFSET_HIGH and STAGEx_OFFSET_LOW
registers in Bank 2. The user must program the STAGEx_OFFSET
_HIGH and STAGEx_OFFSET_LOW registers on device power­up. See the Environmental Calibration section of the data sheet
for more information.

06663-018

Complete Solution for Capacitance Sensing

Analog Devices, Inc., provides a complete solution for
capacitance sensing. The two main elements to the solution are
the sensor PCB and the AD7147.

If the application requires high resolution sensors such as scroll
bars or wheels, software is required that runs on the host
processor. The memory requirements for the host depend on
the sensor and are typically 10 kB of code and 600 bytes of data
memory, depending on the sensor type.

SENSOR PCB

AD7147

Figure 21. Three-Part Capacitance Sensing Solution

SPI OR I2C

HOST PROCESSOR

1 MIPS

10kB ROM

600 BYTES RAM

06663-019

Analog Devices supplies the sensor PCB footprint design
libraries to the customer and supplies any necessary software on
an open source basis.

BIAS PIN

This pin is connected internally to a bias node of the AD7147.
To ensure correct operation of the AD7147, connect a 10 nF
capacitor between the BIAS pin and ground. The voltage seen at
the BIAS pin is V

/2.

CC

OPERATING MODES

The AD7147 has three operating modes. Full power mode, where
the device is always fully powered, is suited for applications where
power is not a concern (for example, game consoles that have an
ac power supply). Low power mode, where the part automatically
powers down when no sensor is active, is tailored to provide
significant power savings compared with full power mode and
is suited for mobile applications, where power must be
conserved. In shutdown mode, the part shuts down completely.

The POWER_MODE bits (Bit 0 and Bit 1) of the control
register set the operating mode on the AD7147. The control
register is at Address 0x000. Ta ble 8 shows the POWER_MODE
settings for each operating mode. To put the AD7147 into
shutdown mode, set the POWER_MODE bits to either 01 or 11.

Table 8. POWER_MODE Settings

POWER_MODE Bits Operating Mode

00 Full power mode
01 Shutdown mode
10 Low power mode
11 Shutdown mode

The power-on default setting of the POWER_MODE bits is 00,
full power mode.

Rev. A | Page 12 of 72

AD7147

www.BDTIC.com/ADI

Full Power Mode

In full power mode, all sections of the AD7147 remain fully
powered and converting at all times. While a sensor is being
touched, the AD7147 processes the sensor data. If no sensor is
touched, the AD7147 measures the ambient capacitance level
and uses this data for the on-chip compensation routines. In full
power mode, the AD7147 converts at a constant rate. See the
CDC Conversion Sequence Time section for more information.

Low Power Mode

When AD7147 is in low power mode, the POWER_MODE bits
are set to 10 upon device initialization. If the external sensors
are not touched, the AD7147 reduces its conversion frequency,
thereby greatly reducing its power consumption. The part remains
in a reduced power state while the sensors are not touched. The
AD7147 performs a conversion after a delay defined by the
LP_CONV_DELAY bits, and it uses this data to update the
compensation logic and check if the sensors are active. The
LP_CONV_DELAY bits set the delay between conversions to
200 ms, 400 ms, 600 ms, or 800 ms.

In low power mode, the total current consumption of the AD7147
is an average of the current used during a conversion and the
current used while the AD7147 is waiting for the next conversion
to begin. For example, when LP_CONV_DELAY is 400 ms, the
AD7147 typically uses 0.85 mA of current for 36 ms and 14 A
of current for 400 ms during the conversion interval. (Note that
these conversion timings can be altered through the register

AD7147 SETUP

AND INITIAL IZATIO N

POWER_MO DE = 10

settings. See the CDC Conversion Sequence Time section for
more information.)

The time for the AD7147 to transition from a full power state to
a reduced power state after the user stops touching the external
sensors is configurable. The PWR_DOWN_TIMEOUT bits (in
the Ambient Compensation Control 0 (AMB_COMP_CTRL0)
Register at Address 0x002) control the time delay before the
AD7147 transitions to the reduced power state after the user
stops touching the sensors.

Latency from Touch to Response

In low power mode, the AD7147 remains in a low power state
until any one of the external sensors are touched. When a
sensor is touched, the AD7147 begins a conversion sequence
every 36 ms to read back data from the sensors. This means that
the latency between the user touching the sensor, and the AD7147
responding, is a maximum of LP_CONV_DELAY ms.

Low Latency from Touch to Response

In low power mode, the AD7147P model remains in a low power
state until proximity is detected on any one of the external sensors.
When proximity is detected, the AD714P begins a conversion
sequence every 36 ms, or 18 ms, or 9 ms to readback data from the
sensors. The latency between first touch and the AD7147P
responding is much reduced, compared to the AD7147, because
the part is already in a full power state by the time the user has
touched the sensor.

AD7147P SETUP

AND INITIAL IZATIO N

POWER_MODE = 10

CONVERSION S EQUENCE

EVERY LP_CONV_DELAY

UPDATE COMPENSAT ION

LOGIC DAT A PATH

Figure 22. Low Power Mode Operation, AD7147

ANY

NO YES

SENSOR

TOUCHED?

YES

CONVERSION SEQUENCE

EVERY 9/18/ 36ms FOR

SENSOR READBACK

ANY SENSOR

TOUCHED?

NO

PROXIMITY TIMER

COUNTDOWN

TIMEOUT

Rev. A | Page 13 of 72

USER IN

NO YES

PROXIMITY

TO SENSOR?

CONVERSION SEQUENCE

EVERY LP_CONV_DELAY

UPDATE COMPENSAT ION

LOGI C DATA PAT H

06663-020

Figure 23. Low Power Mode Operation, AD7147P

CONVERSION SEQUENCE

EVERY 9/18/ 36ms FOR

SENSOR READBACK

USER IN

YES

PROXIMITY

TO SENSOR?

NO

PROXIMITY TIMER

COUNTDO WN

TIMEOUT

06663-066

AD7147

www.BDTIC.com/ADI

CAPACITIANCE-TO-DIGITAL CONVERTER

The capacitance-to-digital converter on the AD7147 has a Σ-
architecture with 16-bit resolution. There are 13 possible inputs to
the CDC that are connected to the input of the converter through a
switch matrix. The sampling frequency of the CDC is 250 kHz.

OVERSAMPLING THE CDC OUTPUT

The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the power control (PWR_CONTROL) register
(Address 0x000), as listed in Tab le 9 .

from midscale, decrease the POS_AFE_OFFSET or
NEG_AFE_OFFSET value by 1.

The goal is to ensure that the CDC_RESULT_Sx is as close
to midscale as possible. This process is only required once
during the initial capacitance sensor characterization.

+DAC

(20pF RANGE)

6

POS_AFE_OFFSET

Table 9. CDC Decimation Rate

CDC Output Rate

Decimation Bits Decimation Rate

00 256 3.072
01 128 1.536
10 64 0.768
11 64 0.768

Per Stage (ms)

The decimation process on the AD7147 is an averaging process,
where a number of samples are taken and the averaged result is
output. Due to the architecture of the digital filter employed, the
number of samples taken (per stage) is equal to 3× the decimation
rate. So 3 × 256 or 3 × 128 samples are averaged to obtain each
stage result.

The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage; therefore, there is a trade-off
possible between the amount of noise in the signal and the
speed of sampling.

CAPACITANCE SENSOR OFFSET CONTROL

There are two programmable DACs on board the AD7147 to null
the effect of any stray capacitances on the CDC measurement.
These offsets are due to stray capacitance to ground.

A simplified block diagram in Figure 24 shows how to apply the
STAGEx_AFE_OFFSET registers to null the offsets. The 6-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET bits program the
offset DAC to provide 0.32 pF resolution offset adjustment over
a range of 20 pF.

The best practice is to ensure that the CDC output for any stage
is approximately equal to midscale (~32,700) when all sensors
are inactive. To correctly offset the stray capacitance to ground for
each stage, use the following procedure:

1. Read back the CDC value from the CDC_RESULT_Sx register.

2. If this value is not close to midscale, increase the value of

POS_AFE_OFFSET or NEG_AFE_OFFSET (depending
on if the CINx input is connected to the positive or negative
input of the converter) by 1. The CINx connections are
determined by the STAGEx_CONNECTION registers.

3. If the CDC value in CDC_RESULT_Sx is now closer

to midscale, repeat Step 2. If the CDC value is further

POS_AFE_OFFSET_SWAP BIT

CINx

CINx_CONNECTION_SETUP

Figure 24. Analog Front-End Offset Control

+

16-BIT

CDC

_

NEG_AFE_OF FSET_SW AP BIT

–DAC

(20pF RANGE)

6

16

NEG_AFE_OFFSET

06663-021

CONVERSION SEQUENCER

The AD7147 has an on-chip sequencer to implement conversion
control for the input channels. Up to 12 conversion stages can be
performed in one sequence. Each of the 12 conversions stages can
measure the input from a different sensor. By using the Bank 2
registers, each stage can be uniquely configured to support multiple
capacitance sensor interface requirements. For example, a slider
sensor can be assigned to STAGE1 through STAGE8, with a
button sensor assigned to STAGE0. For each conversion stage,
the input mux that connects the CINx inputs to the converter
can have a unique setting.

The AD7147 on-chip sequence controller provides conversion
control, beginning with STAGE0. Figure 25 shows a block diagram
of the CDC conversion stages and CINx inputs. A conversion
sequence is defined as a sequence of CDC conversions starting
at STAGE0 and ending at the stage determined by the value
programmed in the SEQUENCE_STAGE_NUM bits. Depending
on the number and type of capacitance sensors that are used, not all
conversion stages are required. Use the SEQUENCE_STAGE_NUM
bits to set the number of conversions in one sequence. This number
depends on the sensor interface requirements. For example, the
register should be set to 5 if the CINx inputs are mapped to only six
conversion stages. In addition, the STAGE_CAL_EN register
should be set according to the number of stages that are used.

The number of required conversion stages depends solely on
the number of sensors attached to the AD7147. Figure 26 shows
how many conversion stages are required for each sensor and
how many inputs to the AD7147 each sensor requires.

Rev. A | Page 14 of 72

AD7147

www.BDTIC.com/ADI

A button sensor generally requires one sequencer stage; this is
shown in Figure 26 as B1. However, it is possible to configure
two button sensors to operate differentially for one conversion
stage. Only one button can be activated at a time; pressing both
buttons simultaneously results in neither button being activated.
The configuration with two button sensors operating differentially
requires one conversion stage and is shown in Figure 26, with
B2 and B3 representing the differentially configured button sensors.

STAGE4

STAGE3

STAGE2

STAGE1

STAGE0

CIN0

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

CIN7

CIN8

CIN9

CIN10

CIN11

CIN12

SWITCH MA TRIX

Figure 25. CDC Conversion Stages

STAGE7

STAGE6

STAGE5

16-BIT

ADC

A wheel sensor requires eight stages, whereas a slider requires two
stages. The result from each stage is used by the host software to
determine the user’s position on the slider or wheel. The algorithms
that perform this process are available from Analog Devices and are
free of charge, but require signing a software license.

STAGE11

STAGE10

STAGE9

STAGE8

E

C

N

E

-

U

Q

E

S

N

O

I

S

R

E

V

N

O

C

06663-022

SCROLL

WHEEL

AD7147

SEQUENCER

STAGE0

+

CDC

–

STAGE1

+

CDC

–

STAGE2

+

CDC

–

STAGE3

+

CDC

–

STAGE4

+

CDC

–

STAGE5

+

CDC

–

STAGE6

+

CDC

–

STAGE7

+

CDC

–

BUTTONS

B1

B2

B3

SLIDER

AD7147

SEQUENCER

STAGE8

+

CDC

–

STAGE9

+

CDC

–

AD7147

SEQUENCER

STAGE10

+

CDC

–

STAGE11

+

CDC

–

06663-023

Figure 26. Sequencer Setup for Sensors

Rev. A | Page 15 of 72

AD7147

C

www.BDTIC.com/ADI

CDC CONVERSION SEQUENCE TIME

Table 10. CDC Conversion Times for Full Power Mode

Conversion Time (ms)

SEQUENCE_STAGE_NUM Decimation = 64 Decimation = 128 Decimation = 256

0 0.768 1.536 3.072
1 1.536 3.072 6.144
2 2.304 4.608 9.216
3 3.072 6.144 12.288
4 3.84 7.68 15.36
5 4.608 9.216 18.432
6 5.376 10.752 21.504
7 6.144 12.288 24.576
8 6.912 13.824 27.648
9 7.68 15.36 30.72
10 8.448 16.896 33.792
11 9.216 18.432 36.864

The time required for the CDC to complete the measurement of
all 12 stages is defined as the CDC conversion sequence time. The
SEQUENCE_STAGE_NUM and DECIMATION bits determine
the conversion time, as listed in Tab le 1 0.

For example, if the device is operated with a decimation rate
of 128 and the SEQUENCE_STAGE_NUM bit is set to 5 for the
conversion of six stages in a sequence, the conversion sequence
time is 9.216 ms.

Full Power Mode CDC Conversion Sequence Time

The full power mode CDC conversion sequence time for all
12 stages is set by configuring the SEQUENCE_STAGE_NUM
and DECIMATION bits as outlined in Tabl e 10 .

Figure 27 shows a simplified timing diagram of the full power
mode CDC conversion time. The full power mode CDC con­version time (t

CDC

ONVERSION

Figure 27. Full Power Mode CDC Conversion Sequence Time

) is set using the values shown in Tabl e 10 .

CONV_FP

t

CONV_FP

CONVERSION

SEQUENCE N

CONVERSION

SEQUENCE N + 1

CONVERSION

SEQUENCE N + 2

6663-024

Low Power Mode CDC Conversion Sequence Time with Delay

The frequency of each CDC conversion while operating in the
low power automatic wake-up mode is controlled by using the
LP_CONV_DELAY bits located at Address 0x000[3:2] in
addition to the registers listed in Tab le 1 0 . This feature provides
some flexibility for optimizing the tradeoff between the conversion
time needed to meet system requirements and the power
consumption of the AD7147.

For example, maximum power savings is achieved when the
LP_CONV_DELAY bits are set to 11. With a setting of 11,

the AD7147 automatically wakes up, performing a conversion
every 800 ms.

Table 11. LP_CONV_DELAY Settings

LP_CONV_DELAY Bits Delay Between Conversions (ms)

00 200
01 400
10 600
11 800

Figure 28 shows a simplified timing example of the low power
mode CDC conversion time. As shown, the low power mode CDC
conversion time is set by t

t

CONV_FP

CDC

CONVERSION

CONVERSION

SEQUENCE N

Figure 28. Low Power Mode CDC Conversion Sequence Time

and the LP_CONV_DELAY bits.

CONV_FP

t

CONV_LP

LP_CONV_DELAY

CONVERSION

SEQUENCE N + 1

6663-025

CDC CONVERSION RESULTS

Certain high resolution sensors require the host to read back the
CDC conversion results for processing. The registers required
for host processing are located in the Bank 3 registers. The host
processes the data read back from these registers using a software
algorithm in order to determine position information.

In addition to the results registers in the Bank 3 registers, the
AD7147 provides the 16-bit CDC output data directly, starting
at Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.

Rev. A | Page 16 of 72

AD7147

www.BDTIC.com/ADI

CAPACITANCE SENSOR INPUT CONFIGURATION

Each input connection from the external capacitance sensors to
the converter of the AD7147 can be uniquely configured by
using the registers in Bank 2 (see Table 3 8). These registers are
used to configure the input pin connection setups, sensor offsets,
sensor sensitivities, and sensor limits for each stage. Each sensor
can be individually optimized. For example, a button sensor
connected to STAGE0 can have different sensitivity and offset
values than a button with another function that is connected to a
different stage.

CINx INPUT MULTIPLEXER SETUP

Tabl e 34 and Ta bl e 35 list the available options for the
CINx_CONNECTION_SETUP bits when the sensor input
pins are connected to the CDC.

The AD7147 has an on-chip multiplexer that routes the input
signals from each CINx pin to the input of the converter. Each
input pin can be tied to either the negative or positive input of
the CDC, or it can be left floating. Each input can also be
internally connected to the BIAS signal to help prevent cross
coupling. If an input is not used, always connect it to the BIAS.

Connecting a CINx input pin to the positive CDC input results
in an increase in CDC output code when the corresponding
sensor is activated. Connecting a CINx input pin to the negative
CDC input results in a decrease in CDC output code when the
corresponding sensor is activated.

The AD7147 performs a sequence of 12 conversions. The multi­plexer can have different settings for each of the 12 conversions.
For example, CIN0 is connected to the negative CDC input for
conversion STAGE1, left floating for conversion STAGE1, and
so on, for all 12 conversion stages.

For each CINx input for each conversion stage, two bits control
how the input is connected to the converter, as shown in Figure 29.

Examples

To connect CIN3 to the positive CDC input on Stage 0 use the
following setting:

STAGE0_CONNECTION[6:0] = 0xFFBF
STAGE0_CONNECTION[12:7] = 0x2FFF

To connect CIN0 to the positive CDC input and CIN12 to the
negative CIN input on Stage 5 use the following settings:

STAGE5_CONNECTION[6:0] = 0xFFFE
STAGE5_CONNECTION[12:7] = 0x37FF

SINGLE-ENDED CONNECTIONS TO THE CDC

A single-ended connection to the CDC is defined as one CINx
input connected to either the positive or negative CDC input
for one conversion stage. A differential connection to the CDC is
defined as one CINx input connected to the positive CDC input
and a second CINx input connected to the negative input of the
CDC for one conversion stage.

For any stage, if a single-ended connection to the CDC is made
in that stage, the SE_CONNECTION_SETUP bits (Bits[13:12] in
the STAGEx_CONNECTION[12:7] register) should be applied as
follows:

• SE_CONNECTION_SETUP = 00: do not use.

• SE_CONNECTION_SETUP = 01: single-ended connection.

For this stage, there is one CINx connected to the positive
CDC input.

• SE_CONNECTION_SETUP = 10: single-ended connection.

For this stage, there is one CINx connected to the negative
CDC input.

• SE_CONNECTION_SETUP = 11: differential connection.

For this stage, there is one CINx connected to the nega
tive CDC input and one CINx connected to the positive
CDC input.

These bits ensure that during a single-ended connection to the
CDC, the input paths to both CDC terminals are matched,
which in turn improves the power-supply rejection of the
converter measurement.

These bits should be applied in addition to setting the other bits
in the STAGEx_CONNECTION registers, as outlined in the
CINx Input Multiplexer Setup section.

If more than one CINx input is connected to either the positive
or negative input of the converter for the same conversion, set
SE_CONNECTION_SETUP to 11. For example, if CIN0 and
CIN3 are connected to the positive input of the CDC, set
SE_CONNECTION_SETUP to 11.

CIN CONNECTION SETUP BITS CIN SETTING

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8

CIN9
CIN10
CIN11
CIN12

00 CI Nx FLOATING

01

10

11

Figure 29. Input Mux Configuration Options

CINx CONNECTED T O
NEGATIVE CDC INPUT

CINx CONNECTED T O
POSITIVE CDC INPUT

CINx CONNECTED T O
BIAS

Rev. A | Page 17 of 72

+

CDC

–

06663-026

AD7147

www.BDTIC.com/ADI

NONCONTACT PROXIMITY DETECTION

The AD7147 internal signal processing continuously monitors
all capacitance sensors for noncontact proximity detection. This
feature provides the ability to detect when a user is approaching
a sensor, at which time all internal calibration is immediately
disabled while the AD7147 is automatically configured to detect
a valid contact.

The proximity control register bits are described in Ta ble 1 2. The
FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register
bits control the length of the calibration disable period after
the user stops touching the sensor and is not in close proximity
to the sensor during full or low power mode. The calibration is
disabled during this period and then enabled again. Figure 30
and Figure 31 show examples of how these registers are used to set
the calibration disable periods for the full and low power modes.

The calibration disable period in full power mode is the value
of the FP_PROXIMITY_CNT multiplied by 16 multiplied by
the time for one conversion sequence in full power mode. The
calibration disable period in low power mode is the value of the
LP_PROXIMITY_CNT multiplied by 4 multiplied by the time
for one conversion sequence in low power mode.

by the PROXIMITY_RECAL_LVL bits for a set period of time
known as the recalibration timeout. In full power mode, the recali­bration timeout is controlled by FP_PROXIMITY_RECAL; in
low power mode, by LP_PROXMTY_RECAL.

The recalibration timeout in full power mode is the value of
the FP_PROXIMITY_RECAL multiplied by the time for one
conversion sequence in full power mode. The recalibration time­out in low power mode is the value of the LP_PROXIMITY_
RECAL multiplied by the time for one conversion sequence in
low power mode.

Figure 32 and Figure 33 show examples of how the
FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL
register bits control the timeout period before a recalibration
while operating in the full and low power modes. In these
examples, a user approaches a sensor and then leaves, but the
proximity detection remains active. The measured CDC value
exceeds the stored ambient value by the amount set in the
PROXIMITY_RECAL_LVL bits for the entire timeout period.
The sensor is automatically recalibrated at the end of the
timeout period.

RECALIBRATION

In certain situations (for example, when a user hovers over a
sensor for a long time), the proximity flag can be set for a long
period. The environmental calibration on the AD7147 is sus­pended while proximity is detected, but changes may occur
to the ambient capacitance level during the proximity event.
This means that the ambient value stored on the AD7147 no
longer represents the actual ambient value. In this case, even
when the user is not in close proximity to the sensor, the prox­imity flag may still be set. This situation can occur if the user
interaction creates some moisture on the sensor, causing the
new sensor ambient value to be different from the expected
value. In this situation, the AD7147 automatically forces a
recalibration internally. This ensures that the ambient values
are recalibrated, regardless of how long the user hovers over
the sensor. A recalibration ensures maximum AD7147 sensor
performance.

The AD7147 recalibrates automatically when the measured CDC
value exceeds the stored ambient value by an amount determined

PROXIMITY SENSITIVITY

The fast filter in Figure 34 is used to detect when someone is close
to the sensor (proximity). Two conditions, detected by Compa­rator 1 and Comparator 2, set the internal proximity detection
signal: Comparator 1 detects when a user is approaching or
leaving a sensor, and Comparator 2 detects when a user hovers
over a sensor or approaches a sensor very slowly.

The sensitivity of Comparator 1 is controlled by the
PROXIMITY_DETECTION_RATE bits. For example, if
PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1
signal is set when the absolute difference between WORD1 and
WORD3 exceeds (4 × 16) LSB codes.

The PROXIMITY_RECAL_LVL bits (Address 0x003) control
the sensitivity of Comparator 2. For example, if PROXIMITY_
RECAL_LVL is set to 75, the Proximity 2 signal is set when the
absolute difference between the fast filter average value and the
ambient value exceeds (75 × 16) LSB codes.

Rev. A | Page 18 of 72

AD7147

www.BDTIC.com/ADI

Table 12. Proximity Control Registers (See Figure 34)

Length

Bit Name

FP_PROXIMITY_CNT 4 0x002[7:4] Calibration disable time in full power mode.
LP_PROXIMITY_CNT 4 0x002[11:8] Calibration disable time in low power mode.
FP_PROXIMITY_RECAL 8 0x004[9:0] Full power mode proximity recalibration time.
LP_PROXIMITY_RECAL 6 0x004[15:10] Low power mode proximity recalibration time.
PROXIMITY_RECAL_LVL 8 0x003[7:0]

PROXIMITY_DETECTION_RATE 6 0x003[13:8]

CDC CONVERSION

SEQUENCE
(INTERNAL)

PROXIMITY
DETECTIO N
(INTERNAL)

(Bits) Register Address Description

Proximity recalibration level. This value multiplied by 16 controls the
sensitivity of Comparator 2 (see Figure 34).

Proximity detection rate. This value multiplied by 16 controls the
sensitivity of Comparator 1 (see Figure 34).

USER APPROACHES

SENSOR

12345678910111213141516

USER LEAVES

SENSOR AREA

t

CALDIS

17 18 19 20 21 22 23 24

t

CONV_FP

CALIBRATIO N

(INTERNAL)

CALIBRATION ENABLEDCALIBRATION DISABLED

06663-027

Figure 30. Example of Full Power Mode Proximity Detection (FP_PROXIMITY_CNT = 1)

USER LEAVES
SENSOR AREA

t

=

CONV_LP

t

CONV_FP

17 18 19 20 21 22 23 24

t

CALDIS

+ LP_CONV_DELAY.

t

CONV_LP

CALIBRATION ENABLEDCALIBRATION DISABL ED

06663-028

CDC CONVERSION

SEQUENCE

(INTERNAL)

PROXIMITY

DETECTIO N
(INTERNAL)

CALIBRATIO N

(INTERNAL)

USER APPROACHES

SENSOR

12345678910111213141516

NOTES

1. SEQUENCE CO NVERSION T IME

2. PROXIMITY IS SET WHEN USER APPROACHES THE SENS OR, AT WHI CH TIME T HE INTERNAL CAL IBRATION I S DISABLED.

3.

t

= (

t

CALDIS

× LP_PROXI MITY_CNT × 4).

CONV_LP

Figure 31. Example of Low Power Mode Proximity Detection (LP_PROXIMITY_CNT = 4)

Rev. A | Page 19 of 72

AD7147

www.BDTIC.com/ADI

CDC CONVERSION

SEQUENCE

(INTERNAL)

PROXIMITY
DETECTIO N
(INTERNAL)

CALIBRATIO N

(INTERNAL)

RECALIBRATIO N

COUNTER

(INTERNAL)

Figure 32. Example of Full Power Mode Proximity Detection with Forced Recalibration (FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40)

CDC CONVERSION

SEQUENCE

(INTERNAL)

USER APPROACHES

SENSOR

USER LEAVES

SENSOR AREA

CALIBRATION DISABLED

NOTES

1. SEQUENCE CO NVERSION T IME

2.

t

=

t

CALDIS

3.

t

RECAL_TIM EOUT

4.

t

= 2 ×

RECAL

USER APPROACHES

SENSOR

× FP_PROXI MITY_CNT × 16.

CONV_FP

=

t

CONV_FP

t

.

CONV_FP

USER LEAVES

SENSOR AREA

× FP_PROXI MITY_RE CAL.

t

MEASURED CDC VALUE > ST ORED AMBIENT

BY PROXIMITY_RECAL _LVL

16 30 70

t

CALDIS

RECALIBRATIO N TIMEO UT

t

RECAL_TIM EOUT

t

(SEE TABLE 10).

CONV_FP

MEASURED CDC VALUE > ST ORED AMBIENT

BY PROXIMITY_RECAL _LVL

16 30 70

RECAL

t

RECAL

t

CONV_FP

CALIBRATIO N ENABLED

t

CONV_LP

06663-029

PROXIMITY
DETECTIO N
(INTERNAL)

CALIBRATIO N

(INTERNAL)

RECALIBRATIO N

(INTERNAL)

Figure 33. Example of Low Power Mode Proximity Detection with Forced Recalibration (LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40)

CALIBRATION DISABLED

NOTES

1. SEQUENCE CO NVERSION TIME

2.

t

=

t

CALDIS

3.

t

RECAL_TIM EOUT

4.

t

RECAL

= 2 ×

× LP_PROXI MITY_CNT × 4.

CONV_LP

=

t

CONV_LP

t

.

CONV_LP

× LP_PROXI MITY_RE CAL.

t

CONV_LP

t

CALDIS

=

t

+ LP_CONV_DELAY.

CONV_FP

RECALIBRATIO N TIMEO UT

t

RECAL_TIM EOUT

CALIBRATIO N ENABLED

06663-030

Rev. A | Page 20 of 72

AD7147

www.BDTIC.com/ADI

FF_SKIP_CNT

The proximity detection fast FIFO is used by the on-chip logic
to determine if proximity is detected. The fast FIFO expects to
receive samples from the converter at a set rate. FF_SKIP_CNT
is used to normalize the frequency of the samples going into the
FIFO, regardless of how many conversion stages are in a sequence.
In Register 0x002, Bits[3:0] are the fast filter skip control,
FF_SKIP_CNT. This value determines which CDC samples
are not used (skipped) by the proximity detection fast FIFO.

Table 13. FF_SKIP_CNT Settings

FF_SKIP
_CNT

0 0.768 × (SEQUENCE_STAGE_NUM + 1) ms 1.536 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms
1 1.536 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms
2 2.3 × (SEQUENCE_STAGE_NUM + 1) ms 4.608 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms
3 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms
4 3.84 × (SEQUENCE_STAGE_NUM + 1) ms 7.68 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × (SEQUENCE_STAGE_NUM + 1) ms
5 4.6 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms
6 5.376 × (SEQUENCE_STAGE_NUM + 1) ms 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms
7 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms
8 6.912 × (SEQUENCE_STAGE_NUM + 1) ms 13.824 × (SEQUENCE_STAGE_NUM + 1) ms 27.648 × (SEQUENCE_STAGE_NUM + 1) ms
9 7.68 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × (SEQUENCE_STAGE_NUM + 1) ms 30.72 × (SEQUENCE_STAGE_NUM + 1) ms
10 8.448 × (SEQUENCE_STAGE_NUM + 1) ms 16.896 × (SEQUENCE_STAGE_NUM + 1) ms 33.792 × (SEQUENCE_STAGE_NUM + 1) ms
11 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 36.864 × (SEQUENCE_STAGE_NUM + 1) ms
12 9.984 × (SEQUENCE_STAGE_NUM + 1) ms 19.968 × (SEQUENCE_STAGE_NUM + 1) ms 39.936 × (SEQUENCE_STAGE_NUM + 1) ms
13 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 43.008 × (SEQUENCE_STAGE_NUM + 1) ms
14 11.52 × (SEQUENCE_STAGE_NUM + 1) ms 23.04 × (SEQUENCE_STAGE_NUM + 1) ms 46.08 × (SEQUENCE_STAGE_NUM + 1) ms
15 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 49.152 × (SEQUENCE_STAGE_NUM + 1) ms

Decimation = 64 Decimation = 128 Decimation = 256

FAST FIFO Update Rate

Determining the FF_SKIP_CNT value is required only once
during the initial setup of the capacitance sensor interface.
Table 13 shows how FF_SKIP_CNT controls the update rate of
the fast FIFO. The recommended value for the setting when
using all 12 conversion stages on the AD7147 is 0000, or no
samples skipped.

Rev. A | Page 21 of 72

AD7147

www.BDTIC.com/ADI

16

CDC

STAGEx_FF_WORD0

STAGEx_FF_WORD1

STAGEx_FF_WORD2

STAGEx_FF_WORD3

STAGEx_FF_WORD4

STAGEx_FF_WORD5

STAGEx_FF_WORD6

STAGEx_FF_WORD7

BANK 3 REGISTE RS

7

WORD(N)



N = 0

8

PROXIMITY

SLOW_FILTER_EN

COMPARATOR 3

WORD0 – CDC VALUE

SLOW_F ILTER_UP DATE_LVL

REGISTER 0x003

NOTES

1. SLOW _FILT ER_EN, WHI CH IS THE NAME O F THE O UTPUT OF COMPARATO R 3, IS SET AND SW1 IS CL OSED WHEN
EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER PRO VIDING PROXIMITY IS NOT SET.

2. PROXIMITY 1 IS SET WHEN
PROXIMI TY_DETECT ION_RATE REGISTER.

3. PROXIMITY 2 IS SET WHEN|AVERAGE – AMBIENT|EXCEEDS THE VALUE PRO GRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER.

4. DESCRIPTI ON OF COMPARATOR F UNCTIONS:
COMPARATOR 1: USED TO DET ECT WHEN A USER IS APPROACHING OR LEAVI NG A SENSOR.
COMPARATOR 2: USED TO DETECT WHEN A USER I S HOVERING OVER A SENSO R OR APPROACHING A SENSOR VERY SLOWLY.
ALSO USED T O DETECT IF THE SENSOR AMBIENT L EVEL HAS CHANGED AS A RESULT OF THE USER INT ERACTION.
FOR EXAMPL E, HUMIDI TY OR DIRT LEFT BEHI ND ON SENSOR.
COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW_FILTER_EN IS SET AND
PROXIMITY IS NOT SET.

STAGEx_SF_WORD0

STAGEx_SF_WORD1

STAGEx_SF_WORD2

STAGEx_SF_WORD3

STAGEx_SF_WORD4

STAGEx_SF_WORD5

STAGEx_SF_WORD6

STAGEx_SF_WORD7

BANK 3 REGISTERS

|STAGEx_FF_

SW1

WORD0 – STAGEx_FF_WORD3| EXCEEDS THE VALUE PROGRAMMED IN THE

COMPARATOR 1

|WORD0 – WORD3|

PROXIMITY_DETECTION_RATE

REGISTER 0x003

STAGEx_FF_AVG

BANK 3 REGISTERS

PROXIMIT Y_RECAL_LVL

STAGEx_SF _AMBIENT

BANK 3 REGISTERS

PROXIMITY 1 PROXIMITY

PROXIMITY 2

COMPARATOR 2

|AVERAGE – AMBIE NT|

REGISTER 0x003

FP_PROXIMITY_CNT

REGISTER 0x002

PROXIMITY TI MING

FP_PROXI MITY_RECAL

REGISTER 0x004

STAGEx_FF_WORDx

STAGEx_SF_WORDx

CDC OUTPUT CODE

CONTROL L OGIC

|STAGE x_SF_

Figure 34. AD7147 Proximity-Detection Logic

LP_PROXI MITY_CNT

REGIST ER 0x002

LP_PROXIMITY_RECAL

REGISTER 0x004

SENSOR

CONTACT

WORD0 – CDC VALUE

AMBIENT
VALUE

t

|

06663-031

Rev. A | Page 22 of 72