ANALOG DEVICES AD7142, AD7142-1 Service Manual

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Programmable Capacitance-to-Digital

Converter with Environmental

Preliminary Technical Data

FEATURES

Programmable capacitance-to-digital converter

30 Hz update rate (@ maximum sequence length)
Better than one femto Farad resolution
14 capacitance sensor input channels
No external RC tuning components required
Automatic conversion sequencer

On-chip automatic calibration logic

Automatic compensation for environmental changes

Automatic adaptive threshold and sensitivity levels
On-chip RAM to store calibration data
SPI®- or I
Separate V
Interrupt output and GPIO
32-lead, 5 mm x 5 mm LFCSP

2.7 V to 3.3 V supply voltage
Low operating current

APPLICATIONS

Personal music and multimedia players
Cell phones
Digital still cameras
Smart hand-held devices
Television, A/V and remote controls
Gaming consoles

2

C®- (AD7142-1) compatible serial interface

level for serial interface

DRIVE

Full power mode: less than1 mA

Low power mode: 50 μA

C

SHIELD

V

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8

CIN9
CIN10
CIN11
CIN12
CIN13

SRC

SRC

DRIVE

Compensation

AD7142/AD7142-1

FUNCTIONAL BLOCK DIAGRAM

V

V

REF+

REF–

30
31
32

1
2
3
4
5
6
7
8

9
10
11

12

15

16

20

SWITCH

240kHz

EXCITATION

SOURCE

MATRIX

16-BIT

Σ-Δ

CDC

AD7142

CONTROL

AND

DATA

REGISTERS

SERIAL INTERFACE

AND CONTROL LOGIC

22 23 24 25

21

SDO/

SDI/

ADD0

SCLK

SDA

Figure 1.

CALIBRATION

CALIBRATION

CS/

ADD1

ENGINE

RAM

TEST

272829

POWER-ON

RESET
LOGIC

INTERRUPT

AND GPIO

LOGIC

INT

13

14

17

18

19

26

AV

CC

AGND

DV

CC

DGND1

DGND2

GPIO

05702-001

GENERAL DESCRIPTION

The AD7142 and AD7142-1 are integrated capacitance-to­digital converters (CDCs) with on-chip environmental
calibration for use in systems requiring a novel user input
method. The AD7142 and AD7142-1 can interface to external
capacitance sensors implementing functions such as capacitive
buttons, scroll bars, or joypads.

The CDC has 14 inputs, channeled through a switch matrix to a
16-bit, 240 kHz sigma-delta (∑-∆) capacitance-to-digital
converter. The CDC is capable of sensing changes in the
capacitance of the external sensors and uses this information to
register a sensor activation. The external sensors can be
arranged as a series of buttons, as a scroll bar or wheel, or as a
combination of sensor types. By programming the registers, the
user has full control over the CDC setup. High resolution scroll
bar sensors require software to run on the host processor.

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The AD7142 and AD7142-1 have on-chip calibration logic to
account for

changes in the ambient environment. The calibration

sequence is performed automatically and at continuous intervals,
while the sensors are not touched. This ensures that there are no
false or nonregistering touches on the external sensors due to a
changing environment.

The AD7142 has an SPI-compatible serial interface, and the

2

AD7142-1 has an I

C-compatible serial interface. Both versions
of AD7142 have an interrupt output, as well as a general-purpose
input output (GPIO).

The AD7142 and AD7142-1 are available in a 32-lead, 5 mm ×
5 mm LFCSP package and operate from a 2.7 V to 3.3 V supply.
The operating current consumption is less than 1 mA, falling
to 50 µA in low power mode (conversion interval of 400 ms).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD7142/AD7142-1 Preliminary Technical Data

TABLE OF CONTENTS

Features .............................................................................................. 1

Adaptive Threshold and Sensitivity............................................. 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

SPI Timing Specifications AD7142............................................ 4

2

I

C Timing Specifications AD7142-1 ........................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Functional Descriptions......................... 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ........................................................................ 9

Capacitance Sensing Theory ....................................................... 9

Operating Modes........................................................................ 10

Capacitance Sensor Input Configuration.................................... 11

Interrupt Output............................................................................. 21

CDC Conversion Complete Interrupt..................................... 21

Sensor Threshold Interrupt ...................................................... 21

INT

GPIO

Output Control ....................................................... 22

Outputs ............................................................................................ 24

Excitation Source........................................................................ 24

C

Output ............................................................................. 24

SHIELD

GPIO ............................................................................................ 24

Serial Interface................................................................................ 25

SPI Interface ................................................................................ 25

2

I

C Interface ................................................................................ 27

V

Input ................................................................................. 29

DRIVE

PCB Design Guidelines ................................................................. 30

Capacitive Sensor Board Mechanical Specifications............. 30

Chip Scale Packages ................................................................... 30

CIN Input Multiplexer Setup.................................................... 11

Capacitiance-to-Digital Converter............................................... 12

Oversampling the CDC Output ............................................... 12

Capacitance Sensor Offset Control .......................................... 12

Conversion Sequencer ............................................................... 12

CDC Conversion Time.............................................................. 13

CDC Conversion Results........................................................... 14

Non-Contact Proximity Detection............................................... 15

Environmental Calibration ........................................................... 19

REVISION HISTORY

12/05—Preliminary Version D

7/05—Preliminary Version C

2/05—Preliminary Version B

Power-Up Sequence ....................................................................... 31

Typical Applicat i o n C i rc uits ......................................................... 32

Register Map ................................................................................... 33

Detailed Register Descriptions..................................................... 34

Bank 1 Registers ......................................................................... 34

Bank 2 Registers ......................................................................... 44

Bank 3 Registers ......................................................................... 47

Outline Dimensions ....................................................................... 62

Ordering Guide .......................................................................... 62

1/05—Preliminary Version A

Rev. PrD | Page 2 of 64

Preliminary Technical Data AD7142/AD7142-1

SPECIFICATIONS

VCC = 2.7 V to 3.3 V, TA = −40oC to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

CAPACITANCE-TO-DIGITAL CONVERTER

Update Rate 30 Hz Maximum programmed sequence length
Resolution 16 Bit
Range ±2 pF
No Missing Codes 16 Bit

Total Unadjusted Error TBD fF
Power Supply Rejection 500 aF/V
Output Noise (Peak-to-Peak) 10 aF/√Hz
Parasitic Capacitance 60 pF

EXCITATION SOURCE

Frequency TBD 240 TBD kHz
Output Voltage AV

CC

V
Short-Circuit Current 10 mA
Maximum Output Load 500 pF Capacitance load on source to ground
C

Output Drive 10 μA

SHIELD

C

Bias Level AVCC/2 V

SHIELD

LOGIC INPUTS (SDI, SCLK, CS, SDA, GPI, TEST)

V

Input High Voltage 0.7 x V

IH

VIL Input Low Voltage 0.3 x V
I

Input High Voltage −1 μA

IH

V

DRIVE

V

DRIVE

IIL Input Low Voltage 1 μA
Hysteresis 150 mV

OPEN-DRAIN OUTPUTS (SDO, SDA, INT)

VOL Output Low Voltage 0.4 V I
IOH Output High Leakage Current 0.1 1 μA V

LOGIC OUTPUTS

VOL Output Low Voltage 0.4 V I
VOH Output High Voltage V

− 0.6 V I

DRIVE

Floating State Leakage Current ±10 μA Pin tri-stated

POWER

AV
V
I

DRIVE

CC

DV

CC,

CC

2.7 3.6 V

1.65 DVCC + 0.3 V Serial interface operating voltage

1 TBD mA Full power mode
50 TBD μA Low power mode (conversion delay = 400 ms)
2 TBD μA Full shutdown

Guaranteed by design, but not production
tested

Parasitic capacitance to ground, guaranteed
by characterization

= −1 mA

SINK

= V

OUT

DRIVE

= 1 mA, V

SINK

SOURCE

= 1 mA

= 1.6 V to DVCC + 0.3 V

DRIVE

Rev. PrD | Page 3 of 64

AD7142/AD7142-1 Preliminary Technical Data

SPI TIMING SPECIFICATIONS AD7142

TA = −40°C to +105°C; V
compliance. All input signals are specified with t

Table 2. SPI Timing Specifications

Parameter Limit at T

1

f

SCLK

10 kHz min
10 MHz max
t

1

t

2

5 ns min

20 ns min SCLK high pulse width
t3 20 ns min SCLK low pulse width
t4 15 ns min SDI set-up time
t5 15 ns min SDI hold time
t

6

20 ns max SDO access time after SCLK falling edge
t7 16 ns max
t

8

1

Mark/space ratio (duty cycle) for the DCLK input is 40/60 to 60/40.

TBD ns

CS

SCLK

SDI

= 1.8 V to 3.6 V; AVCC, DVCC = 2.7 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure

DRIVE

= tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.

R

MIN

, T

MAX

Unit Description

CS falling edge to first SCLK falling edge

CS rising edge to SDO high impedance
SCLK rising edge to

t

1

t

t

4

MSB

2

1

t

5

t

3

23

15

16

LSB

CS high

12

t

8

15

16

t

SDO

6

MSB

Figure 2. SPI Detailed Timing Diagram

LSB

t

7

05702-002

Rev. PrD | Page 4 of 64

Preliminary Technical Data AD7142/AD7142-1

S

A

I2C TIMING SPECIFICATIONS AD7142-1

TA = −40°C to +105°C; V
Sample tested at 25°C to ensure compliance. All input signals timed from a voltage level of 1.6 V.

2

Table 3. I

C Timing Specifications

Parameter Limit Unit Description

f
t
t
t
t
t
t
t
t

SCLK

1

2

3

4

5

6

7

8

400 kHz max

0.6 μs min Start condition hold time, t

1.3 μs min Clock low period, between 10% points, t

0.6 μs min Clock high period, between 90% points, t
100 ns min Data setup time , t
50 ns min Data hold time, t

0.6 μs min Stop condition setup time, t

0.6 μs min Start condition setup time, t

1.3 μs min Bus free time between stop and start conditions, t
tR 300 ns max Clock/data rise time
tF 300 ns max Clock/data fall time

1

Guaranteed by design, but not production tested.

= 1.8 V to 3.6 V; AVCC, DVCC = 2.7 V to 3.6 V, unless otherwise noted.

DRIVE

1

SU; DAT

HD; DAT

HD; STA

SU; STO

SU; STA

LOW

HIGH

BUF

t

t

2

SCLK

t

1

DAT

t

8

STOP START STOPSTART

R

t

5

t

F

t

3

Figure 3. I

t

4

2

C Detailed Timing Diagram

t

1

t

7

t

6

05702-003

Rev. PrD | Page 5 of 64

AD7142/AD7142-1 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

AVCC to AGND, DVCC to DGND −0.3 V to +3.6 V
Analog Input Voltage to AGND −0.3 V to AVCC + 0.3 V
Digital Input Voltage to DGND −0.3 V to V
Digital Output Voltage to DGND −0.3 V to V
Input Current to Any Pin Except

Supplies

1

10 mA

DRIVE

DRIVE

+ 0.3 V
+ 0.3 V

ESD Rating 2.5 kV
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
LFCSP Package

Power Dissipation 450 mW

θJA Thermal Impedance 135.7°C/W
IR Reflow Peak Temperature 260°C (±0.5°C)
Lead Temperature (Soldering 10 sec) 300°C

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

200μAI

TO OUTPUT

PIN

C

L

50pF

200μAI

Figure 4. Load Circuit for Digital Output Timing Specifications

OL

1.6V

OH

05702-004

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrD | Page 6 of 64

Preliminary Technical Data AD7142/AD7142-1

+

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

T

REF

REF–

V

CIN2
32

TEST

CIN0

V

GPIO

CIN1
31

30

IN

29

28

27

26

25

CIN2
32

REF+

REF–

V

TEST

GPIO

CIN1

CIN0

31

30

INT

V

26

25

29

28

27

1CIN3

PIN 1

2CIN4

INDICATOR

3CIN5
4CIN6

AD7142

5CIN7

TOP VIEW

6CIN8

(Not to Scale)
7CIN9
8CIN10

9

11

13

10

12

3

CC

AV

CIN11

CIN12

CIN1

SHIELD

C

Figure 5. AD7142, 32-Lead LFCSP Pin Configuration

24 CS
23 SCLK
22 SDI
21 SDO
20 V

DRIVE

19 DGND2
18 DGND1
17 DV

CC

15

14

16

SRC

SRC

AGND

05702-005

1CIN3
2CIN4
3CIN5
4CIN6
5CIN7
6CIN8
7CIN9
8CIN10

PIN 1
INDICATOR

AD7142-1

TOP VIEW

(Not to Scale)

9

11

12

10

CIN13

CIN11

CIN12

SHIELD

C

16

15

13

14

CC

SRC

SRC

AV

AGND

Figure 6. AD7142-1, 32-Lead LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Name Description

1 CIN3 Capacitance Sensor Input.
2 CIN4 Capacitance Sensor Input.
3 CIN5 Capacitance Sensor Input.
4 CIN6 Capacitance Sensor Input.
5 CIN7 Capacitance Sensor Input.
6 CIN8 Capacitance Sensor Input.
7 CIN9 Capacitance Sensor Input.
8 CIN10 Capacitance Sensor Input.
9 CIN11 Capacitance Sensor Input.
10 CIN12 Capacitance Sensor Input.
11 CIN13 Capacitance Sensor Input.
12 C
13 AV

SHIELD

CC

CDC Shield Potential Output. Requires 10 nF capacitor to ground. Connect to external shield.

CDC Supply Voltage.
14 AGND Analog Ground Reference Point for All CDC Circuitry. Tie to analog ground plane.
15 SRC CDC Excitation Source Output.
16

SRC

17 DV

CC

Inverted Excitation Source Output.

Digital Core Supply Voltage.
18 DGND1 Digital Ground.
19 DGND2 Digital Ground.
20 V

DRIVE

Serial Interface Operating Voltage Supply.
21 SDO AD7142 SPI Serial Data Output.
SDA AD7142-1 I2C Serial Data Input/Output. SDA requires pull-up resistor.
22 SDI AD7142 SPI Serial Data Input.
ADD0 AD7142-1 I2C Address Bit 0.
23 SCLK Clock Input for Serial Interface.
24

CS

AD7142 SPI Chip Select Signal.
ADD1 AD7142-1 I2C Address Bit 1.

25

INT

General Purpose Interrupt Output. Programmable polarity. Requires pull-up resistor.
26 GPIO Programmable GPIO.
27 TEST Factory Test Pin. Tie to ground.
28 V
29 V

REF+

REF−

CDC Positive Reference Input. Normally tied to analog power.

CDC Negative Reference Input. Tie to analog ground.
30 CIN0 Capacitance Sensor Input.
31 CIN1 Capacitance Sensor Input.
32 CIN2 Capacitance Sensor Input.

24 ADD1
23 SCLK
22 ADD0
21 SDA
20 V

DRIVE

19 DGND2
18 DGND1
17 DV

CC

05702-044

Rev. PrD | Page 7 of 64

AD7142/AD7142-1 Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. Supply Current vs. AV

DD

Rev. PrD | Page 8 of 64

Preliminary Technical Data AD7142/AD7142-1

THEORY OF OPERATION

The AD7142 and AD7142-1 are capacitance-to-digital
converters (CDCs) with on-chip environmental compensation,
intended for use in portable systems requiring high resolution
user input. The internal circuitry consists of a 16-bit, ∑-∆ con­verter that converts a capacitive input signal into a digital value.
There are 14 input pins on the AD7142 and AD7142-1, CIN0 to
CIN13. A switch matrix routes the input signals to the CDC.
The result of each capacitance-to-digital conversion is stored in
on-chip registers. The host subsequently reads the results over
the serial interface. The AD7142 contains an SPI interface and
the AD7142-1 has an I

2

C interface ensuring that the parts are
compatible with a wide range of host processors. Because the
AD7142 and AD7142-1 are identical parts, with the exception of
the serial interface, AD7142 refers to both the AD7142 and
AD7142-1 throughout this data sheet.

The AD7142 interfaces with to up to 14 external capacitance
sensors. These sensors can be arranged as buttons, scroll bars,
joypads, or as a combination of sensor types. The external
sensors consist of electrodes on a 2- or 4-layer PCB that
interfaces directly to the AD7142.

The AD7142 has a general interrupt output,
when new data has been placed into the registers.
to interrupt the host on sensor activation. The AD7142 oper­ates from a 2.7 V to 3.6 V supply, and is available in a 32-lead,
5 mm × 5 mm LFCSP.

CAPACITANCE SENSING THEORY

The AD7142 uses a method of sensing capacitance known as
the shunt method. Using this method, an excitation source is
connected to a transmitter generating an electric field to a
receiver. The field lines measured at the receiver are translated
into the digital domain by a ∑-∆ converter. When a finger, or
other grounded object, interferes with the electric field, some of
the field lines are shunted to ground and do not reach the
receiver (see
measured at the receiver decreases when an object comes close
to the induced field.

Figure 8). Therefore, the total capacitance

INT

, to indicate

INT

is used

The AD7142 can be set up to implement any set of input
sensors by programming the on-chip registers. The registers
can also be programmed to control features such as averaging,
offsets, and gains for each of the external sensors. There is a
sequencer on-chip to control how each of the capacitance
inputs is polled.

The AD7142 has on-chip digital logic and 528 words of RAM
that are used for environmental compensation. The effects of
humidity, temperature, and other environmental factors can
effect the operation of capacitance sensors. Transparent to the
user, the AD7142 performs continuous calibration to
compensate for these effects, allowing the AD7142 to give
error-free results at all times.

The AD7142 requires some minor companion software that
runs on the host or other microcontroller to implement sensor
functions such as a scroll bar or joypad. However, no companion
software is required to implement buttons, including 8-way
button functionality. The algorithms required for button
sensors are implemented in digital logic on-chip.

The AD7142 can be programmed to operate in either always
powered mode, or in an automatic wake-up mode. The auto
wake-up mode is particularly suited for portable devices that
require low power operation giving the user significant power
savings coupled with full functionality.

RX

16-BIT

DATA

Σ-Δ

ADC

Figure 8. Sensing Capacitance Method

TX

EXCITATION
SIGNAL
240KHz

05702-007

In practice, the excitation source and ∑-∆ ADC are implemented
on the AD7142, while the transmitter and receiver are constructed
on a PCB that makes up the external sensor.

Registering a Sensor Activation

When a sensor is approached, the total capacitance associated
with that sensor, measured by the AD7142, changes. When the
capacitance changes to such an extent that a set threshold is
exceeded, the AD7142 registers this as a sensor touch.

For example, consider the case of two button sensors that are
connected to the AD7142 in a differential manner. When one
button is activated, the AD7142 registers an increase in capacitance;
if the other button is activated, the AD7142 registers a decrease
in capacitance. If neither of the buttons are activated, the AD7142
measures the background or ambient capacitance level.

Rev. PrD | Page 9 of 64

AD7142/AD7142-1 Preliminary Technical Data

Preprogrammed threshold levels are used to determine if a
change in capacitance is due to a button being activated. If the
capacitance exceeds one of the threshold limits, the AD7142
registers this as a true button activation.

The same thresholds principle is used to determine if other
types of sensors, such as sliders or joypads, are activated.

Complete Solution for Capacitance Sensing

Analog Devices provides a complete solution for capacitance
sensing. The two main elements to the solution are the sensor
PCB and the AD7142.

If the application requires sensors in the shape of a slider or
joypad, software is required that runs on the host processor.
(No software is required for button sensors.) The software
typically requires 3 kB of code and 500 bytes of data memory
for a slider sensor.

SENSOR PCB

AD7142

Figure 9. 3-Part Capacitance Sensing Solution

SPI or I2C

HOST PROCESSOR

1 MIPS

3kB ROM

500BYTES RAM

Analog Devices supplies the sensor PCB design to the customer
based on the customer’s specifications, and supplies any necessary
software on an open-source basis. Standard sensor designs are
also available as PCB library components.

OPERATING MODES

The AD7142 has three operating modes. Full power mode,
where the device is always fully powered, is suited for applications
where power is not a concern, for example game consoles that
have an ac power supply. Low power mode, where the part
automatically powers down, is tailored to give significant power
savings over full power mode, and is suited for mobile applications
where power must be conserved. The AD7142 also has a com­plete shutdown mode.

The POWER_MODE bits (Bit 0 and Bit 1) of the control
register set the operating mode on the AD7142. The control
register is at Address 0x000.

Table 6. POWER_MODE Settings

POWER_MODE Bits Operating Mode

00 Full power mode
01 Full shutdown mode
10 Low power mode
11 Full shutdown mode

Tabl e 6 shows the POWER_MODE settings for each operating
mode. To put the AD7142 into shutdown mode, set the
POWER_MODE bits to either 01 or 11.

05702-008

The power-on default setting of the POWER_MODE bits is 00,
full power mode.

Full Power Mode

In full power mode, all sections of the AD7142 remain fully
powered at all times. While a sensor is being touched, the
AD7142 processes the sensor data. If no sensor is touched, the
AD7142 measures the ambient capacitance level and uses this
data for the on-chip compensation routines. In full power
mode, the AD7142 converts at a constant rate. See the
Conversion Time

section for more information.

CDC

Low Power Mode

When in low power mode, the AD7142 POWER_MODE bits
are set to 10 upon device initialization. If the external sensors
are not touched, the AD7142 reduces its conversion frequency,
thereby greatly reducing its power consumption. The part
remains in a low power state while the sensors are not touched.
Every 400 ms, the AD7142 performs a conversion and uses this
data to update the compensation logic. When an external
sensor is touched, the AD7142 begins a conversion sequence
every 40 ms to read back data from the sensors. In low power
mode, the total current consumption of the AD7142 is an
average of the current used during a conversion, and the
current used while the AD7142 is waiting for the next
conversion to begin. For example, when the low power mode
conversion interval is 400 ms, the AD7142 uses typically 0.9 mA
current for 40 ms, and 15 A for 360 ms of the conversion
interval. (Note that these conversion timings can be altered
through the register settings. See the

CDC Conversion Time

section for more information.)

AD7142 SETUP

AND INITIALIZATION

POWER_MODE = 10

ANY

NO

SENSOR

TOUCHED?

YES

CONVERSIONS EVERY 400ms

UPDATE COMPENSATION

LOGIC DATA PATH

ANY

SENSOR

NO

TOUCHED?

YES

Figure 10. Low Power Mode Operation

SEQUENCER-CONTROLLED

CONVERSIONS ON ALL SENSORS

EVERY 40ms

ANY

SENSOR

YES

TOUCHED?

NO

TIMEOUT

PROXIMITY

TIMER

COUNT DOWN

05702-009

Rev. PrD | Page 10 of 64

Preliminary Technical Data AD7142/AD7142-1

CAPACITANCE SENSOR INPUT CONFIGURATION

Each stage of the AD7142 capacitance sensors can be uniquely
configured by using the registers in

Tabl e 53 and Tabl e 54 . These
registers are used to configure input pin connection set ups,
sensor offsets, sensor sensitivities, and sensor limits for each
stage. Apply this feature to optimize the function of each sensor
to the application. For example, a button sensor connected to
STAGE0 may require a different sensitivity and offset values
than a button with a different function that is connected to a
different stage.

CIN INPUT MULTIPLEXER SETUP

The CIN_CONNECTION_SETUP registers in Tab l e 5 3 list the
different options that are provided for connecting the sensor
input pin to the CDC converter.

The AD7142 has an on-chip multiplexer to route the input
signals from each pin to the input of the converter. Each input
pin can be tied to either the negative or the positive input of the
CDC, or it can be left floating. Each input can also be internally
connected to the C
an input is not used, always connect it to C

signal to help prevent cross coupling. If

SHIELD

SHIELD.

For each input pin, CIN0 to CIN13, the multiplexer settings can
be set on a per sequencer stage basis. For example, CIN0 is
connected to the negative CDC input for conversion STAGE1,
left floating for sequencer STAGE1, and so on for all twelve
conversion stages.

Two bits in each register control the mux setting for the input pin.

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9

CIN10

CIN11
CIN12
CIN13

CIN_CONNECTION
_SETUP BITS

00
01 CINX CONNECTED TO

10

11

Figure 11. Input Mux Configuration Options

CIN SETTING

CINX FLOATING

NEGATIVE CDC INPUT
CINX CONNECTED TO

POSITIVE CDC INPUT
CINX CONNECTED TO

C

SHIELD

+

–

CDC

05702-010

Rev. PrD | Page 11 of 64

AD7142/AD7142-1 Preliminary Technical Data

CAPACITIANCE-TO-DIGITAL CONVERTER

The capacitance-to-digital converter on the AD7142 has a
sigma-delta (Σ-) architecture with 16-bit resolution. There are
14 possible inputs to the CDC that are connected to the input of
the converter through a switch matrix. The sampling frequency
of the CDC is 240 kHz.

OVERSAMPLING THE CDC OUTPUT

It is possible to sample the result of any CDC conversion at a
rate less than 240 kHz. The decimation rate, or over–sampling
ratio, is determined by Bits[9:8] of the control register, as listed
in

Tabl e 7.

Table 7. CDC Decimation Rate

Decimation Bit Value Decimation Rate CDC Sample Rate

00 256 312.5 Hz
01 128 625 Hz
10 64 1.25 kHz
11 64 1.25 kHz

The decimation process on the AD7142 is an averaging process
where a number of samples are taken and the averaged result is
output. The amount of samples taken is set equal to the
decimation rate, so 256, 128, or 64 samples are averaged to
obtain the CDC output.

The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the sampling frequency, thus, a tradeoff is required
between a noise-free signal and speed of sampling.

CAPACITANCE SENSOR OFFSET CONTROL

Apply the STAGE_OFFSET registers to null any capacitance
sensor offsets associated with printed circuit board parasitic
capacitance, or capacitance due to any other source, such as
connectors. This is only required once during the initial
capacitance sensor characterization.

A simplified block diagram in
STAGE_OFFSET registers to null the offsets. The 7-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET registers provide

0.16 pF resolution offset adjustment over a range of 20 pF. Apply
the positive and negative offsets to either the positive or the
negative CDC input using the NEG_AFE_OFFSET and
POS_AFE_OFFSET registers.

Figure 12 shows how to apply the

CONVERSION SEQUENCER

The AD7142 has an on-chip sequencer to implement
conversion control for the input channels. Up to 12 conversion
stages can be performed in sequence. By using the Bank 2
registers, each stage can be uniquely configured to support
multiple capacitance sensor interface requirements. For
example, a slider sensor can be assigned to STAGE1 with a
button sensor assigned to STAGE2.

The AD7142 on-chip sequencer controller provides conversion
control beginning with STAGE0.
of the CDC conversion stages and CIN inputs. A conversion
sequence is defined as a sequence of CDC conversion starting at
STAGE0 and ending at the stage determined by the value pro­grammed in the SEQUENCE_STAGE_NUM register. In
the conversion sequence is from STAGE0 through STAGE5.
Depending on the number and type of capacitance sensors that are
used, not all conversion stages are required. Use the
SEQUENCE_STAGE_NUM register to set the number of
conversions in one sequence, depending on the sensor interface
requirements. For example, this register would be set to 5 if the
CIN inputs were mapped to only six stages as shown in
In addition, set the STAGE_CAL_EN registers according to the
number of stages that are used.

SENSOR

+DAC

(20pF RANGE)

CIN

EXT

CIN_CONNECTION_SETUP

REGISTER

Figure 12. Analog Front End Offset Control

–DAC

(20pF RANGE)

Figure 13 shows a block diagram

7

POS_AFE_OFFSET

REGISTER

POS_AFE_OFFSET_SWAP

REGISTER

+

16-BIT

CDC

_

NEG_AFE_OFFSET_SWAP

16

REGISTER

7

NEG_AFE_OFFSET

REGISTER

Figure 14,

Figure 14.

05702-011

Rev. PrD | Page 12 of 64

Preliminary Technical Data AD7142/AD7142-1

C

C

C

C

C

C

C

C

STAGE 11

STAGE 10

STAGE 9

STAGE 8

STAGE 7

STAGE 6

STAGE 5

STAGE 4

STAGE 3

STAGE 2

STAGE 1

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9

IN10
IN11
IN12

IN13

STAGE 0

Σ-Δ

16-BIT

ADC

SWITCH MATRIX

CON

E

ENC

U

EQ

S

N

O

ERSI

V

05702-012

Figure 13. AD7142 CDC Conversion Stages

STAGE 11

STAGE 10

STAGE 9

STAGE 8

STAGE 7

STAGE 6

STAGE 5

STAGE 4

STAGE 3

STAGE 2

STAGE 1

CIN0
CIN1

CIN2
CIN3

CIN4
CIN5
CIN6

CIN7
CIN8

CIN9

IN10
IN11
IN12

IN13

NOTES

1. SEQUENCE_STAGE_NUM = 5.

2. FF_SKIP_CNT = 3 (VALUE SELECTED FROM TABLE 8
FOR DECIMATION = 128).

STAGE 0

Σ-Δ

16-BIT

ADC

SWITCH MATRIX

FF_SKIP_CNT

SEQUENCE_CONV_NUM

Figure 14. Example Using SEQUENCE_CON_NUM and

FF_SKIP_CNT Registers

The number of required conversion stages depends wholly on
the number of sensors attached to the AD7142.

Figure 15 shows
how many conversion stages are required for each sensor, and
how many inputs to the AD7142 each sensor requires.

05702-013

BUTTONS

SLIDER

8-WAY SWITCH

Figure 15. Sequencer Setup for Sensors

A button sensor generally requires one sequencer stage;
however, it is possible to configure two button sensors to
operate differentially. Only one button from the pair can be
activated at a time; pressing both buttons together results in
neither button being activated. This configuration requires one
conversion stage.

A slider sensor requires two stages: one stage for sensor
activation; the other stage for measuring positional data from
the slider. In

Figure 15, the slider activation uses STAGE2, while

the positional data uses STAGE3.

The 8-way switch is made from two pairs of differential buttons.
It, therefore, requires two conversion stages, one for each of the
differential button pairs. The buttons are orientated so that one
pair makes up the top and bottom portions of the 8-way switch;
the other pair makes up the left and right portions of the 8-way
switch.

CDC CONVERSION TIME

The time required for one complete measurement by the CDC
is defined as the CDC conversion time. For optimal system per­formance, configure the AD7142 CDC conversion time within a
range of 35 ms to 40 ms. The SEQUENCE_STAGE_NUM,
FF_SKIP_CNT, and DECIMATION registers determine the
conversion time as listed in

AD7142 SEQUENCER

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

CIN7
CIN8

Tabl e 8.

STAGE 0
+

CDC

–

STAGE 1

+

CDC

–

STAGE 2

+

CDC

–

STAGE 3

+

CDC

–

STAGE 4

+

CDC

–

STAGE 5

+

CDC

–

05702-014

Rev. PrD | Page 13 of 64

AD7142/AD7142-1 Preliminary Technical Data

C

C

Table 8. CDC Conversion Times for Full Power Mode

DECIMATION = 64 DECIMATION = 128 DECIMATION = 256

SEQUENCE_STAGE_NUM

FF_SKIP_CNT

Time (ms)

FF_SKIP_CNT

0 11 9.2 11 18.4 11 36.5
1 11 18.4 11 36.8 5 36.5
2 11 27.6 7 36.8 3 36.5
3 11 36.8 5 36.8 2 36.5
4 9 38.4 4 38.4 2 46.0
5 7 36.8 3 36.8 1 36.8
6 6 37.6 2 32.2 1 43.0
7 5 36.8 2 36.8 1 49.1
8 4 34.5 2 41.4 0 27.6
9 4 38.4 1 30.7 0 30.7
10 3 33.8 1 33.8 0 33.7
11 3 36.8 1 36.8 0 36.8

CDC Conversion

For example, while operating with a decimation rate of 128,
if the SEQUENCE_STAGE_NUM register is set to 5 for the
conversion of six stages in a sequence, the FF_SKIP_CNT
register should be set to 3 resulting in a conversion time of

36.8 ms. This example is shown in

Figure 14.

Determining the FF_SKIP_CNT value is only required one time
during the initial setup of the capacitance sensor interface. This
value determines which CDC samples are not used (skipped) in
the proximity detection fast FIFO.

Full Power Mode CDC Conversion Time

The full power mode CDC conversion time is set by

LP_CONV_DELAY is set to 3. With a setting of 3, the AD7142
automatically wakes up, performing a conversion every 400 ms.

Table 9. LP_CONV_DELAY Settings

LP_CONV_DELAY BITS Delay Between Conversions

00 100 ms
01 200 ms
10 300 ms
11 400 ms

Figure 17 shows a simplified timing example of the low power
CDC conversion time. As shown, the low power CDC
conversion time is set by t
register.

configuring the SEQUENCE_STAGE_NUM, FF_SKIP_CNT
and DECIMATION registers as outlined in

Tabl e 8.

CDC Conversion
Time (ms)

t

CONV_LP

FF_SKIP_CNT

and the LP_CONV_DELAY

CONV_FP

CDC Conversion
Time (ms)

Figure 16 shows a simplified timing diagram of the full power
CDC conversion time. The full power mode CDC conversion
time t

ONVERSION

is set using Tabl e 8.

CONV_FP

t

CONV_FP

CDC

CONVERSIONNCONVERSION

NOTES

1.

t

= VALUE SET FROM TABLE 8.

CONV_FP

Figure 16. Full Power Mode CDC Conversion Time

N + 1

CONVERSION

N + 2

05702-015

Low Power Mode CDC Conversion Time with Delay

The frequency of each CDC conversion while operating in the
low power automatic wake up mode is controlled by using the
LP_CONV_DELAY register bits (Bits[3:2] in Register 0x00), in
addition to the registers listed in

Tabl e 8. This feature provides
some flexibility for optimizing the conversion time to meet
system requirements vs. AD7142 power consumption. For
example, maximum power savings is achieved when the

Rev. PrD | Page 14 of 64

CDC

ONVERSION

Figure 17. Low Power Mode CDC Conversion Time CDC Conversion Results

CONVERSION N CONVERSION N + 1

NOTES

t

1.

CONV_LP

=t

+ LP_CONV_DELAY

CONV_FP

05702-016

CDC CONVERSION RESULTS

Certain applications, such as a slider function, require reading
back the CDC conversion results for host processing. The
registers required for host processing are located in Register
Bank 3. The host processes the data read back from these
registers to determine relative position information.

In addition to the results registers in Bank 3, the AD7142
provides the 16-bit CDC output data directly starting at
Address 0x00B of Register Bank 1. Reading back the CDC
16-bit conversion data register allows for customer specific
application data processing.

Preliminary Technical Data AD7142/AD7142-1

NON-CONTACT PROXIMITY DETECTION

The AD7142 internal signal processing continuously monitors
all capacitance sensors for non-contact proximity detection.
This feature provides the ability to detect when a user is
approaching a sensor, at which time all internal calibration is
immediately disabled while the AD7142 is automatically
configured to detect a valid contact.

The proximity control register bits are described in

Tabl e 10 .
The FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register
bits control how long the calibration disable period is after
proximity is detected. The calibration is disabled during this
time and enabled again at the end of this period provided that
the user is no longer approaching, or in contact with, the sensor.
Figure 18 and Figure 19 show examples of how these registers
are used to set the full and low power mode calibration disable
periods.

Recalibration

In the event of a very long proximity detection event, such as a
user hovering over a sensor for a long period of time, the
FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL bits
in register 0x004 can be applied to force a recalibration. This
feature ensures that the ambient values are recalibrated
regardless of how long the user may be hovering over a sensor.
A recalibration ensures maximum AD7142 sensor performance.
Figure 20 and Figure 21 show examples of using the
FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL

register bits to force a recalibration while operating in the full
and low power modes. These figures show a user approaching a
sensor followed by the user leaving the sensor while the
proximity detection remained active after the user left the
sensor. This situation could occur if the user interaction created
some moisture on the sensor for example thus causing the new
sensor value to be different from the expected value. In this
case, the internal recalibration would be applied to
automatically recalibrate the sensor. The force calibration event
takes two interrupt cycles: nothing should be read from or
written to the AD7142 during the recalibration period.

Proximity Sensitivity

There are two conditions that set the internal proximity
detection signal as described in

Figure 22 with Comparator 1
and Comparator 2. Comparator 1 detects when a user is
approaching a sensor. The sensitivity of Comparator 1 is
controlled by PROXIMITY_DETECTION_RATE. For example,
if PROXIMITY_DETECTION_RATE is set to 4, the Proximity
1 signal is set when the absolute difference between WORD1
and WORD3 exceed four LSB codes. Comparator 2 detects
when a user is hovering over a sensor or approaches a sensor
very slowly. The sensitivity of Comparator 2 is controlled by the
PROXIMITY_RECAL_LVL in

Register 0x003. For example, if
PROXIMITY_RECAL_LVL is set to 75, the Proximity 2 signal
is set when the absolute difference between the fast filter
average value and the ambient value exceeds 75 LSB codes.

Table 10. Proximity Control Registers (Refer to

Figure 22)

Length

Register

(Bits)

Register Address Description

FP_PROXIMITY_CNT 4 0x002 Full power mode proximity control
LP_PROXIMITY_CNT 4 0x002 Low power mode proximity control
FP_PROXIMITY_RECAL 8 0x004 Full power mode proximity recalibration control
LP_PROXIMITY_RECAL 6 0x004 Low power mode proximity recalibration control
PROXIMITY_RECAL_LVL 8 0x003 Proximity recalibration level
PROXIMITY_DETECTION_RATE 6 0x003 Proximity detection rate

CDC CONVERSIONS

(INTERNAL)

PROXIMITY DETECTION

(INTERNAL)

CALIBRATION

(INTERNAL)

USER APPROCHES
SENSOR HERE

12345678910111213141516

Figure 18. Full Power Mode Proximity Detection Example with FP_PROXIMITY = 1

USER LEAVES SENSOR

AREA HERE

t

CALDIS

CALIBRATION DISABLED

CALIBRATION ENABLED

t

CONV_FP

05702-017

Rev. PrD | Page 15 of 64

AD7142/AD7142-1 Preliminary Technical Data

CDC CONVERSIONS

(INTERNAL)

USER APPROCHES
SENSOR HERE

12345678910111213141516

USER LEAVES SENSOR

AREA HERE

t

CALDIS

t

CONV_FP

PROXIMITY DETECTION

CALIBRATION

CDC CONVERSIONS

(INTERNAL)

PROXIMITY DETECTION

(INTERNAL)

CALIBRATION

(INTERNAL)

(INTERNAL)

(INTERNAL)

USER A PPROCHES

CALIBRATION DISABLED

NOTES

1. CONVERSION TIME

2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED.

3.

t

= (

CALDIS

t

= (

t

CONV_LP

t

× LP_PROXIMITY_CNT × 4) + LP_CONV_DELAY.

CONV_LP

+ LP_CONV_DELAY).

CONV_FP

CALIBRATION ENABLED

Figure 19. Low Power Mode Proximity Detection with LP_PROXIMITY = 4 and LP_CONV_DELAY = 0

SENSOR HERE

USER IN CONTACT WITH SENSOR

t

DISCAL

USER LEAVES SENSOR

AREA HERE

CDC CONVERSION VALUES EXCEED
PROXIMITY_RECALIBRATION _LVL

16 30 70

RECALIBRATION PERIOD

CALIBRATION ENABLEDCALIBRATION DISABLED

05702-018

t

CONV_FP

t

RECALIBRATION

(INTERNAL)

NOTES

1. CONVERSION TIME

2.

t

t

DISCAL

=

= (

CONV_FP

t

CONV_FP

3.

t

RECAL

t

DETERMINED FROM TABLE 8

CONV_FP

× FP_PROXIMITY_CNT)

× FP_PROXIMITY_RECAL)

RECAL

Figure 20. Full Power Mode Proximity Detection with Forced Recalibration Example with FP_PROXIMITY = 1 and FP_PROXIMITY_RECAL = 40

Rev. PrD | Page 16 of 64

05702-019

Preliminary Technical Data AD7142/AD7142-1

CDC CONVERSIONS

(INTERNAL)

PROXIMITY DETECTION

(INTERNAL)

CALIBRATION

(INTERNAL)

RECALIBRATION

(INTERNAL)

Figure 21. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMITY = 4 and LP_PROXIMITY_RECAL = 10

USER APPROCHES

SENSOR HERE

NOTES

CONVERSION TIME

1.

2.

t

=

t

DISCAL
RECAL

= (

CONV_LP

t

CONV_LP

3.

t

USER LEAVES SENSOR

USER IN CONTACT WITH SENSOR

16 30 70

t

DISCAL

t

=

t

CONV_LP

× (16 × LP_PROXIMITY_CNT)
× LP_PROXIMITY_RECAL × 4)

+ LP_CONV_DELAY.

CONV_HP

AREA HERE

CDC CONVERSION VALUES EXCEED
PROXIMITY_RECALIBRATION _LVL

RECALIBRATION PERIOD

t

RECAL

t

CONV_FP

CALIBRATION ENABLEDCALIBRATION DISABLED

05702-020

Rev. PrD | Page 17 of 64

AD7142/AD7142-1 Preliminary Technical Data

STAGE_MAX_WORD0

Σ-Δ

16

16-BIT

CDC

SLOW_FILTER_UPDATE_LVL

REGISTER 0x003

COMPARATOR 3

WORD 0 – WORD 3

PROXIMITY

SLOW FILTER EN

SW1

STAGE_SF_WORD0
STAGE_SF_WORD1
STAGE_SF_WORD2
STAGE_SF_WORD3
STAGE_SF_WORD4
STAGE_SF_WORD5
STAGE_SF_WORD6
STAGE_SF_WORD7

BANK 3 REGISTERS

SW

STAGE_FF_WORD0
STAGE_FF_WORD1
STAGE_FF_WORD2
STAGE_FF_WORD3
STAGE_FF_WORD4
STAGE_FF_WORD5
STAGE_FF_WORD6
STAGE_FF_WORD7

7

WORD(N)

Σ

N = 0

8

STAGE_FF_AVG

BANK 3 REGISTERS

STAGE_SF_AMBIENT

BANK 3 REGISTERS

CONTROL
LOGIC

PROXIMITY_DETECTION_RATE

BANK 3 REGISTERS

MAX LEVEL
DETECTION

LOGIC

MIN LEVEL

DETECTION

LOGIC

COMPARATOR 1

WORD 0 – WORD 3

REGISTER 0x003

COMPARATOR 2

AVERAGE – AMBIENT

PROXIMITY_RECAL_LVL

REGISTER 0x003

STAGE_MAX_WORD1
STAGE_MAX_WORD2
STAGE_MAX_WORD3

STAGE_MAX_AVG

BANK 3 REGISTERS

STAGE_MAX_TEMP

BANK 3 REGISTERS

STAGE_HIGH_THRESHOLD

BANK 3 REGISTERS

STAGE_MIN_WORD0
STAGE_MIN_WORD1
STAGE_MIN_WORD2
STAGE_MIN_WORD3

STAGE_MIN_AVG

BANK 3 REGISTER3

STAGE_MIN_TEMP

BANK 3 REGISTERS

STAGE_LOW_THRESHOLD

BANK 3 REGISTERS

PROXIMITY 1

PROXIMITY 2

BANK 3 REGISTERS

BANK 3 REGISTERS

FP_PROXIMITY_CNT

REGISTER 0x004

PROXIMITY

FP_PROXIMITY_RECAL

REGISTER 0x004

STAGE_FF_WORDX

STAGE_SF_WORDX

CDC OUTPUT CODE

LP_PROXIMITY_CNT

REGISTER 0X004

PROXIMITY TIMING

CONTROL LOGIC

LP_PROXIMITY_RECAL

SENSOR

CONTACT

REGISTER 0X004

AMBIENT VALUE

TIME

NOTES

1. SLOW FILTER EN IS SET AND SW1 IS CLOSED WHEN /WORD 0–WORD 3/ EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE REGISTER PROVIDING
PROXIMITY IS NOT SET.

2. PROXIMITY 1 IS SET WHEN /WORD 0–WORD 3/ EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_DETECTION_RATE REGISTER.

3. PROXIMITY 2 IS SET WHEN /AVERAGE–AMBIENT/ EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER.

4. DESCRIPTION OF COMPARATOR FUNCTIONS:
COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR.
COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR, OR APPROACHING A SENSOR VERY SLOWLY.
ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION.
FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR.
COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW FILTER EN IS SET AND PROXIMITY IS NOT SET.

05702-021

Figure 22. AD7142 Proximity Detection and Environmental Calibration

Rev. PrD | Page 18 of 64

Preliminary Technical Data AD7142/AD7142-1

ENVIRONMENTAL CALIBRATION

The AD7142 provides on-chip capacitance sensor calibration to
automatically adjust for environmental conditions that have an
effect on the capacitance sensor ambient levels. Capacitance
sensor output levels are sensitive to temperature, humidity, and
in some cases, dirt. The AD7142 achieves optimal and reliable
sensor performance by continuously monitoring the CDC
ambient levels and correcting for any changes by adjusting the
initial STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW
register values. The CDC ambient level is defined as the
capacitance sensor output level during periods when the user is
not approaching or in contact with the sensor.

The compensation logic runs automatically on every conversion
after configuration when the AD7142 is not being touched. This
allows the AD7142 to account for rapidly changing environ­mental conditions.

calibration algorithm prevents errors such as this from
occurring.

SENSOR 1 INT

ASSERTED

CDC OUTPUT CODES

SENSOR 2 INT

NOT ASSERTED

CHANGING ENVIRONMENTALCONDITIONS

Figure 24. Typical Sensor Behavior without Calibration Applied

STAGE_OFFSET_HIGH
(INITIAL REGISTER VALUE)

CDC AMBIENT
VALUE DRIFTING

STAGE_OFFSET_LOW
(INITIAL REGISTER VALUE)

t

05702-023

The ambient compensation control registers give the host access
to general setup and controls for the compensation algorithm.
The RAM stores the compensation data for each conversion
stage, as well as setup information specific to each stage.

Figure 23 shows an example of an ideal capacitance sensor
behavior where the CDC ambient level remains constant
regardless of the environmental conditions. In this example, the
initial settings programmed in the STAGE_OFFSET_HIGH and
STAGE_OFFSET_LOW registers are sufficient to detect a
sensor contact resulting with the AD7142 asserting the

INT

output when the offset levels are exceeded.

SENSOR 1 INT

ASSERTED

CDC OUTPUT CODES

SENSOR 2 INT

ASSERTED

CHANGING ENVIRONMENTALCONDITIONS

STAGE_OFFSET_HIGH
(INITIAL REGISTER VALUE)

CDC AMBIENT VALUE

STAGE_OFFSET_LOW
(INITIAL REGISTER VALUE)

t

Figure 23. Ideal Sensor Behavior with a Constant Ambient Level

Capacitance Sensor Behavior Without Calibration

Figure 24 shows the typical behavior of a capacitance sensor
with no applied calibration. This figure shows ambient levels
drifting over time as environmental conditions change. The
ambient level drift has resulted in the detection of a missed user
contact on Sensor 2. This is a result of the initial low offset level
remaining constant while the ambient levels drifted upward
beyond the detection range. The
with Calibration

section describes how the AD7142 adaptive

Capacitance Sensor Behavior

Capacitance Sensor Behavior with Calibration

The AD7142 on-chip adaptive calibration algorithm prevents
sensor detection errors such the one shown in

Figure 24. This is
achieved by monitoring the CDC ambient levels and internally
adjusting the initial offset level register values according to the
amount of ambient drift measured on each sensor. This closed
loop routine ensures the reliability and repeatability operation
of every sensor connected to the AD7142 under dynamic
environmental conditions.

Figure 25 shows a simplified
example of how the AD7142 applies the adaptive calibration
process resulting in no interrupt errors under changing CDC
ambient levels due to environmental conditions.

SENSOR 1 INT

ASSERTED

1

CDC OUTPUT CODES

4

05702-022

CHANGING ENVIRONMENTALCONDITIONS

NOTES

1. INITIAL STAGE_OFFSET_HIGH REGISTER VALUE

2. POST CALIBRATED REGISTER STAGE_OFFSET_HIGH VALUE

3. POST CALIBRATED REGISTER STAGE_OFFSET_HIGH VALUE

4. INITIAL STAGE_OFFSET_LOW REGISTER VALUE

5. POST CALIBRATED REGISTER STAGE_OFFSET_LOW VALUE

6. POST CALIBRATED REGISTER STAGE_OFFSET_LOW VALUE

2

5

SENSOR 2 INT

ASSERTED

Figure 25. Typical Sensor Behavior with

Calibration Applied on the Data Path

3

6

STAGE_OFFSET_HIGH
(POST CALIBRATED
REGISTER VALUE)

CDC AMBIENT
VALUE DRIFTING

STAGE_OFFSET_LOW
(POST CALIBRATED
REGISTER VALUE)

t

05702-024

Rev. PrD | Page 19 of 64

AD7142/AD7142-1 Preliminary Technical Data

ADAPTIVE THRESHOLD AND SENSITIVITY

The AD7142 provides an on-chip self-learning adaptive
threshold and sensitivity algorithm. This algorithm continu­ously monitors the output levels of each sensor and automatically
rescales the threshold levels proportionally to the sensor area
covered by the user. As a result, the AD7142 maintains optimal
threshold and sensitivity levels for all types of users regardless
of their finger sizes.

The threshold level is always referenced from the ambient level
and is defined as the CDC converter output level that must be
exceeded for a valid sensor contact. The sensitivity level is
defined as how sensitive the sensor is before a valid contact is
registered.

Figure 26 provides an example of how the adaptive threshold
and sensitivity algorithm works. In a case where the adaptive
threshold and sensitivity algorithm are disabled, the positive
and negative sensor threshold levels are set by the

STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW initial
values. Reference A in

Figure 26 shows that this results in an under
sensitive threshold level for a small finger user, demonstrating the
disadvantages of a fixed threshold level. By enabling the adaptive
threshold and sensitivity algorithm, the positive and negative
threshold levels are determined by the POS_THRESHOLD_SENSI
TIVITY and NEG_THRESHOLD_SENSITIVITY register values
and the most recent average maximum sensor output value.
These registers can be used to select 16 different positive and
negative sensitivity levels ranging between 25% and 95.32% of
the most recent average maximum output level referenced from
the ambient value. Reference B shows that the positive adaptive
threshold level is set at almost mid sensitivity with a 62.51%
threshold level by setting POS_THRESHOLD_SENSITIVITY =

1000.

Figure 26 also provides a similar example for the negative

threshold level with NEG_THRESHOLD_SENSITIVITY = 0001.

CDC OUTPUT CODES

AMBIENT LEVEL

NEG ADAPTIVE THRESHOLD LEVEL = 39.08%

Figure 26. Threshold Sensitivity Example with POS_THRESHOLD_SENSITIVITY = 1000 and NEG_THRESHOLD_SENSITIVITY = 0011

A

B

AVERAGE MAX VALUE

95.32%

62.51% = POS ADAPTIVE THRESHOLD LEVEL

25%

25%

95.32%

SENSOR CONTACTED

BY SMALL FINGER

AVERAGE MAX VALUE

25%

NEG ADAPTIVE THRESHOLD LEVEL = 39.08%

95.32%

SENSOR CONTACTED

BY LARGE FINGER

95.32%

62.51% = POS ADAPTIVE THRESHOLD LEVEL

STAGE_OFFSET_HIGH
(INITIAL VALUE)

25%

STAGE_OFFSET_LOW
(INITIAL VALUE)

05702-025

Rev. PrD | Page 20 of 64