Analog Devices AD7008JP50, AD7008AP20, AD7008-PCB Datasheet

CMOS

a

FEATURES
Single +5 V Supply
32-Bit Phase Accumulator
On-Chip COSINE and SINE Look-Up Tables
On-Chip 10-Bit DAC
Frequency, Phase and Amplitude Modulation
Parallel and Serial Loading
Software and Hardware Power Down Options
20 MHz and 50 MHz Speed Grades
44-Pin PLCC

APPLICATIONS
Frequency Synthesizers
Frequency, Phase or Amplitude Modulators
DDS Tuning
Digital Modulation

PRODUCT DESCRIPTION

The AD7008 direct digital synthesis chip is a numerically con­trolled oscillator employing a 32-bit phase accumulator, sine and
cosine look-up tables and a 10-bit D/A converter integrated on a
single CMOS chip. Modulation capabilities are provided for

DDS Modulator

AD7008

phase modulation, frequency modulation, and both in-phase and
quadrature amplitude modulation suitable for QAM and SSB
generation.

Clock rates up to 20 MHz and 50 MHz are supported. Fre­quency accuracy can be controlled to one part in 4 billion.
Modulation may be effected by loading registers either through
the parallel microprocessor interface or the serial interface. A
frequency-select pin permits selection between two frequencies
on a per cycle basis.

The serial and parallel interfaces may be operated independently
and asynchronously from the DDS clock; the transfer control
signals are internally synchronized to prevent metastability prob­lems. The synchronizer can be bypassed to reduce the transfer
latency in the event that the microprocessor clock is synchro­nous with the DDS clock.

A power-down pin allows external control of a power-down
mode (also accessible through the microprocessor interface)
The AD7008 is available in 44-pin PLCC.

PRODUCT HIGHLIGHT

1. Low Power

2. DSP/µP Interface

3. Completely Integrated

FUNCTIONAL BLOCK DIAGRAM

CLOCK

FSELECT

SCLK

SDATA

V

AA

FREQ0

FREQ1

32

REG

32

REG

32-BIT SERIAL REGISTER

32-BIT PARALLEL REGISTER

MPU INTERFACE

D0

MUX

GND

32

ACCUMULATOR

D15

Σ

PHASE

WR CS

32

12

Σ

12

PHASE REG

COMMAND REG

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

V

ADJUST

10-BIT DAC

RESETTEST

REF

COMP

IOUT

IOUT

SLEEP

© Analog Devices, Inc., 1995

FS ADJUST

IQMOD [19:10]

10

10

SIN

12

SIN/COS

ROM

10

COS

TRANSFER LOGIC

TC0 TC3 LOAD

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

10

Σ

10

10

IQMOD [9:0]

FULLSCALE

10

AD7008

AD7008–SPECIFICATIONS

(VAA = VDD = +5 V ± 5%; TA = T

1

IOUT and

IOUT, unless otherwise noted)

MIN

to T

MAX

, R

SET

= 390 Ω, R

= 1 Ω for

LOAD

Parameter Min Typ Max Min Typ Max Units Comments

AD7008AP20 AD7008JP50 Test Conditions/

SIGNAL DAC SPECIFICATIONS

Resolution 10 10 Bits
Update Rate (f

) 20 50 MSPS

MAX

IOUT Full Scale 20 20 mA
Output Compliance 1 1 Volts
DC Accuracy

Integral Nonlinearity

+1 +1 LSB

Differential Nonlinearity ± 1 ±1 LSB

DDS SPECIFICATIONS

Update Rate (f

2

) 20 50 MSPS

MAX

Dynamic Specifications

Signal-to-Noise 50 50 dB f

Total Harmonic Distortion –55 –53 dB f

Spurious Free Dynamic Range (SFDR)

3

Narrow Band (±50 kHz) –70 –70 dBc f

= f

CLK

MAX

= 2 MHz

f

OUT

= f

CLK

MAX

f

= 2 MHz

OUT

= 6.25 MHz,

CLK

= 2.11 MHz

f

OUT

Wide Band (±2 MHz) –55 –55 dBc

VOLTAGE REFERENCE

Internal Reference @ +25°C
Reference TC 300 300 ppm/°C
V

Overdrive

REF

5

4

1.2 1.27 1.35 1.2 1.27 1.35 Volts

02 02 V

LOGIC INPUTS

V

, Input High Voltage VDD–0.9 VDD–0.9 Volts

INH

, Input Low Voltage 0.9 0.9 Volts

V

INL

I

, Input Current 10 10 µA

INH

CIN, Input Capacitance 10 10 pF

POWER SUPPLIES

V

DD

I

AA

I

DD

I

+ I

AA

DD

f

= Max 80 110 125 160 mA

CLK

Sleep = V

NOTES

1

Operating temperature ranges as follows: A Version: –40°C to +85°C; J Version: 0°C to +70°C.

2

All dynamic specifications are measured using IOUT. 100% Production tested.

3

f

= 6.25 MHz, Frequency Word = 5671C71C HEX, f

CLK

4

V

may be externally driven between 0 and VDD.

REF

5

Do not allow reference current to cause power dissipation beyond the limit of IAA + IDD shown above.

Specifications subject to change without notice.

DD

4.75 5.25 4.75 5.25 Volts
26 26 mA R
22 + 1.5/MHz 22 + 1.5/MHz mA

10 20 mA

= 2.11 MHz.

OUT

= 390 Ω

SET

,

,

–2–

REV. B

AD7008

D0–D15

VALID DATA

CS

WR

t

11

t

10

t

12

t

13

t

15

t

14

SCLK

DB31SDATA

DB0

t

20

t

16

t

17

t

19

t

18

TIMING CHARACTERISTICS

(VAA = VDD +5 V ± 5%; TA = T

MIN

to T

, unless otherwise noted)

MAX

AD7008AP20 AD7008JP50

Parameter Min Typ Max Min Typ Max Units Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

t

15

t

16

t

17

t

18

t

19

t

20

NOTE

1

May be reduced to 1t1 if LOAD is synchronized to CLOCK and Setup (t4) and Hold (t5) Times for LOAD to CLOCK are observed.

50 20 ns CLOCK Period
20 8 ns CLOCK High Duration
20 8 ns CLOCK Low Duration
5 5 ns CLOCK to Control Setup Time
3 3 ns CLOCK to Control Hold Time
4t
2t

1
1

4t
2t

1
1

ns LOAD Period
ns LOAD High Duration

1

5 5 ns LOAD High to TC0–TC3 Setup Time
5 5 ns LOAD High to TC0–TC3 Hold Time
10 10 ns WR Falling to CS Low Setup Time
10 10 ns WR Falling to CS Low Hold Time
20 20 ns Minimum WR Low Duration
10 10 ns Minimum WR High Duration
33 nsWR to D0–D15 Setup Time
33 nsWR to D0–D15 Hold Time
20 20 ns SCLK Period
8 8 ns SCLK High Duration
8 8 ns SCLK Low Duration
10 10 ns SCLK Rising to SDATA Setup Time
10 10 ns SCLK Rising to SDATA Hold Time

t

1

t

2

CLOCK

t

t

4

FSEL, LOAD,

TC3–TC0

VALID VALID

t

5

Figure 1. Clock Synchronization Timing

t

7

LOAD

t

8

TC0–TC3

VALID

Figure 2. Register Transfer Timing

REV. B

3

Figure 3. Parallel Port Timing

t

6

t

9

Figure 4. Serial Port Timing

–3–

AD7008

MSB LSB

A WORD

D15–D0 ← A WORD*

B WORD

D15–D0 ← B WORD

A WORD

32-BIT PARALLEL ASSEMBLY REGISTER

*MOST SIGNIFICANT WORD IS LOADED FIRST

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

VAA, VDD to GND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . . . . –0.3 V to V

Analog I/O Voltage to AGND . . . . . . . . –0.3 V to V

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C

Commercial (J Version) . . . . . . . . . . . . . . . . . .0°C to +70°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +115°C

PLCC θ
θ

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Thermal Impedance . . . . . . . . . . . . . . . +53.8°C/W

JA

Thermal Impedance . . . . . . . . . . . . . . . +24.1°C/W

JC

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

+ 0.3 V

DD

+ 0.3 V

DD

Figure 5. 16-Bit Parallel Port Loading Sequence

MSB LSB

*MOST SIGNIFICANT BYTE IS LOADED FIRST

32-BIT PARALLEL ASSEMBLY REGISTER

A BYTE

A BYTE

B BYTE

A BYTE

A BYTE

B BYTE

C BYTE D BYTE

B BYTE

C BYTE

D7–D0 ← A BYTE*

D7–D0 ← B BYTE

D7–D0 ← C BYTE

D7–D0 ← D BYTE

AD7008AP20 –40°C to +85°C 44-Pin PLCC P-44A
AD7008JP50 0°C to +70°C 44-Pin PLCC P-44A
AD7008/PCB* 1–3.5" Disk

*AD7008/PCB DDS Evaluation Kit, assembled and tested. Kit includes an

AD7008JP50.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7008 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

7

DGND

D8
D9

D10

D11
D12
D13
D14
D15

WR

V

17

DD

PIN CONFIGURATION

PLCC

AA

V

COMP

D0

IOUT

FS ADJUST

PIN NO. 1 IDENTIFIER

AD7008 PLCC

TOP VIEW

(NOT TO SCALE)

D1

D3D4D5

D2

IOUT

AGND

DGND

D6

6

18

REF

V

DGND

Figure 6. 8-Bit Parallel Port Loading Sequence

WARNING!

ESD SENSITIVE DEVICE

TEST

SCLK

SDATA

40

V

39

DD

RESET
SLEEP
LOAD
TC3
TC2
TC1
TC0
FSELECT
CLOCK
DGND

29

28

DD

D7

CS

V

–4–

REV. B

PIN DESCRIPTION

Mnemonic Function

POWER SUPPLY

V

AA

Positive power supply for the analog section. A 0.1 µF decoupling capacitor should be connected between V
AGND. This is +5 V ± 5%.

AGND Analog Ground.
V

DD

Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between V
and DGND. This is +5 V ± 5%. Both V

and VDD should be externally tied together.

AA

DGND Digital Ground; both AGND and DGND should be externally tied together.

ANALOG SIGNAL AND REFERENCE

IOUT,

FS ADJUST Full-Scale Adjust Control. A resistor (R

IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT

and AGND.

nitude of the full-scale DAC current. The relationship between R

IOUT should be either tied directly to AGND or through an external load resistor to AGND.

) is connected between this pin and AGND. This determines the mag-

SET

and the full-scale current is as follows:

SET

AD7008

AA

DD

and

IOUT

V

REF

Voltage Reference Input. A 0.1 µF decoupling ceramic capacitor should be connected between V

FULL-SCALE

(mA) =

6233 ×V

R

SET

REF

V

= 1.27 V nominal R

REF

= 390 Ω typical

SET

and VAA.

REF

There is an internal 1.27 volt reference which can be overdriven by an external reference if required. See
specifications for maximum range.

COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF decoupling ceramic

capacitor should be connected between COMP and V

AA

.

DIGITAL INTERFACE AND CONTROL

CLOCK Digital Clock Input for DAC and NCO. DDS output frequencies are expressed as a binary fraction of the fre-

quency of this clock. The output frequency accuracy and phase noise is determined by this clock.

FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase

accumulator. Frequency selection can be done on a cycle-per-cycle basis. See Tables I, II and III.

LOAD Register load, active high digital Input. This pin, in conjunction with TC3–TC0, control loading of internal regis-

ters from either the parallel or serial assembly registers. The load pin must be high at least 1t

. See Table II.

1

TC3–TC0 Transfer Control address bus, digital inputs. This address determines the source and destination registers that are

used during a transfer. The source register can either be the parallel assembly register or the serial assembly regis­ter. The destination register can be any of the following: COMMAND REG, FREQ0 REG, FREQ1 REG,
PHASE REG or IQMOD REG. TC3–TC0 should be valid prior to LOAD rising and should not change until
LOAD falls. The Command Register can only be loaded from the parallel assembly register. See Table II.

CS Chip Select, active low digital input. This input in conjunction with WR is used when writing to the parallel

assembly register.

WR Write, active low digital input. This input in conjunction with CS is used when writing to the parallel assembly

register.

D7–D0 Data Bus, digital inputs. These represent the low byte of the 16-bit data input port used to write to the 32-bit

parallel assembly register. The databus can configured for either a 8-bit or 16-bit MPU/DSP ports.

D15–D8 Data Bus, digital inputs. These represent the high byte of the 16-bit data input port used to write to the 32-bit

parallel assembly register. The databus can be configured for either a 8-bit or 16-bit MPU/DSP ports. When the
databus is configured for 8-bit operation, D8–D15 should be tied to DGND.

SCLK Serial Clock, digital input. SCLK is used, in conjunction with SDATA, to clock data into the 32-bit serial assem-

bly register.
SDATA Serial Data, digital input. Serial data is clocked on the rising edge of SCLK, Most Significant Bit (MSB) first.
SLEEP Low power sleep control, active high digital input. SLEEP puts the AD7008 into a low power sleep mode. Inter-

nal clocks are disabled, while also turning off the DAC current sources. A SLEEP bit is also provided in the

COMMAND REG to put the AD7008 into a low power sleep mode.
RESET Register Reset, active high digital input. RESET clears the COMMAND REG and all the modulation registers to

zero.
TEST Test Mode. This is used for factory test only and should be left as a No Connect.

REV. B

–5–