Analog Devices AD7002AS, AD7002 Datasheet

LC2MOS

a

FEATURES
Single +5 V Supply
Transmit Channel

On-Chip GMSK Modulator
Two 10-Bit D/A Converters
Analog Reconstruction Filters
Power-Down Mode

Receive Channel

Two Sigma-Delta A/D Converters
FIR Digital Filters
On-Chip Offset Calibration

Power-Down Mode
3 Auxiliary D/A Converters
Power-Down Modes
On-Chip Voltage Reference
Low Power
44-Lead PQFP

APPLICATIONS
GSM
PCN

GSM Baseband I/O Port

AD7002

GENERAL DESCRIPTION

The AD7002 is a complete low power, two-channel, input/
output port with signal conditioning. The device is used as a
baseband digitization subsystem, performing signal conversion
between the DSP and the IF/RF sections in the Pan-European
telephone system (GSM).

The transmit path consists of an onboard digital modulator,
containing all the code necessary for performing Gaussian Mini­mum Shift Keying (GMSK), two high accuracy, fast DACs with
output reconstruction filters. The receive path is composed of
two high performance sigma-delta ADCs with digital filtering. A
common bandgap reference feeds the ADCs and signal DACs.

Three control DACs (AUX DAC1 to AUX DAC3) are in­cluded for such functions as AFC, AGC and carrier signal shap­ing. In addition, AUX FLAG may be used for routing digital
control information through the device to the IF/RF sections.

As it is a necessity for all GSM mobile systems to use the lowest
power possible, the device has power-down or sleep options for
all sections (transmit, receive and auxiliary).

The AD7002 is housed in 44-lead PQFP (Plastic Quad Flatpack).

Tx SLEEP

Tx DATA

Tx CLK

THREE-STATE

ENABLE

Rx CLK

Rx DATA (I DATA)

Rx SYNC

I/Q (Q DATA)

RATE

MODE

AUX DATA

AUX CLK

AUX LATCH

Rx SLEEP1
Rx SLEEP2

FUNCTIONAL BLOCK DIAGRAM

DV

DGND

DD

10-BIT DAC

GMSK PULSE

SHAPING ROM

10-BIT DAC

RECEIVE

CHANNEL

SERIAL

INTERFACE

16-BIT SHIFT REGISTER

9-BIT DAC 10-BIT DAC 8-BIT DAC

AUX

DAC 1

AUX

DAC 2

AUX

DAC 3

AUX

FLAG

2.5V

REFERENCE

I CHANNEL

DIGITAL FIR FILTER

OFFSET REGISTER

OFFSET REGISTER

Q CHANNEL

DIGITAL FIR FILTER

CAL

CLK2

AV

DD

AGND

4TH ORDER BESSEL

LOW-PASS FILTER

4TH ORDER BESSEL

LOW-PASS FILTER

Σ−∆ MODULATOR

Σ−∆ MODULATOR

CLK1 MZERO

AD7002

REFERENCE

OUTPUT BUFFER

SWITCH-CAP

FILTER

SWITCH-CAP

FILTER

I Tx

Q Tx

REF OUT

I Rx

Q Rx

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD7002–SPECIFICATIONS

(AVDD = +5 V 6 10%; DVDD = +5 V 6 10%; AGND = DGND = 0 V, f

1

TA = T

MIN

to T

, Rx SLEEP1 = Rx SLEEP2 = Tx SLEEP = DVDD, unless otherwise noted)

MAX

CLK1

= f

= 13 MHz;

CLK2

Parameter AD7002A Units Test Conditions/Comments

ADC SPECIFICATIONS

Resolution 12 Bits Rx SLEEP = 0 V, Tx SLEEP = V

Signal Input Span ±V

/2 Volts Biased on V

REF

(2.5 V)

REF

DD

Sampling Rate 13 MSPS
Output Word Rate 270.8 kHz RATE 0

541.7 kHz RATE 1

Accuracy

Integral ±1 LSB typ

Differential

2

0

Bias Offset Error ±6.5 LSB max After External Calibration; MZERO Low

±8 LSB typ After Internal Calibration; MZERO High

Input Resistance (DC) 300 kΩ typ

Input Capacitance 10 pF typ
Dynamic Specifications Input Frequency = 67.7 kHz

Dynamic Range 64 dB typ
Signal to (Noise+Distortion) 62 dB min

Gain Error ±0.5 dB max Input Frequency = 67.7 kHz, w.r.t. 2.5 V
Gain Match Between Channels ±0.15 dB max Input Frequency = 67.7 kHz
Filter Settling Time 47 µs typ

Frequency Response

0 kHz–100 kHz ±0.05 dB max

110 kHz –0.8 dB max

122 kHz –3.0 dB max

200 kHz –66 dB max

400 kHz–6.5 MHz –72 dB max

Absolute Group Delay 23 µs typ

Group Delay Between Channels (0 kHz–120 kHz) 5 ns typ
Coding Twos Complement
Power-Down Option Yes Rx SLEEP = VDD, Independent of Transmit

TRANSMIT DAC SPECIFICATIONS

Resolution 10 Bits Rx SLEEP = V

, Tx SLEEP = 0 V

DD

Number of Channels 2
Update Rate 4.33 MSPS 163 Oversampling of the Bit Rate
DC Accuracy

Integral ±0.7 LSB typ

Differential ±1.0 LSB typ
Output Signal Span ±V

/2 Volts Centered on V

REF

Nominal (100 kΩ/20 pF

REF

Load)

Output Signal Full-Scale Accuracy ±1 dB max w.r.t. 2.5 V
Offset Error ±25 mV max 10 0000 0000 Loaded to DAC
I Tx & Q Tx Gain Matching ±0.15 dB max
Absolute Group Delay 10 µs typ Measured at 67.7 kHz

Group Delay Linearity (0 kHz–120 kHz) 30 ns typ Each Channel, 10 kHz < F

Phase Matching Between Channels 0.5 ° typ Generating 67.7 kHz Sine Waves

GMSK Spectrum Mask

3

< 100 kHz

OUT

100 kHz –3 dB min

200 kHz –32 dB min

250 kHz –35 dB min

400 kHz –63 dB min

0.6 MHz –71 dB min

4.3 MHz –63 dB min

6.5 MHz –63 dB min

GMSK Phase Trajectory Error

Maximum Phase Effect Instance

3

3

2 ° rms max
6 ° peak max
9 µs typ

Output Impedance

I Tx 120 Ω typ

Q Tx 120 Ω typ

GMSK ROM Yes Contains GMSK Coding, Four-Bit Impulse

Response

Power-Down Option Yes Tx SLEEP = VDD, Independent of Receive

–2–

REV. B

AD7002

Parameter AD7002A Units Test Conditions/Comments

AUXILIARY DAC SPECIFICATIONS AUX1 AUX2 AUX3

Resolution 9 10 8 Bits
DC Accuracy

Integral ±2 ±2 ± 1 LSB max
Differential ±1 ±1 ±1 LSB max Guaranteed Monotonic
Offset Error ±2 ±4 ±1 LSB max
Gain Error ±4 ±4 ±2 LSB max

LSB Size 4.88 2.44 9.77 mV typ
Output Signal Span 0 to V

REF

0 to V

Output Impedance 10 10 10 kΩ max AUX DACs Have Unbuffered

888 kΩ typ

Coding Binary Binary Binary
Power-Down Yes Yes Yes Power-Down Is Implemented by

REFERENCE SPECIFICATIONS

REFOUT, Reference Output 2.4/2.6 V min/V max R

REFOUT, Reference Output @ +25°C 2.5 V typ R
Reference Temperature Coefficient 100 ppm/°C typ

Reference Variation

4

± 10 mV max

Output Impedance 60 Ω typ

LOGIC INPUTS

, Input High Voltage VDD – 0 9 V min

V

INH

, Input Low Voltage 0.9 V max

V

INL

, Input Current 10 µA max

I

INH

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

, Output High Voltage 4.0 V min |I

V

OH

VOL, Output Low Voltage 0.4 V max |I

POWER SUPPLIES

AV

DD

DV

DD

I

DD

All Sections Active 30 mA max
ADC and Auxiliary Paths Active

Transmit DAC and AUX Paths Active

Auxiliary Path only Active

NOTES

1

Operating temperature range: A Version: –40°C to +85°C.

2

Unmeasurable: sigma-delta conversion is inherently free of differential nonlinearities.

3

See terminology.

4

Change in reference voltage due to a change in Tx SLEEP or Rx SLEEP modes.

5

Measured while the digital inputs to the transmit interface are static.

6

Measured while the digital inputs to the receive interface are static.

7

Measured while the digital inputs to the auxiliary interface are static.

Specifications subject to change without notice.

5

6

5, 6, 7

4.5/5.5 V min/V max

4.5/5.5 V min/V max

18 mA max Tx SLEEP = V
15 mA typ
14 mA max Rx SLEEP1 = Rx SLEEP2 = V
11 mA typ

2 mA max Tx SLEEP = Rx SLEEP1 =

REF

0 to V

Volts Unloaded Output

REF

Resistive Outputs

Loading All 1s or All 0s

= 100 kΩ, C

L

= 100 kΩ, C

L

| ≤ 200 µA

OUT

| ≤ 1.6 mA

OUT

Rx SLEEP2 = V

= 1 nF

L

= 1 nF

L

DD

DD

DD

–3–REV. B

AD7002

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C unless otherwise noted)

A

1

DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DV

Analog Input Voltage to AGND . . . . –0.3 V to AV

Input Current to Any Pin Except Supplies

2

. . . . . . . . ±10 mA

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial Plastic (A Version) . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates Above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at those or any other conditions above those listed in the operational sections
of this specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

PIN DESCRIPTION

DD

AUX DAC2

Q Tx

AV

AGND
38

37

39

36

17

18

20

19

NC

Rx SYNC

I/Q (QDATA)

Rx DATA (IDATA)

AUX DAC3

AUX DAC1

35

34

22

21

Rx CLK

3-STATE ENABLE

33

AUX FLAG

32

AUX LATCH

31

AUX CLK
AUX DATA

30

MZERO

29
28

NC
Rx SLEEP1

27
26

TEST2

25

NC

24

Rx SLEEP2

23

CAL

Tx SLEEP

Tx DATA

Tx CLK

DV

DGND

NC

CLK1

TEST1

NC
NC

CLK2

DD

I Rx

44

1
2
3
4
5
6
7
8
9

10

11

NC = NO CONNECT

PIN 1 IDENTIFIER

12

RATE

TEST4

REFOUT

I Tx

Q Rx
42

40

43

41

AD7002 PQFP

TOP VIEW

(Not to Scale)

13

15

14

16

DD

DV

DGND

MODE

TEST3

TERMINOLOGY
Absolute Group Delay

Absolute group delay is the rate of change of phase versus fre-

quency, dθ/df. It is expressed in microseconds.

Bias Offset Error

This is the offset error (in LSBs) in the ADC section.

Differential Nonlinearity

This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the DAC
or ADC.

Dynamic Range

Dynamic Range is the ratio of the maximum output signal to the
smallest output signal the converter can produce (1 LSB), ex­pressed logarithmically, in decibels (dB = 20log
an N-bit converter, the ratio is theoretically very nearly equal to

N

2

(in dB, 20Nlog10(2) = 6.02N). However, this theoretical

(ratio)). For

10

value is degraded by converter noise and inaccuracies in the
LSB weight.

Full-Scale Accuracy

This is the measure of the ADC full-scale error after the offset
has been adjusted out.

Gain Error

This is a measure of the output error between an ideal DAC and
the actual device output with all ls loaded after offset error has
been adjusted out and is expressed in LSBs. In the AD7002,
gain error is specified for the auxiliary section.

Gain Matching Between Channels

This is the gain matching between the ITx and QTx channel
and is expressed in dBs.

GMSK Spectrum Mask

This is the combined output spectrum of the I and Q analog
outputs when transmitting a random sequence of data bits on
the AD7002 transmit channel.

–3

–32

–35

AMPLITUDE – dB

100 200

250

–63

–71 –71

400 600 1800 4300

FREQUENCY – kHz

–63

–63

6500

ORDERING GUIDE

AD7002 Transmit GMSK Spectrum Mask

Temperature Package Package

Model Range Description Option

AD7002AS –40°C to +85°C Plastic Quad Flatpack S-44

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7002 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

AD7002

GMSK Phase Trajectory Error

This is a measure of the phase error between the transmitted

phase of an ideal GMSK modulator and the actual phase trans-

mitted by the AD7002, when transmitting a random sequence

of data bits. It is specified as a peak phase error and also as an

rms phase error.

Group Delay Linearity

The group delay linearity, or differential group delay, is the

group delay over the full band relative to the group delay at one

particular frequency. The reference frequency for the AD7002 is

1 kHz.

Group Delay Between Channels

This is the difference between the group delay of the I and Q

channels and is a measure of the phase matching characteristics

of the two.

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the DAC or ADC transfer function.

Maximum Phase Effect Instance

This is the time at which a transmitted data bit will have its

maximum phase change at the ITx and QTx outputs (see fig-

ure). This time includes the delay in the GMSK modulator and

in the Analog low-pass filters. Maximum phase effect instance is

measured from the Tx CLK falling edge, which latches the data

bit, to the ITx and QTx analog outputs.

90

°

45

°

FOR ONE DATA BIT

TRANSMITTED PHASE

0

°

≈ 9µs

DATA BIT

CLOCKED IN BY TxCLK

MAXIMUM PHASE
EFFECT INSTANT

Transmit Channel Maximum Phase Effect Instance

Output Rate

This is the rate at which data words are made available at the

Rx DATA pin (Mode 0) or the IDATA and QDATA pins

(Mode 1). There are two rates, depending on whether the de-

vice is operated in RATE0 or RATE1.

Offset Error

This is the amount of offset, w.r.t. V

in the transmit DACs

REF

and the auxiliary DACs and is expressed in mVs for the Trans­mit section and in LSBs for the Auxiliary section.

Output Impedance

This is a measure of the drive capability of the auxiliary DAC

outputs and is expressed in kΩs.

Output Signal Span

This is the output signal range for the Transmit Channel section
and the Auxiliary DAC section. For the transmit channel the

span is ±1.25 volts centered on 2.5 volts, and for the Auxiliary

DAC section it is 0 to +V

REF

.

Output Signal Full-Scale Accuracy

This is the accuracy of the full-scale output (all 1s loaded to the
DACs) on each transmit channel measured w.r.t. 25 V and is
expressed in dBs.

Phase Matching Between Channels

This is a measure of the phase matching characteristics of the I
and Q transmit channels. It is obtained by transmitting all ones
and then measuring the difference between the actual phase
shift between the I and Q outputs and the ideal phase shift of

90°.

Sampling Rate

This is the rate at which the modulators on the receive channels
sample the analog input.

Settling Time

This is the digital filter settling time in the AD7002 receive
section. On initial power-up, or after returning from the sleep
mode, it is necessary to wait this amount of time to obtain use­ful data.

Signal Input Span

The input signal range for the I and Q channels is biased about
V

. It can go ±1.25 volts about this point.

REF

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the
output of the receive channel. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all amplitude of the
fundamental. Noise is the rms sum of all nonfundamental sig­nals up to half the sampling frequency (f

/2), excluding dc. The

S

ratio is dependent upon the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza­tion noise. The theoretical signal-to-(noise+distortion) ratio for
a sine wave is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

–5–REV. B