Analog Devices AD676 Datasheet

16-Bit 100 kSPS

a

FEATURES
Autocalibrating
On-Chip Sample-Hold Function
Parallel Output Format
16 Bits No Missing Codes
61 LSB INL
–97 dB THD
90 dB S/(N+D)
1 MHz Full Power Bandwidth

PRODUCT DESCRIPTION

The AD676 is a multipurpose 16-bit parallel output analog-to­digital converter which utilizes a switched-capacitor/charge
redistribution architecture to achieve a 100 kSPS conversion
rate (10 µs total conversion time). Overall performance is opti-
mized by digitally correcting internal nonlinearities through
on-chip autocalibration.

The AD676 circuitry is segmented onto two monolithic chips—
a digital control chip fabricated on Analog Devices DSP CMOS
process and an analog ADC chip fabricated on our BiMOS II
process. Both chips are contained in a single package.

The AD676 is specified for ac (or “dynamic”) parameters such
as S/(N+D) Ratio, THD and IMD which are important in sig­nal processing applications. In addition, dc parameters are
specified which are important in measurement applications.

Sampling ADC

AD676

FUNCTIONAL BLOCK DIAGRAM

SAR
PAT

GEN
ALU

RAM

ANALOG

COMP

AD676

CHIP

L
A
T
C

H

BUSY

7

1
6

BIT 1 – BIT 16

19
28

V

15

IN

V

REF

AGND

CAL

SAMPLE

CLK 10

14
16

16
13

DIGITAL
CHIP

8

9

INPUT

BUFFERS

MICRO-CODED

CONTROLLER

16-BIT

CAL
DAC

LOGIC & TIMING

LEVEL TRANSLATORS

DAC

AGND SENSE

The AD676 operates from +5 V and ± 12 V supplies and typi­cally consumes 360 mW during conversion. The digital supply
(V

) is separated from the analog supplies (VCC, VEE) for re-

DD

duced digital crosstalk. An analog ground sense is provided for
the analog input. Separate analog and digital grounds are also
provided.

The AD676 is available in a 28-pin plastic DIP or 28-pin side­brazed ceramic package. A serial-output version, the AD677, is
available in a 16-pin 300 mil wide ceramic or plastic package.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD676–SPECIFICATIONS

AC SPECIFICATIONS

(T

MIN

to T

= +12 V 6 5%, V

MAX, VCC

= –12 V 6 5%, VDD = +5 V 6 10%)

EE

1

AD676J/A AD676K/B

Parameter Min Typ Max Min Typ Max Units

Total Harmonic Distortion (THD)

@ 83 kSPS, T

MIN

to T

MAX

2

–96 –88 –97 –90 dB

0.0016 0.004 0.0014 0.003 %

@ 100 kSPS, +25°C –96 –97 dB

0.0016 0.0014 %

@ 100 kSPS, T

Signal-to-Noise and Distortion Ratio (S/(N+D))

@ 83 kSPS, T

MIN

MIN

to T

to T

MAX

MAX

2, 3

–92 –92 dB

0.0025 0.0025 %

85 89 87 90 dB

@ 100 kSPS, +25°C8990dB

@ 100 kSPS, T
Peak Spurious or Peak Harmonic Component –98 –98 dB
Intermodulation Distortion (IMD)

MIN

to T

MAX

86 86 dB

4

2nd Order Products –102 –102 dB

3rd Order Products –98 –98 dB
Full Power Bandwidth 1 1 MHz
Noise 160 160 µV rms

DIGITAL SPECIFICATIONS

(for all grades T

MIN

to T

, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)

MAX

Parameter Test Conditions Min Typ Max Units

LOGIC INPUTS
V

IH

V

IL

I

IH

I

IL

C

IN

High Level Input Voltage 2.4 VDD + 0.3 V
Low Level Input Voltage –0.3 0.8 V
High Level Input Current VIH = V
Low Level Input Current V

= 0 V –10 +10 µA

IL

DD

–10 +10 µA

Input Capacitance 10 pF

LOGIC OUTPUTS
V

OH

V

OL

NOTES

1

V

= 10.0 V, (Conversion Rate (fs) = 83 kSPS, fIN = 1.0 kHz, VIN = –0.05 dB, Bandwidth = fs/2 unless otherwise indicated. All measurements referred to a 0 dB

REF

(20 V p-p) input signal. Values are post-calibration.

2

For other input amplitudes, refer to Figure 13.

3

For other input ranges/voltages reference values see Figure 12.

4

fa = 1008 Hz. fb = 1055 Hz. See Definition of Specifications section and Figure 15.

Specifications subject to change without notice.

High Level Output Voltage IOH = 0.1 mA VDD –1 V V

I

= 0.5 mA 2.4 V

OH

Low Level Output Voltage IOL = 1.6 mA 0.4 V

–2–

REV. A

AD676

DC SPECIFICATIONS

(T

to T

MIN

, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 1O%)

MAX

1

AD676J/A AD676K/B

Parameter Min Typ Max Min Typ Max Units

TEMPERATURE RANGE

J, K Grades 0 +70 0 +70 °C
A, B Grades –40 +85 –40 +85 °C

ACCURACY

Resolution 16 16 Bits
Integral Nonlinearity (INL)

@ 83 kSPS, T

MIN

to T

MAX

±1 ±1 ±1.5 LSB

@ 100 kSPS, +25°C ±1 ±1 LSB

@ 100 kSPS, T
Differential Nonlinearity (DNL)–No Missing Codes 16 16 Bits
Bipolar Zero Error
Gain Error (at Nominal Supplies)

@ 83 kSPS

2

@ 100 kSPS, +25°C 0.005 0.005 % FSR

@ 100 kSPS
Temperature Drift, Bipolar Zero

to T

MIN

MAX

2

(at Nominal Supplies) 0.005 0.005 % FSR

±2 ±2 LSB

0.005 0.005 % FSR

2

3

0.01 0.01 % FSR
% FSR

J, K Grades 0.0015 0.0015 % FSR
A, B Grades 0.003 0.003 % FSR

Temperature Drift, Gain

3

J, K Grades 0.0015 0.0015 % FSR
A, B Grades 0.003 0.003 % FSR

VOLTAGE REFERENCE INPUT RANGE4 (V

ANALOG INPUT

Input Range (V

5

) ±V

IN

)5 10 5 10V

REF

REF

±V

REF

V

Input Impedance * *
Input Settling Time 2 2 µs
Input Capacitance During Sample 50* 50* pF
Aperture Delay 6 6 ns
Aperture Jitter 100 100 ps

POWER SUPPLIES

Power Supply Rejection

V

= +12 V ± 5% ±1 ±1 LSB

CC

V

= –12 V ± 5% ±1 ±1 LSB

EE

V

= +5 V ± 10% ±1 ±1 LSB

DD

Operating Current

I

CC

I

EE

I

DD

14.5 18 14.5 18 mA

14.5 18 14.5 18 mA

25 25mA

Power Consumption 360 480 360 480 mW

NOTES

1

V

= 5.0 V, Conversion Rate = 83 kSPS unless otherwise noted. Values are post-calibration.

REF

2

Values shown apply to any temperature from T

3

Values shown are based upon calibration at +25°C with no additional calibration at temperature. Values shown are the worst case variation from the value at +25 °C.

4

See “APPLICATIONS” section for recommended voltage reference circuit, and Figure 12 for dynamic performance with other reference voltage values.

5

See “APPLICATIONS” section for recommended input buffer circuit.

*For explanation of input characteristics, see “ANALOG INPUT” section.
Specifications subject to change without notice.

MIN

to T

after calibration at that temperature.

MAX

REV. A

–3–

AD676

SAMPLE

(INPUT)

CLK

(INPUT)

BIT 1 – BIT 16

(OUTPUTS)

BUSY

(OUTPUT)

12345

t

S

t

SL

t

SC

t

CLK

t

CL

t

CH

t

OD

t

SD

t

SB

t

BS

t

C

13 14 15

16 17

t

S

(PREVIOUS CONVERSION)

(NEW DATA)

TIMING SPECIFICATIONS

(T

MIN

to T

= +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%, V

MAX VCC

= 10.0 V)

REF

1

Parameter Symbol Min Typ Max Units

Conversion Time
CLK Period
Calibration Time t
Sampling Time (Included in tC)t
CAL to BUSY Delay t
BUSY to SAMPLE Delay t
SAMPLE to BUSY Delay t
CLK HIGH
CLK LOW
SAMPLE LOW to 1st CLK Delay t
SAMPLE LOW t
Output Delay t
Status Delay t
CAL HIGH Time t

NOTES

1

See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.

2

Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion time is specified to account for the droop of the
internal sample/hold function. Longer conversion times may degrade performance. See “General Conversion Guidelines” for additional explanation of maximum con­version time.

3

580 ns is recommended for optimal accuracy over temperature.

4

tCH + tCL = t

2

3

4

4

and must be greater than 480 ns.

CLK

t

C

t

CLK
CT
S
CALB
BS
SB

t

CH

t

CL
SC
SL
OD
SD
CALH

t

CALH

10 1000 µs
480 ns

85,530 t

CLK

2 µs

75 150 ns

2 µs

15 100 ns
50 ns
50 ns
50 ns
100 ns

125 200 ns
50 ns
50 ns

SAMPLE

(INPUT)

CLK

(INPUT)

BIT 1 – BIT 16

(OUTPUTS)

BUSY

(OUTPUT)

CAL

BUSY

CLK

t

t

S

t

SC

t

BS

Figure 2a. General Conversion Timing

t

SL

12345

(PREVIOUS CONVERSION)

t

SB

C

t

CL

t

CLK

t

CH

13 14 15

t

CH

t

OD

t

t

CALB

t

CL

CT

t

CLK

Figure 1. Calibration Timing

16 17

(NEW DATA)

t

SD

Figure 2b. Continuous Conversion Timing

–4–

t

OD

REV. A

ORDERING GUIDE

WARNING!

ESD SENSITIVE DEVICE

Package

Model Temperature Range1S/(N+D) Max INL Package Description Option

AD676JD 0°C to +70°C 85 dB Ceramic 28-Pin DIP D-28
AD676KD 0°C to +70°C 87 dB ±1.5 LSB Ceramic 28-Pin DIP D-28
AD676AD –40°C to +85°C 85 dB Ceramic 28-Pin DIP D-28
AD676BD –40°C to +85°C 87 dB ±1.5 LSB Ceramic 28-Pin DIP D-28

NOTES

1

For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the AD676/883 data sheet.

2

D = Ceramic DIP.

ABSOLUTE MAXIMUM RATINGS*

VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +26.4 V

V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

CC

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –18 V to +0.3 V

EE

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V

Digital Inputs to DGND . . . . . . . . . . . . . . . . . . 0 V to +5.5 V

Analog Inputs, V

. . . . . . . . . . . . . . . . . . . . . . . (V

to AGND

REF

+ 0.3 V) to (VEE – 0.3 V)

CC

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

AD676

2

CAUTION

The AD676 features input protection circuitry consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast,
low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD676
has been classified as a Category 1 Device.

Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test
equipment, and discharge without detection. Unused devices must be stored in conductive foam
or shunts, and the foam discharged to the destination socket before devices are removed. For further
information on ESD Precaution. Refer to Analog Devices’ ESD Prevention Manual.

REV. A

–5–