Analog Devices AD674BBR, AD674BBD, AD674BAR, AD674BTD, AD674BKN Datasheet

Complete 12-Bit

a

FEATURES
Complete Monolithic 12-Bit A/D Converters with

Reference, Clock, and Three-State Output Buffers
Industry Standard Pinout
High Speed Upgrades for AD574A
8- and 16-Bit Microprocessor Interface
8 s (Max) Conversion Time (AD774B)
15 s (Max) Conversion Time (AD674B)
5 V, 10 V, 0 V–10 V, 0 V–20 V Input Ranges
Commercial, Industrial, and Military Temperature

Range Grades
MIL-STD-883-Compliant Versions Available

5V SUPPLY

V

DATA MODE SELECT

SHORT CYCLE A

READ/CONVERT R/C

ANALOG COMMON

REFERENCE INPUT

–12V/–15V SUPPLY

LOGIC

12/8

CHIP SELECT

BYTE ADDRESS/

CHIP ENABLE

12V/15V SUPPLY

10V REFERENCE

BIPOLAR OFFSET

V

REF OUT

REF IN

V

BIPOFF

10V SPAN INPUT

10V

20V SPAN INPUT

20V

A/D Converters

*

AD674B

FUNCTIONAL BLOCK DIAGRAM

1

2

3

CS

4

0

5

6

CE

7

CC

8

9

AC

10

11

EE

12

13

IN

14

IN

10V
REF

199.95
k

VO LTAG E

DIVIDER

CONTROL

CLOCK SAR

COMP

–

+

I DAC

I REF

+

–

DAC

N

AD674B/AD774B

V

EE

/AD774B

MSB

N
Y
B

3

B
L

S

E

T
A

12

A

T
E

N
Y

O

B

U

B

T

L

P

E

U
T

B

N

B

Y

U

B

F

B

F

L

E

E

R
S

C

LSB

STATUS

28

STS

27

DB11 (MSB)

26

DB10

25

DB9

24

DB8

23

DB7

22

DB6

21

DB5

20

DB4

19

DB3

18

DB2

17

DB1

16

DB0 (LSB)

DIGITAL

15

COMMON DC

*

DIGITAL
DATA
OUTPUTS

PRODUCT DESCRIPTION

The AD674B and AD774B are complete 12-bit successive­approximation analog-to-digital converters with three-state
output buffer circuitry for direct interface to 8- and 16-bit
microprocessor busses. A high-precision voltage reference and
clock are included on chip, and the circuit requires only power
supplies and control signals for operation.

The AD674B and AD774B are pin-compatible with the indus­try standard AD574A, but offer faster conversion time and bus­access speed than the AD574A and lower power consumption.
The AD674B converts in 15 µs (maximum) and the AD774B
converts in 8 µs (maximum).

The monolithic design is implemented using Analog Devices’
BiMOS II process allowing high-performance bipolar analog
circuitry to be combined on the same die with digital CMOS logic.
Offset, linearity, and scaling errors are minimized by active
laser trimming of thin-film resistors.

Five different grades are available. The J and K grades are
specified for operation over the 0°C to 70°C temperature range.
The A and B grades are specified from –40°C to +85°C, the T grade
is specified from –55°C to +125°C. The J and K grades are
available in a 28-lead plastic DIP or 28-lead SOIC. All other grades
are available in a 28-lead hermetically sealed ceramic DIP.

PRODUCT HIGHLIGHTS

1. Industry Standard Pinout: The AD674B and AD774B use
the pinout established by the industry standard AD574A.

2. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges: 0 V to
10 V and 0 V to 20 V unipolar; –5 V to +5 V and –10 V to
+10 V bipolar. The AD674B and AD774B operate on +5 V
and ± 12 V or ± 15 V power supplies.

3. Flexible Digital Interface: On-chip multiple-mode three-state
output buffers and interface logic allow direct connection to
most microprocessors. The 12 bits of output data can be
read either as one 12-bit word or as two 8-bit bytes (one with
8 data bits, the other with 4 data bits and 4 trailing zeros).

4. The internal reference is trimmed to 10.00 V with 1% maxi­mum error and 10 ppm/°C typical temperature coefficient.
The reference is available externally and can drive up to

2.0 mA beyond the requirements of the converter and bipo­lar offset resistors.

5. The AD674B and AD774B are available in versions compli­ant with MIL-STD-883. Refer to the Analog Devices Mili­tary Products Databook or current AD674B/AD774B/883B
data sheet for detailed specifications.

*Protected by U.S. Patent Nos. 4,250,445; 4,808,908; RE30586.

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

(T

AD674B/AD774B–SPECIFICATIONS

V

= +5 V  10%, VEE = –15 V  10% or –12 V  5%, unless otherwise noted.)

LOGIC

MIN

to T

with VCC = +15 V  10% or +12 V  5%,

MAX

J Grade K Grade A Grade B Grade T Grade

Model (AD674B or AD774B) Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 12 12 12 12 12 Bits

LINEARITY ERROR @ 25°C 1 1/2 1 1/2 1/2 LSB

T

MIN

to T

MAX

1 1/2 1 1/2 1 LSB

DIFFERENTIAL LINEARITY ERROR

(Minimum Resolution for Which No
Missing Codes are Guaranteed) 12 12 12 12 12 Bits

UNIPOLAR OFFSET1 @ 25°C 2 2 2 2 2 LSB

BIPOLAR OFFSET1 @ 25°C 6 3 6 3 3 LSB

FULL-SCALE CALIBRATION ERROR

1, 2

@ 25°C (with Fixed 50 Ω Resistor
from REF OUT to REF IN) 0.1 0.25 0.1 0.125 0.1 0.25 0.1 0.125 0.1 0.125 % of FS

TEMPERATURE RANGE 0 70 0 70 –40 +85 –40 +85 –55 +125 °C

TEMPERATURE DRIFT

3

(Using Internal Reference)

Unipolar 2 1 2 1 1 LSB
Bipolar Offset 2 1 2 1 2 LSB
Full-Scale Calibration 6 2 8 5 7 LSB

POWER SUPPLY REJECTION

Max Change in Full-Scale Calibration

VCC = +15 V ± 1.5 V or +12 V ± 0.6 V 2 1 2 1 1 LSB
V

= +5 V ± 0.5 V 1/2 1/2 1/2 1/2 1/2 LSB

LOGIC

VEE = –15 V ± 1.5 V or –12 V ± 0.6 V 2 1 2 1 1 LSB

ANALOG INPUT

Input Ranges

Bipolar –5 +5 –5 +5 –5 +5 –5 +5 –5 +5 V

–10 +10 –10 +10 –10 +10 –10 +10 –10 +10 V

Unipolar 0 10 0 10 0 10 0 10 0 10 V

0 20 0 20 0 20 0 20 0 20 V

Input Impedance

10 V Span 3 5 735 735 735 735 7 kΩ
20 V Span 6 10 14 6 10 14 6 10 14 6 10 14 6 10 14 kΩ

POWER SUPPLIES

Operating Range

V
V
V

LOGIC

CC

EE

4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V

11.4 16.5 11.4 16.5 11.4 16.5 11.4 16.5 11.4 16.5 V
–16.5 –11.4 –16.5 –11.4 –16.5 –11.4 –16.5 –11.4 –16.5 –11.4 V

Operating Current

I

LOGIC

I

CC

I

EE

3.5 7 3.5 7 3.5 7 3.5 7 3.5 7 mA

3.5 7 3.5 7 3.5 7 3.5 7 3.5 7 mA
10 14 10 14 10 14 10 14 10 14 mA

POWER CONSUMPTION 220 375 220 375 220 375 220 375 220 375 mW

175 175 175 175 175 mW

INTERNAL REFERENCE VOLTAGE 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 V

Output Current

(Available for External Loads) 2.0 2.0 2.0 2.0 2.0 mA

(External Load Should Not

Change During the Conversion)

NOTES

1

Adjustable to zero.

2

Includes internal voltage reference error.

3

Maximum change from 25°C value to the value at T

4

Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +16.5 V, VEE = –16.5 V, V

5

Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +12 V, VEE = –12 V, V

Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at T
max specifications are guaranteed, although only those shown in boldface are tested.

MIN

or T

MAX

.

, 25°C, and T

MIN

= +5.5 V, and outputs in high-Z mode.

LOGIC

= +5 V, and outputs in high-Z mode.

LOGIC

. Results from those tests are used to calculate outgoing quality levels. All min and

MAX

4

5

–2–

REV. C

t

HEC

t

HSC

t

SSC

t

HRC

t

SRC

t

SAC

t

HAC

t

C

t

DSC

CE

CS

R/C

A

0

STS

DB11 – DB0

HIGH

IMPEDANCE

AD674B/AD774B

(For all grades T

DIGITAL SPECIFICATIONS

VEE = –15 V  10% or –12 V  5%, unless otherwise noted.)

Parameter Test Conditions Min Max Unit

LOGIC INPUTS
V

IH

V

IL

I

IH

I

IL

C

IN

High Level Input Voltage 2.0 V
Low Level Input Voltage –0.5 +0.8 V
High Level Input Current VIN = V
Low Level Input Current VIN = 0 V –10 +10 µA
Input Capacitance 10 pF

LOGIC OUTPUTS
V

OH

V

OL

I

OZ

C

OZ

High Level Output Voltage IOH = 0.5 mA 2.4 V
Low Level Output Voltage IOL = 1.6 mA 0.4 V
High-Z Leakage Current VIN = 0 to V
High-Z Output Capacitance 10 pF

(For all grades T

SWITCHING SPECIFICATIONS

CONVERTER START TIMING (Figure 1)

J, K, A, B Grades T Grade

Parameter Symbol Min Typ Max Min Typ Max Unit

Conversion Time

8-Bit Cycle (AD674B) t
12-Bit Cycle (AD674B) t
8-Bit Cycle (AD774B) t

12-Bit Cycle (AD774B) t
STS Delay from CE t
CE Pulsewidth t

CS to CE Setup t
CS Low During CE High t

R/C to CE Setup t
R/C LOW During CE High t
A0 to CE Setup t
A0 Valid During CE High t

C

C

C

C

DSC

HEC

SSC

HSC

SRC

HRC

SAC

HAC

READ TIMING—FULL CONTROL MODE (Figure 2)

Parameter Symbol Min Typ Max Min Typ Max Unit

Access Time

CL = 100 pF t
Data Valid After CE Low t

Output Float Delay t
CS to CE Setup t
R/C to CE Setup t
A0 to CE Setup t
CS Valid After CE Low t
R/C High After CE Low t
A0 Valid After CE Low t

NOTES

1

tDD is measured with the load circuit of Figure 3a and is defined as the time required

for an output to cross 0.4 V or 2.4 V.

2

0°C to T

3

At –40°C.

4

At –55°C.

5

tHL is defined as the time required for the data lines to change 0.5 V when loaded with

the circuit of Figure 3b.

Specifications shown in boldface are tested on all devices at final electrical test with

MAX

.

worst case supply voltages at T
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
Specifications subject to change without notice.

REV. C

DD

HD

HL

SSR

SRR

SAR

HSR

HRR

HAR

MIN

6810 6810 µs
91215 91215 µs
456 456 µs
6 7.3 8 6 7.3 8 µs

50 50 ns
50 50 ns
50 50 ns
50 50 ns
50 50 ns
00ns
50 50 ns

J, K, A, B Grades T Grade

1

5

25
20

2

3

50 50 ns
00ns
50 50 ns
00ns
00ns
50 50 ns

, 25°C, and T

V

LOGIC

200 225 ns

75 150 75 150 ns

150 150 ns

. Results from those tests are used

MAX

to T

MIN

with VCC = +15 V  10% or +12 V  5%, V

MAX

LOGIC

to T

MIN

LOGIC

with VCC = +15 V  10% or +12 V  5%,

MAX

–10 +10 µA

–10 +10 µA

LOGIC

+ 0.5 V

LOGIC

= +5 V  10%, VEE = –15 V  10% or –12 V  5%, unless otherwise noted.)

Figure 1. Convert Start Timing

CE

t

HSR

t

HAR

t

HD

DATA

VA LI D

t

DD

25
15

t

CS

R/C

A

0

2

4

ns
ns

STS

DB11 – DB0

SSR

t

SRR

t

HIGH

IMPEDANCE

SAR

Figure 2. Read Cycle Timing

DB

N

3k

100pF

DB

N

HIGH-Z TO LOGIC 0HIGH-Z TO LOGIC 1

High-Z to Logic 1 High-Z to Logic 0

Figure 3a. Load Circuit for Access Time Test

DB

N

3k

LOGIC 1 TO HIGH-Z

100pF

DB

N

LOGIC 0 TO HIGH-Z

Logic 1 to High-Z Logic 0 to High-Z

Figure 3b. Load Circuit for Output Float Delay Test

–3–

= +5 V  10%,

t

HRR

HIGH

IMPEDANCE

t

HL

5V

3k

100pF

5V

3k

100pF

AD674B/AD774B

WARNING!

ESD SENSITIVE DEVICE

TIMING—STAND ALONE MODE (Figures 4a and 4b)

Parameter Symbol Min Typ Max Min Typ Max Unit

Data Access Time t
Low R/C Pulsewidth t
STS Delay from R/C t
Data Valid After R/C Low t
STS Delay After Data Valid t

High R/C Pulsewidth t

Specifications subject to change without notice.

J, K, A, B Grades T Grade

DDR

HRL

DS

HDR

HS

HRH

50 50 ns

25 25 ns
30 200 600 30 200 600 ns

150 150 ns

150 150 ns

200 225 ns

ABSOLUTE MAXIMUM RATINGS*

VCC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +16.5 V

to Digital Common . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V

V

EE

V

to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +7 V

LOGIC

Analog Common to Digital Common . . . . . . . . . . . . . . . ± 1 V

Digital Inputs to Digital Common . . . –0.5 V to V

Analog Inputs to Analog Common . . . . . . . . . . . . V

LOGIC

EE

+0.5 V

to V

CC

20 VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . ±24 V

REF OUT . . . . . . . . . . . . . . . . . . Indefinite Short to Common

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to V

CC

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

t

HRL

R/C

t

DS

STS

t

C

t

HDR

DB11–DB0

DATA

VA LI D

HIGH–Z

DATA VAL ID

Flgure 4a. Standalone Mode Timing Low Pulse R/

R/C

STS

DB11–DB0

t

HRH

t

DDRtHDR

HIGH–Z HIGH–Z

DATA

VA LI D

t

DS

t

C

t

HL

Figure 4b. Standalone Mode Timing High Pulse for R/

t

HS

C

C

ORDERING GUIDE

Conversion INL Package Package

MIN

to T

) Description Option

MAX

Model

l

Temperature Time (max) (T

AD674BJN 0°C to 70°C 15 µs ± 1 LSB Plastic DIP N-28
AD674BKN 0°C to 70°C 15 µs ± 1/2 LSB Plastic DIP N-28
AD674BAR –40°C to +85°C 15 µs ± 1 LSB Plastic SOIC R-28
AD674BBR –40°C to +85°C 15 µs ± 1/2 LSB Plastic SOIC R-28
AD674BAD –40°C to +85°C 15 µs ± 1 LSB Ceramic DIP D-28
AD674BBD –40°C to +85°C 15 µs ± 1/2 LSB Ceramic DIP D-28
AD674BTD –55°C to +125°C 15 µs ±1 LSB Ceramic DIP D-28
AD774BJN 0°C to 70°C8 µs ±1 LSB Plastic DIP N-28
AD774BKN 0°C to 70°C8 µs ± 1/2 LSB Plastic DIP N-28
AD774BAR –40°C to +85°C8 µs ±1 LSB Plastic SOIC R-28
AD774BBR –40°C to +85°C8 µs ± 1/2 LSB Plastic SOIC R-28
AD774BAD –40°C to +85°C8 µs ± 1 LSB Ceramic DIP D-28
AD774BBD –40°C to +85°C8 µs ± 1/2 LSB Ceramic DIP D-28
AD774BTD –55°C to +125°C8 µs ± 1 LSB Ceramic DIP D-28

NOTES

1

For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military

Products Databook or the current AD674B/ AD774B/883B data sheet.

2

N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD674B/AD774B features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

2

REV. C–4–