Complete
a
FEATURES
Complete Monolithic 12-Bit A/D Converters with
Reference, Clock, and Three-State Output Buffers
Industry Standard Pinout
High Speed Upgrades for AD574A
8- and 16-Bit Microprocessor Interface
8 ms (max) Conversion Time (AD774B)
15 ms (max) Conversion Time (AD674B)
65 V, 610 V, 0-10 V, 0-20 V Input Ranges
Commercial, Industrial and Military Temperature
Range Grades
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTION
The AD674B and AD774B are complete 12-bit successiveapproximation analog-to-digital converters with three-state
output buffer circuitry for direct interface to 8- and 16-bit
microprocessor busses. A high precision voltage reference and
clock are included on chip, and the circuit requires only power
supplies and control signals for operation.
The AD674B and AD774B are pin compatible with the industry
standard AD574A, but offer faster conversion time and busaccess speed than the AD574A and lower power consumption.
The AD674B converts in 15 µs (maximum) and the AD774B
converts in 8 µs (maximum).
The monolithic design is implemented using Analog Devices’
BiMOS II process allowing high performance bipolar analog circuitry to be combined on the same die with digital CMOS logic.
Offset, linearity and scaling errors are minimized by active lasertrimming of thin-film resistors.
Five different grades are available. The J and K grades are specified for operation over the 0°C to +70°C temperature range.
The A and B grades are specified from –40°C to +85°C, the T
grade is specified from –55°C to +125°C. The J and K grades
are available in a 28-pin plastic DIP or 28-lead SOIC. All other
grades are available in a 28-pin hermetically sealed ceramic
DIP.
12-Bit A/D Converters
AD674B*/AD774B*
FUNCTIONAL BLOCK DIAGRAM
+5V SUPPLY
DATA MODE SELECT
CHIP SELECT
BYTE ADDRESS/
SHORT CYCLE
READ/ CONVERT
CHIP ENABLE
+12/+15V SUPPLY
+10V REFERENCE
ANALOG COMMON
REFERENCE INPUT
_
_
12/ 15V SUPPLY
BIPOLAR OFFSET
10V SPAN INPUT
20V SPAN INPUT
V
LOGIC
V
REF OUT
REF IN
BIPOFF
10V
20V
1
2
12/8
3
CS
4
A
0
5
R/C
6
CE
7
CC
8
9
AC
10
11
V
EE
12
13
IN
14
IN
19.95k
10V
REF
VOLTAGE
DIVIDER
CONTROL
CLOCK
DAC
REF
I
SAR
COMP
I DAC
N
12
AD674B/AD774B
MSB
3
S
T
A
T
E
12
O
U
T
P
12
U
T
B
U
F
F
E
R
S
V
EE
LSB
PRODUCT HIGHLIGHTS
1. Industry Standard Pinout: The AD674B and AD774B utilize
the pinout established by the industry standard AD574A.
2. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges: 0 to
+10 V and 0 to +20 V unipolar; –5 V to +5 V and –10 V to
+10 V bipolar. The AD674B and AD774B operate on +5 V
and ±12 V or ±15 V power supplies.
3. Flexible Digital Interface: On-chip multiple-mode three-state
output buffers and interface logic allow direct connection to
most microprocessors. The 12 bits of output data can be
read either as one 12-bit word or as two 8-bit bytes (one with
8 data bits, the other with 4 data bits and 4 trailing zeros).
4. The internal reference is trimmed to 10.00 volts with 1%
maximum error and 10 ppm/°C typical temperature coefficient. The reference is available externally and can drive up
to 2.0 mA beyond the requirements of the converter and bipolar offset resistors.
5. The AD674B and AD774B are available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD674B/AD774B/883B
data sheet for detailed specifications.
N
Y
B
B
L
E
A
N
Y
B
B
L
E
B
N
Y
B
B
L
E
C
STATUS
28
STS
DB11 (MSB)
27
DB10
26
DB9
25
DB8
24
DB7
23
22
DB6
DB5
21
DB4
20
DB3
19
DB2
18
DB1
17
DB0 (LSB)
16
DIGITAL COMMON DC
15
DIGITAL
DATA
OUTPUTS
*Protected by U.S. Patent Nos. 4,250,445; 4,808,908; RE30586.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD674B/AD774B—SPECIFICATIONS
(T
V
= +5 V 6 10%, VEE = –15 V 6 10% or –12 V 6 5% unless otherwise noted)
LOGIC
MIN
to T
with VCC = +15 V 6 10% or +12 V 6 5%,
MAX
J Grade K Grade
Model (AD674B or AD774B) Min Typ Max Min Typ Max
RESOLUTION 12 12
LINEARITY ERROR @ +25°C 61 61/2
T
MIN
to T
MAX
61 61/2
DIFFERENTIAL LINEARITY ERROR
(Minimum Resolution for Which No
Missing Codes are Guaranteed) 12 12
UNIPOLAR OFFSET
BIPOLAR OFFSET
FULL-SCALE CALIBRATION ERROR
1
@ +25°C 62 62
1
@ +25°C 66 63
1, 2
@ +25°C
(with Fixed 50 Ω Resistor from REF OUT to REF IN) 0.1 0.25 0.1 0.125
TEMPERATURE RANGE 0 +70 0 +70
TEMPERATURE DRIFT
3
(Using Internal Reference)
Unipolar 62 61
Bipolar Offset 62 61
Full-Scale Calibration 66 62
POWER SUPPLY REJECTION
Max Change in Full-Scale Calibration
V
= 15 V ± 1.5 V or 12 V ± 0.6 V 62 61
CC
= 5 V ± 0.5 V 61/2 61/2
V
LOGIC
V
= –15 V ± 1.5 V or –12 V ± 0.6 V 62 61
EE
ANALOG INPUT
Input Ranges
Bipolar –5 +5 –5 +5
–10 +10 –10 +10
Unipolar 0 +10 0 +10
0 +20 0 +20
Input Impedance
10 Volt Span 3 5 7357
20 Volt Span 6 10 14 6 10 14
POWER SUPPLIES
Operating Range
V
LOGIC
V
CC
V
EE
+4.5 +5.5 +4.5 +5.5
+11.4 +16.5 +11.4 +16.5
–16.5 –11.4 –16.5 –11.4
Operating Current
I
LOGIC
I
CC
I
EE
3.5 7 3.5 7
3.5 7 3.5 7
10 14 10 14
POWER CONSUMPTION 220 375 220 375
175 175
INTERNAL REFERENCE VOLTAGE 9.9 10.0 10.1 9.9 10.0 10.1
Output Current (Available for External Loads) 2.0 2.0
(External Load Should Not Change During the Conversion)
NOTES
1
Adjustable to zero.
2
Includes internal voltage reference error.
3
Maximum change from +25°C value to the value at T
4
Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +16.5 V, VEE = –16.5 V, V
5
Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +12 V, VEE = –12 V, V
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at T
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
MIN
or T
MAX
.
, +25°C, and T
MIN
–2–
= +5.5 V, and outputs in high-Z mode.
LOGIC
= +5 V, and outputs in high-Z mode.
LOGIC
, and results from those tests are used to calculate outgoing
MAX
REV. B
AD674B/AD774B
A Grade B Grade T Grade
Min Typ Max Min Typ Max Min Typ Max Units
12 12 12 Bits
61 61/2 61/2 LSB
61 61/2 61 LSB
12 12 12 Bits
62 62 62 LSB
66 63 63 LSB
0.1 0.25 0.1 0.125 0.1 0.125 % of FS
–40 +85 –40 +85 –55 +125 °C
62 61 61 LSB
62 61 62 LSB
68 65 67 LSB
62 61 61 LSB
61/2 61/2 61/2 LSB
62 61 61 LSB
–5 +5 –5 +5 –5 +5 Volts
–10 +10 –10 +10 –10 +10 Volts
0 +10 0 +10 0 +10 Volts
0 +20 0 +20 0 +20 Volts
3 5 7357357kΩ
6 10 14 6 10 14 6 10 14 kΩ
+4.5 +5.5 +4.5 +5.5 +4.5 +5.5 Volts
+11.4 +16.5 +11.4 +16.5 +11.4 +16.5 Volts
–16.5 –11.4 –16.5 –11.4 –16.5 –11.4 Volts
3.5 7 3.5 7 3.5 7 mA
3.5 7 3.5 7 3.5 7 mA
10 14 10 14 10 14 mA
220 375 220 375 220 375 mW
175 175 175 mW
9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 Volts
2.0 2.0 2.0 mA
4
5
REV. B
–3–
AD674B/AD774B
3k
100pF
+5V
3k
100pF
DB
N
DB
N
10pF
10pF
3k
+5V
3k
DB
N
DB
N
(for all grades T
DIGITAL SPECIFICATIONS
VEE = –15 V 6 10% or –12 V 6 5%)
Parameter Test Conditions Min Max Units
LOGIC INPUTS
V
IH
V
IL
I
IH
I
IL
C
IN
High Level Input Voltage +2.0 V
Low Level Input Voltage –0.5 +0.8 V
High Level Input Current VIN = V
Low Level Input Current V
Input Capacitance 10 pF
LOGIC OUTPUTS
V
OH
V
OL
I
OZ
C
OZ
High Level Output Voltage IOH = 0.5 mA +2.4 V
Low Level Output Voltage IOL = 1.6 mA +0.4 V
High-Z Leakage Current VIN = 0 to V
High-Z Output Capacitance 10 pF
(for all grades T
SWITCHING SPECIFICATIONS
V
LOGIC
to T
MIN
IN
with VCC = +15 V 6 10% or +12 V 6 5%, V
MAX
LOGIC
–10 +10 µA
= 0 V –10 +10 µA
–10 +10 µA
MIN
LOGIC
to T
with VCC = +15 V 6 10% or +12 V 6 5%,
MAX
= +5 V 6 10%,
LOGIC
+0.5 V V
LOGIC
= +5 V 6 10%, VEE = –15 V 6 10% or –12 V 6 5%; unless otherwise noted)
CONVERTER START TIMING (Figure 1)
J, K, A, B Grades T Grade
Parameter Symbol Min Typ Max Min Typ Max Units
Conversion Time
8-Bit Cycle (AD674B) t
12-Bit Cycle (AD674B) t
8-Bit Cycle (AD774B) t
12-Bit Cycle (AD774B) t
STS Delay from CE t
CE Pulse Width t
CS to CE Setup t
CS Low During CE High t
R/C to CE Setup t
R/C LOW During CE High t
A0 to CE Setup t
A
Valid During CE High t
0
C
C
C
C
DSC
HEC
SSC
HSC
SRC
HRC
SAC
HAC
6810 6810 µs
91215 91215 µs
456 456 µs
6 7.3 8 6 7.3 8 µs
200 225 ns
50 50 ns
50 50 ns
50 50 ns
50 50 ns
50 50 ns
00ns
50 50 ns
READ TIMING—FULL CONTROL MODE (Figure 2)
J, K, A, B Grades T Grade
Parameter Symbol Min Typ Max Min Typ Max Units
Access Time
CL = 100 pF t
Data Valid After CE Low t
Output Float Delay t
CS to CE Setup t
R/C to CE Setup t
A
to CE Setup t
0
CS Valid After CE Low t
R/C High After CE Low t
A
Valid After CE Low t
0
NOTES
1
tDD is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
2
0°C to T
3
At –40°C.
4
At –55°C.
5
tHL is defined as the time required for the data lines to change 0.5 V when loaded with
MAX
.
the circuit of Figure 3b.
Specifications shown in boldface are tested on all devices at final electrical test with
worst case supply voltages at T
to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
DD
HD
HL
SSR
SRR
SAR
HSR
HRR
HAR
MIN
1
5
75 150 75 150 ns
25
20
2
3
25
15
2
4
150 150 ns
50 50 ns
00ns
50 50 ns
00ns
00ns
50 50 ns
, +25°C, and T
. Results from those tests are used
MAX
t
t
SRC
t
HSC
t
HRC
t
HEC
t
HAC
C
DSC
HIGH IMPEDANCE
t
CE
__
CS
R/C
A
STS
DB11 – DB0
t
SSC
_
t
SAC
0
Figure 1. Convert Start Timing
CE
CS
_
R/C
A
0
STS
ns
DB11 – DB0
ns
t
SSR
t
SRR
HIGH
IMPEDANCE
t
HSR
t
HRR
t
DATA
VALID
HAR
t
HD
HIGH
IMP.
t
HL
t
SAR
t
DD
Figure 2. Read Cycle Timing
High-Z to Logic 1 High-Z to Logic 0
Figure 3a. Load Circuit for Access Time Test
Logic 1 to High-Z Logic 0 to High-Z
Figure 3b. Load Circuit for Output Float Delay Test
REV. B–4–
TIMING—STAND-ALONE MODE (Figures 4a and 4b)
DATA
VALID
DATA VALID
HIGH-Z
t
HS
t
HDR
DS
t
t
DS
t
C
t
HRL
STS
R/C
DB11 DB0
_
DATA
VALID
STS
HIGH-Z
HIGH-Z
t
C
t
DS
t
HRH
t
DDR
t
HDR
t
HL
R/C
DB11 DB0
_
WARNING!
ESD SENSITIVE DEVICE
AD674B/AD774B
Parameter Symbol Min Typ Max Min Typ Max Units
Data Access Time t
Low R/C Pulse Width t
STS Delay from R/C t
Data Valid After R/C Low t
STS Delay After Data Valid t
High R/C Pulse Width t
Specifications subject to change without notice.
J, K, A, B Grades T Grade
DDR
HRL
DS
HDR
HS
HRH
50 50 ns
25 25 ns
30 200 600 30 200 600 ns
150 150 ns
150 150 ns
200 225 ns
ABSOLUTE MAXIMUM RATINGS*
VCC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +16.5 V
V
to Digital Common . . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V
EE
V
to Digital Common . . . . . . . . . . . . . . . . . . . . 0 to +7 V
LOGIC
Analog Common to Digital Common . . . . . . . . . . . . . . . ±1 V
Digital Inputs to Digital Common . . . –0.5 V to V
Analog Inputs to Analog Common . . . . . . . . . . . . . V
20 V
to Analog Common . . . . . . . . . . . . . . . . . . . . . . ±24 V
IN
LOGIC
EE
+0.5 V
to V
CC
REF OUT . . . . . . . . . . . . . . . . . . Indefinite Short to Common
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to V
CC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .825 mW
Lead Temperature, Soldering . . . . . . . . . . . . . . 300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Flgure 4a. Stand-Alone Mode Timing Low Pulse R/
C
Figure 4b. Stand-Alone Mode Timing High Pulse for R/
C
ORDERING GUIDE
Conversion INL Package Package
MIN
to T
) Description Option
MAX
Model
l
Temperature Time (max) (T
AD674BJN 0°C to +70°C 15 µs ±1 LSB Plastic DIP N-28
AD674BKN 0°C to +70°C 15 µs ±1/2 LSB Plastic DIP N-28
AD674BJR 0°C to +70°C 15 µs ±1 LSB Plastic SOIC R-28
AD674BKR 0°C to +70°C 15 µs ±1/2 LSB Plastic SOIC R-28
AD674BAD –40°C to +85°C 15 µs ± 1 LSB Ceramic DIP D-28
AD674BBD –40°C to +85°C 15 µs ±1/2 LSB Ceramic DIP D-28
AD674BTD –55°C to +125°C 15 µs ±1 LSB Ceramic DIP D-28
AD774BJN 0°C to +70°C8 µs ±1 LSB Plastic DIP N-28
AD774BKN 0°C to +70°C8 µs ±1/2 LSB Plastic DIP N-28
AD774BJR 0°C to +70°C 15 µs ±1 LSB Plastic SOIC R-28
AD774BKR 0°C to +70°C 15 µs ±1/2 LSB Plastic SOIC R-28
AD774BAD –40°C to +85°C8 µs ±1 LSB Ceramic DIP D-28
AD774BBD –40°C to +85°C8 µs ±1/2 LSB Ceramic DIP D-28
AD774BTD –55°C to +125°C8 µs ±1 LSB Ceramic DIP D-28
NOTES
1
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military
Products Databook or current AD674B/ AD774B/883B data sheet.
2
N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.
accumulate on the human body and test equipment and can discharge without detection. Although
the AD674B/AD774B features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
2
AD674B/AD774B
DEFINITION OF SPECIFICATIONS
LINEARITY ERROR
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale.” The point
used as “zero” occurs 1/2 LSB (1.22 mV for 10 volt span) before the first code transition (all zeroes to only the LSB “on”).
“Full scale” is defined as a level 1 1/2 LSB beyond the last code
transition (to all ones). The deviation of a code from the true
straight line is measured from the middle of each particular
code.
The K, B. and T grades are guaranteed for maximum nonlinearity of ±1/2 LSB. For these grades, this means that an analog
value which falls exactly in the center of a given code width will
result in the correct digital output code. Values nearer the upper
or lower transition of the code width may produce the next upper or lower digital output code. The J and A grades are guaranteed to ±1 LSB max error. For these grades, an analog value
which falls within a given code width will result in either the
correct code for that region or either adjacent one.
Note that the linearity error is not user adjustable.
DIFFERENTIAL LINEARITY ERROR (NO MISSING
CODES)
A specification which guarantees no missing codes requires that
every code combination appear in a monotonic increasing sequence as the analog input level is increased. Thus every code
must have a finite width. The AD674B and AD774B guarantee
no missing codes to 12-bit resolution, requiring that all 4096
codes must be present over the entire operating temperature
ranges.
UNIPOLAR OFFSET
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the actual transition from that point. This offset can be adjusted as
discussed later. The unipolar offset temperature coefficient
specifies the maximum change of the transition point over temperature, with or without external adjustment.
BIPOLAR OFFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
QUANTIZATION UNCERTAINTY
Analog-to-digital converters exhibit an inherent quantization
uncertainty of ±1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
LEFT-JUSTIFIED DATA
The output data format is left-justified. This means that the
data represents the analog input as a fraction of full scale, ranging from 0 to 4095/4096. This implies a binary point 4095 to
the left of the MSB.
FULL-SCALE CALIBRATION ERROR
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 volts for 10.000 volts full scale). The full-scale
calibration error is the deviation of the actual level at the last
transition from the ideal level. This error, which is typically 0.05
to 0.1% of full scale, can be trimmed out as shown in Figures 7
and 8. The full-scale calibration error over temperature is given
with and without the initial error trimmed out. The temperature
coefficients for each grade indicate the maximum change in
the full-scale gain from the initial value using the internal 10 V
reference.
TEMPERATURE DRIFT
The temperature drift for full-scale calibration, unipolar offset,
and bipolar offset specifies the maximum change from the initial
(+25°C) value to the value at T
POWER SUPPLY REJECTION
The standard specifications assume use of +5.00 V and
± 15.00 V or ±12.00 V supplies. The only effect of power supply
error on the performance of the device will be a small change in
the full-scale calibration. This will result in a linear change in all
low-order codes. The specifications show the maximum fullscale change from the initial value with the supplies at the various limits.
CODE WIDTH
A fundamental quantity for A/D converter specifications is the
code width. This is defined as the range of analog input values
for which a given digital output code will occur. The nominal
value of a code width is equivalent to 1 least significant bit
(LSB) of the full-scale range or 2.44 mV out of 10 volts for a
12-bit ADC.
MIN
or T
MAX
.
REV. B–6–
AD674B/AD774B
AD674B AND AD774B PIN DESCRIPTION
Symbol Pin No. Type Name and Function
AGND 9 P Analog Ground (Common).
A
0
BIP OFF 12 AI Bipolar Offset. Connect through a 50 Ω resistor to REF OUT for bipolar operation or to Analog
CE 6 DI Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
CS 3 DI Chip Select. Chip Select is Active LOW.
DB11-DB8 27-24 DO Data Bits 11 through 8. In the 12-bit format (see 12/
DB7-DB4 23-20 DO Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
DB3-DB0 19-16 DO Data Bits 3 through 0. In both the 12-bit and 8-bit format these pins provide the lower 4 bits of
DGND 15 P Digital Ground (Common).
REF OUT 8 AO +10 V Reference Output.
C 5 DI Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW
R/
REF IN 10 AI Reference Input is connected through a 50 Ω resistor to +10 V Reference for normal operation.
STS 28 DO Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
V
CC
V
EE
V
LOGIC
10 V
IN
20 V
IN
8 2 DI The 12/8 pin determines whether the digital output data is to be organized as two 8-bit words
12/
4 DI Byte Address/Short Cycle. If a conversion is started with A0 Active LOW, a full 12-bit conversion
cycle is initiated. If A
results. During Read (R/
and A
= HIGH enables DB3-DB0 and sets DB7-DB4 = 0.
0
is Active HIGH during a convert start, a shorter 8-bit conversion cycle
0
C = 1) with 12/8 LOW, A0 = LOW enables the 8 most significant bits,
Common for unipolar operation.
8 and A0 pins), these pins provide the upper
4 bits of data. In the 8-bit format, they provide the upper 4 bits when A
disabled when A
8-bit format they provide the middle 4 bits when A
data when A
is HIGH.
0
is LOW and all zeroes when A0 is HIGH.
0
is HIGH; they are disabled when A0 is LOW.
0
for a convert operation. In the stand-alone mode, the falling edge of R/
is LOW and are
0
C initiates a conversion.
completed.
7 P +12 V/+15 V Analog Supply.
11 P –12 V/–15 V Analog Supply.
1 P +5 V Logic Supply.
13 AI 10 V Span Input, 0 to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the
20 V Span, 10 V
should not be connected.
IN
14 AI 20 V Span Input, 0 to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using the
10 V Span, 20 V
should not be connected.
IN
(12/8 LOW) or a single 12-bit word (12/8 HIGH).
TYPE: AI = Analog Input
AO = Analog Output
DI = Digital Input
DO = Digital Output
P = Power
REV. B
PIN CONFIGURATION
V
LOGIC
12/8
CS
A
R/C
CE
V
CC
REF OUT
AGND
REF IN
V
EE
BIP OFF
10V
IN
20V
_
__
0
_
IN
1
2
3
4
5
AD674B
6
AD774B
7
8
9
(Not to Scale)
10
11
12
13
14
TOP VIEW
or
28
27
26
25
24
23
22
21
20
19
18
17
16
15
–7–
STS
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DGND
AD674B/AD774B
CIRCUIT OPERATION
The AD674B and AD774B are complete 12-bit monolithic A/D
converters which require no external components to provide the
complete successive-approximation analog-to-digital conversion
function. A block diagram is shown in Figure 5.
+5V SUPPLY
V
LOGIC
DATA MODE SELECT
CHIP SELECT
BYTE ADDRESS/
SHORT CYCLE
READ/ CONVERT
R/C
CHIP ENABLE
+12/+15V SUPPLY
V
+10V REFERENCE
REF OUT
ANALOG COMMON
REFERENCE INPUT
REF IN
_
_
12/ 15V SUPPLY
V
BIPOLAR OFFSET
BIPOFF
10V SPAN INPUT
10V
20V SPAN INPUT
20V
1
2
12/8
3
CS
4
A
0
5
6
CE
7
CC
8
9
AC
10
11
EE
12
13
IN
14
IN
19.95k
10V
REF
VOLTAGE
DIVIDER
CONTROL
CLOCK
DAC
REF
I
SAR
COMP
I
N
12
AD674B/AD774B
DAC
MSB
3
S
T
A
T
E
12
O
U
T
P
12
U
T
B
U
F
F
E
R
S
V
EE
LSB
28
27
N
Y
B
26
B
L
25
E
A
24
N
23
Y
B
22
B
L
E
21
B
20
N
19
Y
B
18
B
L
E
17
C
16
15
STATUS
STS
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DIGITAL COMMON DC
DIGITAL
DATA
OUTPUTS
Figure 5. Block Diagram of AD674B and AD774B
When the control section is commanded to initiate a conversion
(as described later), it enables the clock and resets the
successive-approximation register (SAR) to all zeroes. Once a
conversion cycle has begun, it cannot be stopped or restarted
and data is not available from the output buffers. The SAR,
timed by the clock, will sequence through the conversion cycle
and return an end-of-convert flag to the control section. The
control section will then disable the clock, bring the output
status flag low, and enable control functions to allow data read
by external command.
During the conversion cycle, the internal 12-bit current output
DAC is sequenced by the SAR from the most-significant-bit
(MSB) to least-significant-bit (LSB) to provide an output current which accurately balances the input signal current through
the divider network. The comparator determines whether the
addition of each successively-weighted bit current causes the
DAC current sum to be greater or less than the input current; if
the sum is less, the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12-bit binary code
which accurately represents the input signal to within ± 1/2 LSB.
The temperature-compensated reference provides the primary
voltage reference to the DAC and guarantees excellent stability
with both time and temperature. The reference is trimmed to
10.00 volts ±1%; it can supply up to 2.0 mA to an external load
in addition to the requirements of the reference input resistor
(0.5 mA) and bipolar offset resistor (0.5 mA). Any external load
on the reference must remain constant during conversion. The
thin film application resistors are trimmed to match the fullscale
output current of the DAC. The input divider network provides
a 10 V or 20 V input range. The bipolar offset resistor is
grounded for unipolar operation and connected to the 10 volt
reference for bipolar operation.
DRIVING THE ANALOG INPUT
The AD674B and AD774B are successive-approximation analogto-digital converters. During the conversion cycle, the ADC
input current is modulated by the DAC test current at approxi-
mately a 1 MHz rate. Thus it is important to recognize that the
signal source driving the ADC must be capable of holding a
constant output voltage under dynamically-changing load
conditions.
Figure 6. Op Amp—ADC Interface
The closed-loop output impedance of an op amp is equal to the
openloop output impedance (usually a few hundred ohms) divided by the loop gain at the frequency of interest. It is often
assumed that the loop gain of a follower-connected op amp is
sufficiently high to reduce the closed-loop output impedance to
a negligibly small value, particularly if the signal is low frequency. However, the amplifier driving the ADC must either
have sufficient loop gain at 1 MHz to reduce the closed-loop
output impedance to a low value or have low open-loop output
impedance. This can be accomplished by using a wideband op
amp, such as the AD711.
If a sample-hold amplifier is required, the monolithic AD585 or
AD781 is recommended, with the output buffer driving the
AD674B or AD774B input directly. A better alternative is the
AD1674 which is a 10 µs sampling ADC in the same pinout
as the AD574A, AD674A or AD774B and is functionally
equivalent.
SUPPLY DECOUPLING AND LAYOUT
CONSIDERATION
It is critically important that the power supplies be filtered, well
regulated, and free from high frequency noise. Use of noisy supplies will cause unstable output codes. Switching power supplies
are not recommended for circuits attempting to achieve 12-bit
accuracy unless great care is used in filtering any switching
spikes present in the output. Few millivolts of noise represent
several counts of error in a 12-bit ADC.
Decoupling capacitors should be used on all power supply pins;
the +5 V supply decoupling capacitor should be connected directly from Pin 1 to Pin 15 (digital common) and the +V
–V
pins should be decoupled directly to analog common (Pin
EE
CC
and
9). A suitable decoupling capacitor is a 4.7 µF tantalum type in
parallel with a 0.1 µF ceramic disc type.
Circuit layout should attempt to locate the ADC, associated
analog input circuitry, and interconnections as far as possible
from logic circuitry. For this reason, the use of wire-wrap circuit
construction is not recommended. Careful printed-circuit layout
and manufacturing is preferred.
REV. B–8–
AD674B/AD774B
UNIPOLAR RANGE CONNECTIONS FOR THE AD674B
AND AD774B
The AD674B and AD774B contain all the active components
required to perform a complete 12-bit A/D conversion. Thus,
for most situations, all that is necessary is connection of the
power supplies (+5 V, +12/+15 V and –12/–15 V), the analog
input, and the conversion initiation command, as discussed on
the next page.
Figure 7. Unipolar Input Connections
All of the thin-film application resistors of the AD674B and
AD774B are factory trimmed for absolute calibration. Therefore, in many applications, no calibration trimming will be required. The absolute accuracy for each grade is given in the
specification tables. For example, if no trims are used, ±2 LSB
max zero offset error and ±0.25% (10 LSB) max full-scale error
are guaranteed. If the offset trim is not required, Pin 12 can be
connected directly to Pin 9; the two resistors and trimmer for
Pin 12 are then not needed. If the full-scale trim is not required,
a 50 Ω 1% metal film resistor should be connected between Pin
8 and Pin 10.
If Pin 12 is connected to Pin 9, the unit will behave in this manner, within specifications. If the offset trim (R1) is used, it
should be trimmed as above, although a different offset can be
set for a particular system requirement. This circuit will give approximately ±15 mV of offset trim range.
The full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 for a 10 V range). Trim R2 to
give the last transition (1111 1111 1110 to 1111 1111 1111).
BIPOLAR OPERATION
The connections for bipolar ranges are shown in Figure 8.
Again, as for the unipolar ranges, if the offset and gain specifications are sufficient, one or both of the trimmers shown can be
replaced by a 50 Ω ±1% fixed resistor. The analog input is
applied as for the unipolar ranges. Bipolar calibration is similar
to unipolar calibration. First, a signal 1/2 LSB above negative
full scale (–4.9988 V for the ± 5 V range) is applied and R1 is
trimmed to give the first transition (0000 0000 0000 to 0000
0000 0001). Then a signal 1 1/2 LSB below positive full scale
(+4.9963 V for the ±5 V range) is applied and R2 trimmed to
give the last transition (1111 1111 1110 to 1111 1111 1111).
The analog input is connected between Pins 13 and 9 for a 0 to
+10 V input range, between Pins 14 and 9 for a 0 to +20 V input range. Input signals beyond the supplies are easily accommodated. For the 10 volt span input, the LSB has a nominal
value of 2.44 mV; for the 20 volt span, 4.88 mV. If a 10.24 V
range is desired (nominal 2.5 mV/bit), the gain trimmer (R2)
should be replaced by a 50 Ω resistor, and a 200 Ω trimmer inserted in series with the analog input to Pin 13 (for a full-scale
range of 20.48 V (5 mV/bit), use a 500 Ω trimmer into Pin 14).
The gain trim described below is now done with these trimmers.
The nominal input impedance into Pin 13 is 5 kΩ, and 10 kΩ
into Pin 14.
UNIPOLAR CALIBRATION
The connections for unipolar ranges are shown in Figure 7. The
AD674B or AD774B is trimmed to a nominal 1/2 LSB offset so
that the exact analog input for a given code will be in the middle
of that code (halfway between the transitions to the codes above
and below it). Thus, when properly calibrated, the first transition (from 0000 0000 0000 to 0000 0000 0001) will occur for
an input level of +1/2 LSB (1.22 mV for 10 V range).
REV. B
–9–
Figure 8. Bipolar Input Connections
GROUNDING CONSIDERATIONS
The analog common at Pin 9 is the ground reference point for
the internal reference and is thus the “high quality” ground for
the ADC; it should be connected directly to the analog reference point of the system. In order to achieve the high accuracy
performance available from the ADC in an environment of high
digital noise content, it is required that the analog and digital
commons be connected together at the package. In some situations, the digital common at Pin 15 can be connected to the
most convenient ground reference point; digital power return is
preferred.
AD674B/AD774B
CE
CS
R/C
A
12/8
VALUE OF A AT LAST CONVERT COMMAND
D
EN
R
Q
S
0
READ
Q
D
EN
0
START CONVERT
Q
S
QB
R
HIGH IF CONVERSION
IN PROGRESS
EOC 12
EOC 8
SAR
RESET
CLK EN
STATUS
NYBBLE A
ENABLE
NYBBLE B
ENABLE
NYBBLE C
ENABLE
NYBBLE B = 0
ENABLE
TO
OUTPUT
BUFFERS
Figure 9. Equivalent Internal Logic Circuitry
CONTROL LOGIC
The AD674B and AD774B contain on-chip logic to provide
conversion initiation and data read operations from signals
commonly available in microprocessor systems; this internal
logic circuitry is shown in Figure 9.
The control signals CE,
the converter. The state of R/
serted determines whether a data read (R/
(R/
C = 0) is in progress. The register control inputs A0 and
12/
8 control conversion length and data format. If a conversion
is started with A
If A
is high during a convert start, a shorter 8-bit conversion
0
0
cycle results. During data read operations, A
CS, and R/C control the operation of
C when CE and CS are both as-
C = 1) or a convert
low, a full 12-bit conversion cycle is initiated.
determines
0
whether the three-state buffers containing the 8 MSBs of the
conversion result (A
The 12/
8 pin determines whether the output data is to be organized as two 8-bit words (12/
or a single 12-bit word (12/
the byte addressed when A
= 0) or the 4 LSBs (A0 = 1) are enabled.
0
8 tied to DIGITAL COMMON)
8 tied to V
is high contains the 4 LSBs from
0
). In the 8-bit mode,
LOGIC
the conversion followed by four trailing zeroes. This organization allows the data lines to be overlapped for direct interface to
8-bit buses without the need for external three-state buffers.
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
Table I. Truth Table
CE CS R/C 12/8 A0Operation
0XXXXNone
X 1 X X X None
1 0 0 X 0 Initiate 12-Bit Conversion
1 0 0 X 1 Initiate 8-Bit Conversion
1011XEnable 12-Bit Parallel Output
10100Enable 8 Most Significant Bits
10101Enable 4 LSBs +4 Trailing Zeroes
The ADC may be operated in one of two modes, the full-control
mode and the stand-alone mode. The full-control mode utilizes
all the control signals and is useful in systems that address decode multiple devices on a single data bus. The stand-alone
mode is useful in systems with dedicated input ports available.
In general, the stand-alone mode is capable of issuing start-convert commands on a more precise basis and, therefore, produces
higher accuracy results. The following sections describe these
two modes in more detail.
FULL-CONTROL MODE
Chip Enable (CE), Chip Select (CS) and Read/Convert (R/C)
are used to control Convert or Read modes of operation. Either
CE or
CS may be used to initiate a conversion. The state of R/C
REV. B–10–
AD674B/AD774B
DB11
(MSB)
DB10 DB9 DB8 DB7
DB6 DB5
DB4
DB3 DB2
DB1
DB0
(LSB)
0
000
D0D7
XXX0
(EVEN ADDR)
XXX1
(ODD ADDR)
when CE and CS are both asserted determines whether a data
Read (R/
should be LOW before both CE and
C = 1) or a Convert (R/C = 0) is in progress. R/C
CS are asserted; if R/C is
HIGH, a Read operation will momentarily occur, possibly resulting in system bus contention.
STAND-ALONE MODE
“Stand-alone” mode is useful in systems with dedicated input
ports available and thus not requiring full bus interface capability. Stand-alone mode applications are generally able to issue
conversion start commands more precisely than full-control
mode, resulting in improved accuracy.
CE and 12/
conversion is controlled by R/
abled when R/
8 are wired HIGH, CS and A0 are wired LOW, and
C. The three-state buffers are en-
C is HIGH and a conversion starts when R/C
goes LOW. This gives rise to two possible control signals—a
high pulse or a low pulse. Operation with a low pulse is shown
in Figure 4a. In this case, the outputs are forced into the high
impedance state in response to the falling edge of R/
C and return to valid logic levels after the conversion cycle is completed.
The STS line goes HIGH 200 ns after R/
C goes LOW and re-
turns low 600 ns after data is valid.
If conversion is initiated by a high pulse as shown in Figure 4b,
the data lines are enabled during the time when R/
The falling edge of R/
C starts the next conversion, and the data
C is HIGH.
lines return to three-state (and remain three-state) until the next
high pulse of R/
CONVERSION TIMING
C.
Once a conversion is started, the STS line goes HIGH. Convert
start commands will be ignored until the conversion cycle is
complete. The output data buffers can be enabled up to 1.2 µs
prior to STS going LOW. The STS line will return LOW at the
end of the conversion cycle.
The register control inputs, A
length and data format. If a conversion is started with A
a full 12-bit conversion cycle is initiated. If A
and 12/8, control conversion
0
is HIGH during a
0
LOW,
0
convert start, a shorter 8-bit conversion cycle results.
During data read operations, A
determines whether the three-
0
state buffers containing the 8 MSBs of the conversion result
(A
= 0) or the 4 LSBs (A0 = 1) are enabled. The 12/8 pin de-
0
termines whether the output data is to be organized as two 8-bit
words (12/
HIGH). In the 8-bit mode, the byte addressed when A
8 tied LOW) or a single 12-bit word (12/8 tied
is high
0
contains the 4 LSBs from the conversion followed by four trailing zeroes. This organization allows the data lines to be overlapped for direct interface to 8-bit buses without the need for
external three-state buffers.
GENERAL A/D CONVERTER INTERFACE
CONSIDERATIONS
A typical A/ D converter interface routine involves several operations. First, a write to the ADC address initiates a conversion. The processor must then wait for the conversion cycle to
complete, since most integrated circuit ADCs take longer than
one instruction cycle to complete a conversion. Valid data can,
of course, only be read after the conversion is complete. The
AD674B and AD774B provide an output signal (STS) which
indicates when a conversion is in progress. This signal can be
polled by the processor by reading it through an external threestate buffer (or other input port). The STS signal can also be
used to generate an interrupt upon completion of conversion if
the system timing requirements are critical and the processor
has other tasks to perform during the ADC conversion cycle.
Another possible time-out method is to assume that the ADC
will take its maximum conversion time to convert, and insert a
sufficient number of “no-op” instructions to ensure that this
amount of processor time is consumed.
Once conversion is complete, the data can be read. For converters with more data bits than are available on the bus, a choice of
data formats is required, and multiple read operations are
needed. The AD674B and AD774B include internal logic to
permit direct interface to 8-bit and 16-bit data buses, selected
by the 12/
8 input. In 16-bit bus applications (12/8 high) the
data lines (DB11 through DB0) may be connected to either the
12 most significant or 12 least significant bits of the data bus.
The remaining four bits should be masked in software. The interface to an 8-bit data bus (12/
format. The even address (A
through DB4). The odd address (A
8 low) is done in a left-justified
low) contains the 8 MSBs (DB11
0
high) contains the 4 LSBs
0
(DB3 through DB0) in the upper half of the byte, followed by
four trailing zeroes, thus eliminating bit masking instructions.
It is not possible to rearrange the output data lines for right-justified 8-bit bus interface.
Figure 10. Data Format for 8-Bit Bus
REV. B
–11–
AD674B/AD774B
0.085
(2.16)
0.017 0.003
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Ceramic DIP Package (D-28)
0.050 (12.83)
28
1
(0.43)
1.42 (36.07)
1.40 (35.56)
+
0.1 (2.54)
–
+
0.047 0.007
–
(1.19)
15
14
0.095 (2.41)
0.59
+
0.01
–
(14.98)
28-Lead Plastic DIP Package (N-28A)
0.050
+
0.010
–
(1.27)
30
SEATING
PLANE
o
0.08 (2.0)
0.125 MIN (3.17)
+
0.010 0.002
–
+
(0.254 0.05)
–
0.6 (15.24)
0.05 (1.27)
0.045 (1.14)
0.145 0.02
(3.68)
C1536–24–7/91
+
–
28
1
0.200
(5.080)
MAX
0.020 (0.508)
0.015 (0.381)
LEADS ARE SOLDER DIPPED OR TIN - PLATED ALLOY 42 OR COPPER.
1.450 (36.83)
1.440 (36.576)
0.105 (2.67)
0.095 (2.41)
0.065 (1.65)
0.045 (1.14)
15
14
0.175 (4.45)
0.120 (3.05)
0.550 (13.97)
0.530 (13.462)
0.606 (15.39)
0.594 (15.09)
0.012 (0.305)
0.008 (0.203)
0.160 (4.06)
0.140 (3.56)
o
15
o
0
PRINTED IN U.S.A.
REV. B–12–
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