Analog Devices AD6426XST, AD6426XB Datasheet

a

Enhanced GSM Processor

Preliminary Technical Information

FEATURES Complete Single Chip GSM Processor Channel Codec Subsystem including

Channel Coder/Decoder Interleaver/De-interleaver Encryption/Decryption

Control Processor Subsystem including

16-bit Control Processor (H8/300H) Parallel and Serial Display Interface Keypad Interface EEPROM Interface SIM-Interface Universal System Connector Interface Interface to AD6425 Control of Radio Subsystem Programmable backlight duty cycle Real Time Clock with Alarm Battery ID Chip Interface

DSP Subsystem including

16-bit DSP with ROM coded firmware for Full rate Speech Encoding/Decoding (GSM 06.10) Enhanced Full Rate Speech

Encoding/Decoding (GSM 06.60) Equalization with 16-state Viterbi (Soft Decision) DTMF and Call Progress Tone Generation

Power Management of Mobile Radio Slow Clocking scheme for low Idle Mode current Ultra Low Power Design On-chip GSM Data Services up to 14.4 kbit/s JTAG Test Interface

2.4V to 3.3V Operating Voltage 144-Lead LQFP and 144-Lead PBGA packages

APPLICATIONS GSM 900 / DCS1800 / PCS1900 Mobile Stations (MS) Compliant to Phase 1 and Phase 2 specifications

GENERAL DESCRIPTION

The AD6426 Enhanced GSM Processor (EGSMP) is the central component of the highly integrated AD20msp425 GSM Chipset. Offering a low total chip count, low bill of materials cost and long talk and standby times, the chipset offers designers a straightforward route to a highly competitive product in the GSM/DCS1800 market.

The EGSMP performs all the baseband functions of the Layer 1 processing of the GSM air interface. This includes all data encoding and decoding processes as well as timing and radio sub-system control functions.

The EGSMP supports full rate and enhanced full rate speech traffic as well as a full range of data services including F14.4.

In addition, the EGSMP supports both A5/1 and A5/2 encryption algorithms as well as operation in non-encrypted mode.

The EGSMP integrates a high performance 16-bit microprocessor (Hitachi H8/300H), that supports all the GSM terminal software, including Layer 1, 2 and 3 of the GSM protocol stack, the MMI and applications software such as data services, test and maintenance.

The use of the standard H8 processor allows the use of HIOS, the Hitachi real time kernel, as well as a full range of software development tools including C compilers, debuggers and incircuit emulators. The EGSMP also integrates a high performance 16-bit Digital Signal Processor (DSP), which provides speech transcoding and supports all audio functions in both transmit and receive. In receive it equalizes the received signal using a 16-state (Viterbi) soft decision equalizer.

The EGSMP interfaces with all the peripheral sub-systems of the terminal, including the keypad, memories, display driver, SIM, DTE and DTA data services interface and radio. It also has a general purpose interface that can be used to support an external connection to a car kit or battery charger.

The EGSMP interfaces with the AD6425 or the AD6421 Voiceband/Baseband Codec through a dedicated serial port.

ORDERING GUIDE

UNIVERSAL

SYSTEM CONN.

INTERFACE

TEST

INTERFACE

SIM

INTERFACE

EEPROM

INTERFACE

MEMORY

INTERFACE

Figure 1. Functional Block Diagram

Model Temperature Range Package AD6426XST -25°C to +85°C 144-Lead LQFP

AD6426XB -25°C to +85°C 144-Lead PBGA

CHANNEL

CODEC

DSP

CHANNEL

EQUALIZER

SPEECH

CODEC

CONTROL

PROCESSOR

AD6426

VOICEBAND /

BASEBAND

CODEC

INTERFACE

DISPLAY

INTERFACE

RADIO

INTERFACE

ACCESSORY

INTERFACE

KEYPAD / BACKLIGHT INTERFACE

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98) - 1 - Confidential Information

Preliminary Technical Information

AD6426

USCRI

SYSTEM

CONNECTOR

ACCESSORY

SIM

EEPROM

BACKLIGHT BACKLIGHT

KEYPAD

FLASH

ROM

SRAM

DISPLAY

POWER

SUB-

SYSTEM

USCRX USCTX USCCTS USCRTS

GPIO [9:0] GPCS GPPWRCTL

SIMCARD SIMDATAOP SIMDATAIP SIMCLK SIMRESET SIMPROG SIMSUPPLY

EEPROMEN EEPROMDATA EEPROMCLK

KEYPADROW [5:0] KEYPADCOL [3:0]

FLASHPWD ROMCS ADD [20:0] DATA [15:0]

RAMCS

RD WR HWR LWR

LCDCTL DISPLAYCS

VDDRTC PWRON

IRQ6 RESET BOOTCODE

ENHANCED

GSM

PROCESSOR

AD6426

VDD(10) GND(10)

CLKIN

OSC13MON

OSCIN

OSCOUT JTAGEN

TCK TMS

TDI

TDO

CLKOUT

VBCRESET

ASDO

ASOFS

ASCLK

ASDI

BSDO

BSOFS

BSCLK

BSDI

BSIFS

VSDO

VSDI

VSCLK

VSFS

RXON

TXENABLE

TXPHASE

TXPA

CALIBRATERADIO

RADIOPWRCTL

SYNTHEN0 SYNTHEN1

SYNTHDATA

SYNTHCLK

AGCA AGCB

VCTCXO

JTAG

PORT

VBC / EVBC AD6421 / 25

MCLK RESET

ASDI ASDIFS ASDOFS ASCLK ASDO

BSDI BSDIFS BSCLK BSDO BSDOFS

MODE

VSDI VSDO VSCLK VSFS

RXON TXON

RADIO

Figure 2. External Interfaces of the AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98) - 2 - Confidential Information

Preliminary Technical Information

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98) - 3 - Confidential Information

Preliminary Technical Information

PIN FUNCTIONALITY ( Normal Mode)

Group Pin Name Pins I/O Default / Alternative Function(s) *

General CLKIN 1 I 13 MHz Clock Input

RESET 1 I Reset input IRQ6 1 I / I Interrupt Request # 6 / Non-Maskable Interrupt (NMI) * OSC13MON 1 O 13 MHz Oscillator Power Control Signal BOOTCODE 1 I Boot Code Enable VDD 10 Supply Voltage

GND 10 Ground Memory ADD19 : 0 20 O Processor Address Bus Interface GPO10 1 O / O General Purpose Output 10 / Address (20) *

DATA15 : 0 16 I/O Processor Data Bus

RD 1 O Processor Read Strobe

HWR 1 O Processor High Write Strobe / Upper Byte Strobe

LWR 1 O Processor Low Write Strobe / Lower Byte Strobe

WR 1 O Processor Write Strobe

FLASHPWD 1 O / I /OFLASH Power Down / WAIT / General Purpose Output

11* RAMCS 1 O External RAM Chip Select ROMCS 1 O External ROM Chip Select

SIM SIMCARD 1 I /

I/O

Interface SIMDATAOP 1 O SIM Data Output

SIMDATAIP 1 I SIM Data Input SIMCLK 1 O SIM Clock SIMRESET 1 O SIM Reset SIMPROG 1 O /

I/O

SIMSUPPLY 1 O SIM Supply Enable

EEPRROM EEPROMDATA 1 I/O EEPROM Data Interface EEPROMCLK 1 O EEPROM Clock / High Speed Logger Clock

EEPROMEN 1 O EEPROM Enable / High Speed Logger Frame Sync

Display / DISPLAYCS 1 O Display Controller Chip Select / Chip Enable Backlight / LCDCTL 1 O LCD Control / Serial Display Data Output Keypad BACKLIGHT 1 O Backlight Control Interface KEYPADROW5 : 0 6 I Keypad Row Inputs

KEYPADCOL3 : 0 4 O Keypad Column Strobes (open drain, pull low)

SIM Card Detect / General Purpose I/O 16 *

SIM Program Enable / General Purpose I/O 15 *

AD6426

* Note: Functionality of these pins can be changed under software control.

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98) - 4 - Confidential Information

Preliminary Technical Information

Pin Functionality ( NORMAL MODE)

Group Pin Name Pins I/O Default / Alternative Function(s) *

EVBC Interface CLKOUT 1 O Clock Output to EVBC

EVBCRESET 1 O EVBC Reset Output (also for Display reset)

ASPORT ASDO 1 O EVBC Auxiliary Serial Port Data Output

ASOFS 1 O EVBC Auxiliary Serial Port Output Framing Signal ASCLK 1 O EVBC Auxiliary Serial Port Clock Output ASDI 1 I EVBC Auxiliary Serial Port Data Input

BSPORT BSDO 1 O EVBC Baseband Serial Port Data Output

BSOFS 1 O EVBC Baseband Serial Port Output Framing Signal BSCLK 1 I EVBC Baseband Serial Port Clock Input BSDI 1 I EVBC Baseband Serial Port Data Input BSIFS 1 I EVBC Baseband Serial Port Input Framing Signal

VSPORT VSDO 1 O EVBC Voiceband Serial Port Data Output

VSDI 1 I EVBC Voiceband Serial Port Data Input VSCLK 1 I EVBC Voiceband Serial Port Clock Input VSFS 1 I EVBC Voiceband Serial Port Framing Signal

Radio Interface RXON 1 O Receiver On

TXPHASE 1 O Switches between Rx and Tx TXENABLE 1 O Transmit Enable / General Purpose Output 14 * TXPA 1 O / O Power Amplifier Enable / General Purpose Output 12 * CALIBRATERADIO 1 O / O Radio Calibration / General Purpose Output 13 * RADIOPWRCTL 1 O Radio Power-Down Control SYNTHEN0 1 O Synthesizer 1 Enable SYNTHEN1 1 O Synthesizer 2 Enable / General Purpose Output 17 * SYNTHDATA 1 O RF Serial Port Data SYNTHCLK 1 O RF Serial Port Clock AGCA 1 O AGC Gain Select / General Purpose Output 18 AGCB 1 O AGC Gain Select / General Purpose Output 19

Universal USCRI 1 1/O USC Ring Indicator / Serial Clock / GPO20 System USCRX 1 I USC Receive Data Connector USCTX 1 O USC Transmit Data / Baseband Serial Port Data Input Interface USCCTS 1 I/O USC Clear to Send / Serial Frame Sync / GPI22

USCRTS 1 O USC Ready to Send / GPO21

AD6426

* Note: Functionality of these pins can be changed under software control.

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Preliminary Technical Information

Pin Functionality ( NORMAL MODE)

Group Pin Name Pins I/O Default / Alternative Function(s) *

Accessory GPIO0 1 I/O General Purpose Inputs/Output 0 Interface GPIO1 1 I/O General Purpose Inputs/Output 1 / Radio BANDSELECT1

* GPIO2 1 I/O General Purpose Inputs/Output 2 / Radio BANDSELECT0

* GPIO3 1 I/O General Purpose Inputs/Outputs 3 / Serial Display Address

Output * GPIO4 1 I/O General Purpose Inputs/Outputs 4 / Serial Display Clock

Output * GPIO5 1 I/O General Purpose Inputs/Outputs 5 / Battery ID Interface * GPIO6 1 I/O General Purpose Inputs/Output 6 / VBIAS * GPIO7 1 I/O General Purpose Inputs/Output 7 / Antenna Select * GPIO8 1 I/O General Purpose Inputs/Output 8 / DEBUG UART

Transmit Data * GPIO9 1 I/O General Purpose Inputs/Output 9 / DEBUG UART

Receive Data * GPCS 1 O General Purpose Chip Select

Real Time OSCIN 1 I 32.768 kHz Crystal Input Clock OSCOUT 1 O 32.768 kHz Oscillator Output and Feedback to Crystal Interface VDDRTC 1 RTC Supply Voltage

PWRON 1 O Power ON/OFF Control

Test Interface JTAGEN 1 I JTAG Enable

TCK 1 I JTAG Test Clock / HSL Data 0 TMS 1 I JTAG Test Mode Select / HSL Data 1 / DAI Reset TDI 1 I JTAG Test Data Input / HSL Data 3 / DAI Data 1 TDO 1 O JTAG Test Data Output / HSL Data 2 / DAI Data 0

AD6426

* Note: Functionality of these pins can be changed under software control.

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Preliminary Technical Information

AD6426

OVERVIEW

The GSM air interface has been formulated to provide high quality digital mobile communication. As well as supporting the traffic channels (speech and/or data), the air interface specifies a number of signaling channels that are used for call set up and communications between the network infrastructure and the mobile. These signaling channels provide the mobile specific features such as handover, as well as a number of other intelligent features.

The GSM system closely follows the OSI 7-layer model for communications. Specifically, GSM defines Layers 1, 2 and 3 of the protocols. The lowest level being Layer 1, or the Physical Layer. It is this part of the network processing for which the EGSMP is responsible, performing some of the Layer 1 functions in dedicated hardware for minimum power consumption and some in software for increased flexibility.

Layer 1 covers those signal processing functions required to format the speech/data for transmission on the physical medium. Data must be structured to allow for identification, recovery and error correction so that the information can be supplied error free to the layer 2 sub-systems and to the traffic sources. In addition, the physical layer processing includes the timing of both transmit and receive data, the encryption of data for security purposes and the control of the Radio subsystem to provide timing and to optimize the radio frequency characteristics. An object code license to Layer 1 software is supplied with the AD20msp425 chipset.

FUNCTIONAL PARTITIONING

This datasheet gives only an overview about the functionality of the EGSMP. The EGSMP consists of three main elements; the Channel Codec and the Control Processor Sub-System including several interfaces and the DSP as shown in Figure

1. The Channel Codec is responsible for the Layer 1 channel

coding and decoding of traffic and control information. The Processor Sub-system supports the software functions of the protocol stack and interfaces with the bus peripheral subsystems of the terminal. The DSP performs the channel equalization and speech transcoding.

Channel Codec Sub-System

The Channel Codec processes data from two principal sources; traffic and signaling. The former is normally continuous and the latter determined on demand. Traffic comes in two forms; speech and user data. The various traffic sources and the signaling sources are all processed differently at the physical layer. Speech traffic data is supplied by the speech transcoder and the remaining data types are sourced from the Control Processor and interfaced via a dedicated data interface. The Channel Codec subsystem functional block diagram is shown in Figure 3.

DSP

INTERFACE

REGISTERS

DECODE

H8

INTERFACE

INTERLEAVEENCODE

DEINTERLEAVE

RADIO / SYNTHESIZER TIMING AND CONTROL

ENCRYPT

DECRYPT

VBC

INTERFACE

TEST

INTERFACE

Figure 3. Channel Codec Subsystem

The transmit and receive functions of the Channel Codec are timed by an internal timebase that maintains accurate timing of all sub-systems. This timebase is aligned with the on-air receive signal and all system control signals, both internal and external, are derived from it.

The physical layer processing can be divided into 4 phases, two each for up- and downlink. The data in the transmit path undergoes an ENCODE phase and then a TRANSMIT phase. Similarly, data in the downlink path is termed the receive data and it undergoes a RECEIVE phase followed by a DECODE phase. The buffer between the ENCODE and TRANSMIT functions is the INTERLEAVE module that holds the data and permits the building of the transmit burst structure. Similarly the DEINTERLEAVE module forms the buffer between the RECEIVE and the DECODE processes.

Each of these four phases is controlled explicitly by the Control Processor via control registers that define the mode of operation of each sub-module and the data source they should process. Typically these control values are updated every TDMA frame in response to interrupts from the internal timebase.

The ENCODE process involves the incorporation of error protection codes. All data is sourced in packets and two forms of error coding applied; block coding (parity or Fire code) and convolution coding. The resultant data block is then written to the INTERLEAVE module where it is buffered in a RAM. Data is read from the interleave buffer memories contiguously but written in non-contiguous manner, thereby implementing the interleaving function. The TRANSMIT process uses a different time structure now associated with the on-air TDMA structure. The data is read from the INTERLEAVE module and formatted into bursts with the requisite timing. This involves adding fixed patterns such as the tail bits and training sequence code. The resultant burst is written to the external Baseband Converter where the modulation is performed and the output timed to the system timebase before transmission.

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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AD6426

A feature of the GSM system is the application, as part of the TRANSMIT process, of data encryption for the purpose of link security. After the INTERLEAVE module the data may be encrypted using the prescribed A5/1 or A5/2 encryption algorithm.

The RECEIVE function requires unmodulated baseband data from the equalizer. As necessary the data is decrypted and written to the DEINTERLEAVE module. This is conducted at TDMA frame rate, although precise timing is not necessary at this stage.

The DECODING process reads data from the DEINTERLEAVE module, inverting the interleave algorithm and decodes the error control codes, correcting and flagging errors as appropriate. The data also includes a measure of confidence expressed as two additional bits per received symbol. These are used in the convolution decoder to improve the error decoding performance. The resultant data is then presented to the original sources as determined by the control programming. The Channel Codec interfaces with the speech transcoder for speech traffic data and with an equalizer for recovered receive data. In the AD6426 the equalizer and speech transcoder are implemented in the DSP.

Processor Sub-System

The Processor Sub-System consists of a high performance 16bit microcontroller together with a selection of peripheral elements. The processor is a version of the Hitachi H8/300H that has been developed to support GSM applications and which is well suited to support the Protocol Stack and Application Layer software.

DSP Sub-System

The DSP Sub-System consists of a high performance 16-bit digital signal processor (DSP) with integrated RAM and ROM memories. The DSP performs two major tasks: speech transcoding and channel equalization. Additionally several support functions are performed by the DSP. The instruction code, which advises the DSP to perform these tasks, is stored in the internal ROM. The DSP sub-system is completely selfcontained, no external memory or user-programming is necessary.

Speech Transcoding

In Full Rate mode the DSP receives the speech data stream from the EVBC and encodes the data from 104 kbit/s to 13 kbit/s. The algorithm used is Regular Pulse Excitation, with Long Term Prediction (RPE-LTP) as specified in the 06-series GSM Recommendations.

In Enhanced Full Rate mode, the DSP encodes the 104 kbit/s speech data into 12.2 kbit/s (speech) +0.8 kbit/s (CRC and repetition bits) as additionally specified in the Phase 2 version of the 06-series GSM Recommendations. In both modes, the DSP also performs the appropriate voice activity detection and discontinuous transmission (VAD/DTX) functions.

Alternatively the DSP receives encoded speech data from the channel codec sub-system including the Bad Frame Indicator (BFI). The Speech decoder supports a Comfort Noise Insertion (CNI) function that inserts a predefined silence descriptor into the decoding process. The resulting data, at 104 kbit/s, is transferred to the EVBC.

Equalization

The Equalizer recovers and demodulates the received signal and establishes local timing and frequency references for the mobile terminal as well as RSSI calculation. The equalization algorithm is a version of the Maximum Likelihood Sequence Estimation (MLSE) using the Viterbi algorithm. Two confidence bits per symbol provide additional information about the accuracy of each decision to the channel codec’s convolutional decoder. The equalizer outputs a sequence of bits including the confidence bits to the channel codec subsystem.

Audio Control

The DSP subsystem is also responsible for the control of the audio path. The EVBC provides two audio inputs and two audio outputs, as well as a separate buzzer output, which are switched and controlled by the DSP. Furthermore the EVBC provides for variable gain and sensitivity which is also controlled by the DSP under command of the Layer 1 software.

Tone Generation

All alert signals are generated by the DSP and output to the EVBC. These alerts can be used for the buzzer or for the earpiece. The tones used for alert signals can be fully defined by the user by means of a description which provides all the parameters required such as frequency content and duration of components of the tone. The tone descriptions are provided by the Layer 1 software.

Automatic Frequency Control (AFC)

The detection of the frequency correction burst provides the frequency offset between the mobile terminal and the received signal. This measure is supplied to the Layer 1 software which then requests a correction of the master clock oscillator frequency via the AFC-DAC in the EVBC. In order to do so the Layer 1 software includes a transfer function for the oscillator frequency against the voltage applied. The DSP provides the measurements for the AFC.

Automatic Gain Control (AGC)

The DSP is also responsible for making measurements of the power in the received signal. This is used for a number of functions including RSSI measurement, adjacent channel monitoring and AGC. The Layer 1 software passes the requested gain level to the DSP, which then analyzes the received signal and generates an AGC control signal. Depending on the radio architecture, this control signal will be used in digital form or, converted by the AD6425 in analog form.

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Preliminary Technical Information

AD6426

REGISTERS

The AD6426 contains 88 Channel Codec Control Registers, 69 H8 Peripheral Registers mapped into the Channel Codec address space starting at 8000h. All registers are normally accessed by the Layer 1 software provided with the AD20msp425 chipset. The user is not expected to read or write to any registers other than through the Layer 1 software. Therefore only a limited description of these registers is given here to ease the understanding of the functional behavior of the AD6426. Only registers which can be modified or monitored by the user under control of the Layer 1 software are shown. The Channel Codec Control Registers are listed in Table 1, and the H8 Peripheral Control Registers in Table 3

A description of the Channel Codec Control Register contents is shown in Table 2, and of the H8 Peripheral Registers in Table 4.

Table 1. CC Control Registers

Address Name

0 00 H SYSTEM R/W 2 02 H RADIO CONTROL R/W 4 04 H BSIC R/W 5 05 H TSC R/W 6 06 H TRAFFIC MODE R/W 7 07 H DAI R/W 8 08 H EEPROM R/W

9 09 H KEYPAD COLUMN R/W 10 0A H KEYPAD ROW RD 28 1C H EVBC SERIAL 1 RMW 29 1D H EVBC SERIAL 2 RMW 30 1E H EVBC IF CONTROL R/W 35 23 H RESET R/W 37 25 H SYNTH BIT COUNT R/W 38 26 H SYNTH CONTROL R/W 39 27 H ERROR COUNT RMW 40 28 H SYNTHESIZER 1 WR 41 29 H SYNTHESIZER 2 WR 42 2A H SYNTHESIZER 3 WR 43 2B H SYNTHESIZER 4 WR 44 2C H POWER CONTROL INT R/W 45 2D H POWER CONTROL EXTERNAL R/W 46 2E H SWRESET 1 R/W 47 2F H SWRESET 2 R/W 48 30 H INTERRUPT COUNTER R/W 49 31 H BBC TX ADDRESS R/W 50 32 H BACKLIGHT WR 51 33 H VERSION CONTROL RD

Address Name

72 48 H SYNTHESIZER PROGRAM R/W 73 49 H TXPA OFFSET 1 R/W 74 4A H TXPA OFFSET 2 R/W 75 4B H TXPA WIDTH 1 R/W 76 4C H TXPA WIDTH 2 R/W 77 4D H IRQ ENABLE R/W 78 4E H IRQ LATCH RMW 79 4F H CC GPIO R/W 88 58 H ccGPO R/W

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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AD6426

Table 2. CC Control Register Contents

# 7 6 5 4 3 2 1 0

0

Autocalibrate Backlight 1 Test Data Enable Calibrate Radio Encryption Type Encrypt Key Load

Tx Monitor

2

Enable

4 5

6 7 8

9 10 28 29 30 35

37

38 39

40 41 42 43

44

45

46

47 48

49 50 51 72 73 74 75 76 77 78 79 88 GPO19 Sel GPO18 Sel

TxPA

Polarity

Isolate

Synthesizer Synthesizer

Enable Polarity

GPO11 Data GPO11 Select IRQ5 Enable IRQ4 Enable IRQ3 Enable IRQ2 Enable FLASHPWD dis. NMI Edge Pol.

Tx Phase

Polarity

INT COUNT[8] OCE OVERRIDE Interrupt Counter

BAND ENABLE NMI Select GPO10 Data GPO10 Select Data Ser. Select DAIRESET

Config. Dynam.

Synthesizer Synthesizer

Enable Type

Coprocessor

Power Control

EVBC Read EVBC Tx Address

Rx Radio Control

Polarity

Synthesizer

Interface active

Synthesizer

Clock Polarity

Backlight Duty Cycle

Output Clock

Enable

Disable Synth.1 Disable Synth. 0 Synt. Enable Sel. Synt. Mode Pin Mode

IRQ5 active IRQ4 active IRQ3 active IRQ2 active

GPIO9 OP En GPIO8 OP En GPIO9 Data GPIO8 Data

Tx Radio Control

Polarity

Override

EEPROM Data

Output Enable

Tx Data Delay EVBC Rx-Buff. full EVBC Tx-Buf.empty

GP Power

Control

INT CNT RST Decode

GPO17 Sel

Tx PHASE

Enable

Base Station Identity Code

Autocalibration

Type

Keypad Row

EVBC Serial Port ( 15 : 8 )

EVBC Serial Port ( 7 : 0 )

EVBC Reset DSP Reset CC Reset

Error Count Synthesizer (31: 24) Synthesizer (23: 16)

Synthesizer (15: 8)

Synthesizer (7: 0)

Encryption

SW-Reset

Version

TD ( 7 : 0 )

TW ( 7 : 0 )

Monitor

Enable

Traffic Frame

Enable

EERPOM

Clock

Keypad Column

Synthesizer Bit Count

Synthesizer

Load Dynamic 1

Synth. Interface

Power Enable

DSP Power

Control

EVBC Interface

SW-Reset

Deinterleave

SW-Reset

Interrupt Counter

Modulate 1 Backlight LED Control

GPO19 GPO18 GPO17

Receive

Enable

Training Sequence Code

Decryption

Enable

EEPROM

Enable

Synthesizer

Load Dynamic 2

DSP Interface Power Enable

Radio Power

Control

DSP Interface

SW-Reset

interleave

SW-Reset

TD ( 9 : 8 )

TW ( 9 : 8 )

Encryption Power

Synthes. Interface

Transmit

Enable

Encryption

Enable

EERPOM

Data

Synthesizer

Clock

Enable

SW-Reset

Encode

SW-Reset

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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AD6426

Table 3. H8 Peripheral Control Registers

Address Name

0 8000h SMSMR R/W 1 8001h SMBRR R/W 2 8002h SMSCR R/W 3 8003h SMDR W 4 8004h SMSSR R/W 5 8005h SMDR R

6 8006h SMSCMR R/W 10 8010h BUFRBR R 10 8010h BUFTHR W 10 8010h BUFDLL R/W 11 8011h BUFIER R/W 11 8011h BUFDLM R/W 12 8012h BUFIIR R 12 8012h BUFFCR W 13 8013h BUFLCR R/W 14 8014h BUFMCR R/W 15 8015h BUFLSR R/W 16 8016h BUFMSR R/W 17 8017h BUFSCR R/W 18 8018h UIBRBR R 18 8018h UIBTHR W 19 8019H UIBSSR R/W 26 801AH UIBER R 27 801BH UIBTSR R 28 801CH UIBTLR R/W 29 801Dh UIBBLR R 32 8020h FIXRBR R 32 8020h FIXTHR W 32 8020h FIXDLL R/W 33 8021h FIXIER R/W 33 8021h FIXDLM R/W 34 8022h FIXIIR R 35 8023h FIXLCR R/W 36 8024h FIXMCR R/W 37 8025h FIXLSR R/W 38 8026h FIXMSR R/W 39 8027h FIXSCR R/W 48 8030h SCCR R/W 49 8031h SPSSR R/W 50 8032h SDIR1 (MS) R 51 8033h SDIR0 (LS) R 52 8034h SDOR1 (MS) W 53 8035h SDOR0 (LS) W

Address Name

64/65 8040/1h DISPDDR W

66 8042h DISPCR R/W 67 8043h DDOR W 68 8044h DDIR R 69 8045h DRR R/W 72 8048h WDTR W 80 8050h MEM IF R/W 81 8051h PERST R/W 82 8052h PERCR R/W 84 8054h TAR R/W 85 8055h PERCLK R/W 96 8060h RTCTR1 R/W 97 8061h RTCTR2 R/W 98 8062h RTCTR3 R/W

99 8063h RTCTR4 R/W 100 8064h RTCTR5 R/W 101 8065h RTCAR1 R/W 102 8066h RTCAR2 R/W 103 8067h RTCAR3 R/W 104 8068h RTCCR R/W 105 8069h RTCSRZ R/W 106 8074h SERDISPLAY/NMI R/W

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98) - 11 - Confidential Information

Preliminary Technical Information

AD6426

Table 4. H8 Peripheral Register Contents

# 7 6 5 4 3 2 1 0

0 ODD 1 BRR[3:0] 2 TIE RIE TE RE AE DATEN CLKPOL CLKEN 3 Transmit[7:0] 4 TDRE RDRF ORER ERS PER TEND 5 Receive[7:0]

6 10 RxData[7:0] 10 TxData[7:0] 10 BRR[7:0] 11 EDSSI ELSI ETBEI ERBFI 11 BRR[15:8] 12 FIFO ST FIFO ST InterruptID[2:0] Int Pend 12 RxLevel[1:0] DMA TX FIFO RX FIFO FIFO EN 13 DLAB SET BRK Stick Par. Ev. Parity Parity EN Stop Bits WLS[1:0] 14 Loop Out2 Out1 RTS DTR 15 Error Rx FIFO TEMT THRE Break Interrupt Framing Error Parity Error Overrun Error Data Ready 16 DCD RI DSR CTS DDCD TERI DDSR DCTS 17 SCR[7:0] 18 RxData[7:0] 18 TxData[7:0] 19 MRESET UIB Enable PROC 26 TE RE FE PE BI OE 27 MODEM TX Level RX Time RX Level 28 Tx Trigger Level [3:0] Rx Trigger Level [3:0] 29 Chars in TX Buffer [3:0] Chars in Rx Buffer [3:0] 32 RxData[7:0] 32 TxData[7:0] 32 BRR[7:0] 33 EDSSI ELSI ETBEI ERBFI 33 BRR[15:8] 34 FIFO ST FIFO ST InterruptID[2:0] Int Pend R 35 DLAB SET BRK Stick Par. Ev. Parity Parity EN Stop Bits WLS[1:0] R/W 36 Loop Out2 Out1 RTS DTR 37 Error Rx FIFO TEMT THRE Break Interrupt Framing Error Parity Error Overrun Error Data Ready 38 DCD RI DSR CTS DDCD TERI DDSR DCTS 39 SCR[7:0] 48 TEST RX MODE CLOCK TX ENABLE CROSSPOINT

SWITCH 49 SDORIE SDIROE IE SDIRIE SDOR EMT SDIR OE SDIR FULL 50 Receive[15:8] 51 Receive[7:0] 52 Transmit[15:8] 53 Transmit[7:0]

64/65 Data[7:0]

UCONN

SWITCH

R/W

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98) - 12 - Confidential Information

Preliminary Technical Information

AD6426

H8 Peripheral Register Contents (Continued)

# 7 6 5 4 3 2 1 0

66 SDISP POL DISP CLKEN CLK FREQ DDREMT 67 Transmit Data [7:0] 68 Receive Data [7:0] 69 Reset Data [7:0] 72 WDT[7:0] 80 TEST CLK Unused Unused UART SEL DALLAS EN RAM SEL7 DISP SRAM16 81 WDT INT RTC INT KEYINT DALLAS INT FA INT UA INT SSINT MONINT 82 WDT IE RTC IE KEY IE DALLAS IE FA IE UA IE SS IE MONIE 84 Test Key[7:0] 85 USCCLK EN BUCLK EN FUCLK EN DSPPLL[2:0] 96 TR[1] 97 TR[2] 98 TR[3]

99 TR[4] 100 TR[5] 101 AR[1] 102 AR[2] 103 AR[3] 104 105 106

INTEN

INT

TIMWEN ALAWEN PWRUEN AGCENN FBENN Unused Unused

TIMER ALARM APWRUP OSCFAIL 32K PRESENT TESTOUT

TXENABLE

NMI

SERDISP MODE

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98) - 13 - Confidential Information

Preliminary Technical Information

AD6426

GENERAL CONTROL Clocks

Clock Input

The AD6426 requires a single 13 MHz, low level clock signal, which has to be provided at the pin CLKIN. For proper operation a signal level of 250 mVPP minimum is required. This feature eases system design and reduces the need for external clock buffering. Only minimal external components are required as shown in Figure 4.

The internal clock buffer can accept any regular waveform as long as it can find voltage points in the signal, for which a 50% duty cycle can be determined. This condition is met for sinewaves, triangles, or slew-limited square waves. Dedicated circuitry searches for these points and generates the respective bias voltage internally.

The external capacitor (1nF) decouples the bias voltage of the clock signal generated by the oscillator from the internally generated bias voltage of the clock buffer circuitry.

The LC-filter shown is optional. It ensures, that the input signal is “well behaved” and sinusoidal. Additionally it filters out harmonics and noise, that may be on top of the pure 13 MHz signal.

Optional

13 MHz Filter

13 MHz

VCTCXO

OUT

2.2 µH

68 pF

1nF

CLKIN

AD6422

Figure 4. Clock Input Circuitry

Clock Output

The input clock drives both the H8 and the Channel Codec directly. A gated version, controlled by the Output Clock Enable flag in CC Control Register 45, drives the CLKOUT pin of the EVBC interface. The stand-by state of CLKOUT is logic zero. The CLKOUT output will be active on reset.

Slow Clocking

To reduce power consumption of AD20msp425 solutions, a new slow clocking scheme has been designed into the AD6426. This scheme allows the VCTCXO to be powered down between paging blocks during Idle Mode and for a

32.768kHz oscillator to keep the time reference during this period. Only a common 32.768kHz watch crystal is required to take advantage of this scheme. As in previous generations, power consumption is also kept to a minimum using asynchronous design techniques and by stopping all unnecessary clocks.

Layer 1 software and logic built into the AD6426 are responsible for maintaining synchronization and calibration of the slow clock and ensure the validity of the time reference

under all circumstances. The active-high OSC13MON output is prevented from becoming inactive if the 32.768kHz signal is not present. The following table describes the functionality of the relevant pins.

Name I/O Function

OSCIN I 32.768kHz Crystal Input OSCOUT O 32.768kHz Oscillator

Output

OSC13MON O 13 MHz Oscillator Power

Control

PWRON O Power ON/OFF Control

The following table lists the recommended specification for a 32kHz crystal.

Parameter Min Typ Max Units

ESR 50

kΩ

Shunt Capacitance 2 pF Load Capacitance 6 12.5 30 pF Turnover

25 °C

Temperature (To) Parabolic Curvature

0.040 ppm/°C

Constant (K)

Real Time Clock and Alarm

The AD6426 provides a simple Real Time Clock (RTC) using the 32.768kHz clock input. A 40 bit counter allows for more than one year of resolution. The RTC module contains a

32.768kHz on chip oscillator buffer designed for very low power consumption and a set of registers for a timer, alarm, control and status functions.

The RTC circuit is supplied by two sources; a VDDRTC supply pin and the main system VDD. It is the handset designer’s responsibility to provide suitable switching between the main system VDD and a backup supply to ensure the RTC module is permanently powered.

The VDDRTC pin is intended to interface to a backup battery circuit or charge holding network in order for the RTC to maintain timing accuracy when the main battery is removed and the handset is powered down.

The user can set an alarm time at which the handset powers up. If an alarm time is set, the current time matches the alarm time, and the power on alarm feature is enabled, the handset is powered up by asserting the PWRON pin for a period of approximately 2 seconds.

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98) - 14 - Confidential Information

Preliminary Technical Information

AD6426

The VDDRTC was designed to interface with either a:

• Lithium Battery or

• Capacitor in the range of 0.4F (maximum for ~24 hours

standby) to 8mF (~30 minutes standby)

Reset

The AD6426 is reset by setting the RESET pin to GND. This will reset the H8-processor, the Channel Codec, the internal DSP as well as the LCD controller interface and Boot ROM logic. Both the DSP and the Channel Codec will be held in reset until the RESET register is written to by the H8. At least 50 CLKIN cycles must elapse before deasserting the RESET pin and at least a further 100 cycles before writing to the RESET register.

For reset at power up, the DSP must be held in reset for at least 2000 clock cycles to enable the internal PLL to lock.

The RESET CC Control Register 35 contains the following flags:

Bit Function

3

EVBC Reset

2

DSP Reset

0

Channel Codec Reset

The H8 fetches its program start vector from location 0x0000 in segment zero. This can either be from external ROM or internal Boot ROM, depending on the status of the BOOTCODE pin.

Interrupts

The interrupts are controlled by the two CC Control Registers 77 and 78. These registers only apply to Emulation Mode, in that they define which of the interrupts are able to assert CCIRQ2.

Bit IRQ ENABLE CC Control Register 77

5

IRQ 5 Enable

4

IRQ 4 Enable

3

IRQ 3 Enable

2

IRQ 2 Enable

Bit IRQ LATCH CC Control Register 78

5

IRQ 5 active

4

IRQ 4 active

3

IRQ 3 active

2

IRQ 2 active

Additionally 8 functional modules can be reset under control of the two SWRESET registers:

Bit SWRESET 1 CC Control Register 46

3

Encryption Software Reset

2

EVBC Interface Software Reset

1

DSP Interface Software Reset

0

Synthesizer Interface Software Reset

Bit SWRESET 2 CC Control Register 47

3

Decode Software Reset

2

Deinterleave Software Reset

1

Interleave Software Reset

0

Encode Software Reset

The JTAG circuitry is reset by a power-on reset mechanism. Further resets must be done by asserting the TMS input high for at least five TCK clock cycles. When JTAG compliance is re-enabled, the JTAG is reset forcing the AD6426 into its normal mode of operation, selecting the BYPASS register by default.

NMI

The non-maskable interrupt NMI input of the H8 processor is multiplexed with the IRQ6 pin. IRQ6 is the default function, though asserting the NMI Select flag in CC Control Register 7 will select the NMI function. When not selected, NMI will be tied off high internally, though it remains driven by the JTAG port for test purposes. The signal is programmable to be edge or level sensitive. It defaults to falling edge. The edge polarity can be changed by programming the H8. However, if FLASHPWD is used then the same setting must be applied to CC Control Register 77. The default of zero implies falling edge sensitive. This way NMI going active can correctly deassert FLASHPWD. The NMI can be used for test purposes or user defined features. NMI is capable of bringing the control processor out of software standby mode and therefore suitable for functions such as alarm inputs, power management etc. During manufacture the NMI can be used to trigger special test code.

In addition NMI can be generated internally thus freeing up the IRQ6 PIN. In this mode the TXENABLE NMI will occur on the rising edge of the TXENABLE as seen at the pin. The H8 should be set up for a negative edge NMI in this case. Setting bit 5 in the SERDISPLAY/NMI H8 Peripheral Control Register 106 to a ONE enables the TXENABLE NMI. However, the Layer 1 Software must program the external INT pin to INT6 before the register bit is set.

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98) - 15 - Confidential Information

Analog Devices AD6426XST, AD6426XB Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

ORDERING GUIDE

Figure 1. Functional Block Diagram

Figure 2. External Interfaces of the AD6426

Table of Contents

PIN FUNCTIONALITY ( Normal Mode)

OVERVIEW

FUNCTIONAL PARTITIONING

Channel Codec Sub-System

Figure 3. Channel Codec Subsystem

Processor Sub-System

DSP Sub-System

Speech Transcoding

Equalization

Audio Control

Tone Generation

Automatic Frequency Control (AFC)

Automatic Gain Control (AGC)

REGISTERS

Table 1. CC Control Registers

Table 2. CC Control Register Contents

Table 3. H8 Peripheral Control Registers

Table 4. H8 Peripheral Register Contents

Clock Input

Clock Output

Slow Clocking

Real Time Clock and Alarm

Reset

Interrupts