Analog Devices AD640 Datasheet

DC-Coupled Demodulating
a
FEATURES Complete, Fully Calibrated Monolithic System Five Stages, Each Having 10 dB Gain, 350 MHz BW Direct Coupled Fully Differential Signal Path Logarithmic Slope, Intercept and AC Response are
Stable Over Full Military Temperature Range Dual Polarity Current Outputs Scaled 1 mA/Decade Voltage Slope Options (1 V/Decade, 100 mV/dB, etc.) Low Power Operation (Typically 220 mW at 5 V) Low Cost Plastic Packages Also Available
APPLICATIONS Radar, Sonar, Ultrasonic and Audio Systems Precision Instrumentation from DC to 120 MHz Power Measurement with Absolute Calibration Wide Range High Accuracy Signal Compression Alternative to Discrete and Hybrid IF Strips Replaces Several Discrete Log Amp ICs
PRODUCT DESCRIPTION
The AD640 is a complete monolithic logarithmic amplifier. A single AD640 provides up to 50 dB of dynamic range for frequencies from dc to 120 MHz. Two AD640s in cascade can provide up to 95 dB of dynamic range at reduced bandwidth. The AD640 uses a successive detection scheme to provide an output current propor­tional to the logarithm of the input voltage. It is laser calibrated to close tolerances and maintains high accuracy over the full military
temperature range using supply voltages from ±4.5 V to ±7.5 V.
The AD640 comprises five cascaded dc-coupled amplifier/limiter stages, each having a small signal voltage gain of 10 dB and a –3 dB bandwidth of 350 MHz. Each stage has an associated full-wave detector, whose output current depends on the absolute value of its input voltage. The five outputs are summed to provide the video
output (when low-pass filtered) scaled at 1 mA per decade (50 µA
per dB). On chip resistors can be used to convert this output cur­rent to a voltage with several convenient slope options. A balanced
FUNCTIONAL BLOCK DIAGRAM
RG1 RG0
1kV
18
17 16 14
1kV
RG2
15
LOG OUT
120 MHz Logarithmic Amplifier
AD640*
signal output at +50 dB (referred to input) is provided to operate AD640s in cascade.
The logarithmic response is absolutely calibrated to within ±1 dB for dc or square wave inputs from ±0.75 mV to ±200 mV, with
an intercept (logarithmic offset) at 1 mV dc. An integral X10
attenuator provides an alternative input range of ±7.5 mV to ±2 V dc. Scaling is also guaranteed for sinusoidal inputs.
The AD640B is specified for the industrial temperature range of
–40°C to +85°C and the AD640T, available processed to MIL­STD-883B, for the military range of –55°C to +125°C. Both are
available in 20-lead side-brazed ceramic DIPs or leadless chip carriers (LCC). The AD640J is specified for the commercial
temperature range of 0°C to +70°C, and is available in both
20-lead plastic DIP (N) and PLCC (P) packages.
This device is now available to Standard Military Drawing (DESC) number 5962-9095501MRA and 5962-9095501M2A.
PRODUCT HIGHLIGHTS
1. Absolute calibration of a wideband logarithmic amplifier is unique. The AD640 is a high accuracy measurement device, not simply a logarithmic building block.
2. Advanced design results in unprecedented stability over the full military temperature range.
3. The fully differential signal path greatly reduces the risk of instability due to inadequate power supply decoupling and shared ground connections, a serious problem with com­monly used unbalanced designs.
4. Differential interfaces also ensure that the appropriate ground connection can be chosen for each signal port. They further increase versatility and simplify applications. The signal input
impedance is ~500 k in shunt with ~2 pF.
5. The dc-coupled signal path eliminates the need for numerous interstage coupling capacitors and simplifies logarithmic conversion of subsonic signals.
(continued on page 4)
LOG COM
13
INTERCEPT POSITIONING BIAS
12
+V
S
FULL-WAVE
DETECTOR
AMPLIFIER/LIMITER
270V
5
ATN IN
SIG +IN SIG –IN
19
20
1 2
27V
3
30V
4
ATN OUT
ATN LO
ATN COM ATN COM
*Protected under U.S. patent number 4,990,803.
6
BL1
FULL-WAVE
DETECTOR
10dB10dB
AMPLIFIER/LIMITER
GAIN BIAS REGULATOR
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
–V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999
FULL-WAVE
DETECTOR
10dB 10dB
AMPLIFIER/LIMITER
7
S
SLOPE BIAS REGULATOR
FULL-WAVE
DETECTOR
AMPLIFIER/LIMITER
11 10
9 8
SIG +OUT SIG –OUT
BL2 ITC
AD640–SPECIFICATIONS
DC SPECIFICATIONS
(VS = ⴞ5 V, TA = +25ⴗC, unless otherwise noted)
Model AD640J AD640B AD640T Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Units
TRANSFER FUNCTION
1
I
= IY LOG |VIN/VX| for V
OUT
= ±0.75 mV to ±200 mV dc
IN
SIGNAL INPUTS (Pins 1, 20)
Input Resistance Differential 500 500 500 k Input Offset Voltage Differential 50 500 50 200 50 200 µV
vs. Temperature 0.8 0.8 0.8 µV/°C Over Temperature T
MIN
to T
MAX
300 µV
vs. Supply 2 2 2 µV/V Input Bias Current 7 25 7 25 7 25 µA Input Bias Offset 1 1 1 µA Common-Mode Range –2 +0.3 –2 +0.3 –2 +0.3 V
INPUT ATTENUATOR
(Pins 2, 3, 4, 5 and 19)
Attenuation
2
Pin 5 to Pin 19 20 20 20 dB
Input Resistance Pins 5 to 3/4 300 300 300
SIGNAL OUTPUT (Pins 10, 11)
Small Signal Gain Peak Differential Output
3
4
50 50 50 dB ±180 ±180 ± 180 mV
Output Resistance Either Pin to COM 75 75 75 Quiescent Output Voltage Either Pin to COM –90 –90 –90 mV
5
LOGARITHMIC OUTPUT
Voltage Compliance Range –0.3 +V Slope Current, I
Y
(Pin 14)
–1 –0.3 +VS –1 –0.3 VS –1 V
S
0.95 1.00 1.05 0.98 1.00 1.02 0.98 1.00 1.02 mA
Accuracy vs. Temperature 0.002 0.002 0.002 %/°C
Accuracy vs. Supply +V Intercept Voltage
6
, V
X
to T
T
MIN
MAX
= 4.5 V to 7.5 V 0.08 1.0 0.08 0.4 0.08 0.4 %/V
S
0.85 1.00 1.15 0.95 1.00 1.05 0.95 1.00 1.05 mV
0.98 1.02 mA
vs. Temperature 0.5 0.5 0.5 µV/°C
Over Temperature T
vs. Supply ±V
to T
MIN
MAX
= 4.5 V to 7.5 V 2 2 2 µV/V
S
0.90 1.10 mV
Logarithmic Offset
(Alt. Definition of V
) –61.5 –60.0 –58.7 –60.5 –60.0 –59.5 –60.5 –60.0 –59.5 dBV
X
vs. Temperature 0.004 0.004 0.004 dB/°C Over Temperature T vs. Supply ±V
Intercept Voltage Using Attenuator 8.25 10.0 11.75 9.0 10.0 11.0 9.0 10.0 11.0 mV Zero Signal Output Current
7
to T
MIN
MAX
= 4.5 V to 7.5 V 0.017 0.017 0.017 dB/V
S
–0.2 –0.2 –0.2 mA
–60.9 –59.1 dB
ITC Disabled Pin 8 to COM –0.27 –0.27 –0.27 mA Maximum Output Current 2.3 2.3 2.3 mA
APPLICATIONS RESISTORS
(Pins 15, 16, 17) 1.000 0.995 1.000 1.005 0.995 1.000 1.005 k
DC LINEARITY
V
±1 mV to ±100 mV 0.35 1.2 0.35 0.6 0.35 0.6 dB
IN
TOTAL ABSOLUTE DC ACCURACY
= ±1 mV to ±100 mV
V
IN
Over Temperature T
Over Supply Range ±V
= ±0.75 mV to ±200 mV 1.0 3 1.0 2.0 1.0 2.0 dB
V
IN
8
to T
MIN
MAX
= 4.5 V to 7.5 V 2 1.0 1.0 dB
S
0.55 2 0.55 0.9 0.55 0.9 dB 3 1.7 1.8 dB
Using Attenuator
= ±10 mV to ±1 V 0.4 2.5 0.4 1.5 0.4 1.5 dB
V
IN
Over Temperature T
V
= ±7.5 mV to 2 V 1.2 3.5 1.2 2.5 1.2 2.5 dB
IN
MIN
to T
MAX
0.6 3 0.6 2.0 0.6 2.0 dB
POWER REQUIREMENTS
Voltage Supply Range Quiescent Current
9
+VS (Pin 12) T –VS (Pin 7) T
MIN
MIN
to T to T
4.5
MAX
MAX
7.5ⴞ4.5
7.5
4.5
7.5 V
915 9 15 9 15 mA 35 60 35 60 35 60 mA
–2–
REV. C
AD640
AC SPECIFICATIONS
(VS = 5 V, TA = +25C, unless otherwise noted)
Model AD640J AD640B AD640T Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Units
SIGNAL INPUTS (Pins 1, 20)
Input Capacitance Either Pin to COM 2 2 2 pF Noise Spectral Density 1 kHz to 10 MHz 2 2 2 nV/Hz Tangential Sensitivity BW = 100 MHz –72 –72 –72 dBm
3 dB BANDWIDTH
Each Stage 350 350 350 MHz All Five Stages Pins 1 & 20 to 10 & 11 145 145 145 MHz
LOGARITHMIC OUTPUTS
Slope Current, I
Y
5
f< = 1 MHz 0.96 1.0 1.04 0.98 1.0 1.02 0.98 1.0 1.02 mA f = 30 MHz 0.88 0.94 1.00 0.91 0.94 0.97 0.91 0.94 0.97 mA f = 60 MHz 0.82 0.90 0.98 0.86 0.90 0.94 0.86 0.90 0.94 mA f = 90 MHz 0.88 0.88 0.88 mA f = 120 MHz 0.85 0.85 0.85 mA
Intercept, Dual AD640s
10, 11
f< = 1 MHz –90.6 –88.6 –86.6 –89.6 –88.6 –87.6 –89.6 –88.6 –87.6 dBm f = 30 MHz –87.6 –87.6 –87.6 dBm f = 60 MHz –86.3 –86.3 –86.3 dBm f = 90 MHz –83.9 –83.9 –83.9 dBm f = 120 MHz –80.3 –80.3 –80.3 dBm
AC LINEARITY
–40 dBm to –2 dBm –35 dBm to –10 dBm –75 dBm to 0 dBm –70 dBm to –10 dBm –75 dBm to +15 dBm
12
12
10
10
13
f = 1 MHz 0.5 2.0 0.5 1.0 0.5 1.0 dB f = 1 MHz 0.25 1.0 0.25 0.5 0.25 0.5 dB f = 1 MHz 0.75 3.0 0.75 1.5 0.75 1.5 dB f = 1 MHz 0.5 2.0 0.5 1.0 0.5 1.0 dB f = 10 kHz 0.5 3.0 0.5 1.5 0.5 1.5 dB
PACKAGE OPTION
20-Lead Ceramic DIP Package (D) AD640BD AD640TD 20-Terminal Ceramic LCC (E) AD640BE AD640TE 20-Lead Plastic DIP Package (N) AD640]N 20-Lead Plastic Leaded Chip Carrier (P) AD640JP AD640BP
NUMBER OF TRANSISTORS 155 155 155
NOTES
1
Logarithms to base 10 are used throughout. The response is independent of the sign of VIN.
2
Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.30%/ °C.
3
Overall gain is trimmed using a ±200 µV square wave at 2 kHz, corrected for the onset of compression.
4
The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.
5
Currents defined as flowing into Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured by linear regression over central region of transfer function.
6
The logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG10 (VX/1 V).
7
The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.
8
Operating in circuit of Figure 24 using ± 0.1% accurate values for R VIN >3 mV dc, and over the full input range in ac applications.
9
Essentially independent of supply voltages.
10
Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm in 50 = 223 mV rms.
11
For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept
for dual AD640 system.
12
Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50 = 223 mV rms.
13
Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input.
and R
LA
Includes slope and nonlinearity errors. Input offset errors also included for
LB.
All min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculate outgoing quality levels.
Specifications subject to change without notice.
REV. C
THERMAL CHARACTERISTICS
␪JC (ⴗC/W) JA (ⴗC/W)
20-Lead Ceramic DIP Package (D-20) 25 85 20-Terminal Ceramic LCC (E-20A) 25 85 20-Lead Plastic DIP Package (N-20) 24 61 20-Lead Plastic Leaded Chip Carrier (P-20A) 28 75
–3–
AD640
WARNING!
ESD SENSITIVE DEVICE
(continued from page 1)
6. The low input offset voltage of 50 µV (200 µV max) ensures
good accuracy for low level dc inputs.
7. Thermal recovery “tails,” which can obscure the response when a small signal immediately follows a high level input, have been minimized by special attention to design details.
8. The noise spectral density of 2 nV/Hz results in a noise floor of ~23 µV rms (–80 dBm) at a bandwidth of 100 MHz. The dy-
namic range using cascaded AD640s can be extended to 95 dB by the inclusion of a simple filter between the two devices.
CHIP DIMENSIONS AND
BONDING DIAGRAM
Dimensions shown in inches and (mm).
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7.5 V
Input Voltage (Pin 1 or Pin 20 to COM) . . . . –3 V to +300 mV
Attenuator Input Voltage (Pin 5 to Pin 3/4) . . . . . . . . . . . ±4 V
Storage Temperature Range D, E . . . . . . . . . –65°C to +150°C
Storage Temperature Range N, P . . . . . . . . . –65°C to +125°C
Ambient Temperature Range, Rated Performance
Industrial, AD640B . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Military, AD640T . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Commercial, AD640J . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD640JN 0°C to +70°C 20-Lead Plastic DIP N-20 AD640JP 0°C to +70°C 20-Lead PLCC P-20A AD640BD –40°C to +85°C 20-Lead Ceramic DIP D-20 AD640BE –40°C to +85°C 20-Terminal Ceramic
LCC E-20A
AD640BP –40°C to +85°C 20-Lead PLCC P-20A AD640TD/883B –55°C to +125°C 20-Lead Ceramic DIP D-20 5962-9095501MRA –55°C to +125°C 20-Lead Ceramic DIP D-20 AD640TE/883B –55°C to +125°C 20-Terminal Ceramic
LCC E-20A
5962-9095501M2A –55°C to +125°C 20-Terminal Ceramic
LCC E-20A
AD640TCHIPS –55°C to +125°CDie
AD640EB Evaluation Board
AD640JP-REEL 0°C to +70°C 13" Tape and Reel P-20A AD640JP-REEL7 0°C to +70°C 7" Tape and Reel P-20A
CONNECTION DIAGRAMS
20-Lead Ceramic DIP (D) Package 20-Lead PLCC (P) Package 20-Terminal Ceramic LCC (E) Package
20-Lead Plastic DIP (N) Package
SIG –IN
ATN LO ATN COM ATN COM
ATN IN
BL1
–V
ITC
BL2
SIG –OUT
1
2
3
4
5
6
7
S
8
9
10
AD640
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
SIG +IN ATN OUT CKT COM RG1 RG0 RG2 LOG OUT LOG COM +V
S
SIG +OUT
ATN COM
ATN IN
BL1 –V
ITC
4 5 6 7
S
8
ATN COM
ATN LO
SIG –IN
3 2 1 20 19
SIG +IN
PIN 1 IDENTIFIER
AD640
TOP VIEW
(Not to Scale)
9 10 11 12 13
BL2
SIG –OUT
SIG +OUT
S
+V
ATN OUT
18
CKT COM
17
RG1
16
RG0
15
RG2
14
LOG OUT
LOG COM
ATN COM
ATN IN
BL1 –V
ITC
4 5 6 7
S
8
ATN COM
ATN LO
SIG –IN
SIG +IN
2
20 191
3
AD640
TOP VIEW
(Not to Scale)
910111213
BL2
SIG –OUT
S
+V
SIG +OUT
ATN OUT
18 17 16 15 14
LOG COM
CKT COM RG1 RG0 RG2 LOG OUT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD640 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. C–4–
Typical DC Performance Characteristics–AD640
4.5 5.0 5.5 6.0 6.5 7.0 7.5 POWER SUPPLY VOLTAGES – 6 Volts
SLOPE CURRENT – mA
1.006
1.004
1.002
1.000
0.998
0.996
0.994 –60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
DEVIATION OF INPUT OFFSET VOLTAGE – mV
0
–0.1
+0.4
+0.3
+0.2
+0.1
–0.2
–0.3
INPUT OFFSET VOLTAGE DEVIATION WILL BE WITHIN SHADED AREA.
2.5
2.0
1.5
1.0
0.5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
0
ABSOLUTE ERROR – dB
1.015
1.010
1.005
1
0.995
0.990
SLOPE CURRENT – mA
0.985
0.980 –60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
Figure 1. Slope Current, IY vs. Temperature
1.015
1.010
1.005
1.000
0.995
INTERCEPT VOLTAGE – mV
0.990
0.985
4.5 5.0 5.5 6.0 6.5 7.0 7.5 POWER SUPPLY VOLTAGES – 6 Volts
1.20
1.15
1.10
1.05
1.00
INTERCEPT – mV
0.95
0.90
0.85 –60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
Figure 2. Intercept Voltage, VX, vs. Temperature
14
13
12
11
10
INTERCEPT – mV
9
8
7 –60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
Figure 3. Slope Current, IY vs. Supply Voltages
Figure 4. Intercept Voltage, VX, vs. Supply Voltages
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
OUTPUT CURRENT – mA
0 –0.2 –0.4
0.1 1.0 1000.010.0 100.0 INPUT VOLTAGE – mV
(EITHER SIGN)
Figure 7. DC Logarithmic Transfer Function and Error Curve for Single AD640
REV. C –5–
2 1 0
ERROR – dB
Figure 5. Intercept Voltage (Using Attenuator) vs. Temperature
2.5
2.0
1.5
1.0
ABSOLUTE ERROR – dB
0.5
0 –60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
Figure 8. Absolute Error vs. Tem­perature, V
= ⴞ1 mV to ⴞ100 mV
IN
Figure 6. Input Offset Voltage Deviation vs. Temperature
Figure 9. Absolute Error vs. Temperature, Using Attenuator. V
= ⴞ10 mV to ⴞ1 V, Pin 8
IN
Grounded to Disable ITC Bias
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