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AD5533 a
Datasheet
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Analog Devices AD5533 a Datasheet

32-Channel Infinite
a
FEATURES Infinite Sample-and-Hold Capability to ⴞ0.018% Accuracy High Integration:
32-Channel DAC in 12 mm ⴛ 12 mm CSPBGA Per Channel Acquisition Time of 16 ␮s Max Adjustable Voltage Output Range Output Impedance 0.5 ⍀ Output Voltage Span 10 V Readback Capability DSP/Microcontroller Compatible Serial Interface Parallel Interface Temperature Range –40ⴗC to +85ⴗC
APPLICATIONS Optical Networks Automatic Test Equipment Level Setting Instrumentation Industrial Control Systems Data Acquisition Low Cost I/O
Sample-and-Hold
OUT
*
for this
AD5533

GENERAL DESCRIPTION

The AD5533 combines a 32-channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, V sentation transferred to a chosen DAC Register. V DAC is then updated to reflect the new contents of the DAC register. Channel selection is accomplished via the parallel address inputs A0–A4 or via the serial input port. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from V
+ 2 V to VDD – 2 V because of the headroom of the
SS
output amplifier.
The device is operated with AV +5.25 V, V
= –4.75 V to –16.5 V, and VDD = +8 V to +16.5 V
SS
and requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. Infinite Droopless Sample-and-Hold Capability.
2. The AD5533 is available in a 74-lead CSPBGA with a body size of 12 mm ⫻ 12 mm.
, is sampled and its digital repre-
IN
= +5 V ± 5%, DVCC = +2.7 V to
CC

FUNCTIONAL BLOCK DIAGRAM

DV
AV
CC
V
IN
TRACK /RESET
BUSY
GND
DAC
AGND
DGND
SER / PAR
*Protected by U.S. Patent No. 5,969,657; other patents pending.
AD5533
ADC
INTERFACE
CONTROL
LOGIC
DIND
CC
OUT
REF IN REF OUT
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
IN
CAL
VDDV
OFFSET SEL
SS
V
0
OUT
V
31
OUT
OFFS
OUT
WR
OFFS
DAC
DAC
DAC
ADDRESS INPUT REGISTER
SYNC/ CS
A4– A0SCLK
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = 2.7 V
AD5533
V
+ 2 V to VDD – 2 V. All outputs unloaded. All specifications T
SS
Parameter
–SPECIFICATIONS
1
ANALOG CHANNEL
to V
V
IN
Nonlinearity ±0.018 % max Input Range 100 mV to 2.96 V.
OUT
Gain 3.46/3.6 min/max 3.52 typ. Offset Error ±50 mV max
ANALOG INPUT (V
)
IN
Input Voltage Range 0–3 V Nominal Input Range. Input Lower Dead Band 70 mV max 50 mV typ. Referred to V
Input Upper Dead Band 40 mV max 12 mV typ. Referred to V
Input Current 1 µA max 100 nA typ. V
Input Capacitance
3
ANALOG INPUT (OFFS_IN)
Input Current 1 µA max 100 nA typ. Input Voltage Range 0/4 V min/max Output Range Restricted
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage 3.0 V Input Voltage Range
3
Input Current 1 µA max <1 nA typ.
REF_OUT
Output Voltage 3 V typ Output Impedance Reference Temperature Coefficient
ANALOG OUTPUTS (V
Output Temperature Coefficient
3
3
0–31)
OUT
3, 4
DC Output Impedance 0.5 Ω typ Output Range V Resistive Load Capacitive Load Short-Circuit Current DC Power Supply Rejection Ratio
DC Crosstalk
ANALOG OUTPUT (OFFS_OUT)
Output Temperature Coefficient DC Output Impedance
3, 5
3, 5
3
3
3
3, 4
3
Output Range 50 to REF_IN – 12 mV typ Output Current 10 µA max Source Current. Capacitive Load 100 pF max
DIGITAL INPUTS
3
Input Current ±10 µA max 5 µA typ. Input Low Voltage 0.8 V max DV
Input High Voltage 2.4 V min DV
Input Hysteresis (SCLK and CS Only) 200 mV typ Input Capacitance 10 pF max
DIGITAL OUTPUTS (BUSY, DOUT)
3
Output Low Voltage 0.4 V max DVCC = 5 V. Sinking 200 µA. Output High Voltage 4.0 V min DV Output Low Voltage 0.4 V max DV Output High Voltage 2.4 V min DV High Impedance Leakage Current ±1 µA max D High Impedance Output Capacitance 15 pF typ D
to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from
to T
MIN
A Version
2
±0.006 % typ After Gain and Offset Adjustment.
20 pF typ
2.85/3.15 V min/max
280 kΩ typ 60 ppm/°C typ
10 ppm/°C typ
+ 2 /VDD – 2 V min/max
SS
5kΩ min 500 pF max 7 mA typ –70 dB typ VDD = +15 V ± 5%. –70 dB typ V 250 µV max
10 ppm/°C typ
1.3 kΩ typ
0.4 V max DV
2.0 V min DV
, unless otherwise noted.)
MAX
Unit Conditions/Comments
See Figure 5.
See Figure 5.
Being Acquired on
IN
One Channel.
from VSS + 2 V to VDD – 2 V.
= –15 V ± 5%.
SS
= 5 V ± 5%.
CC
= 3 V ± 10%.
CC
= 5 V ± 5%.
CC
= 3 V ± 10%.
CC
= 5 V. Sourcing 200 µA.
CC
= 3 V. Sinking 200 µA.
CC
= 3 V. Sourcing 200 µA.
CC
Only.
OUT
Only.
OUT
.
IN
.
IN
–2–
REV. A
AD5533
Parameter
1
A Version
2
Unit Conditions/Comments
POWER REQUIREMENTS
Power Supply Voltages
V
DD
V
SS
AV
CC
DV
CC
Power Supply Currents
I
DD
I
SS
AI
CC
DI
CC
Power Dissipation
NOTES
1
See Terminology.
2
A Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3
Guaranteed by design and characterization, not production tested.
4
AD780 as reference for the AD5533.
5
Ensure that you do not exceed TJ (max). See maximum ratings.
6
Outputs unloaded.
Specifications subject to change without notice.
6
6
8/16.5 V min/max –4.75/–16.5 V min/max
4.75/5.25 V min/max
2.7/5.25 V min/max
15 mA max 10 mA typ. All Channels Full-Scale. 15 mA max 10 mA typ. All Channels Full-Scale. 33 mA max 26 mA typ.
1.5 mA max 1 mA typ. 280 mW typ VDD = +10 V, VSS = –5 V.
(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =

AC CHARACTERISTICS

All specifications T
Parameter A Version
Output Settling Time Acquisition Time 16 µs max OFFS_IN Settling Time Digital Feedthrough Output Noise Spectral Density @ 1 kHz AC Crosstalk
NOTES
1
A Version: Industrial temperature range –40°C to +85°C; typical at 25°C.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
to T
MIN
2
, unless otherwise noted.)
MAX
2
2
2
DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from V
1
Unit Conditions/Comments
3 µs max
10 µs max 500 pF, 5 kΩ Load; 0 V–3 V Step
2
0.2 nV-s typ 400 nV/(√Hz) typ 5nV-s typ
+ 2 V to VDD – 2 V. All outputs unloaded.
SS
REV. A
–3–
AD5533

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Parameter
t
1
t
2
t
3
t
4
t
5
t
6
NOTES
1
See Interface Timing Diagram.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
1, 2
Limit at T (A Version) Unit Conditions/Comments
0 ns min CS to WR Setup Time 0 ns min CS to WR Hold Time 50 ns min CS Pulsewidth Low 50 ns min WR Pulsewidth Low 20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time 7 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time

SERIAL INTERFACE

Parameter
f
CLKIN
t
1
t
2
t
3
t
4
t
5
t
6
t
7
3
t
8
3
t
9
t
10
4
t
11
NOTES
1
See Serial Interface Timing Diagrams.
2
Guaranteed by design and characterization, not production tested.
3
These numbers are measured with the load circuit of Figure 2.
4
SYNC should be taken low while SCLK is low for read back.
Specifications subject to change without notice.
1, 2
Limit at T (A Version) Unit Conditions/Comments
20 MHz max SCLK Frequency 20 ns min SCLK High Pulsewidth 20 ns min SCLK Low Pulsewidth 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time 50 ns min SYNC Low Time 10 ns min DIN Setup Time 5 ns min DIN Hold Time 5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time for Read Back 20 ns max SCLK Rising Edge to D 60 ns max SCLK Falling Edge to D 400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Read Back 7 ns min SCLK Falling Edge to SYNC Falling Edge Setup Time for Read Back
MIN
MIN
, T
, T
MAX
MAX
Valid
OUT
High Impedance
OUT

PARALLEL INTERFACE TIMING DIAGRAM

t
2
5
t
6
CS
WR
A4–A0, CAL,
SEL
OFFS
t
1
t
3
t
4
t
Figure 1. Parallel Write (ISHA Mode Only)
OUTPUT
Figure 2. Load Circuit for D
–4–
TO
PIN
C
L
50pF
200␮A
200␮A
I
OL
1.6V
I
OH
Timing Specifications
OUT
REV. A

SERIAL INTERFACE TIMING DIAGRAMS

t
1
SCLK
SYNC
D
IN
12345678910
t
3
MSB LSB
t
2
t
4
Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)
AD5533
t
5
t
6
SCLK
SYNC
D
OUT
t
7
10
t
11
t
10
t
1
21 34567
t
2
t
4
t
8
MSB
8
9
10
11
12 13 14
t
9
LSB
Figure 4. 14-Bit Read (Both Readback Modes)
REV. A
–5–
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